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drm/i915: Implement .get_format_info() hook for CCS

SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. By providing our own format information for the CCS formats, we should be able to make framebuffer_check() do the right thing for the CCS surface as well. Note that we'll return the same format info for both Y and Yf tiled format as that's what happens with the non-CCS Y vs. Yf as well. If desired, we could potentially return a unique pointer for each pixel_format+tiling+ccs combination, in which case we immediately be able to tell if any of that stuff changed by just comparing the pointers. But that does sound a bit wasteful space wise. v2: Drop the 'dev' argument from the hook v3: Include the description of the CCS surface layout v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h description of CCS layout. (daniels)

Ville Syrjälä committed 9 years ago

Commit bbfb6ce1 parent 148b1e12 files · +56 −0Browse files

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include/uapi/drm/drm_fourcc.h+20−0
@@ -263,6 +263,26 @@ extern "C" { · 262 unmodified lines
263 */263 */
264#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)264#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
265 265
266/*
267 * Intel color control surface (CCS) for render compression
268 *
269 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
270 * The main surface will be plane index 0 and must be Y/Yf-tiled,
271 * the CCS will be plane index 1.
272 *
273 * Each CCS tile matches a 1024x512 pixel area of the main surface.
274 * To match certain aspects of the 3D hardware the CCS is
275 * considered to be made up of normal 128Bx32 Y tiles, Thus
276 * the CCS pitch must be specified in multiples of 128 bytes.
277 *
278 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
279 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
280 * But that fact is not relevant unless the memory is accessed
281 * directly.
282 */
283#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
284#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
285
266/*286/*
267 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks287 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
268 *288 *

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