History

Merge tag 'amd-drm-next-6.5-2023-06-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.5-2023-06-16: amdgpu: - Misc display fixes - W=1 fixes - Improve scheduler naming - DCN 3.1.4 fixes - kdoc fixes - Enable W=1 - VCN 4.0 fix - xgmi fixes - TOPDOWN fix for large BAR systems - eDP fix - PSR fixes - SubVP fixes - Freesync fix - DPIA fix - SMU 13.0.5 fixes - vblflash fix - RAS fixes - SDMA 4 fix - BO locking fix - BO backing store fix - NBIO 7.9 fixes - GC 9.4.3 fixes - GPU reset recovery fixes - HMM fix amdkfd: - Fix NULL check - Trap fixes - Queue count fix - Add event age tracking radeon: - fbdev client fix scheduler: - Avoid an infinite loop UAPI: - Add KFD event age tracking: Proposed ROCT-Thunk-Interface: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/efdbf6cfbc026bd68ac3c35d00dacf84370eb81e https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/1820ae0a2db85b6f584611dc0cde1a00e7c22915 Proposed ROCR-Runtime: https://github.com/RadeonOpenCompute/ROCR-Runtime/compare/master...zhums:ROCR-Runtime:new_event_wait_review https://github.com/RadeonOpenCompute/ROCR-Runtime/commit/e1f5bdb88eb882ac798aeca2c00ea3fbb2dba459 https://github.com/RadeonOpenCompute/ROCR-Runtime/commit/7d26afd14107b5c2a754c1a3f415d89f3aabb503 drm: - DP MST fix

Dave Airlie committed 3 years ago

Commit bcbede62 parents 4e237d8 72f1de493 files · +1222 −431Browse files

Unified · Split

93 files
  1. drivers/gpu/drm/amd/amdgpu/Makefile +12 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +1 −1
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +11 −3
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +1 −1
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +3 −0
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +25 −0
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +2 −0
  8. drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +2 −2
  9. drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +2 −1
  10. drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +14 −3
  11. drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +1 −1
  12. drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +0 −2
  13. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +6 −2
  14. drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +22 −1
  15. drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +2 −0
  16. drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +8 −8
  17. drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +2 −2
  18. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +23 −0
  19. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +1 −0
  20. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +9 −9
  21. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +4 −4
  22. drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +19 −15
  23. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +130 −46
  24. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +4 −0
  25. drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +46 −0
  26. drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c +0 −3
  27. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +6 −12
  28. drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +1 −1
  29. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +1 −0
  30. drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +1 −17
  31. drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +5 −4
  32. drivers/gpu/drm/amd/amdgpu/psp_v13_0.h +2 −0
  33. drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +2 −2
  34. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +12 −8
  35. drivers/gpu/drm/amd/amdgpu/ta_ras_if.h +1 −0
  36. drivers/gpu/drm/amd/amdgpu/umc_v8_10.h +2 −1
  37. drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +5 −1
  38. drivers/gpu/drm/amd/amdkfd/kfd_crat.c +0 −5
  39. drivers/gpu/drm/amd/amdkfd/kfd_debug.c +1 −1
  40. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +3 −3
  41. drivers/gpu/drm/amd/amdkfd/kfd_events.c +34 −12
  42. drivers/gpu/drm/amd/amdkfd/kfd_events.h +1 −0
  43. drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +1 −1
  44. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +41 −24
  45. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +32 −0
  46. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +3 −3
  47. drivers/gpu/drm/amd/display/dc/core/dc.c +16 −20
  48. drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +70 −0
  49. drivers/gpu/drm/amd/display/dc/dc.h +6 −3
  50. drivers/gpu/drm/amd/display/dc/dc_dp_types.h +1 −1
  51. drivers/gpu/drm/amd/display/dc/dc_types.h +1 −0
  52. drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +2 −0
  53. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +12 −8
  54. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +36 −21
  55. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +0 −11
  56. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +3 −0
  57. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +1 −0
  58. drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +1 −0
  59. drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c +1 −0
  60. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +8 −0
  61. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c +5 −0
  62. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c +2 −7
  63. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h +1 −1
  64. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +25 −2
  65. drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c +1 −0
  66. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +4 −7
  67. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h +1 −1
  68. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c +5 −2
  69. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +2 −1
  70. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h +4 −0
  71. drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +104 −43
  72. drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +2 −1
  73. drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +59 −0
  74. drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +110 −68
  75. drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +8 −0
  76. drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +1 −0
  77. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +32 −0
  78. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +1 −1
  79. drivers/gpu/drm/amd/display/dc/link/link_detection.c +5 −0
  80. drivers/gpu/drm/amd/display/modules/freesync/freesync.c +9 −2
  81. drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +14 −4
  82. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +1 −2
  83. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +76 −4
  84. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h +1 −1
  85. drivers/gpu/drm/display/drm_dp_mst_topology.c +47 −7
  86. drivers/gpu/drm/i915/display/intel_dp.c +4 −3
  87. drivers/gpu/drm/nouveau/dispnv50/disp.c +8 −4
  88. drivers/gpu/drm/radeon/radeon_acpi.h +9 −0
  89. drivers/gpu/drm/radeon/radeon_atpx_handler.c +1 −1
  90. drivers/gpu/drm/radeon/radeon_fbdev.c +1 −0
  91. drivers/gpu/drm/scheduler/sched_entity.c +1 −1
  92. include/drm/display/drm_dp_mst_helper.h +5 −2
  93. include/uapi/linux/kfd_ioctl.h +11 −2
drivers/gpu/drm/amd/amdgpu/Makefile+12−1
@@ -40,7 +40,18 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ · 39 unmodified lines
4040 -I$(FULL_AMD_PATH)/amdkfd
4141
4242 subdir-ccflags-y := -Wextra
43−subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
43+subdir-ccflags-y += -Wunused
44+subdir-ccflags-y += -Wmissing-prototypes
45+subdir-ccflags-y += -Wmissing-declarations
46+subdir-ccflags-y += -Wmissing-include-dirs
47+subdir-ccflags-y += -Wold-style-definition
48+subdir-ccflags-y += -Wmissing-format-attribute
49+# Need this to avoid recursive variable evaluation issues
50+cond-flags := $(call cc-option, -Wunused-but-set-variable) \
51+ $(call cc-option, -Wunused-const-variable) \
52+ $(call cc-option, -Wstringop-truncation) \
53+ $(call cc-option, -Wpacked-not-aligned)
54+subdir-ccflags-y += $(cond-flags)
4455 subdir-ccflags-y += -Wno-unused-parameter
4556 subdir-ccflags-y += -Wno-type-limits
4657 subdir-ccflags-y += -Wno-sign-compare
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+1−1
@@ -309,7 +309,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, · 308 unmodified lines
309309 }
310310 p->gang_leader = p->jobs[p->gang_leader_idx];
311311
312− if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
312+ if (p->ctx->generation != p->gang_leader->generation) {
313313 ret = -ECANCELED;
314314 goto free_all_kdata;
315315 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+11−3
@@ -333,7 +333,7 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, · 332 unmodified lines
333333
334334 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter);
335335 ctx->reset_counter_query = ctx->reset_counter;
336− ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter);
336+ ctx->generation = amdgpu_vm_generation(mgr->adev, &fpriv->vm);
337337 ctx->init_priority = priority;
338338 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET;
339339
@@ -432,6 +432,7 @@ int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, · 92 unmodified lines
432432 u32 ring, struct drm_sched_entity **entity)
433433 {
434434 int r;
435+ struct drm_sched_entity *ctx_entity;
435436
436437 if (hw_ip >= AMDGPU_HW_IP_NUM) {
437438 DRM_ERROR("unknown HW IP type: %d\n", hw_ip);
@@ -455,7 +456,14 @@ int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, · 17 unmodified lines
455456 return r;
456457 }
457458
458− *entity = &ctx->entities[hw_ip][ring]->entity;
459+ ctx_entity = &ctx->entities[hw_ip][ring]->entity;
460+ r = drm_sched_entity_error(ctx_entity);
461+ if (r) {
462+ DRM_DEBUG("error entity %p\n", ctx_entity);
463+ return r;
464+ }
465+
466+ *entity = ctx_entity;
459467 return 0;
460468 }
461469
@@ -586,7 +594,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, · 124 unmodified lines
586594 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter))
587595 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET;
588596
589− if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
597+ if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm))
590598 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
591599
592600 if (atomic_read(&ctx->guilty))
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h+1−1
@@ -47,7 +47,7 @@ struct amdgpu_ctx { · 46 unmodified lines
4747 struct amdgpu_ctx_mgr *mgr;
4848 unsigned reset_counter;
4949 unsigned reset_counter_query;
50− uint32_t vram_lost_counter;
50+ uint64_t generation;
5151 spinlock_t ring_lock;
5252 struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
5353 bool preamble_presented;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+3−0
@@ -1515,6 +1515,7 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) · 1514 unmodified lines
15151515 mall_size += mall_size_per_umc;
15161516 }
15171517 adev->gmc.mall_size = mall_size;
1518+ adev->gmc.m_half_use = half_use;
15181519 break;
15191520 default:
15201521 dev_err(adev->dev,
@@ -1896,6 +1897,8 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) · 375 unmodified lines
18961897 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
18971898 break;
18981899 case IP_VERSION(9, 4, 3):
1900+ if (!amdgpu_exp_hw_support)
1901+ return -EINVAL;
18991902 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
19001903 break;
19011904 case IP_VERSION(10, 1, 10):
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+25−0
@@ -691,6 +691,30 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) · 690 unmodified lines
691691 }
692692 }
693693
694+/**
695+ * amdgpu_fence_driver_set_error - set error code on fences
696+ * @ring: the ring which contains the fences
697+ * @error: the error code to set
698+ *
699+ * Set an error code to all the fences pending on the ring.
700+ */
701+void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error)
702+{
703+ struct amdgpu_fence_driver *drv = &ring->fence_drv;
704+ unsigned long flags;
705+
706+ spin_lock_irqsave(&drv->lock, flags);
707+ for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) {
708+ struct dma_fence *fence;
709+
710+ fence = rcu_dereference_protected(drv->fences[i],
711+ lockdep_is_held(&drv->lock));
712+ if (fence && !dma_fence_is_signaled_locked(fence))
713+ dma_fence_set_error(fence, error);
714+ }
715+ spin_unlock_irqrestore(&drv->lock, flags);
716+}
717+
694718 /**
695719 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
696720 *
@@ -699,6 +723,7 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) · 2 unmodified lines
699723 */
700724 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
701725 {
726+ amdgpu_fence_driver_set_error(ring, -ECANCELED);
702727 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
703728 amdgpu_fence_process(ring);
704729 }
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+2−0
@@ -301,6 +301,8 @@ struct amdgpu_gmc { · 300 unmodified lines
301301
302302 /* MALL size */
303303 u64 mall_size;
304+ uint32_t m_half_use;
305+
304306 /* number of UMC instances */
305307 int num_umc;
306308 /* mode2 save restore */
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c+2−2
@@ -190,8 +190,8 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, · 189 unmodified lines
190190 pr_debug("hmm range: start = 0x%lx, end = 0x%lx",
191191 hmm_range->start, hmm_range->end);
192192
193− /* Assuming 512MB takes maxmium 1 second to fault page address */
194− timeout = max((hmm_range->end - hmm_range->start) >> 29, 1UL);
193+ /* Assuming 128MB takes maximum 1 second to fault page address */
194+ timeout = max((hmm_range->end - hmm_range->start) >> 27, 1UL);
195195 timeout *= HMM_RANGE_DEFAULT_TIMEOUT;
196196 timeout = jiffies + msecs_to_jiffies(timeout);
197197
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c+2−1
@@ -467,7 +467,8 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, · 466 unmodified lines
467467 handled = true;
468468
469469 } else {
470− DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
470+ DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",
471+ src_id, client_id);
471472 }
472473
473474 /* Send it to amdkfd as well if it isn't already handled */
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c+14−3
@@ -109,7 +109,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 108 unmodified lines
109109 (*job)->vm = vm;
110110
111111 amdgpu_sync_create(&(*job)->explicit_sync);
112− (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
112+ (*job)->generation = amdgpu_vm_generation(adev, vm);
113113 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
114114
115115 if (!entity)
@@ -258,16 +258,27 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job, · 142 unmodified lines
258258 struct dma_fence *fence = NULL;
259259 int r;
260260
261+ /* Ignore soft recovered fences here */
262+ r = drm_sched_entity_error(s_entity);
263+ if (r && r != -ENODATA)
264+ goto error;
265+
261266 if (!fence && job->gang_submit)
262267 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
263268
264269 while (!fence && job->vm && !job->vmid) {
265270 r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
266− if (r)
271+ if (r) {
267272 DRM_ERROR("Error getting VM ID (%d)\n", r);
273+ goto error;
274+ }
268275 }
269276
270277 return fence;
278+
279+error:
280+ dma_fence_set_error(&job->base.s_fence->finished, r);
281+ return NULL;
271282 }
272283
273284 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
@@ -284,7 +295,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) · 10 unmodified lines
284295 trace_amdgpu_sched_run_job(job);
285296
286297 /* Skip job if VRAM is lost and never resubmit gangs */
287− if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) ||
298+ if (job->generation != amdgpu_vm_generation(adev, job->vm) ||
288299 (job->job_run_counter && job->gang_submit))
289300 dma_fence_set_error(finished, -ECANCELED);
290301
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h+1−1
@@ -61,7 +61,7 @@ struct amdgpu_job { · 60 unmodified lines
6161 uint32_t gds_base, gds_size;
6262 uint32_t gws_base, gws_size;
6363 uint32_t oa_base, oa_size;
64− uint32_t vram_lost_counter;
64+ uint64_t generation;
6565
6666 /* user fence handling */
6767 uint64_t uf_addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h+0−2
@@ -99,8 +99,6 @@ struct amdgpu_nbio_funcs { · 98 unmodified lines
9999 int (*get_compute_partition_mode)(struct amdgpu_device *adev);
100100 u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,
101101 u32 *supp_modes);
102− void (*set_compute_partition_mode)(struct amdgpu_device *adev,
103− enum amdgpu_gfx_partition mode);
104102 };
105103
106104 struct amdgpu_nbio {
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+6−2
@@ -150,7 +150,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) · 149 unmodified lines
150150
151151 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
152152 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
153− else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size)
153+ else
154154 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
155155
156156 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
@@ -1282,8 +1282,12 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, · 1125 unmodified lines
12821282 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
12831283 struct amdgpu_mem_stats *stats)
12841284 {
1285− unsigned int domain;
12861285 uint64_t size = amdgpu_bo_size(bo);
1286+ unsigned int domain;
1287+
1288+ /* Abort if the BO doesn't currently have a backing store */
1289+ if (!bo->tbo.resource)
1290+ return;
12871291
12881292 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
12891293 switch (domain) {
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+22−1
@@ -569,6 +569,26 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index, · 568 unmodified lines
569569 return -ETIME;
570570 }
571571
572+int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
573+ uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
574+{
575+ uint32_t val;
576+ int i;
577+ struct amdgpu_device *adev = psp->adev;
578+
579+ if (psp->adev->no_hw_access)
580+ return 0;
581+
582+ for (i = 0; i < msec_timeout; i++) {
583+ val = RREG32(reg_index);
584+ if ((val & mask) == reg_val)
585+ return 0;
586+ msleep(1);
587+ }
588+
589+ return -ETIME;
590+}
591+
572592 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
573593 {
574594 switch (cmd_id) {
@@ -1653,10 +1673,11 @@ int psp_ras_initialize(struct psp_context *psp) · 1078 unmodified lines
16531673
16541674 if (amdgpu_ras_is_poison_mode_supported(adev))
16551675 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1656− if (!adev->gmc.xgmi.connected_to_cpu)
1676+ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
16571677 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
16581678 ras_cmd->ras_in_message.init_flags.xcc_mask =
16591679 adev->gfx.xcc_mask;
1680+ ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
16601681
16611682 ret = psp_ta_load(psp, &psp->ras_context.context);
16621683
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+2−0
@@ -455,6 +455,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; · 454 unmodified lines
455455
456456 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
457457 uint32_t field_val, uint32_t mask, bool check_changed);
458+extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
459+ uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
458460
459461 int psp_gpu_reset(struct amdgpu_device *adev);
460462 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+8−8
@@ -171,8 +171,7 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre · 170 unmodified lines
171171
172172 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
173173 err_data.err_addr = &err_rec;
174− amdgpu_umc_fill_error_record(&err_data, address,
175− (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
174+ amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
176175
177176 if (amdgpu_bad_page_threshold != 0) {
178177 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
@@ -490,7 +489,8 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, · 311 unmodified lines
490489 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
491490 break;
492491 case 2:
493− if ((data.inject.address >= adev->gmc.mc_vram_size) ||
492+ if ((data.inject.address >= adev->gmc.mc_vram_size &&
493+ adev->gmc.mc_vram_size) ||
494494 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
495495 dev_warn(adev->dev, "RAS WARN: input address "
496496 "0x%llx is invalid.",
@@ -1491,6 +1491,7 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) · 994 unmodified lines
14911491 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
14921492 {
14931493 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1494+ struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
14941495 struct drm_minor *minor = adev_to_drm(adev)->primary;
14951496 struct dentry *dir;
14961497
@@ -1501,6 +1502,7 @@ static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device * · 4 unmodified lines
15011502 &amdgpu_ras_debugfs_eeprom_ops);
15021503 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
15031504 &con->bad_page_cnt_threshold);
1505+ debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
15041506 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
15051507 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
15061508 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
@@ -1685,8 +1687,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager * · 178 unmodified lines
16851687 }
16861688 }
16871689
1688− if (!adev->gmc.xgmi.connected_to_cpu)
1689− amdgpu_umc_poison_handler(adev, false);
1690+ amdgpu_umc_poison_handler(adev, false);
16901691
16911692 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
16921693 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
@@ -2451,11 +2452,10 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) · 758 unmodified lines
24512452 {
24522453 adev->ras_hw_enabled = adev->ras_enabled = 0;
24532454
2454− if (!adev->is_atom_fw ||
2455− !amdgpu_ras_asic_supported(adev))
2455+ if (!amdgpu_ras_asic_supported(adev))
24562456 return;
24572457
2458− if (!adev->gmc.xgmi.connected_to_cpu) {
2458+ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
24592459 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
24602460 dev_info(adev->dev, "MEM ECC is active.\n");
24612461 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+2−2
@@ -72,7 +72,7 @@ · 71 unmodified lines
7272 /* Bad GPU tag ‘BADG’ */
7373 #define RAS_TABLE_HDR_BAD 0x42414447
7474
75−/**
75+/*
7676 * EEPROM Table structure v1
7777 * ---------------------------------
7878 * | |
@@ -94,7 +94,7 @@ · 15 unmodified lines
9494 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
9595 / RAS_TABLE_RECORD_SIZE)
9696
97−/**
97+/*
9898 * EEPROM Table structrue v2.1
9999 * ---------------------------------
100100 * | |
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+23−0
@@ -433,11 +433,18 @@ void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, · 432 unmodified lines
433433 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
434434 struct dma_fence *fence)
435435 {
436+ unsigned long flags;
437+
436438 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
437439
438440 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
439441 return false;
440442
443+ spin_lock_irqsave(fence->lock, flags);
444+ if (!dma_fence_is_signaled_locked(fence))
445+ dma_fence_set_error(fence, -ENODATA);
446+ spin_unlock_irqrestore(fence->lock, flags);
447+
441448 atomic_inc(&ring->adev->gpu_reset_counter);
442449 while (!dma_fence_is_signaled(fence) &&
443450 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
@@ -561,6 +568,17 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { · 117 unmodified lines
561568 .llseek = default_llseek
562569 };
563570
571+static int amdgpu_debugfs_ring_error(void *data, u64 val)
572+{
573+ struct amdgpu_ring *ring = data;
574+
575+ amdgpu_fence_driver_set_error(ring, val);
576+ return 0;
577+}
578+
579+DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL,
580+ amdgpu_debugfs_ring_error, "%lld\n");
581+
564582 #endif
565583
566584 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
@@ -582,6 +600,11 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, · 15 unmodified lines
582600 &amdgpu_debugfs_mqd_fops,
583601 ring->mqd_size);
584602 }
603+
604+ sprintf(name, "amdgpu_error_%s", ring->name);
605+ debugfs_create_file(name, 0200, root, ring,
606+ &amdgpu_debugfs_error_fops);
607+
585608 #endif
586609 }
587610
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+1−0
@@ -126,6 +126,7 @@ struct amdgpu_fence_driver { · 125 unmodified lines
126126 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
127127
128128 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
129+void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
129130 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
130131
131132 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+9−9
@@ -228,7 +228,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 227 unmodified lines
228228 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
229229 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
230230
231− r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
231+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
232232 AMDGPU_FENCE_OWNER_UNDEFINED,
233233 num_dw * 4 + num_bytes,
234234 AMDGPU_IB_POOL_DELAYED, &job);
@@ -1456,7 +1456,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, · 1221 unmodified lines
14561456 memcpy(adev->mman.sdma_access_ptr, buf, len);
14571457
14581458 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1459− r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1459+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
14601460 AMDGPU_FENCE_OWNER_UNDEFINED,
14611461 num_dw * 4, AMDGPU_IB_POOL_DELAYED,
14621462 &job);
@@ -2032,7 +2032,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 569 unmodified lines
20322032
20332033 ring = adev->mman.buffer_funcs_ring;
20342034 sched = &ring->sched;
2035− r = drm_sched_entity_init(&adev->mman.entity,
2035+ r = drm_sched_entity_init(&adev->mman.high_pr,
20362036 DRM_SCHED_PRIORITY_KERNEL, &sched,
20372037 1, NULL);
20382038 if (r) {
@@ -2041,7 +2041,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
20412041 return;
20422042 }
20432043
2044− r = drm_sched_entity_init(&adev->mman.delayed,
2044+ r = drm_sched_entity_init(&adev->mman.low_pr,
20452045 DRM_SCHED_PRIORITY_NORMAL, &sched,
20462046 1, NULL);
20472047 if (r) {
@@ -2050,8 +2050,8 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
20502050 goto error_free_entity;
20512051 }
20522052 } else {
2053− drm_sched_entity_destroy(&adev->mman.entity);
2054− drm_sched_entity_destroy(&adev->mman.delayed);
2053+ drm_sched_entity_destroy(&adev->mman.high_pr);
2054+ drm_sched_entity_destroy(&adev->mman.low_pr);
20552055 dma_fence_put(man->move);
20562056 man->move = NULL;
20572057 }
@@ -2067,7 +2067,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 9 unmodified lines
20672067 return;
20682068
20692069 error_free_entity:
2070− drm_sched_entity_destroy(&adev->mman.entity);
2070+ drm_sched_entity_destroy(&adev->mman.high_pr);
20712071 }
20722072
20732073 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
@@ -2082,8 +2082,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, · 8 unmodified lines
20822082 AMDGPU_IB_POOL_DIRECT :
20832083 AMDGPU_IB_POOL_DELAYED;
20842084 int r;
2085− struct drm_sched_entity *entity = delayed ? &adev->mman.delayed :
2086− &adev->mman.entity;
2085+ struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2086+ &adev->mman.high_pr;
20872087 r = amdgpu_job_alloc_with_ib(adev, entity,
20882088 AMDGPU_FENCE_OWNER_UNDEFINED,
20892089 num_dw * 4, pool, job);
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h+4−4
@@ -59,10 +59,10 @@ struct amdgpu_mman { · 58 unmodified lines
5959 bool buffer_funcs_enabled;
6060
6161 struct mutex gtt_window_lock;
62− /* Scheduler entity for buffer moves */
63− struct drm_sched_entity entity;
64− /* Scheduler entity for VRAM clearing */
65− struct drm_sched_entity delayed;
62+ /* High priority scheduler entity for buffer moves */
63+ struct drm_sched_entity high_pr;
64+ /* Low priority scheduler entity for VRAM clearing */
65+ struct drm_sched_entity low_pr;
6666
6767 struct amdgpu_vram_mgr vram_mgr;
6868 struct amdgpu_gtt_mgr gtt_mgr;
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+19−15
@@ -169,27 +169,31 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset) · 168 unmodified lines
169169 {
170170 int ret = AMDGPU_RAS_SUCCESS;
171171
172− if (!amdgpu_sriov_vf(adev)) {
173− if (!adev->gmc.xgmi.connected_to_cpu) {
174− struct ras_err_data err_data = {0, 0, 0, NULL};
175− struct ras_common_if head = {
176− .block = AMDGPU_RAS_BLOCK__UMC,
177− };
178− struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
179−
180− ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
181−
182− if (ret == AMDGPU_RAS_SUCCESS && obj) {
183− obj->err_data.ue_count += err_data.ue_count;
184− obj->err_data.ce_count += err_data.ce_count;
185− }
186− } else if (reset) {
172+ if (adev->gmc.xgmi.connected_to_cpu ||
173+ adev->gmc.is_app_apu) {
174+ if (reset) {
187175 /* MCA poison handler is only responsible for GPU reset,
188176 * let MCA notifier do page retirement.
189177 */
190178 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
191179 amdgpu_ras_reset_gpu(adev);
192180 }
181+ return ret;
182+ }
183+
184+ if (!amdgpu_sriov_vf(adev)) {
185+ struct ras_err_data err_data = {0, 0, 0, NULL};
186+ struct ras_common_if head = {
187+ .block = AMDGPU_RAS_BLOCK__UMC,
188+ };
189+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
190+
191+ ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
192+
193+ if (ret == AMDGPU_RAS_SUCCESS && obj) {
194+ obj->err_data.ue_count += err_data.ue_count;
195+ obj->err_data.ce_count += err_data.ce_count;
196+ }
193197 } else {
194198 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
195199 adev->virt.ops->ras_poison_handler(adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+130−46
@@ -266,6 +266,32 @@ static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) · 265 unmodified lines
266266 spin_unlock(&vm_bo->vm->status_lock);
267267 }
268268
269+/**
270+ * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
271+ * @vm: the VM which state machine to reset
272+ *
273+ * Move all vm_bo object in the VM into a state where they will be updated
274+ * again during validation.
275+ */
276+static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
277+{
278+ struct amdgpu_vm_bo_base *vm_bo, *tmp;
279+
280+ spin_lock(&vm->status_lock);
281+ list_splice_init(&vm->done, &vm->invalidated);
282+ list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
283+ vm_bo->moved = true;
284+ list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
285+ struct amdgpu_bo *bo = vm_bo->bo;
286+
287+ if (!bo || bo->tbo.type != ttm_bo_type_kernel)
288+ list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
289+ else if (bo->parent)
290+ list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
291+ }
292+ spin_unlock(&vm->status_lock);
293+}
294+
269295 /**
270296 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
271297 *
@@ -351,6 +377,58 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, · 79 unmodified lines
351377 spin_unlock(&adev->mman.bdev.lru_lock);
352378 }
353379
380+/* Create scheduler entities for page table updates */
381+static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
382+ struct amdgpu_vm *vm)
383+{
384+ int r;
385+
386+ r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
387+ adev->vm_manager.vm_pte_scheds,
388+ adev->vm_manager.vm_pte_num_scheds, NULL);
389+ if (r)
390+ goto error;
391+
392+ return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
393+ adev->vm_manager.vm_pte_scheds,
394+ adev->vm_manager.vm_pte_num_scheds, NULL);
395+
396+error:
397+ drm_sched_entity_destroy(&vm->immediate);
398+ return r;
399+}
400+
401+/* Destroy the entities for page table updates again */
402+static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
403+{
404+ drm_sched_entity_destroy(&vm->immediate);
405+ drm_sched_entity_destroy(&vm->delayed);
406+}
407+
408+/**
409+ * amdgpu_vm_generation - return the page table re-generation counter
410+ * @adev: the amdgpu_device
411+ * @vm: optional VM to check, might be NULL
412+ *
413+ * Returns a page table re-generation token to allow checking if submissions
414+ * are still valid to use this VM. The VM parameter might be NULL in which case
415+ * just the VRAM lost counter will be used.
416+ */
417+uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
418+{
419+ uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
420+
421+ if (!vm)
422+ return result;
423+
424+ result += vm->generation;
425+ /* Add one if the page tables will be re-generated on next CS */
426+ if (drm_sched_entity_error(&vm->delayed))
427+ ++result;
428+
429+ return result;
430+}
431+
354432 /**
355433 * amdgpu_vm_validate_pt_bos - validate the page table BOs
356434 *
@@ -373,6 +451,15 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 16 unmodified lines
373451 struct amdgpu_bo *bo;
374452 int r;
375453
454+ if (drm_sched_entity_error(&vm->delayed)) {
455+ ++vm->generation;
456+ amdgpu_vm_bo_reset_state_machine(vm);
457+ amdgpu_vm_fini_entities(vm);
458+ r = amdgpu_vm_init_entities(adev, vm);
459+ if (r)
460+ return r;
461+ }
462+
376463 spin_lock(&vm->status_lock);
377464 while (!list_empty(&vm->evicted)) {
378465 bo_base = list_first_entry(&vm->evicted,
@@ -920,42 +1007,51 @@ error_unlock: · 541 unmodified lines
9201007 return r;
9211008 }
9221009
1010+static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1011+ struct amdgpu_mem_stats *stats)
1012+{
1013+ struct amdgpu_vm *vm = bo_va->base.vm;
1014+ struct amdgpu_bo *bo = bo_va->base.bo;
1015+
1016+ if (!bo)
1017+ return;
1018+
1019+ /*
1020+ * For now ignore BOs which are currently locked and potentially
1021+ * changing their location.
1022+ */
1023+ if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1024+ !dma_resv_trylock(bo->tbo.base.resv))
1025+ return;
1026+
1027+ amdgpu_bo_get_memory(bo, stats);
1028+ if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1029+ dma_resv_unlock(bo->tbo.base.resv);
1030+}
1031+
9231032 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
9241033 struct amdgpu_mem_stats *stats)
9251034 {
9261035 struct amdgpu_bo_va *bo_va, *tmp;
9271036
9281037 spin_lock(&vm->status_lock);
929− list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
930− if (!bo_va->base.bo)
931− continue;
932− amdgpu_bo_get_memory(bo_va->base.bo, stats);
933− }
934− list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
935− if (!bo_va->base.bo)
936− continue;
937− amdgpu_bo_get_memory(bo_va->base.bo, stats);
938− }
939− list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
940− if (!bo_va->base.bo)
941− continue;
942− amdgpu_bo_get_memory(bo_va->base.bo, stats);
943− }
944− list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
945− if (!bo_va->base.bo)
946− continue;
947− amdgpu_bo_get_memory(bo_va->base.bo, stats);
948− }
949− list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
950− if (!bo_va->base.bo)
951− continue;
952− amdgpu_bo_get_memory(bo_va->base.bo, stats);
953− }
954− list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
955− if (!bo_va->base.bo)
956− continue;
957− amdgpu_bo_get_memory(bo_va->base.bo, stats);
958− }
1038+ list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1039+ amdgpu_vm_bo_get_memory(bo_va, stats);
1040+
1041+ list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1042+ amdgpu_vm_bo_get_memory(bo_va, stats);
1043+
1044+ list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1045+ amdgpu_vm_bo_get_memory(bo_va, stats);
1046+
1047+ list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1048+ amdgpu_vm_bo_get_memory(bo_va, stats);
1049+
1050+ list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1051+ amdgpu_vm_bo_get_memory(bo_va, stats);
1052+
1053+ list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1054+ amdgpu_vm_bo_get_memory(bo_va, stats);
9591055 spin_unlock(&vm->status_lock);
9601056 }
9611057
@@ -2039,19 +2135,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 1077 unmodified lines
20392135 INIT_LIST_HEAD(&vm->pt_freed);
20402136 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
20412137
2042− /* create scheduler entities for page table updates */
2043− r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2044− adev->vm_manager.vm_pte_scheds,
2045− adev->vm_manager.vm_pte_num_scheds, NULL);
2138+ r = amdgpu_vm_init_entities(adev, vm);
20462139 if (r)
20472140 return r;
20482141
2049− r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2050− adev->vm_manager.vm_pte_scheds,
2051− adev->vm_manager.vm_pte_num_scheds, NULL);
2052− if (r)
2053− goto error_free_immediate;
2054−
20552142 vm->pte_support_ats = false;
20562143 vm->is_compute_context = false;
20572144
@@ -2072,6 +2159,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 14 unmodified lines
20722159 vm->last_update = dma_fence_get_stub();
20732160 vm->last_unlocked = dma_fence_get_stub();
20742161 vm->last_tlb_flush = dma_fence_get_stub();
2162+ vm->generation = 0;
20752163
20762164 mutex_init(&vm->eviction_lock);
20772165 vm->evicting = false;
@@ -2112,10 +2200,7 @@ error_free_root: · 34 unmodified lines
21122200 error_free_delayed:
21132201 dma_fence_put(vm->last_tlb_flush);
21142202 dma_fence_put(vm->last_unlocked);
2115− drm_sched_entity_destroy(&vm->delayed);
2116−
2117−error_free_immediate:
2118− drm_sched_entity_destroy(&vm->immediate);
2203+ amdgpu_vm_fini_entities(vm);
21192204
21202205 return r;
21212206 }
@@ -2268,8 +2353,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) · 146 unmodified lines
22682353 amdgpu_bo_unref(&root);
22692354 WARN_ON(vm->root.bo);
22702355
2271− drm_sched_entity_destroy(&vm->immediate);
2272− drm_sched_entity_destroy(&vm->delayed);
2356+ amdgpu_vm_fini_entities(vm);
22732357
22742358 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
22752359 dev_err(adev->dev, "still active bo inside vm\n");
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+4−0
@@ -295,6 +295,9 @@ struct amdgpu_vm { · 294 unmodified lines
295295 atomic64_t tlb_seq;
296296 struct dma_fence *last_tlb_flush;
297297
298+ /* How many times we had to re-generate the page tables */
299+ uint64_t generation;
300+
298301 /* Last unlocked submission to the scheduler entities */
299302 struct dma_fence *last_unlocked;
300303
@@ -397,6 +400,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, · 96 unmodified lines
397400 struct list_head *validated,
398401 struct amdgpu_bo_list_entry *entry);
399402 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
403+uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
400404 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
401405 int (*callback)(void *p, struct amdgpu_bo *bo),
402406 void *param);
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+46−0
@@ -325,6 +325,36 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, · 324 unmodified lines
325325
326326 }
327327
328+static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev,
329+ struct device_attribute *attr,
330+ char *buf)
331+{
332+ struct drm_device *ddev = dev_get_drvdata(dev);
333+ struct amdgpu_device *adev = drm_to_adev(ddev);
334+ struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
335+ int i;
336+
337+ for (i = 0; i < top->num_nodes; i++)
338+ sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops);
339+
340+ return sysfs_emit(buf, "%s\n", buf);
341+}
342+
343+static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,
344+ struct device_attribute *attr,
345+ char *buf)
346+{
347+ struct drm_device *ddev = dev_get_drvdata(dev);
348+ struct amdgpu_device *adev = drm_to_adev(ddev);
349+ struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
350+ int i;
351+
352+ for (i = 0; i < top->num_nodes; i++)
353+ sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links);
354+
355+ return sysfs_emit(buf, "%s\n", buf);
356+}
357+
328358 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801)
329359 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
330360 struct device_attribute *attr,
@@ -361,6 +391,8 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev, · 30 unmodified lines
361391
362392 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
363393 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
394+static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);
395+static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);
364396
365397 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
366398 struct amdgpu_hive_info *hive)
@@ -380,6 +412,15 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, · 13 unmodified lines
380412 if (ret)
381413 pr_err("failed to create xgmi_error\n");
382414
415+ /* Create xgmi num hops file */
416+ ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops);
417+ if (ret)
418+ pr_err("failed to create xgmi_num_hops\n");
419+
420+ /* Create xgmi num links file */
421+ ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links);
422+ if (ret)
423+ pr_err("failed to create xgmi_num_links\n");
383424
384425 /* Create sysfs link to hive info folder on the first device */
385426 if (hive->kobj.parent != (&adev->dev->kobj)) {
@@ -407,6 +448,9 @@ remove_link: · 21 unmodified lines
407448
408449 remove_file:
409450 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
451+ device_remove_file(adev->dev, &dev_attr_xgmi_error);
452+ device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
453+ device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
410454
411455 success:
412456 return ret;
@@ -420,6 +464,8 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, · 7 unmodified lines
420464
421465 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
422466 device_remove_file(adev->dev, &dev_attr_xgmi_error);
467+ device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
468+ device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
423469
424470 if (hive->kobj.parent != (&adev->dev->kobj))
425471 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c+0−3
@@ -518,9 +518,6 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, · 517 unmodified lines
518518 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
519519 num_xcc_per_xcp);
520520
521− if (adev->nbio.funcs->set_compute_partition_mode)
522− adev->nbio.funcs->set_compute_partition_mode(adev, mode);
523−
524521 /* Init info about new xcps */
525522 *num_xcps = num_xcc / num_xcc_per_xcp;
526523 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c+6−12
@@ -623,22 +623,16 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, · 622 unmodified lines
623623 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
624624 int num_xccs_per_xcp)
625625 {
626− int i, num_xcc;
627− u32 tmp = 0;
628−
629− num_xcc = NUM_XCC(adev->gfx.xcc_mask);
626+ int ret;
630627
631− for (i = 0; i < num_xcc; i++) {
632− tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
633− num_xccs_per_xcp);
634− tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
635− i % num_xccs_per_xcp);
636− WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp);
637− }
628+ ret = psp_spatial_partition(&adev->psp, NUM_XCC(adev->gfx.xcc_mask) /
629+ num_xccs_per_xcp);
630+ if (ret)
631+ return ret;
638632
639633 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
640634
641− return 0;
635+ return ret;
642636 }
643637
644638 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+1−1
@@ -382,7 +382,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 381 unmodified lines
382382 * translation. Avoid this by doing the invalidation from the SDMA
383383 * itself.
384384 */
385− r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.entity,
385+ r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
386386 AMDGPU_FENCE_OWNER_UNDEFINED,
387387 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
388388 &job);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+1−0
@@ -2107,6 +2107,7 @@ static int gmc_v9_0_sw_init(void *handle) · 2106 unmodified lines
21072107 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
21082108
21092109 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2110+ adev->gmc.translate_further = adev->vm_manager.num_level > 1;
21102111 break;
21112112 default:
21122113 break;
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c+1−17
@@ -390,22 +390,7 @@ static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) · 389 unmodified lines
390390 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
391391 PARTITION_MODE);
392392
393− return ffs(px);
394−}
395−
396−static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
397− enum amdgpu_gfx_partition mode)
398−{
399− u32 tmp;
400−
401− /* Each bit represents DPX,TPX,QPX,CPX mode. No bit set means default
402− * SPX mode.
403− */
404− tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
405− tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
406− PARTITION_MODE, mode ? BIT(mode - 1) : mode);
407−
408− WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS, tmp);
393+ return px;
409394 }
410395
411396 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
@@ -463,7 +448,6 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { · 51 unmodified lines
463448 .ih_control = nbio_v7_9_ih_control,
464449 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
465450 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
466− .set_compute_partition_mode = nbio_v7_9_set_compute_partition_mode,
467451 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
468452 .init_registers = nbio_v7_9_init_registers,
469453 };
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c+5−4
@@ -624,10 +624,11 @@ static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) · 623 unmodified lines
624624 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
625625
626626 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
627− return 0;
628−
629− ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
630− MBOX_READY_FLAG, MBOX_READY_MASK, false);
627+ ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
628+ MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
629+ else
630+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
631+ MBOX_READY_FLAG, MBOX_READY_MASK, false);
631632 if (ret) {
632633 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
633634 return ret;
drivers/gpu/drm/amd/amdgpu/psp_v13_0.h+2−0
@@ -25,6 +25,8 @@ · 24 unmodified lines
2525
2626 #include "amdgpu_psp.h"
2727
28+#define PSP_SPIROM_UPDATE_TIMEOUT 60000 /* 60s */
29+
2830 void psp_v13_0_set_psp_funcs(struct psp_context *psp);
2931
3032 #endif
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+2−2
@@ -2312,7 +2312,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = { · 2311 unmodified lines
23122312
23132313 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
23142314 .type = AMDGPU_RING_TYPE_SDMA,
2315− .align_mask = 0xf,
2315+ .align_mask = 0xff,
23162316 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
23172317 .support_64bit_ptrs = true,
23182318 .secure_submission_supported = true,
@@ -2344,7 +2344,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { · 25 unmodified lines
23442344
23452345 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
23462346 .type = AMDGPU_RING_TYPE_SDMA,
2347− .align_mask = 0xf,
2347+ .align_mask = 0xff,
23482348 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
23492349 .support_64bit_ptrs = true,
23502350 .secure_submission_supported = true,
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c+12−8
@@ -1434,9 +1434,11 @@ static int sdma_v4_4_2_hw_fini(void *handle) · 1433 unmodified lines
14341434 return 0;
14351435
14361436 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1437− for (i = 0; i < adev->sdma.num_instances; i++) {
1438− amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1439− AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1437+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1438+ for (i = 0; i < adev->sdma.num_instances; i++) {
1439+ amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1440+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1441+ }
14401442 }
14411443
14421444 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
@@ -1823,7 +1825,7 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { · 380 unmodified lines
18231825
18241826 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
18251827 .type = AMDGPU_RING_TYPE_SDMA,
1826− .align_mask = 0xf,
1828+ .align_mask = 0xff,
18271829 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
18281830 .support_64bit_ptrs = true,
18291831 .get_rptr = sdma_v4_4_2_ring_get_rptr,
@@ -1854,7 +1856,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { · 24 unmodified lines
18541856
18551857 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
18561858 .type = AMDGPU_RING_TYPE_SDMA,
1857− .align_mask = 0xf,
1859+ .align_mask = 0xff,
18581860 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
18591861 .support_64bit_ptrs = true,
18601862 .get_rptr = sdma_v4_4_2_ring_get_rptr,
@@ -2073,9 +2075,11 @@ static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) · 212 unmodified lines
20732075 uint32_t tmp_mask = inst_mask;
20742076 int i;
20752077
2076− for_each_inst(i, tmp_mask) {
2077− amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2078− AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2078+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2079+ for_each_inst(i, tmp_mask) {
2080+ amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2081+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2082+ }
20792083 }
20802084
20812085 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h+1−0
@@ -130,6 +130,7 @@ struct ta_ras_init_flags { · 129 unmodified lines
130130 uint8_t poison_mode_en;
131131 uint8_t dgpu_mode;
132132 uint16_t xcc_mask;
133+ uint8_t channel_dis_num;
133134 };
134135
135136 struct ta_ras_output_flags {
drivers/gpu/drm/amd/amdgpu/umc_v8_10.h+2−1
@@ -33,7 +33,8 @@ · 32 unmodified lines
3333
3434 /* Total channel instances for all available umc nodes */
3535 #define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \
36− (UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * (adev)->gmc.num_umc)
36+ (UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * \
37+ (adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
3738
3839 /* UMC regiser per channel offset */
3940 #define UMC_V8_10_PER_CHANNEL_OFFSET 0x400
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c+5−1
@@ -129,7 +129,11 @@ static int vcn_v4_0_sw_init(void *handle) · 128 unmodified lines
129129 if (adev->vcn.harvest_config & (1 << i))
130130 continue;
131131
132− atomic_set(&adev->vcn.inst[i].sched_score, 0);
132+ /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
133+ if (i == 0)
134+ atomic_set(&adev->vcn.inst[i].sched_score, 1);
135+ else
136+ atomic_set(&adev->vcn.inst[i].sched_score, 0);
133137
134138 /* VCN UNIFIED TRAP */
135139 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
drivers/gpu/drm/amd/amdkfd/kfd_crat.c+0−5
@@ -30,9 +30,6 @@ · 29 unmodified lines
3030 #include "amdgpu.h"
3131 #include "amdgpu_amdkfd.h"
3232
33−/* Fixme: Fake 32GB for 1PNPS1 mode bringup */
34−#define DUMMY_VRAM_SIZE 31138512896
35−
3633 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
3734 * GPU processor ID are expressed with Bit[31]=1.
3835 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
@@ -1056,8 +1053,6 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, · 1017 unmodified lines
10561053
10571054 props->heap_type = heap_type;
10581055 props->flags = flags;
1059− if (size_in_bytes == 0)
1060− size_in_bytes = DUMMY_VRAM_SIZE; /* Fixme: TBD */
10611056 props->size_in_bytes = size_in_bytes;
10621057 props->width = width;
10631058
drivers/gpu/drm/amd/amdkfd/kfd_debug.c+1−1
@@ -1097,7 +1097,7 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, · 1096 unmodified lines
10971097
10981098 pqm = &target->pqm;
10991099 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
1100− if (!pqn)
1100+ if (!pqn->q)
11011101 continue;
11021102
11031103 found_mask |= pqn->q->properties.exception_status;
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+3−3
@@ -227,7 +227,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, · 226 unmodified lines
227227 queue_input.tba_addr = qpd->tba_addr;
228228 queue_input.tma_addr = qpd->tma_addr;
229229 queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) ||
230− KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0);
230+ KFD_GC_VERSION(q->device) > IP_VERSION(11, 0, 3);
231231 queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled;
232232
233233 queue_type = convert_to_mes_queue_type(q->properties.type);
@@ -1807,7 +1807,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, · 1573 unmodified lines
18071807 q->properties.is_evicted = !!qpd->evicted;
18081808 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
18091809 KFD_GC_VERSION(q->device) >= IP_VERSION(11, 0, 0) &&
1810− KFD_GC_VERSION(q->device) < IP_VERSION(12, 0, 0);
1810+ KFD_GC_VERSION(q->device) <= IP_VERSION(11, 0, 3);
18111811
18121812 if (qd)
18131813 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
@@ -2089,8 +2089,8 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, · 275 unmodified lines
20892089 list_del(&q->list);
20902090 qpd->queue_count--;
20912091 if (q->properties.is_active) {
2092+ decrement_queue_count(dqm, qpd, q);
20922093 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2093− decrement_queue_count(dqm, qpd, q);
20942094 retval = execute_queues_cpsch(dqm,
20952095 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
20962096 USE_DEFAULT_GRACE_PERIOD);
drivers/gpu/drm/amd/amdkfd/kfd_events.c+34−12
@@ -41,6 +41,7 @@ struct kfd_event_waiter { · 40 unmodified lines
4141 wait_queue_entry_t wait;
4242 struct kfd_event *event; /* Event to wait for */
4343 bool activated; /* Becomes true when event is signaled */
44+ bool event_age_enabled; /* set to true when last_event_age is non-zero */
4445 };
4546
4647 /*
@@ -431,6 +432,7 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p, · 384 unmodified lines
431432 if (!ret) {
432433 *event_id = ev->event_id;
433434 *event_trigger_data = ev->event_id;
435+ ev->event_age = 1;
434436 } else {
435437 kfree(ev);
436438 }
@@ -629,6 +631,11 @@ static void set_event(struct kfd_event *ev) · 192 unmodified lines
629631 * updating the wait queues in kfd_wait_on_events.
630632 */
631633 ev->signaled = !ev->auto_reset || !waitqueue_active(&ev->wq);
634+ if (!(++ev->event_age)) {
635+ /* Never wrap back to reserved/default event age 0/1 */
636+ ev->event_age = 2;
637+ WARN_ONCE(1, "event_age wrap back!");
638+ }
632639
633640 list_for_each_entry(waiter, &ev->wq.head, wait.entry)
634641 WRITE_ONCE(waiter->activated, true);
@@ -791,9 +798,9 @@ static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) · 156 unmodified lines
791798
792799 static int init_event_waiter(struct kfd_process *p,
793800 struct kfd_event_waiter *waiter,
794− uint32_t event_id)
801+ struct kfd_event_data *event_data)
795802 {
796− struct kfd_event *ev = lookup_event_by_id(p, event_id);
803+ struct kfd_event *ev = lookup_event_by_id(p, event_data->event_id);
797804
798805 if (!ev)
799806 return -EINVAL;
@@ -802,6 +809,15 @@ static int init_event_waiter(struct kfd_process *p, · 2 unmodified lines
802809 waiter->event = ev;
803810 waiter->activated = ev->signaled;
804811 ev->signaled = ev->signaled && !ev->auto_reset;
812+
813+ /* last_event_age = 0 reserved for backward compatible */
814+ if (waiter->event->type == KFD_EVENT_TYPE_SIGNAL &&
815+ event_data->signal_event_data.last_event_age) {
816+ waiter->event_age_enabled = true;
817+ if (ev->event_age != event_data->signal_event_data.last_event_age)
818+ waiter->activated = true;
819+ }
820+
805821 if (!waiter->activated)
806822 add_wait_queue(&ev->wq, &waiter->wait);
807823 spin_unlock(&ev->lock);
@@ -849,22 +865,29 @@ static int copy_signaled_event_data(uint32_t num_events, · 41 unmodified lines
849865 struct kfd_event_waiter *event_waiters,
850866 struct kfd_event_data __user *data)
851867 {
852− struct kfd_hsa_memory_exception_data *src;
853− struct kfd_hsa_memory_exception_data __user *dst;
868+ void *src;
869+ void __user *dst;
854870 struct kfd_event_waiter *waiter;
855871 struct kfd_event *event;
856− uint32_t i;
872+ uint32_t i, size = 0;
857873
858874 for (i = 0; i < num_events; i++) {
859875 waiter = &event_waiters[i];
860876 event = waiter->event;
861877 if (!event)
862878 return -EINVAL; /* event was destroyed */
863− if (waiter->activated && event->type == KFD_EVENT_TYPE_MEMORY) {
864− dst = &data[i].memory_exception_data;
865− src = &event->memory_exception_data;
866− if (copy_to_user(dst, src,
867− sizeof(struct kfd_hsa_memory_exception_data)))
879+ if (waiter->activated) {
880+ if (event->type == KFD_EVENT_TYPE_MEMORY) {
881+ dst = &data[i].memory_exception_data;
882+ src = &event->memory_exception_data;
883+ size = sizeof(struct kfd_hsa_memory_exception_data);
884+ } else if (event->type == KFD_EVENT_TYPE_SIGNAL &&
885+ waiter->event_age_enabled) {
886+ dst = &data[i].signal_event_data.last_event_age;
887+ src = &event->event_age;
888+ size = sizeof(u64);
889+ }
890+ if (size && copy_to_user(dst, src, size))
868891 return -EFAULT;
869892 }
870893 }
@@ -942,8 +965,7 @@ int kfd_wait_on_events(struct kfd_process *p, · 71 unmodified lines
942965 goto out_unlock;
943966 }
944967
945− ret = init_event_waiter(p, &event_waiters[i],
946− event_data.event_id);
968+ ret = init_event_waiter(p, &event_waiters[i], &event_data);
947969 if (ret)
948970 goto out_unlock;
949971 }
drivers/gpu/drm/amd/amdkfd/kfd_events.h+1−0
@@ -53,6 +53,7 @@ struct signal_page; · 52 unmodified lines
5353
5454 struct kfd_event {
5555 u32 event_id;
56+ u64 event_age;
5657
5758 bool signaled;
5859 bool auto_reset;
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c+1−1
@@ -64,7 +64,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages, · 63 unmodified lines
6464 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
6565 num_bytes = npages * 8;
6666
67− r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
67+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
6868 AMDGPU_FENCE_OWNER_UNDEFINED,
6969 num_dw * 4 + num_bytes,
7070 AMDGPU_IB_POOL_DELAYED,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+41−24
@@ -3267,6 +3267,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) · 3266 unmodified lines
32673267
32683268 while (dret == dpcd_bytes_to_read &&
32693269 process_count < max_process_count) {
3270+ u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
32703271 u8 retry;
32713272 dret = 0;
32723273
@@ -3275,28 +3276,29 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) · 2 unmodified lines
32753276 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
32763277 /* handle HPD short pulse irq */
32773278 if (aconnector->mst_mgr.mst_state)
3278− drm_dp_mst_hpd_irq(
3279− &aconnector->mst_mgr,
3280− esi,
3281− &new_irq_handled);
3279+ drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
3280+ esi,
3281+ ack,
3282+ &new_irq_handled);
32823283
32833284 if (new_irq_handled) {
32843285 /* ACK at DPCD to notify down stream */
3285− const int ack_dpcd_bytes_to_write =
3286− dpcd_bytes_to_read - 1;
3287−
32883286 for (retry = 0; retry < 3; retry++) {
3289− u8 wret;
3290−
3291− wret = drm_dp_dpcd_write(
3292− &aconnector->dm_dp_aux.aux,
3293− dpcd_addr + 1,
3294− &esi[1],
3295− ack_dpcd_bytes_to_write);
3296− if (wret == ack_dpcd_bytes_to_write)
3287+ ssize_t wret;
3288+
3289+ wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
3290+ dpcd_addr + 1,
3291+ ack[1]);
3292+ if (wret == 1)
32973293 break;
32983294 }
32993295
3296+ if (retry == 3) {
3297+ DRM_ERROR("Failed to ack MST event.\n");
3298+ return;
3299+ }
3300+
3301+ drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
33003302 /* check if there is new irq to be handled */
33013303 dret = drm_dp_dpcd_read(
33023304 &aconnector->dm_dp_aux.aux,
@@ -7256,7 +7258,13 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) · 3953 unmodified lines
72567258 drm_add_modes_noedid(connector, 1920, 1080);
72577259 } else {
72587260 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7259− amdgpu_dm_connector_add_common_modes(encoder, connector);
7261+ /* most eDP supports only timings from its edid,
7262+ * usually only detailed timings are available
7263+ * from eDP edid. timings which are not from edid
7264+ * may damage eDP
7265+ */
7266+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
7267+ amdgpu_dm_connector_add_common_modes(encoder, connector);
72607268 amdgpu_dm_connector_add_freesync_modes(connector, edid);
72617269 }
72627270 amdgpu_dm_fbc_init(connector);
@@ -8273,6 +8281,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 1010 unmodified lines
82738281 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
82748282 bundle->stream_update.abm_level = &acrtc_state->abm_level;
82758283
8284+ mutex_lock(&dm->dc_lock);
8285+ if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8286+ acrtc_state->stream->link->psr_settings.psr_allow_active)
8287+ amdgpu_dm_psr_disable(acrtc_state->stream);
8288+ mutex_unlock(&dm->dc_lock);
8289+
82768290 /*
82778291 * If FreeSync state on the stream has changed then we need to
82788292 * re-adjust the min/max bounds now that DC doesn't handle this
@@ -8286,10 +8300,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 7 unmodified lines
82868300 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
82878301 }
82888302 mutex_lock(&dm->dc_lock);
8289− if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8290− acrtc_state->stream->link->psr_settings.psr_allow_active)
8291− amdgpu_dm_psr_disable(acrtc_state->stream);
8292−
82938303 update_planes_and_stream_adapter(dm->dc,
82948304 acrtc_state->update_type,
82958305 planes_count,
@@ -8951,10 +8961,17 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 655 unmodified lines
89518961
89528962 drm_atomic_helper_cleanup_planes(dev, state);
89538963
8954− /* return the stolen vga memory back to VRAM */
8955− if (!adev->mman.keep_stolen_vga_memory)
8956− amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8957− amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8964+ /* Don't free the memory if we are hitting this as part of suspend.
8965+ * This way we don't free any memory during suspend; see
8966+ * amdgpu_bo_free_kernel(). The memory will be freed in the first
8967+ * non-suspend modeset or when the driver is torn down.
8968+ */
8969+ if (!adev->in_suspend) {
8970+ /* return the stolen vga memory back to VRAM */
8971+ if (!adev->mman.keep_stolen_vga_memory)
8972+ amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8973+ amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8974+ }
89588975
89598976 /*
89608977 * Finally, drop a runtime PM reference for each newly disabled CRTC,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c+32−0
@@ -2760,6 +2760,32 @@ static int psr_read_residency(void *data, u64 *val) · 2759 unmodified lines
27602760 return 0;
27612761 }
27622762
2763+/* read allow_edp_hotplug_detection */
2764+static int allow_edp_hotplug_detection_get(void *data, u64 *val)
2765+{
2766+ struct amdgpu_dm_connector *aconnector = data;
2767+ struct drm_connector *connector = &aconnector->base;
2768+ struct drm_device *dev = connector->dev;
2769+ struct amdgpu_device *adev = drm_to_adev(dev);
2770+
2771+ *val = adev->dm.dc->config.allow_edp_hotplug_detection;
2772+
2773+ return 0;
2774+}
2775+
2776+/* set allow_edp_hotplug_detection */
2777+static int allow_edp_hotplug_detection_set(void *data, u64 val)
2778+{
2779+ struct amdgpu_dm_connector *aconnector = data;
2780+ struct drm_connector *connector = &aconnector->base;
2781+ struct drm_device *dev = connector->dev;
2782+ struct amdgpu_device *adev = drm_to_adev(dev);
2783+
2784+ adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
2785+
2786+ return 0;
2787+}
2788+
27632789 /*
27642790 * Set dmcub trace event IRQ enable or disable.
27652791 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
@@ -2798,6 +2824,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); · 32 unmodified lines
27982824 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
27992825 "%llu\n");
28002826
2827+DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
2828+ allow_edp_hotplug_detection_get,
2829+ allow_edp_hotplug_detection_set, "%llu\n");
2830+
28012831 DEFINE_SHOW_ATTRIBUTE(current_backlight);
28022832 DEFINE_SHOW_ATTRIBUTE(target_backlight);
28032833
@@ -2968,6 +2998,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) · 164 unmodified lines
29682998 &target_backlight_fops);
29692999 debugfs_create_file("ilr_setting", 0644, dir, connector,
29703000 &edp_ilr_debugfs_fops);
3001+ debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3002+ &allow_edp_hotplug_detection_fops);
29713003 }
29723004
29733005 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c+3−3
@@ -44,9 +44,6 @@ · 43 unmodified lines
4444 #include "dm_helpers.h"
4545 #include "ddc_service_types.h"
4646
47−/* MST Dock */
48−static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
49−
5047 /* dm_helpers_parse_edid_caps
5148 *
5249 * Parse edid caps
@@ -702,6 +699,9 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) · 649 unmodified lines
702699 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
703700 }
704701
702+/* MST Dock */
703+static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
704+
705705 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
706706 struct drm_dp_aux *aux,
707707 const struct dc_stream_state *stream,
drivers/gpu/drm/amd/display/dc/core/dc.c+16−20
@@ -1296,7 +1296,7 @@ static void disable_vbios_mode_if_required( · 1295 unmodified lines
12961296
12971297 if (pix_clk_100hz != requested_pix_clk_100hz) {
12981298 dc->link_srv->set_dpms_off(pipe);
1299− pipe->stream->dpms_off = true;
1299+ pipe->stream->dpms_off = false;
13001300 }
13011301 }
13021302 }
@@ -3480,23 +3480,21 @@ static void build_dmub_update_dirty_rect( · 2177 unmodified lines
34803480
34813481
34823482 /**
3483− * ************************************************************************************************
3484− * build_dmub_cmd_list: Build an array of DMCUB commands to be sent to DMCUB
3483+ * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
34853484 *
3486− * @param [in]: dc: Current DC state
3487− * @param [in]: srf_updates: Array of surface updates
3488− * @param [in]: surface_count: Number of surfaces that have an updated
3489− * @param [in]: stream: Correponding stream to be updated in the current flip
3490− * @param [in]: context: New DC state to be programmed
3485+ * @dc: Current DC state
3486+ * @srf_updates: Array of surface updates
3487+ * @surface_count: Number of surfaces that have an updated
3488+ * @stream: Corresponding stream to be updated in the current flip
3489+ * @context: New DC state to be programmed
34913490 *
3492− * @param [out]: dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3493− * @param [out]: dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3491+ * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3492+ * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
34943493 *
34953494 * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
34963495 * to build an array of commands and have them sent while the OTG lock is acquired.
34973496 *
3498− * @return: void
3499− * ************************************************************************************************
3497+ * Return: void
35003498 */
35013499 static void build_dmub_cmd_list(struct dc *dc,
35023500 struct dc_surface_update *srf_updates,
@@ -4201,20 +4199,18 @@ static bool commit_minimal_transition_state(struct dc *dc, · 698 unmodified lines
42014199 }
42024200
42034201 /**
4204− * *******************************************************************************
4205− * update_seamless_boot_flags: Helper function for updating seamless boot flags
4202+ * update_seamless_boot_flags() - Helper function for updating seamless boot flags
42064203 *
4207− * @param [in]: dc: Current DC state
4208− * @param [in]: context: New DC state to be programmed
4209− * @param [in]: surface_count: Number of surfaces that have an updated
4210− * @param [in]: stream: Correponding stream to be updated in the current flip
4204+ * @dc: Current DC state
4205+ * @context: New DC state to be programmed
4206+ * @surface_count: Number of surfaces that have an updated
4207+ * @stream: Corresponding stream to be updated in the current flip
42114208 *
42124209 * Updating seamless boot flags do not need to be part of the commit sequence. This
42134210 * helper function will update the seamless boot flags on each flip (if required)
42144211 * outside of the HW commit sequence (fast or slow).
42154212 *
4216− * @return: void
4217− * *******************************************************************************
4213+ * Return: void
42184214 */
42194215 static void update_seamless_boot_flags(struct dc *dc,
42204216 struct dc_state *context,
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c+70−0
@@ -562,6 +562,29 @@ void hwss_build_fast_sequence(struct dc *dc, · 561 unmodified lines
562562 (*num_steps)++;
563563 }
564564
565+ if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
566+ block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
567+ block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
568+ block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
569+ block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
570+ (*num_steps)++;
571+
572+ if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
573+ block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
574+ block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
575+ block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
576+ block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
577+ block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
578+ (*num_steps)++;
579+ } else {
580+ block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
581+ block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
582+ block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
583+ block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
584+ block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
585+ (*num_steps)++;
586+ }
587+ }
565588 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
566589 }
567590 current_pipe = current_pipe->next_odm_pipe;
@@ -661,6 +684,15 @@ void hwss_execute_sequence(struct dc *dc, · 93 unmodified lines
661684 params->update_visual_confirm_params.pipe_ctx,
662685 params->update_visual_confirm_params.mpcc_id);
663686 break;
687+ case MPC_POWER_ON_MPC_MEM_PWR:
688+ hwss_power_on_mpc_mem_pwr(params);
689+ break;
690+ case MPC_SET_OUTPUT_CSC:
691+ hwss_set_output_csc(params);
692+ break;
693+ case MPC_SET_OCSC_DEFAULT:
694+ hwss_set_ocsc_default(params);
695+ break;
664696 case DMUB_SEND_DMCUB_CMD:
665697 hwss_send_dmcub_cmd(params);
666698 break;
@@ -718,6 +750,44 @@ void hwss_program_bias_and_scale(union block_sequence_params *params) · 51 unmodified lines
718750 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
719751 }
720752
753+void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
754+{
755+ struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
756+ int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
757+ bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
758+
759+ if (mpc->funcs->power_on_mpc_mem_pwr)
760+ mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
761+}
762+
763+void hwss_set_output_csc(union block_sequence_params *params)
764+{
765+ struct mpc *mpc = params->set_output_csc_params.mpc;
766+ int opp_id = params->set_output_csc_params.opp_id;
767+ const uint16_t *matrix = params->set_output_csc_params.regval;
768+ enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
769+
770+ if (mpc->funcs->set_output_csc != NULL)
771+ mpc->funcs->set_output_csc(mpc,
772+ opp_id,
773+ matrix,
774+ ocsc_mode);
775+}
776+
777+void hwss_set_ocsc_default(union block_sequence_params *params)
778+{
779+ struct mpc *mpc = params->set_ocsc_default_params.mpc;
780+ int opp_id = params->set_ocsc_default_params.opp_id;
781+ enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
782+ enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
783+
784+ if (mpc->funcs->set_ocsc_default != NULL)
785+ mpc->funcs->set_ocsc_default(mpc,
786+ opp_id,
787+ colorspace,
788+ ocsc_mode);
789+}
790+
721791 void get_mclk_switch_visual_confirm_color(
722792 struct dc *dc,
723793 struct dc_state *context,
drivers/gpu/drm/amd/display/dc/dc.h+6−3
@@ -1,5 +1,5 @@
11 /*
2− * Copyright 2012-14 Advanced Micro Devices, Inc.
2+ * Copyright 2012-2023 Advanced Micro Devices, Inc.
33 *
44 * Permission is hereby granted, free of charge, to any person obtaining a
55 * copy of this software and associated documentation files (the "Software"),
@@ -45,7 +45,7 @@ struct aux_payload; · 39 unmodified lines
4545 struct set_config_cmd_payload;
4646 struct dmub_notification;
4747
48−#define DC_VER "3.2.237"
48+#define DC_VER "3.2.239"
4949
5050 #define MAX_SURFACES 3
5151 #define MAX_PLANES 6
@@ -60,7 +60,9 @@ struct dc_versions { · 8 unmodified lines
6060 };
6161
6262 enum dp_protocol_version {
63− DP_VERSION_1_4,
63+ DP_VERSION_1_4 = 0,
64+ DP_VERSION_2_1,
65+ DP_VERSION_UNKNOWN,
6466 };
6567
6668 enum dc_plane_type {
@@ -264,6 +266,7 @@ struct dc_caps { · 197 unmodified lines
264266 uint16_t subvp_pstate_allow_width_us;
265267 uint16_t subvp_vertical_int_margin_us;
266268 bool seamless_odm;
269+ uint32_t max_v_total;
267270 uint8_t subvp_drr_vblank_start_margin_us;
268271 };
269272
drivers/gpu/drm/amd/display/dc/dc_dp_types.h+1−1
@@ -61,7 +61,7 @@ enum dc_link_rate { · 60 unmodified lines
6161 */
6262 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
6363 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane
64− LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane
64+ LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane
6565 };
6666
6767 enum dc_link_spread {
drivers/gpu/drm/amd/display/dc/dc_types.h+1−0
@@ -597,6 +597,7 @@ enum dc_psr_state { · 596 unmodified lines
597597 PSR_STATE4b_FULL_FRAME,
598598 PSR_STATE4c_FULL_FRAME,
599599 PSR_STATE4_FULL_FRAME_POWERUP,
600+ PSR_STATE4_FULL_FRAME_HW_LOCK,
600601 PSR_STATE5,
601602 PSR_STATE5a,
602603 PSR_STATE5b,
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c+2−0
@@ -87,6 +87,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state) · 86 unmodified lines
8787 state = PSR_STATE4c_FULL_FRAME;
8888 else if (raw_state == 0x4E)
8989 state = PSR_STATE4_FULL_FRAME_POWERUP;
90+ else if (raw_state == 0x4F)
91+ state = PSR_STATE4_FULL_FRAME_HW_LOCK;
9092 else if (raw_state == 0x60)
9193 state = PSR_STATE_HWLOCK_MGR;
9294 else if (raw_state == 0x61)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c+12−8
@@ -37,14 +37,14 @@ · 36 unmodified lines
3737 #define CTX \
3838 oppn10->base.ctx
3939
40−
41−/************* FORMATTER ************/
42−
4340 /**
44− * set_truncation
41+ * opp1_set_truncation():
4542 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
4643 * 2) enable truncation
4744 * 3) HW remove 12bit FMT support for DCE11 power saving reason.
45+ *
46+ * @oppn10: output_pixel_processor struct instance for dcn10.
47+ * @params: pointer to bit_depth_reduction_params.
4848 */
4949 static void opp1_set_truncation(
5050 struct dcn10_opp *oppn10,
@@ -149,11 +149,12 @@ void opp1_program_bit_depth_reduction( · 98 unmodified lines
149149 }
150150
151151 /**
152− * set_pixel_encoding
153− *
154− * Set Pixel Encoding
152+ * opp1_set_pixel_encoding():
155153 * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
156154 * 1: YCbCr 4:2:2
155+ *
156+ * @oppn10: output_pixel_processor struct instance for dcn10.
157+ * @params: pointer to clamping_and_pixel_encoding_params.
157158 */
158159 static void opp1_set_pixel_encoding(
159160 struct dcn10_opp *oppn10,
@@ -180,13 +181,16 @@ static void opp1_set_pixel_encoding( · 20 unmodified lines
180181 }
181182
182183 /**
183− * Set Clamping
184+ * opp1_set_clamping():
184185 * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
185186 * 1 for 8 bpc
186187 * 2 for 10 bpc
187188 * 3 for 12 bpc
188189 * 7 for programable
189190 * 2) Enable clamp if Limited range requested
191+ *
192+ * @oppn10: output_pixel_processor struct instance for dcn10.
193+ * @params: pointer to clamping_and_pixel_encoding_params.
190194 */
191195 static void opp1_set_clamping(
192196 struct dcn10_opp *oppn10,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+36−21
@@ -42,11 +42,13 @@ · 41 unmodified lines
4242 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
4343
4444 /**
45−* apply_front_porch_workaround TODO FPGA still need?
46−*
47−* This is a workaround for a bug that has existed since R5xx and has not been
48−* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
49−*/
45+ * apply_front_porch_workaround() - This is a workaround for a bug that has
46+ * existed since R5xx and has not been fixed
47+ * keep Front porch at minimum 2 for Interlaced
48+ * mode or 1 for progressive.
49+ *
50+ * @timing: Timing parameters used to configure DCN blocks.
51+ */
5052 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
5153 {
5254 if (timing->flags.INTERLACE == 1) {
@@ -133,9 +135,20 @@ void optc1_setup_vertical_interrupt2( · 80 unmodified lines
133135 }
134136
135137 /**
136− * program_timing_generator used by mode timing set
137− * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
138− * Including SYNC. Call BIOS command table to program Timings.
138+ * optc1_program_timing() - used by mode timing set Program
139+ * CRTC Timing Registers - OTG_H_*,
140+ * OTG_V_*, Pixel repetition.
141+ * Including SYNC. Call BIOS command table to program Timings.
142+ *
143+ * @optc: timing_generator instance.
144+ * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
145+ * @vready_offset: Vready's starting position.
146+ * @vstartup_start: Vstartup period.
147+ * @vupdate_offset: Vupdate starting position.
148+ * @vupdate_width: Vupdate duration.
149+ * @signal: DC signal types.
150+ * @use_vbios: to program timings from BIOS command table.
151+ *
139152 */
140153 void optc1_program_timing(
141154 struct timing_generator *optc,
@@ -385,6 +398,9 @@ void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enab · 243 unmodified lines
385398 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
386399 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
387400 *
401+ * @optc: timing_generator instance.
402+ * @enable: Enable DRR double buffering control if true, disable otherwise.
403+ *
388404 * Options: any time, start of frame, dp start of frame (range timing)
389405 */
390406 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
@@ -397,8 +413,9 @@ void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) · 6 unmodified lines
397413 }
398414
399415 /**
400− * unblank_crtc
401− * Call ASIC Control Object to UnBlank CRTC.
416+ * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
417+ *
418+ * @optc: timing_generator instance.
402419 */
403420 static void optc1_unblank_crtc(struct timing_generator *optc)
404421 {
@@ -419,8 +436,9 @@ static void optc1_unblank_crtc(struct timing_generator *optc) · 14 unmodified lines
419436 }
420437
421438 /**
422− * blank_crtc
423− * Call ASIC Control Object to Blank CRTC.
439+ * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
440+ *
441+ * @optc: timing_generator instance.
424442 */
425443
426444 static void optc1_blank_crtc(struct timing_generator *optc)
@@ -493,8 +511,9 @@ void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) · 66 unmodified lines
493511 }
494512
495513 /**
496− * Enable CRTC
497− * Enable CRTC - call ASIC Control Object to enable Timing generator.
514+ * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
515+ *
516+ * @optc: timing_generator instance.
498517 */
499518 static bool optc1_enable_crtc(struct timing_generator *optc)
500519 {
@@ -890,15 +909,11 @@ static void optc1_program_manual_trigger(struct timing_generator *optc) · 389 unmodified lines
890909 MANUAL_FLOW_CONTROL, 0);
891910 }
892911
893−
894912 /**
895− *****************************************************************************
896− * Function: set_drr
913+ * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
897914 *
898− * @brief
899− * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
900− *
901− *****************************************************************************
915+ * @optc: timing_generator instance.
916+ * @params: parameters used for Dynamic Refresh Rate.
902917 */
903918 void optc1_set_drr(
904919 struct timing_generator *optc,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+0−11
@@ -1741,17 +1741,6 @@ static void dcn20_program_pipe( · 1740 unmodified lines
17411741
17421742 if (hws->funcs.setup_vupdate_interrupt)
17431743 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1744−
1745− if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
1746− unsigned int k1_div, k2_div;
1747−
1748− hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
1749−
1750− dc->res_pool->dccg->funcs->set_pixel_rate_div(
1751− dc->res_pool->dccg,
1752− pipe_ctx->stream_res.tg->inst,
1753− k1_div, k2_div);
1754− }
17551744 }
17561745
17571746 if (pipe_ctx->update_flags.bits.odm)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c+3−0
@@ -279,6 +279,9 @@ static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, in · 278 unmodified lines
279279 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
280280 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
281281 *
282+ * @optc: timing_generator instance.
283+ * @enable: Enable DRR double buffering control if true, disable otherwise.
284+ *
282285 * Options: any time, start of frame, dp start of frame (range timing)
283286 */
284287 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+1−0
@@ -2328,6 +2328,7 @@ static bool dcn30_resource_construct( · 2327 unmodified lines
23282328 dc->caps.color.mpc.ocsc = 1;
23292329
23302330 dc->caps.dp_hdmi21_pcon_support = true;
2331+ dc->caps.max_v_total = (1 << 15) - 1;
23312332
23322333 /* read VBIOS LTTPR caps */
23332334 {
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+1−0
@@ -1227,6 +1227,7 @@ static bool dcn302_resource_construct( · 1226 unmodified lines
12271227 dc->caps.force_dp_tps4_for_cp2520 = true;
12281228 dc->caps.extended_aux_timeout_support = true;
12291229 dc->caps.dmcub_support = true;
1230+ dc->caps.max_v_total = (1 << 15) - 1;
12301231
12311232 /* Color pipeline capabilities */
12321233 dc->caps.color.dpp.dcn_arch = 1;
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+1−0
@@ -1152,6 +1152,7 @@ static bool dcn303_resource_construct( · 1151 unmodified lines
11521152 dc->caps.force_dp_tps4_for_cp2520 = true;
11531153 dc->caps.extended_aux_timeout_support = true;
11541154 dc->caps.dmcub_support = true;
1155+ dc->caps.max_v_total = (1 << 15) - 1;
11551156
11561157 /* Color pipeline capabilities */
11571158 dc->caps.color.dpp.dcn_arch = 1;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c+8−0
@@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) · 46 unmodified lines
4747 {
4848 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
4949
50+ if (dccg->dpp_clock_gated[dpp_inst]) {
51+ /*
52+ * Do not update the DPPCLK DTO if the clock is stopped.
53+ * It is treated the same as if the pipe itself were in PG.
54+ */
55+ return;
56+ }
57+
5058 if (dccg->ref_dppclk && req_dppclk) {
5159 int ref_dppclk = dccg->ref_dppclk;
5260 int modulo, phase;
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c+5−0
@@ -332,6 +332,9 @@ static void dccg314_dpp_root_clock_control( · 331 unmodified lines
332332 {
333333 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
334334
335+ if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
336+ return;
337+
335338 if (clock_on) {
336339 /* turn off the DTO and leave phase/modulo at max */
337340 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
@@ -345,6 +348,8 @@ static void dccg314_dpp_root_clock_control( · 7 unmodified lines
345348 DPPCLK0_DTO_PHASE, 0,
346349 DPPCLK0_DTO_MODULO, 1);
347350 }
351+
352+ dccg->dpp_clock_gated[dpp_inst] = !clock_on;
348353 }
349354
350355 static const struct dccg_funcs dccg314_funcs = {
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c+2−7
@@ -337,14 +337,13 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) · 336 unmodified lines
337337 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
338338 }
339339
340−unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
340+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
341341 {
342342 struct dc_stream_state *stream = pipe_ctx->stream;
343− unsigned int odm_combine_factor = 0;
344343 bool two_pix_per_container = false;
345344
346345 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
347− odm_combine_factor = get_odm_config(pipe_ctx, NULL);
346+ get_odm_config(pipe_ctx, NULL);
348347
349348 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
350349 *k1_div = PIXEL_RATE_DIV_BY_1;
@@ -362,15 +361,11 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig · 11 unmodified lines
362361 } else {
363362 *k1_div = PIXEL_RATE_DIV_BY_1;
364363 *k2_div = PIXEL_RATE_DIV_BY_4;
365− if (odm_combine_factor == 2)
366− *k2_div = PIXEL_RATE_DIV_BY_2;
367364 }
368365 }
369366
370367 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
371368 ASSERT(false);
372−
373− return odm_combine_factor;
374369 }
375370
376371 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h+1−1
@@ -37,7 +37,7 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po · 36 unmodified lines
3737
3838 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
3939
40−unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
40+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
4141
4242 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
4343
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c+25−2
@@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = { · 873 unmodified lines
874874 .force_abm_enable = false,
875875 .timing_trace = false,
876876 .clock_trace = true,
877− .disable_dpp_power_gate = true,
878− .disable_hubp_power_gate = true,
877+ .disable_dpp_power_gate = false,
878+ .disable_hubp_power_gate = false,
879879 .disable_pplib_clock_request = false,
880880 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
881881 .force_single_disp_pipe_split = false,
@@ -904,6 +904,22 @@ static const struct dc_debug_options debug_defaults_drv = { · 22 unmodified lines
904904 .afmt = true,
905905 }
906906 },
907+
908+ .root_clock_optimization = {
909+ .bits = {
910+ .dpp = true,
911+ .dsc = false,
912+ .hdmistream = false,
913+ .hdmichar = false,
914+ .dpstream = false,
915+ .symclk32_se = false,
916+ .symclk32_le = false,
917+ .symclk_fe = false,
918+ .physymclk = false,
919+ .dpiasymclk = false,
920+ }
921+ },
922+
907923 .seamless_boot_odm_combine = true
908924 };
909925
@@ -1867,6 +1883,13 @@ static bool dcn314_resource_construct( · 957 unmodified lines
18671883 /* Use pipe context based otg sync logic */
18681884 dc->config.use_pipe_ctx_sync_logic = true;
18691885
1886+ /* Disable pipe power gating when unsupported */
1887+ if (ctx->asic_id.hw_internal_rev == 0x01 ||
1888+ ctx->asic_id.hw_internal_rev == 0x80) {
1889+ dc->debug.disable_dpp_power_gate = true;
1890+ dc->debug.disable_hubp_power_gate = true;
1891+ }
1892+
18701893 /* read VBIOS LTTPR caps */
18711894 {
18721895 if (ctx->dc_bios->funcs->get_lttpr_caps) {
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c+1−0
@@ -1742,6 +1742,7 @@ static int dcn315_populate_dml_pipes_from_context( · 1741 unmodified lines
17421742 /* Do not use asymetric crb if not enough for pstate support */
17431743 if (remaining_det_segs < 0) {
17441744 pipes[pipe_cnt].pipe.src.det_size_override = 0;
1745+ pipe_cnt++;
17451746 continue;
17461747 }
17471748
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c+4−7
@@ -1141,10 +1141,9 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * · 1140 unmodified lines
11411141 }
11421142 }
11431143
1144−unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1144+void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
11451145 {
11461146 struct dc_stream_state *stream = pipe_ctx->stream;
1147− unsigned int odm_combine_factor = 0;
11481147 bool two_pix_per_container = false;
11491148
11501149 // For phantom pipes, use the same programming as the main pipes
@@ -1152,7 +1151,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign · 1 unmodified line
11521151 stream = pipe_ctx->stream->mall_stream_config.paired_stream;
11531152 }
11541153 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1155− odm_combine_factor = get_odm_config(pipe_ctx, NULL);
11561154
11571155 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
11581156 *k1_div = PIXEL_RATE_DIV_BY_1;
@@ -1170,15 +1168,13 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign · 11 unmodified lines
11701168 } else {
11711169 *k1_div = PIXEL_RATE_DIV_BY_1;
11721170 *k2_div = PIXEL_RATE_DIV_BY_4;
1173− if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1171+ if (dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
11741172 *k2_div = PIXEL_RATE_DIV_BY_2;
11751173 }
11761174 }
11771175
11781176 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
11791177 ASSERT(false);
1180−
1181− return odm_combine_factor;
11821178 }
11831179
11841180 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
@@ -1211,7 +1207,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_ · 26 unmodified lines
12111207 if (pipe->top_pipe || pipe->prev_odm_pipe)
12121208 continue;
12131209
1214− if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
1210+ if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1211+ && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
12151212 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
12161213 reset_sync_context_for_pipe(dc, context, i);
12171214 otg_disabled[i] = true;
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h+1−1
@@ -71,7 +71,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context); · 70 unmodified lines
7171
7272 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
7373
74−unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
74+void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
7575
7676 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
7777
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c+5−2
@@ -106,8 +106,11 @@ void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool man · 105 unmodified lines
106106 OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
107107 }
108108 /**
109− * Enable CRTC
110− * Enable CRTC - call ASIC Control Object to enable Timing generator.
109+ * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
110+ *
111+ * @optc: timing_generator instance.
112+ *
113+ * Return: If CRTC is enabled, return true.
111114 */
112115 static bool optc32_enable_crtc(struct timing_generator *optc)
113116 {
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+2−1
@@ -728,7 +728,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 727 unmodified lines
728728 .fpo_vactive_margin_us = 2000, // 2000us
729729 .disable_fpo_vactive = false,
730730 .disable_boot_optimizations = false,
731− .disable_subvp_high_refresh = true,
731+ .disable_subvp_high_refresh = false,
732732 .disable_dp_plus_plus_wa = true,
733733 .fpo_vactive_min_active_margin_us = 200,
734734 .fpo_vactive_max_blank_us = 1000,
@@ -2175,6 +2175,7 @@ static bool dcn32_resource_construct( · 1440 unmodified lines
21752175 dc->caps.extended_aux_timeout_support = true;
21762176 dc->caps.dmcub_support = true;
21772177 dc->caps.seamless_odm = true;
2178+ dc->caps.max_v_total = (1 << 15) - 1;
21782179
21792180 /* Color pipeline capabilities */
21802181 dc->caps.color.dpp.dcn_arch = 1;
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h+4−0
@@ -169,6 +169,10 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *conte · 168 unmodified lines
169169
170170 bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);
171171
172+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);
173+
174+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);
175+
172176 /* definitions for run time init of reg offsets */
173177
174178 /* CLK SRC */
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c+104−43
@@ -255,8 +255,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 254 unmodified lines
255255 return psr_capable;
256256 }
257257
258−#define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
259−
260258 /**
261259 * dcn32_determine_det_override(): Determine DET allocation for each pipe
262260 *
@@ -267,6 +265,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 4 unmodified lines
267265 * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
268266 * number of DET for that given plane will be split among the pipes driving that plane.
269267 *
268+ *
270269 * High level algorithm:
271270 * 1. Split total DET among number of streams
272271 * 2. For each stream, split DET among the planes
@@ -274,18 +273,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 1 unmodified line
274273 * among those pipes.
275274 * 4. Assign the DET override to the DML pipes.
276275 *
277− * Special cases:
278− *
279− * For two displays that have a large difference in pixel rate, we may experience
280− * underflow on the larger display when we divide the DET equally. For this, we
281− * will implement a modified algorithm to assign more DET to larger display.
282− *
283− * 1. Calculate difference in pixel rates ( multiplier ) between two displays
284− * 2. If the multiplier exceeds DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER, then
285− * implement the modified DET override algorithm.
286− * 3. Assign smaller DET size for lower pixel display and higher DET size for
287− * higher pixel display
288− *
289276 * @dc: Current DC state
290277 * @context: New DC state to be programmed
291278 * @pipes: Array of DML pipes
@@ -303,31 +290,10 @@ void dcn32_determine_det_override(struct dc *dc, · 11 unmodified lines
303290 struct dc_plane_state *current_plane = NULL;
304291 uint8_t stream_count = 0;
305292
306− int phy_pix_clk_mult, lower_mode_stream_index;
307− int phy_pix_clk[MAX_PIPES] = {0};
308− bool use_new_det_override_algorithm = false;
309−
310293 for (i = 0; i < context->stream_count; i++) {
311294 /* Don't count SubVP streams for DET allocation */
312− if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {
313− phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
295+ if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM)
314296 stream_count++;
315− }
316− }
317−
318− /* Check for special case with two displays, one with much higher pixel rate */
319− if (stream_count == 2) {
320− ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
321− if (phy_pix_clk[0] < phy_pix_clk[1]) {
322− lower_mode_stream_index = 0;
323− phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
324− } else {
325− lower_mode_stream_index = 1;
326− phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
327− }
328−
329− if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
330− use_new_det_override_algorithm = true;
331297 }
332298
333299 if (stream_count > 0) {
@@ -336,13 +302,6 @@ void dcn32_determine_det_override(struct dc *dc, · 2 unmodified lines
336302 if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM)
337303 continue;
338304
339− if (use_new_det_override_algorithm) {
340− if (i == lower_mode_stream_index)
341− stream_segments = 4;
342− else
343− stream_segments = 14;
344− }
345−
346305 if (context->stream_status[i].plane_count > 0)
347306 plane_segments = stream_segments / context->stream_status[i].plane_count;
348307 else
@@ -660,3 +619,105 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int widt · 311 unmodified lines
660619
661620 return is_native_scaling;
662621 }
622+
623+/**
624+ * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible
625+ *
626+ * @dc: Current DC state
627+ * @context: New DC state to be programmed
628+ *
629+ * SubVP + DRR is admissible under the following conditions:
630+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
631+ * - One display is SubVP
632+ * - Other display must have Freesync enabled
633+ * - The potential DRR display must not be PSR capable
634+ *
635+ * Return: True if admissible, false otherwise
636+ */
637+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
638+{
639+ bool result = false;
640+ uint32_t i;
641+ uint8_t subvp_count = 0;
642+ uint8_t non_subvp_pipes = 0;
643+ bool drr_pipe_found = false;
644+ bool drr_psr_capable = false;
645+
646+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
647+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
648+
649+ if (!pipe->stream)
650+ continue;
651+
652+ if (pipe->plane_state && !pipe->top_pipe) {
653+ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
654+ subvp_count++;
655+ if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
656+ non_subvp_pipes++;
657+ drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));
658+ if (pipe->stream->ignore_msa_timing_param &&
659+ (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
660+ drr_pipe_found = true;
661+ }
662+ }
663+ }
664+ }
665+
666+ if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable)
667+ result = true;
668+
669+ return result;
670+}
671+
672+/**
673+ * dcn32_subvp_vblank_admissable() - Determine if SubVP + Vblank config is admissible
674+ *
675+ * @dc: Current DC state
676+ * @context: New DC state to be programmed
677+ * @vlevel: Voltage level calculated by DML
678+ *
679+ * SubVP + Vblank is admissible under the following conditions:
680+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
681+ * - One display is SubVP
682+ * - Other display must not have Freesync capability
683+ * - DML must have output DRAM clock change support as SubVP + Vblank
684+ * - The potential vblank display must not be PSR capable
685+ *
686+ * Return: True if admissible, false otherwise
687+ */
688+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)
689+{
690+ bool result = false;
691+ uint32_t i;
692+ uint8_t subvp_count = 0;
693+ uint8_t non_subvp_pipes = 0;
694+ bool drr_pipe_found = false;
695+ struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
696+ bool vblank_psr_capable = false;
697+
698+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
699+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
700+
701+ if (!pipe->stream)
702+ continue;
703+
704+ if (pipe->plane_state && !pipe->top_pipe) {
705+ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
706+ subvp_count++;
707+ if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
708+ non_subvp_pipes++;
709+ vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));
710+ if (pipe->stream->ignore_msa_timing_param &&
711+ (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
712+ drr_pipe_found = true;
713+ }
714+ }
715+ }
716+ }
717+
718+ if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
719+ vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
720+ result = true;
721+
722+ return result;
723+}
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c+2−1
@@ -727,7 +727,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 726 unmodified lines
727727 .fpo_vactive_margin_us = 2000, // 2000us
728728 .disable_fpo_vactive = false,
729729 .disable_boot_optimizations = false,
730− .disable_subvp_high_refresh = true,
730+ .disable_subvp_high_refresh = false,
731731 .fpo_vactive_min_active_margin_us = 200,
732732 .fpo_vactive_max_blank_us = 1000,
733733 };
@@ -1718,6 +1718,7 @@ static bool dcn321_resource_construct( · 984 unmodified lines
17181718 dc->caps.edp_dsc_support = true;
17191719 dc->caps.extended_aux_timeout_support = true;
17201720 dc->caps.dmcub_support = true;
1721+ dc->caps.max_v_total = (1 << 15) - 1;
17211722
17221723 /* Color pipeline capabilities */
17231724 dc->caps.color.dpp.dcn_arch = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c+59−0
@@ -5557,6 +5557,65 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ · 5556 unmodified lines
55575557 }
55585558 }
55595559 }
5560+ for (i = v->soc.num_states; i >= 0; i--) {
5561+ for (j = 0; j < 2; j++) {
5562+ enum dm_validation_status status = DML_VALIDATION_OK;
5563+
5564+ if (!v->ScaleRatioAndTapsSupport) {
5565+ status = DML_FAIL_SCALE_RATIO_TAP;
5566+ } else if (!v->SourceFormatPixelAndScanSupport) {
5567+ status = DML_FAIL_SOURCE_PIXEL_FORMAT;
5568+ } else if (!v->ViewportSizeSupport[i][j]) {
5569+ status = DML_FAIL_VIEWPORT_SIZE;
5570+ } else if (P2IWith420) {
5571+ status = DML_FAIL_P2I_WITH_420;
5572+ } else if (DSCOnlyIfNecessaryWithBPP) {
5573+ status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
5574+ } else if (DSC422NativeNotSupported) {
5575+ status = DML_FAIL_NOT_DSC422_NATIVE;
5576+ } else if (!v->ODMCombine4To1SupportCheckOK[i]) {
5577+ status = DML_FAIL_ODM_COMBINE4TO1;
5578+ } else if (v->NotEnoughDSCUnits[i]) {
5579+ status = DML_FAIL_NOT_ENOUGH_DSC;
5580+ } else if (!v->ROBSupport[i][j]) {
5581+ status = DML_FAIL_REORDERING_BUFFER;
5582+ } else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
5583+ status = DML_FAIL_DISPCLK_DPPCLK;
5584+ } else if (!v->TotalAvailablePipesSupport[i][j]) {
5585+ status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
5586+ } else if (!EnoughWritebackUnits) {
5587+ status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
5588+ } else if (!v->WritebackLatencySupport) {
5589+ status = DML_FAIL_WRITEBACK_LATENCY;
5590+ } else if (!v->WritebackScaleRatioAndTapsSupport) {
5591+ status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
5592+ } else if (!v->CursorSupport) {
5593+ status = DML_FAIL_CURSOR_SUPPORT;
5594+ } else if (!v->PitchSupport) {
5595+ status = DML_FAIL_PITCH_SUPPORT;
5596+ } else if (ViewportExceedsSurface) {
5597+ status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
5598+ } else if (!v->PrefetchSupported[i][j]) {
5599+ status = DML_FAIL_PREFETCH_SUPPORT;
5600+ } else if (!v->DynamicMetadataSupported[i][j]) {
5601+ status = DML_FAIL_DYNAMIC_METADATA;
5602+ } else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) {
5603+ status = DML_FAIL_TOTAL_V_ACTIVE_BW;
5604+ } else if (!v->VRatioInPrefetchSupported[i][j]) {
5605+ status = DML_FAIL_V_RATIO_PREFETCH;
5606+ } else if (!v->PTEBufferSizeNotExceeded[i][j]) {
5607+ status = DML_FAIL_PTE_BUFFER_SIZE;
5608+ } else if (v->NonsupportedDSCInputBPC) {
5609+ status = DML_FAIL_DSC_INPUT_BPC;
5610+ } else if ((v->HostVMEnable
5611+ && !v->ImmediateFlipSupportedForState[i][j])) {
5612+ status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
5613+ } else if (FMTBufferExceeded) {
5614+ status = DML_FAIL_FMT_BUFFER_EXCEEDED;
5615+ }
5616+ mode_lib->vba.ValidationStatus[i] = status;
5617+ }
5618+ }
55605619
55615620 {
55625621 unsigned int MaximumMPCCombine = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+110−68
@@ -679,7 +679,6 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, · 678 unmodified lines
679679 unsigned int max_frame_time = 0;
680680 bool valid_assignment_found = false;
681681 unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
682− bool current_assignment_freesync = false;
683682 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
684683
685684 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
@@ -720,19 +719,10 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, · 34 unmodified lines
720719 struct dc_stream_state *stream = pipe->stream;
721720 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
722721 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
723− if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
722+ if (frame_us > max_frame_time) {
724723 *index = i;
725724 max_frame_time = frame_us;
726725 valid_assignment_found = true;
727− current_assignment_freesync = false;
728− /* For the 2-Freesync display case, still choose the one with the
729− * longest frame time
730− */
731− } else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
732− (current_assignment_freesync && frame_us > max_frame_time))) {
733− *index = i;
734− valid_assignment_found = true;
735− current_assignment_freesync = true;
736726 }
737727 }
738728 }
@@ -864,10 +854,9 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) · 125 unmodified lines
864854 }
865855
866856 /**
867− * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable
857+ * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
868858 * @dc: current dc state
869859 * @context: new dc state
870− * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
871860 *
872861 * High level algorithm:
873862 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
@@ -878,11 +867,12 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) · 4 unmodified lines
878867 *
879868 * Return: True if the SubVP + DRR config is schedulable, false otherwise
880869 */
881−static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
870+static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
882871 {
883872 bool schedulable = false;
884873 uint32_t i;
885874 struct pipe_ctx *pipe = NULL;
875+ struct pipe_ctx *drr_pipe = NULL;
886876 struct dc_crtc_timing *main_timing = NULL;
887877 struct dc_crtc_timing *phantom_timing = NULL;
888878 struct dc_crtc_timing *drr_timing = NULL;
@@ -908,6 +898,19 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struc · 19 unmodified lines
908898 break;
909899 }
910900
901+ // Find the DRR pipe
902+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
903+ drr_pipe = &context->res_ctx.pipe_ctx[i];
904+
905+ // We check for master pipe only
906+ if (!drr_pipe->stream || !drr_pipe->plane_state || drr_pipe->top_pipe || drr_pipe->prev_odm_pipe)
907+ continue;
908+
909+ if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
910+ (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
911+ break;
912+ }
913+
911914 main_timing = &pipe->stream->timing;
912915 phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
913916 drr_timing = &drr_pipe->stream->timing;
@@ -993,13 +996,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) · 79 unmodified lines
993996 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
994997 subvp_pipe = pipe;
995998 }
996− // Use ignore_msa_timing_param and VRR active, or Freesync flag to identify as DRR On
997− if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param &&
998− (context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync ||
999− context->res_ctx.pipe_ctx[vblank_index].stream->vrr_active_variable)) {
1000− // SUBVP + DRR case -- only allowed if run through DRR validation path
1001− schedulable = false;
1002− } else if (found) {
999+ if (found) {
10031000 main_timing = &subvp_pipe->stream->timing;
10041001 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
10051002 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
@@ -1028,6 +1025,53 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) · 22 unmodified lines
10281025 return schedulable;
10291026 }
10301027
1028+/**
1029+ * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
1030+ *
1031+ * @dc: Current DC state
1032+ * @context: New DC state to be programmed
1033+ *
1034+ * SubVP + SubVP is admissible under the following conditions:
1035+ * - All SubVP pipes are < 120Hz OR
1036+ * - All SubVP pipes are >= 120hz
1037+ *
1038+ * Return: True if admissible, false otherwise
1039+ */
1040+static bool subvp_subvp_admissable(struct dc *dc,
1041+ struct dc_state *context)
1042+{
1043+ bool result = false;
1044+ uint32_t i;
1045+ uint8_t subvp_count = 0;
1046+ uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
1047+ uint32_t refresh_rate = 0;
1048+
1049+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
1050+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1051+
1052+ if (!pipe->stream)
1053+ continue;
1054+
1055+ if (pipe->plane_state && !pipe->top_pipe &&
1056+ pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1057+ refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
1058+ pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
1059+ / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
1060+ if (refresh_rate < min_refresh)
1061+ min_refresh = refresh_rate;
1062+ if (refresh_rate > max_refresh)
1063+ max_refresh = refresh_rate;
1064+ subvp_count++;
1065+ }
1066+ }
1067+
1068+ if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
1069+ (min_refresh >= 120 && max_refresh >= 120)))
1070+ result = true;
1071+
1072+ return result;
1073+}
1074+
10311075 /**
10321076 * subvp_validate_static_schedulability - Check which SubVP case is calculated
10331077 * and handle static analysis based on the case.
@@ -1046,11 +1090,12 @@ static bool subvp_validate_static_schedulability(struct dc *dc, · 12 unmodified lines
10461090 struct dc_state *context,
10471091 int vlevel)
10481092 {
1049− bool schedulable = true; // true by default for single display case
1093+ bool schedulable = false;
10501094 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
10511095 uint32_t i, pipe_idx;
10521096 uint8_t subvp_count = 0;
10531097 uint8_t vactive_count = 0;
1098+ uint8_t non_subvp_pipes = 0;
10541099
10551100 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
10561101 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -1058,14 +1103,18 @@ static bool subvp_validate_static_schedulability(struct dc *dc, · 1 unmodified line
10581103 if (!pipe->stream)
10591104 continue;
10601105
1061− if (pipe->plane_state && !pipe->top_pipe &&
1062− pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1063− subvp_count++;
1106+ if (pipe->plane_state && !pipe->top_pipe) {
1107+ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1108+ subvp_count++;
1109+ if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1110+ non_subvp_pipes++;
1111+ }
1112+ }
10641113
10651114 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
10661115 // switching (SubVP + VACTIVE unsupported). In situations where we force
10671116 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1068− if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
1117+ if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
10691118 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
10701119 vactive_count++;
10711120 }
@@ -1074,13 +1123,14 @@ static bool subvp_validate_static_schedulability(struct dc *dc, · 2 unmodified lines
10741123
10751124 if (subvp_count == 2) {
10761125 // Static schedulability check for SubVP + SubVP case
1077− schedulable = subvp_subvp_schedulable(dc, context);
1078− } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
1079− // Static schedulability check for SubVP + VBLANK case. Also handle the case where
1080− // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
1081− if (vactive_count > 0)
1082− schedulable = false;
1083− else
1126+ schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
1127+ } else if (subvp_count == 1 && non_subvp_pipes == 0) {
1128+ // Single SubVP configs will be supported by default as long as it's suppported by DML
1129+ schedulable = true;
1130+ } else if (subvp_count == 1 && non_subvp_pipes == 1) {
1131+ if (dcn32_subvp_drr_admissable(dc, context))
1132+ schedulable = subvp_drr_schedulable(dc, context);
1133+ else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
10841134 schedulable = subvp_vblank_schedulable(dc, context);
10851135 } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
10861136 vactive_count > 0) {
@@ -1104,10 +1154,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, · 17 unmodified lines
11041154 unsigned int dc_pipe_idx = 0;
11051155 int i = 0;
11061156 bool found_supported_config = false;
1107− struct pipe_ctx *pipe = NULL;
1108− uint32_t non_subvp_pipes = 0;
1109− bool drr_pipe_found = false;
1110− uint32_t drr_pipe_index = 0;
11111157
11121158 dc_assert_fp_enabled();
11131159
@@ -1197,31 +1243,12 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, · 83 unmodified lines
11971243 }
11981244 }
11991245
1200− if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1201− vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
1202− && subvp_validate_static_schedulability(dc, context, *vlevel)) {
1246+ if (*vlevel < context->bw_ctx.dml.soc.num_states
1247+ && subvp_validate_static_schedulability(dc, context, *vlevel))
12031248 found_supported_config = true;
1204− } else if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1205− /* Case where 1 SubVP is added, and DML reports MCLK unsupported or DRR is allowed.
1206− * This handles the case for SubVP + DRR, where the DRR display does not support MCLK
1207− * switch at it's native refresh rate / timing, or DRR is allowed for the non-subvp
1208− * display.
1209− */
1210− for (i = 0; i < dc->res_pool->pipe_count; i++) {
1211− pipe = &context->res_ctx.pipe_ctx[i];
1212− if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
1213− pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1214− non_subvp_pipes++;
1215− // Use ignore_msa_timing_param flag to identify as DRR
1216− if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) {
1217− drr_pipe_found = true;
1218− drr_pipe_index = i;
1219− }
1220− }
1221− }
1222− // If there is only 1 remaining non SubVP pipe that is DRR, check static
1223− // schedulability for SubVP + DRR.
1224− if (non_subvp_pipes == 1 && drr_pipe_found) {
1249+ if (found_supported_config) {
1250+ // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1251+ if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
12251252 /* find lowest vlevel that supports the config */
12261253 for (i = *vlevel; i >= 0; i--) {
12271254 if (vba->ModeSupport[i][vba->maxMpcComb]) {
@@ -1230,9 +1257,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, · 2 unmodified lines
12301257 break;
12311258 }
12321259 }
1233−
1234− found_supported_config = subvp_drr_schedulable(dc, context,
1235− &context->res_ctx.pipe_ctx[drr_pipe_index]);
12361260 }
12371261 }
12381262 }
@@ -2882,16 +2906,34 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context · 1643 unmodified lines
28822906 {
28832907 bool allow = false;
28842908 uint32_t refresh_rate = 0;
2885− uint32_t min_refresh = subvp_high_refresh_list.min_refresh;
2886− uint32_t max_refresh = subvp_high_refresh_list.max_refresh;
2909+ uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
2910+ uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
2911+ uint32_t min_refresh = subvp_max_refresh;
28872912 uint32_t i;
28882913
2889− if (!dc->debug.disable_subvp_high_refresh && pipe->stream &&
2914+ /* Only allow SubVP on high refresh displays if all connected displays
2915+ * are considered "high refresh" (i.e. >= 120hz). We do not want to
2916+ * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
2917+ */
2918+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
2919+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2920+
2921+ if (!pipe_ctx->stream)
2922+ continue;
2923+ refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
2924+ pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
2925+ / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
2926+
2927+ if (refresh_rate < min_refresh)
2928+ min_refresh = refresh_rate;
2929+ }
2930+
2931+ if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
28902932 pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
28912933 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
28922934 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
28932935 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
2894− if (refresh_rate >= min_refresh && refresh_rate <= max_refresh) {
2936+ if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
28952937 for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
28962938 uint32_t width = subvp_high_refresh_list.res[i].width;
28972939 uint32_t height = subvp_high_refresh_list.res[i].height;
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h+8−0
@@ -190,6 +190,14 @@ enum dm_validation_status { · 189 unmodified lines
190190 DML_FAIL_DSC_INPUT_BPC,
191191 DML_FAIL_PREFETCH_SUPPORT,
192192 DML_FAIL_V_RATIO_PREFETCH,
193+ DML_FAIL_P2I_WITH_420,
194+ DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP,
195+ DML_FAIL_NOT_DSC422_NATIVE,
196+ DML_FAIL_ODM_COMBINE4TO1,
197+ DML_FAIL_ENOUGH_WRITEBACK_UNITS,
198+ DML_FAIL_VIEWPORT_EXCEEDS_SURFACE,
199+ DML_FAIL_DYNAMIC_METADATA,
200+ DML_FAIL_FMT_BUFFER_EXCEEDED,
193201 };
194202
195203 enum writeback_config {
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h+1−0
@@ -68,6 +68,7 @@ struct dccg { · 67 unmodified lines
6868 const struct dccg_funcs *funcs;
6969 int pipe_dppclk_khz[MAX_PIPES];
7070 int ref_dppclk;
71+ bool dpp_clock_gated[MAX_PIPES];
7172 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
7273 //int audio_dtbclk_khz;/* TODO needs to be removed */
7374 //int ref_dtbclk_khz;/* TODO needs to be removed */
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+32−0
@@ -114,6 +114,26 @@ struct update_visual_confirm_params { · 113 unmodified lines
114114 int mpcc_id;
115115 };
116116
117+struct power_on_mpc_mem_pwr_params {
118+ struct mpc *mpc;
119+ int mpcc_id;
120+ bool power_on;
121+};
122+
123+struct set_output_csc_params {
124+ struct mpc *mpc;
125+ int opp_id;
126+ const uint16_t *regval;
127+ enum mpc_output_csc_mode ocsc_mode;
128+};
129+
130+struct set_ocsc_default_params {
131+ struct mpc *mpc;
132+ int opp_id;
133+ enum dc_color_space color_space;
134+ enum mpc_output_csc_mode ocsc_mode;
135+};
136+
117137 union block_sequence_params {
118138 struct update_plane_addr_params update_plane_addr_params;
119139 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;
@@ -128,6 +148,9 @@ union block_sequence_params { · 8 unmodified lines
128148 struct program_bias_and_scale_params program_bias_and_scale_params;
129149 struct set_output_transfer_func_params set_output_transfer_func_params;
130150 struct update_visual_confirm_params update_visual_confirm_params;
151+ struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params;
152+ struct set_output_csc_params set_output_csc_params;
153+ struct set_ocsc_default_params set_ocsc_default_params;
131154 };
132155
133156 enum block_sequence_func {
@@ -144,6 +167,9 @@ enum block_sequence_func { · 10 unmodified lines
144167 DPP_PROGRAM_BIAS_AND_SCALE,
145168 DPP_SET_OUTPUT_TRANSFER_FUNC,
146169 MPC_UPDATE_VISUAL_CONFIRM,
170+ MPC_POWER_ON_MPC_MEM_PWR,
171+ MPC_SET_OUTPUT_CSC,
172+ MPC_SET_OCSC_DEFAULT,
147173 };
148174
149175 struct block_sequence {
@@ -439,4 +465,10 @@ void hwss_setup_dpp(union block_sequence_params *params); · 289 unmodified lines
439465
440466 void hwss_program_bias_and_scale(union block_sequence_params *params);
441467
468+void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params);
469+
470+void hwss_set_output_csc(union block_sequence_params *params);
471+
472+void hwss_set_ocsc_default(union block_sequence_params *params);
473+
442474 #endif /* __DC_HW_SEQUENCER_H__ */
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h+1−1
@@ -156,7 +156,7 @@ struct hwseq_private_funcs { · 155 unmodified lines
156156 void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
157157 void (*update_force_pstate)(struct dc *dc, struct dc_state *context);
158158 void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
159− unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
159+ void (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
160160 unsigned int *k1_div,
161161 unsigned int *k2_div);
162162 void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
drivers/gpu/drm/amd/display/dc/link/link_detection.c+5−0
@@ -984,6 +984,11 @@ static bool detect_link_and_local_sink(struct dc_link *link, · 983 unmodified lines
984984 (link->dpcd_caps.dongle_type !=
985985 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
986986 converter_disable_audio = true;
987+
988+ /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
989+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
990+ link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
991+ link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
987992 break;
988993 }
989994
drivers/gpu/drm/amd/display/modules/freesync/freesync.c+9−2
@@ -1,5 +1,5 @@
11 /*
2− * Copyright 2016 Advanced Micro Devices, Inc.
2+ * Copyright 2016-2023 Advanced Micro Devices, Inc.
33 *
44 * Permission is hereby granted, free of charge, to any person obtaining a
55 * copy of this software and associated documentation files (the "Software"),
@@ -989,6 +989,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, · 983 unmodified lines
989989 unsigned int refresh_range = 0;
990990 unsigned long long min_refresh_in_uhz = 0;
991991 unsigned long long max_refresh_in_uhz = 0;
992+ unsigned long long min_hardware_refresh_in_uhz = 0;
992993
993994 if (mod_freesync == NULL)
994995 return;
@@ -999,7 +1000,13 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, · 4 unmodified lines
9991000 nominal_field_rate_in_uhz =
10001001 mod_freesync_calc_nominal_field_rate(stream);
10011002
1002− min_refresh_in_uhz = in_config->min_refresh_in_uhz;
1003+ if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
1004+ min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
1005+ (stream->timing.h_total * stream->ctx->dc->caps.max_v_total));
1006+ }
1007+ /* Limit minimum refresh rate to what can be supported by hardware */
1008+ min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
1009+ min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
10031010 max_refresh_in_uhz = in_config->max_refresh_in_uhz;
10041011
10051012 /* Full range may be larger than current video timing, so cap at nominal */
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+14−4
@@ -431,7 +431,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) · 430 unmodified lines
431431 {
432432 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
433433 int index, ret;
434− I2cControllerConfig_t *table_member;
434+ PPTable_beige_goby_t *ppt_beige_goby;
435+ PPTable_t *ppt;
436+
437+ if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
438+ ppt_beige_goby = smu->smu_table.driver_pptable;
439+ else
440+ ppt = smu->smu_table.driver_pptable;
435441
436442 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
437443 smc_dpm_info);
@@ -440,9 +446,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) · 2 unmodified lines
440446 (uint8_t **)&smc_dpm_table);
441447 if (ret)
442448 return ret;
443− GET_PPTABLE_MEMBER(I2cControllers, &table_member);
444− memcpy(table_member, smc_dpm_table->I2cControllers,
445− sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
449+
450+ if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
451+ smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
452+ smc_dpm_table, I2cControllers);
453+ else
454+ smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
455+ smc_dpm_table, I2cControllers);
446456
447457 return 0;
448458 }
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+1−2
@@ -46,7 +46,6 @@ · 45 unmodified lines
4646 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
4747 #include "smu_cmn.h"
4848 #include "amdgpu_ras.h"
49−#include "umc_v8_10.h"
5049
5150 /*
5251 * DO NOT use these for err/warn/info/debug messages.
@@ -2609,7 +2608,7 @@ static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu, · 2556 unmodified lines
26092608
26102609 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
26112610
2612− for (i = 0; i < UMC_V8_10_TOTAL_CHANNEL_NUM(adev); i++) {
2611+ for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
26132612 ecc_info_per_channel = &(eccinfo->ecc[i]);
26142613 ecc_info_per_channel->ce_count_lo_chip =
26152614 ecc_table->EccInfo[i].ce_count_lo_chip;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c+76−4
@@ -831,6 +831,8 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, · 830 unmodified lines
831831 uint32_t max)
832832 {
833833 enum smu_message_type msg_set_min, msg_set_max;
834+ uint32_t min_clk = min;
835+ uint32_t max_clk = max;
834836 int ret = 0;
835837
836838 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
@@ -851,11 +853,16 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, · 14 unmodified lines
851853 return -EINVAL;
852854 }
853855
854− ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
856+ if (clk_type == SMU_VCLK) {
857+ min_clk = min << SMU_13_VCLK_SHIFT;
858+ max_clk = max << SMU_13_VCLK_SHIFT;
859+ }
860+
861+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
855862 if (ret)
856863 goto out;
857864
858− ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
865+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
859866 if (ret)
860867 goto out;
861868
@@ -971,31 +978,79 @@ force_level_out: · 109 unmodified lines
971978 return ret;
972979 }
973980
981+static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
982+ enum amd_dpm_forced_level level,
983+ enum smu_clk_type clk_type,
984+ uint32_t *min_clk,
985+ uint32_t *max_clk)
986+{
987+ int ret = 0;
988+ uint32_t clk_limit = 0;
989+
990+ switch (clk_type) {
991+ case SMU_GFXCLK:
992+ case SMU_SCLK:
993+ clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
994+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
995+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
996+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
997+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
998+ break;
999+ case SMU_VCLK:
1000+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1001+ break;
1002+ case SMU_DCLK:
1003+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1004+ break;
1005+ default:
1006+ ret = -EINVAL;
1007+ break;
1008+ }
1009+ *min_clk = *max_clk = clk_limit;
1010+ return ret;
1011+}
1012+
9741013 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
9751014 enum amd_dpm_forced_level level)
9761015 {
9771016 struct amdgpu_device *adev = smu->adev;
9781017 uint32_t sclk_min = 0, sclk_max = 0;
1018+ uint32_t vclk_min = 0, vclk_max = 0;
1019+ uint32_t dclk_min = 0, dclk_max = 0;
9791020 int ret = 0;
9801021
9811022 switch (level) {
9821023 case AMD_DPM_FORCED_LEVEL_HIGH:
9831024 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1025+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1026+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
9841027 sclk_min = sclk_max;
1028+ vclk_min = vclk_max;
1029+ dclk_min = dclk_max;
9851030 break;
9861031 case AMD_DPM_FORCED_LEVEL_LOW:
9871032 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1033+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1034+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
9881035 sclk_max = sclk_min;
1036+ vclk_max = vclk_min;
1037+ dclk_max = dclk_min;
9891038 break;
9901039 case AMD_DPM_FORCED_LEVEL_AUTO:
9911040 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1041+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1042+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
9921043 break;
9931044 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
9941045 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
995− case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
9961046 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
997− /* Temporarily do nothing since the optimal clocks haven't been provided yet */
1047+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1048+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1049+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
9981050 break;
1051+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1052+ dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
1053+ return -EOPNOTSUPP;
9991054 case AMD_DPM_FORCED_LEVEL_MANUAL:
10001055 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
10011056 return 0;
@@ -1016,6 +1071,23 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu, · 14 unmodified lines
10161071 smu->gfx_actual_soft_max_freq = sclk_max;
10171072 }
10181073
1074+ if (vclk_min && vclk_max) {
1075+ ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1076+ SMU_VCLK,
1077+ vclk_min,
1078+ vclk_max);
1079+ if (ret)
1080+ return ret;
1081+ }
1082+
1083+ if (dclk_min && dclk_max) {
1084+ ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1085+ SMU_DCLK,
1086+ dclk_min,
1087+ dclk_max);
1088+ if (ret)
1089+ return ret;
1090+ }
10191091 return ret;
10201092 }
10211093
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h+1−1
@@ -24,6 +24,6 @@ · 23 unmodified lines
2424 #define __SMU_V13_0_5_PPT_H__
2525
2626 extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);
27−#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100
27+#define SMU_13_0_5_UMD_PSTATE_GFXCLK 700
2828
2929 #endif
drivers/gpu/drm/display/drm_dp_mst_topology.c+47−7
@@ -4053,17 +4053,28 @@ out: · 4052 unmodified lines
40534053 }
40544054
40554055 /**
4056− * drm_dp_mst_hpd_irq() - MST hotplug IRQ notify
4056+ * drm_dp_mst_hpd_irq_handle_event() - MST hotplug IRQ handle MST event
40574057 * @mgr: manager to notify irq for.
40584058 * @esi: 4 bytes from SINK_COUNT_ESI
4059+ * @ack: 4 bytes used to ack events starting from SINK_COUNT_ESI
40594060 * @handled: whether the hpd interrupt was consumed or not
40604061 *
4061− * This should be called from the driver when it detects a short IRQ,
4062+ * This should be called from the driver when it detects a HPD IRQ,
40624063 * along with the value of the DEVICE_SERVICE_IRQ_VECTOR_ESI0. The
4063− * topology manager will process the sideband messages received as a result
4064− * of this.
4064+ * topology manager will process the sideband messages received
4065+ * as indicated in the DEVICE_SERVICE_IRQ_VECTOR_ESI0 and set the
4066+ * corresponding flags that Driver has to ack the DP receiver later.
4067+ *
4068+ * Note that driver shall also call
4069+ * drm_dp_mst_hpd_irq_send_new_request() if the 'handled' is set
4070+ * after calling this function, to try to kick off a new request in
4071+ * the queue if the previous message transaction is completed.
4072+ *
4073+ * See also:
4074+ * drm_dp_mst_hpd_irq_send_new_request()
40654075 */
4066−int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled)
4076+int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr *mgr, const u8 *esi,
4077+ u8 *ack, bool *handled)
40674078 {
40684079 int ret = 0;
40694080 int sc;
@@ -4078,18 +4089,47 @@ int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handl · 8 unmodified lines
40784089 if (esi[1] & DP_DOWN_REP_MSG_RDY) {
40794090 ret = drm_dp_mst_handle_down_rep(mgr);
40804091 *handled = true;
4092+ ack[1] |= DP_DOWN_REP_MSG_RDY;
40814093 }
40824094
40834095 if (esi[1] & DP_UP_REQ_MSG_RDY) {
40844096 ret |= drm_dp_mst_handle_up_req(mgr);
40854097 *handled = true;
4098+ ack[1] |= DP_UP_REQ_MSG_RDY;
40864099 }
40874100
4088− drm_dp_mst_kick_tx(mgr);
40894101 return ret;
40904102 }
4091−EXPORT_SYMBOL(drm_dp_mst_hpd_irq);
4103+EXPORT_SYMBOL(drm_dp_mst_hpd_irq_handle_event);
40924104
4105+/**
4106+ * drm_dp_mst_hpd_irq_send_new_request() - MST hotplug IRQ kick off new request
4107+ * @mgr: manager to notify irq for.
4108+ *
4109+ * This should be called from the driver when mst irq event is handled
4110+ * and acked. Note that new down request should only be sent when
4111+ * previous message transaction is completed. Source is not supposed to generate
4112+ * interleaved message transactions.
4113+ */
4114+void drm_dp_mst_hpd_irq_send_new_request(struct drm_dp_mst_topology_mgr *mgr)
4115+{
4116+ struct drm_dp_sideband_msg_tx *txmsg;
4117+ bool kick = true;
4118+
4119+ mutex_lock(&mgr->qlock);
4120+ txmsg = list_first_entry_or_null(&mgr->tx_msg_downq,
4121+ struct drm_dp_sideband_msg_tx, next);
4122+ /* If last transaction is not completed yet*/
4123+ if (!txmsg ||
4124+ txmsg->state == DRM_DP_SIDEBAND_TX_START_SEND ||
4125+ txmsg->state == DRM_DP_SIDEBAND_TX_SENT)
4126+ kick = false;
4127+ mutex_unlock(&mgr->qlock);
4128+
4129+ if (kick)
4130+ drm_dp_mst_kick_tx(mgr);
4131+}
4132+EXPORT_SYMBOL(drm_dp_mst_hpd_irq_send_new_request);
40934133 /**
40944134 * drm_dp_mst_detect_port() - get connection status for an MST port
40954135 * @connector: DRM connector for this port
drivers/gpu/drm/i915/display/intel_dp.c+4−3
@@ -4069,9 +4069,7 @@ intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) · 4068 unmodified lines
40694069 {
40704070 bool handled = false;
40714071
4072− drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4073− if (handled)
4074− ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
4072+ drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
40754073
40764074 if (esi[1] & DP_CP_IRQ) {
40774075 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
@@ -4146,6 +4144,9 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) · 68 unmodified lines
41464144
41474145 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
41484146 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4147+
4148+ if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4149+ drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
41494150 }
41504151
41514152 return link_ok;
drivers/gpu/drm/nouveau/dispnv50/disp.c+8−4
@@ -1359,22 +1359,26 @@ nv50_mstm_service(struct nouveau_drm *drm, · 1358 unmodified lines
13591359 u8 esi[8] = {};
13601360
13611361 while (handled) {
1362+ u8 ack[8] = {};
1363+
13621364 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
13631365 if (rc != 8) {
13641366 ret = false;
13651367 break;
13661368 }
13671369
1368− drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1370+ drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
13691371 if (!handled)
13701372 break;
13711373
1372− rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1373− 3);
1374− if (rc != 3) {
1374+ rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1375+
1376+ if (rc != 1) {
13751377 ret = false;
13761378 break;
13771379 }
1380+
1381+ drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
13781382 }
13791383
13801384 if (!ret)
drivers/gpu/drm/radeon/radeon_acpi.h+9−0
@@ -453,4 +453,13 @@ struct acpi_bus_event; · 452 unmodified lines
453453 * BYTE - number of active lanes
454454 */
455455
456+#if defined(CONFIG_VGA_SWITCHEROO)
457+void radeon_register_atpx_handler(void);
458+void radeon_unregister_atpx_handler(void);
459+bool radeon_has_atpx_dgpu_power_cntl(void);
460+bool radeon_is_atpx_hybrid(void);
461+bool radeon_has_atpx(void);
462+bool radeon_atpx_dgpu_req_power_for_displays(void);
463+#endif
464+
456465 #endif
drivers/gpu/drm/radeon/radeon_atpx_handler.c+1−1
@@ -147,7 +147,7 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas · 146 unmodified lines
147147 }
148148
149149 /**
150− * radeon_atpx_validate_functions - validate ATPX functions
150+ * radeon_atpx_validate() - validate ATPX functions
151151 *
152152 * @atpx: radeon atpx struct
153153 *
drivers/gpu/drm/radeon/radeon_fbdev.c+1−0
@@ -304,6 +304,7 @@ static void radeon_fbdev_client_unregister(struct drm_client_dev *client) · 303 unmodified lines
304304
305305 if (fb_helper->info) {
306306 vga_switcheroo_client_fb_set(rdev->pdev, NULL);
307+ drm_helper_force_disable_all(dev);
307308 drm_fb_helper_unregister_info(fb_helper);
308309 } else {
309310 drm_client_release(&fb_helper->client);
drivers/gpu/drm/scheduler/sched_entity.c+1−1
@@ -384,7 +384,7 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) · 383 unmodified lines
384384 }
385385
386386 s_fence = to_drm_sched_fence(fence);
387− if (s_fence && s_fence->sched == sched &&
387+ if (!fence->error && s_fence && s_fence->sched == sched &&
388388 !test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {
389389
390390 /*
include/drm/display/drm_dp_mst_helper.h+5−2
@@ -810,8 +810,11 @@ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); · 809 unmodified lines
810810 bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
811811 int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);
812812
813−int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled);
814−
813+int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr *mgr,
814+ const u8 *esi,
815+ u8 *ack,
816+ bool *handled);
817+void drm_dp_mst_hpd_irq_send_new_request(struct drm_dp_mst_topology_mgr *mgr);
815818
816819 int
817820 drm_dp_mst_detect_port(struct drm_connector *connector,
include/uapi/linux/kfd_ioctl.h+11−2
@@ -39,9 +39,10 @@ · 38 unmodified lines
3939 * - 1.11 - Add unified memory for ctx save/restore area
4040 * - 1.12 - Add DMA buf export ioctl
4141 * - 1.13 - Add debugger API
42+ * - 1.14 - Update kfd_event_data
4243 */
4344 #define KFD_IOCTL_MAJOR_VERSION 1
44−#define KFD_IOCTL_MINOR_VERSION 13
45+#define KFD_IOCTL_MINOR_VERSION 14
4546
4647 struct kfd_ioctl_get_version_args {
4748 __u32 major_version; /* from KFD */
@@ -320,12 +321,20 @@ struct kfd_hsa_hw_exception_data { · 272 unmodified lines
320321 __u32 gpu_id;
321322 };
322323
324+/* hsa signal event data */
325+struct kfd_hsa_signal_event_data {
326+ __u64 last_event_age; /* to and from KFD */
327+};
328+
323329 /* Event data */
324330 struct kfd_event_data {
325331 union {
332+ /* From KFD */
326333 struct kfd_hsa_memory_exception_data memory_exception_data;
327334 struct kfd_hsa_hw_exception_data hw_exception_data;
328− }; /* From KFD */
335+ /* To and From KFD */
336+ struct kfd_hsa_signal_event_data signal_event_data;
337+ };
329338 __u64 kfd_event_data_ext; /* pointer to an extension structure
330339 for future exception types */
331340 __u32 event_id; /* to KFD */

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