lael-labs/linux

Documentation/cgroup-v2.txt+6−5

@@ -1142,16 +1142,17 @@ used by the kernel. · 1141 unmodified lines
1142		1142
1143	pids.max	1143	pids.max
1144		1144
1145	A read-write single value file which exists on non-root cgroups. The	1145	A read-write single value file which exists on non-root
1146	default is "max".	1146	cgroups. The default is "max".
1147		1147
1148	Hard limit of number of processes.	1148	Hard limit of number of processes.
1149		1149
1150	pids.current	1150	pids.current
1151		1151
1152	A read-only single value file which exists on all cgroups.	1152	A read-only single value file which exists on all cgroups.
1153		1153
1154	The number of processes currently in the cgroup and its descendants.	1154	The number of processes currently in the cgroup and its
		1155	descendants.
1155		1156
1156	Organisational operations are not blocked by cgroup policies, so it is	1157	Organisational operations are not blocked by cgroup policies, so it is
1157	possible to have pids.current > pids.max. This can be done by either	1158	possible to have pids.current > pids.max. This can be done by either

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt+3−3

@@ -45,7 +45,7 @@ The following clocks are available: · 44 unmodified lines
45	- 1 15 SATA	45	- 1 15 SATA
46	- 1 16 SATA USB	46	- 1 16 SATA USB
47	- 1 17 Main	47	- 1 17 Main
48	- 1 18 SD/MMC	48	- 1 18 SD/MMC/GOP
49	- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)	49	- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
50	- 1 22 USB3H0	50	- 1 22 USB3H0
51	- 1 23 USB3H1	51	- 1 23 USB3H1
@@ -65,7 +65,7 @@ Required properties: · 13 unmodified lines
65	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",	65	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
66	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",	66	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
67	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",	67	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
68	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",	68	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
69	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";	69	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
70		70
71	Example:	71	Example:
@@ -78,6 +78,6 @@ Example: · 6 unmodified lines
78	gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",	78	gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
79	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",	79	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
80	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",	80	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
81	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",	81	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
82	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";	82	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
83	};	83	};

Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt+0−1

@@ -4,7 +4,6 @@ Required properties: · 3 unmodified lines
4	- compatible: value should be one of the following	4	- compatible: value should be one of the following
5	"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */	5	"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6	"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */	6	"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7	"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
8	"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */	7	"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
9	"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */	8	"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
10	"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */	9	"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */

Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt+0−1

@@ -11,7 +11,6 @@ Required properties: · 10 unmodified lines
11	"samsung,s5pv210-fimd"; /* for S5PV210 SoC */	11	"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12	"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */	12	"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13	"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */	13	"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14	"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
15	"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */	14	"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
16	"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */	15	"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
17		16

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt+1−1

@@ -13,7 +13,7 @@ Required Properties: · 12 unmodified lines
13	- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,	13	- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
14	before RK3288	14	before RK3288
15	- "rockchip,rk3288-dw-mshc": for Rockchip RK3288	15	- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
16	- "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108	16	- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
17	- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036	17	- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
18	- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368	18	- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
19	- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399	19	- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399

Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt+0−39

@@ -1,39 +0,0 @@
1	Broadcom USB3 phy binding for northstar plus SoC
2	The USB3 phy is internal to the SoC and is accessed using mdio interface.
3
4	Required mdio bus properties:
5	- reg: Should be 0x0 for SoC internal USB3 phy
6	- #address-cells: must be 1
7	- #size-cells: must be 0
8
9	Required USB3 PHY properties:
10	- compatible: should be "brcm,nsp-usb3-phy"
11	- reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10.
12	- usb3-ctrl-syscon: handler of syscon node defining physical address
13	of usb3 control register.
14	- #phy-cells: must be 0
15
16	Required usb3 control properties:
17	- compatible: should be "brcm,nsp-usb3-ctrl"
18	- reg: offset and length of the control registers
19
20	Example:
21
22	mdio@0 {
23	reg = <0x0>;
24	#address-cells = <1>;
25	#size-cells = <0>;
26
27	usb3_phy: usb-phy@10 {
28	compatible = "brcm,nsp-usb3-phy";
29	reg = <0x10>;
30	usb3-ctrl-syscon = <&usb3_ctrl>;
31	#phy-cells = <0>;
32	status = "disabled";
33	};
34	};
35
36	usb3_ctrl: syscon@104408 {
37	compatible = "brcm,nsp-usb3-ctrl", "syscon";
38	reg = <0x104408 0x3fc>;
39	};

Documentation/devicetree/bindings/powerpc/4xx/emac.txt+60−2

@@ -71,6 +71,9 @@ · 70 unmodified lines
71	For Axon it can be absent, though my current driver	71	For Axon it can be absent, though my current driver
72	doesn't handle phy-address yet so for now, keep	72	doesn't handle phy-address yet so for now, keep
73	0x00ffffff in it.	73	0x00ffffff in it.
		74	- phy-handle : Used to describe configurations where a external PHY
		75	is used. Please refer to:
		76	Documentation/devicetree/bindings/net/ethernet.txt
74	- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec	77	- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
75	operations (if absent the value is the same as	78	operations (if absent the value is the same as
76	rx-fifo-size). For Axon, either absent or 2048.	79	rx-fifo-size). For Axon, either absent or 2048.
@@ -81,8 +84,22 @@ · 4 unmodified lines
81	offload, phandle of the TAH device node.	84	offload, phandle of the TAH device node.
82	- tah-channel : 1 cell, optional. If appropriate, channel used on the	85	- tah-channel : 1 cell, optional. If appropriate, channel used on the
83	TAH engine.	86	TAH engine.
		87	- fixed-link : Fixed-link subnode describing a link to a non-MDIO
		88	managed entity. See
		89	Documentation/devicetree/bindings/net/fixed-link.txt
		90	for details.
		91	- mdio subnode : When the EMAC has a phy connected to its local
		92	mdio, which us supported by the kernel's network
		93	PHY library in drivers/net/phy, there must be device
		94	tree subnode with the following required properties:
		95	- #address-cells: Must be <1>.
		96	- #size-cells: Must be <0>.
84		97
85	Example:	98	For PHY definitions: Please refer to
		99	Documentation/devicetree/bindings/net/phy.txt and
		100	Documentation/devicetree/bindings/net/ethernet.txt
		101
		102	Examples:
86		103
87	EMAC0: ethernet@40000800 {	104	EMAC0: ethernet@40000800 {
88	device_type = "network";	105	device_type = "network";
@@ -104,6 +121,48 @@ · 15 unmodified lines
104	zmii-channel = <0>;	121	zmii-channel = <0>;
105	};	122	};
106		123
		124	EMAC1: ethernet@ef600c00 {
		125	device_type = "network";
		126	compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
		127	interrupt-parent = <&EMAC1>;
		128	interrupts = <0 1>;
		129	#interrupt-cells = <1>;
		130	#address-cells = <0>;
		131	#size-cells = <0>;
		132	interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
		133	1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
		134	reg = <0xef600c00 0x000000c4>;
		135	local-mac-address = [000000000000]; /* Filled in by U-Boot */
		136	mal-device = <&MAL0>;
		137	mal-tx-channel = <0>;
		138	mal-rx-channel = <0>;
		139	cell-index = <0>;
		140	max-frame-size = <9000>;
		141	rx-fifo-size = <16384>;
		142	tx-fifo-size = <2048>;
		143	fifo-entry-size = <10>;
		144	phy-mode = "rgmii";
		145	phy-handle = <&phy0>;
		146	phy-map = <0x00000000>;
		147	rgmii-device = <&RGMII0>;
		148	rgmii-channel = <0>;
		149	tah-device = <&TAH0>;
		150	tah-channel = <0>;
		151	has-inverted-stacr-oc;
		152	has-new-stacr-staopc;
		153
		154	mdio {
		155	#address-cells = <1>;
		156	#size-cells = <0>;
		157
		158	phy0: ethernet-phy@0 {
		159	compatible = "ethernet-phy-ieee802.3-c22";
		160	reg = <0>;
		161	};
		162	};
		163	};
		164
		165
107	ii) McMAL node	166	ii) McMAL node
108		167
109	Required properties:	168	Required properties:
@@ -145,4 +204,3 @@ · 35 unmodified lines
145	- revision : as provided by the RGMII new version register if	204	- revision : as provided by the RGMII new version register if
146	available.	205	available.
147	For Axon: 0x0000012a	206	For Axon: 0x0000012a
148

Documentation/extcon/intel-int3496.txt+5−0

@@ -20,3 +20,8 @@ Index 1: The output gpio for enabling Vbus output from the device to the otg · 19 unmodified lines
20	Index 2: The output gpio for muxing of the data pins between the USB host and	20	Index 2: The output gpio for muxing of the data pins between the USB host and
21	the USB peripheral controller, write 1 to mux to the peripheral	21	the USB peripheral controller, write 1 to mux to the peripheral
22	controller	22	controller
		23
		24	There is a mapping between indices and GPIO connection IDs as follows
		25	id index 0
		26	vbus index 1
		27	mux index 2

Documentation/gcc-plugins.txt+2−2

@@ -18,8 +18,8 @@ because gcc versions 4.5 and 4.6 are compiled by a C compiler, · 17 unmodified lines
18	gcc-4.7 can be compiled by a C or a C++ compiler,	18	gcc-4.7 can be compiled by a C or a C++ compiler,
19	and versions 4.8+ can only be compiled by a C++ compiler.	19	and versions 4.8+ can only be compiled by a C++ compiler.
20		20
21	Currently the GCC plugin infrastructure supports only the x86, arm and arm64	21	Currently the GCC plugin infrastructure supports only the x86, arm, arm64 and
22	architectures.	22	powerpc architectures.
23		23
24	This infrastructure was ported from grsecurity [6] and PaX [7].	24	This infrastructure was ported from grsecurity [6] and PaX [7].
25		25

Documentation/networking/ip-sysctl.txt+2−1

@@ -1006,7 +1006,8 @@ accept_redirects - BOOLEAN · 1005 unmodified lines
1006	FALSE (router)	1006	FALSE (router)
1007		1007
1008	forwarding - BOOLEAN	1008	forwarding - BOOLEAN
1009	Enable IP forwarding on this interface.	1009	Enable IP forwarding on this interface. This controls whether packets
		1010	received _on_ this interface can be forwarded.
1010		1011
1011	mc_forwarding - BOOLEAN	1012	mc_forwarding - BOOLEAN
1012	Do multicast routing. The kernel needs to be compiled with CONFIG_MROUTE	1013	Do multicast routing. The kernel needs to be compiled with CONFIG_MROUTE

MAINTAINERS+2−16

 CISCO VIC ETHERNET NIC DRIVER
 M:	Christian Benvenuti <benve@cisco.com>
-M:	Sujith Sankar <ssujith@cisco.com>
 M:	Govindarajulu Varadarajan <_govind@gmx.com>
 M:	Neel Patel <neepatel@cisco.com>
 S:	Supported
 F:	net/mac80211/
 F:	drivers/net/wireless/mac80211_hwsim.[ch]
-MACVLAN DRIVER
-M:	Patrick McHardy <kaber@trash.net>
-L:	netdev@vger.kernel.org
-S:	Maintained
-F:	drivers/net/macvlan.c
-F:	include/linux/if_macvlan.h
 MAILBOX API
 M:	Jassi Brar <jassisinghbrar@gmail.com>
 L:	linux-kernel@vger.kernel.org
 MARVELL MWIFIEX WIRELESS DRIVER
 M:	Amitkumar Karwar <akarwar@marvell.com>
 M:	Nishant Sarmukadam <nishants@marvell.com>
+M:	Ganapathi Bhat <gbhat@marvell.com>
+M:	Xinming Hu <huxm@marvell.com>
 L:	linux-wireless@vger.kernel.org
 S:	Maintained
 F:	drivers/net/wireless/marvell/mwifiex/
 S:	Maintained
 F:	drivers/media/platform/vivid/*
-VLAN (802.1Q)
-M:	Patrick McHardy <kaber@trash.net>
-L:	netdev@vger.kernel.org
-S:	Maintained
-F:	drivers/net/macvlan.c
-F:	include/linux/if_*vlan.h
-F:	net/8021q/
 VLYNQ BUS
 M:	Florian Fainelli <f.fainelli@gmail.com>
 L:	openwrt-devel@lists.openwrt.org (subscribers-only)

Makefile+1−1

@@ -1,7 +1,7 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 11	2	PATCHLEVEL = 11
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc2	4	EXTRAVERSION = -rc4
5	NAME = Fearless Coyote	5	NAME = Fearless Coyote
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION

arch/arm/boot/dts/am335x-pcm-953.dtsi+2−2

@@ -63,14 +63,14 @@ · 62 unmodified lines
63	label = "home";	63	label = "home";
64	linux,code = <KEY_HOME>;	64	linux,code = <KEY_HOME>;
65	gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;	65	gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
66	gpio-key,wakeup;	66	wakeup-source;
67	};	67	};
68		68
69	button@1 {	69	button@1 {
70	label = "menu";	70	label = "menu";
71	linux,code = <KEY_MENU>;	71	linux,code = <KEY_MENU>;
72	gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;	72	gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
73	gpio-key,wakeup;	73	wakeup-source;
74	};	74	};
75		75
76	};	76	};

arch/arm/boot/dts/am57xx-idk-common.dtsi+7−7

 			/* ID & VBUS GPIOs provided in board dts */
 		};
 	};
+	tpic2810: tpic2810@60 {
+		compatible = "ti,tpic2810";
+		reg = <0x60>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
 &mcspi3 {
 		spi-max-frequency = <1000000>;
 		spi-cpol;
 	};
-	tpic2810: tpic2810@60 {
-		compatible = "ti,tpic2810";
-		reg = <0x60>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
 };
 &uart3 {

arch/arm/boot/dts/bcm5301x.dtsi+2−2

@@ -66,14 +66,14 @@ · 65 unmodified lines
66	timer@20200 {	66	timer@20200 {
67	compatible = "arm,cortex-a9-global-timer";	67	compatible = "arm,cortex-a9-global-timer";
68	reg = <0x20200 0x100>;	68	reg = <0x20200 0x100>;
69	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;	69	interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
70	clocks = <&periph_clk>;	70	clocks = <&periph_clk>;
71	};	71	};
72		72
73	local-timer@20600 {	73	local-timer@20600 {
74	compatible = "arm,cortex-a9-twd-timer";	74	compatible = "arm,cortex-a9-twd-timer";
75	reg = <0x20600 0x100>;	75	reg = <0x20600 0x100>;
76	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;	76	interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
77	clocks = <&periph_clk>;	77	clocks = <&periph_clk>;
78	};	78	};
79		79

arch/arm/boot/dts/bcm953012k.dts+2−3

 	};
 	memory {
-		reg = <0x00000000 0x10000000>;
+		reg = <0x80000000 0x10000000>;
 	};
 };
 &uart0 {
-	clock-frequency = <62499840>;
+	status = "okay";
 };
 &uart1 {
-	clock-frequency = <62499840>;
 	status = "okay";
 };

arch/arm/boot/dts/bcm958522er.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm958525er.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm958525xmc.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 31 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 31 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm958622hr.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm958623hr.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm958625hr.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/bcm988312hr.dts+1−0

@@ -55,6 +55,7 @@ · 54 unmodified lines
55	gpio-restart {	55	gpio-restart {
56	compatible = "gpio-restart";	56	compatible = "gpio-restart";
57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;	57	gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		58	open-source;
58	priority = <200>;	59	priority = <200>;
59	};	60	};
60	};	61	};

arch/arm/boot/dts/imx6sx-udoo-neo.dtsi+0−5

 	};
 };
-&cpu0 {
-	arm-supply = <&sw1a_reg>;
-	soc-supply = <&sw1c_reg>;
-};
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;

arch/arm/boot/dts/sama5d2.dtsi+1−1

@@ -266,7 +266,7 @@ · 265 unmodified lines
266	};	266	};
267		267
268	usb1: ohci@00400000 {	268	usb1: ohci@00400000 {
269	compatible = "atmel,sama5d2-ohci", "usb-ohci";	269	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
270	reg = <0x00400000 0x100000>;	270	reg = <0x00400000 0x100000>;
271	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;	271	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
272	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;	272	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;

arch/arm/boot/dts/ste-dbx5x0.dtsi+19−0

 #include <dt-bindings/mfd/dbx500-prcmu.h>
 #include <dt-bindings/arm/ux500_pm_domains.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/ste-ab8500.h>
 #include "skeleton.dtsi"
 / {
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				ab8500_clock: clock-controller {
+					compatible = "stericsson,ab8500-clk";
+					#clock-cells = <1>;
+				};
 				ab8500_gpio: ab8500-gpio {
 					compatible = "stericsson,ab8500-gpio";
 					gpio-controller;
 				ab8500-pwm {
 					compatible = "stericsson,ab8500-pwm";
+					clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+					clock-names = "intclk";
 				};
 				ab8500-debugfs {
 					V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 					V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
+					clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
+					clock-names = "audioclk";
 					stericsson,earpeice-cmv = <950>; /* Units in mV. */
 				};
 			status = "disabled";
 		};
+		sound {
+			compatible = "stericsson,snd-soc-mop500";
+			stericsson,cpu-dai = <&msp1 &msp3>;
+			stericsson,audio-codec = <&codec>;
+			clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
+			clock-names = "sysclk", "ulpclk", "intclk";
+		};
 		msp0: msp@80123000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80123000 0x1000>;

arch/arm/boot/dts/ste-href.dtsi+0−9

@@ -186,15 +186,6 @@ · 185 unmodified lines
186	status = "okay";	186	status = "okay";
187	};	187	};
188		188
189	sound {
190	compatible = "stericsson,snd-soc-mop500";
191
192	stericsson,cpu-dai = <&msp1 &msp3>;
193	stericsson,audio-codec = <&codec>;
194	clocks = <&prcmu_clk PRCMU_SYSCLK>;
195	clock-names = "sysclk";
196	};
197
198	msp0: msp@80123000 {	189	msp0: msp@80123000 {
199	pinctrl-names = "default";	190	pinctrl-names = "default";
200	pinctrl-0 = <&msp0_default_mode>;	191	pinctrl-0 = <&msp0_default_mode>;

arch/arm/boot/dts/ste-snowball.dts+0−9

@@ -159,15 +159,6 @@ · 158 unmodified lines
159	"", "", "", "", "", "", "", "";	159	"", "", "", "", "", "", "", "";
160	};	160	};
161		161
162	sound {
163	compatible = "stericsson,snd-soc-mop500";
164
165	stericsson,cpu-dai = <&msp1 &msp3>;
166	stericsson,audio-codec = <&codec>;
167	clocks = <&prcmu_clk PRCMU_SYSCLK>;
168	clock-names = "sysclk";
169	};
170
171	msp0: msp@80123000 {	162	msp0: msp@80123000 {
172	pinctrl-names = "default";	163	pinctrl-names = "default";
173	pinctrl-0 = <&msp0_default_mode>;	164	pinctrl-0 = <&msp0_default_mode>;

arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts+1−1

@@ -167,7 +167,7 @@ · 166 unmodified lines
167	reg = <8>;	167	reg = <8>;
168	label = "cpu";	168	label = "cpu";
169	ethernet = <&gmac>;	169	ethernet = <&gmac>;
170	phy-mode = "rgmii";	170	phy-mode = "rgmii-txid";
171	fixed-link {	171	fixed-link {
172	speed = <1000>;	172	speed = <1000>;
173	full-duplex;	173	full-duplex;

arch/arm/boot/dts/sun8i-a23-a33.dtsi+1−1

@@ -495,7 +495,7 @@ · 494 unmodified lines
495	resets = <&ccu RST_BUS_GPU>;	495	resets = <&ccu RST_BUS_GPU>;
496		496
497	assigned-clocks = <&ccu CLK_GPU>;	497	assigned-clocks = <&ccu CLK_GPU>;
498	assigned-clock-rates = <408000000>;	498	assigned-clock-rates = <384000000>;
499	};	499	};
500		500
501	gic: interrupt-controller@01c81000 {	501	gic: interrupt-controller@01c81000 {

arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi+0−7

 	backlight: backlight {
 		compatible = "pwm-backlight";
-		pinctrl-names = "default";
-		pinctrl-0 = <&bl_en_pin>;
 		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 };
 &pio {
-	bl_en_pin: bl_en_pin@0 {
-		pins = "PH6";
-		function = "gpio_in";
-	};
 	mmc0_cd_pin: mmc0_cd_pin@0 {
 		pins = "PB4";
 		function = "gpio_in";

arch/arm/configs/omap2plus_defconfig+1−0

@@ -188,6 +188,7 @@ CONFIG_WL12XX=m · 187 unmodified lines
188	CONFIG_WL18XX=m	188	CONFIG_WL18XX=m
189	CONFIG_WLCORE_SPI=m	189	CONFIG_WLCORE_SPI=m
190	CONFIG_WLCORE_SDIO=m	190	CONFIG_WLCORE_SDIO=m
		191	CONFIG_INPUT_MOUSEDEV=m
191	CONFIG_INPUT_JOYDEV=m	192	CONFIG_INPUT_JOYDEV=m
192	CONFIG_INPUT_EVDEV=m	193	CONFIG_INPUT_EVDEV=m
193	CONFIG_KEYBOARD_ATKBD=m	194	CONFIG_KEYBOARD_ATKBD=m

arch/arm/mach-at91/pm.c+17−1

@@ -289,6 +289,22 @@ static void at91_ddr_standby(void) · 288 unmodified lines
289	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);	289	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
290	}	290	}
291		291
		292	static void sama5d3_ddr_standby(void)
		293	{
		294	u32 lpr0;
		295	u32 saved_lpr0;
		296
		297	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
		298	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
		299	lpr0 \|= AT91_DDRSDRC_LPCB_POWER_DOWN;
		300
		301	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
		302
		303	cpu_do_idle();
		304
		305	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
		306	}
		307
292	/* We manage both DDRAM/SDRAM controllers, we need more than one value to	308	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
293	* remember.	309	* remember.
294	*/	310	*/
@@ -323,7 +339,7 @@ static const struct of_device_id const ramc_ids[] __initconst = { · 28 unmodified lines
323	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },	339	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
324	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },	340	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
325	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },	341	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
326	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },	342	{ .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
327	{ /sentinel/ }	343	{ /sentinel/ }
328	};	344	};
329		345

arch/arm/mach-omap2/Makefile+0−3

@@ -241,6 +241,3 @@ obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o · 240 unmodified lines
241		241
242	onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o	242	onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
243	obj-y += $(onenand-m) $(onenand-y)	243	obj-y += $(onenand-m) $(onenand-y)
244
245	nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
246	obj-y += $(nand-m) $(nand-y)

arch/arm/mach-omap2/gpmc-nand.c+0−154

@@ -1,154 +0,0 @@
1	/*
2	* gpmc-nand.c
3	*
4	* Copyright (C) 2009 Texas Instruments
5	* Vimal Singh <vimalsingh@ti.com>
6	*
7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License version 2 as
9	* published by the Free Software Foundation.
10	*/
11
12	#include <linux/kernel.h>
13	#include <linux/platform_device.h>
14	#include <linux/io.h>
15	#include <linux/omap-gpmc.h>
16	#include <linux/mtd/nand.h>
17	#include <linux/platform_data/mtd-nand-omap2.h>
18
19	#include <asm/mach/flash.h>
20
21	#include "soc.h"
22
23	/* minimum size for IO mapping */
24	#define NAND_IO_SIZE 4
25
26	static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
27	{
28	/* platforms which support all ECC schemes */
29	if (soc_is_am33xx() \|\| soc_is_am43xx() \|\| cpu_is_omap44xx() \|\|
30	soc_is_omap54xx() \|\| soc_is_dra7xx())
31	return 1;
32
33	if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW \|\|
34	ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) {
35	if (cpu_is_omap24xx())
36	return 0;
37	else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
38	return 0;
39	else
40	return 1;
41	}
42
43	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
44	* which require H/W based ECC error detection */
45	if ((cpu_is_omap34xx() \|\| cpu_is_omap3630()) &&
46	((ecc_opt == OMAP_ECC_BCH4_CODE_HW) \|\|
47	(ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
48	return 0;
49
50	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
51	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW \|\|
52	ecc_opt == OMAP_ECC_HAM1_CODE_SW)
53	return 1;
54	else
55	return 0;
56	}
57
58	/* This function will go away once the device-tree convertion is complete */
59	static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
60	struct gpmc_settings *s)
61	{
62	/* Enable RD PIN Monitoring Reg */
63	if (gpmc_nand_data->dev_ready) {
64	s->wait_on_read = true;
65	s->wait_on_write = true;
66	}
67
68	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
69	s->device_width = GPMC_DEVWIDTH_16BIT;
70	else
71	s->device_width = GPMC_DEVWIDTH_8BIT;
72	}
73
74	int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
75	struct gpmc_timings *gpmc_t)
76	{
77	int err = 0;
78	struct gpmc_settings s;
79	struct platform_device *pdev;
80	struct resource gpmc_nand_res[] = {
81	{ .flags = IORESOURCE_MEM, },
82	{ .flags = IORESOURCE_IRQ, },
83	{ .flags = IORESOURCE_IRQ, },
84	};
85
86	BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
87
88	err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
89	(unsigned long *)&gpmc_nand_res[0].start);
90	if (err < 0) {
91	pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
92	gpmc_nand_data->cs, err);
93	return err;
94	}
95	gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
96	gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
97	gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
98
99	memset(&s, 0, sizeof(struct gpmc_settings));
100	gpmc_set_legacy(gpmc_nand_data, &s);
101
102	s.device_nand = true;
103
104	if (gpmc_t) {
105	err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s);
106	if (err < 0) {
107	pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n",
108	err);
109	return err;
110	}
111	}
112
113	err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
114	if (err < 0)
115	goto out_free_cs;
116
117	err = gpmc_configure(GPMC_CONFIG_WP, 0);
118	if (err < 0)
119	goto out_free_cs;
120
121	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
122	pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
123	err = -EINVAL;
124	goto out_free_cs;
125	}
126
127
128	pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
129	if (pdev) {
130	err = platform_device_add_resources(pdev, gpmc_nand_res,
131	ARRAY_SIZE(gpmc_nand_res));
132	if (!err)
133	pdev->dev.platform_data = gpmc_nand_data;
134	} else {
135	err = -ENOMEM;
136	}
137	if (err)
138	goto out_free_pdev;
139
140	err = platform_device_add(pdev);
141	if (err) {
142	dev_err(&pdev->dev, "Unable to register NAND device\n");
143	goto out_free_pdev;
144	}
145
146	return 0;
147
148	out_free_pdev:
149	platform_device_put(pdev);
150	out_free_cs:
151	gpmc_cs_free(gpmc_nand_data->cs);
152
153	return err;
154	}

arch/arm/mach-omap2/gpmc-onenand.c+6−4

 	return ret;
 }
-void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
+int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
 	int err;
 	struct device *dev = &gpmc_onenand_device.dev;
 	if (err < 0) {
 		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
 			gpmc_onenand_data->cs, err);
-		return;
+		return err;
 	}
 	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
 							ONENAND_IO_SIZE - 1;
-	if (platform_device_register(&gpmc_onenand_device) < 0) {
+	err = platform_device_register(&gpmc_onenand_device);
+	if (err) {
 		dev_err(dev, "Unable to register OneNAND device\n");
 		gpmc_cs_free(gpmc_onenand_data->cs);
-		return;
 	}
+	return err;
 }

arch/arm/mach-omap2/omap-headsmp.S+2−1

 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/assembler.h>
 #include "omap44xx.h"
 	cmp	r0, r4
 	bne	wait_2
 	ldr	r12, =API_HYP_ENTRY
-	adr	r0, hyp_boot
+	badr	r0, hyp_boot
 	smc	#0
 hyp_boot:
 	b	omap_secondary_startup

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c+37−8

 };
 /* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+	{
+		.pa_start	= OMAP34XX_SR1_BASE,
+		.pa_end		= OMAP34XX_SR1_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+	{ },
+};
 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap34xx_sr1_hwmod,
 	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap36xx_sr1_hwmod,
 	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 /* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+	{
+		.pa_start	= OMAP34XX_SR2_BASE,
+		.pa_end		= OMAP34XX_SR2_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+	{ },
+};
 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap34xx_sr2_hwmod,
 	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap36xx_sr2_hwmod,
 	.clk		= "sr_l4_ick",
+	.addr		= omap3_sr2_addr_space,
 	.user		= OCP_USER_MPU,
 };
  * Return: 0 if device named @dev_name is not likely to be accessible,
  * or 1 if it is likely to be accessible.
  */
-static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
+static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
-						       const char *dev_name)
+							const char *dev_name)
 {
+	struct device_node *node;
+	bool available;
 	if (!bus)
-		return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
+		return omap_type() == OMAP2_DEVICE_TYPE_GP;
-	if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
+	node = of_get_child_by_name(bus, dev_name);
-		return 1;
+	available = of_device_is_available(node);
+	of_node_put(node);
-	return 0;
+	return available;
 }
 int __init omap3xxx_hwmod_init(void)
 	if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
 		r = omap_hwmod_register_links(h_sham);
-		if (r < 0)
+		if (r < 0) {
+			of_node_put(bus);
 			return r;
+		}
 	}
 	if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
 		r = omap_hwmod_register_links(h_aes);
-		if (r < 0)
+		if (r < 0) {
+			of_node_put(bus);
 			return r;
+		}
 	}
+	of_node_put(bus);
 	/*
 	 * Register hwmod links specific to certain ES levels of a

arch/arm/tools/syscall.tbl+1−0

@@ -411,3 +411,4 @@ · 410 unmodified lines
411	394 common pkey_mprotect sys_pkey_mprotect	411	394 common pkey_mprotect sys_pkey_mprotect
412	395 common pkey_alloc sys_pkey_alloc	412	395 common pkey_alloc sys_pkey_alloc
413	396 common pkey_free sys_pkey_free	413	396 common pkey_free sys_pkey_free
		414	397 common statx sys_statx

arch/arm64/Kconfig+4−0

@@ -1073,6 +1073,10 @@ config SYSVIPC_COMPAT · 1072 unmodified lines
1073	def_bool y	1073	def_bool y
1074	depends on COMPAT && SYSVIPC	1074	depends on COMPAT && SYSVIPC
1075		1075
		1076	config KEYS_COMPAT
		1077	def_bool y
		1078	depends on COMPAT && KEYS
		1079
1076	endmenu	1080	endmenu
1077		1081
1078	menu "Power management options"	1082	menu "Power management options"

arch/arm64/boot/dts/broadcom/ns2.dtsi+11−0

 	pcie0: pcie@20020000 {
 		compatible = "brcm,iproc-pcie";
 		reg = <0 0x20020000 0 0x1000>;
+		dma-coherent;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
 	pcie4: pcie@50020000 {
 		compatible = "brcm,iproc-pcie";
 		reg = <0 0x50020000 0 0x1000>;
+		dma-coherent;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
 	pcie8: pcie@60c00000 {
 		compatible = "brcm,iproc-pcie-paxc";
 		reg = <0 0x60c00000 0 0x1000>;
+		dma-coherent;
 		linux,pci-domain = <8>;
 		bus-range = <0x0 0x1>;
 			      <0x61030000 0x100>;
 			reg-names = "amac_base", "idm_base", "nicpm_base";
 			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 			phy-handle = <&gphy0>;
 			phy-mode = "rgmii";
 			status = "disabled";
 			reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <1>;
+			dma-coherent;
 			brcm,rx-status-len = <32>;
 			brcm,use-bcm-hdr;
 		};
 			reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
 			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <1>;
+			dma-coherent;
 			brcm,rx-status-len = <32>;
 			brcm,use-bcm-hdr;
 		};
 			reg = <0x61300000 0x445>;  /* PDC FS2 regs */
 			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <1>;
+			dma-coherent;
 			brcm,rx-status-len = <32>;
 			brcm,use-bcm-hdr;
 		};
 			reg = <0x61320000 0x445>;  /* PDC FS3 regs */
 			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <1>;
+			dma-coherent;
 			brcm,rx-status-len = <32>;
 			brcm,use-bcm-hdr;
 		};
 		sata: ahci@663f2000 {
 			compatible = "brcm,iproc-ahci", "generic-ahci";
 			reg = <0x663f2000 0x1000>;
+			dma-coherent;
 			reg-names = "ahci";
 			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			compatible = "brcm,sdhci-iproc-cygnus";
 			reg = <0x66420000 0x100>;
 			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 			bus-width = <8>;
 			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 			status = "disabled";
 			compatible = "brcm,sdhci-iproc-cygnus";
 			reg = <0x66430000 0x100>;
 			interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 			bus-width = <8>;
 			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 			status = "disabled";

arch/arm64/include/asm/cpufeature.h+1−1

@@ -251,7 +251,7 @@ static inline bool system_supports_fpsimd(void) · 250 unmodified lines
251	static inline bool system_uses_ttbr0_pan(void)	251	static inline bool system_uses_ttbr0_pan(void)
252	{	252	{
253	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&	253	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
254	!cpus_have_cap(ARM64_HAS_PAN);	254	!cpus_have_const_cap(ARM64_HAS_PAN);
255	}	255	}
256		256
257	#endif /* __ASSEMBLY__ */	257	#endif /* __ASSEMBLY__ */

arch/arm64/include/asm/unistd.h+1−1

@@ -44,7 +44,7 @@ · 43 unmodified lines
44	#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)	44	#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)
45	#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)	45	#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)
46		46
47	#define __NR_compat_syscalls 394	47	#define __NR_compat_syscalls 398
48	#endif	48	#endif
49		49
50	#define __ARCH_WANT_SYS_CLONE	50	#define __ARCH_WANT_SYS_CLONE

arch/arm64/include/asm/unistd32.h+8−0

@@ -809,6 +809,14 @@ __SYSCALL(__NR_copy_file_range, sys_copy_file_range) · 808 unmodified lines
809	__SYSCALL(__NR_preadv2, compat_sys_preadv2)	809	__SYSCALL(__NR_preadv2, compat_sys_preadv2)
810	#define __NR_pwritev2 393	810	#define __NR_pwritev2 393
811	__SYSCALL(__NR_pwritev2, compat_sys_pwritev2)	811	__SYSCALL(__NR_pwritev2, compat_sys_pwritev2)
		812	#define __NR_pkey_mprotect 394
		813	__SYSCALL(__NR_pkey_mprotect, sys_pkey_mprotect)
		814	#define __NR_pkey_alloc 395
		815	__SYSCALL(__NR_pkey_alloc, sys_pkey_alloc)
		816	#define __NR_pkey_free 396
		817	__SYSCALL(__NR_pkey_free, sys_pkey_free)
		818	#define __NR_statx 397
		819	__SYSCALL(__NR_statx, sys_statx)
812		820
813	/*	821	/*
814	* Please add new compat syscalls above this comment and update	822	* Please add new compat syscalls above this comment and update

arch/arm64/kernel/cpuidle.c+1−1

@@ -30,7 +30,7 @@ int arm_cpuidle_init(unsigned int cpu) · 29 unmodified lines
30	}	30	}
31		31
32	/**	32	/**
33	* cpu_suspend() - function to enter a low-power idle state	33	* arm_cpuidle_suspend() - function to enter a low-power idle state
34	* @arg: argument to pass to CPU suspend operations	34	* @arg: argument to pass to CPU suspend operations
35	*	35	*
36	* Return: 0 on success, -EOPNOTSUPP if CPU suspend hook not initialized, CPU	36	* Return: 0 on success, -EOPNOTSUPP if CPU suspend hook not initialized, CPU

arch/arm64/kernel/kaslr.c+7−3

 	/*
 	 * The kernel Image should not extend across a 1GB/32MB/512MB alignment
 	 * boundary (for 4KB/16KB/64KB granule kernels, respectively). If this
-	 * happens, increase the KASLR offset by the size of the kernel image.
+	 * happens, increase the KASLR offset by the size of the kernel image
+	 * rounded up by SWAPPER_BLOCK_SIZE.
 	 */
 	if ((((u64)_text + offset + modulo_offset) >> SWAPPER_TABLE_SHIFT) !=
-	    (((u64)_end + offset + modulo_offset) >> SWAPPER_TABLE_SHIFT))
+	    (((u64)_end + offset + modulo_offset) >> SWAPPER_TABLE_SHIFT)) {
-		offset = (offset + (u64)(_end - _text)) & mask;
+		u64 kimg_sz = _end - _text;
+		offset = (offset + round_up(kimg_sz, SWAPPER_BLOCK_SIZE))
+				& mask;
+	}
 	if (IS_ENABLED(CONFIG_KASAN))
 		/*

arch/arm64/kernel/probes/kprobes.c+0−6

 	return 0;
 }
-int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
-				       unsigned long val, void *data)
-{
-	return NOTIFY_DONE;
-}
 static void __kprobes kprobe_handler(struct pt_regs *regs)
 {
 	struct kprobe *p, *cur_kprobe;

arch/arm64/mm/kasan_init.c+1−1

@@ -162,7 +162,7 @@ void __init kasan_init(void) · 161 unmodified lines
162	clear_pgds(KASAN_SHADOW_START, KASAN_SHADOW_END);	162	clear_pgds(KASAN_SHADOW_START, KASAN_SHADOW_END);
163		163
164	vmemmap_populate(kimg_shadow_start, kimg_shadow_end,	164	vmemmap_populate(kimg_shadow_start, kimg_shadow_end,
165	pfn_to_nid(virt_to_pfn(_text)));	165	pfn_to_nid(virt_to_pfn(lm_alias(_text))));
166		166
167	/*	167	/*
168	* vmemmap_populate() has populated the shadow region that covers the	168	* vmemmap_populate() has populated the shadow region that covers the

arch/openrisc/include/asm/cmpxchg.h+6−2

 	return val;
 }
-#define xchg(ptr, with) \
+#define xchg(ptr, with) 						\
-	((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), sizeof(*(ptr))))
+	({								\
+		(__typeof__(*(ptr))) __xchg((unsigned long)(with),	\
+					    (ptr),			\
+					    sizeof(*(ptr)));		\
+	})
 #endif /* __ASM_OPENRISC_CMPXCHG_H */

arch/openrisc/include/asm/uaccess.h+1−1

@@ -211,7 +211,7 @@ do { \ · 210 unmodified lines
211	case 1: __get_user_asm(x, ptr, retval, "l.lbz"); break; \	211	case 1: __get_user_asm(x, ptr, retval, "l.lbz"); break; \
212	case 2: __get_user_asm(x, ptr, retval, "l.lhz"); break; \	212	case 2: __get_user_asm(x, ptr, retval, "l.lhz"); break; \
213	case 4: __get_user_asm(x, ptr, retval, "l.lwz"); break; \	213	case 4: __get_user_asm(x, ptr, retval, "l.lwz"); break; \
214	case 8: __get_user_asm2(x, ptr, retval); \	214	case 8: __get_user_asm2(x, ptr, retval); break; \
215	default: (x) = __get_user_bad(); \	215	default: (x) = __get_user_bad(); \
216	} \	216	} \
217	} while (0)	217	} while (0)

arch/openrisc/kernel/or32_ksyms.c+4−0

 #include <asm/hardirq.h>
 #include <asm/delay.h>
 #include <asm/pgalloc.h>
+#include <asm/pgtable.h>
 #define DECLARE_EXPORT(name) extern void name(void); EXPORT_SYMBOL(name)
 DECLARE_EXPORT(__ashrdi3);
 DECLARE_EXPORT(__ashldi3);
 DECLARE_EXPORT(__lshrdi3);
+DECLARE_EXPORT(__ucmpdi2);
+EXPORT_SYMBOL(empty_zero_page);
 EXPORT_SYMBOL(__copy_tofrom_user);
+EXPORT_SYMBOL(__clear_user);
 EXPORT_SYMBOL(memset);

arch/openrisc/kernel/process.c+1−0

@@ -90,6 +90,7 @@ void arch_cpu_idle(void) · 89 unmodified lines
90	}	90	}
91		91
92	void (*pm_power_off) (void) = machine_power_off;	92	void (*pm_power_off) (void) = machine_power_off;
		93	EXPORT_SYMBOL(pm_power_off);
93		94
94	/*	95	/*
95	* When a process does an "exec", machine state like FPU and debug	96	* When a process does an "exec", machine state like FPU and debug

arch/parisc/include/asm/cacheflush.h+2−21

@@ -43,28 +43,9 @@ static inline void flush_kernel_dcache_page(struct page *page) · 42 unmodified lines
43		43
44	#define flush_kernel_dcache_range(start,size) \	44	#define flush_kernel_dcache_range(start,size) \
45	flush_kernel_dcache_range_asm((start), (start)+(size));	45	flush_kernel_dcache_range_asm((start), (start)+(size));
46	/* vmap range flushes and invalidates. Architecturally, we don't need
47	* the invalidate, because the CPU should refuse to speculate once an
48	* area has been flushed, so invalidate is left empty */
49	static inline void flush_kernel_vmap_range(void *vaddr, int size)
50	{
51	unsigned long start = (unsigned long)vaddr;
52
53	flush_kernel_dcache_range_asm(start, start + size);
54	}
55	static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
56	{
57	unsigned long start = (unsigned long)vaddr;
58	void *cursor = vaddr;
59		46
60	for ( ; cursor < vaddr + size; cursor += PAGE_SIZE) {	47	void flush_kernel_vmap_range(void *vaddr, int size);
61	struct page *page = vmalloc_to_page(cursor);	48	void invalidate_kernel_vmap_range(void *vaddr, int size);
62
63	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
64	flush_kernel_dcache_page(page);
65	}
66	flush_kernel_dcache_range_asm(start, start + size);
67	}
68		49
69	#define flush_cache_vmap(start, end) flush_cache_all()	50	#define flush_cache_vmap(start, end) flush_cache_all()
70	#define flush_cache_vunmap(start, end) flush_cache_all()	51	#define flush_cache_vunmap(start, end) flush_cache_all()

arch/parisc/include/asm/uaccess.h+2−1

@@ -32,7 +32,8 @@ · 31 unmodified lines
32	* that put_user is the same as __put_user, etc.	32	* that put_user is the same as __put_user, etc.
33	*/	33	*/
34		34
35	#define access_ok(type, uaddr, size) (1)	35	#define access_ok(type, uaddr, size) \
		36	( (uaddr) == (uaddr) )
36		37
37	#define put_user __put_user	38	#define put_user __put_user
38	#define get_user __get_user	39	#define get_user __get_user

arch/parisc/include/uapi/asm/unistd.h+2−1

@@ -362,8 +362,9 @@ · 361 unmodified lines
362	#define __NR_copy_file_range (__NR_Linux + 346)	362	#define __NR_copy_file_range (__NR_Linux + 346)
363	#define __NR_preadv2 (__NR_Linux + 347)	363	#define __NR_preadv2 (__NR_Linux + 347)
364	#define __NR_pwritev2 (__NR_Linux + 348)	364	#define __NR_pwritev2 (__NR_Linux + 348)
		365	#define __NR_statx (__NR_Linux + 349)
365		366
366	#define __NR_Linux_syscalls (__NR_pwritev2 + 1)	367	#define __NR_Linux_syscalls (__NR_statx + 1)
367		368
368		369
369	#define __IGNORE_select /* newselect */	370	#define __IGNORE_select /* newselect */

arch/parisc/kernel/cache.c+22−0

@@ -616,3 +616,25 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long · 615 unmodified lines
616	__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));	616	__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
617	}	617	}
618	}	618	}
		619
		620	void flush_kernel_vmap_range(void *vaddr, int size)
		621	{
		622	unsigned long start = (unsigned long)vaddr;
		623
		624	if ((unsigned long)size > parisc_cache_flush_threshold)
		625	flush_data_cache();
		626	else
		627	flush_kernel_dcache_range_asm(start, start + size);
		628	}
		629	EXPORT_SYMBOL(flush_kernel_vmap_range);
		630
		631	void invalidate_kernel_vmap_range(void *vaddr, int size)
		632	{
		633	unsigned long start = (unsigned long)vaddr;
		634
		635	if ((unsigned long)size > parisc_cache_flush_threshold)
		636	flush_data_cache();
		637	else
		638	flush_kernel_dcache_range_asm(start, start + size);
		639	}
		640	EXPORT_SYMBOL(invalidate_kernel_vmap_range);

arch/parisc/kernel/module.c+8−0

 			 */
 			*loc = fsel(val, addend);
 			break;
+		case R_PARISC_SECREL32:
+			/* 32-bit section relative address. */
+			*loc = fsel(val, addend);
+			break;
 		case R_PARISC_DPREL21L:
 			/* left 21 bit of relative address */
 			val = lrsel(val - dp, addend);
 			 */
 			*loc = fsel(val, addend);
 			break;
+		case R_PARISC_SECREL32:
+			/* 32-bit section relative address. */
+			*loc = fsel(val, addend);
+			break;
 		case R_PARISC_FPTR64:
 			/* 64-bit function address */
 			if(in_local(me, (void *)(val + addend))) {

arch/parisc/kernel/perf.c+49−45

  *  the PDC INTRIGUE calls.  This is done to eliminate bugs introduced
  *  in various PDC revisions.  The code is much more maintainable
  *  and reliable this way vs having to debug on every version of PDC
  *  on every box.
  */
 #include <linux/capability.h>
 static int perf_release(struct inode *inode, struct file *file);
 static int perf_open(struct inode *inode, struct file *file);
 static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos);
-static ssize_t perf_write(struct file *file, const char __user *buf, size_t count,
+static ssize_t perf_write(struct file *file, const char __user *buf,
-	loff_t *ppos);
+	size_t count, loff_t *ppos);
 static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 static void perf_start_counters(void);
 static int perf_stop_counters(uint32_t *raddr);
 /*
  * configure:
  *
  * Configure the cpu with a given data image.  First turn off the counters,
  * then download the image, then turn the counters back on.
  */
 static int perf_config(uint32_t *image_ptr)
 	error = perf_stop_counters(raddr);
 	if (error != 0) {
 		printk("perf_config: perf_stop_counters = %ld\n", error);
 		return -EINVAL;
 	}
 printk("Preparing to write image\n");
 	error = perf_write_image((uint64_t *)image_ptr);
 	if (error != 0) {
 		printk("perf_config: DOWNLOAD = %ld\n", error);
 		return -EINVAL;
 	}
 printk("Preparing to start counters\n");
 }
 /*
  * Open the device and initialize all of its memory.  The device is only
  * opened once, but can be "queried" by multiple processes that know its
  * file descriptor.
  */
  * called on the processor that the download should happen
  * on.
  */
-static ssize_t perf_write(struct file *file, const char __user *buf, size_t count,
+static ssize_t perf_write(struct file *file, const char __user *buf,
-	loff_t *ppos)
+	size_t count, loff_t *ppos)
 {
 	size_t image_size;
 	uint32_t image_type;
 	uint32_t interface_type;
 	uint32_t test;
 	if (perf_processor_interface == ONYX_INTF)
 		image_size = PCXU_IMAGE_SIZE;
 	else if (perf_processor_interface == CUDA_INTF)
 		image_size = PCXW_IMAGE_SIZE;
 	else
 		return -EFAULT;
 	if (!capable(CAP_SYS_ADMIN))
 	/* First check the machine type is correct for
 	   the requested image */
-        if (((perf_processor_interface == CUDA_INTF) &&
+	if (((perf_processor_interface == CUDA_INTF) &&
-		       (interface_type != CUDA_INTF)) ||
+			(interface_type != CUDA_INTF)) ||
-	    ((perf_processor_interface == ONYX_INTF) &&
+		((perf_processor_interface == ONYX_INTF) &&
-	               (interface_type != ONYX_INTF)))
+			(interface_type != ONYX_INTF)))
 		return -EINVAL;
 	/* Next check to make sure the requested image
 	   is valid */
 	if (((interface_type == CUDA_INTF) &&
 		       (test >= MAX_CUDA_IMAGES)) ||
 	    ((interface_type == ONYX_INTF) &&
 		       (test >= MAX_ONYX_IMAGES)))
 		return -EINVAL;
 	/* Copy the image into the processor */
 	if (interface_type == CUDA_INTF)
 		return perf_config(cuda_images[test]);
 	else
 		return perf_config(onyx_images[test]);
 static void perf_patch_images(void)
 {
 #if 0 /* FIXME!! */
 /*
  * NOTE:  this routine is VERY specific to the current TLB image.
  * If the image is changed, this routine might also need to be changed.
  */
 	extern void $i_dtlb_miss_2_0();
 	extern void PA2_0_iva();
 	/*
 	 * We can only use the lower 32-bits, the upper 32-bits should be 0
 	 * anyway given this is in the kernel
 	 */
 	uint32_t itlb_addr  = (uint32_t)&($i_itlb_miss_2_0);
 	uint32_t dtlb_addr  = (uint32_t)&($i_dtlb_miss_2_0);
 	if (perf_processor_interface == ONYX_INTF) {
 		/* clear last 2 bytes */
 		onyx_images[TLBMISS][15] &= 0xffffff00;
 		/* set 2 bytes */
 		onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
 		onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
 		onyx_images[TLBMISS][17] = itlb_addr;
 		/* clear last 2 bytes */
 		onyx_images[TLBHANDMISS][15] &= 0xffffff00;
 		/* set 2 bytes */
 		onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
 		onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
 		onyx_images[TLBHANDMISS][17] = itlb_addr;
 		/* clear last 2 bytes */
 		onyx_images[BIG_CPI][15] &= 0xffffff00;
 		/* set 2 bytes */
 		onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24));
 		onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
 	} else if (perf_processor_interface == CUDA_INTF) {
 		/* Cuda interface */
 		cuda_images[TLBMISS][16] =
 			(cuda_images[TLBMISS][16]&0xffff0000) |
 			((dtlb_addr >> 8)&0x0000ffff);
 		cuda_images[TLBMISS][17] =
 			((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 		cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
 		cuda_images[TLBHANDMISS][16] =
 			(cuda_images[TLBHANDMISS][16]&0xffff0000) |
 			((dtlb_addr >> 8)&0x0000ffff);
 		cuda_images[TLBHANDMISS][17] =
 			((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 		cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
 		cuda_images[BIG_CPI][16] =
 			(cuda_images[BIG_CPI][16]&0xffff0000) |
 			((dtlb_addr >> 8)&0x0000ffff);
 		cuda_images[BIG_CPI][17] =
 			((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 		cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
 	} else {
 /*
  * ioctl routine
  * All routines effect the processor that they are executed on.  Thus you
  * must be running on the processor that you wish to change.
  */
 			}
 			/* copy out the Counters */
 			if (copy_to_user((void __user *)arg, raddr,
 					sizeof (raddr)) != 0) {
 				error =  -EFAULT;
 				break;
 	.open = perf_open,
 	.release = perf_release
 };
 static struct miscdevice perf_dev = {
 	MISC_DYNAMIC_MINOR,
 	PA_PERF_DEV,
 		/* OR sticky2 (bit 1496) to counter2 bit 32 */
 		tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
 		raddr[2] = (uint32_t)tmp64;
 		/* Counter3 is bits 1497 to 1528 */
 		tmp64 =  (userbuf[23] >> 7) & 0x00000000ffffffff;
 		/* OR sticky3 (bit 1529) to counter3 bit 32 */
 		userbuf[22] = 0;
 		userbuf[23] = 0;
 		/*
 		 * Write back the zeroed bytes + the image given
 		 * the read was destructive.
 		 */
 	} else {
 		/*
 		 * Read RDR-15 which contains the counters and sticky bits
 		 */
 		if (!perf_rdr_read_ubuf(15, userbuf)) {
 			return -13;
 		}
 		/*
 		 * Clear out the counters
 		 */
 		perf_rdr_clear(15);
 		raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
 		raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
 	}
 	return 0;
 }
 	i = tentry->num_words;
 	while (i--) {
 		buffer[i] = 0;
 	}
 	/* Check for bits an even number of 64 */
 	if ((xbits = width & 0x03f) != 0) {
 	}
 	runway = ioremap_nocache(cpu_device->hpa.start, 4096);
+	if (!runway) {
+		pr_err("perf_write_image: ioremap failed!\n");
+		return -ENOMEM;
+	}
 	/* Merge intrigue bits into Runway STATUS 0 */
 	tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;
 	__raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul),
 		     runway + RUNWAY_STATUS);
 	/* Write RUNWAY DEBUG registers */
 	for (i = 0; i < 8; i++) {
 		__raw_writeq(*memaddr++, runway + RUNWAY_DEBUG);
 	}
 	return 0;
 }
 /*
 			perf_rdr_shift_out_U(rdr_num, buffer[i]);
 		} else {
 			perf_rdr_shift_out_W(rdr_num, buffer[i]);
 		}
 	}
 printk("perf_rdr_write done\n");
 }

arch/parisc/kernel/process.c+2−0

@@ -142,6 +142,8 @@ void machine_power_off(void) · 141 unmodified lines
142		142
143	printk(KERN_EMERG "System shut down completed.\n"	143	printk(KERN_EMERG "System shut down completed.\n"
144	"Please power this system off now.");	144	"Please power this system off now.");
		145
		146	for (;;);
145	}	147	}
146		148
147	void (*pm_power_off)(void) = machine_power_off;	149	void (*pm_power_off)(void) = machine_power_off;

arch/parisc/kernel/syscall_table.S+1−0

@@ -444,6 +444,7 @@ · 443 unmodified lines
444	ENTRY_SAME(copy_file_range)	444	ENTRY_SAME(copy_file_range)
445	ENTRY_COMP(preadv2)	445	ENTRY_COMP(preadv2)
446	ENTRY_COMP(pwritev2)	446	ENTRY_COMP(pwritev2)
		447	ENTRY_SAME(statx)
447		448
448		449
449	.ifne (. - 90b) - (__NR_Linux_syscalls * (91b - 90b))	450	.ifne (. - 90b) - (__NR_Linux_syscalls * (91b - 90b))

arch/powerpc/boot/zImage.lds.S+1−0

@@ -68,6 +68,7 @@ SECTIONS · 67 unmodified lines
68	}	68	}
69		69
70	#ifdef CONFIG_PPC64_BOOT_WRAPPER	70	#ifdef CONFIG_PPC64_BOOT_WRAPPER
		71	. = ALIGN(256);
71	.got :	72	.got :
72	{	73	{
73	__toc_start = .;	74	__toc_start = .;

arch/powerpc/crypto/crc32c-vpmsum_glue.c+1−1

@@ -52,7 +52,7 @@ static int crc32c_vpmsum_cra_init(struct crypto_tfm *tfm) · 51 unmodified lines
52	{	52	{
53	u32 *key = crypto_tfm_ctx(tfm);	53	u32 *key = crypto_tfm_ctx(tfm);
54		54
55	*key = 0;	55	*key = ~0;
56		56
57	return 0;	57	return 0;
58	}	58	}

arch/powerpc/include/asm/bitops.h+4−0

@@ -51,6 +51,10 @@ · 50 unmodified lines
51	#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))	51	#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
52	#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) \| PPC_BIT(bs))	52	#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) \| PPC_BIT(bs))
53		53
		54	/* Put a PPC bit into a "normal" bit position */
		55	#define PPC_BITEXTRACT(bits, ppc_bit, dst_bit) \
		56	((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit))
		57
54	#include <asm/barrier.h>	58	#include <asm/barrier.h>
55		59
56	/* Macro for generating the **_bits() functions /	60	/* Macro for generating the **_bits() functions /

arch/powerpc/include/asm/mce.h+107−1

@@ -66,6 +66,55 @@ · 65 unmodified lines
66		66
67	#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS \| \	67	#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS \| \
68	P8_DSISR_MC_ERAT_MULTIHIT_SEC)	68	P8_DSISR_MC_ERAT_MULTIHIT_SEC)
		69
		70	/*
		71	* Machine Check bits on power9
		72	*/
		73	#define P9_SRR1_MC_LOADSTORE(srr1) (((srr1) >> PPC_BITLSHIFT(42)) & 1)
		74
		75	#define P9_SRR1_MC_IFETCH(srr1) ( \
		76	PPC_BITEXTRACT(srr1, 45, 0) \| \
		77	PPC_BITEXTRACT(srr1, 44, 1) \| \
		78	PPC_BITEXTRACT(srr1, 43, 2) \| \
		79	PPC_BITEXTRACT(srr1, 36, 3) )
		80
		81	/* 0 is reserved */
		82	#define P9_SRR1_MC_IFETCH_UE 1
		83	#define P9_SRR1_MC_IFETCH_SLB_PARITY 2
		84	#define P9_SRR1_MC_IFETCH_SLB_MULTIHIT 3
		85	#define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT 4
		86	#define P9_SRR1_MC_IFETCH_TLB_MULTIHIT 5
		87	#define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD 6
		88	/* 7 is reserved */
		89	#define P9_SRR1_MC_IFETCH_LINK_TIMEOUT 8
		90	#define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT 9
		91	/* 10 ? */
		92	#define P9_SRR1_MC_IFETCH_RA 11
		93	#define P9_SRR1_MC_IFETCH_RA_TABLEWALK 12
		94	#define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE 13
		95	#define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT 14
		96	#define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN 15
		97
		98	/* DSISR bits for machine check (On Power9) */
		99	#define P9_DSISR_MC_UE (PPC_BIT(48))
		100	#define P9_DSISR_MC_UE_TABLEWALK (PPC_BIT(49))
		101	#define P9_DSISR_MC_LINK_LOAD_TIMEOUT (PPC_BIT(50))
		102	#define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT (PPC_BIT(51))
		103	#define P9_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52))
		104	#define P9_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53))
		105	#define P9_DSISR_MC_USER_TLBIE (PPC_BIT(54))
		106	#define P9_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55))
		107	#define P9_DSISR_MC_SLB_MULTIHIT_MFSLB (PPC_BIT(56))
		108	#define P9_DSISR_MC_RA_LOAD (PPC_BIT(57))
		109	#define P9_DSISR_MC_RA_TABLEWALK (PPC_BIT(58))
		110	#define P9_DSISR_MC_RA_TABLEWALK_FOREIGN (PPC_BIT(59))
		111	#define P9_DSISR_MC_RA_FOREIGN (PPC_BIT(60))
		112
		113	/* SLB error bits */
		114	#define P9_DSISR_MC_SLB_ERRORS (P9_DSISR_MC_ERAT_MULTIHIT \| \
		115	P9_DSISR_MC_SLB_PARITY_MFSLB \| \
		116	P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
		117
69	enum MCE_Version {	118	enum MCE_Version {
70	MCE_V1 = 1,	119	MCE_V1 = 1,
71	};	120	};
@@ -93,6 +142,9 @@ enum MCE_ErrorType { · 21 unmodified lines
93	MCE_ERROR_TYPE_SLB = 2,	142	MCE_ERROR_TYPE_SLB = 2,
94	MCE_ERROR_TYPE_ERAT = 3,	143	MCE_ERROR_TYPE_ERAT = 3,
95	MCE_ERROR_TYPE_TLB = 4,	144	MCE_ERROR_TYPE_TLB = 4,
		145	MCE_ERROR_TYPE_USER = 5,
		146	MCE_ERROR_TYPE_RA = 6,
		147	MCE_ERROR_TYPE_LINK = 7,
96	};	148	};
97		149
98	enum MCE_UeErrorType {	150	enum MCE_UeErrorType {
@@ -121,6 +173,32 @@ enum MCE_TlbErrorType { · 22 unmodified lines
121	MCE_TLB_ERROR_MULTIHIT = 2,	173	MCE_TLB_ERROR_MULTIHIT = 2,
122	};	174	};
123		175
		176	enum MCE_UserErrorType {
		177	MCE_USER_ERROR_INDETERMINATE = 0,
		178	MCE_USER_ERROR_TLBIE = 1,
		179	};
		180
		181	enum MCE_RaErrorType {
		182	MCE_RA_ERROR_INDETERMINATE = 0,
		183	MCE_RA_ERROR_IFETCH = 1,
		184	MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
		185	MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN = 3,
		186	MCE_RA_ERROR_LOAD = 4,
		187	MCE_RA_ERROR_STORE = 5,
		188	MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 6,
		189	MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN = 7,
		190	MCE_RA_ERROR_LOAD_STORE_FOREIGN = 8,
		191	};
		192
		193	enum MCE_LinkErrorType {
		194	MCE_LINK_ERROR_INDETERMINATE = 0,
		195	MCE_LINK_ERROR_IFETCH_TIMEOUT = 1,
		196	MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT = 2,
		197	MCE_LINK_ERROR_LOAD_TIMEOUT = 3,
		198	MCE_LINK_ERROR_STORE_TIMEOUT = 4,
		199	MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT = 5,
		200	};
		201
124	struct machine_check_event {	202	struct machine_check_event {
125	enum MCE_Version version:8; /* 0x00 */	203	enum MCE_Version version:8; /* 0x00 */
126	uint8_t in_use; /* 0x01 */	204	uint8_t in_use; /* 0x01 */
@@ -166,6 +244,30 @@ struct machine_check_event { · 39 unmodified lines
166	uint64_t effective_address;	244	uint64_t effective_address;
167	uint8_t reserved_2[16];	245	uint8_t reserved_2[16];
168	} tlb_error;	246	} tlb_error;
		247
		248	struct {
		249	enum MCE_UserErrorType user_error_type:8;
		250	uint8_t effective_address_provided;
		251	uint8_t reserved_1[6];
		252	uint64_t effective_address;
		253	uint8_t reserved_2[16];
		254	} user_error;
		255
		256	struct {
		257	enum MCE_RaErrorType ra_error_type:8;
		258	uint8_t effective_address_provided;
		259	uint8_t reserved_1[6];
		260	uint64_t effective_address;
		261	uint8_t reserved_2[16];
		262	} ra_error;
		263
		264	struct {
		265	enum MCE_LinkErrorType link_error_type:8;
		266	uint8_t effective_address_provided;
		267	uint8_t reserved_1[6];
		268	uint64_t effective_address;
		269	uint8_t reserved_2[16];
		270	} link_error;
169	} u;	271	} u;
170	};	272	};
171		273
@@ -176,8 +278,12 @@ struct mce_error_info { · 4 unmodified lines
176	enum MCE_SlbErrorType slb_error_type:8;	278	enum MCE_SlbErrorType slb_error_type:8;
177	enum MCE_EratErrorType erat_error_type:8;	279	enum MCE_EratErrorType erat_error_type:8;
178	enum MCE_TlbErrorType tlb_error_type:8;	280	enum MCE_TlbErrorType tlb_error_type:8;
		281	enum MCE_UserErrorType user_error_type:8;
		282	enum MCE_RaErrorType ra_error_type:8;
		283	enum MCE_LinkErrorType link_error_type:8;
179	} u;	284	} u;
180	uint8_t reserved[2];	285	enum MCE_Severity severity:8;
		286	enum MCE_Initiator initiator:8;
181	};	287	};
182		288
183	#define MAX_MC_EVT 100	289	#define MAX_MC_EVT 100

arch/powerpc/include/asm/systbl.h+1−0

@@ -387,3 +387,4 @@ SYSCALL(copy_file_range) · 386 unmodified lines
387	COMPAT_SYS_SPU(preadv2)	387	COMPAT_SYS_SPU(preadv2)
388	COMPAT_SYS_SPU(pwritev2)	388	COMPAT_SYS_SPU(pwritev2)
389	SYSCALL(kexec_file_load)	389	SYSCALL(kexec_file_load)
		390	SYSCALL(statx)

arch/powerpc/include/asm/unistd.h+1−1

@@ -12,7 +12,7 @@ · 11 unmodified lines
12	#include <uapi/asm/unistd.h>	12	#include <uapi/asm/unistd.h>
13		13
14		14
15	#define NR_syscalls 383	15	#define NR_syscalls 384
16		16
17	#define __NR__exit __NR_exit	17	#define __NR__exit __NR_exit
18		18

arch/powerpc/include/uapi/asm/unistd.h+1−0

@@ -393,5 +393,6 @@ · 392 unmodified lines
393	#define __NR_preadv2 380	393	#define __NR_preadv2 380
394	#define __NR_pwritev2 381	394	#define __NR_pwritev2 381
395	#define __NR_kexec_file_load 382	395	#define __NR_kexec_file_load 382
		396	#define __NR_statx 383
396		397
397	#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */	398	#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */

arch/powerpc/kernel/cputable.c+3−0

 extern void __flush_tlb_power9(unsigned int action);
 extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
 extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
 #endif /* CONFIG_PPC64 */
 #if defined(CONFIG_E500)
 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
 		.cpu_setup		= __setup_cpu_power9,
 		.cpu_restore		= __restore_cpu_power9,
 		.flush_tlb		= __flush_tlb_power9,
+		.machine_check_early	= __machine_check_early_realmode_p9,
 		.platform		= "power9",
 	},
 	{	/* Power9 */
 		.cpu_setup		= __setup_cpu_power9,
 		.cpu_restore		= __restore_cpu_power9,
 		.flush_tlb		= __flush_tlb_power9,
+		.machine_check_early	= __machine_check_early_realmode_p9,
 		.platform		= "power9",
 	},
 	{	/* Cell Broadband Engine */

arch/powerpc/kernel/idle_book3s.S+17−3

@@ -449,9 +449,23 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) · 448 unmodified lines
449	_GLOBAL(pnv_wakeup_tb_loss)	449	_GLOBAL(pnv_wakeup_tb_loss)
450	ld r1,PACAR1(r13)	450	ld r1,PACAR1(r13)
451	/*	451	/*
452	* Before entering any idle state, the NVGPRs are saved in the stack	452	* Before entering any idle state, the NVGPRs are saved in the stack.
453	* and they are restored before switching to the process context. Hence	453	* If there was a state loss, or PACA_NAPSTATELOST was set, then the
454	* until they are restored, they are free to be used.	454	* NVGPRs are restored. If we are here, it is likely that state is lost,
		455	* but not guaranteed -- neither ISA207 nor ISA300 tests to reach
		456	* here are the same as the test to restore NVGPRS:
		457	* PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
		458	* and SRR1 test for restoring NVGPRs.
		459	*
		460	* We are about to clobber NVGPRs now, so set NAPSTATELOST to
		461	* guarantee they will always be restored. This might be tightened
		462	* with careful reading of specs (particularly for ISA300) but this
		463	* is already a slow wakeup path and it's simpler to be safe.
		464	*/
		465	li r0,1
		466	stb r0,PACA_NAPSTATELOST(r13)
		467
		468	/*
455	*	469	*
456	* Save SRR1 and LR in NVGPRs as they might be clobbered in	470	* Save SRR1 and LR in NVGPRs as they might be clobbered in
457	* opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required	471	* opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required

arch/powerpc/kernel/mce.c+86−2

@@ -58,6 +58,15 @@ static void mce_set_error_info(struct machine_check_event *mce, · 57 unmodified lines
58	case MCE_ERROR_TYPE_TLB:	58	case MCE_ERROR_TYPE_TLB:
59	mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;	59	mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;
60	break;	60	break;
		61	case MCE_ERROR_TYPE_USER:
		62	mce->u.user_error.user_error_type = mce_err->u.user_error_type;
		63	break;
		64	case MCE_ERROR_TYPE_RA:
		65	mce->u.ra_error.ra_error_type = mce_err->u.ra_error_type;
		66	break;
		67	case MCE_ERROR_TYPE_LINK:
		68	mce->u.link_error.link_error_type = mce_err->u.link_error_type;
		69	break;
61	case MCE_ERROR_TYPE_UNKNOWN:	70	case MCE_ERROR_TYPE_UNKNOWN:
62	default:	71	default:
63	break;	72	break;
@@ -90,13 +99,14 @@ void save_mce_event(struct pt_regs *regs, long handled, · 26 unmodified lines
90	mce->gpr3 = regs->gpr[3];	99	mce->gpr3 = regs->gpr[3];
91	mce->in_use = 1;	100	mce->in_use = 1;
92		101
93	mce->initiator = MCE_INITIATOR_CPU;
94	/* Mark it recovered if we have handled it and MSR(RI=1). */	102	/* Mark it recovered if we have handled it and MSR(RI=1). */
95	if (handled && (regs->msr & MSR_RI))	103	if (handled && (regs->msr & MSR_RI))
96	mce->disposition = MCE_DISPOSITION_RECOVERED;	104	mce->disposition = MCE_DISPOSITION_RECOVERED;
97	else	105	else
98	mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;	106	mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;
99	mce->severity = MCE_SEV_ERROR_SYNC;	107
		108	mce->initiator = mce_err->initiator;
		109	mce->severity = mce_err->severity;
100		110
101	/*	111	/*
102	* Populate the mce error_type and type-specific error_type.	112	* Populate the mce error_type and type-specific error_type.
@@ -115,6 +125,15 @@ void save_mce_event(struct pt_regs *regs, long handled, · 12 unmodified lines
115	} else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {	125	} else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {
116	mce->u.erat_error.effective_address_provided = true;	126	mce->u.erat_error.effective_address_provided = true;
117	mce->u.erat_error.effective_address = addr;	127	mce->u.erat_error.effective_address = addr;
		128	} else if (mce->error_type == MCE_ERROR_TYPE_USER) {
		129	mce->u.user_error.effective_address_provided = true;
		130	mce->u.user_error.effective_address = addr;
		131	} else if (mce->error_type == MCE_ERROR_TYPE_RA) {
		132	mce->u.ra_error.effective_address_provided = true;
		133	mce->u.ra_error.effective_address = addr;
		134	} else if (mce->error_type == MCE_ERROR_TYPE_LINK) {
		135	mce->u.link_error.effective_address_provided = true;
		136	mce->u.link_error.effective_address = addr;
118	} else if (mce->error_type == MCE_ERROR_TYPE_UE) {	137	} else if (mce->error_type == MCE_ERROR_TYPE_UE) {
119	mce->u.ue_error.effective_address_provided = true;	138	mce->u.ue_error.effective_address_provided = true;
120	mce->u.ue_error.effective_address = addr;	139	mce->u.ue_error.effective_address = addr;
@@ -239,6 +258,29 @@ void machine_check_print_event_info(struct machine_check_event *evt) · 118 unmodified lines
239	"Parity",	258	"Parity",
240	"Multihit",	259	"Multihit",
241	};	260	};
		261	static const char *mc_user_types[] = {
		262	"Indeterminate",
		263	"tlbie(l) invalid",
		264	};
		265	static const char *mc_ra_types[] = {
		266	"Indeterminate",
		267	"Instruction fetch (bad)",
		268	"Page table walk ifetch (bad)",
		269	"Page table walk ifetch (foreign)",
		270	"Load (bad)",
		271	"Store (bad)",
		272	"Page table walk Load/Store (bad)",
		273	"Page table walk Load/Store (foreign)",
		274	"Load/Store (foreign)",
		275	};
		276	static const char *mc_link_types[] = {
		277	"Indeterminate",
		278	"Instruction fetch (timeout)",
		279	"Page table walk ifetch (timeout)",
		280	"Load (timeout)",
		281	"Store (timeout)",
		282	"Page table walk Load/Store (timeout)",
		283	};
242		284
243	/* Print things out */	285	/* Print things out */
244	if (evt->version != MCE_V1) {	286	if (evt->version != MCE_V1) {
@@ -315,6 +357,36 @@ void machine_check_print_event_info(struct machine_check_event *evt) · 70 unmodified lines
315	printk("%s Effective address: %016llx\n",	357	printk("%s Effective address: %016llx\n",
316	level, evt->u.tlb_error.effective_address);	358	level, evt->u.tlb_error.effective_address);
317	break;	359	break;
		360	case MCE_ERROR_TYPE_USER:
		361	subtype = evt->u.user_error.user_error_type <
		362	ARRAY_SIZE(mc_user_types) ?
		363	mc_user_types[evt->u.user_error.user_error_type]
		364	: "Unknown";
		365	printk("%s Error type: User [%s]\n", level, subtype);
		366	if (evt->u.user_error.effective_address_provided)
		367	printk("%s Effective address: %016llx\n",
		368	level, evt->u.user_error.effective_address);
		369	break;
		370	case MCE_ERROR_TYPE_RA:
		371	subtype = evt->u.ra_error.ra_error_type <
		372	ARRAY_SIZE(mc_ra_types) ?
		373	mc_ra_types[evt->u.ra_error.ra_error_type]
		374	: "Unknown";
		375	printk("%s Error type: Real address [%s]\n", level, subtype);
		376	if (evt->u.ra_error.effective_address_provided)
		377	printk("%s Effective address: %016llx\n",
		378	level, evt->u.ra_error.effective_address);
		379	break;
		380	case MCE_ERROR_TYPE_LINK:
		381	subtype = evt->u.link_error.link_error_type <
		382	ARRAY_SIZE(mc_link_types) ?
		383	mc_link_types[evt->u.link_error.link_error_type]
		384	: "Unknown";
		385	printk("%s Error type: Link [%s]\n", level, subtype);
		386	if (evt->u.link_error.effective_address_provided)
		387	printk("%s Effective address: %016llx\n",
		388	level, evt->u.link_error.effective_address);
		389	break;
318	default:	390	default:
319	case MCE_ERROR_TYPE_UNKNOWN:	391	case MCE_ERROR_TYPE_UNKNOWN:
320	printk("%s Error type: Unknown\n", level);	392	printk("%s Error type: Unknown\n", level);
@@ -341,6 +413,18 @@ uint64_t get_mce_fault_addr(struct machine_check_event *evt) · 20 unmodified lines
341	if (evt->u.tlb_error.effective_address_provided)	413	if (evt->u.tlb_error.effective_address_provided)
342	return evt->u.tlb_error.effective_address;	414	return evt->u.tlb_error.effective_address;
343	break;	415	break;
		416	case MCE_ERROR_TYPE_USER:
		417	if (evt->u.user_error.effective_address_provided)
		418	return evt->u.user_error.effective_address;
		419	break;
		420	case MCE_ERROR_TYPE_RA:
		421	if (evt->u.ra_error.effective_address_provided)
		422	return evt->u.ra_error.effective_address;
		423	break;
		424	case MCE_ERROR_TYPE_LINK:
		425	if (evt->u.link_error.effective_address_provided)
		426	return evt->u.link_error.effective_address;
		427	break;
344	default:	428	default:
345	case MCE_ERROR_TYPE_UNKNOWN:	429	case MCE_ERROR_TYPE_UNKNOWN:
346	break;	430	break;

arch/powerpc/kernel/mce_power.c+237−0

@@ -116,6 +116,51 @@ static void flush_and_reload_slb(void) · 115 unmodified lines
116	}	116	}
117	#endif	117	#endif
118		118
		119	static void flush_erat(void)
		120	{
		121	asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
		122	}
		123
		124	#define MCE_FLUSH_SLB 1
		125	#define MCE_FLUSH_TLB 2
		126	#define MCE_FLUSH_ERAT 3
		127
		128	static int mce_flush(int what)
		129	{
		130	#ifdef CONFIG_PPC_STD_MMU_64
		131	if (what == MCE_FLUSH_SLB) {
		132	flush_and_reload_slb();
		133	return 1;
		134	}
		135	#endif
		136	if (what == MCE_FLUSH_ERAT) {
		137	flush_erat();
		138	return 1;
		139	}
		140	if (what == MCE_FLUSH_TLB) {
		141	if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
		142	cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
		143	return 1;
		144	}
		145	}
		146
		147	return 0;
		148	}
		149
		150	static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat)
		151	{
		152	if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB))
		153	dsisr &= ~slb;
		154	if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT))
		155	dsisr &= ~erat;
		156	if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB))
		157	dsisr &= ~tlb;
		158	/* Any other errors we don't understand? */
		159	if (dsisr)
		160	return 0;
		161	return 1;
		162	}
		163
119	static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)	164	static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
120	{	165	{
121	long handled = 1;	166	long handled = 1;
@@ -281,6 +326,9 @@ long __machine_check_early_realmode_p7(struct pt_regs *regs) · 159 unmodified lines
281	long handled = 1;	326	long handled = 1;
282	struct mce_error_info mce_error_info = { 0 };	327	struct mce_error_info mce_error_info = { 0 };
283		328
		329	mce_error_info.severity = MCE_SEV_ERROR_SYNC;
		330	mce_error_info.initiator = MCE_INITIATOR_CPU;
		331
284	srr1 = regs->msr;	332	srr1 = regs->msr;
285	nip = regs->nip;	333	nip = regs->nip;
286		334
@@ -352,6 +400,9 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) · 65 unmodified lines
352	long handled = 1;	400	long handled = 1;
353	struct mce_error_info mce_error_info = { 0 };	401	struct mce_error_info mce_error_info = { 0 };
354		402
		403	mce_error_info.severity = MCE_SEV_ERROR_SYNC;
		404	mce_error_info.initiator = MCE_INITIATOR_CPU;
		405
355	srr1 = regs->msr;	406	srr1 = regs->msr;
356	nip = regs->nip;	407	nip = regs->nip;
357		408
@@ -372,3 +423,189 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) · 14 unmodified lines
372	save_mce_event(regs, handled, &mce_error_info, nip, addr);	423	save_mce_event(regs, handled, &mce_error_info, nip, addr);
373	return handled;	424	return handled;
374	}	425	}
		426
		427	static int mce_handle_derror_p9(struct pt_regs *regs)
		428	{
		429	uint64_t dsisr = regs->dsisr;
		430
		431	return mce_handle_flush_derrors(dsisr,
		432	P9_DSISR_MC_SLB_PARITY_MFSLB \|
		433	P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
		434
		435	P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
		436
		437	P9_DSISR_MC_ERAT_MULTIHIT);
		438	}
		439
		440	static int mce_handle_ierror_p9(struct pt_regs *regs)
		441	{
		442	uint64_t srr1 = regs->msr;
		443
		444	switch (P9_SRR1_MC_IFETCH(srr1)) {
		445	case P9_SRR1_MC_IFETCH_SLB_PARITY:
		446	case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
		447	return mce_flush(MCE_FLUSH_SLB);
		448	case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
		449	return mce_flush(MCE_FLUSH_TLB);
		450	case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
		451	return mce_flush(MCE_FLUSH_ERAT);
		452	default:
		453	return 0;
		454	}
		455	}
		456
		457	static void mce_get_derror_p9(struct pt_regs *regs,
		458	struct mce_error_info mce_err, uint64_t addr)
		459	{
		460	uint64_t dsisr = regs->dsisr;
		461
		462	mce_err->severity = MCE_SEV_ERROR_SYNC;
		463	mce_err->initiator = MCE_INITIATOR_CPU;
		464
		465	if (dsisr & P9_DSISR_MC_USER_TLBIE)
		466	*addr = regs->nip;
		467	else
		468	*addr = regs->dar;
		469
		470	if (dsisr & P9_DSISR_MC_UE) {
		471	mce_err->error_type = MCE_ERROR_TYPE_UE;
		472	mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
		473	} else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
		474	mce_err->error_type = MCE_ERROR_TYPE_UE;
		475	mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
		476	} else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
		477	mce_err->error_type = MCE_ERROR_TYPE_LINK;
		478	mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
		479	} else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
		480	mce_err->error_type = MCE_ERROR_TYPE_LINK;
		481	mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
		482	} else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
		483	mce_err->error_type = MCE_ERROR_TYPE_ERAT;
		484	mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
		485	} else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
		486	mce_err->error_type = MCE_ERROR_TYPE_TLB;
		487	mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
		488	} else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
		489	mce_err->error_type = MCE_ERROR_TYPE_USER;
		490	mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
		491	} else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
		492	mce_err->error_type = MCE_ERROR_TYPE_SLB;
		493	mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
		494	} else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
		495	mce_err->error_type = MCE_ERROR_TYPE_SLB;
		496	mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
		497	} else if (dsisr & P9_DSISR_MC_RA_LOAD) {
		498	mce_err->error_type = MCE_ERROR_TYPE_RA;
		499	mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
		500	} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
		501	mce_err->error_type = MCE_ERROR_TYPE_RA;
		502	mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
		503	} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
		504	mce_err->error_type = MCE_ERROR_TYPE_RA;
		505	mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
		506	} else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
		507	mce_err->error_type = MCE_ERROR_TYPE_RA;
		508	mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
		509	}
		510	}
		511
		512	static void mce_get_ierror_p9(struct pt_regs *regs,
		513	struct mce_error_info mce_err, uint64_t addr)
		514	{
		515	uint64_t srr1 = regs->msr;
		516
		517	switch (P9_SRR1_MC_IFETCH(srr1)) {
		518	case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
		519	case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
		520	mce_err->severity = MCE_SEV_FATAL;
		521	break;
		522	default:
		523	mce_err->severity = MCE_SEV_ERROR_SYNC;
		524	break;
		525	}
		526
		527	mce_err->initiator = MCE_INITIATOR_CPU;
		528
		529	*addr = regs->nip;
		530
		531	switch (P9_SRR1_MC_IFETCH(srr1)) {
		532	case P9_SRR1_MC_IFETCH_UE:
		533	mce_err->error_type = MCE_ERROR_TYPE_UE;
		534	mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
		535	break;
		536	case P9_SRR1_MC_IFETCH_SLB_PARITY:
		537	mce_err->error_type = MCE_ERROR_TYPE_SLB;
		538	mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
		539	break;
		540	case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
		541	mce_err->error_type = MCE_ERROR_TYPE_SLB;
		542	mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
		543	break;
		544	case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
		545	mce_err->error_type = MCE_ERROR_TYPE_ERAT;
		546	mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
		547	break;
		548	case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
		549	mce_err->error_type = MCE_ERROR_TYPE_TLB;
		550	mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
		551	break;
		552	case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
		553	mce_err->error_type = MCE_ERROR_TYPE_UE;
		554	mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
		555	break;
		556	case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
		557	mce_err->error_type = MCE_ERROR_TYPE_LINK;
		558	mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
		559	break;
		560	case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
		561	mce_err->error_type = MCE_ERROR_TYPE_LINK;
		562	mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
		563	break;
		564	case P9_SRR1_MC_IFETCH_RA:
		565	mce_err->error_type = MCE_ERROR_TYPE_RA;
		566	mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
		567	break;
		568	case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
		569	mce_err->error_type = MCE_ERROR_TYPE_RA;
		570	mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
		571	break;
		572	case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
		573	mce_err->error_type = MCE_ERROR_TYPE_RA;
		574	mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
		575	break;
		576	case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
		577	mce_err->error_type = MCE_ERROR_TYPE_LINK;
		578	mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
		579	break;
		580	case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
		581	mce_err->error_type = MCE_ERROR_TYPE_RA;
		582	mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
		583	break;
		584	default:
		585	break;
		586	}
		587	}
		588
		589	long __machine_check_early_realmode_p9(struct pt_regs *regs)
		590	{
		591	uint64_t nip, addr;
		592	long handled;
		593	struct mce_error_info mce_error_info = { 0 };
		594
		595	nip = regs->nip;
		596
		597	if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
		598	handled = mce_handle_derror_p9(regs);
		599	mce_get_derror_p9(regs, &mce_error_info, &addr);
		600	} else {
		601	handled = mce_handle_ierror_p9(regs);
		602	mce_get_ierror_p9(regs, &mce_error_info, &addr);
		603	}
		604
		605	/* Handle UE error. */
		606	if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
		607	handled = mce_handle_ue_error(regs);
		608
		609	save_mce_event(regs, handled, &mce_error_info, nip, addr);
		610	return handled;
		611	}

arch/powerpc/mm/init_64.c+1−2

@@ -397,8 +397,7 @@ static void early_check_vec5(void) · 396 unmodified lines
397	void __init mmu_early_init_devtree(void)	397	void __init mmu_early_init_devtree(void)
398	{	398	{
399	/* Disable radix mode based on kernel command line. */	399	/* Disable radix mode based on kernel command line. */
400	/* We don't yet have the machinery to do radix as a guest. */	400	if (disable_radix)
401	if (disable_radix \|\| !(mfmsr() & MSR_HV))
402	cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;	401	cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;
403		402
404	/*	403	/*

arch/powerpc/perf/core-book3s.c+2−0

@@ -188,6 +188,8 @@ static inline void perf_get_data_addr(struct pt_regs regs, u64 addrp) · 187 unmodified lines
188	sdsync = POWER7P_MMCRA_SDAR_VALID;	188	sdsync = POWER7P_MMCRA_SDAR_VALID;
189	else if (ppmu->flags & PPMU_ALT_SIPR)	189	else if (ppmu->flags & PPMU_ALT_SIPR)
190	sdsync = POWER6_MMCRA_SDSYNC;	190	sdsync = POWER6_MMCRA_SDSYNC;
		191	else if (ppmu->flags & PPMU_NO_SIAR)
		192	sdsync = MMCRA_SAMPLE_ENABLE;
191	else	193	else
192	sdsync = MMCRA_SDSYNC;	194	sdsync = MMCRA_SDSYNC;
193		195

arch/powerpc/perf/isa207-common.c+36−7

 	return !(event & ~valid_mask);
 }
-static u64 mmcra_sdar_mode(u64 event)
+static inline bool is_event_marked(u64 event)
 {
-	if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
+	if (event & EVENT_IS_MARKED)
-		return p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
+		return true;
+	return false;
+}
-	return MMCRA_SDAR_MODE_TLB;
+static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
+{
+	/*
+	 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
+	 * continous sampling mode.
+	 *
+	 * Incase of Power8:
+	 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling
+	 * mode and will be un-changed when setting MMCRA[63] (Marked events).
+	 *
+	 * Incase of Power9:
+	 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
+	 *               or if group already have any marked events.
+	 * Non-Marked events (for DD1):
+	 *	MMCRA[SDAR_MODE] will be set to 0b01
+	 * For rest
+	 *	MMCRA[SDAR_MODE] will be set from event code.
+	 */
+	if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+		if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
+			*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
+		else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
+			*mmcra |=  p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
+		else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+			*mmcra |= MMCRA_SDAR_MODE_TLB;
+	} else
+		*mmcra |= MMCRA_SDAR_MODE_TLB;
 }
 static u64 thresh_cmp_val(u64 value)
 		value |= CNST_L1_QUAL_VAL(cache);
 	}
-	if (event & EVENT_IS_MARKED) {
+	if (is_event_marked(event)) {
 		mask  |= CNST_SAMPLE_MASK;
 		value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
 	}
 		}
 		/* In continuous sampling mode, update SDAR on TLB miss */
-		mmcra |= mmcra_sdar_mode(event[i]);
+		mmcra_sdar_mode(event[i], &mmcra);
 		if (event[i] & EVENT_IS_L1) {
 			cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
 			mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
 		}
-		if (event[i] & EVENT_IS_MARKED) {
+		if (is_event_marked(event[i])) {
 			mmcra |= MMCRA_SAMPLE_ENABLE;
 			val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;

arch/powerpc/perf/isa207-common.h+1−0

@@ -246,6 +246,7 @@ · 245 unmodified lines
246	#define MMCRA_THR_CMP_SHIFT 32	246	#define MMCRA_THR_CMP_SHIFT 32
247	#define MMCRA_SDAR_MODE_SHIFT 42	247	#define MMCRA_SDAR_MODE_SHIFT 42
248	#define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)	248	#define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)
		249	#define MMCRA_SDAR_MODE_NO_UPDATES ~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
249	#define MMCRA_IFM_SHIFT 30	250	#define MMCRA_IFM_SHIFT 30
250		251
251	/* MMCR1 Threshold Compare bit constant for power9 */	252	/* MMCR1 Threshold Compare bit constant for power9 */

arch/powerpc/platforms/powernv/opal.c+6−15

 					struct machine_check_event *evt)
 {
 	int recovered = 0;
-	uint64_t ea = get_mce_fault_addr(evt);
 	if (!(regs->msr & MSR_RI)) {
 		/* If MSR_RI isn't set, we cannot recover */
 	} else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
 		/* Platform corrected itself */
 		recovered = 1;
-	} else if (ea && !is_kernel_addr(ea)) {
+	} else if (evt->severity == MCE_SEV_FATAL) {
+		/* Fatal machine check */
+		pr_err("Machine check interrupt is fatal\n");
+		recovered = 0;
+	} else if ((evt->severity == MCE_SEV_ERROR_SYNC) &&
+			(user_mode(regs) && !is_global_init(current))) {
 		/*
-		 * Faulting address is not in kernel text. We should be fine.
-		 * We need to find which process uses this address.
 		 * For now, kill the task if we have received exception when
 		 * in userspace.
 		 *
 		 * TODO: Queue up this address for hwpoisioning later.
 		 */
-		if (user_mode(regs) && !is_global_init(current)) {
-			_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
-			recovered = 1;
-		} else
-			recovered = 0;
-	} else if (user_mode(regs) && !is_global_init(current) &&
-		evt->severity == MCE_SEV_ERROR_SYNC) {
-		/*
-		 * If we have received a synchronous error when in userspace
-		 * kill the task.
-		 */
 		_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
 		recovered = 1;
 	}

arch/powerpc/platforms/powernv/pci-ioda.c+15−5

 }
 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
-				   struct pci_bus *bus)
+				   struct pci_bus *bus,
+				   bool add_to_group)
 {
 	struct pci_dev *dev;
 	list_for_each_entry(dev, &bus->devices, bus_list) {
 		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
 		set_dma_offset(&dev->dev, pe->tce_bypass_base);
-		iommu_add_device(&dev->dev);
+		if (add_to_group)
+			iommu_add_device(&dev->dev);
 		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
-			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
+			pnv_ioda_setup_bus_dma(pe, dev->subordinate,
+					add_to_group);
 	}
 }
 		set_iommu_table_base(&pe->pdev->dev, tbl);
 		iommu_add_device(&pe->pdev->dev);
 	} else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
-		pnv_ioda_setup_bus_dma(pe, pe->pbus);
+		pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
 	return;
  fail:
 	pnv_pci_ioda2_set_bypass(pe, false);
 	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
+	if (pe->pbus)
+		pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
 	pnv_ioda2_table_free(tbl);
 }
 						table_group);
 	pnv_pci_ioda2_setup_default_config(pe);
+	if (pe->pbus)
+		pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
 }
 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
 	level_shift = entries_shift + 3;
 	level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
+	if ((level_shift - 3) * levels + page_shift >= 60)
+		return -EINVAL;
 	/* Allocate TCE table */
 	addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
 			levels, tce_table_size, &offset, &total_allocated);
 	if (pe->flags & PNV_IODA_PE_DEV)
 		iommu_add_device(&pe->pdev->dev);
 	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
-		pnv_ioda_setup_bus_dma(pe, pe->pbus);
+		pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
 }
 #ifdef CONFIG_PCI_MSI

arch/powerpc/platforms/pseries/lpar.c+3−1

@@ -751,7 +751,9 @@ void __init hpte_init_pseries(void) · 750 unmodified lines
751	mmu_hash_ops.flush_hash_range = pSeries_lpar_flush_hash_range;	751	mmu_hash_ops.flush_hash_range = pSeries_lpar_flush_hash_range;
752	mmu_hash_ops.hpte_clear_all = pseries_hpte_clear_all;	752	mmu_hash_ops.hpte_clear_all = pseries_hpte_clear_all;
753	mmu_hash_ops.hugepage_invalidate = pSeries_lpar_hugepage_invalidate;	753	mmu_hash_ops.hugepage_invalidate = pSeries_lpar_hugepage_invalidate;
754	mmu_hash_ops.resize_hpt = pseries_lpar_resize_hpt;	754
		755	if (firmware_has_feature(FW_FEATURE_HPT_RESIZE))
		756	mmu_hash_ops.resize_hpt = pseries_lpar_resize_hpt;
755	}	757	}
756		758
757	void radix_init_pseries(void)	759	void radix_init_pseries(void)

arch/x86/events/core.c+14−2

 static void refresh_pce(void *ignored)
 {
-	if (current->mm)
+	if (current->active_mm)
-		load_mm_cr4(current->mm);
+		load_mm_cr4(current->active_mm);
 }
 static void x86_pmu_event_mapped(struct perf_event *event)
 	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
 		return;
+	/*
+	 * This function relies on not being called concurrently in two
+	 * tasks in the same mm.  Otherwise one task could observe
+	 * perf_rdpmc_allowed > 1 and return all the way back to
+	 * userspace with CR4.PCE clear while another task is still
+	 * doing on_each_cpu_mask() to propagate CR4.PCE.
+	 *
+	 * For now, this can't happen because all callers hold mmap_sem
+	 * for write.  If this changes, we'll need a different solution.
+	 */
+	lockdep_assert_held_exclusive(&current->mm->mmap_sem);
 	if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
 		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
 }

arch/x86/include/asm/pgtable-3level.h+0−3

 	*(tmp + 1) = 0;
 }
-#if !defined(CONFIG_SMP) || (defined(CONFIG_HIGHMEM64G) && \
-		defined(CONFIG_PARAVIRT))
 static inline void native_pud_clear(pud_t *pudp)
 {
 }
-#endif
 static inline void pud_clear(pud_t *pudp)
 {

arch/x86/include/asm/pgtable.h+1−1

@@ -62,7 +62,7 @@ extern struct mm_struct pgd_page_get_mm(struct page page); · 61 unmodified lines
62	# define set_pud(pudp, pud) native_set_pud(pudp, pud)	62	# define set_pud(pudp, pud) native_set_pud(pudp, pud)
63	#endif	63	#endif
64		64
65	#ifndef __PAGETABLE_PMD_FOLDED	65	#ifndef __PAGETABLE_PUD_FOLDED
66	#define pud_clear(pud) native_pud_clear(pud)	66	#define pud_clear(pud) native_pud_clear(pud)
67	#endif	67	#endif
68		68

arch/x86/include/asm/pmem.h+31−11

  * @size:	number of bytes to write back
  *
  * Write back a cache range using the CLWB (cache line write back)
- * instruction.
+ * instruction. Note that @size is internally rounded up to be cache
+ * line size aligned.
  */
 static inline void arch_wb_cache_pmem(void *addr, size_t size)
 {
 		clwb(p);
 }
-/*
- * copy_from_iter_nocache() on x86 only uses non-temporal stores for iovec
- * iterators, so for other types (bvec & kvec) we must do a cache write-back.
- */
-static inline bool __iter_needs_pmem_wb(struct iov_iter *i)
-{
-	return iter_is_iovec(i) == false;
-}
 /**
  * arch_copy_from_iter_pmem - copy data from an iterator to PMEM
  * @addr:	PMEM destination address
 	/* TODO: skip the write-back by always using non-temporal stores */
 	len = copy_from_iter_nocache(addr, bytes, i);
-	if (__iter_needs_pmem_wb(i))
+	/*
+	 * In the iovec case on x86_64 copy_from_iter_nocache() uses
+	 * non-temporal stores for the bulk of the transfer, but we need
+	 * to manually flush if the transfer is unaligned. A cached
+	 * memory copy is used when destination or size is not naturally
+	 * aligned. That is:
+	 *   - Require 8-byte alignment when size is 8 bytes or larger.
+	 *   - Require 4-byte alignment when size is 4 bytes.
+	 *
+	 * In the non-iovec case the entire destination needs to be
+	 * flushed.
+	 */
+	if (iter_is_iovec(i)) {
+		unsigned long flushed, dest = (unsigned long) addr;
+		if (bytes < 8) {
+			if (!IS_ALIGNED(dest, 4) || (bytes != 4))
+				arch_wb_cache_pmem(addr, 1);
+		} else {
+			if (!IS_ALIGNED(dest, 8)) {
+				dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);
+				arch_wb_cache_pmem(addr, 1);
+			}
+			flushed = dest - (unsigned long) addr;
+			if (bytes > flushed && !IS_ALIGNED(bytes - flushed, 8))
+				arch_wb_cache_pmem(addr + bytes - 1, 1);
+		}
+	} else
 		arch_wb_cache_pmem(addr, bytes);
 	return len;

arch/x86/kernel/acpi/boot.c+7−2

 		return -EINVAL;
 	}
+	if (!enabled) {
+		++disabled_cpus;
+		return -EINVAL;
+	}
 	if (boot_cpu_physical_apicid != -1U)
 		ver = boot_cpu_apic_version;
-	cpu = __generic_processor_info(id, ver, enabled);
+	cpu = generic_processor_info(id, ver);
 	if (cpu >= 0)
 		early_per_cpu(x86_cpu_to_acpiid, cpu) = acpiid;
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 #include <acpi/processor.h>
-int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
+static int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
 {
 #ifdef CONFIG_ACPI_NUMA
 	int nid;

arch/x86/kernel/apic/apic.c+7−19

@@ -2063,7 +2063,7 @@ static int allocate_logical_cpuid(int apicid) · 2062 unmodified lines
2063	return nr_logical_cpuids++;	2063	return nr_logical_cpuids++;
2064	}	2064	}
2065		2065
2066	int __generic_processor_info(int apicid, int version, bool enabled)	2066	int generic_processor_info(int apicid, int version)
2067	{	2067	{
2068	int cpu, max = nr_cpu_ids;	2068	int cpu, max = nr_cpu_ids;
2069	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,	2069	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
@@ -2121,11 +2121,9 @@ int __generic_processor_info(int apicid, int version, bool enabled) · 51 unmodified lines
2121	if (num_processors >= nr_cpu_ids) {	2121	if (num_processors >= nr_cpu_ids) {
2122	int thiscpu = max + disabled_cpus;	2122	int thiscpu = max + disabled_cpus;
2123		2123
2124	if (enabled) {	2124	pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2125	pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "	2125	"reached. Processor %d/0x%x ignored.\n",
2126	"reached. Processor %d/0x%x ignored.\n",	2126	max, thiscpu, apicid);
2127	max, thiscpu, apicid);
2128	}
2129		2127
2130	disabled_cpus++;	2128	disabled_cpus++;
2131	return -EINVAL;	2129	return -EINVAL;
@@ -2177,23 +2175,13 @@ int __generic_processor_info(int apicid, int version, bool enabled) · 45 unmodified lines
2177	apic->x86_32_early_logical_apicid(cpu);	2175	apic->x86_32_early_logical_apicid(cpu);
2178	#endif	2176	#endif
2179	set_cpu_possible(cpu, true);	2177	set_cpu_possible(cpu, true);
2180		2178	physid_set(apicid, phys_cpu_present_map);
2181	if (enabled) {	2179	set_cpu_present(cpu, true);
2182	num_processors++;	2180	num_processors++;
2183	physid_set(apicid, phys_cpu_present_map);
2184	set_cpu_present(cpu, true);
2185	} else {
2186	disabled_cpus++;
2187	}
2188		2181
2189	return cpu;	2182	return cpu;
2190	}	2183	}
2191		2184
2192	int generic_processor_info(int apicid, int version)
2193	{
2194	return __generic_processor_info(apicid, version, true);
2195	}
2196
2197	int hard_smp_processor_id(void)	2185	int hard_smp_processor_id(void)
2198	{	2186	{
2199	return read_apic_id();	2187	return read_apic_id();

arch/x86/kernel/cpu/intel_rdt_rdtgroup.c+1−1

@@ -727,7 +727,7 @@ void rdtgroup_kn_unlock(struct kernfs_node *kn) · 726 unmodified lines
727	if (atomic_dec_and_test(&rdtgrp->waitcount) &&	727	if (atomic_dec_and_test(&rdtgrp->waitcount) &&
728	(rdtgrp->flags & RDT_DELETED)) {	728	(rdtgrp->flags & RDT_DELETED)) {
729	kernfs_unbreak_active_protection(kn);	729	kernfs_unbreak_active_protection(kn);
730	kernfs_put(kn);	730	kernfs_put(rdtgrp->kn);
731	kfree(rdtgrp);	731	kfree(rdtgrp);
732	} else {	732	} else {
733	kernfs_unbreak_active_protection(kn);	733	kernfs_unbreak_active_protection(kn);

arch/x86/kernel/head64.c+1−0

@@ -4,6 +4,7 @@ · 3 unmodified lines
4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5	*/	5	*/
6		6
		7	#define DISABLE_BRANCH_PROFILING
7	#include <linux/init.h>	8	#include <linux/init.h>
8	#include <linux/linkage.h>	9	#include <linux/linkage.h>
9	#include <linux/types.h>	10	#include <linux/types.h>

arch/x86/kernel/nmi.c+2−4

 	spin_lock_irqsave(&desc->lock, flags);
 	/*
-	 * most handlers of type NMI_UNKNOWN never return because
+	 * Indicate if there are multiple registrations on the
-	 * they just assume the NMI is theirs.  Just a sanity check
+	 * internal NMI handler call chains (SERR and IO_CHECK).
-	 * to manage expectations
 	 */
-	WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
 	WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
 	WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));

arch/x86/kernel/tsc.c+2−0

 	 * the refined calibration and directly register it as a clocksource.
 	 */
 	if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
+		if (boot_cpu_has(X86_FEATURE_ART))
+			art_related_clocksource = &clocksource_tsc;
 		clocksource_register_khz(&clocksource_tsc, tsc_khz);
 		return 0;
 	}

arch/x86/kernel/unwind_frame.c+30−6

@@ -82,19 +82,43 @@ static size_t regs_size(struct pt_regs *regs) · 81 unmodified lines
82	return sizeof(*regs);	82	return sizeof(*regs);
83	}	83	}
84		84
		85	#ifdef CONFIG_X86_32
		86	#define GCC_REALIGN_WORDS 3
		87	#else
		88	#define GCC_REALIGN_WORDS 1
		89	#endif
		90
85	static bool is_last_task_frame(struct unwind_state *state)	91	static bool is_last_task_frame(struct unwind_state *state)
86	{	92	{
87	unsigned long bp = (unsigned long)state->bp;	93	unsigned long last_bp = (unsigned long )task_pt_regs(state->task) - 2;
88	unsigned long regs = (unsigned long)task_pt_regs(state->task);	94	unsigned long *aligned_bp = last_bp - GCC_REALIGN_WORDS;
89		95
90	/*	96	/*
91	* We have to check for the last task frame at two different locations	97	* We have to check for the last task frame at two different locations
92	* because gcc can occasionally decide to realign the stack pointer and	98	* because gcc can occasionally decide to realign the stack pointer and
93	* change the offset of the stack frame by a word in the prologue of a	99	* change the offset of the stack frame in the prologue of a function
94	* function called by head/entry code.	100	* called by head/entry code. Examples:
		101	*
		102	* <start_secondary>:
		103	* push %edi
		104	* lea 0x8(%esp),%edi
		105	* and $0xfffffff8,%esp
		106	* pushl -0x4(%edi)
		107	* push %ebp
		108	* mov %esp,%ebp
		109	*
		110	* <x86_64_start_kernel>:
		111	* lea 0x8(%rsp),%r10
		112	* and $0xfffffffffffffff0,%rsp
		113	* pushq -0x8(%r10)
		114	* push %rbp
		115	* mov %rsp,%rbp
		116	*
		117	* Note that after aligning the stack, it pushes a duplicate copy of
		118	* the return address before pushing the frame pointer.
95	*/	119	*/
96	return bp == regs - FRAME_HEADER_SIZE \|\|	120	return (state->bp == last_bp \|\|
97	bp == regs - FRAME_HEADER_SIZE - sizeof(long);	121	(state->bp == aligned_bp && (aligned_bp+1) == (last_bp+1)));
98	}	122	}
99		123
100	/*	124	/*

arch/x86/mm/kasan_init_64.c+1−0

@@ -1,3 +1,4 @@
		1	#define DISABLE_BRANCH_PROFILING
1	#define pr_fmt(fmt) "kasan: " fmt	2	#define pr_fmt(fmt) "kasan: " fmt
2	#include <linux/bootmem.h>	3	#include <linux/bootmem.h>
3	#include <linux/kasan.h>	4	#include <linux/kasan.h>

arch/x86/mm/mpx.c+1−1

@@ -590,7 +590,7 @@ static unsigned long mpx_bd_entry_to_bt_addr(struct mm_struct *mm, · 589 unmodified lines
590	* we might run off the end of the bounds table if we are on	590	* we might run off the end of the bounds table if we are on
591	* a 64-bit kernel and try to get 8 bytes.	591	* a 64-bit kernel and try to get 8 bytes.
592	*/	592	*/
593	int get_user_bd_entry(struct mm_struct mm, unsigned long bd_entry_ret,	593	static int get_user_bd_entry(struct mm_struct mm, unsigned long bd_entry_ret,
594	long __user *bd_entry_ptr)	594	long __user *bd_entry_ptr)
595	{	595	{
596	u32 bd_entry_32;	596	u32 bd_entry_32;

arch/x86/platform/intel-mid/device_libs/Makefile+1−0

@@ -26,5 +26,6 @@ obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_pcal9555a.o · 25 unmodified lines
26	obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o	26	obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
27	# MISC Devices	27	# MISC Devices
28	obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o	28	obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
		29	obj-$(subst m,y,$(CONFIG_INTEL_MID_POWER_BUTTON)) += platform_mrfld_power_btn.o
29	obj-$(subst m,y,$(CONFIG_RTC_DRV_CMOS)) += platform_mrfld_rtc.o	30	obj-$(subst m,y,$(CONFIG_RTC_DRV_CMOS)) += platform_mrfld_rtc.o
30	obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_mrfld_wdt.o	31	obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_mrfld_wdt.o

arch/x86/platform/intel-mid/device_libs/platform_mrfld_power_btn.c+82−0

@@ -0,0 +1,82 @@
	1	/*
	2	* Intel Merrifield power button support
	3	*
	4	* (C) Copyright 2017 Intel Corporation
	5	*
	6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; version 2
	11	* of the License.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/ioport.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/sfi.h>
	18
	19	#include <asm/intel-mid.h>
	20	#include <asm/intel_scu_ipc.h>
	21
	22	static struct resource mrfld_power_btn_resources[] = {
	23	{
	24	.flags = IORESOURCE_IRQ,
	25	},
	26	};
	27
	28	static struct platform_device mrfld_power_btn_dev = {
	29	.name = "msic_power_btn",
	30	.id = PLATFORM_DEVID_NONE,
	31	.num_resources = ARRAY_SIZE(mrfld_power_btn_resources),
	32	.resource = mrfld_power_btn_resources,
	33	};
	34
	35	static int mrfld_power_btn_scu_status_change(struct notifier_block *nb,
	36	unsigned long code, void *data)
	37	{
	38	if (code == SCU_DOWN) {
	39	platform_device_unregister(&mrfld_power_btn_dev);
	40	return 0;
	41	}
	42
	43	return platform_device_register(&mrfld_power_btn_dev);
	44	}
	45
	46	static struct notifier_block mrfld_power_btn_scu_notifier = {
	47	.notifier_call = mrfld_power_btn_scu_status_change,
	48	};
	49
	50	static int __init register_mrfld_power_btn(void)
	51	{
	52	if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_TANGIER)
	53	return -ENODEV;
	54
	55	/*
	56	* We need to be sure that the SCU IPC is ready before
	57	* PMIC power button device can be registered:
	58	*/
	59	intel_scu_notifier_add(&mrfld_power_btn_scu_notifier);
	60
	61	return 0;
	62	}
	63	arch_initcall(register_mrfld_power_btn);
	64
	65	static void __init mrfld_power_btn_platform_data(void info)
	66	{
	67	struct resource *res = mrfld_power_btn_resources;
	68	struct sfi_device_table_entry *pentry = info;
	69
	70	res->start = res->end = pentry->irq;
	71	return NULL;
	72	}
	73
	74	static const struct devs_id mrfld_power_btn_dev_id __initconst = {
	75	.name = "bcove_power_btn",
	76	.type = SFI_DEV_TYPE_IPC,
	77	.delay = 1,
	78	.msic = 1,
	79	.get_platform_data = &mrfld_power_btn_platform_data,
	80	};
	81
	82	sfi_device(mrfld_power_btn_dev_id);

arch/x86/platform/intel-mid/device_libs/platform_mrfld_wdt.c+1−1

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	#include <asm/intel_scu_ipc.h>	19	#include <asm/intel_scu_ipc.h>
20	#include <asm/io_apic.h>	20	#include <asm/io_apic.h>
21		21
22	#define TANGIER_EXT_TIMER0_MSI 15	22	#define TANGIER_EXT_TIMER0_MSI 12
23		23
24	static struct platform_device wdt_dev = {	24	static struct platform_device wdt_dev = {
25	.name = "intel_mid_wdt",	25	.name = "intel_mid_wdt",

arch/x86/platform/intel-mid/mfld.c+4−11

 #include "intel_mid_weak_decls.h"
-static void penwell_arch_setup(void);
-/* penwell arch ops */
-static struct intel_mid_ops penwell_ops = {
-	.arch_setup = penwell_arch_setup,
-};
-static void mfld_power_off(void)
-{
-}
 static unsigned long __init mfld_calibrate_tsc(void)
 {
 	unsigned long fast_calibrate;
 static void __init penwell_arch_setup(void)
 {
 	x86_platform.calibrate_tsc = mfld_calibrate_tsc;
-	pm_power_off = mfld_power_off;
 }
+static struct intel_mid_ops penwell_ops = {
+	.arch_setup = penwell_arch_setup,
+};
 void *get_penwell_ops(void)
 {
 	return &penwell_ops;

block/bio.c+9−3

 	bio_list_init(&punt);
 	bio_list_init(&nopunt);
-	while ((bio = bio_list_pop(current->bio_list)))
+	while ((bio = bio_list_pop(&current->bio_list[0])))
 		bio_list_add(bio->bi_pool == bs ? &punt : &nopunt, bio);
+	current->bio_list[0] = nopunt;
-	*current->bio_list = nopunt;
+	bio_list_init(&nopunt);
+	while ((bio = bio_list_pop(&current->bio_list[1])))
+		bio_list_add(bio->bi_pool == bs ? &punt : &nopunt, bio);
+	current->bio_list[1] = nopunt;
 	spin_lock(&bs->rescue_lock);
 	bio_list_merge(&bs->rescue_list, &punt);
 		 * we retry with the original gfp_flags.
 		 */
-		if (current->bio_list && !bio_list_empty(current->bio_list))
+		if (current->bio_list &&
+		    (!bio_list_empty(&current->bio_list[0]) ||
+		     !bio_list_empty(&current->bio_list[1])))
 			gfp_mask &= ~__GFP_DIRECT_RECLAIM;
 		p = mempool_alloc(bs->bio_pool, gfp_mask);

block/blk-core.c+18−12

  */
 blk_qc_t generic_make_request(struct bio *bio)
 {
-	struct bio_list bio_list_on_stack;
+	/*
+	 * bio_list_on_stack[0] contains bios submitted by the current
+	 * make_request_fn.
+	 * bio_list_on_stack[1] contains bios that were submitted before
+	 * the current make_request_fn, but that haven't been processed
+	 * yet.
+	 */
+	struct bio_list bio_list_on_stack[2];
 	blk_qc_t ret = BLK_QC_T_NONE;
 	if (!generic_make_request_checks(bio))
 	 * should be added at the tail
 	 */
 	if (current->bio_list) {
-		bio_list_add(current->bio_list, bio);
+		bio_list_add(&current->bio_list[0], bio);
 		goto out;
 	}
 	 * bio_list, and call into ->make_request() again.
 	 */
 	BUG_ON(bio->bi_next);
-	bio_list_init(&bio_list_on_stack);
+	bio_list_init(&bio_list_on_stack[0]);
-	current->bio_list = &bio_list_on_stack;
+	current->bio_list = bio_list_on_stack;
 	do {
 		struct request_queue *q = bdev_get_queue(bio->bi_bdev);
 		if (likely(blk_queue_enter(q, false) == 0)) {
-			struct bio_list hold;
 			struct bio_list lower, same;
 			/* Create a fresh bio_list for all subordinate requests */
-			hold = bio_list_on_stack;
+			bio_list_on_stack[1] = bio_list_on_stack[0];
-			bio_list_init(&bio_list_on_stack);
+			bio_list_init(&bio_list_on_stack[0]);
 			ret = q->make_request_fn(q, bio);
 			blk_queue_exit(q);
 			 */
 			bio_list_init(&lower);
 			bio_list_init(&same);
-			while ((bio = bio_list_pop(&bio_list_on_stack)) != NULL)
+			while ((bio = bio_list_pop(&bio_list_on_stack[0])) != NULL)
 				if (q == bdev_get_queue(bio->bi_bdev))
 					bio_list_add(&same, bio);
 				else
 					bio_list_add(&lower, bio);
 			/* now assemble so we handle the lowest level first */
-			bio_list_merge(&bio_list_on_stack, &lower);
+			bio_list_merge(&bio_list_on_stack[0], &lower);
-			bio_list_merge(&bio_list_on_stack, &same);
+			bio_list_merge(&bio_list_on_stack[0], &same);
-			bio_list_merge(&bio_list_on_stack, &hold);
+			bio_list_merge(&bio_list_on_stack[0], &bio_list_on_stack[1]);
 		} else {
 			bio_io_error(bio);
 		}
-		bio = bio_list_pop(current->bio_list);
+		bio = bio_list_pop(&bio_list_on_stack[0]);
 	} while (bio);
 	current->bio_list = NULL; /* deactivate */

block/blk-mq-tag.c+3−0

@@ -295,6 +295,9 @@ int blk_mq_reinit_tagset(struct blk_mq_tag_set *set) · 294 unmodified lines
295	for (i = 0; i < set->nr_hw_queues; i++) {	295	for (i = 0; i < set->nr_hw_queues; i++) {
296	struct blk_mq_tags *tags = set->tags[i];	296	struct blk_mq_tags *tags = set->tags[i];
297		297
		298	if (!tags)
		299	continue;
		300
298	for (j = 0; j < tags->nr_tags; j++) {	301	for (j = 0; j < tags->nr_tags; j++) {
299	if (!tags->static_rqs[j])	302	if (!tags->static_rqs[j])
300	continue;	303	continue;

block/blk-mq.c+6−14

 {
 	struct blk_mq_timeout_data *data = priv;
-	if (!test_bit(REQ_ATOM_STARTED, &rq->atomic_flags)) {
+	if (!test_bit(REQ_ATOM_STARTED, &rq->atomic_flags))
-		/*
-		 * If a request wasn't started before the queue was
-		 * marked dying, kill it here or it'll go unnoticed.
-		 */
-		if (unlikely(blk_queue_dying(rq->q))) {
-			rq->errors = -EIO;
-			blk_mq_end_request(rq, rq->errors);
-		}
 		return;
-	}
 	if (time_after_eq(jiffies, rq->deadline)) {
 		if (!blk_mark_rq_complete(rq))
 	return blk_tag_to_qc_t(rq->internal_tag, hctx->queue_num, true);
 }
-static void blk_mq_try_issue_directly(struct request *rq, blk_qc_t *cookie)
+static void blk_mq_try_issue_directly(struct request *rq, blk_qc_t *cookie,
+				      bool may_sleep)
 {
 	struct request_queue *q = rq->q;
 	struct blk_mq_queue_data bd = {
 	}
 insert:
-	blk_mq_sched_insert_request(rq, false, true, true, false);
+	blk_mq_sched_insert_request(rq, false, true, false, may_sleep);
 }
 /*
 		if (!(data.hctx->flags & BLK_MQ_F_BLOCKING)) {
 			rcu_read_lock();
-			blk_mq_try_issue_directly(old_rq, &cookie);
+			blk_mq_try_issue_directly(old_rq, &cookie, false);
 			rcu_read_unlock();
 		} else {
 			srcu_idx = srcu_read_lock(&data.hctx->queue_rq_srcu);
-			blk_mq_try_issue_directly(old_rq, &cookie);
+			blk_mq_try_issue_directly(old_rq, &cookie, true);
 			srcu_read_unlock(&data.hctx->queue_rq_srcu, srcu_idx);
 		}
 		goto done;

block/blk-stat.c+2−2

 static void blk_stat_sum(struct blk_rq_stat *dst, struct blk_rq_stat *src)
 {
+	blk_stat_flush_batch(src);
 	if (!src->nr_samples)
 		return;
-	blk_stat_flush_batch(src);
 	dst->min = min(dst->min, src->min);
 	dst->max = max(dst->max, src->max);

crypto/af_alg.c+5−4

 	return err;
 }
-int af_alg_accept(struct sock *sk, struct socket *newsock)
+int af_alg_accept(struct sock *sk, struct socket *newsock, bool kern)
 {
 	struct alg_sock *ask = alg_sk(sk);
 	const struct af_alg_type *type;
 	if (!type)
 		goto unlock;
-	sk2 = sk_alloc(sock_net(sk), PF_ALG, GFP_KERNEL, &alg_proto, 0);
+	sk2 = sk_alloc(sock_net(sk), PF_ALG, GFP_KERNEL, &alg_proto, kern);
 	err = -ENOMEM;
 	if (!sk2)
 		goto unlock;
 }
 EXPORT_SYMBOL_GPL(af_alg_accept);
-static int alg_accept(struct socket *sock, struct socket *newsock, int flags)
+static int alg_accept(struct socket *sock, struct socket *newsock, int flags,
+		      bool kern)
 {
-	return af_alg_accept(sock->sk, newsock);
+	return af_alg_accept(sock->sk, newsock, kern);
 }
 static const struct proto_ops alg_proto_ops = {

crypto/algif_hash.c+5−4

 	return err ?: len;
 }
-static int hash_accept(struct socket *sock, struct socket *newsock, int flags)
+static int hash_accept(struct socket *sock, struct socket *newsock, int flags,
+		       bool kern)
 {
 	struct sock *sk = sock->sk;
 	struct alg_sock *ask = alg_sk(sk);
 	if (err)
 		return err;
-	err = af_alg_accept(ask->parent, newsock);
+	err = af_alg_accept(ask->parent, newsock, kern);
 	if (err)
 		return err;
 }
 static int hash_accept_nokey(struct socket *sock, struct socket *newsock,
-			     int flags)
+			     int flags, bool kern)
 {
 	int err;
 	if (err)
 		return err;
-	return hash_accept(sock, newsock, flags);
+	return hash_accept(sock, newsock, flags, kern);
 }
 static struct proto_ops algif_hash_ops_nokey = {

drivers/acpi/acpi_processor.c+42−15

@@ -182,11 +182,6 @@ int __weak arch_register_cpu(int cpu) · 181 unmodified lines
182		182
183	void __weak arch_unregister_cpu(int cpu) {}	183	void __weak arch_unregister_cpu(int cpu) {}
184		184
185	int __weak acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
186	{
187	return -ENODEV;
188	}
189
190	static int acpi_processor_hotadd_init(struct acpi_processor *pr)	185	static int acpi_processor_hotadd_init(struct acpi_processor *pr)
191	{	186	{
192	unsigned long long sta;	187	unsigned long long sta;
@@ -285,6 +280,13 @@ static int acpi_processor_get_info(struct acpi_device *device) · 92 unmodified lines
285	pr->acpi_id = value;	280	pr->acpi_id = value;
286	}	281	}
287		282
		283	if (acpi_duplicate_processor_id(pr->acpi_id)) {
		284	dev_err(&device->dev,
		285	"Failed to get unique processor _UID (0x%x)\n",
		286	pr->acpi_id);
		287	return -ENODEV;
		288	}
		289
288	pr->phys_id = acpi_get_phys_id(pr->handle, device_declaration,	290	pr->phys_id = acpi_get_phys_id(pr->handle, device_declaration,
289	pr->acpi_id);	291	pr->acpi_id);
290	if (invalid_phys_cpuid(pr->phys_id))	292	if (invalid_phys_cpuid(pr->phys_id))
@@ -585,7 +587,7 @@ static struct acpi_scan_handler processor_container_handler = { · 294 unmodified lines
585	static int nr_unique_ids __initdata;	587	static int nr_unique_ids __initdata;
586		588
587	/* The number of the duplicate processor IDs */	589	/* The number of the duplicate processor IDs */
588	static int nr_duplicate_ids __initdata;	590	static int nr_duplicate_ids;
589		591
590	/* Used to store the unique processor IDs */	592	/* Used to store the unique processor IDs */
591	static int unique_processor_ids[] __initdata = {	593	static int unique_processor_ids[] __initdata = {
@@ -593,7 +595,7 @@ static int unique_processor_ids[] __initdata = { · 1 unmodified line
593	};	595	};
594		596
595	/* Used to store the duplicate processor IDs */	597	/* Used to store the duplicate processor IDs */
596	static int duplicate_processor_ids[] __initdata = {	598	static int duplicate_processor_ids[] = {
597	[0 ... NR_CPUS - 1] = -1,	599	[0 ... NR_CPUS - 1] = -1,
598	};	600	};
599		601
@@ -638,28 +640,53 @@ static acpi_status __init acpi_processor_ids_walk(acpi_handle handle, · 38 unmodified lines
638	void **rv)	640	void **rv)
639	{	641	{
640	acpi_status status;	642	acpi_status status;
		643	acpi_object_type acpi_type;
		644	unsigned long long uid;
641	union acpi_object object = { 0 };	645	union acpi_object object = { 0 };
642	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };	646	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };
643		647
644	status = acpi_evaluate_object(handle, NULL, NULL, &buffer);	648	status = acpi_get_type(handle, &acpi_type);
645	if (ACPI_FAILURE(status))	649	if (ACPI_FAILURE(status))
646	acpi_handle_info(handle, "Not get the processor object\n");	650	return false;
647	else	651
648	processor_validated_ids_update(object.processor.proc_id);	652	switch (acpi_type) {
		653	case ACPI_TYPE_PROCESSOR:
		654	status = acpi_evaluate_object(handle, NULL, NULL, &buffer);
		655	if (ACPI_FAILURE(status))
		656	goto err;
		657	uid = object.processor.proc_id;
		658	break;
		659
		660	case ACPI_TYPE_DEVICE:
		661	status = acpi_evaluate_integer(handle, "_UID", NULL, &uid);
		662	if (ACPI_FAILURE(status))
		663	goto err;
		664	break;
		665	default:
		666	goto err;
		667	}
		668
		669	processor_validated_ids_update(uid);
		670	return true;
		671
		672	err:
		673	acpi_handle_info(handle, "Invalid processor object\n");
		674	return false;
649		675
650	return AE_OK;
651	}	676	}
652		677
653	static void __init acpi_processor_check_duplicates(void)	678	void __init acpi_processor_check_duplicates(void)
654	{	679	{
655	/* Search all processor nodes in ACPI namespace */	680	/* check the correctness for all processors in ACPI namespace */
656	acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,	681	acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
657	ACPI_UINT32_MAX,	682	ACPI_UINT32_MAX,
658	acpi_processor_ids_walk,	683	acpi_processor_ids_walk,
659	NULL, NULL, NULL);	684	NULL, NULL, NULL);
		685	acpi_get_devices(ACPI_PROCESSOR_DEVICE_HID, acpi_processor_ids_walk,
		686	NULL, NULL);
660	}	687	}
661		688
662	bool __init acpi_processor_validate_proc_id(int proc_id)	689	bool acpi_duplicate_processor_id(int proc_id)
663	{	690	{
664	int i;	691	int i;
665		692

drivers/acpi/bus.c+0−1

@@ -1249,7 +1249,6 @@ static int __init acpi_init(void) · 1248 unmodified lines
1249	acpi_wakeup_device_init();	1249	acpi_wakeup_device_init();
1250	acpi_debugger_init();	1250	acpi_debugger_init();
1251	acpi_setup_sb_notify_handler();	1251	acpi_setup_sb_notify_handler();
1252	acpi_set_processor_mapping();
1253	return 0;	1252	return 0;
1254	}	1253	}
1255		1254

drivers/acpi/nfit/core.c+5−1

 	const struct nfit_set_info_map *map0 = m0;
 	const struct nfit_set_info_map *map1 = m1;
-	return map0->region_offset - map1->region_offset;
+	if (map0->region_offset < map1->region_offset)
+		return -1;
+	else if (map0->region_offset > map1->region_offset)
+		return 1;
+	return 0;
 }
 /* Retrieve the nth entry referencing this spa */

drivers/acpi/processor_core.c+22−111

 }
 static int map_lapic_id(struct acpi_subtable_header *entry,
-		 u32 acpi_id, phys_cpuid_t *apic_id, bool ignore_disabled)
+		 u32 acpi_id, phys_cpuid_t *apic_id)
 {
 	struct acpi_madt_local_apic *lapic =
 		container_of(entry, struct acpi_madt_local_apic, header);
-	if (ignore_disabled && !(lapic->lapic_flags & ACPI_MADT_ENABLED))
+	if (!(lapic->lapic_flags & ACPI_MADT_ENABLED))
 		return -ENODEV;
 	if (lapic->processor_id != acpi_id)
 }
 static int map_x2apic_id(struct acpi_subtable_header *entry,
-		int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id,
+		int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id)
-		bool ignore_disabled)
 {
 	struct acpi_madt_local_x2apic *apic =
 		container_of(entry, struct acpi_madt_local_x2apic, header);
-	if (ignore_disabled && !(apic->lapic_flags & ACPI_MADT_ENABLED))
+	if (!(apic->lapic_flags & ACPI_MADT_ENABLED))
 		return -ENODEV;
 	if (device_declaration && (apic->uid == acpi_id)) {
 }
 static int map_lsapic_id(struct acpi_subtable_header *entry,
-		int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id,
+		int device_declaration, u32 acpi_id, phys_cpuid_t *apic_id)
-		bool ignore_disabled)
 {
 	struct acpi_madt_local_sapic *lsapic =
 		container_of(entry, struct acpi_madt_local_sapic, header);
-	if (ignore_disabled && !(lsapic->lapic_flags & ACPI_MADT_ENABLED))
+	if (!(lsapic->lapic_flags & ACPI_MADT_ENABLED))
 		return -ENODEV;
 	if (device_declaration) {
  * Retrieve the ARM CPU physical identifier (MPIDR)
  */
 static int map_gicc_mpidr(struct acpi_subtable_header *entry,
-		int device_declaration, u32 acpi_id, phys_cpuid_t *mpidr,
+		int device_declaration, u32 acpi_id, phys_cpuid_t *mpidr)
-		bool ignore_disabled)
 {
 	struct acpi_madt_generic_interrupt *gicc =
 	    container_of(entry, struct acpi_madt_generic_interrupt, header);
-	if (ignore_disabled && !(gicc->flags & ACPI_MADT_ENABLED))
+	if (!(gicc->flags & ACPI_MADT_ENABLED))
 		return -ENODEV;
 	/* device_declaration means Device object in DSDT, in the
 }
 static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt,
-				   int type, u32 acpi_id, bool ignore_disabled)
+				   int type, u32 acpi_id)
 {
 	unsigned long madt_end, entry;
 	phys_cpuid_t phys_id = PHYS_CPUID_INVALID;	/* CPU hardware ID */
 		struct acpi_subtable_header *header =
 			(struct acpi_subtable_header *)entry;
 		if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) {
-			if (!map_lapic_id(header, acpi_id, &phys_id,
+			if (!map_lapic_id(header, acpi_id, &phys_id))
-					  ignore_disabled))
 				break;
 		} else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) {
-			if (!map_x2apic_id(header, type, acpi_id, &phys_id,
+			if (!map_x2apic_id(header, type, acpi_id, &phys_id))
-					   ignore_disabled))
 				break;
 		} else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) {
-			if (!map_lsapic_id(header, type, acpi_id, &phys_id,
+			if (!map_lsapic_id(header, type, acpi_id, &phys_id))
-					   ignore_disabled))
 				break;
 		} else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) {
-			if (!map_gicc_mpidr(header, type, acpi_id, &phys_id,
+			if (!map_gicc_mpidr(header, type, acpi_id, &phys_id))
-					    ignore_disabled))
 				break;
 		}
 		entry += header->length;
 	if (!madt)
 		return PHYS_CPUID_INVALID;
-	rv = map_madt_entry(madt, 1, acpi_id, true);
+	rv = map_madt_entry(madt, 1, acpi_id);
 	acpi_put_table((struct acpi_table_header *)madt);
 	return rv;
 }
-static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id,
+static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
-				  bool ignore_disabled)
 {
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 	union acpi_object *obj;
 	header = (struct acpi_subtable_header *)obj->buffer.pointer;
 	if (header->type == ACPI_MADT_TYPE_LOCAL_APIC)
-		map_lapic_id(header, acpi_id, &phys_id, ignore_disabled);
+		map_lapic_id(header, acpi_id, &phys_id);
 	else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC)
-		map_lsapic_id(header, type, acpi_id, &phys_id, ignore_disabled);
+		map_lsapic_id(header, type, acpi_id, &phys_id);
 	else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC)
-		map_x2apic_id(header, type, acpi_id, &phys_id, ignore_disabled);
+		map_x2apic_id(header, type, acpi_id, &phys_id);
 	else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT)
-		map_gicc_mpidr(header, type, acpi_id, &phys_id,
+		map_gicc_mpidr(header, type, acpi_id, &phys_id);
-			       ignore_disabled);
 exit:
 	kfree(buffer.pointer);
 	return phys_id;
 }
-static phys_cpuid_t __acpi_get_phys_id(acpi_handle handle, int type,
+phys_cpuid_t acpi_get_phys_id(acpi_handle handle, int type, u32 acpi_id)
-				       u32 acpi_id, bool ignore_disabled)
 {
 	phys_cpuid_t phys_id;
-	phys_id = map_mat_entry(handle, type, acpi_id, ignore_disabled);
+	phys_id = map_mat_entry(handle, type, acpi_id);
 	if (invalid_phys_cpuid(phys_id))
-		phys_id = map_madt_entry(get_madt_table(), type, acpi_id,
+		phys_id = map_madt_entry(get_madt_table(), type, acpi_id);
-					   ignore_disabled);
 	return phys_id;
 }
-phys_cpuid_t acpi_get_phys_id(acpi_handle handle, int type, u32 acpi_id)
-{
-	return __acpi_get_phys_id(handle, type, acpi_id, true);
-}
 int acpi_map_cpuid(phys_cpuid_t phys_id, u32 acpi_id)
 {
 #ifdef CONFIG_SMP
 }
 EXPORT_SYMBOL_GPL(acpi_get_cpuid);
-#ifdef CONFIG_ACPI_HOTPLUG_CPU
-static bool __init
-map_processor(acpi_handle handle, phys_cpuid_t *phys_id, int *cpuid)
-{
-	int type, id;
-	u32 acpi_id;
-	acpi_status status;
-	acpi_object_type acpi_type;
-	unsigned long long tmp;
-	union acpi_object object = { 0 };
-	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };
-	status = acpi_get_type(handle, &acpi_type);
-	if (ACPI_FAILURE(status))
-		return false;
-	switch (acpi_type) {
-	case ACPI_TYPE_PROCESSOR:
-		status = acpi_evaluate_object(handle, NULL, NULL, &buffer);
-		if (ACPI_FAILURE(status))
-			return false;
-		acpi_id = object.processor.proc_id;
-		/* validate the acpi_id */
-		if(acpi_processor_validate_proc_id(acpi_id))
-			return false;
-		break;
-	case ACPI_TYPE_DEVICE:
-		status = acpi_evaluate_integer(handle, "_UID", NULL, &tmp);
-		if (ACPI_FAILURE(status))
-			return false;
-		acpi_id = tmp;
-		break;
-	default:
-		return false;
-	}
-	type = (acpi_type == ACPI_TYPE_DEVICE) ? 1 : 0;
-	*phys_id = __acpi_get_phys_id(handle, type, acpi_id, false);
-	id = acpi_map_cpuid(*phys_id, acpi_id);
-	if (id < 0)
-		return false;
-	*cpuid = id;
-	return true;
-}
-static acpi_status __init
-set_processor_node_mapping(acpi_handle handle, u32 lvl, void *context,
-			   void **rv)
-{
-	phys_cpuid_t phys_id;
-	int cpu_id;
-	if (!map_processor(handle, &phys_id, &cpu_id))
-		return AE_ERROR;
-	acpi_map_cpu2node(handle, cpu_id, phys_id);
-	return AE_OK;
-}
-void __init acpi_set_processor_mapping(void)
-{
-	/* Set persistent cpu <-> node mapping for all processors. */
-	acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
-			    ACPI_UINT32_MAX, set_processor_node_mapping,
-			    NULL, NULL, NULL);
-}
-#else
-void __init acpi_set_processor_mapping(void) {}
-#endif /* CONFIG_ACPI_HOTPLUG_CPU */
 #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC
 static int get_ioapic_id(struct acpi_subtable_header *entry, u32 gsi_base,
 			 u64 *phys_addr, int *ioapic_id)

drivers/acpi/spcr.c+1−1

@@ -30,7 +30,7 @@ static bool qdf2400_erratum_44_present(struct acpi_table_header *h) · 29 unmodified lines
30	return true;	30	return true;
31		31
32	if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&	32	if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
33	h->oem_revision == 0)	33	h->oem_revision == 1)
34	return true;	34	return true;
35		35
36	return false;	36	return false;

drivers/ata/ahci_qoriq.c+4−2

 	case AHCI_LS1043A:
 		if (!qpriv->ecc_addr)
 			return -EINVAL;
-		writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+				qpriv->ecc_addr);
 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 		if (qpriv->is_dmacoherent)
 	case AHCI_LS1046A:
 		if (!qpriv->ecc_addr)
 			return -EINVAL;
-		writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+				qpriv->ecc_addr);
 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 		if (qpriv->is_dmacoherent)

drivers/ata/libata-sff.c+0−1

@@ -1482,7 +1482,6 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) · 1481 unmodified lines
1482	break;	1482	break;
1483		1483
1484	default:	1484	default:
1485	WARN_ON_ONCE(1);
1486	return AC_ERR_SYSTEM;	1485	return AC_ERR_SYSTEM;
1487	}	1486	}
1488		1487

drivers/ata/libata-transport.c+3−6

 static void ata_tport_release(struct device *dev)
 {
-	put_device(dev->parent);
 }
 /**
 	device_initialize(dev);
 	dev->type = &ata_port_type;
-	dev->parent = get_device(parent);
+	dev->parent = parent;
 	dev->release = ata_tport_release;
 	dev_set_name(dev, "ata%d", ap->print_id);
 	transport_setup_device(dev);
 static void ata_tlink_release(struct device *dev)
 {
-	put_device(dev->parent);
 }
 /**
 	int error;
 	device_initialize(dev);
-	dev->parent = get_device(&ap->tdev);
+	dev->parent = &ap->tdev;
 	dev->release = ata_tlink_release;
 	if (ata_is_host_link(link))
 		dev_set_name(dev, "link%d", ap->print_id);
 static void ata_tdev_release(struct device *dev)
 {
-	put_device(dev->parent);
 }
 /**
 	int error;
 	device_initialize(dev);
-	dev->parent = get_device(&link->tdev);
+	dev->parent = &link->tdev;
 	dev->release = ata_tdev_release;
 	if (ata_is_host_link(link))
 		dev_set_name(dev, "dev%d.%d", ap->print_id,ata_dev->devno);

drivers/auxdisplay/img-ascii-lcd.c+1−0

@@ -218,6 +218,7 @@ static const struct of_device_id img_ascii_lcd_matches[] = { · 217 unmodified lines
218	{ .compatible = "img,boston-lcd", .data = &boston_config },	218	{ .compatible = "img,boston-lcd", .data = &boston_config },
219	{ .compatible = "mti,malta-lcd", .data = &malta_config },	219	{ .compatible = "mti,malta-lcd", .data = &malta_config },
220	{ .compatible = "mti,sead3-lcd", .data = &sead3_config },	220	{ .compatible = "mti,sead3-lcd", .data = &sead3_config },
		221	{ /* sentinel */ }
221	};	222	};
222		223
223	/**	224	/**

drivers/base/core.c+0−5

 	return restart_syscall();
 }
-void assert_held_device_hotplug(void)
-{
-	lockdep_assert_held(&device_hotplug_lock);
-}
 #ifdef CONFIG_BLOCK
 static inline int device_is_not_partition(struct device *dev)
 {

drivers/bluetooth/Kconfig+2−1

@@ -344,7 +344,8 @@ config BT_WILINK · 343 unmodified lines
344		344
345	config BT_QCOMSMD	345	config BT_QCOMSMD
346	tristate "Qualcomm SMD based HCI support"	346	tristate "Qualcomm SMD based HCI support"
347	depends on (QCOM_SMD && QCOM_WCNSS_CTRL) \|\| COMPILE_TEST	347	depends on QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n)
		348	depends on QCOM_WCNSS_CTRL \|\| (COMPILE_TEST && QCOM_WCNSS_CTRL=n)
348	select BT_QCA	349	select BT_QCA
349	help	350	help
350	Qualcomm SMD based HCI driver.	351	Qualcomm SMD based HCI driver.

drivers/char/hw_random/amd-rng.c+34−8

 struct amd768_priv {
 	void __iomem *iobase;
 	struct pci_dev *pcidev;
+	u32 pmbase;
 };
 static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 	if (pmbase == 0)
 		return -EIO;
-	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
-	if (!devm_request_region(&pdev->dev, pmbase + PMBASE_OFFSET,
+	if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
-				PMBASE_SIZE, DRV_NAME)) {
 		dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
 			pmbase + 0xF0);
-		return -EBUSY;
+		err = -EBUSY;
+		goto out;
 	}
-	priv->iobase = devm_ioport_map(&pdev->dev, pmbase + PMBASE_OFFSET,
+	priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
-			PMBASE_SIZE);
 	if (!priv->iobase) {
 		pr_err(DRV_NAME "Cannot map ioport\n");
-		return -ENOMEM;
+		err = -EINVAL;
+		goto err_iomap;
 	}
 	amd_rng.priv = (unsigned long)priv;
+	priv->pmbase = pmbase;
 	priv->pcidev = pdev;
 	pr_info(DRV_NAME " detected\n");
-	return devm_hwrng_register(&pdev->dev, &amd_rng);
+	err = hwrng_register(&amd_rng);
+	if (err) {
+		pr_err(DRV_NAME " registering failed (%d)\n", err);
+		goto err_hwrng;
+	}
+	return 0;
+err_hwrng:
+	ioport_unmap(priv->iobase);
+err_iomap:
+	release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
+out:
+	kfree(priv);
+	return err;
 }
 static void __exit mod_exit(void)
 {
+	struct amd768_priv *priv;
+	priv = (struct amd768_priv *)amd_rng.priv;
+	hwrng_unregister(&amd_rng);
+	ioport_unmap(priv->iobase);
+	release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
+	kfree(priv);
 }
 module_init(mod_init);

drivers/char/hw_random/geode-rng.c+35−15

 #include <linux/module.h>
 #include <linux/pci.h>
+#define PFX	KBUILD_MODNAME ": "
 #define GEODE_RNG_DATA_REG   0x50
 #define GEODE_RNG_STATUS_REG 0x54
 static int __init mod_init(void)
 {
+	int err = -ENODEV;
 	struct pci_dev *pdev = NULL;
 	const struct pci_device_id *ent;
 	void __iomem *mem;
 	for_each_pci_dev(pdev) {
 		ent = pci_match_id(pci_tbl, pdev);
-		if (ent) {
+		if (ent)
-			rng_base = pci_resource_start(pdev, 0);
+			goto found;
-			if (rng_base == 0)
-				return -ENODEV;
-			mem = devm_ioremap(&pdev->dev, rng_base, 0x58);
-			if (!mem)
-				return -ENOMEM;
-			geode_rng.priv = (unsigned long)mem;
-			pr_info("AMD Geode RNG detected\n");
-			return devm_hwrng_register(&pdev->dev, &geode_rng);
-		}
 	}
 	/* Device not found. */
-	return -ENODEV;
+	goto out;
+found:
+	rng_base = pci_resource_start(pdev, 0);
+	if (rng_base == 0)
+		goto out;
+	err = -ENOMEM;
+	mem = ioremap(rng_base, 0x58);
+	if (!mem)
+		goto out;
+	geode_rng.priv = (unsigned long)mem;
+	pr_info("AMD Geode RNG detected\n");
+	err = hwrng_register(&geode_rng);
+	if (err) {
+		pr_err(PFX "RNG registering failed (%d)\n",
+		       err);
+		goto err_unmap;
+	}
+out:
+	return err;
+err_unmap:
+	iounmap(mem);
+	goto out;
 }
 static void __exit mod_exit(void)
 {
+	void __iomem *mem = (void __iomem *)geode_rng.priv;
+	hwrng_unregister(&geode_rng);
+	iounmap(mem);
 }
 module_init(mod_init);

drivers/char/hw_random/omap-rng.c+14−2

 				irq, err);
 			return err;
 		}
-		omap_rng_write(priv, RNG_INTMASK_REG, RNG_SHUTDOWN_OFLO_MASK);
-		priv->clk = of_clk_get(pdev->dev.of_node, 0);
+		priv->clk = devm_clk_get(&pdev->dev, NULL);
 		if (IS_ERR(priv->clk) && PTR_ERR(priv->clk) == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 		if (!IS_ERR(priv->clk)) {
 				dev_err(&pdev->dev, "unable to enable the clk, "
 						    "err = %d\n", err);
 		}
+		/*
+		 * On OMAP4, enabling the shutdown_oflo interrupt is
+		 * done in the interrupt mask register. There is no
+		 * such register on EIP76, and it's enabled by the
+		 * same bit in the control register
+		 */
+		if (priv->pdata->regs[RNG_INTMASK_REG])
+			omap_rng_write(priv, RNG_INTMASK_REG,
+				       RNG_SHUTDOWN_OFLO_MASK);
+		else
+			omap_rng_write(priv, RNG_CONTROL_REG,
+				       RNG_SHUTDOWN_OFLO_MASK);
 	}
 	return 0;
 }

drivers/char/ppdev.c+9−2

 	struct ieee1284_info state;
 	struct ieee1284_info saved_state;
 	long default_inactivity;
+	int index;
 };
 /* should we use PARDEVICE_MAX here? */
 static struct device *devices[PARPORT_MAX];
+static DEFINE_IDA(ida_index);
 /* pp_struct.flags bitfields */
 #define PP_CLAIMED    (1<<0)
 #define PP_EXCL       (1<<1)
 	struct pardevice *pdev = NULL;
 	char *name;
 	struct pardev_cb ppdev_cb;
-	int rc = 0;
+	int rc = 0, index;
 	name = kasprintf(GFP_KERNEL, CHRDEV "%x", minor);
 	if (name == NULL)
 		goto err;
 	}
+	index = ida_simple_get(&ida_index, 0, 0, GFP_KERNEL);
 	memset(&ppdev_cb, 0, sizeof(ppdev_cb));
 	ppdev_cb.irq_func = pp_irq;
 	ppdev_cb.flags = (pp->flags & PP_EXCL) ? PARPORT_FLAG_EXCL : 0;
 	ppdev_cb.private = pp;
-	pdev = parport_register_dev_model(port, name, &ppdev_cb, minor);
+	pdev = parport_register_dev_model(port, name, &ppdev_cb, index);
 	parport_put_port(port);
 	if (!pdev) {
 		pr_warn("%s: failed to register device!\n", name);
 		rc = -ENXIO;
+		ida_simple_remove(&ida_index, index);
 		goto err;
 	}
 	pp->pdev = pdev;
+	pp->index = index;
 	dev_dbg(&pdev->dev, "registered pardevice\n");
 err:
 	kfree(name);
 	if (pp->pdev) {
 		parport_unregister_device(pp->pdev);
+		ida_simple_remove(&ida_index, pp->index);
 		pp->pdev = NULL;
 		pr_debug(CHRDEV "%x: unregistered pardevice\n", minor);
 	}

drivers/clk/clk.c+2−1

 	clk->core = hw->core;
 	clk->dev_id = dev_id;
-	clk->con_id = con_id;
+	clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
 	clk->max_rate = ULONG_MAX;
 	clk_prepare_lock();
 	hlist_del(&clk->clks_node);
 	clk_prepare_unlock();
+	kfree_const(clk->con_id);
 	kfree(clk);
 }

drivers/clk/rockchip/clk-rk3036.c+8−1

 PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };
 PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };
-PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll" "usb480m" };
+PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };
 PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };
 PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 		return;
 	}
+	/*
+	 * Make uart_pll_clk a child of the gpll, as all other sources are
+	 * not that usable / stable.
+	 */
+	writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
+		       reg_base + RK2928_CLKSEL_CON(13));
 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 	if (IS_ERR(ctx)) {
 		pr_err("%s: rockchip clk init failed\n", __func__);

drivers/clk/sunxi-ng/Kconfig+1−0

@@ -80,6 +80,7 @@ config SUN6I_A31_CCU · 79 unmodified lines
80	select SUNXI_CCU_DIV	80	select SUNXI_CCU_DIV
81	select SUNXI_CCU_NK	81	select SUNXI_CCU_NK
82	select SUNXI_CCU_NKM	82	select SUNXI_CCU_NKM
		83	select SUNXI_CCU_NKMP
83	select SUNXI_CCU_NM	84	select SUNXI_CCU_NM
84	select SUNXI_CCU_MP	85	select SUNXI_CCU_MP
85	select SUNXI_CCU_PHASE	86	select SUNXI_CCU_PHASE

drivers/clk/sunxi-ng/ccu-sun50i-a64.c+1−1

@@ -566,7 +566,7 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", · 565 unmodified lines
566	0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);	566	0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
567		567
568	/* Fixed Factor clocks */	568	/* Fixed Factor clocks */
569	static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);	569	static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
570		570
571	/* We hardcode the divider to 4 for now */	571	/* We hardcode the divider to 4 for now */
572	static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",	572	static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

drivers/clk/sunxi-ng/ccu-sun6i-a31.c+1−1

@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, · 607 unmodified lines
608	0x150, 0, 4, 24, 2, BIT(31),	608	0x150, 0, 4, 24, 2, BIT(31),
609	CLK_SET_RATE_PARENT);	609	CLK_SET_RATE_PARENT);
610		610
611	static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);	611	static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
612		612
613	static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);	613	static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
614		614

drivers/clk/sunxi-ng/ccu_mp.c+8−0

 	unsigned int m, p;
 	u32 reg;
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
 	reg = readl(cmp->common.base + cmp->common.reg);
 	m = reg >> cmp->m.shift;
 	unsigned int m, p;
 	u32 reg;
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
 	max_m = cmp->m.max ?: 1 << cmp->m.width;
 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);

drivers/clk/sunxi-ng/ccu_nkmp.c+1−1

@@ -107,7 +107,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw, · 106 unmodified lines
107	p = reg >> nkmp->p.shift;	107	p = reg >> nkmp->p.shift;
108	p &= (1 << nkmp->p.width) - 1;	108	p &= (1 << nkmp->p.width) - 1;
109		109
110	return parent_rate * n * k >> p / m;	110	return (parent_rate * n * k >> p) / m;
111	}	111	}
112		112
113	static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,	113	static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,

drivers/clocksource/tcb_clksrc.c+1−15

 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/atmel_tc.h>
-#include <linux/sched_clock.h>
 /*
 	return (upper << 16) | lower;
 }
-static u32 tc_get_cv32(void)
-{
-	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-}
 static u64 tc_get_cycles32(struct clocksource *cs)
 {
-	return tc_get_cv32();
+	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
 }
 static struct clocksource clksrc = {
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
-static u64 notrace tc_read_sched_clock(void)
-{
-	return tc_get_cv32();
-}
 #ifdef CONFIG_GENERIC_CLOCKEVENTS
 struct tc_clkevt_device {
 		clksrc.read = tc_get_cycles32;
 		/* setup ony channel 0 */
 		tcb_setup_single_chan(tc, best_divisor_idx);
-		/* register sched_clock on chips with single 32 bit counter */
-		sched_clock_register(tc_read_sched_clock, 32, divided_rate);
 	} else {
 		/* tclib will give us three clocks no matter what the
 		 * underlying platform supports.

drivers/cpufreq/cpufreq.c+8−3

@@ -680,9 +680,11 @@ static ssize_t show_cpuinfo_cur_freq(struct cpufreq_policy *policy, · 679 unmodified lines
680	char *buf)	680	char *buf)
681	{	681	{
682	unsigned int cur_freq = __cpufreq_get(policy);	682	unsigned int cur_freq = __cpufreq_get(policy);
683	if (!cur_freq)	683
684	return sprintf(buf, "<unknown>");	684	if (cur_freq)
685	return sprintf(buf, "%u\n", cur_freq);	685	return sprintf(buf, "%u\n", cur_freq);
		686
		687	return sprintf(buf, "<unknown>\n");
686	}	688	}
687		689
688	/**	690	/**
@@ -1182,6 +1184,9 @@ static int cpufreq_online(unsigned int cpu) · 493 unmodified lines
1182	for_each_cpu(j, policy->related_cpus)	1184	for_each_cpu(j, policy->related_cpus)
1183	per_cpu(cpufreq_cpu_data, j) = policy;	1185	per_cpu(cpufreq_cpu_data, j) = policy;
1184	write_unlock_irqrestore(&cpufreq_driver_lock, flags);	1186	write_unlock_irqrestore(&cpufreq_driver_lock, flags);
		1187	} else {
		1188	policy->min = policy->user_policy.min;
		1189	policy->max = policy->user_policy.max;
1185	}	1190	}
1186		1191
1187	if (cpufreq_driver->get && !cpufreq_driver->setpolicy) {	1192	if (cpufreq_driver->get && !cpufreq_driver->setpolicy) {

drivers/cpufreq/intel_pstate.c+79−148

@@ -84,6 +84,11 @@ static inline u64 div_ext_fp(u64 x, u64 y) · 83 unmodified lines
84	return div64_u64(x << EXT_FRAC_BITS, y);	84	return div64_u64(x << EXT_FRAC_BITS, y);
85	}	85	}
86		86
		87	static inline int32_t percent_ext_fp(int percent)
		88	{
		89	return div_ext_fp(percent, 100);
		90	}
		91
87	/**	92	/**
88	* struct sample - Store performance sample	93	* struct sample - Store performance sample
89	* @core_avg_perf: Ratio of APERF/MPERF which is the actual average	94	* @core_avg_perf: Ratio of APERF/MPERF which is the actual average
@@ -359,9 +364,7 @@ static bool driver_registered __read_mostly; · 269 unmodified lines
359	static bool acpi_ppc;	364	static bool acpi_ppc;
360	#endif	365	#endif
361		366
362	static struct perf_limits performance_limits;	367	static struct perf_limits global;
363	static struct perf_limits powersave_limits;
364	static struct perf_limits *limits;
365		368
366	static void intel_pstate_init_limits(struct perf_limits *limits)	369	static void intel_pstate_init_limits(struct perf_limits *limits)
367	{	370	{
@@ -372,14 +375,6 @@ static void intel_pstate_init_limits(struct perf_limits *limits) · 4 unmodified lines
372	limits->max_sysfs_pct = 100;	375	limits->max_sysfs_pct = 100;
373	}	376	}
374		377
375	static void intel_pstate_set_performance_limits(struct perf_limits *limits)
376	{
377	intel_pstate_init_limits(limits);
378	limits->min_perf_pct = 100;
379	limits->min_perf = int_ext_tofp(1);
380	limits->min_sysfs_pct = 100;
381	}
382
383	static DEFINE_MUTEX(intel_pstate_driver_lock);	378	static DEFINE_MUTEX(intel_pstate_driver_lock);
384	static DEFINE_MUTEX(intel_pstate_limits_lock);	379	static DEFINE_MUTEX(intel_pstate_limits_lock);
385		380
@@ -502,7 +497,7 @@ static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) · 116 unmodified lines
502	* correct max turbo frequency based on the turbo state.	497	* correct max turbo frequency based on the turbo state.
503	* Also need to convert to MHz as _PSS freq is in MHz.	498	* Also need to convert to MHz as _PSS freq is in MHz.
504	*/	499	*/
505	if (!limits->turbo_disabled)	500	if (!global.turbo_disabled)
506	cpu->acpi_perf_data.states[0].core_frequency =	501	cpu->acpi_perf_data.states[0].core_frequency =
507	policy->cpuinfo.max_freq / 1000;	502	policy->cpuinfo.max_freq / 1000;
508	cpu->valid_pss_table = true;	503	cpu->valid_pss_table = true;
@@ -621,7 +616,7 @@ static inline void update_turbo_state(void) · 112 unmodified lines
621		616
622	cpu = all_cpu_data[0];	617	cpu = all_cpu_data[0];
623	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);	618	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
624	limits->turbo_disabled =	619	global.turbo_disabled =
625	(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE \|\|	620	(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE \|\|
626	cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);	621	cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
627	}	622	}
@@ -845,12 +840,11 @@ static struct freq_attr *hwp_cpufreq_attrs[] = { · 217 unmodified lines
845		840
846	static void intel_pstate_hwp_set(struct cpufreq_policy *policy)	841	static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
847	{	842	{
848	int min, hw_min, max, hw_max, cpu, range, adj_range;	843	int min, hw_min, max, hw_max, cpu;
849	struct perf_limits *perf_limits = limits;	844	struct perf_limits *perf_limits = &global;
850	u64 value, cap;	845	u64 value, cap;
851		846
852	for_each_cpu(cpu, policy->cpus) {	847	for_each_cpu(cpu, policy->cpus) {
853	int max_perf_pct, min_perf_pct;
854	struct cpudata *cpu_data = all_cpu_data[cpu];	848	struct cpudata *cpu_data = all_cpu_data[cpu];
855	s16 epp;	849	s16 epp;
856		850
@@ -859,24 +853,22 @@ static void intel_pstate_hwp_set(struct cpufreq_policy *policy) · 2 unmodified lines
859		853
860	rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);	854	rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
861	hw_min = HWP_LOWEST_PERF(cap);	855	hw_min = HWP_LOWEST_PERF(cap);
862	if (limits->no_turbo)	856	if (global.no_turbo)
863	hw_max = HWP_GUARANTEED_PERF(cap);	857	hw_max = HWP_GUARANTEED_PERF(cap);
864	else	858	else
865	hw_max = HWP_HIGHEST_PERF(cap);	859	hw_max = HWP_HIGHEST_PERF(cap);
866	range = hw_max - hw_min;
867		860
868	max_perf_pct = perf_limits->max_perf_pct;	861	max = fp_ext_toint(hw_max * perf_limits->max_perf);
869	min_perf_pct = perf_limits->min_perf_pct;	862	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
		863	min = max;
		864	else
		865	min = fp_ext_toint(hw_max * perf_limits->min_perf);
870		866
871	rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);	867	rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
872	adj_range = min_perf_pct * range / 100;	868
873	min = hw_min + adj_range;
874	value &= ~HWP_MIN_PERF(~0L);	869	value &= ~HWP_MIN_PERF(~0L);
875	value \|= HWP_MIN_PERF(min);	870	value \|= HWP_MIN_PERF(min);
876		871
877	adj_range = max_perf_pct * range / 100;
878	max = hw_min + adj_range;
879
880	value &= ~HWP_MAX_PERF(~0L);	872	value &= ~HWP_MAX_PERF(~0L);
881	value \|= HWP_MAX_PERF(max);	873	value \|= HWP_MAX_PERF(max);
882		874
@@ -969,26 +961,18 @@ static int intel_pstate_resume(struct cpufreq_policy *policy) · 86 unmodified lines
969	}	961	}
970		962
971	static void intel_pstate_update_policies(void)	963	static void intel_pstate_update_policies(void)
972	__releases(&intel_pstate_limits_lock)
973	__acquires(&intel_pstate_limits_lock)
974	{	964	{
975	struct perf_limits *saved_limits = limits;
976	int cpu;	965	int cpu;
977		966
978	mutex_unlock(&intel_pstate_limits_lock);
979
980	for_each_possible_cpu(cpu)	967	for_each_possible_cpu(cpu)
981	cpufreq_update_policy(cpu);	968	cpufreq_update_policy(cpu);
982
983	mutex_lock(&intel_pstate_limits_lock);
984
985	limits = saved_limits;
986	}	969	}
987		970
988	/************************ debugfs begin **********************/	971	/************************ debugfs begin **********************/
989	static int pid_param_set(void *data, u64 val)	972	static int pid_param_set(void *data, u64 val)
990	{	973	{
991	(u32 )data = val;	974	(u32 )data = val;
		975	pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
992	intel_pstate_reset_all_pid();	976	intel_pstate_reset_all_pid();
993	return 0;	977	return 0;
994	}	978	}
@@ -1060,7 +1044,7 @@ static void intel_pstate_debug_hide_params(void) · 65 unmodified lines
1060	static ssize_t show_##file_name \	1044	static ssize_t show_##file_name \
1061	(struct kobject kobj, struct attribute attr, char *buf) \	1045	(struct kobject kobj, struct attribute attr, char *buf) \
1062	{ \	1046	{ \
1063	return sprintf(buf, "%u\n", limits->object); \	1047	return sprintf(buf, "%u\n", global.object); \
1064	}	1048	}
1065		1049
1066	static ssize_t intel_pstate_show_status(char *buf);	1050	static ssize_t intel_pstate_show_status(char *buf);
@@ -1151,10 +1135,10 @@ static ssize_t show_no_turbo(struct kobject *kobj, · 84 unmodified lines
1151	}	1135	}
1152		1136
1153	update_turbo_state();	1137	update_turbo_state();
1154	if (limits->turbo_disabled)	1138	if (global.turbo_disabled)
1155	ret = sprintf(buf, "%u\n", limits->turbo_disabled);	1139	ret = sprintf(buf, "%u\n", global.turbo_disabled);
1156	else	1140	else
1157	ret = sprintf(buf, "%u\n", limits->no_turbo);	1141	ret = sprintf(buf, "%u\n", global.no_turbo);
1158		1142
1159	mutex_unlock(&intel_pstate_driver_lock);	1143	mutex_unlock(&intel_pstate_driver_lock);
1160		1144
@@ -1181,19 +1165,19 @@ static ssize_t store_no_turbo(struct kobject a, struct attribute b, · 20 unmodified lines
1181	mutex_lock(&intel_pstate_limits_lock);	1165	mutex_lock(&intel_pstate_limits_lock);
1182		1166
1183	update_turbo_state();	1167	update_turbo_state();
1184	if (limits->turbo_disabled) {	1168	if (global.turbo_disabled) {
1185	pr_warn("Turbo disabled by BIOS or unavailable on processor\n");	1169	pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1186	mutex_unlock(&intel_pstate_limits_lock);	1170	mutex_unlock(&intel_pstate_limits_lock);
1187	mutex_unlock(&intel_pstate_driver_lock);	1171	mutex_unlock(&intel_pstate_driver_lock);
1188	return -EPERM;	1172	return -EPERM;
1189	}	1173	}
1190		1174
1191	limits->no_turbo = clamp_t(int, input, 0, 1);	1175	global.no_turbo = clamp_t(int, input, 0, 1);
1192
1193	intel_pstate_update_policies();
1194		1176
1195	mutex_unlock(&intel_pstate_limits_lock);	1177	mutex_unlock(&intel_pstate_limits_lock);
1196		1178
		1179	intel_pstate_update_policies();
		1180
1197	mutex_unlock(&intel_pstate_driver_lock);	1181	mutex_unlock(&intel_pstate_driver_lock);
1198		1182
1199	return count;	1183	return count;
@@ -1218,19 +1202,16 @@ static ssize_t store_max_perf_pct(struct kobject a, struct attribute b, · 18 unmodified lines
1218		1202
1219	mutex_lock(&intel_pstate_limits_lock);	1203	mutex_lock(&intel_pstate_limits_lock);
1220		1204
1221	limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);	1205	global.max_sysfs_pct = clamp_t(int, input, 0 , 100);
1222	limits->max_perf_pct = min(limits->max_policy_pct,	1206	global.max_perf_pct = min(global.max_policy_pct, global.max_sysfs_pct);
1223	limits->max_sysfs_pct);	1207	global.max_perf_pct = max(global.min_policy_pct, global.max_perf_pct);
1224	limits->max_perf_pct = max(limits->min_policy_pct,	1208	global.max_perf_pct = max(global.min_perf_pct, global.max_perf_pct);
1225	limits->max_perf_pct);	1209	global.max_perf = percent_ext_fp(global.max_perf_pct);
1226	limits->max_perf_pct = max(limits->min_perf_pct,
1227	limits->max_perf_pct);
1228	limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1229
1230	intel_pstate_update_policies();
1231		1210
1232	mutex_unlock(&intel_pstate_limits_lock);	1211	mutex_unlock(&intel_pstate_limits_lock);
1233		1212
		1213	intel_pstate_update_policies();
		1214
1234	mutex_unlock(&intel_pstate_driver_lock);	1215	mutex_unlock(&intel_pstate_driver_lock);
1235		1216
1236	return count;	1217	return count;
@@ -1255,19 +1236,16 @@ static ssize_t store_min_perf_pct(struct kobject a, struct attribute b, · 18 unmodified lines
1255		1236
1256	mutex_lock(&intel_pstate_limits_lock);	1237	mutex_lock(&intel_pstate_limits_lock);
1257		1238
1258	limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);	1239	global.min_sysfs_pct = clamp_t(int, input, 0 , 100);
1259	limits->min_perf_pct = max(limits->min_policy_pct,	1240	global.min_perf_pct = max(global.min_policy_pct, global.min_sysfs_pct);
1260	limits->min_sysfs_pct);	1241	global.min_perf_pct = min(global.max_policy_pct, global.min_perf_pct);
1261	limits->min_perf_pct = min(limits->max_policy_pct,	1242	global.min_perf_pct = min(global.max_perf_pct, global.min_perf_pct);
1262	limits->min_perf_pct);	1243	global.min_perf = percent_ext_fp(global.min_perf_pct);
1263	limits->min_perf_pct = min(limits->max_perf_pct,
1264	limits->min_perf_pct);
1265	limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1266
1267	intel_pstate_update_policies();
1268		1244
1269	mutex_unlock(&intel_pstate_limits_lock);	1245	mutex_unlock(&intel_pstate_limits_lock);
1270		1246
		1247	intel_pstate_update_policies();
		1248
1271	mutex_unlock(&intel_pstate_driver_lock);	1249	mutex_unlock(&intel_pstate_driver_lock);
1272		1250
1273	return count;	1251	return count;
@@ -1387,7 +1365,7 @@ static u64 atom_get_val(struct cpudata *cpudata, int pstate) · 113 unmodified lines
1387	u32 vid;	1365	u32 vid;
1388		1366
1389	val = (u64)pstate << 8;	1367	val = (u64)pstate << 8;
1390	if (limits->no_turbo && !limits->turbo_disabled)	1368	if (global.no_turbo && !global.turbo_disabled)
1391	val \|= (u64)1 << 32;	1369	val \|= (u64)1 << 32;
1392		1370
1393	vid_fp = cpudata->vid.min + mul_fp(	1371	vid_fp = cpudata->vid.min + mul_fp(
@@ -1557,7 +1535,7 @@ static u64 core_get_val(struct cpudata *cpudata, int pstate) · 163 unmodified lines
1557	u64 val;	1535	u64 val;
1558		1536
1559	val = (u64)pstate << 8;	1537	val = (u64)pstate << 8;
1560	if (limits->no_turbo && !limits->turbo_disabled)	1538	if (global.no_turbo && !global.turbo_disabled)
1561	val \|= (u64)1 << 32;	1539	val \|= (u64)1 << 32;
1562		1540
1563	return val;	1541	return val;
@@ -1683,9 +1661,9 @@ static void intel_pstate_get_min_max(struct cpudata cpu, int min, int *max) · 119 unmodified lines
1683	int max_perf = cpu->pstate.turbo_pstate;	1661	int max_perf = cpu->pstate.turbo_pstate;
1684	int max_perf_adj;	1662	int max_perf_adj;
1685	int min_perf;	1663	int min_perf;
1686	struct perf_limits *perf_limits = limits;	1664	struct perf_limits *perf_limits = &global;
1687		1665
1688	if (limits->no_turbo \|\| limits->turbo_disabled)	1666	if (global.no_turbo \|\| global.turbo_disabled)
1689	max_perf = cpu->pstate.max_pstate;	1667	max_perf = cpu->pstate.max_pstate;
1690		1668
1691	if (per_cpu_limits)	1669	if (per_cpu_limits)
@@ -1820,7 +1798,7 @@ static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) · 128 unmodified lines
1820		1798
1821	sample->busy_scaled = busy_frac * 100;	1799	sample->busy_scaled = busy_frac * 100;
1822		1800
1823	target = limits->no_turbo \|\| limits->turbo_disabled ?	1801	target = global.no_turbo \|\| global.turbo_disabled ?
1824	cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;	1802	cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1825	target += target >> 2;	1803	target += target >> 2;
1826	target = mul_fp(target, busy_frac);	1804	target = mul_fp(target, busy_frac);
@@ -2080,36 +2058,34 @@ static void intel_pstate_clear_update_util_hook(unsigned int cpu) · 253 unmodified lines
2080	static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,	2058	static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2081	struct perf_limits *limits)	2059	struct perf_limits *limits)
2082	{	2060	{
		2061	int32_t max_policy_perf, min_policy_perf;
2083		2062
2084	limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,	2063	max_policy_perf = div_ext_fp(policy->max, policy->cpuinfo.max_freq);
2085	policy->cpuinfo.max_freq);	2064	max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
2086	limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2087	if (policy->max == policy->min) {	2065	if (policy->max == policy->min) {
2088	limits->min_policy_pct = limits->max_policy_pct;	2066	min_policy_perf = max_policy_perf;
2089	} else {	2067	} else {
2090	limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,	2068	min_policy_perf = div_ext_fp(policy->min,
2091	policy->cpuinfo.max_freq);	2069	policy->cpuinfo.max_freq);
2092	limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,	2070	min_policy_perf = clamp_t(int32_t, min_policy_perf,
2093	0, 100);	2071	0, max_policy_perf);
2094	}	2072	}
2095		2073
2096	/* Normalize user input to [min_policy_pct, max_policy_pct] */	2074	/* Normalize user input to [min_perf, max_perf] */
2097	limits->min_perf_pct = max(limits->min_policy_pct,	2075	limits->min_perf = max(min_policy_perf,
2098	limits->min_sysfs_pct);	2076	percent_ext_fp(limits->min_sysfs_pct));
2099	limits->min_perf_pct = min(limits->max_policy_pct,	2077	limits->min_perf = min(limits->min_perf, max_policy_perf);
2100	limits->min_perf_pct);	2078	limits->max_perf = min(max_policy_perf,
2101	limits->max_perf_pct = min(limits->max_policy_pct,	2079	percent_ext_fp(limits->max_sysfs_pct));
2102	limits->max_sysfs_pct);	2080	limits->max_perf = max(min_policy_perf, limits->max_perf);
2103	limits->max_perf_pct = max(limits->min_policy_pct,	2081
2104	limits->max_perf_pct);	2082	/* Make sure min_perf <= max_perf */
2105		2083	limits->min_perf = min(limits->min_perf, limits->max_perf);
2106	/* Make sure min_perf_pct <= max_perf_pct */	2084
2107	limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2108
2109	limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2110	limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2111	limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);	2085	limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2112	limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);	2086	limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
		2087	limits->max_perf_pct = fp_ext_toint(limits->max_perf * 100);
		2088	limits->min_perf_pct = fp_ext_toint(limits->min_perf * 100);
2113		2089
2114	pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,	2090	pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2115	limits->max_perf_pct, limits->min_perf_pct);	2091	limits->max_perf_pct, limits->min_perf_pct);
@@ -2118,7 +2094,7 @@ static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, · 2 unmodified lines
2118	static int intel_pstate_set_policy(struct cpufreq_policy *policy)	2094	static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2119	{	2095	{
2120	struct cpudata *cpu;	2096	struct cpudata *cpu;
2121	struct perf_limits *perf_limits = NULL;	2097	struct perf_limits *perf_limits = &global;
2122		2098
2123	if (!policy->cpuinfo.max_freq)	2099	if (!policy->cpuinfo.max_freq)
2124	return -ENODEV;	2100	return -ENODEV;
@@ -2141,21 +2117,6 @@ static int intel_pstate_set_policy(struct cpufreq_policy *policy) · 16 unmodified lines
2141		2117
2142	mutex_lock(&intel_pstate_limits_lock);	2118	mutex_lock(&intel_pstate_limits_lock);
2143		2119
2144	if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2145	pr_debug("set performance\n");
2146	if (!perf_limits) {
2147	limits = &performance_limits;
2148	perf_limits = limits;
2149	}
2150	} else {
2151	pr_debug("set powersave\n");
2152	if (!perf_limits) {
2153	limits = &powersave_limits;
2154	perf_limits = limits;
2155	}
2156
2157	}
2158
2159	intel_pstate_update_perf_limits(policy, perf_limits);	2120	intel_pstate_update_perf_limits(policy, perf_limits);
2160		2121
2161	if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {	2122	if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
@@ -2179,16 +2140,9 @@ static int intel_pstate_set_policy(struct cpufreq_policy *policy) · 17 unmodified lines
2179	static int intel_pstate_verify_policy(struct cpufreq_policy *policy)	2140	static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2180	{	2141	{
2181	struct cpudata *cpu = all_cpu_data[policy->cpu];	2142	struct cpudata *cpu = all_cpu_data[policy->cpu];
2182	struct perf_limits *perf_limits;
2183
2184	if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2185	perf_limits = &performance_limits;
2186	else
2187	perf_limits = &powersave_limits;
2188		2143
2189	update_turbo_state();	2144	update_turbo_state();
2190	policy->cpuinfo.max_freq = perf_limits->turbo_disabled \|\|	2145	policy->cpuinfo.max_freq = global.turbo_disabled \|\| global.no_turbo ?
2191	perf_limits->no_turbo ?
2192	cpu->pstate.max_freq :	2146	cpu->pstate.max_freq :
2193	cpu->pstate.turbo_freq;	2147	cpu->pstate.turbo_freq;
2194		2148
@@ -2203,9 +2157,9 @@ static int intel_pstate_verify_policy(struct cpufreq_policy *policy) · 8 unmodified lines
2203	unsigned int max_freq, min_freq;	2157	unsigned int max_freq, min_freq;
2204		2158
2205	max_freq = policy->cpuinfo.max_freq *	2159	max_freq = policy->cpuinfo.max_freq *
2206	perf_limits->max_sysfs_pct / 100;	2160	global.max_sysfs_pct / 100;
2207	min_freq = policy->cpuinfo.max_freq *	2161	min_freq = policy->cpuinfo.max_freq *
2208	perf_limits->min_sysfs_pct / 100;	2162	global.min_sysfs_pct / 100;
2209	cpufreq_verify_within_limits(policy, min_freq, max_freq);	2163	cpufreq_verify_within_limits(policy, min_freq, max_freq);
2210	}	2164	}
2211		2165
@@ -2257,7 +2211,7 @@ static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) · 45 unmodified lines
2257	/* cpuinfo and default policy values */	2211	/* cpuinfo and default policy values */
2258	policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;	2212	policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2259	update_turbo_state();	2213	update_turbo_state();
2260	policy->cpuinfo.max_freq = limits->turbo_disabled ?	2214	policy->cpuinfo.max_freq = global.turbo_disabled ?
2261	cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;	2215	cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2262	policy->cpuinfo.max_freq *= cpu->pstate.scaling;	2216	policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2263		2217
@@ -2277,7 +2231,7 @@ static int intel_pstate_cpu_init(struct cpufreq_policy *policy) · 13 unmodified lines
2277	return ret;	2231	return ret;
2278		2232
2279	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;	2233	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2280	if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)	2234	if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2281	policy->policy = CPUFREQ_POLICY_PERFORMANCE;	2235	policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2282	else	2236	else
2283	policy->policy = CPUFREQ_POLICY_POWERSAVE;	2237	policy->policy = CPUFREQ_POLICY_POWERSAVE;
@@ -2303,7 +2257,7 @@ static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) · 19 unmodified lines
2303	struct cpudata *cpu = all_cpu_data[policy->cpu];	2257	struct cpudata *cpu = all_cpu_data[policy->cpu];
2304		2258
2305	update_turbo_state();	2259	update_turbo_state();
2306	policy->cpuinfo.max_freq = limits->turbo_disabled ?	2260	policy->cpuinfo.max_freq = global.no_turbo \|\| global.turbo_disabled ?
2307	cpu->pstate.max_freq : cpu->pstate.turbo_freq;	2261	cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2308		2262
2309	cpufreq_verify_within_cpu_limits(policy);	2263	cpufreq_verify_within_cpu_limits(policy);
@@ -2311,26 +2265,6 @@ static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) · 1 unmodified line
2311	return 0;	2265	return 0;
2312	}	2266	}
2313		2267
2314	static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2315	struct cpufreq_policy *policy,
2316	unsigned int target_freq)
2317	{
2318	unsigned int max_freq;
2319
2320	update_turbo_state();
2321
2322	max_freq = limits->no_turbo \|\| limits->turbo_disabled ?
2323	cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2324	policy->cpuinfo.max_freq = max_freq;
2325	if (policy->max > max_freq)
2326	policy->max = max_freq;
2327
2328	if (target_freq > max_freq)
2329	target_freq = max_freq;
2330
2331	return target_freq;
2332	}
2333
2334	static int intel_cpufreq_target(struct cpufreq_policy *policy,	2268	static int intel_cpufreq_target(struct cpufreq_policy *policy,
2335	unsigned int target_freq,	2269	unsigned int target_freq,
2336	unsigned int relation)	2270	unsigned int relation)
@@ -2339,8 +2273,10 @@ static int intel_cpufreq_target(struct cpufreq_policy *policy, · 2 unmodified lines
2339	struct cpufreq_freqs freqs;	2273	struct cpufreq_freqs freqs;
2340	int target_pstate;	2274	int target_pstate;
2341		2275
		2276	update_turbo_state();
		2277
2342	freqs.old = policy->cur;	2278	freqs.old = policy->cur;
2343	freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);	2279	freqs.new = target_freq;
2344		2280
2345	cpufreq_freq_transition_begin(policy, &freqs);	2281	cpufreq_freq_transition_begin(policy, &freqs);
2346	switch (relation) {	2282	switch (relation) {
@@ -2372,7 +2308,8 @@ static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, · 25 unmodified lines
2372	struct cpudata *cpu = all_cpu_data[policy->cpu];	2308	struct cpudata *cpu = all_cpu_data[policy->cpu];
2373	int target_pstate;	2309	int target_pstate;
2374		2310
2375	target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);	2311	update_turbo_state();
		2312
2376	target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);	2313	target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2377	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);	2314	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2378	intel_pstate_update_pstate(cpu, target_pstate);	2315	intel_pstate_update_pstate(cpu, target_pstate);
@@ -2427,13 +2364,7 @@ static int intel_pstate_register_driver(void) · 48 unmodified lines
2427	{	2364	{
2428	int ret;	2365	int ret;
2429		2366
2430	intel_pstate_init_limits(&powersave_limits);	2367	intel_pstate_init_limits(&global);
2431	intel_pstate_set_performance_limits(&performance_limits);
2432	if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) &&
2433	intel_pstate_driver == &intel_pstate)
2434	limits = &performance_limits;
2435	else
2436	limits = &powersave_limits;
2437		2368
2438	ret = cpufreq_register_driver(intel_pstate_driver);	2369	ret = cpufreq_register_driver(intel_pstate_driver);
2439	if (ret) {	2370	if (ret) {

drivers/cpuidle/sysfs.c+12−0

@@ -615,6 +615,18 @@ int cpuidle_add_sysfs(struct cpuidle_device *dev) · 614 unmodified lines
615	struct device *cpu_dev = get_cpu_device((unsigned long)dev->cpu);	615	struct device *cpu_dev = get_cpu_device((unsigned long)dev->cpu);
616	int error;	616	int error;
617		617
		618	/*
		619	* Return if cpu_device is not setup for this CPU.
		620	*
		621	* This could happen if the arch did not set up cpu_device
		622	* since this CPU is not in cpu_present mask and the
		623	* driver did not send a correct CPU mask during registration.
		624	* Without this check we would end up passing bogus
		625	* value for &cpu_dev->kobj in kobject_init_and_add()
		626	*/
		627	if (!cpu_dev)
		628	return -ENODEV;
		629
618	kdev = kzalloc(sizeof(*kdev), GFP_KERNEL);	630	kdev = kzalloc(sizeof(*kdev), GFP_KERNEL);
619	if (!kdev)	631	if (!kdev)
620	return -ENOMEM;	632	return -ENOMEM;

drivers/crypto/ccp/ccp-dev.c+4−1

  */
 int ccp_enqueue_cmd(struct ccp_cmd *cmd)
 {
-	struct ccp_device *ccp = ccp_get_device();
+	struct ccp_device *ccp;
 	unsigned long flags;
 	unsigned int i;
 	int ret;
+	/* Some commands might need to be sent to a specific device */
+	ccp = cmd->ccp ? cmd->ccp : ccp_get_device();
 	if (!ccp)
 		return -ENODEV;

drivers/crypto/ccp/ccp-dmaengine.c+1−0

@@ -390,6 +390,7 @@ static struct ccp_dma_desc ccp_create_desc(struct dma_chan dma_chan, · 389 unmodified lines
390	goto err;	390	goto err;
391		391
392	ccp_cmd = &cmd->ccp_cmd;	392	ccp_cmd = &cmd->ccp_cmd;
		393	ccp_cmd->ccp = chan->ccp;
393	ccp_pt = &ccp_cmd->u.passthru_nomap;	394	ccp_pt = &ccp_cmd->u.passthru_nomap;
394	ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;	395	ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;
395	ccp_cmd->flags \|= CCP_CMD_PASSTHRU_NO_DMA_MAP;	396	ccp_cmd->flags \|= CCP_CMD_PASSTHRU_NO_DMA_MAP;

drivers/crypto/s5p-sss.c+85−47

@@ -270,7 +270,7 @@ static void s5p_sg_copy_buf(void buf, struct scatterlist sg, · 269 unmodified lines
270	scatterwalk_done(&walk, out, 0);	270	scatterwalk_done(&walk, out, 0);
271	}	271	}
272		272
273	static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)	273	static void s5p_sg_done(struct s5p_aes_dev *dev)
274	{	274	{
275	if (dev->sg_dst_cpy) {	275	if (dev->sg_dst_cpy) {
276	dev_dbg(dev->dev,	276	dev_dbg(dev->dev,
@@ -281,8 +281,11 @@ static void s5p_aes_complete(struct s5p_aes_dev *dev, int err) · 4 unmodified lines
281	}	281	}
282	s5p_free_sg_cpy(dev, &dev->sg_src_cpy);	282	s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
283	s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);	283	s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
		284	}
284		285
285	/* holding a lock outside */	286	/* Calls the completion. Cannot be called with dev->lock hold. */
		287	static void s5p_aes_complete(struct s5p_aes_dev *dev, int err)
		288	{
286	dev->req->base.complete(&dev->req->base, err);	289	dev->req->base.complete(&dev->req->base, err);
287	dev->busy = false;	290	dev->busy = false;
288	}	291	}
@@ -368,51 +371,44 @@ exit: · 79 unmodified lines
368	}	371	}
369		372
370	/*	373	/*
371	* Returns true if new transmitting (output) data is ready and its	374	* Returns -ERRNO on error (mapping of new data failed).
372	* address+length have to be written to device (by calling	375	* On success returns:
373	* s5p_set_dma_outdata()). False otherwise.	376	* - 0 if there is no more data,
		377	* - 1 if new transmitting (output) data is ready and its address+length
		378	* have to be written to device (by calling s5p_set_dma_outdata()).
374	*/	379	*/
375	static bool s5p_aes_tx(struct s5p_aes_dev *dev)	380	static int s5p_aes_tx(struct s5p_aes_dev *dev)
376	{	381	{
377	int err = 0;	382	int ret = 0;
378	bool ret = false;
379		383
380	s5p_unset_outdata(dev);	384	s5p_unset_outdata(dev);
381		385
382	if (!sg_is_last(dev->sg_dst)) {	386	if (!sg_is_last(dev->sg_dst)) {
383	err = s5p_set_outdata(dev, sg_next(dev->sg_dst));	387	ret = s5p_set_outdata(dev, sg_next(dev->sg_dst));
384	if (err)	388	if (!ret)
385	s5p_aes_complete(dev, err);	389	ret = 1;
386	else
387	ret = true;
388	} else {
389	s5p_aes_complete(dev, err);
390
391	dev->busy = true;
392	tasklet_schedule(&dev->tasklet);
393	}	390	}
394		391
395	return ret;	392	return ret;
396	}	393	}
397		394
398	/*	395	/*
399	* Returns true if new receiving (input) data is ready and its	396	* Returns -ERRNO on error (mapping of new data failed).
400	* address+length have to be written to device (by calling	397	* On success returns:
401	* s5p_set_dma_indata()). False otherwise.	398	* - 0 if there is no more data,
		399	* - 1 if new receiving (input) data is ready and its address+length
		400	* have to be written to device (by calling s5p_set_dma_indata()).
402	*/	401	*/
403	static bool s5p_aes_rx(struct s5p_aes_dev *dev)	402	static int s5p_aes_rx(struct s5p_aes_dev dev/, bool set_dma/)
404	{	403	{
405	int err;	404	int ret = 0;
406	bool ret = false;
407		405
408	s5p_unset_indata(dev);	406	s5p_unset_indata(dev);
409		407
410	if (!sg_is_last(dev->sg_src)) {	408	if (!sg_is_last(dev->sg_src)) {
411	err = s5p_set_indata(dev, sg_next(dev->sg_src));	409	ret = s5p_set_indata(dev, sg_next(dev->sg_src));
412	if (err)	410	if (!ret)
413	s5p_aes_complete(dev, err);	411	ret = 1;
414	else
415	ret = true;
416	}	412	}
417		413
418	return ret;	414	return ret;
@@ -422,33 +418,73 @@ static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) · 3 unmodified lines
422	{	418	{
423	struct platform_device *pdev = dev_id;	419	struct platform_device *pdev = dev_id;
424	struct s5p_aes_dev *dev = platform_get_drvdata(pdev);	420	struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
425	bool set_dma_tx = false;	421	int err_dma_tx = 0;
426	bool set_dma_rx = false;	422	int err_dma_rx = 0;
		423	bool tx_end = false;
427	unsigned long flags;	424	unsigned long flags;
428	uint32_t status;	425	uint32_t status;
		426	int err;
429		427
430	spin_lock_irqsave(&dev->lock, flags);	428	spin_lock_irqsave(&dev->lock, flags);
431		429
		430	/*
		431	* Handle rx or tx interrupt. If there is still data (scatterlist did not
		432	* reach end), then map next scatterlist entry.
		433	* In case of such mapping error, s5p_aes_complete() should be called.
		434	*
		435	* If there is no more data in tx scatter list, call s5p_aes_complete()
		436	* and schedule new tasklet.
		437	*/
432	status = SSS_READ(dev, FCINTSTAT);	438	status = SSS_READ(dev, FCINTSTAT);
433	if (status & SSS_FCINTSTAT_BRDMAINT)	439	if (status & SSS_FCINTSTAT_BRDMAINT)
434	set_dma_rx = s5p_aes_rx(dev);	440	err_dma_rx = s5p_aes_rx(dev);
435	if (status & SSS_FCINTSTAT_BTDMAINT)	441
436	set_dma_tx = s5p_aes_tx(dev);	442	if (status & SSS_FCINTSTAT_BTDMAINT) {
		443	if (sg_is_last(dev->sg_dst))
		444	tx_end = true;
		445	err_dma_tx = s5p_aes_tx(dev);
		446	}
437		447
438	SSS_WRITE(dev, FCINTPEND, status);	448	SSS_WRITE(dev, FCINTPEND, status);
439		449
440	/*	450	if (err_dma_rx < 0) {
441	* Writing length of DMA block (either receiving or transmitting)	451	err = err_dma_rx;
442	* will start the operation immediately, so this should be done	452	goto error;
443	* at the end (even after clearing pending interrupts to not miss the	453	}
444	* interrupt).	454	if (err_dma_tx < 0) {
445	*/	455	err = err_dma_tx;
446	if (set_dma_tx)	456	goto error;
447	s5p_set_dma_outdata(dev, dev->sg_dst);	457	}
448	if (set_dma_rx)	458
449	s5p_set_dma_indata(dev, dev->sg_src);	459	if (tx_end) {
		460	s5p_sg_done(dev);
		461
		462	spin_unlock_irqrestore(&dev->lock, flags);
		463
		464	s5p_aes_complete(dev, 0);
		465	dev->busy = true;
		466	tasklet_schedule(&dev->tasklet);
		467	} else {
		468	/*
		469	* Writing length of DMA block (either receiving or
		470	* transmitting) will start the operation immediately, so this
		471	* should be done at the end (even after clearing pending
		472	* interrupts to not miss the interrupt).
		473	*/
		474	if (err_dma_tx == 1)
		475	s5p_set_dma_outdata(dev, dev->sg_dst);
		476	if (err_dma_rx == 1)
		477	s5p_set_dma_indata(dev, dev->sg_src);
450		478
		479	spin_unlock_irqrestore(&dev->lock, flags);
		480	}
		481
		482	return IRQ_HANDLED;
		483
		484	error:
		485	s5p_sg_done(dev);
451	spin_unlock_irqrestore(&dev->lock, flags);	486	spin_unlock_irqrestore(&dev->lock, flags);
		487	s5p_aes_complete(dev, err);
452		488
453	return IRQ_HANDLED;	489	return IRQ_HANDLED;
454	}	490	}
@@ -597,8 +633,9 @@ outdata_error: · 142 unmodified lines
597	s5p_unset_indata(dev);	633	s5p_unset_indata(dev);
598		634
599	indata_error:	635	indata_error:
600	s5p_aes_complete(dev, err);	636	s5p_sg_done(dev);
601	spin_unlock_irqrestore(&dev->lock, flags);	637	spin_unlock_irqrestore(&dev->lock, flags);
		638	s5p_aes_complete(dev, err);
602	}	639	}
603		640
604	static void s5p_tasklet_cb(unsigned long data)	641	static void s5p_tasklet_cb(unsigned long data)
@@ -805,8 +842,9 @@ static int s5p_aes_probe(struct platform_device *pdev) · 200 unmodified lines
805	dev_warn(dev, "feed control interrupt is not available.\n");	842	dev_warn(dev, "feed control interrupt is not available.\n");
806	goto err_irq;	843	goto err_irq;
807	}	844	}
808	err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,	845	err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL,
809	IRQF_SHARED, pdev->name, pdev);	846	s5p_aes_interrupt, IRQF_ONESHOT,
		847	pdev->name, pdev);
810	if (err < 0) {	848	if (err < 0) {
811	dev_warn(dev, "feed control interrupt is not available.\n");	849	dev_warn(dev, "feed control interrupt is not available.\n");
812	goto err_irq;	850	goto err_irq;

drivers/dax/Kconfig+1−0

@@ -2,6 +2,7 @@ menuconfig DEV_DAX · 1 unmodified line
2	tristate "DAX: direct access to differentiated memory"	2	tristate "DAX: direct access to differentiated memory"
3	default m if NVDIMM_DAX	3	default m if NVDIMM_DAX
4	depends on TRANSPARENT_HUGEPAGE	4	depends on TRANSPARENT_HUGEPAGE
		5	select SRCU
5	help	6	help
6	Support raw access to differentiated (persistence, bandwidth,	7	Support raw access to differentiated (persistence, bandwidth,
7	latency...) memory via an mmap(2) capable character	8	latency...) memory via an mmap(2) capable character

drivers/dax/dax.c+37−9

 #include "dax.h"
 static dev_t dax_devt;
+DEFINE_STATIC_SRCU(dax_srcu);
 static struct class *dax_class;
 static DEFINE_IDA(dax_minor_ida);
 static int nr_dax = CONFIG_NR_DEV_DAX;
  * @region - parent region
  * @dev - device backing the character device
  * @cdev - core chardev data
- * @alive - !alive + rcu grace period == no new mappings can be established
+ * @alive - !alive + srcu grace period == no new mappings can be established
  * @id - child id in the region
  * @num_resources - number of physical address extents in this device
  * @res - array of physical address ranges
 	int rc = VM_FAULT_SIGBUS;
 	phys_addr_t phys;
 	pfn_t pfn;
+	unsigned int fault_size = PAGE_SIZE;
 	if (check_vma(dax_dev, vmf->vma, __func__))
 		return VM_FAULT_SIGBUS;
 		return VM_FAULT_SIGBUS;
 	}
+	if (fault_size != dax_region->align)
+		return VM_FAULT_SIGBUS;
 	phys = pgoff_to_phys(dax_dev, vmf->pgoff, PAGE_SIZE);
 	if (phys == -1) {
-		dev_dbg(dev, "%s: phys_to_pgoff(%#lx) failed\n", __func__,
+		dev_dbg(dev, "%s: pgoff_to_phys(%#lx) failed\n", __func__,
 				vmf->pgoff);
 		return VM_FAULT_SIGBUS;
 	}
 	phys_addr_t phys;
 	pgoff_t pgoff;
 	pfn_t pfn;
+	unsigned int fault_size = PMD_SIZE;
 	if (check_vma(dax_dev, vmf->vma, __func__))
 		return VM_FAULT_SIGBUS;
 		return VM_FAULT_SIGBUS;
 	}
+	if (fault_size < dax_region->align)
+		return VM_FAULT_SIGBUS;
+	else if (fault_size > dax_region->align)
+		return VM_FAULT_FALLBACK;
+	/* if we are outside of the VMA */
+	if (pmd_addr < vmf->vma->vm_start ||
+			(pmd_addr + PMD_SIZE) > vmf->vma->vm_end)
+		return VM_FAULT_SIGBUS;
 	pgoff = linear_page_index(vmf->vma, pmd_addr);
 	phys = pgoff_to_phys(dax_dev, pgoff, PMD_SIZE);
 	if (phys == -1) {
-		dev_dbg(dev, "%s: phys_to_pgoff(%#lx) failed\n", __func__,
+		dev_dbg(dev, "%s: pgoff_to_phys(%#lx) failed\n", __func__,
 				pgoff);
 		return VM_FAULT_SIGBUS;
 	}
 	phys_addr_t phys;
 	pgoff_t pgoff;
 	pfn_t pfn;
+	unsigned int fault_size = PUD_SIZE;
 	if (check_vma(dax_dev, vmf->vma, __func__))
 		return VM_FAULT_SIGBUS;
 		return VM_FAULT_SIGBUS;
 	}
+	if (fault_size < dax_region->align)
+		return VM_FAULT_SIGBUS;
+	else if (fault_size > dax_region->align)
+		return VM_FAULT_FALLBACK;
+	/* if we are outside of the VMA */
+	if (pud_addr < vmf->vma->vm_start ||
+			(pud_addr + PUD_SIZE) > vmf->vma->vm_end)
+		return VM_FAULT_SIGBUS;
 	pgoff = linear_page_index(vmf->vma, pud_addr);
 	phys = pgoff_to_phys(dax_dev, pgoff, PUD_SIZE);
 	if (phys == -1) {
-		dev_dbg(dev, "%s: phys_to_pgoff(%#lx) failed\n", __func__,
+		dev_dbg(dev, "%s: pgoff_to_phys(%#lx) failed\n", __func__,
 				pgoff);
 		return VM_FAULT_SIGBUS;
 	}
 static int dax_dev_huge_fault(struct vm_fault *vmf,
 		enum page_entry_size pe_size)
 {
-	int rc;
+	int rc, id;
 	struct file *filp = vmf->vma->vm_file;
 	struct dax_dev *dax_dev = filp->private_data;
 			? "write" : "read",
 			vmf->vma->vm_start, vmf->vma->vm_end);
-	rcu_read_lock();
+	id = srcu_read_lock(&dax_srcu);
 	switch (pe_size) {
 	case PE_SIZE_PTE:
 		rc = __dax_dev_pte_fault(dax_dev, vmf);
 	default:
 		return VM_FAULT_FALLBACK;
 	}
-	rcu_read_unlock();
+	srcu_read_unlock(&dax_srcu, id);
 	return rc;
 }
 	 * Note, rcu is not protecting the liveness of dax_dev, rcu is
 	 * ensuring that any fault handlers that might have seen
 	 * dax_dev->alive == true, have completed.  Any fault handlers
-	 * that start after synchronize_rcu() has started will abort
+	 * that start after synchronize_srcu() has started will abort
 	 * upon seeing dax_dev->alive == false.
 	 */
 	dax_dev->alive = false;
-	synchronize_rcu();
+	synchronize_srcu(&dax_srcu);
 	unmap_mapping_range(dax_dev->inode->i_mapping, 0, 0, 1);
 }

drivers/extcon/Kconfig+1−1

@@ -44,7 +44,7 @@ config EXTCON_GPIO · 43 unmodified lines
44		44
45	config EXTCON_INTEL_INT3496	45	config EXTCON_INTEL_INT3496
46	tristate "Intel INT3496 ACPI device extcon driver"	46	tristate "Intel INT3496 ACPI device extcon driver"
47	depends on GPIOLIB && ACPI	47	depends on GPIOLIB && ACPI && (X86 \|\| COMPILE_TEST)
48	help	48	help
49	Say Y here to enable extcon support for USB OTG ports controlled by	49	Say Y here to enable extcon support for USB OTG ports controlled by
50	an Intel INT3496 ACPI device.	50	an Intel INT3496 ACPI device.

drivers/extcon/extcon-intel-int3496.c+28−11

 	EXTCON_NONE,
 };
+static const struct acpi_gpio_params id_gpios = { INT3496_GPIO_USB_ID, 0, false };
+static const struct acpi_gpio_params vbus_gpios = { INT3496_GPIO_VBUS_EN, 0, false };
+static const struct acpi_gpio_params mux_gpios = { INT3496_GPIO_USB_MUX, 0, false };
+static const struct acpi_gpio_mapping acpi_int3496_default_gpios[] = {
+	{ "id-gpios", &id_gpios, 1 },
+	{ "vbus-gpios", &vbus_gpios, 1 },
+	{ "mux-gpios", &mux_gpios, 1 },
+	{ },
+};
 static void int3496_do_usb_id(struct work_struct *work)
 {
 	struct int3496_data *data =
 	struct int3496_data *data;
 	int ret;
+	ret = acpi_dev_add_driver_gpios(ACPI_COMPANION(dev),
+					acpi_int3496_default_gpios);
+	if (ret) {
+		dev_err(dev, "can't add GPIO ACPI mapping\n");
+		return ret;
+	}
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 	data->dev = dev;
 	INIT_DELAYED_WORK(&data->work, int3496_do_usb_id);
-	data->gpio_usb_id = devm_gpiod_get_index(dev, "id",
+	data->gpio_usb_id = devm_gpiod_get(dev, "id", GPIOD_IN);
-						INT3496_GPIO_USB_ID,
-						GPIOD_IN);
 	if (IS_ERR(data->gpio_usb_id)) {
 		ret = PTR_ERR(data->gpio_usb_id);
 		dev_err(dev, "can't request USB ID GPIO: %d\n", ret);
 		return ret;
+	} else if (gpiod_get_direction(data->gpio_usb_id) != GPIOF_DIR_IN) {
+		dev_warn(dev, FW_BUG "USB ID GPIO not in input mode, fixing\n");
+		gpiod_direction_input(data->gpio_usb_id);
 	}
 	data->usb_id_irq = gpiod_to_irq(data->gpio_usb_id);
-	if (data->usb_id_irq <= 0) {
+	if (data->usb_id_irq < 0) {
 		dev_err(dev, "can't get USB ID IRQ: %d\n", data->usb_id_irq);
-		return -EINVAL;
+		return data->usb_id_irq;
 	}
-	data->gpio_vbus_en = devm_gpiod_get_index(dev, "vbus en",
+	data->gpio_vbus_en = devm_gpiod_get(dev, "vbus", GPIOD_ASIS);
-						 INT3496_GPIO_VBUS_EN,
-						 GPIOD_ASIS);
 	if (IS_ERR(data->gpio_vbus_en))
 		dev_info(dev, "can't request VBUS EN GPIO\n");
-	data->gpio_usb_mux = devm_gpiod_get_index(dev, "usb mux",
+	data->gpio_usb_mux = devm_gpiod_get(dev, "mux", GPIOD_ASIS);
-						 INT3496_GPIO_USB_MUX,
-						 GPIOD_ASIS);
 	if (IS_ERR(data->gpio_usb_mux))
 		dev_info(dev, "can't request USB MUX GPIO\n");
 	devm_free_irq(&pdev->dev, data->usb_id_irq, data);
 	cancel_delayed_work_sync(&data->work);
+	acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pdev->dev));
 	return 0;
 }

drivers/gpio/gpio-altera-a10sr.c+1−1

@@ -96,7 +96,7 @@ static int altr_a10sr_gpio_probe(struct platform_device *pdev) · 95 unmodified lines
96	gpio->regmap = a10sr->regmap;	96	gpio->regmap = a10sr->regmap;
97		97
98	gpio->gp = altr_a10sr_gc;	98	gpio->gp = altr_a10sr_gc;
99		99	gpio->gp.parent = pdev->dev.parent;
100	gpio->gp.of_node = pdev->dev.of_node;	100	gpio->gp.of_node = pdev->dev.of_node;
101		101
102	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);	102	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);

drivers/gpio/gpio-altera.c+11−15

@@ -90,21 +90,18 @@ static int altera_gpio_irq_set_type(struct irq_data *d, · 89 unmodified lines
90		90
91	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));	91	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
92		92
93	if (type == IRQ_TYPE_NONE)	93	if (type == IRQ_TYPE_NONE) {
		94	irq_set_handler_locked(d, handle_bad_irq);
94	return 0;	95	return 0;
95	if (type == IRQ_TYPE_LEVEL_HIGH &&	96	}
96	altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)	97	if (type == altera_gc->interrupt_trigger) {
97	return 0;	98	if (type == IRQ_TYPE_LEVEL_HIGH)
98	if (type == IRQ_TYPE_EDGE_RISING &&	99	irq_set_handler_locked(d, handle_level_irq);
99	altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)	100	else
100	return 0;	101	irq_set_handler_locked(d, handle_simple_irq);
101	if (type == IRQ_TYPE_EDGE_FALLING &&
102	altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
103	return 0;
104	if (type == IRQ_TYPE_EDGE_BOTH &&
105	altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
106	return 0;	102	return 0;
107		103	}
		104	irq_set_handler_locked(d, handle_bad_irq);
108	return -EINVAL;	105	return -EINVAL;
109	}	106	}
110		107
@@ -230,7 +227,6 @@ static void altera_gpio_irq_edge_handler(struct irq_desc *desc) · 119 unmodified lines
230	chained_irq_exit(chip, desc);	227	chained_irq_exit(chip, desc);
231	}	228	}
232		229
233
234	static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)	230	static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
235	{	231	{
236	struct altera_gpio_chip *altera_gc;	232	struct altera_gpio_chip *altera_gc;
@@ -310,7 +306,7 @@ static int altera_gpio_probe(struct platform_device *pdev) · 73 unmodified lines
310	altera_gc->interrupt_trigger = reg;	306	altera_gc->interrupt_trigger = reg;
311		307
312	ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,	308	ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
313	handle_simple_irq, IRQ_TYPE_NONE);	309	handle_bad_irq, IRQ_TYPE_NONE);
314		310
315	if (ret) {	311	if (ret) {
316	dev_err(&pdev->dev, "could not add irqchip\n");	312	dev_err(&pdev->dev, "could not add irqchip\n");

drivers/gpio/gpio-mcp23s08.c+60−5

@@ -270,8 +270,10 @@ mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) · 269 unmodified lines
270	static irqreturn_t mcp23s08_irq(int irq, void *data)	270	static irqreturn_t mcp23s08_irq(int irq, void *data)
271	{	271	{
272	struct mcp23s08 *mcp = data;	272	struct mcp23s08 *mcp = data;
273	int intcap, intf, i;	273	int intcap, intf, i, gpio, gpio_orig, intcap_mask;
274	unsigned int child_irq;	274	unsigned int child_irq;
		275	bool intf_set, intcap_changed, gpio_bit_changed,
		276	defval_changed, gpio_set;
275		277
276	mutex_lock(&mcp->lock);	278	mutex_lock(&mcp->lock);
277	if (mcp_read(mcp, MCP_INTF, &intf) < 0) {	279	if (mcp_read(mcp, MCP_INTF, &intf) < 0) {
@@ -287,14 +289,67 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) · 9 unmodified lines
287	}	289	}
288		290
289	mcp->cache[MCP_INTCAP] = intcap;	291	mcp->cache[MCP_INTCAP] = intcap;
		292
		293	/* This clears the interrupt(configurable on S18) */
		294	if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) {
		295	mutex_unlock(&mcp->lock);
		296	return IRQ_HANDLED;
		297	}
		298	gpio_orig = mcp->cache[MCP_GPIO];
		299	mcp->cache[MCP_GPIO] = gpio;
290	mutex_unlock(&mcp->lock);	300	mutex_unlock(&mcp->lock);
291		301
		302	if (mcp->cache[MCP_INTF] == 0) {
		303	/* There is no interrupt pending */
		304	return IRQ_HANDLED;
		305	}
		306
		307	dev_dbg(mcp->chip.parent,
		308	"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
		309	intcap, intf, gpio_orig, gpio);
292		310
293	for (i = 0; i < mcp->chip.ngpio; i++) {	311	for (i = 0; i < mcp->chip.ngpio; i++) {
294	if ((BIT(i) & mcp->cache[MCP_INTF]) &&	312	/* We must check all of the inputs on the chip,
295	((BIT(i) & intcap & mcp->irq_rise) \|\|	313	* otherwise we may not notice a change on >=2 pins.
296	(mcp->irq_fall & ~intcap & BIT(i)) \|\|	314	*
297	(BIT(i) & mcp->cache[MCP_INTCON]))) {	315	* On at least the mcp23s17, INTCAP is only updated
		316	* one byte at a time(INTCAPA and INTCAPB are
		317	* not written to at the same time - only on a per-bank
		318	* basis).
		319	*
		320	* INTF only contains the single bit that caused the
		321	* interrupt per-bank. On the mcp23s17, there is
		322	* INTFA and INTFB. If two pins are changed on the A
		323	* side at the same time, INTF will only have one bit
		324	* set. If one pin on the A side and one pin on the B
		325	* side are changed at the same time, INTF will have
		326	* two bits set. Thus, INTF can't be the only check
		327	* to see if the input has changed.
		328	*/
		329
		330	intf_set = BIT(i) & mcp->cache[MCP_INTF];
		331	if (i < 8 && intf_set)
		332	intcap_mask = 0x00FF;
		333	else if (i >= 8 && intf_set)
		334	intcap_mask = 0xFF00;
		335	else
		336	intcap_mask = 0x00;
		337
		338	intcap_changed = (intcap_mask &
		339	(BIT(i) & mcp->cache[MCP_INTCAP])) !=
		340	(intcap_mask & (BIT(i) & gpio_orig));
		341	gpio_set = BIT(i) & mcp->cache[MCP_GPIO];
		342	gpio_bit_changed = (BIT(i) & gpio_orig) !=
		343	(BIT(i) & mcp->cache[MCP_GPIO]);
		344	defval_changed = (BIT(i) & mcp->cache[MCP_INTCON]) &&
		345	((BIT(i) & mcp->cache[MCP_GPIO]) !=
		346	(BIT(i) & mcp->cache[MCP_DEFVAL]));
		347
		348	if (((gpio_bit_changed \|\| intcap_changed) &&
		349	(BIT(i) & mcp->irq_rise) && gpio_set) \|\|
		350	((gpio_bit_changed \|\| intcap_changed) &&
		351	(BIT(i) & mcp->irq_fall) && !gpio_set) \|\|
		352	defval_changed) {
298	child_irq = irq_find_mapping(mcp->chip.irqdomain, i);	353	child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
299	handle_nested_irq(child_irq);	354	handle_nested_irq(child_irq);
300	}	355	}

drivers/gpio/gpio-mockup.c+3−4

 	struct seq_file *sfile;
 	struct gpio_desc *desc;
 	struct gpio_chip *gc;
-	int status, val;
+	int val;
 	char buf;
 	sfile = file->private_data;
 	chip = priv->chip;
 	gc = &chip->gc;
-	status = copy_from_user(&buf, usr_buf, 1);
+	if (copy_from_user(&buf, usr_buf, 1))
-	if (status)
+		return -EFAULT;
-		return status;
 	if (buf == '0')
 		val = 0;

drivers/gpio/gpio-xgene.c+3−10

 	struct gpio_chip	chip;
 	void __iomem		*base;
 	spinlock_t		lock;
-#ifdef CONFIG_PM
 	u32			set_dr_val[XGENE_MAX_GPIO_BANKS];
-#endif
 };
 static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
 	return 0;
 }
-#ifdef CONFIG_PM
+static __maybe_unused int xgene_gpio_suspend(struct device *dev)
-static int xgene_gpio_suspend(struct device *dev)
 {
 	struct xgene_gpio *gpio = dev_get_drvdata(dev);
 	unsigned long bank_offset;
 	return 0;
 }
-static int xgene_gpio_resume(struct device *dev)
+static __maybe_unused int xgene_gpio_resume(struct device *dev)
 {
 	struct xgene_gpio *gpio = dev_get_drvdata(dev);
 	unsigned long bank_offset;
 }
 static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
-#define XGENE_GPIO_PM_OPS	(&xgene_gpio_pm)
-#else
-#define XGENE_GPIO_PM_OPS	NULL
-#endif
 static int xgene_gpio_probe(struct platform_device *pdev)
 {
 		.name = "xgene-gpio",
 		.of_match_table = xgene_gpio_of_match,
 		.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
-		.pm     = XGENE_GPIO_PM_OPS,
+		.pm     = &xgene_gpio_pm,
 	},
 	.probe = xgene_gpio_probe,
 };

drivers/gpu/drm/amd/acp/Makefile+0−2

@@ -3,6 +3,4 @@ · 2 unmodified lines
3	# of AMDSOC/AMDGPU drm driver.	3	# of AMDSOC/AMDGPU drm driver.
4	# It provides the HW control for ACP related functionalities.	4	# It provides the HW control for ACP related functionalities.
5		5
6	subdir-ccflags-y += -I$(AMDACPPATH)/ -I$(AMDACPPATH)/include
7
8	AMD_ACP_FILES := $(AMDACPPATH)/acp_hw.o	6	AMD_ACP_FILES := $(AMDACPPATH)/acp_hw.o

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+2−0

 	for (; i >= 0; i--)
 		drm_free_large(p->chunks[i].kdata);
 	kfree(p->chunks);
+	p->chunks = NULL;
+	p->nchunks = 0;
 put_ctx:
 	amdgpu_ctx_put(p->ctx);
 free_chunk:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+4−4

@@ -475,7 +475,7 @@ static int amdgpu_wb_init(struct amdgpu_device *adev) · 474 unmodified lines
475	int r;	475	int r;
476		476
477	if (adev->wb.wb_obj == NULL) {	477	if (adev->wb.wb_obj == NULL) {
478	r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4,	478	r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t),
479	PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,	479	PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
480	&adev->wb.wb_obj, &adev->wb.gpu_addr,	480	&adev->wb.wb_obj, &adev->wb.gpu_addr,
481	(void **)&adev->wb.wb);	481	(void **)&adev->wb.wb);
@@ -488,7 +488,7 @@ static int amdgpu_wb_init(struct amdgpu_device *adev) · 6 unmodified lines
488	memset(&adev->wb.used, 0, sizeof(adev->wb.used));	488	memset(&adev->wb.used, 0, sizeof(adev->wb.used));
489		489
490	/* clear wb memory */	490	/* clear wb memory */
491	memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);	491	memset((char )adev->wb.wb, 0, AMDGPU_MAX_WB sizeof(uint32_t));
492	}	492	}
493		493
494	return 0;	494	return 0;
@@ -2590,7 +2590,7 @@ static ssize_t amdgpu_debugfs_regs_read(struct file f, char __user buf, · 2095 unmodified lines
2590	use_bank = 0;	2590	use_bank = 0;
2591	}	2591	}
2592		2592
2593	*pos &= 0x3FFFF;	2593	*pos &= (1UL << 22) - 1;
2594		2594
2595	if (use_bank) {	2595	if (use_bank) {
2596	if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) \|\|	2596	if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) \|\|
@@ -2666,7 +2666,7 @@ static ssize_t amdgpu_debugfs_regs_write(struct file f, const char __user buf, · 69 unmodified lines
2666	use_bank = 0;	2666	use_bank = 0;
2667	}	2667	}
2668		2668
2669	*pos &= 0x3FFFF;	2669	*pos &= (1UL << 22) - 1;
2670		2670
2671	if (use_bank) {	2671	if (use_bank) {
2672	if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) \|\|	2672	if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) \|\|

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+1−0

@@ -421,6 +421,7 @@ static const struct pci_device_id pciidlist[] = { · 420 unmodified lines
421	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},	421	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
422	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},	422	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
423	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},	423	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
		424	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
424	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},	425	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
425		426
426	{0, 0, 0}	427	{0, 0, 0}

drivers/gpu/drm/amd/amdgpu/si_dpm.c+10−0

@@ -3464,6 +3464,16 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, · 3463 unmodified lines
3464	(adev->pdev->device == 0x6667)) {	3464	(adev->pdev->device == 0x6667)) {
3465	max_sclk = 75000;	3465	max_sclk = 75000;
3466	}	3466	}
		3467	} else if (adev->asic_type == CHIP_OLAND) {
		3468	if ((adev->pdev->revision == 0xC7) \|\|
		3469	(adev->pdev->revision == 0x80) \|\|
		3470	(adev->pdev->revision == 0x81) \|\|
		3471	(adev->pdev->revision == 0x83) \|\|
		3472	(adev->pdev->revision == 0x87) \|\|
		3473	(adev->pdev->device == 0x6604) \|\|
		3474	(adev->pdev->device == 0x6605)) {
		3475	max_sclk = 75000;
		3476	}
3467	}	3477	}
3468		3478
3469	if (rps->vce_active) {	3479	if (rps->vce_active) {

drivers/gpu/drm/amd/amdgpu/vi.c+1−1

@@ -1051,7 +1051,7 @@ static int vi_common_early_init(void *handle) · 1050 unmodified lines
1051	/* rev0 hardware requires workarounds to support PG */	1051	/* rev0 hardware requires workarounds to support PG */
1052	adev->pg_flags = 0;	1052	adev->pg_flags = 0;
1053	if (adev->rev_id != 0x00) {	1053	if (adev->rev_id != 0x00) {
1054	adev->pg_flags \|= AMD_PG_SUPPORT_GFX_PG \|	1054	adev->pg_flags \|=
1055	AMD_PG_SUPPORT_GFX_SMG \|	1055	AMD_PG_SUPPORT_GFX_SMG \|
1056	AMD_PG_SUPPORT_GFX_PIPELINE \|	1056	AMD_PG_SUPPORT_GFX_PIPELINE \|
1057	AMD_PG_SUPPORT_CP \|	1057	AMD_PG_SUPPORT_CP \|

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c+1−1

@@ -178,7 +178,7 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) · 177 unmodified lines
178	if (bgate) {	178	if (bgate) {
179	cgs_set_powergating_state(hwmgr->device,	179	cgs_set_powergating_state(hwmgr->device,
180	AMD_IP_BLOCK_TYPE_VCE,	180	AMD_IP_BLOCK_TYPE_VCE,
181	AMD_PG_STATE_UNGATE);	181	AMD_PG_STATE_GATE);
182	cgs_set_clockgating_state(hwmgr->device,	182	cgs_set_clockgating_state(hwmgr->device,
183	AMD_IP_BLOCK_TYPE_VCE,	183	AMD_IP_BLOCK_TYPE_VCE,
184	AMD_CG_STATE_GATE);	184	AMD_CG_STATE_GATE);

drivers/gpu/drm/arm/malidp_crtc.c+1−2

@@ -63,8 +63,7 @@ static void malidp_crtc_enable(struct drm_crtc *crtc) · 62 unmodified lines
63		63
64	clk_prepare_enable(hwdev->pxlclk);	64	clk_prepare_enable(hwdev->pxlclk);
65		65
66	/* mclk needs to be set to the same or higher rate than pxlclk */	66	/* We rely on firmware to set mclk to a sensible level. */
67	clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000);
68	clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);	67	clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
69		68
70	hwdev->modeset(hwdev, &vm);	69	hwdev->modeset(hwdev, &vm);

drivers/gpu/drm/arm/malidp_hw.c+1−1

@@ -83,7 +83,7 @@ static const struct malidp_layer malidp550_layers[] = { · 82 unmodified lines
83	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },	83	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
84	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },	84	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },
85	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },	85	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
86	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, 0 },	86	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE },
87	};	87	};
88		88
89	#define MALIDP_DE_DEFAULT_PREFETCH_START 5	89	#define MALIDP_DE_DEFAULT_PREFETCH_START 5

drivers/gpu/drm/arm/malidp_planes.c+16−2

 #define   LAYER_V_VAL(x)		(((x) & 0x1fff) << 16)
 #define MALIDP_LAYER_COMP_SIZE		0x010
 #define MALIDP_LAYER_OFFSET		0x014
+#define MALIDP550_LS_ENABLE		0x01c
+#define MALIDP550_LS_R1_IN_SIZE		0x020
 /*
  * This 4-entry look-up-table is used to determine the full 8-bit alpha value
 			LAYER_V_VAL(plane->state->crtc_y),
 			mp->layer->base + MALIDP_LAYER_OFFSET);
+	if (mp->layer->id == DE_SMART)
+		malidp_hw_write(mp->hwdev,
+				LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
+				mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
 	/* first clear the rotation bits */
 	val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
 	val &= ~LAYER_ROT_MASK;
 		plane->hwdev = malidp->dev;
 		plane->layer = &map->layers[i];
-		/* Skip the features which the SMART layer doesn't have */
+		if (id == DE_SMART) {
-		if (id == DE_SMART)
+			/*
+			 * Enable the first rectangle in the SMART layer to be
+			 * able to use it as a drm plane.
+			 */
+			malidp_hw_write(malidp->dev, 1,
+					plane->layer->base + MALIDP550_LS_ENABLE);
+			/* Skip the features which the SMART layer doesn't have. */
 			continue;
+		}
 		drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags);
 		malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,

drivers/gpu/drm/arm/malidp_regs.h+1−0

@@ -84,6 +84,7 @@ · 83 unmodified lines
84	/* Stride register offsets relative to Lx_BASE */	84	/* Stride register offsets relative to Lx_BASE */
85	#define MALIDP_DE_LG_STRIDE 0x18	85	#define MALIDP_DE_LG_STRIDE 0x18
86	#define MALIDP_DE_LV_STRIDE0 0x18	86	#define MALIDP_DE_LV_STRIDE0 0x18
		87	#define MALIDP550_DE_LS_R1_STRIDE 0x28
87		88
88	/* macros to set values into registers */	89	/* macros to set values into registers */
89	#define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0)	90	#define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0)

drivers/gpu/drm/drm_fb_helper.c+3−3

@@ -1260,9 +1260,9 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var, · 1259 unmodified lines
1260	* to KMS, hence fail if different settings are requested.	1260	* to KMS, hence fail if different settings are requested.
1261	*/	1261	*/
1262	if (var->bits_per_pixel != fb->format->cpp[0] * 8 \|\|	1262	if (var->bits_per_pixel != fb->format->cpp[0] * 8 \|\|
1263	var->xres != fb->width \|\| var->yres != fb->height \|\|	1263	var->xres > fb->width \|\| var->yres > fb->height \|\|
1264	var->xres_virtual != fb->width \|\| var->yres_virtual != fb->height) {	1264	var->xres_virtual > fb->width \|\| var->yres_virtual > fb->height) {
1265	DRM_DEBUG("fb userspace requested width/height/bpp different than current fb "	1265	DRM_DEBUG("fb requested width/height/bpp can't fit in current fb "
1266	"request %dx%d-%d (virtual %dx%d) > %dx%d-%d\n",	1266	"request %dx%d-%d (virtual %dx%d) > %dx%d-%d\n",
1267	var->xres, var->yres, var->bits_per_pixel,	1267	var->xres, var->yres, var->bits_per_pixel,
1268	var->xres_virtual, var->yres_virtual,	1268	var->xres_virtual, var->yres_virtual,

drivers/gpu/drm/exynos/exynos5433_drm_decon.c+82−5

 	unsigned long			flags;
 	unsigned long			out_type;
 	int				first_win;
+	spinlock_t			vblank_lock;
+	u32				frame_id;
 };
 static const uint32_t decon_formats[] = {
 		if (ctx->out_type & IFTYPE_I80)
 			val |= VIDINTCON0_FRAMEDONE;
 		else
-			val |= VIDINTCON0_INTFRMEN;
+			val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 		writel(val, ctx->addr + DECON_VIDINTCON0);
 	}
 		writel(0, ctx->addr + DECON_VIDINTCON0);
 }
+/* return number of starts/ends of frame transmissions since reset */
+static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
+{
+	u32 frm, pfrm, status, cnt = 2;
+	/* To get consistent result repeat read until frame id is stable.
+	 * Usually the loop will be executed once, in rare cases when the loop
+	 * is executed at frame change time 2nd pass will be needed.
+	 */
+	frm = readl(ctx->addr + DECON_CRFMID);
+	do {
+		status = readl(ctx->addr + DECON_VIDCON1);
+		pfrm = frm;
+		frm = readl(ctx->addr + DECON_CRFMID);
+	} while (frm != pfrm && --cnt);
+	/* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
+	 * of RGB, it should be taken into account.
+	 */
+	if (!frm)
+		return 0;
+	switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
+	case VIDCON1_VSTATUS_VS:
+		if (!(ctx->out_type & IFTYPE_I80))
+			--frm;
+		break;
+	case VIDCON1_VSTATUS_BP:
+		--frm;
+		break;
+	case VIDCON1_I80_ACTIVE:
+	case VIDCON1_VSTATUS_AC:
+		if (end)
+			--frm;
+		break;
+	default:
+		break;
+	}
+	return frm;
+}
 static void decon_setup_trigger(struct decon_context *ctx)
 {
 	if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 		return;
 	if (!(ctx->out_type & I80_HW_TRG)) {
-		writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
+		writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
-		       | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
+		       TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 		       ctx->addr + DECON_TRIGCON);
 		return;
 	}
 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 {
 	struct decon_context *ctx = crtc->ctx;
+	unsigned long flags;
 	int i;
 	if (test_bit(BIT_SUSPENDED, &ctx->flags))
 		return;
+	spin_lock_irqsave(&ctx->vblank_lock, flags);
 	for (i = ctx->first_win; i < WINDOWS_NR; i++)
 		decon_shadow_protect_win(ctx, i, false);
 	if (ctx->out_type & IFTYPE_I80)
 		set_bit(BIT_WIN_UPDATED, &ctx->flags);
+	ctx->frame_id = decon_get_frame_count(ctx, true);
+	exynos_crtc_handle_event(crtc);
+	spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 }
 static void decon_swreset(struct decon_context *ctx)
 {
 	unsigned int tries;
+	unsigned long flags;
 	writel(0, ctx->addr + DECON_VIDCON0);
 	for (tries = 2000; tries; --tries) {
 	WARN(tries == 0, "failed to software reset DECON\n");
+	spin_lock_irqsave(&ctx->vblank_lock, flags);
+	ctx->frame_id = 0;
+	spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 	if (!(ctx->out_type & IFTYPE_HDMI))
 		return;
 	.unbind = decon_unbind,
 };
+static void decon_handle_vblank(struct decon_context *ctx)
+{
+	u32 frm;
+	spin_lock(&ctx->vblank_lock);
+	frm = decon_get_frame_count(ctx, true);
+	if (frm != ctx->frame_id) {
+		/* handle only if incremented, take care of wrap-around */
+		if ((s32)(frm - ctx->frame_id) > 0)
+			drm_crtc_handle_vblank(&ctx->crtc->base);
+		ctx->frame_id = frm;
+	}
+	spin_unlock(&ctx->vblank_lock);
+}
 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 {
 	struct decon_context *ctx = dev_id;
 			    (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 				return IRQ_HANDLED;
 		}
-		drm_crtc_handle_vblank(&ctx->crtc->base);
+		decon_handle_vblank(ctx);
 	}
 out:
 	__set_bit(BIT_SUSPENDED, &ctx->flags);
 	ctx->dev = dev;
 	ctx->out_type = (unsigned long)of_device_get_match_data(dev);
+	spin_lock_init(&ctx->vblank_lock);
 	if (ctx->out_type & IFTYPE_HDMI) {
 		ctx->first_win = 1;
 		ctx->out_type |= IFTYPE_I80;
 	}
-	if (ctx->out_type | I80_HW_TRG) {
+	if (ctx->out_type & I80_HW_TRG) {
 		ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 							"samsung,disp-sysreg");
 		if (IS_ERR(ctx->sysreg)) {

drivers/gpu/drm/exynos/exynos7_drm_decon.c+1−0

@@ -526,6 +526,7 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc) · 525 unmodified lines
526		526
527	for (i = 0; i < WINDOWS_NR; i++)	527	for (i = 0; i < WINDOWS_NR; i++)
528	decon_shadow_protect_win(ctx, i, false);	528	decon_shadow_protect_win(ctx, i, false);
		529	exynos_crtc_handle_event(crtc);
529	}	530	}
530		531
531	static void decon_init(struct decon_context *ctx)	532	static void decon_init(struct decon_context *ctx)

drivers/gpu/drm/exynos/exynos_drm_crtc.c+16−13

 				     struct drm_crtc_state *old_crtc_state)
 {
 	struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
-	struct drm_pending_vblank_event *event;
-	unsigned long flags;
 	if (exynos_crtc->ops->atomic_flush)
 		exynos_crtc->ops->atomic_flush(exynos_crtc);
+}
+static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = {
+	.enable		= exynos_drm_crtc_enable,
+	.disable	= exynos_drm_crtc_disable,
+	.mode_set_nofb	= exynos_drm_crtc_mode_set_nofb,
+	.atomic_check	= exynos_crtc_atomic_check,
+	.atomic_begin	= exynos_crtc_atomic_begin,
+	.atomic_flush	= exynos_crtc_atomic_flush,
+};
+void exynos_crtc_handle_event(struct exynos_drm_crtc *exynos_crtc)
+{
+	struct drm_crtc *crtc = &exynos_crtc->base;
+	struct drm_pending_vblank_event *event = crtc->state->event;
+	unsigned long flags;
-	event = crtc->state->event;
 	if (event) {
 		crtc->state->event = NULL;
 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
 		if (drm_crtc_vblank_get(crtc) == 0)
 			drm_crtc_arm_vblank_event(crtc, event);
 }
-static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = {
-	.enable		= exynos_drm_crtc_enable,
-	.disable	= exynos_drm_crtc_disable,
-	.mode_set_nofb	= exynos_drm_crtc_mode_set_nofb,
-	.atomic_check	= exynos_crtc_atomic_check,
-	.atomic_begin	= exynos_crtc_atomic_begin,
-	.atomic_flush	= exynos_crtc_atomic_flush,
-};
 static void exynos_drm_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);

drivers/gpu/drm/exynos/exynos_drm_crtc.h+2−0

@@ -40,4 +40,6 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev, · 39 unmodified lines
40	*/	40	*/
41	void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);	41	void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
42		42
		43	void exynos_crtc_handle_event(struct exynos_drm_crtc *exynos_crtc);
		44
43	#endif	45	#endif

drivers/gpu/drm/exynos/exynos_drm_dsi.c+7−17

 #define DSIM_SYNC_INFORM		(1 << 27)
 #define DSIM_EOT_DISABLE		(1 << 28)
 #define DSIM_MFLUSH_VS			(1 << 29)
-/* This flag is valid only for exynos3250/3472/4415/5260/5430 */
+/* This flag is valid only for exynos3250/3472/5260/5430 */
 #define DSIM_CLKLANE_STOP		(1 << 30)
 /* DSIM_ESCMODE */
 	.reg_values = reg_values,
 };
-static const struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
-	.reg_ofs = exynos_reg_ofs,
-	.plltmr_reg = 0x58,
-	.has_clklane_stop = 1,
-	.num_clks = 2,
-	.max_freq = 1000,
-	.wait_for_reset = 1,
-	.num_bits_resol = 11,
-	.reg_values = reg_values,
-};
 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
 	.reg_ofs = exynos_reg_ofs,
 	.plltmr_reg = 0x58,
 	  .data = &exynos3_dsi_driver_data },
 	{ .compatible = "samsung,exynos4210-mipi-dsi",
 	  .data = &exynos4_dsi_driver_data },
-	{ .compatible = "samsung,exynos4415-mipi-dsi",
-	  .data = &exynos4415_dsi_driver_data },
 	{ .compatible = "samsung,exynos5410-mipi-dsi",
 	  .data = &exynos5_dsi_driver_data },
 	{ .compatible = "samsung,exynos5422-mipi-dsi",
 	bool first = !xfer->tx_done;
 	u32 reg;
-	dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
+	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
 		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
 	if (length > DSI_TX_FIFO_SIZE)
 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
 	dev_dbg(dsi->dev,
-		"> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
+		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
 		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
 		xfer->rx_done);
 	int te_gpio_irq;
 	dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
+	if (dsi->te_gpio == -ENOENT)
+		return 0;
 	if (!gpio_is_valid(dsi->te_gpio)) {
-		dev_err(dsi->dev, "no te-gpios specified\n");
 		ret = dsi->te_gpio;
+		dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
 		goto out;
 	}

drivers/gpu/drm/exynos/exynos_drm_fimc.c+1−1

@@ -1695,7 +1695,7 @@ static int fimc_probe(struct platform_device *pdev) · 1694 unmodified lines
1695	goto err_put_clk;	1695	goto err_put_clk;
1696	}	1696	}
1697		1697
1698	DRM_DEBUG_KMS("id[%d]ippdrv[%p]\n", ctx->id, ippdrv);	1698	DRM_DEBUG_KMS("id[%d]ippdrv[%pK]\n", ctx->id, ippdrv);
1699		1699
1700	spin_lock_init(&ctx->lock);	1700	spin_lock_init(&ctx->lock);
1701	platform_set_drvdata(pdev, ctx);	1701	platform_set_drvdata(pdev, ctx);

drivers/gpu/drm/exynos/exynos_drm_fimd.c+5−17

 #define TRIGCON				0x1A4
 #define TRGMODE_ENABLE			(1 << 0)
 #define SWTRGCMD_ENABLE			(1 << 1)
-/* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */
+/* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
 #define HWTRGEN_ENABLE			(1 << 3)
 #define HWTRGMASK_ENABLE		(1 << 4)
-/* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */
+/* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
 #define HWTRIGEN_PER_ENABLE		(1 << 31)
 /* display mode change control register except exynos4 */
 	.has_vtsel = 1,
 };
-static struct fimd_driver_data exynos4415_fimd_driver_data = {
-	.timing_base = 0x20000,
-	.lcdblk_offset = 0x210,
-	.lcdblk_vt_shift = 10,
-	.lcdblk_bypass_shift = 1,
-	.trg_type = I80_HW_TRG,
-	.has_shadowcon = 1,
-	.has_vidoutcon = 1,
-	.has_vtsel = 1,
-	.has_trigger_per_te = 1,
-};
 static struct fimd_driver_data exynos5_fimd_driver_data = {
 	.timing_base = 0x20000,
 	.lcdblk_offset = 0x214,
 	  .data = &exynos3_fimd_driver_data },
 	{ .compatible = "samsung,exynos4210-fimd",
 	  .data = &exynos4_fimd_driver_data },
-	{ .compatible = "samsung,exynos4415-fimd",
-	  .data = &exynos4415_fimd_driver_data },
 	{ .compatible = "samsung,exynos5250-fimd",
 	  .data = &exynos5_fimd_driver_data },
 	{ .compatible = "samsung,exynos5420-fimd",
 			val |= VIDINTCON0_INT_FRAME;
 			val &= ~VIDINTCON0_FRAMESEL0_MASK;
-			val |= VIDINTCON0_FRAMESEL0_VSYNC;
+			val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 			val &= ~VIDINTCON0_FRAMESEL1_MASK;
 			val |= VIDINTCON0_FRAMESEL1_NONE;
 		}
 	for (i = 0; i < WINDOWS_NR; i++)
 		fimd_shadow_protect_win(ctx, i, false);
+	exynos_crtc_handle_event(crtc);
 }
 static void fimd_update_plane(struct exynos_drm_crtc *crtc,

drivers/gpu/drm/exynos/exynos_drm_gem.c+1−1

@@ -218,7 +218,7 @@ static struct exynos_drm_gem exynos_drm_gem_init(struct drm_device dev, · 217 unmodified lines
218	return ERR_PTR(ret);	218	return ERR_PTR(ret);
219	}	219	}
220		220
221	DRM_DEBUG_KMS("created file object = %p\n", obj->filp);	221	DRM_DEBUG_KMS("created file object = %pK\n", obj->filp);
222		222
223	return exynos_gem;	223	return exynos_gem;
224	}	224	}

drivers/gpu/drm/exynos/exynos_drm_gsc.c+1−1

@@ -1723,7 +1723,7 @@ static int gsc_probe(struct platform_device *pdev) · 1722 unmodified lines
1723	return ret;	1723	return ret;
1724	}	1724	}
1725		1725
1726	DRM_DEBUG_KMS("id[%d]ippdrv[%p]\n", ctx->id, ippdrv);	1726	DRM_DEBUG_KMS("id[%d]ippdrv[%pK]\n", ctx->id, ippdrv);
1727		1727
1728	mutex_init(&ctx->lock);	1728	mutex_init(&ctx->lock);
1729	platform_set_drvdata(pdev, ctx);	1729	platform_set_drvdata(pdev, ctx);

drivers/gpu/drm/exynos/exynos_drm_ipp.c+11−11

@@ -208,7 +208,7 @@ static struct exynos_drm_ippdrv *ipp_find_drv_by_handle(u32 prop_id) · 207 unmodified lines
208	* e.g PAUSE state, queue buf, command control.	208	* e.g PAUSE state, queue buf, command control.
209	*/	209	*/
210	list_for_each_entry(ippdrv, &exynos_drm_ippdrv_list, drv_list) {	210	list_for_each_entry(ippdrv, &exynos_drm_ippdrv_list, drv_list) {
211	DRM_DEBUG_KMS("count[%d]ippdrv[%p]\n", count++, ippdrv);	211	DRM_DEBUG_KMS("count[%d]ippdrv[%pK]\n", count++, ippdrv);
212		212
213	mutex_lock(&ippdrv->cmd_lock);	213	mutex_lock(&ippdrv->cmd_lock);
214	list_for_each_entry(c_node, &ippdrv->cmd_list, list) {	214	list_for_each_entry(c_node, &ippdrv->cmd_list, list) {
@@ -388,7 +388,7 @@ int exynos_drm_ipp_set_property(struct drm_device drm_dev, void data, · 173 unmodified lines
388	}	388	}
389	property->prop_id = ret;	389	property->prop_id = ret;
390		390
391	DRM_DEBUG_KMS("created prop_id[%d]cmd[%d]ippdrv[%p]\n",	391	DRM_DEBUG_KMS("created prop_id[%d]cmd[%d]ippdrv[%pK]\n",
392	property->prop_id, property->cmd, ippdrv);	392	property->prop_id, property->cmd, ippdrv);
393		393
394	/* stored property information and ippdrv in private data */	394	/* stored property information and ippdrv in private data */
@@ -518,7 +518,7 @@ static int ipp_put_mem_node(struct drm_device *drm_dev, · 123 unmodified lines
518	{	518	{
519	int i;	519	int i;
520		520
521	DRM_DEBUG_KMS("node[%p]\n", m_node);	521	DRM_DEBUG_KMS("node[%pK]\n", m_node);
522		522
523	if (!m_node) {	523	if (!m_node) {
524	DRM_ERROR("invalid dequeue node.\n");	524	DRM_ERROR("invalid dequeue node.\n");
@@ -562,7 +562,7 @@ static struct drm_exynos_ipp_mem_node · 37 unmodified lines
562	m_node->buf_id = qbuf->buf_id;	562	m_node->buf_id = qbuf->buf_id;
563	INIT_LIST_HEAD(&m_node->list);	563	INIT_LIST_HEAD(&m_node->list);
564		564
565	DRM_DEBUG_KMS("m_node[%p]ops_id[%d]\n", m_node, qbuf->ops_id);	565	DRM_DEBUG_KMS("m_node[%pK]ops_id[%d]\n", m_node, qbuf->ops_id);
566	DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]\n", qbuf->prop_id, m_node->buf_id);	566	DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]\n", qbuf->prop_id, m_node->buf_id);
567		567
568	for_each_ipp_planar(i) {	568	for_each_ipp_planar(i) {
@@ -659,7 +659,7 @@ static void ipp_put_event(struct drm_exynos_ipp_cmd_node *c_node, · 90 unmodified lines
659		659
660	mutex_lock(&c_node->event_lock);	660	mutex_lock(&c_node->event_lock);
661	list_for_each_entry_safe(e, te, &c_node->event_list, base.link) {	661	list_for_each_entry_safe(e, te, &c_node->event_list, base.link) {
662	DRM_DEBUG_KMS("count[%d]e[%p]\n", count++, e);	662	DRM_DEBUG_KMS("count[%d]e[%pK]\n", count++, e);
663		663
664	/*	664	/*
665	* qbuf == NULL condition means all event deletion.	665	* qbuf == NULL condition means all event deletion.
@@ -750,7 +750,7 @@ static struct drm_exynos_ipp_mem_node · 84 unmodified lines
750		750
751	/* find memory node from memory list */	751	/* find memory node from memory list */
752	list_for_each_entry(m_node, head, list) {	752	list_for_each_entry(m_node, head, list) {
753	DRM_DEBUG_KMS("count[%d]m_node[%p]\n", count++, m_node);	753	DRM_DEBUG_KMS("count[%d]m_node[%pK]\n", count++, m_node);
754		754
755	/* compare buffer id */	755	/* compare buffer id */
756	if (m_node->buf_id == qbuf->buf_id)	756	if (m_node->buf_id == qbuf->buf_id)
@@ -767,7 +767,7 @@ static int ipp_set_mem_node(struct exynos_drm_ippdrv *ippdrv, · 10 unmodified lines
767	struct exynos_drm_ipp_ops *ops = NULL;	767	struct exynos_drm_ipp_ops *ops = NULL;
768	int ret = 0;	768	int ret = 0;
769		769
770	DRM_DEBUG_KMS("node[%p]\n", m_node);	770	DRM_DEBUG_KMS("node[%pK]\n", m_node);
771		771
772	if (!m_node) {	772	if (!m_node) {
773	DRM_ERROR("invalid queue node.\n");	773	DRM_ERROR("invalid queue node.\n");
@@ -1232,7 +1232,7 @@ static int ipp_start_property(struct exynos_drm_ippdrv *ippdrv, · 458 unmodified lines
1232	m_node = list_first_entry(head,	1232	m_node = list_first_entry(head,
1233	struct drm_exynos_ipp_mem_node, list);	1233	struct drm_exynos_ipp_mem_node, list);
1234		1234
1235	DRM_DEBUG_KMS("m_node[%p]\n", m_node);	1235	DRM_DEBUG_KMS("m_node[%pK]\n", m_node);
1236		1236
1237	ret = ipp_set_mem_node(ippdrv, c_node, m_node);	1237	ret = ipp_set_mem_node(ippdrv, c_node, m_node);
1238	if (ret) {	1238	if (ret) {
@@ -1601,7 +1601,7 @@ static int ipp_subdrv_probe(struct drm_device drm_dev, struct device dev) · 362 unmodified lines
1601	}	1601	}
1602	ippdrv->prop_list.ipp_id = ret;	1602	ippdrv->prop_list.ipp_id = ret;
1603		1603
1604	DRM_DEBUG_KMS("count[%d]ippdrv[%p]ipp_id[%d]\n",	1604	DRM_DEBUG_KMS("count[%d]ippdrv[%pK]ipp_id[%d]\n",
1605	count++, ippdrv, ret);	1605	count++, ippdrv, ret);
1606		1606
1607	/* store parent device for node */	1607	/* store parent device for node */
@@ -1659,7 +1659,7 @@ static int ipp_subdrv_open(struct drm_device drm_dev, struct device dev, · 51 unmodified lines
1659		1659
1660	file_priv->ipp_dev = dev;	1660	file_priv->ipp_dev = dev;
1661		1661
1662	DRM_DEBUG_KMS("done priv[%p]\n", dev);	1662	DRM_DEBUG_KMS("done priv[%pK]\n", dev);
1663		1663
1664	return 0;	1664	return 0;
1665	}	1665	}
@@ -1676,7 +1676,7 @@ static void ipp_subdrv_close(struct drm_device drm_dev, struct device dev, · 10 unmodified lines
1676	mutex_lock(&ippdrv->cmd_lock);	1676	mutex_lock(&ippdrv->cmd_lock);
1677	list_for_each_entry_safe(c_node, tc_node,	1677	list_for_each_entry_safe(c_node, tc_node,
1678	&ippdrv->cmd_list, list) {	1678	&ippdrv->cmd_list, list) {
1679	DRM_DEBUG_KMS("count[%d]ippdrv[%p]\n",	1679	DRM_DEBUG_KMS("count[%d]ippdrv[%pK]\n",
1680	count++, ippdrv);	1680	count++, ippdrv);
1681		1681
1682	if (c_node->filp == file) {	1682	if (c_node->filp == file) {

drivers/gpu/drm/exynos/exynos_drm_rotator.c+1−1

@@ -748,7 +748,7 @@ static int rotator_probe(struct platform_device *pdev) · 747 unmodified lines
748	goto err_ippdrv_register;	748	goto err_ippdrv_register;
749	}	749	}
750		750
751	DRM_DEBUG_KMS("ippdrv[%p]\n", ippdrv);	751	DRM_DEBUG_KMS("ippdrv[%pK]\n", ippdrv);
752		752
753	platform_set_drvdata(pdev, rot);	753	platform_set_drvdata(pdev, rot);
754		754

drivers/gpu/drm/exynos/exynos_drm_vidi.c+1−0

@@ -170,6 +170,7 @@ static const struct exynos_drm_crtc_ops vidi_crtc_ops = { · 169 unmodified lines
170	.enable_vblank = vidi_enable_vblank,	170	.enable_vblank = vidi_enable_vblank,
171	.disable_vblank = vidi_disable_vblank,	171	.disable_vblank = vidi_disable_vblank,
172	.update_plane = vidi_update_plane,	172	.update_plane = vidi_update_plane,
		173	.atomic_flush = exynos_crtc_handle_event,
173	};	174	};
174		175
175	static void vidi_fake_vblank_timer(unsigned long arg)	176	static void vidi_fake_vblank_timer(unsigned long arg)

drivers/gpu/drm/exynos/exynos_mixer.c+1−0

@@ -1012,6 +1012,7 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) · 1011 unmodified lines
1012	return;	1012	return;
1013		1013
1014	mixer_vsync_set_update(mixer_ctx, true);	1014	mixer_vsync_set_update(mixer_ctx, true);
		1015	exynos_crtc_handle_event(crtc);
1015	}	1016	}
1016		1017
1017	static void mixer_enable(struct exynos_drm_crtc *crtc)	1018	static void mixer_enable(struct exynos_drm_crtc *crtc)

drivers/gpu/drm/i915/gvt/aperture_gm.c+4−4

@@ -242,7 +242,7 @@ static int alloc_resource(struct intel_vgpu *vgpu, · 241 unmodified lines
242	const char *item;	242	const char *item;
243		243
244	if (!param->low_gm_sz \|\| !param->high_gm_sz \|\| !param->fence_sz) {	244	if (!param->low_gm_sz \|\| !param->high_gm_sz \|\| !param->fence_sz) {
245	gvt_err("Invalid vGPU creation params\n");	245	gvt_vgpu_err("Invalid vGPU creation params\n");
246	return -EINVAL;	246	return -EINVAL;
247	}	247	}
248		248
@@ -285,9 +285,9 @@ static int alloc_resource(struct intel_vgpu *vgpu, · 36 unmodified lines
285	return 0;	285	return 0;
286		286
287	no_enough_resource:	287	no_enough_resource:
288	gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);	288	gvt_vgpu_err("fail to allocate resource %s\n", item);
289	gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",	289	gvt_vgpu_err("request %luMB avail %luMB max %luMB taken %luMB\n",
290	vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),	290	BYTES_TO_MB(request), BYTES_TO_MB(avail),
291	BYTES_TO_MB(max), BYTES_TO_MB(taken));	291	BYTES_TO_MB(max), BYTES_TO_MB(taken));
292	return -ENOSPC;	292	return -ENOSPC;
293	}	293	}

drivers/gpu/drm/i915/gvt/cmd_parser.c+72−37

@@ -817,6 +817,25 @@ static bool is_shadowed_mmio(unsigned int offset) · 816 unmodified lines
817	return ret;	817	return ret;
818	}	818	}
819		819
		820	static inline bool is_force_nonpriv_mmio(unsigned int offset)
		821	{
		822	return (offset >= 0x24d0 && offset < 0x2500);
		823	}
		824
		825	static int force_nonpriv_reg_handler(struct parser_exec_state *s,
		826	unsigned int offset, unsigned int index)
		827	{
		828	struct intel_gvt *gvt = s->vgpu->gvt;
		829	unsigned int data = cmd_val(s, index + 1);
		830
		831	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
		832	gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
		833	offset, data);
		834	return -EINVAL;
		835	}
		836	return 0;
		837	}
		838
820	static int cmd_reg_handler(struct parser_exec_state *s,	839	static int cmd_reg_handler(struct parser_exec_state *s,
821	unsigned int offset, unsigned int index, char *cmd)	840	unsigned int offset, unsigned int index, char *cmd)
822	{	841	{
@@ -824,23 +843,26 @@ static int cmd_reg_handler(struct parser_exec_state *s, · 1 unmodified line
824	struct intel_gvt *gvt = vgpu->gvt;	843	struct intel_gvt *gvt = vgpu->gvt;
825		844
826	if (offset + 4 > gvt->device_info.mmio_size) {	845	if (offset + 4 > gvt->device_info.mmio_size) {
827	gvt_err("%s access to (%x) outside of MMIO range\n",	846	gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
828	cmd, offset);	847	cmd, offset);
829	return -EINVAL;	848	return -EINVAL;
830	}	849	}
831		850
832	if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {	851	if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
833	gvt_err("vgpu%d: %s access to non-render register (%x)\n",	852	gvt_vgpu_err("%s access to non-render register (%x)\n",
834	s->vgpu->id, cmd, offset);	853	cmd, offset);
835	return 0;	854	return 0;
836	}	855	}
837		856
838	if (is_shadowed_mmio(offset)) {	857	if (is_shadowed_mmio(offset)) {
839	gvt_err("vgpu%d: found access of shadowed MMIO %x\n",	858	gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
840	s->vgpu->id, offset);
841	return 0;	859	return 0;
842	}	860	}
843		861
		862	if (is_force_nonpriv_mmio(offset) &&
		863	force_nonpriv_reg_handler(s, offset, index))
		864	return -EINVAL;
		865
844	if (offset == i915_mmio_reg_offset(DERRMR) \|\|	866	if (offset == i915_mmio_reg_offset(DERRMR) \|\|
845	offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {	867	offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
846	/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */	868	/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
@@ -1008,7 +1030,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) · 161 unmodified lines
1008	ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");	1030	ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1009	else if (post_sync == 1) {	1031	else if (post_sync == 1) {
1010	/* check ggtt*/	1032	/* check ggtt*/
1011	if ((cmd_val(s, 2) & (1 << 2))) {	1033	if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1012	gma = cmd_val(s, 2) & GENMASK(31, 3);	1034	gma = cmd_val(s, 2) & GENMASK(31, 3);
1013	if (gmadr_bytes == 8)	1035	if (gmadr_bytes == 8)
1014	gma \|= (cmd_gma_hi(s, 3)) << 32;	1036	gma \|= (cmd_gma_hi(s, 3)) << 32;
@@ -1129,6 +1151,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, · 114 unmodified lines
1129	struct mi_display_flip_command_info *info)	1151	struct mi_display_flip_command_info *info)
1130	{	1152	{
1131	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;	1153	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
		1154	struct intel_vgpu *vgpu = s->vgpu;
1132	u32 dword0 = cmd_val(s, 0);	1155	u32 dword0 = cmd_val(s, 0);
1133	u32 dword1 = cmd_val(s, 1);	1156	u32 dword1 = cmd_val(s, 1);
1134	u32 dword2 = cmd_val(s, 2);	1157	u32 dword2 = cmd_val(s, 2);
@@ -1167,7 +1190,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, · 32 unmodified lines
1167	break;	1190	break;
1168		1191
1169	default:	1192	default:
1170	gvt_err("unknown plane code %d\n", plane);	1193	gvt_vgpu_err("unknown plane code %d\n", plane);
1171	return -EINVAL;	1194	return -EINVAL;
1172	}	1195	}
1173		1196
@@ -1274,25 +1297,26 @@ static int update_plane_mmio_from_mi_display_flip( · 100 unmodified lines
1274	static int cmd_handler_mi_display_flip(struct parser_exec_state *s)	1297	static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1275	{	1298	{
1276	struct mi_display_flip_command_info info;	1299	struct mi_display_flip_command_info info;
		1300	struct intel_vgpu *vgpu = s->vgpu;
1277	int ret;	1301	int ret;
1278	int i;	1302	int i;
1279	int len = cmd_length(s);	1303	int len = cmd_length(s);
1280		1304
1281	ret = decode_mi_display_flip(s, &info);	1305	ret = decode_mi_display_flip(s, &info);
1282	if (ret) {	1306	if (ret) {
1283	gvt_err("fail to decode MI display flip command\n");	1307	gvt_vgpu_err("fail to decode MI display flip command\n");
1284	return ret;	1308	return ret;
1285	}	1309	}
1286		1310
1287	ret = check_mi_display_flip(s, &info);	1311	ret = check_mi_display_flip(s, &info);
1288	if (ret) {	1312	if (ret) {
1289	gvt_err("invalid MI display flip command\n");	1313	gvt_vgpu_err("invalid MI display flip command\n");
1290	return ret;	1314	return ret;
1291	}	1315	}
1292		1316
1293	ret = update_plane_mmio_from_mi_display_flip(s, &info);	1317	ret = update_plane_mmio_from_mi_display_flip(s, &info);
1294	if (ret) {	1318	if (ret) {
1295	gvt_err("fail to update plane mmio\n");	1319	gvt_vgpu_err("fail to update plane mmio\n");
1296	return ret;	1320	return ret;
1297	}	1321	}
1298		1322
@@ -1350,7 +1374,8 @@ static inline int cmd_address_audit(struct parser_exec_state *s, · 51 unmodified lines
1350	int ret;	1374	int ret;
1351		1375
1352	if (op_size > max_surface_size) {	1376	if (op_size > max_surface_size) {
1353	gvt_err("command address audit fail name %s\n", s->info->name);	1377	gvt_vgpu_err("command address audit fail name %s\n",
		1378	s->info->name);
1354	return -EINVAL;	1379	return -EINVAL;
1355	}	1380	}
1356		1381
@@ -1367,7 +1392,7 @@ static inline int cmd_address_audit(struct parser_exec_state *s, · 10 unmodified lines
1367	}	1392	}
1368	return 0;	1393	return 0;
1369	err:	1394	err:
1370	gvt_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",	1395	gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1371	s->info->name, guest_gma, op_size);	1396	s->info->name, guest_gma, op_size);
1372		1397
1373	pr_err("cmd dump: ");	1398	pr_err("cmd dump: ");
@@ -1412,8 +1437,10 @@ static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) · 38 unmodified lines
1412		1437
1413	static inline int unexpected_cmd(struct parser_exec_state *s)	1438	static inline int unexpected_cmd(struct parser_exec_state *s)
1414	{	1439	{
1415	gvt_err("vgpu%d: Unexpected %s in command buffer!\n",	1440	struct intel_vgpu *vgpu = s->vgpu;
1416	s->vgpu->id, s->info->name);	1441
		1442	gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
		1443
1417	return -EINVAL;	1444	return -EINVAL;
1418	}	1445	}
1419		1446
@@ -1516,7 +1543,7 @@ static int copy_gma_to_hva(struct intel_vgpu vgpu, struct intel_vgpu_mm mm, · 96 unmodified lines
1516	while (gma != end_gma) {	1543	while (gma != end_gma) {
1517	gpa = intel_vgpu_gma_to_gpa(mm, gma);	1544	gpa = intel_vgpu_gma_to_gpa(mm, gma);
1518	if (gpa == INTEL_GVT_INVALID_ADDR) {	1545	if (gpa == INTEL_GVT_INVALID_ADDR) {
1519	gvt_err("invalid gma address: %lx\n", gma);	1546	gvt_vgpu_err("invalid gma address: %lx\n", gma);
1520	return -EFAULT;	1547	return -EFAULT;
1521	}	1548	}
1522		1549
@@ -1557,6 +1584,7 @@ static uint32_t find_bb_size(struct parser_exec_state *s) · 34 unmodified lines
1557	uint32_t bb_size = 0;	1584	uint32_t bb_size = 0;
1558	uint32_t cmd_len = 0;	1585	uint32_t cmd_len = 0;
1559	bool met_bb_end = false;	1586	bool met_bb_end = false;
		1587	struct intel_vgpu *vgpu = s->vgpu;
1560	u32 cmd;	1588	u32 cmd;
1561		1589
1562	/* get the start gm address of the batch buffer */	1590	/* get the start gm address of the batch buffer */
@@ -1565,7 +1593,7 @@ static uint32_t find_bb_size(struct parser_exec_state *s) · 2 unmodified lines
1565		1593
1566	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);	1594	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1567	if (info == NULL) {	1595	if (info == NULL) {
1568	gvt_err("unknown cmd 0x%x, opcode=0x%x\n",	1596	gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1569	cmd, get_opcode(cmd, s->ring_id));	1597	cmd, get_opcode(cmd, s->ring_id));
1570	return -EINVAL;	1598	return -EINVAL;
1571	}	1599	}
@@ -1574,7 +1602,7 @@ static uint32_t find_bb_size(struct parser_exec_state *s) · 2 unmodified lines
1574	gma, gma + 4, &cmd);	1602	gma, gma + 4, &cmd);
1575	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);	1603	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1576	if (info == NULL) {	1604	if (info == NULL) {
1577	gvt_err("unknown cmd 0x%x, opcode=0x%x\n",	1605	gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1578	cmd, get_opcode(cmd, s->ring_id));	1606	cmd, get_opcode(cmd, s->ring_id));
1579	return -EINVAL;	1607	return -EINVAL;
1580	}	1608	}
@@ -1599,6 +1627,7 @@ static uint32_t find_bb_size(struct parser_exec_state *s) · 18 unmodified lines
1599	static int perform_bb_shadow(struct parser_exec_state *s)	1627	static int perform_bb_shadow(struct parser_exec_state *s)
1600	{	1628	{
1601	struct intel_shadow_bb_entry *entry_obj;	1629	struct intel_shadow_bb_entry *entry_obj;
		1630	struct intel_vgpu *vgpu = s->vgpu;
1602	unsigned long gma = 0;	1631	unsigned long gma = 0;
1603	uint32_t bb_size;	1632	uint32_t bb_size;
1604	void *dst = NULL;	1633	void *dst = NULL;
@@ -1633,7 +1662,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) · 28 unmodified lines
1633		1662
1634	ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);	1663	ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
1635	if (ret) {	1664	if (ret) {
1636	gvt_err("failed to set shadow batch to CPU\n");	1665	gvt_vgpu_err("failed to set shadow batch to CPU\n");
1637	goto unmap_src;	1666	goto unmap_src;
1638	}	1667	}
1639		1668
@@ -1645,7 +1674,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) · 5 unmodified lines
1645	gma, gma + bb_size,	1674	gma, gma + bb_size,
1646	dst);	1675	dst);
1647	if (ret) {	1676	if (ret) {
1648	gvt_err("fail to copy guest ring buffer\n");	1677	gvt_vgpu_err("fail to copy guest ring buffer\n");
1649	goto unmap_src;	1678	goto unmap_src;
1650	}	1679	}
1651		1680
@@ -1676,15 +1705,16 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) · 24 unmodified lines
1676	{	1705	{
1677	bool second_level;	1706	bool second_level;
1678	int ret = 0;	1707	int ret = 0;
		1708	struct intel_vgpu *vgpu = s->vgpu;
1679		1709
1680	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {	1710	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1681	gvt_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");	1711	gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1682	return -EINVAL;	1712	return -EINVAL;
1683	}	1713	}
1684		1714
1685	second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;	1715	second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1686	if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {	1716	if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1687	gvt_err("Jumping to 2nd level BB from RB is not allowed\n");	1717	gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1688	return -EINVAL;	1718	return -EINVAL;
1689	}	1719	}
1690		1720
@@ -1702,7 +1732,7 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) · 11 unmodified lines
1702	if (batch_buffer_needs_scan(s)) {	1732	if (batch_buffer_needs_scan(s)) {
1703	ret = perform_bb_shadow(s);	1733	ret = perform_bb_shadow(s);
1704	if (ret < 0)	1734	if (ret < 0)
1705	gvt_err("invalid shadow batch buffer\n");	1735	gvt_vgpu_err("invalid shadow batch buffer\n");
1706	} else {	1736	} else {
1707	/* emulate a batch buffer end to do return right */	1737	/* emulate a batch buffer end to do return right */
1708	ret = cmd_handler_mi_batch_buffer_end(s);	1738	ret = cmd_handler_mi_batch_buffer_end(s);
@@ -2429,6 +2459,7 @@ static int cmd_parser_exec(struct parser_exec_state *s) · 720 unmodified lines
2429	int ret = 0;	2459	int ret = 0;
2430	cycles_t t0, t1, t2;	2460	cycles_t t0, t1, t2;
2431	struct parser_exec_state s_before_advance_custom;	2461	struct parser_exec_state s_before_advance_custom;
		2462	struct intel_vgpu *vgpu = s->vgpu;
2432		2463
2433	t0 = get_cycles();	2464	t0 = get_cycles();
2434		2465
@@ -2436,7 +2467,7 @@ static int cmd_parser_exec(struct parser_exec_state *s) · 1 unmodified line
2436		2467
2437	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);	2468	info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2438	if (info == NULL) {	2469	if (info == NULL) {
2439	gvt_err("unknown cmd 0x%x, opcode=0x%x\n",	2470	gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
2440	cmd, get_opcode(cmd, s->ring_id));	2471	cmd, get_opcode(cmd, s->ring_id));
2441	return -EINVAL;	2472	return -EINVAL;
2442	}	2473	}
@@ -2452,7 +2483,7 @@ static int cmd_parser_exec(struct parser_exec_state *s) · 9 unmodified lines
2452	if (info->handler) {	2483	if (info->handler) {
2453	ret = info->handler(s);	2484	ret = info->handler(s);
2454	if (ret < 0) {	2485	if (ret < 0) {
2455	gvt_err("%s handler error\n", info->name);	2486	gvt_vgpu_err("%s handler error\n", info->name);
2456	return ret;	2487	return ret;
2457	}	2488	}
2458	}	2489	}
@@ -2463,7 +2494,7 @@ static int cmd_parser_exec(struct parser_exec_state *s) · 4 unmodified lines
2463	if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {	2494	if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2464	ret = cmd_advance_default(s);	2495	ret = cmd_advance_default(s);
2465	if (ret) {	2496	if (ret) {
2466	gvt_err("%s IP advance error\n", info->name);	2497	gvt_vgpu_err("%s IP advance error\n", info->name);
2467	return ret;	2498	return ret;
2468	}	2499	}
2469	}	2500	}
@@ -2486,6 +2517,7 @@ static int command_scan(struct parser_exec_state *s, · 16 unmodified lines
2486		2517
2487	unsigned long gma_head, gma_tail, gma_bottom;	2518	unsigned long gma_head, gma_tail, gma_bottom;
2488	int ret = 0;	2519	int ret = 0;
		2520	struct intel_vgpu *vgpu = s->vgpu;
2489		2521
2490	gma_head = rb_start + rb_head;	2522	gma_head = rb_start + rb_head;
2491	gma_tail = rb_start + rb_tail;	2523	gma_tail = rb_start + rb_tail;
@@ -2497,7 +2529,7 @@ static int command_scan(struct parser_exec_state *s, · 5 unmodified lines
2497	if (s->buf_type == RING_BUFFER_INSTRUCTION) {	2529	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2498	if (!(s->ip_gma >= rb_start) \|\|	2530	if (!(s->ip_gma >= rb_start) \|\|
2499	!(s->ip_gma < gma_bottom)) {	2531	!(s->ip_gma < gma_bottom)) {
2500	gvt_err("ip_gma %lx out of ring scope."	2532	gvt_vgpu_err("ip_gma %lx out of ring scope."
2501	"(base:0x%lx, bottom: 0x%lx)\n",	2533	"(base:0x%lx, bottom: 0x%lx)\n",
2502	s->ip_gma, rb_start,	2534	s->ip_gma, rb_start,
2503	gma_bottom);	2535	gma_bottom);
@@ -2505,7 +2537,7 @@ static int command_scan(struct parser_exec_state *s, · 1 unmodified line
2505	return -EINVAL;	2537	return -EINVAL;
2506	}	2538	}
2507	if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {	2539	if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2508	gvt_err("ip_gma %lx out of range."	2540	gvt_vgpu_err("ip_gma %lx out of range."
2509	"base 0x%lx head 0x%lx tail 0x%lx\n",	2541	"base 0x%lx head 0x%lx tail 0x%lx\n",
2510	s->ip_gma, rb_start,	2542	s->ip_gma, rb_start,
2511	rb_head, rb_tail);	2543	rb_head, rb_tail);
@@ -2515,7 +2547,7 @@ static int command_scan(struct parser_exec_state *s, · 3 unmodified lines
2515	}	2547	}
2516	ret = cmd_parser_exec(s);	2548	ret = cmd_parser_exec(s);
2517	if (ret) {	2549	if (ret) {
2518	gvt_err("cmd parser error\n");	2550	gvt_vgpu_err("cmd parser error\n");
2519	parser_exec_state_dump(s);	2551	parser_exec_state_dump(s);
2520	break;	2552	break;
2521	}	2553	}
@@ -2639,7 +2671,7 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) · 117 unmodified lines
2639	gma_head, gma_top,	2671	gma_head, gma_top,
2640	workload->shadow_ring_buffer_va);	2672	workload->shadow_ring_buffer_va);
2641	if (ret) {	2673	if (ret) {
2642	gvt_err("fail to copy guest ring buffer\n");	2674	gvt_vgpu_err("fail to copy guest ring buffer\n");
2643	return ret;	2675	return ret;
2644	}	2676	}
2645	copy_len = gma_top - gma_head;	2677	copy_len = gma_top - gma_head;
@@ -2651,7 +2683,7 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) · 5 unmodified lines
2651	gma_head, gma_tail,	2683	gma_head, gma_tail,
2652	workload->shadow_ring_buffer_va + copy_len);	2684	workload->shadow_ring_buffer_va + copy_len);
2653	if (ret) {	2685	if (ret) {
2654	gvt_err("fail to copy guest ring buffer\n");	2686	gvt_vgpu_err("fail to copy guest ring buffer\n");
2655	return ret;	2687	return ret;
2656	}	2688	}
2657	ring->tail += workload->rb_len;	2689	ring->tail += workload->rb_len;
@@ -2662,16 +2694,17 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) · 4 unmodified lines
2662	int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)	2694	int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
2663	{	2695	{
2664	int ret;	2696	int ret;
		2697	struct intel_vgpu *vgpu = workload->vgpu;
2665		2698
2666	ret = shadow_workload_ring_buffer(workload);	2699	ret = shadow_workload_ring_buffer(workload);
2667	if (ret) {	2700	if (ret) {
2668	gvt_err("fail to shadow workload ring_buffer\n");	2701	gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2669	return ret;	2702	return ret;
2670	}	2703	}
2671		2704
2672	ret = scan_workload(workload);	2705	ret = scan_workload(workload);
2673	if (ret) {	2706	if (ret) {
2674	gvt_err("scan workload error\n");	2707	gvt_vgpu_err("scan workload error\n");
2675	return ret;	2708	return ret;
2676	}	2709	}
2677	return 0;	2710	return 0;
@@ -2681,6 +2714,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 3 unmodified lines
2681	{	2714	{
2682	int ctx_size = wa_ctx->indirect_ctx.size;	2715	int ctx_size = wa_ctx->indirect_ctx.size;
2683	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;	2716	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
		2717	struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;
2684	struct drm_i915_gem_object *obj;	2718	struct drm_i915_gem_object *obj;
2685	int ret = 0;	2719	int ret = 0;
2686	void *map;	2720	void *map;
@@ -2694,14 +2728,14 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 7 unmodified lines
2694	/* get the va of the shadow batch buffer */	2728	/* get the va of the shadow batch buffer */
2695	map = i915_gem_object_pin_map(obj, I915_MAP_WB);	2729	map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2696	if (IS_ERR(map)) {	2730	if (IS_ERR(map)) {
2697	gvt_err("failed to vmap shadow indirect ctx\n");	2731	gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2698	ret = PTR_ERR(map);	2732	ret = PTR_ERR(map);
2699	goto put_obj;	2733	goto put_obj;
2700	}	2734	}
2701		2735
2702	ret = i915_gem_object_set_to_cpu_domain(obj, false);	2736	ret = i915_gem_object_set_to_cpu_domain(obj, false);
2703	if (ret) {	2737	if (ret) {
2704	gvt_err("failed to set shadow indirect ctx to CPU\n");	2738	gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2705	goto unmap_src;	2739	goto unmap_src;
2706	}	2740	}
2707		2741
@@ -2710,7 +2744,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 2 unmodified lines
2710	guest_gma, guest_gma + ctx_size,	2744	guest_gma, guest_gma + ctx_size,
2711	map);	2745	map);
2712	if (ret) {	2746	if (ret) {
2713	gvt_err("fail to copy guest indirect ctx\n");	2747	gvt_vgpu_err("fail to copy guest indirect ctx\n");
2714	goto unmap_src;	2748	goto unmap_src;
2715	}	2749	}
2716		2750
@@ -2744,13 +2778,14 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 27 unmodified lines
2744	int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)	2778	int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2745	{	2779	{
2746	int ret;	2780	int ret;
		2781	struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;
2747		2782
2748	if (wa_ctx->indirect_ctx.size == 0)	2783	if (wa_ctx->indirect_ctx.size == 0)
2749	return 0;	2784	return 0;
2750		2785
2751	ret = shadow_indirect_ctx(wa_ctx);	2786	ret = shadow_indirect_ctx(wa_ctx);
2752	if (ret) {	2787	if (ret) {
2753	gvt_err("fail to shadow indirect ctx\n");	2788	gvt_vgpu_err("fail to shadow indirect ctx\n");
2754	return ret;	2789	return ret;
2755	}	2790	}
2756		2791
@@ -2758,7 +2793,7 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 1 unmodified line
2758		2793
2759	ret = scan_wa_ctx(wa_ctx);	2794	ret = scan_wa_ctx(wa_ctx);
2760	if (ret) {	2795	if (ret) {
2761	gvt_err("scan wa ctx error\n");	2796	gvt_vgpu_err("scan wa ctx error\n");
2762	return ret;	2797	return ret;
2763	}	2798	}
2764		2799

drivers/gpu/drm/i915/gvt/debug.h+8−0

@@ -27,6 +27,14 @@ · 26 unmodified lines
27	#define gvt_err(fmt, args...) \	27	#define gvt_err(fmt, args...) \
28	DRM_ERROR("gvt: "fmt, ##args)	28	DRM_ERROR("gvt: "fmt, ##args)
29		29
		30	#define gvt_vgpu_err(fmt, args...) \
		31	do { \
		32	if (IS_ERR_OR_NULL(vgpu)) \
		33	DRM_DEBUG_DRIVER("gvt: "fmt, ##args); \
		34	else \
		35	DRM_DEBUG_DRIVER("gvt: vgpu %d: "fmt, vgpu->id, ##args);\
		36	} while (0)
		37
30	#define gvt_dbg_core(fmt, args...) \	38	#define gvt_dbg_core(fmt, args...) \
31	DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)	39	DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
32		40

drivers/gpu/drm/i915/gvt/edid.c+6−7

 	unsigned char chr = 0;
 	if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
-		gvt_err("Driver tries to read EDID without proper sequence!\n");
+		gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
 		return 0;
 	}
 	if (edid->current_edid_read >= EDID_SIZE) {
-		gvt_err("edid_get_byte() exceeds the size of EDID!\n");
+		gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
 		return 0;
 	}
 	if (!edid->edid_available) {
-		gvt_err("Reading EDID but EDID is not available!\n");
+		gvt_vgpu_err("Reading EDID but EDID is not available!\n");
 		return 0;
 	}
 		chr = edid_data->edid_block[edid->current_edid_read];
 		edid->current_edid_read++;
 	} else {
-		gvt_err("No EDID available during the reading?\n");
+		gvt_vgpu_err("No EDID available during the reading?\n");
 	}
 	return chr;
 }
 			vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
 			break;
 		default:
-			gvt_err("Unknown/reserved GMBUS cycle detected!\n");
+			gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
 			break;
 		}
 		/*
 		 */
 	} else {
 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
-		gvt_err("vgpu%d: warning: gmbus3 read with nothing returned\n",
+		gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
-				vgpu->id);
 	}
 	return 0;
 }

drivers/gpu/drm/i915/gvt/execlist.c+13−16

 		struct intel_vgpu_execlist *execlist,
 		struct execlist_ctx_descriptor_format *ctx)
 {
+	struct intel_vgpu *vgpu = execlist->vgpu;
 	struct intel_vgpu_execlist_slot *running = execlist->running_slot;
 	struct intel_vgpu_execlist_slot *pending = execlist->pending_slot;
 	struct execlist_ctx_descriptor_format *ctx0 = &running->ctx[0];
 	gvt_dbg_el("schedule out context id %x\n", ctx->context_id);
 	if (WARN_ON(!same_context(ctx, execlist->running_context))) {
-		gvt_err("schedule out context is not running context,"
+		gvt_vgpu_err("schedule out context is not running context,"
 				"ctx id %x running ctx id %x\n",
 				ctx->context_id,
 				execlist->running_context->context_id);
 	status.udw = vgpu_vreg(vgpu, status_reg + 4);
 	if (status.execlist_queue_full) {
-		gvt_err("virtual execlist slots are full\n");
+		gvt_vgpu_err("virtual execlist slots are full\n");
 		return NULL;
 	}
 	struct execlist_ctx_descriptor_format *ctx0, *ctx1;
 	struct execlist_context_status_format status;
+	struct intel_vgpu *vgpu = execlist->vgpu;
 	gvt_dbg_el("emulate schedule-in\n");
 	if (!slot) {
-		gvt_err("no available execlist slot\n");
+		gvt_vgpu_err("no available execlist slot\n");
 		return -EINVAL;
 	}
 		vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
 		if (IS_ERR(vma)) {
-			gvt_err("Cannot pin\n");
 			return;
 		}
 	vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 				       0, CACHELINE_BYTES, 0);
 	if (IS_ERR(vma)) {
-		gvt_err("Cannot pin indirect ctx obj\n");
 		return;
 	}
 {
 	struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
 	struct intel_vgpu_mm *mm;
+	struct intel_vgpu *vgpu = workload->vgpu;
 	int page_table_level;
 	u32 pdp[8];
 	} else if (desc->addressing_mode == 3) { /* legacy 64 bit */
 		page_table_level = 4;
 	} else {
-		gvt_err("Advanced Context mode(SVM) is not supported!\n");
+		gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
 		return -EINVAL;
 	}
 		mm = intel_vgpu_create_mm(workload->vgpu, INTEL_GVT_MM_PPGTT,
 				pdp, page_table_level, 0);
 		if (IS_ERR(mm)) {
-			gvt_err("fail to create mm object.\n");
+			gvt_vgpu_err("fail to create mm object.\n");
 			return PTR_ERR(mm);
 		}
 	}
 	ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 			(u32)((desc->lrca + 1) << GTT_PAGE_SHIFT));
 	if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
-		gvt_err("invalid guest context LRCA: %x\n", desc->lrca);
+		gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
 		return -EINVAL;
 	}
 			continue;
 		if (!desc[i]->privilege_access) {
-			gvt_err("vgpu%d: unexpected GGTT elsp submission\n",
+			gvt_vgpu_err("unexpected GGTT elsp submission\n");
-					vgpu->id);
 			return -EINVAL;
 		}
 	}
 	if (!valid_desc_bitmap) {
-		gvt_err("vgpu%d: no valid desc in a elsp submission\n",
+		gvt_vgpu_err("no valid desc in a elsp submission\n");
-				vgpu->id);
 		return -EINVAL;
 	}
 	if (!test_bit(0, (void *)&valid_desc_bitmap) &&
 			test_bit(1, (void *)&valid_desc_bitmap)) {
-		gvt_err("vgpu%d: weird elsp submission, desc 0 is not valid\n",
+		gvt_vgpu_err("weird elsp submission, desc 0 is not valid\n");
-				vgpu->id);
 		return -EINVAL;
 	}
 		ret = submit_context(vgpu, ring_id, &valid_desc[i],
 				emulate_schedule_in);
 		if (ret) {
-			gvt_err("vgpu%d: fail to schedule workload\n",
+			gvt_vgpu_err("fail to schedule workload\n");
-					vgpu->id);
 			return ret;
 		}
 		emulate_schedule_in = false;

drivers/gpu/drm/i915/gvt/gtt.c+36−38

 {
 	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
 			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
-		gvt_err("vgpu%d: invalid range gmadr 0x%llx size 0x%x\n",
+		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
-				vgpu->id, addr, size);
+				addr, size);
 		return false;
 	}
 	return true;
 	mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
 	if (mfn == INTEL_GVT_INVALID_ADDR) {
-		gvt_err("fail to translate gfn: 0x%lx\n", gfn);
+		gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
 		return -ENXIO;
 	}
 	daddr = dma_map_page(kdev, p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 	if (dma_mapping_error(kdev, daddr)) {
-		gvt_err("fail to map dma addr\n");
+		gvt_vgpu_err("fail to map dma addr\n");
 		return -EINVAL;
 	}
 		if (reclaim_one_mm(vgpu->gvt))
 			goto retry;
-		gvt_err("fail to allocate ppgtt shadow page\n");
+		gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
 		return ERR_PTR(-ENOMEM);
 	}
 	 */
 	ret = init_shadow_page(vgpu, &spt->shadow_page, type);
 	if (ret) {
-		gvt_err("fail to initialize shadow page for spt\n");
+		gvt_vgpu_err("fail to initialize shadow page for spt\n");
 		goto err;
 	}
 	ret = intel_vgpu_init_guest_page(vgpu, &spt->guest_page,
 			gfn, ppgtt_write_protection_handler, NULL);
 	if (ret) {
-		gvt_err("fail to initialize guest page for spt\n");
+		gvt_vgpu_err("fail to initialize guest page for spt\n");
 		goto err;
 	}
 	if (p)
 		return shadow_page_to_ppgtt_spt(p);
-	gvt_err("vgpu%d: fail to find ppgtt shadow page: 0x%lx\n",
+	gvt_vgpu_err("fail to find ppgtt shadow page: 0x%lx\n", mfn);
-			vgpu->id, mfn);
 	return NULL;
 }
 	}
 	s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
 	if (!s) {
-		gvt_err("vgpu%d: fail to find shadow page: mfn: 0x%lx\n",
+		gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
-				vgpu->id, ops->get_pfn(e));
+				ops->get_pfn(e));
 		return -ENXIO;
 	}
 	return ppgtt_invalidate_shadow_page(s);
 static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
 {
+	struct intel_vgpu *vgpu = spt->vgpu;
 	struct intel_gvt_gtt_entry e;
 	unsigned long index;
 	int ret;
 	for_each_present_shadow_entry(spt, &e, index) {
 		if (!gtt_type_is_pt(get_next_pt_type(e.type))) {
-			gvt_err("GVT doesn't support pse bit for now\n");
+			gvt_vgpu_err("GVT doesn't support pse bit for now\n");
 			return -EINVAL;
 		}
 		ret = ppgtt_invalidate_shadow_page_by_shadow_entry(
 	ppgtt_free_shadow_page(spt);
 	return 0;
 fail:
-	gvt_err("vgpu%d: fail: shadow page %p shadow entry 0x%llx type %d\n",
+	gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
-			spt->vgpu->id, spt, e.val64, e.type);
+			spt, e.val64, e.type);
 	return ret;
 }
 	}
 	return s;
 fail:
-	gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
-			vgpu->id, s, we->val64, we->type);
+			s, we->val64, we->type);
 	return ERR_PTR(ret);
 }
 	for_each_present_guest_entry(spt, &ge, i) {
 		if (!gtt_type_is_pt(get_next_pt_type(ge.type))) {
-			gvt_err("GVT doesn't support pse bit now\n");
+			gvt_vgpu_err("GVT doesn't support pse bit now\n");
 			ret = -EINVAL;
 			goto fail;
 		}
 	}
 	return 0;
 fail:
-	gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
-			vgpu->id, spt, ge.val64, ge.type);
+			spt, ge.val64, ge.type);
 	return ret;
 }
 		struct intel_vgpu_ppgtt_spt *s =
 			ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e));
 		if (!s) {
-			gvt_err("fail to find guest page\n");
+			gvt_vgpu_err("fail to find guest page\n");
 			ret = -ENXIO;
 			goto fail;
 		}
 	ppgtt_set_shadow_entry(spt, &e, index);
 	return 0;
 fail:
-	gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
-			vgpu->id, spt, e.val64, e.type);
+			spt, e.val64, e.type);
 	return ret;
 }
 	}
 	return 0;
 fail:
-	gvt_err("vgpu%d: fail: spt %p guest entry 0x%llx type %d\n", vgpu->id,
+	gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
-			spt, we->val64, we->type);
+		spt, we->val64, we->type);
 	return ret;
 }
 	}
 	return 0;
 fail:
-	gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d.\n",
+	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
-			vgpu->id, spt, we->val64, we->type);
+			spt, we->val64, we->type);
 	return ret;
 }
 		spt = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge);
 		if (IS_ERR(spt)) {
-			gvt_err("fail to populate guest root pointer\n");
+			gvt_vgpu_err("fail to populate guest root pointer\n");
 			ret = PTR_ERR(spt);
 			goto fail;
 		}
 	ret = gtt->mm_alloc_page_table(mm);
 	if (ret) {
-		gvt_err("fail to allocate page table for mm\n");
+		gvt_vgpu_err("fail to allocate page table for mm\n");
 		goto fail;
 	}
 	}
 	return mm;
 fail:
-	gvt_err("fail to create mm\n");
+	gvt_vgpu_err("fail to create mm\n");
 	if (mm)
 		intel_gvt_mm_unreference(mm);
 	return ERR_PTR(ret);
 			mm->page_table_level, gma, gpa);
 	return gpa;
 err:
-	gvt_err("invalid mm type: %d gma %lx\n", mm->type, gma);
+	gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
 	return INTEL_GVT_INVALID_ADDR;
 }
 	if (ops->test_present(&e)) {
 		ret = gtt_entry_p2m(vgpu, &e, &m);
 		if (ret) {
-			gvt_err("vgpu%d: fail to translate guest gtt entry\n",
+			gvt_vgpu_err("fail to translate guest gtt entry\n");
-					vgpu->id);
 			return ret;
 		}
 	} else {
 	scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
 	if (!scratch_pt) {
-		gvt_err("fail to allocate scratch page\n");
+		gvt_vgpu_err("fail to allocate scratch page\n");
 		return -ENOMEM;
 	}
 	daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
 			4096, PCI_DMA_BIDIRECTIONAL);
 	if (dma_mapping_error(dev, daddr)) {
-		gvt_err("fail to dmamap scratch_pt\n");
+		gvt_vgpu_err("fail to dmamap scratch_pt\n");
 		__free_page(virt_to_page(scratch_pt));
 		return -ENOMEM;
 	}
 	ggtt_mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_GGTT,
 			NULL, 1, 0);
 	if (IS_ERR(ggtt_mm)) {
-		gvt_err("fail to create mm for ggtt.\n");
+		gvt_vgpu_err("fail to create mm for ggtt.\n");
 		return PTR_ERR(ggtt_mm);
 	}
 	for (i = 0; i < preallocated_oos_pages; i++) {
 		oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
 		if (!oos_page) {
-			gvt_err("fail to pre-allocate oos page\n");
 			ret = -ENOMEM;
 			goto fail;
 		}
 		mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_PPGTT,
 				pdp, page_table_level, 0);
 		if (IS_ERR(mm)) {
-			gvt_err("fail to create mm\n");
+			gvt_vgpu_err("fail to create mm\n");
 			return PTR_ERR(mm);
 		}
 	}
 	mm = intel_vgpu_find_ppgtt_mm(vgpu, page_table_level, pdp);
 	if (!mm) {
-		gvt_err("fail to find ppgtt instance.\n");
+		gvt_vgpu_err("fail to find ppgtt instance.\n");
 		return -EINVAL;
 	}
 	intel_gvt_mm_unreference(mm);

drivers/gpu/drm/i915/gvt/gvt.h+1−1

 	atomic_t running_workload_num;
 	DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
 	struct i915_gem_context *shadow_ctx;
-	struct notifier_block shadow_ctx_notifier_block;
 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
 	struct {
 	struct intel_gvt_gtt gtt;
 	struct intel_gvt_opregion opregion;
 	struct intel_gvt_workload_scheduler scheduler;
+	struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
 	DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
 	struct intel_vgpu_type *types;
 	unsigned int num_types;

drivers/gpu/drm/i915/gvt/handlers.c+30−15

 					GVT_FAILSAFE_UNSUPPORTED_GUEST);
 		if (!vgpu->mmio.disable_warn_untrack) {
-			gvt_err("vgpu%d: found oob fence register access\n",
+			gvt_vgpu_err("found oob fence register access\n");
-					vgpu->id);
+			gvt_vgpu_err("total fence %d, access fence %d\n",
-			gvt_err("vgpu%d: total fence %d, access fence %d\n",
+					vgpu_fence_sz(vgpu), fence_num);
-					vgpu->id, vgpu_fence_sz(vgpu),
-					fence_num);
 		}
 		memset(p_data, 0, bytes);
 		return -EINVAL;
 			break;
 		default:
 			/*should not hit here*/
-			gvt_err("invalid forcewake offset 0x%x\n", offset);
+			gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
 			return -EINVAL;
 		}
 	} else {
 		fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
 		fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
 	} else {
-		gvt_err("Invalid train pattern %d\n", train_pattern);
+		gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
 		return -EINVAL;
 	}
 	else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
 		index = FDI_RX_IMR_TO_PIPE(offset);
 	else {
-		gvt_err("Unsupport registers %x\n", offset);
+		gvt_vgpu_err("Unsupport registers %x\n", offset);
 		return -EINVAL;
 	}
 	u32 data;
 	if (!dpy_is_valid_port(port_index)) {
-		gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id);
+		gvt_vgpu_err("Unsupported DP port access!\n");
 		return 0;
 	}
 	if (i == num) {
 		if (num == SBI_REG_MAX) {
-			gvt_err("vgpu%d: SBI caching meets maximum limits\n",
+			gvt_vgpu_err("SBI caching meets maximum limits\n");
-					vgpu->id);
 			return;
 		}
 		display->sbi.number++;
 		break;
 	}
 	if (invalid_read)
-		gvt_err("invalid pvinfo read: [%x:%x] = %x\n",
+		gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
 				offset, bytes, *(u32 *)p_data);
 	vgpu->pv_notified = true;
 	return 0;
 	case 1:	/* Remove this in guest driver. */
 		break;
 	default:
-		gvt_err("Invalid PV notification %d\n", notification);
+		gvt_vgpu_err("Invalid PV notification %d\n", notification);
 	}
 	return ret;
 }
 		enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
 		break;
 	default:
-		gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
+		gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
 				offset, bytes, data);
 		break;
 	}
 	if (execlist->elsp_dwords.index == 3) {
 		ret = intel_vgpu_submit_execlist(vgpu, ring_id);
 		if(ret)
-			gvt_err("fail submit workload on ring %d\n", ring_id);
+			gvt_vgpu_err("fail submit workload on ring %d\n",
+				ring_id);
 	}
 	++execlist->elsp_dwords.index;
 	write_vreg(vgpu, offset, p_data, bytes);
 	return 0;
 }
+/**
+ * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
+ * force-nopriv register
+ *
+ * @gvt: a GVT device
+ * @offset: register offset
+ *
+ * Returns:
+ * True if the register is in force-nonpriv whitelist;
+ * False if outside;
+ */
+bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
+					  unsigned int offset)
+{
+	return in_whitelist(offset);
+}

drivers/gpu/drm/i915/gvt/kvmgt.c+23−14

 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 {
-	struct intel_vgpu *vgpu;
+	struct intel_vgpu *vgpu = NULL;
 	struct intel_vgpu_type *type;
 	struct device *pdev;
 	void *gvt;
 	type = intel_gvt_find_vgpu_type(gvt, kobject_name(kobj));
 	if (!type) {
-		gvt_err("failed to find type %s to create\n",
+		gvt_vgpu_err("failed to find type %s to create\n",
 						kobject_name(kobj));
 		ret = -EINVAL;
 		goto out;
 	vgpu = intel_gvt_ops->vgpu_create(gvt, type);
 	if (IS_ERR_OR_NULL(vgpu)) {
 		ret = vgpu == NULL ? -EFAULT : PTR_ERR(vgpu);
-		gvt_err("failed to create intel vgpu: %d\n", ret);
+		gvt_vgpu_err("failed to create intel vgpu: %d\n", ret);
 		goto out;
 	}
 	ret = vfio_register_notifier(mdev_dev(mdev), VFIO_IOMMU_NOTIFY, &events,
 				&vgpu->vdev.iommu_notifier);
 	if (ret != 0) {
-		gvt_err("vfio_register_notifier for iommu failed: %d\n", ret);
+		gvt_vgpu_err("vfio_register_notifier for iommu failed: %d\n",
+			ret);
 		goto out;
 	}
 	ret = vfio_register_notifier(mdev_dev(mdev), VFIO_GROUP_NOTIFY, &events,
 				&vgpu->vdev.group_notifier);
 	if (ret != 0) {
-		gvt_err("vfio_register_notifier for group failed: %d\n", ret);
+		gvt_vgpu_err("vfio_register_notifier for group failed: %d\n",
+			ret);
 		goto undo_iommu;
 	}
 	if (index >= VFIO_PCI_NUM_REGIONS) {
-		gvt_err("invalid index: %u\n", index);
+		gvt_vgpu_err("invalid index: %u\n", index);
 		return -EINVAL;
 	}
 	case VFIO_PCI_VGA_REGION_INDEX:
 	case VFIO_PCI_ROM_REGION_INDEX:
 	default:
-		gvt_err("unsupported region: %u\n", index);
+		gvt_vgpu_err("unsupported region: %u\n", index);
 	}
 	return ret == 0 ? count : ret;
 		trigger = eventfd_ctx_fdget(fd);
 		if (IS_ERR(trigger)) {
-			gvt_err("eventfd_ctx_fdget failed\n");
+			gvt_vgpu_err("eventfd_ctx_fdget failed\n");
 			return PTR_ERR(trigger);
 		}
 		vgpu->vdev.msi_trigger = trigger;
 			ret = vfio_set_irqs_validate_and_prepare(&hdr, max,
 						VFIO_PCI_NUM_IRQS, &data_size);
 			if (ret) {
-				gvt_err("intel:vfio_set_irqs_validate_and_prepare failed\n");
+				gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n");
 				return -EINVAL;
 			}
 			if (data_size) {
 	kvm = vgpu->vdev.kvm;
 	if (!kvm || kvm->mm != current->mm) {
-		gvt_err("KVM is required to use Intel vGPU\n");
+		gvt_vgpu_err("KVM is required to use Intel vGPU\n");
 		return -ESRCH;
 	}
 static bool kvmgt_guest_exit(struct kvmgt_guest_info *info)
 {
+	struct intel_vgpu *vgpu = info->vgpu;
 	if (!info) {
-		gvt_err("kvmgt_guest_info invalid\n");
+		gvt_vgpu_err("kvmgt_guest_info invalid\n");
 		return false;
 	}
 	unsigned long iova, pfn;
 	struct kvmgt_guest_info *info;
 	struct device *dev;
+	struct intel_vgpu *vgpu;
 	int rc;
 	if (!handle_valid(handle))
 		return INTEL_GVT_INVALID_ADDR;
 	info = (struct kvmgt_guest_info *)handle;
+	vgpu = info->vgpu;
 	iova = gvt_cache_find(info->vgpu, gfn);
 	if (iova != INTEL_GVT_INVALID_ADDR)
 		return iova;
 	dev = mdev_dev(info->vgpu->vdev.mdev);
 	rc = vfio_pin_pages(dev, &gfn, 1, IOMMU_READ | IOMMU_WRITE, &pfn);
 	if (rc != 1) {
-		gvt_err("vfio_pin_pages failed for gfn 0x%lx: %d\n", gfn, rc);
+		gvt_vgpu_err("vfio_pin_pages failed for gfn 0x%lx: %d\n",
+			gfn, rc);
 		return INTEL_GVT_INVALID_ADDR;
 	}
 	/* transfer to host iova for GFX to use DMA */
 	rc = gvt_dma_map_iova(info->vgpu, pfn, &iova);
 	if (rc) {
-		gvt_err("gvt_dma_map_iova failed for gfn: 0x%lx\n", gfn);
+		gvt_vgpu_err("gvt_dma_map_iova failed for gfn: 0x%lx\n", gfn);
 		vfio_unpin_pages(dev, &gfn, 1);
 		return INTEL_GVT_INVALID_ADDR;
 	}
 {
 	struct kvmgt_guest_info *info;
 	struct kvm *kvm;
-	int ret;
+	int idx, ret;
 	bool kthread = current->mm == NULL;
 	if (!handle_valid(handle))
 	if (kthread)
 		use_mm(kvm->mm);
+	idx = srcu_read_lock(&kvm->srcu);
 	ret = write ? kvm_write_guest(kvm, gpa, buf, len) :
 		      kvm_read_guest(kvm, gpa, buf, len);
+	srcu_read_unlock(&kvm->srcu, idx);
 	if (kthread)
 		unuse_mm(kvm->mm);

drivers/gpu/drm/i915/gvt/mmio.c+19−19

 			ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
 					p_data, bytes);
 			if (ret) {
-				gvt_err("vgpu%d: guest page read error %d, "
+				gvt_vgpu_err("guest page read error %d, "
 					"gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
-					vgpu->id, ret,
+					ret, gp->gfn, pa, *(u32 *)p_data,
-					gp->gfn, pa, *(u32 *)p_data, bytes);
+					bytes);
 			}
 			mutex_unlock(&gvt->lock);
 			return ret;
 		ret = intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
 		if (!vgpu->mmio.disable_warn_untrack) {
-			gvt_err("vgpu%d: read untracked MMIO %x(%dB) val %x\n",
+			gvt_vgpu_err("read untracked MMIO %x(%dB) val %x\n",
-				vgpu->id, offset, bytes, *(u32 *)p_data);
+				offset, bytes, *(u32 *)p_data);
 			if (offset == 0x206c) {
-				gvt_err("------------------------------------------\n");
+				gvt_vgpu_err("------------------------------------------\n");
-				gvt_err("vgpu%d: likely triggers a gfx reset\n",
+				gvt_vgpu_err("likely triggers a gfx reset\n");
-					vgpu->id);
+				gvt_vgpu_err("------------------------------------------\n");
-				gvt_err("------------------------------------------\n");
 				vgpu->mmio.disable_warn_untrack = true;
 			}
 		}
 	mutex_unlock(&gvt->lock);
 	return 0;
 err:
-	gvt_err("vgpu%d: fail to emulate MMIO read %08x len %d\n",
+	gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
-			vgpu->id, offset, bytes);
+			offset, bytes);
 	mutex_unlock(&gvt->lock);
 	return ret;
 }
 		if (gp) {
 			ret = gp->handler(gp, pa, p_data, bytes);
 			if (ret) {
-				gvt_err("vgpu%d: guest page write error %d, "
+				gvt_err("guest page write error %d, "
-					"gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
+					"gfn 0x%lx, pa 0x%llx, "
-					vgpu->id, ret,
+					"var 0x%x, len %d\n",
-					gp->gfn, pa, *(u32 *)p_data, bytes);
+					ret, gp->gfn, pa,
+					*(u32 *)p_data, bytes);
 			}
 			mutex_unlock(&gvt->lock);
 			return ret;
 			/* all register bits are RO. */
 			if (ro_mask == ~(u64)0) {
-				gvt_err("vgpu%d: try to write RO reg %x\n",
+				gvt_vgpu_err("try to write RO reg %x\n",
-						vgpu->id, offset);
+					offset);
 				ret = 0;
 				goto out;
 			}
 	mutex_unlock(&gvt->lock);
 	return 0;
 err:
-	gvt_err("vgpu%d: fail to emulate MMIO write %08x len %d\n",
+	gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
-			vgpu->id, offset, bytes);
+		     bytes);
 	mutex_unlock(&gvt->lock);
 	return ret;
 }

drivers/gpu/drm/i915/gvt/mmio.h+3−0

@@ -107,4 +107,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, · 106 unmodified lines
107	void *p_data, unsigned int bytes);	107	void *p_data, unsigned int bytes);
108	int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,	108	int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
109	void *p_data, unsigned int bytes);	109	void *p_data, unsigned int bytes);
		110
		111	bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
		112	unsigned int offset);
110	#endif	113	#endif

drivers/gpu/drm/i915/gvt/opregion.c+5−5

 		mfn = intel_gvt_hypervisor_virt_to_mfn(vgpu_opregion(vgpu)->va
 			+ i * PAGE_SIZE);
 		if (mfn == INTEL_GVT_INVALID_ADDR) {
-			gvt_err("fail to get MFN from VA\n");
+			gvt_vgpu_err("fail to get MFN from VA\n");
 			return -EINVAL;
 		}
 		ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu,
 				vgpu_opregion(vgpu)->gfn[i],
 				mfn, 1, map);
 		if (ret) {
-			gvt_err("fail to map GFN to MFN, errno: %d\n", ret);
+			gvt_vgpu_err("fail to map GFN to MFN, errno: %d\n",
+				ret);
 			return ret;
 		}
 	}
 	parm = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_PARM;
 	if (!(swsci & SWSCI_SCI_SELECT)) {
-		gvt_err("vgpu%d: requesting SMI service\n", vgpu->id);
+		gvt_vgpu_err("requesting SMI service\n");
 		return 0;
 	}
 	/* ignore non 0->1 trasitions */
 	func = GVT_OPREGION_FUNC(*scic);
 	subfunc = GVT_OPREGION_SUBFUNC(*scic);
 	if (!querying_capabilities(*scic)) {
-		gvt_err("vgpu%d: requesting runtime service: func \"%s\","
+		gvt_vgpu_err("requesting runtime service: func \"%s\","
 				" subfunc \"%s\"\n",
-				vgpu->id,
 				opregion_func_name(func),
 				opregion_subfunc_name(subfunc));
 		/*

drivers/gpu/drm/i915/gvt/render.c+1−1

@@ -167,7 +167,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) · 166 unmodified lines
167	I915_WRITE_FW(reg, 0x1);	167	I915_WRITE_FW(reg, 0x1);
168		168
169	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))	169	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
170	gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id);	170	gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
171	else	171	else
172	vgpu_vreg(vgpu, regs[ring_id]) = 0;	172	vgpu_vreg(vgpu, regs[ring_id]) = 0;
173		173

drivers/gpu/drm/i915/gvt/sched_policy.c+2−2

@@ -101,7 +101,7 @@ struct tbs_sched_data { · 100 unmodified lines
101	struct list_head runq_head;	101	struct list_head runq_head;
102	};	102	};
103		103
104	#define GVT_DEFAULT_TIME_SLICE (1 * HZ / 1000)	104	#define GVT_DEFAULT_TIME_SLICE (msecs_to_jiffies(1))
105		105
106	static void tbs_sched_func(struct work_struct *work)	106	static void tbs_sched_func(struct work_struct *work)
107	{	107	{
@@ -223,7 +223,7 @@ static void tbs_sched_start_schedule(struct intel_vgpu *vgpu) · 115 unmodified lines
223	return;	223	return;
224		224
225	list_add_tail(&vgpu_data->list, &sched_data->runq_head);	225	list_add_tail(&vgpu_data->list, &sched_data->runq_head);
226	schedule_delayed_work(&sched_data->work, sched_data->period);	226	schedule_delayed_work(&sched_data->work, 0);
227	}	227	}
228		228
229	static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)	229	static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)

drivers/gpu/drm/i915/gvt/scheduler.c+60−46

 				(u32)((workload->ctx_desc.lrca + i) <<
 				GTT_PAGE_SHIFT));
 		if (context_gpa == INTEL_GVT_INVALID_ADDR) {
-			gvt_err("Invalid guest context descriptor\n");
+			gvt_vgpu_err("Invalid guest context descriptor\n");
 			return -EINVAL;
 		}
 static int shadow_context_status_change(struct notifier_block *nb,
 		unsigned long action, void *data)
 {
-	struct intel_vgpu *vgpu = container_of(nb,
+	struct drm_i915_gem_request *req = (struct drm_i915_gem_request *)data;
-			struct intel_vgpu, shadow_ctx_notifier_block);
+	struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
-	struct drm_i915_gem_request *req =
+				shadow_ctx_notifier_block[req->engine->id]);
-		(struct drm_i915_gem_request *)data;
+	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
-	struct intel_gvt_workload_scheduler *scheduler =
-		&vgpu->gvt->scheduler;
 	struct intel_vgpu_workload *workload =
 		scheduler->current_workload[req->engine->id];
 	int ring_id = workload->ring_id;
 	struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 	struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
+	struct intel_engine_cs *engine = dev_priv->engine[ring_id];
 	struct drm_i915_gem_request *rq;
+	struct intel_vgpu *vgpu = workload->vgpu;
 	int ret;
 	gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 	mutex_lock(&dev_priv->drm.struct_mutex);
+	/* pin shadow context by gvt even the shadow context will be pinned
+	 * when i915 alloc request. That is because gvt will update the guest
+	 * context from shadow context when workload is completed, and at that
+	 * moment, i915 may already unpined the shadow context to make the
+	 * shadow_ctx pages invalid. So gvt need to pin itself. After update
+	 * the guest context, gvt can unpin the shadow_ctx safely.
+	 */
+	ret = engine->context_pin(engine, shadow_ctx);
+	if (ret) {
+		gvt_vgpu_err("fail to pin shadow context\n");
+		workload->status = ret;
+		mutex_unlock(&dev_priv->drm.struct_mutex);
+		return ret;
+	}
 	rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
 	if (IS_ERR(rq)) {
-		gvt_err("fail to allocate gem request\n");
+		gvt_vgpu_err("fail to allocate gem request\n");
 		ret = PTR_ERR(rq);
 		goto out;
 	}
 	if (ret)
 		goto out;
-	ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
+	if ((workload->ring_id == RCS) &&
-	if (ret)
+	    (workload->wa_ctx.indirect_ctx.size != 0)) {
-		goto out;
+		ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
+		if (ret)
+			goto out;
+	}
 	ret = populate_shadow_context(workload);
 	if (ret)
 	if (!IS_ERR_OR_NULL(rq))
 		i915_add_request_no_flush(rq);
+	else
+		engine->context_unpin(engine, shadow_ctx);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 	return ret;
 }
 				(u32)((workload->ctx_desc.lrca + i) <<
 					GTT_PAGE_SHIFT));
 		if (context_gpa == INTEL_GVT_INVALID_ADDR) {
-			gvt_err("invalid guest context descriptor\n");
+			gvt_vgpu_err("invalid guest context descriptor\n");
 			return;
 		}
 	 * For the workload w/o request, directly complete the workload.
 	 */
 	if (workload->req) {
+		struct drm_i915_private *dev_priv =
+			workload->vgpu->gvt->dev_priv;
+		struct intel_engine_cs *engine =
+			dev_priv->engine[workload->ring_id];
 		wait_event(workload->shadow_ctx_status_wq,
 			   !atomic_read(&workload->shadow_ctx_active));
 					 INTEL_GVT_EVENT_MAX)
 				intel_vgpu_trigger_virtual_event(vgpu, event);
 		}
+		mutex_lock(&dev_priv->drm.struct_mutex);
+		/* unpin shadow ctx as the shadow_ctx update is done */
+		engine->context_unpin(engine, workload->vgpu->shadow_ctx);
+		mutex_unlock(&dev_priv->drm.struct_mutex);
 	}
 	gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 	int ring_id = p->ring_id;
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 	struct intel_vgpu_workload *workload = NULL;
+	struct intel_vgpu *vgpu = NULL;
 	int ret;
 	bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
 	DEFINE_WAIT_FUNC(wait, woken_wake_function);
 		mutex_unlock(&gvt->lock);
 		if (ret) {
-			gvt_err("fail to dispatch workload, skip\n");
+			vgpu = workload->vgpu;
+			gvt_vgpu_err("fail to dispatch workload, skip\n");
 			goto complete;
 		}
 		gvt_dbg_sched("ring id %d wait workload %p\n",
 				workload->ring_id, workload);
-retry:
+		i915_wait_request(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
-		i915_wait_request(workload->req,
-					 0, MAX_SCHEDULE_TIMEOUT);
-		/* I915 has replay mechanism and a request will be replayed
-		 * if there is i915 reset. So the seqno will be updated anyway.
-		 * If the seqno is not updated yet after waiting, which means
-		 * the replay may still be in progress and we can wait again.
-		 */
-		if (!i915_gem_request_completed(workload->req)) {
-			gvt_dbg_sched("workload %p not completed, wait again\n",
-					workload);
-			goto retry;
-		}
 complete:
 		gvt_dbg_sched("will complete workload %p, status: %d\n",
 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
 {
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
-	int i;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id i;
 	gvt_dbg_core("clean workload scheduler\n");
-	for (i = 0; i < I915_NUM_ENGINES; i++) {
+	for_each_engine(engine, gvt->dev_priv, i) {
-		if (scheduler->thread[i]) {
+		atomic_notifier_chain_unregister(
-			kthread_stop(scheduler->thread[i]);
+					&engine->context_status_notifier,
-			scheduler->thread[i] = NULL;
+					&gvt->shadow_ctx_notifier_block[i]);
-		}
+		kthread_stop(scheduler->thread[i]);
 	}
 }
 {
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 	struct workload_thread_param *param = NULL;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id i;
 	int ret;
-	int i;
 	gvt_dbg_core("init workload scheduler\n");
 	init_waitqueue_head(&scheduler->workload_complete_wq);
-	for (i = 0; i < I915_NUM_ENGINES; i++) {
+	for_each_engine(engine, gvt->dev_priv, i) {
-		/* check ring mask at init time */
-		if (!HAS_ENGINE(gvt->dev_priv, i))
-			continue;
 		init_waitqueue_head(&scheduler->waitq[i]);
 		param = kzalloc(sizeof(*param), GFP_KERNEL);
 			ret = PTR_ERR(scheduler->thread[i]);
 			goto err;
 		}
+		gvt->shadow_ctx_notifier_block[i].notifier_call =
+					shadow_context_status_change;
+		atomic_notifier_chain_register(&engine->context_status_notifier,
+					&gvt->shadow_ctx_notifier_block[i]);
 	}
 	return 0;
 err:
 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
 {
-	atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier,
-			&vgpu->shadow_ctx_notifier_block);
 	i915_gem_context_put_unlocked(vgpu->shadow_ctx);
 }
 	vgpu->shadow_ctx->engine[RCS].initialised = true;
-	vgpu->shadow_ctx_notifier_block.notifier_call =
-		shadow_context_status_change;
-	atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier,
-				       &vgpu->shadow_ctx_notifier_block);
 	return 0;
 }

drivers/gpu/drm/i915/i915_drv.c+3−4

 	case I915_PARAM_IRQ_ACTIVE:
 	case I915_PARAM_ALLOW_BATCHBUFFER:
 	case I915_PARAM_LAST_DISPATCH:
+	case I915_PARAM_HAS_EXEC_CONSTANTS:
 		/* Reject all old ums/dri params. */
 		return -ENODEV;
 	case I915_PARAM_CHIPSET_ID:
 	case I915_PARAM_HAS_BSD2:
 		value = !!dev_priv->engine[VCS2];
 		break;
-	case I915_PARAM_HAS_EXEC_CONSTANTS:
-		value = INTEL_GEN(dev_priv) >= 4;
-		break;
 	case I915_PARAM_HAS_LLC:
 		value = HAS_LLC(dev_priv);
 		break;
 		goto error;
 	}
-	i915_gem_reset_finish(dev_priv);
+	i915_gem_reset(dev_priv);
 	intel_overlay_reset(dev_priv);
 	/* Ok, now get things going again... */
 	i915_queue_hangcheck(dev_priv);
 wakeup:
+	i915_gem_reset_finish(dev_priv);
 	enable_irq(dev_priv->drm.irq);
 	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
 	return;

drivers/gpu/drm/i915/i915_drv.h+3−3

 	PLANE_PRIMARY,
 	PLANE_SPRITE0,
 	PLANE_SPRITE1,
+	PLANE_SPRITE2,
 	PLANE_CURSOR,
 	I915_MAX_PLANES,
 };
 	unsigned boosts;
 	/* manual wa residency calculations */
-	struct intel_rps_ei up_ei, down_ei;
+	struct intel_rps_ei ei;
 	/*
 	 * Protects RPS/RC6 register access and PCU communication.
 	const struct intel_device_info info;
-	int relative_constants_mode;
 	void __iomem *regs;
 	struct intel_uncore uncore;
 }
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
+void i915_gem_reset(struct drm_i915_private *dev_priv);
 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);

drivers/gpu/drm/i915/i915_gem.c+115−6

@@ -1434,6 +1434,12 @@ i915_gem_pwrite_ioctl(struct drm_device dev, void data, · 1433 unmodified lines
1434		1434
1435	trace_i915_gem_object_pwrite(obj, args->offset, args->size);	1435	trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1436		1436
		1437	ret = -ENODEV;
		1438	if (obj->ops->pwrite)
		1439	ret = obj->ops->pwrite(obj, args);
		1440	if (ret != -ENODEV)
		1441	goto err;
		1442
1437	ret = i915_gem_object_wait(obj,	1443	ret = i915_gem_object_wait(obj,
1438	I915_WAIT_INTERRUPTIBLE \|	1444	I915_WAIT_INTERRUPTIBLE \|
1439	I915_WAIT_ALL,	1445	I915_WAIT_ALL,
@@ -2119,6 +2125,7 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj) · 679 unmodified lines
2119	*/	2125	*/
2120	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);	2126	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2121	obj->mm.madv = __I915_MADV_PURGED;	2127	obj->mm.madv = __I915_MADV_PURGED;
		2128	obj->mm.pages = ERR_PTR(-EFAULT);
2122	}	2129	}
2123		2130
2124	/* Try to discard unwanted pages */	2131	/* Try to discard unwanted pages */
@@ -2218,7 +2225,9 @@ void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, · 93 unmodified lines
2218		2225
2219	__i915_gem_object_reset_page_iter(obj);	2226	__i915_gem_object_reset_page_iter(obj);
2220		2227
2221	obj->ops->put_pages(obj, pages);	2228	if (!IS_ERR(pages))
		2229	obj->ops->put_pages(obj, pages);
		2230
2222	unlock:	2231	unlock:
2223	mutex_unlock(&obj->mm.lock);	2232	mutex_unlock(&obj->mm.lock);
2224	}	2233	}
@@ -2437,7 +2446,7 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) · 212 unmodified lines
2437	if (err)	2446	if (err)
2438	return err;	2447	return err;
2439		2448
2440	if (unlikely(!obj->mm.pages)) {	2449	if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2441	err = ____i915_gem_object_get_pages(obj);	2450	err = ____i915_gem_object_get_pages(obj);
2442	if (err)	2451	if (err)
2443	goto unlock;	2452	goto unlock;
@@ -2515,7 +2524,7 @@ void i915_gem_object_pin_map(struct drm_i915_gem_object obj, · 71 unmodified lines
2515		2524
2516	pinned = true;	2525	pinned = true;
2517	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {	2526	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2518	if (unlikely(!obj->mm.pages)) {	2527	if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2519	ret = ____i915_gem_object_get_pages(obj);	2528	ret = ____i915_gem_object_get_pages(obj);
2520	if (ret)	2529	if (ret)
2521	goto err_unlock;	2530	goto err_unlock;
@@ -2563,6 +2572,75 @@ err_unlock: · 41 unmodified lines
2563	goto out_unlock;	2572	goto out_unlock;
2564	}	2573	}
2565		2574
		2575	static int
		2576	i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
		2577	const struct drm_i915_gem_pwrite *arg)
		2578	{
		2579	struct address_space *mapping = obj->base.filp->f_mapping;
		2580	char __user *user_data = u64_to_user_ptr(arg->data_ptr);
		2581	u64 remain, offset;
		2582	unsigned int pg;
		2583
		2584	/* Before we instantiate/pin the backing store for our use, we
		2585	* can prepopulate the shmemfs filp efficiently using a write into
		2586	* the pagecache. We avoid the penalty of instantiating all the
		2587	* pages, important if the user is just writing to a few and never
		2588	* uses the object on the GPU, and using a direct write into shmemfs
		2589	* allows it to avoid the cost of retrieving a page (either swapin
		2590	* or clearing-before-use) before it is overwritten.
		2591	*/
		2592	if (READ_ONCE(obj->mm.pages))
		2593	return -ENODEV;
		2594
		2595	/* Before the pages are instantiated the object is treated as being
		2596	* in the CPU domain. The pages will be clflushed as required before
		2597	* use, and we can freely write into the pages directly. If userspace
		2598	* races pwrite with any other operation; corruption will ensue -
		2599	* that is userspace's prerogative!
		2600	*/
		2601
		2602	remain = arg->size;
		2603	offset = arg->offset;
		2604	pg = offset_in_page(offset);
		2605
		2606	do {
		2607	unsigned int len, unwritten;
		2608	struct page *page;
		2609	void data, vaddr;
		2610	int err;
		2611
		2612	len = PAGE_SIZE - pg;
		2613	if (len > remain)
		2614	len = remain;
		2615
		2616	err = pagecache_write_begin(obj->base.filp, mapping,
		2617	offset, len, 0,
		2618	&page, &data);
		2619	if (err < 0)
		2620	return err;
		2621
		2622	vaddr = kmap(page);
		2623	unwritten = copy_from_user(vaddr + pg, user_data, len);
		2624	kunmap(page);
		2625
		2626	err = pagecache_write_end(obj->base.filp, mapping,
		2627	offset, len, len - unwritten,
		2628	page, data);
		2629	if (err < 0)
		2630	return err;
		2631
		2632	if (unwritten)
		2633	return -EFAULT;
		2634
		2635	remain -= len;
		2636	user_data += len;
		2637	offset += len;
		2638	pg = 0;
		2639	} while (remain);
		2640
		2641	return 0;
		2642	}
		2643
2566	static bool ban_context(const struct i915_gem_context *ctx)	2644	static bool ban_context(const struct i915_gem_context *ctx)
2567	{	2645	{
2568	return (i915_gem_context_is_bannable(ctx) &&	2646	return (i915_gem_context_is_bannable(ctx) &&
@@ -2641,7 +2719,16 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) · 72 unmodified lines
2641	for_each_engine(engine, dev_priv, id) {	2719	for_each_engine(engine, dev_priv, id) {
2642	struct drm_i915_gem_request *request;	2720	struct drm_i915_gem_request *request;
2643		2721
		2722	/* Prevent request submission to the hardware until we have
		2723	* completed the reset in i915_gem_reset_finish(). If a request
		2724	* is completed by one engine, it may then queue a request
		2725	* to a second via its engine->irq_tasklet just as we are
		2726	* calling engine->init_hw() and also writing the ELSP.
		2727	* Turning off the engine->irq_tasklet until the reset is over
		2728	* prevents the race.
		2729	*/
2644	tasklet_kill(&engine->irq_tasklet);	2730	tasklet_kill(&engine->irq_tasklet);
		2731	tasklet_disable(&engine->irq_tasklet);
2645		2732
2646	if (engine_stalled(engine)) {	2733	if (engine_stalled(engine)) {
2647	request = i915_gem_find_active_request(engine);	2734	request = i915_gem_find_active_request(engine);
@@ -2756,7 +2843,7 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) · 108 unmodified lines
2756	engine->reset_hw(engine, request);	2843	engine->reset_hw(engine, request);
2757	}	2844	}
2758		2845
2759	void i915_gem_reset_finish(struct drm_i915_private *dev_priv)	2846	void i915_gem_reset(struct drm_i915_private *dev_priv)
2760	{	2847	{
2761	struct intel_engine_cs *engine;	2848	struct intel_engine_cs *engine;
2762	enum intel_engine_id id;	2849	enum intel_engine_id id;
@@ -2778,6 +2865,17 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) · 15 unmodified lines
2778	}	2865	}
2779	}	2866	}
2780		2867
		2868	void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
		2869	{
		2870	struct intel_engine_cs *engine;
		2871	enum intel_engine_id id;
		2872
		2873	lockdep_assert_held(&dev_priv->drm.struct_mutex);
		2874
		2875	for_each_engine(engine, dev_priv, id)
		2876	tasklet_enable(&engine->irq_tasklet);
		2877	}
		2878
2781	static void nop_submit_request(struct drm_i915_gem_request *request)	2879	static void nop_submit_request(struct drm_i915_gem_request *request)
2782	{	2880	{
2783	dma_fence_set_error(&request->fence, -EIO);	2881	dma_fence_set_error(&request->fence, -EIO);
@@ -3029,6 +3127,16 @@ i915_gem_wait_ioctl(struct drm_device dev, void data, struct drm_file *file) · 245 unmodified lines
3029	args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));	3127	args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3030	if (args->timeout_ns < 0)	3128	if (args->timeout_ns < 0)
3031	args->timeout_ns = 0;	3129	args->timeout_ns = 0;
		3130
		3131	/*
		3132	* Apparently ktime isn't accurate enough and occasionally has a
		3133	* bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
		3134	* things up to make the test happy. We allow up to 1 jiffy.
		3135	*
		3136	* This is a regression from the timespec->ktime conversion.
		3137	*/
		3138	if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
		3139	args->timeout_ns = 0;
3032	}	3140	}
3033		3141
3034	i915_gem_object_put(obj);	3142	i915_gem_object_put(obj);
@@ -3974,8 +4082,11 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, · 939 unmodified lines
3974	static const struct drm_i915_gem_object_ops i915_gem_object_ops = {	4082	static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3975	.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE \|	4083	.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE \|
3976	I915_GEM_OBJECT_IS_SHRINKABLE,	4084	I915_GEM_OBJECT_IS_SHRINKABLE,
		4085
3977	.get_pages = i915_gem_object_get_pages_gtt,	4086	.get_pages = i915_gem_object_get_pages_gtt,
3978	.put_pages = i915_gem_object_put_pages_gtt,	4087	.put_pages = i915_gem_object_put_pages_gtt,
		4088
		4089	.pwrite = i915_gem_object_pwrite_gtt,
3979	};	4090	};
3980		4091
3981	struct drm_i915_gem_object *	4092	struct drm_i915_gem_object *
@@ -4583,8 +4694,6 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) · 601 unmodified lines
4583	init_waitqueue_head(&dev_priv->gpu_error.wait_queue);	4694	init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4584	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);	4695	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4585		4696
4586	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4587
4588	init_waitqueue_head(&dev_priv->pending_flip_queue);	4697	init_waitqueue_head(&dev_priv->pending_flip_queue);
4589		4698
4590	dev_priv->mm.interruptible = true;	4699	dev_priv->mm.interruptible = true;

drivers/gpu/drm/i915/i915_gem_context.c+0−1

@@ -311,7 +311,6 @@ __create_hw_context(struct drm_i915_private *dev_priv, · 310 unmodified lines
311	ctx->ring_size = 4 * PAGE_SIZE;	311	ctx->ring_size = 4 * PAGE_SIZE;
312	ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<	312	ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
313	GEN8_CTX_ADDRESSING_MODE_SHIFT;	313	GEN8_CTX_ADDRESSING_MODE_SHIFT;
314	ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
315		314
316	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not	315	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
317	* present or not in use we still need a small bias as ring wraparound	316	* present or not in use we still need a small bias as ring wraparound

drivers/gpu/drm/i915/i915_gem_context.h+0−3

@@ -160,9 +160,6 @@ struct i915_gem_context { · 159 unmodified lines
160	/** desc_template: invariant fields for the HW context descriptor */	160	/** desc_template: invariant fields for the HW context descriptor */
161	u32 desc_template;	161	u32 desc_template;
162		162
163	/** status_notifier: list of callbacks for context-switch changes */
164	struct atomic_notifier_head status_notifier;
165
166	/** guilty_count: How many times this context has caused a GPU hang. */	163	/** guilty_count: How many times this context has caused a GPU hang. */
167	unsigned int guilty_count;	164	unsigned int guilty_count;
168	/**	165	/**

drivers/gpu/drm/i915/i915_gem_evict.c+4−4

@@ -293,12 +293,12 @@ int i915_gem_evict_for_node(struct i915_address_space *vm, · 292 unmodified lines
293	* those as well to make room for our guard pages.	293	* those as well to make room for our guard pages.
294	*/	294	*/
295	if (check_color) {	295	if (check_color) {
296	if (vma->node.start + vma->node.size == node->start) {	296	if (node->start + node->size == target->start) {
297	if (vma->node.color == node->color)	297	if (node->color == target->color)
298	continue;	298	continue;
299	}	299	}
300	if (vma->node.start == node->start + node->size) {	300	if (node->start == target->start + target->size) {
301	if (vma->node.color == node->color)	301	if (node->color == target->color)
302	continue;	302	continue;
303	}	303	}
304	}	304	}

drivers/gpu/drm/i915/i915_gem_execbuffer.c+2−50

@@ -1408,10 +1408,7 @@ execbuf_submit(struct i915_execbuffer_params *params, · 1407 unmodified lines
1408	struct drm_i915_gem_execbuffer2 *args,	1408	struct drm_i915_gem_execbuffer2 *args,
1409	struct list_head *vmas)	1409	struct list_head *vmas)
1410	{	1410	{
1411	struct drm_i915_private *dev_priv = params->request->i915;
1412	u64 exec_start, exec_len;	1411	u64 exec_start, exec_len;
1413	int instp_mode;
1414	u32 instp_mask;
1415	int ret;	1412	int ret;
1416		1413
1417	ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);	1414	ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
@@ -1422,56 +1419,11 @@ execbuf_submit(struct i915_execbuffer_params *params, · 4 unmodified lines
1422	if (ret)	1419	if (ret)
1423	return ret;	1420	return ret;
1424		1421
1425	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;	1422	if (args->flags & I915_EXEC_CONSTANTS_MASK) {
1426	instp_mask = I915_EXEC_CONSTANTS_MASK;	1423	DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n");
1427	switch (instp_mode) {
1428	case I915_EXEC_CONSTANTS_REL_GENERAL:
1429	case I915_EXEC_CONSTANTS_ABSOLUTE:
1430	case I915_EXEC_CONSTANTS_REL_SURFACE:
1431	if (instp_mode != 0 && params->engine->id != RCS) {
1432	DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1433	return -EINVAL;
1434	}
1435
1436	if (instp_mode != dev_priv->relative_constants_mode) {
1437	if (INTEL_INFO(dev_priv)->gen < 4) {
1438	DRM_DEBUG("no rel constants on pre-gen4\n");
1439	return -EINVAL;
1440	}
1441
1442	if (INTEL_INFO(dev_priv)->gen > 5 &&
1443	instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1444	DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1445	return -EINVAL;
1446	}
1447
1448	/* The HW changed the meaning on this bit on gen6 */
1449	if (INTEL_INFO(dev_priv)->gen >= 6)
1450	instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1451	}
1452	break;
1453	default:
1454	DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1455	return -EINVAL;	1424	return -EINVAL;
1456	}	1425	}
1457		1426
1458	if (params->engine->id == RCS &&
1459	instp_mode != dev_priv->relative_constants_mode) {
1460	struct intel_ring *ring = params->request->ring;
1461
1462	ret = intel_ring_begin(params->request, 4);
1463	if (ret)
1464	return ret;
1465
1466	intel_ring_emit(ring, MI_NOOP);
1467	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1468	intel_ring_emit_reg(ring, INSTPM);
1469	intel_ring_emit(ring, instp_mask << 16 \| instp_mode);
1470	intel_ring_advance(ring);
1471
1472	dev_priv->relative_constants_mode = instp_mode;
1473	}
1474
1475	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {	1427	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1476	ret = i915_reset_gen7_sol_offsets(params->request);	1428	ret = i915_reset_gen7_sol_offsets(params->request);
1477	if (ret)	1429	if (ret)

drivers/gpu/drm/i915/i915_gem_object.h+3−0

@@ -54,6 +54,9 @@ struct drm_i915_gem_object_ops { · 53 unmodified lines
54	struct sg_table (get_pages)(struct drm_i915_gem_object *);	54	struct sg_table (get_pages)(struct drm_i915_gem_object *);
55	void (put_pages)(struct drm_i915_gem_object , struct sg_table *);	55	void (put_pages)(struct drm_i915_gem_object , struct sg_table *);
56		56
		57	int (pwrite)(struct drm_i915_gem_object ,
		58	const struct drm_i915_gem_pwrite *);
		59
57	int (dmabuf_export)(struct drm_i915_gem_object );	60	int (dmabuf_export)(struct drm_i915_gem_object );
58	void (release)(struct drm_i915_gem_object );	61	void (release)(struct drm_i915_gem_object );
59	};	62	};

drivers/gpu/drm/i915/i915_gem_shrinker.c+1−1

@@ -263,7 +263,7 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv) · 262 unmodified lines
263	I915_SHRINK_BOUND \|	263	I915_SHRINK_BOUND \|
264	I915_SHRINK_UNBOUND \|	264	I915_SHRINK_UNBOUND \|
265	I915_SHRINK_ACTIVE);	265	I915_SHRINK_ACTIVE);
266	rcu_barrier(); /* wait until our RCU delayed slab frees are completed */	266	synchronize_rcu(); /* wait for our earlier RCU delayed slab frees */
267		267
268	return freed;	268	return freed;
269	}	269	}

drivers/gpu/drm/i915/i915_irq.c+38−45

@@ -1046,68 +1046,51 @@ static void vlv_c0_read(struct drm_i915_private *dev_priv, · 1045 unmodified lines
1046	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);	1046	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1047	}	1047	}
1048		1048
1049	static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1050	const struct intel_rps_ei *old,
1051	const struct intel_rps_ei *now,
1052	int threshold)
1053	{
1054	u64 time, c0;
1055	unsigned int mul = 100;
1056
1057	if (old->cz_clock == 0)
1058	return false;
1059
1060	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1061	mul <<= 8;
1062
1063	time = now->cz_clock - old->cz_clock;
1064	time = threshold dev_priv->czclk_freq;
1065
1066	/* Workload can be split between render + media, e.g. SwapBuffers
1067	* being blitted in X after being rendered in mesa. To account for
1068	* this we need to combine both engines into our activity counter.
1069	*/
1070	c0 = now->render_c0 - old->render_c0;
1071	c0 += now->media_c0 - old->media_c0;
1072	c0 = mul VLV_CZ_CLOCK_TO_MILLI_SEC;
1073
1074	return c0 >= time;
1075	}
1076
1077	void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)	1049	void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1078	{	1050	{
1079	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);	1051	memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
1080	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1081	}	1052	}
1082		1053
1083	static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)	1054	static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1084	{	1055	{
		1056	const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1085	struct intel_rps_ei now;	1057	struct intel_rps_ei now;
1086	u32 events = 0;	1058	u32 events = 0;
1087		1059
1088	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED \| GEN6_PM_RP_UP_EI_EXPIRED)) == 0)	1060	if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1089	return 0;	1061	return 0;
1090		1062
1091	vlv_c0_read(dev_priv, &now);	1063	vlv_c0_read(dev_priv, &now);
1092	if (now.cz_clock == 0)	1064	if (now.cz_clock == 0)
1093	return 0;	1065	return 0;
1094		1066
1095	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {	1067	if (prev->cz_clock) {
1096	if (!vlv_c0_above(dev_priv,	1068	u64 time, c0;
1097	&dev_priv->rps.down_ei, &now,	1069	unsigned int mul;
1098	dev_priv->rps.down_threshold))	1070
1099	events \|= GEN6_PM_RP_DOWN_THRESHOLD;	1071	mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
1100	dev_priv->rps.down_ei = now;	1072	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1101	}	1073	mul <<= 8;
1102		1074
1103	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {	1075	time = now.cz_clock - prev->cz_clock;
1104	if (vlv_c0_above(dev_priv,	1076	time *= dev_priv->czclk_freq;
1105	&dev_priv->rps.up_ei, &now,	1077
1106	dev_priv->rps.up_threshold))	1078	/* Workload can be split between render + media,
1107	events \|= GEN6_PM_RP_UP_THRESHOLD;	1079	* e.g. SwapBuffers being blitted in X after being rendered in
1108	dev_priv->rps.up_ei = now;	1080	* mesa. To account for this we need to combine both engines
		1081	* into our activity counter.
		1082	*/
		1083	c0 = now.render_c0 - prev->render_c0;
		1084	c0 += now.media_c0 - prev->media_c0;
		1085	c0 *= mul;
		1086
		1087	if (c0 > time * dev_priv->rps.up_threshold)
		1088	events = GEN6_PM_RP_UP_THRESHOLD;
		1089	else if (c0 < time * dev_priv->rps.down_threshold)
		1090	events = GEN6_PM_RP_DOWN_THRESHOLD;
1109	}	1091	}
1110		1092
		1093	dev_priv->rps.ei = now;
1111	return events;	1094	return events;
1112	}	1095	}
1113		1096
@@ -4228,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) · 3114 unmodified lines
4228	/* Let's track the enabled rps events */	4211	/* Let's track the enabled rps events */
4229	if (IS_VALLEYVIEW(dev_priv))	4212	if (IS_VALLEYVIEW(dev_priv))
4230	/* WaGsvRC0ResidencyMethod:vlv */	4213	/* WaGsvRC0ResidencyMethod:vlv */
4231	dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED \| GEN6_PM_RP_UP_EI_EXPIRED;	4214	dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4232	else	4215	else
4233	dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;	4216	dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4234		4217
@@ -4266,6 +4249,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) · 31 unmodified lines
4266	if (!IS_GEN2(dev_priv))	4249	if (!IS_GEN2(dev_priv))
4267	dev->vblank_disable_immediate = true;	4250	dev->vblank_disable_immediate = true;
4268		4251
		4252	/* Most platforms treat the display irq block as an always-on
		4253	* power domain. vlv/chv can disable it at runtime and need
		4254	* special care to avoid writing any of the display block registers
		4255	* outside of the power domain. We defer setting up the display irqs
		4256	* in this case to the runtime pm.
		4257	*/
		4258	dev_priv->display_irqs_enabled = true;
		4259	if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
		4260	dev_priv->display_irqs_enabled = false;
		4261
4269	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;	4262	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4270	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;	4263	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4271		4264

drivers/gpu/drm/i915/i915_vma.c+37−20

 	return ret;
 }
+static void
+i915_vma_remove(struct i915_vma *vma)
+{
+	struct drm_i915_gem_object *obj = vma->obj;
+	GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+	GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
+	drm_mm_remove_node(&vma->node);
+	list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
+	/* Since the unbound list is global, only move to that list if
+	 * no more VMAs exist.
+	 */
+	if (--obj->bind_count == 0)
+		list_move_tail(&obj->global_link,
+			       &to_i915(obj->base.dev)->mm.unbound_list);
+	/* And finally now the object is completely decoupled from this vma,
+	 * we can drop its hold on the backing storage and allow it to be
+	 * reaped by the shrinker.
+	 */
+	i915_gem_object_unpin_pages(obj);
+	GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
+}
 int __i915_vma_do_pin(struct i915_vma *vma,
 		      u64 size, u64 alignment, u64 flags)
 {
-	unsigned int bound = vma->flags;
+	const unsigned int bound = vma->flags;
 	int ret;
 	lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
 	if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) {
 		ret = -EBUSY;
-		goto err;
+		goto err_unpin;
 	}
 	if ((bound & I915_VMA_BIND_MASK) == 0) {
 		ret = i915_vma_insert(vma, size, alignment, flags);
 		if (ret)
-			goto err;
+			goto err_unpin;
 	}
 	ret = i915_vma_bind(vma, vma->obj->cache_level, flags);
 	if (ret)
-		goto err;
+		goto err_remove;
 	if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND)
 		__i915_vma_set_map_and_fenceable(vma);
 	GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags));
 	return 0;
-err:
+err_remove:
+	if ((bound & I915_VMA_BIND_MASK) == 0) {
+		GEM_BUG_ON(vma->pages);
+		i915_vma_remove(vma);
+	}
+err_unpin:
 	__i915_vma_unpin(vma);
 	return ret;
 }
 	}
 	vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND);
-	drm_mm_remove_node(&vma->node);
-	list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
 	if (vma->pages != obj->mm.pages) {
 		GEM_BUG_ON(!vma->pages);
 		sg_free_table(vma->pages);
 	}
 	vma->pages = NULL;
-	/* Since the unbound list is global, only move to that list if
+	i915_vma_remove(vma);
-	 * no more VMAs exist. */
-	if (--obj->bind_count == 0)
-		list_move_tail(&obj->global_link,
-			       &to_i915(obj->base.dev)->mm.unbound_list);
-	/* And finally now the object is completely decoupled from this vma,
-	 * we can drop its hold on the backing storage and allow it to be
-	 * reaped by the shrinker.
-	 */
-	i915_gem_object_unpin_pages(obj);
-	GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
 destroy:
 	if (unlikely(i915_vma_is_closed(vma)))

drivers/gpu/drm/i915/intel_csr.c+0−1

@@ -35,7 +35,6 @@ · 34 unmodified lines
35	*/	35	*/
36		36
37	#define I915_CSR_GLK "i915/glk_dmc_ver1_01.bin"	37	#define I915_CSR_GLK "i915/glk_dmc_ver1_01.bin"
38	MODULE_FIRMWARE(I915_CSR_GLK);
39	#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)	38	#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
40		39
41	#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"	40	#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"

drivers/gpu/drm/i915/intel_display.c+32−35

 	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
 	crtc->base.mode = crtc->base.state->mode;
-	DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
-		      old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
-		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
 	/*
 	 * Update pipe size and adjust fitter if needed: the reason for this is
 	 * that in compute_mode_changes we check the native mode (not the pfit
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc->config->scaler_state;
-	DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
 	if (crtc->config->pch_pfit.enabled) {
 		int id;
-		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
+		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
-			DRM_ERROR("Requesting pfit without getting a scaler first\n");
 			return;
-		}
 		id = scaler_state->scaler_id;
 		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
 			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
 		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
-		DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
 	}
 }
 	} while (progress);
 }
+static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
+{
+	struct intel_atomic_state *state, *next;
+	struct llist_node *freed;
+	freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+	llist_for_each_entry_safe(state, next, freed, freed)
+		drm_atomic_state_put(&state->base);
+}
+static void intel_atomic_helper_free_state_worker(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+	intel_atomic_helper_free_state(dev_priv);
+}
 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 {
 	struct drm_device *dev = state->dev;
 	 * can happen also when the device is completely off.
 	 */
 	intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+	intel_atomic_helper_free_state(dev_priv);
 }
 static void intel_atomic_commit_work(struct work_struct *work)
 		to_intel_atomic_state(old_crtc_state->state);
 	bool modeset = needs_modeset(crtc->state);
+	if (!modeset &&
+	    (intel_cstate->base.color_mgmt_changed ||
+	     intel_cstate->update_pipe)) {
+		intel_color_set_csc(crtc->state);
+		intel_color_load_luts(crtc->state);
+	}
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(intel_crtc);
 	if (modeset)
 		goto out;
-	if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
-		intel_color_set_csc(crtc->state);
-		intel_color_load_luts(crtc->state);
-	}
 	if (intel_cstate->update_pipe)
 		intel_update_pipe_config(intel_crtc, old_intel_cstate);
 	else if (INTEL_GEN(dev_priv) >= 9)
 	drm_modeset_acquire_fini(&ctx);
 }
-static void intel_atomic_helper_free_state(struct work_struct *work)
-{
-	struct drm_i915_private *dev_priv =
-		container_of(work, typeof(*dev_priv), atomic_helper.free_work);
-	struct intel_atomic_state *state, *next;
-	struct llist_node *freed;
-	freed = llist_del_all(&dev_priv->atomic_helper.free_list);
-	llist_for_each_entry_safe(state, next, freed, freed)
-		drm_atomic_state_put(&state->base);
-}
 int intel_modeset_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	dev->mode_config.funcs = &intel_mode_funcs;
 	INIT_WORK(&dev_priv->atomic_helper.free_work,
-		  intel_atomic_helper_free_state);
+		  intel_atomic_helper_free_state_worker);
 	intel_init_quirks(dev);
 		}
 	}
-	intel_update_czclk(dev_priv);
-	intel_update_cdclk(dev_priv);
-	dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
 	intel_shared_dpll_init(dev);
+	intel_update_czclk(dev_priv);
+	intel_modeset_init_hw(dev);
 	if (dev_priv->max_cdclk_freq == 0)
 		intel_update_max_cdclk(dev_priv);
 	intel_init_gt_powersave(dev_priv);
-	intel_modeset_init_hw(dev);
 	intel_setup_overlay(dev_priv);
 }

drivers/gpu/drm/i915/intel_engine_cs.c+2−0

@@ -105,6 +105,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, · 104 unmodified lines
105	/* Nothing to do here, execute in order of dependencies */	105	/* Nothing to do here, execute in order of dependencies */
106	engine->schedule = NULL;	106	engine->schedule = NULL;
107		107
		108	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
		109
108	dev_priv->engine[id] = engine;	110	dev_priv->engine[id] = engine;
109	return 0;	111	return 0;
110	}	112	}

drivers/gpu/drm/i915/intel_fbdev.c+4−6

 				    bool *enabled, int width, int height)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
-	unsigned long conn_configured, mask;
+	unsigned long conn_configured, conn_seq, mask;
 	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
 	int i, j;
 	bool *save_enabled;
 	bool fallback = true;
 	int num_connectors_enabled = 0;
 	int num_connectors_detected = 0;
-	int pass = 0;
 	save_enabled = kcalloc(count, sizeof(bool), GFP_KERNEL);
 	if (!save_enabled)
 	mask = BIT(count) - 1;
 	conn_configured = 0;
 retry:
+	conn_seq = conn_configured;
 	for (i = 0; i < count; i++) {
 		struct drm_fb_helper_connector *fb_conn;
 		struct drm_connector *connector;
 		if (conn_configured & BIT(i))
 			continue;
-		if (pass == 0 && !connector->has_tile)
+		if (conn_seq == 0 && !connector->has_tile)
 			continue;
 		if (connector->status == connector_status_connected)
 		conn_configured |= BIT(i);
 	}
-	if ((conn_configured & mask) != mask) {
+	if ((conn_configured & mask) != mask && conn_configured != conn_seq)
-		pass++;
 		goto retry;
-	}
 	/*
 	 * If the BIOS didn't enable everything it could, fall back to have the

drivers/gpu/drm/i915/intel_gvt.c+5−0

 		goto bail;
 	}
+	if (!i915.enable_execlists) {
+		DRM_INFO("GPU guest virtualisation [GVT-g] disabled due to disabled execlist submission [i915.enable_execlists module parameter]\n");
+		goto bail;
+	}
 	/*
 	 * We're not in host or fail to find a MPT module, disable GVT-g
 	 */

drivers/gpu/drm/i915/intel_hdmi.c+21−3

@@ -1298,16 +1298,34 @@ intel_hdmi_mode_valid(struct drm_connector *connector, · 1297 unmodified lines
1298		1298
1299	static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)	1299	static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1300	{	1300	{
1301	struct drm_device *dev = crtc_state->base.crtc->dev;	1301	struct drm_i915_private *dev_priv =
		1302	to_i915(crtc_state->base.crtc->dev);
		1303	struct drm_atomic_state *state = crtc_state->base.state;
		1304	struct drm_connector_state *connector_state;
		1305	struct drm_connector *connector;
		1306	int i;
1302		1307
1303	if (HAS_GMCH_DISPLAY(to_i915(dev)))	1308	if (HAS_GMCH_DISPLAY(dev_priv))
1304	return false;	1309	return false;
1305		1310
1306	/*	1311	/*
1307	* HDMI 12bpc affects the clocks, so it's only possible	1312	* HDMI 12bpc affects the clocks, so it's only possible
1308	* when not cloning with other encoder types.	1313	* when not cloning with other encoder types.
1309	*/	1314	*/
1310	return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;	1315	if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
		1316	return false;
		1317
		1318	for_each_connector_in_state(state, connector, connector_state, i) {
		1319	const struct drm_display_info *info = &connector->display_info;
		1320
		1321	if (connector_state->crtc != crtc_state->base.crtc)
		1322	continue;
		1323
		1324	if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
		1325	return false;
		1326	}
		1327
		1328	return true;
1311	}	1329	}
1312		1330
1313	bool intel_hdmi_compute_config(struct intel_encoder *encoder,	1331	bool intel_hdmi_compute_config(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_hotplug.c+8−6

 			}
 		}
 	}
-	if (dev_priv->display.hpd_irq_setup)
+	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
 		dev_priv->display.hpd_irq_setup(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 		}
 	}
-	if (storm_detected)
+	if (storm_detected && dev_priv->display_irqs_enabled)
 		dev_priv->display.hpd_irq_setup(dev_priv);
 	spin_unlock(&dev_priv->irq_lock);
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
 	 * just to make the assert_spin_locked checks happy.
 	 */
-	spin_lock_irq(&dev_priv->irq_lock);
+	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
-	if (dev_priv->display.hpd_irq_setup)
+		spin_lock_irq(&dev_priv->irq_lock);
-		dev_priv->display.hpd_irq_setup(dev_priv);
+		if (dev_priv->display_irqs_enabled)
-	spin_unlock_irq(&dev_priv->irq_lock);
+			dev_priv->display.hpd_irq_setup(dev_priv);
+		spin_unlock_irq(&dev_priv->irq_lock);
+	}
 }
 static void i915_hpd_poll_init_work(struct work_struct *work)

drivers/gpu/drm/i915/intel_lrc.c+2−1

@@ -345,7 +345,8 @@ execlists_context_status_change(struct drm_i915_gem_request *rq, · 344 unmodified lines
345	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))	345	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
346	return;	346	return;
347		347
348	atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);	348	atomic_notifier_call_chain(&rq->engine->context_status_notifier,
		349	status, rq);
349	}	350	}
350		351
351	static void	352	static void

drivers/gpu/drm/i915/intel_pm.c+16−7

 		break;
 	}
+	/* When byt can survive without system hang with dynamic
+	 * sw freq adjustments, this restriction can be lifted.
+	 */
+	if (IS_VALLEYVIEW(dev_priv))
+		goto skip_hw_write;
 	I915_WRITE(GEN6_RP_UP_EI,
 		   GT_INTERVAL_FROM_US(dev_priv, ei_up));
 	I915_WRITE(GEN6_RP_UP_THRESHOLD,
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
+skip_hw_write:
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.up_threshold = threshold_up;
 	dev_priv->rps.down_threshold = threshold_down;
 {
 	u32 mask = 0;
+	/* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
 	if (val > dev_priv->rps.min_freq_softlimit)
-		mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
+		mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
 	if (val < dev_priv->rps.max_freq_softlimit)
 		mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
 {
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
-		if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
+		if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
 			gen6_rps_reset_ei(dev_priv);
 		I915_WRITE(GEN6_PMINTRMSK,
 			   gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
  * @timeout_base_ms: timeout for polling with preemption enabled
  *
  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
- * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
+ * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
  * The request is acknowledged once the PCODE reply dword equals @reply after
  * applying @reply_mask. Polling is first attempted with preemption enabled
- * for @timeout_base_ms and if this times out for another 10 ms with
+ * for @timeout_base_ms and if this times out for another 50 ms with
  * preemption disabled.
  *
  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
 	 * worst case) _and_ PCODE was busy for some reason even after a
 	 * (queued) request and @timeout_base_ms delay. As a workaround retry
 	 * the poll with preemption disabled to maximize the number of
-	 * requests. Increase the timeout from @timeout_base_ms to 10ms to
+	 * requests. Increase the timeout from @timeout_base_ms to 50ms to
 	 * account for interrupts that could reduce the number of these
-	 * requests.
+	 * requests, and for any quirks of the PCODE firmware that delays
+	 * the request completion.
 	 */
 	DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
 	WARN_ON_ONCE(timeout_base_ms > 3);
 	preempt_disable();
-	ret = wait_for_atomic(COND, 10);
+	ret = wait_for_atomic(COND, 50);
 	preempt_enable();
 out:

drivers/gpu/drm/i915/intel_ringbuffer.h+3−0

@@ -403,6 +403,9 @@ struct intel_engine_cs { · 402 unmodified lines
403	*/	403	*/
404	struct i915_gem_context *legacy_active_context;	404	struct i915_gem_context *legacy_active_context;
405		405
		406	/* status_notifier: list of callbacks for context-switch changes */
		407	struct atomic_notifier_head context_status_notifier;
		408
406	struct intel_engine_hangcheck hangcheck;	409	struct intel_engine_hangcheck hangcheck;
407		410
408	bool needs_cmd_parser;	411	bool needs_cmd_parser;

drivers/gpu/drm/i915/intel_sprite.c+0−3

@@ -254,9 +254,6 @@ skl_update_plane(struct drm_plane *drm_plane, · 253 unmodified lines
254	int scaler_id = plane_state->scaler_id;	254	int scaler_id = plane_state->scaler_id;
255	const struct intel_scaler *scaler;	255	const struct intel_scaler *scaler;
256		256
257	DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n",
258	plane_id, PS_PLANE_SEL(plane_id));
259
260	scaler = &crtc_state->scaler_state.scalers[scaler_id];	257	scaler = &crtc_state->scaler_state.scalers[scaler_id];
261		258
262	I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),	259	I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),

drivers/gpu/drm/i915/intel_uncore.c+6−7

 	for_each_fw_domain_masked(d, fw_domains, dev_priv)
 		fw_domain_wait_ack(d);
+	dev_priv->uncore.fw_domains_active |= fw_domains;
 }
 static void
 		fw_domain_put(d);
 		fw_domain_posting_read(d);
 	}
+	dev_priv->uncore.fw_domains_active &= ~fw_domains;
 }
 static void
 	if (WARN_ON(domain->wake_count == 0))
 		domain->wake_count++;
-	if (--domain->wake_count == 0) {
+	if (--domain->wake_count == 0)
 		dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
-		dev_priv->uncore.fw_domains_active &= ~domain->mask;
-	}
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 			fw_domains &= ~domain->mask;
 	}
-	if (fw_domains) {
+	if (fw_domains)
 		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
-		dev_priv->uncore.fw_domains_active |= fw_domains;
-	}
 }
 /**
 		fw_domain_arm_timer(domain);
 	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
-	dev_priv->uncore.fw_domains_active |= fw_domains;
 }
 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,

drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c+0−3

@@ -147,9 +147,6 @@ static int omap_gem_dmabuf_mmap(struct dma_buf *buffer, · 146 unmodified lines
147	struct drm_gem_object *obj = buffer->priv;	147	struct drm_gem_object *obj = buffer->priv;
148	int ret = 0;	148	int ret = 0;
149		149
150	if (WARN_ON(!obj->filp))
151	return -EINVAL;
152
153	ret = drm_gem_mmap_obj(obj, omap_gem_mmap_size(obj), vma);	150	ret = drm_gem_mmap_obj(obj, omap_gem_mmap_size(obj), vma);
154	if (ret < 0)	151	if (ret < 0)
155	return ret;	152	return ret;

drivers/gpu/drm/radeon/si_dpm.c+10−0

@@ -2984,6 +2984,16 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, · 2983 unmodified lines
2984	(rdev->pdev->device == 0x6667)) {	2984	(rdev->pdev->device == 0x6667)) {
2985	max_sclk = 75000;	2985	max_sclk = 75000;
2986	}	2986	}
		2987	} else if (rdev->family == CHIP_OLAND) {
		2988	if ((rdev->pdev->revision == 0xC7) \|\|
		2989	(rdev->pdev->revision == 0x80) \|\|
		2990	(rdev->pdev->revision == 0x81) \|\|
		2991	(rdev->pdev->revision == 0x83) \|\|
		2992	(rdev->pdev->revision == 0x87) \|\|
		2993	(rdev->pdev->device == 0x6604) \|\|
		2994	(rdev->pdev->device == 0x6605)) {
		2995	max_sclk = 75000;
		2996	}
2987	}	2997	}
2988		2998
2989	if (rps->vce_active) {	2999	if (rps->vce_active) {

drivers/gpu/drm/tilcdc/tilcdc_crtc.c+24−13

@@ -464,6 +464,7 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc) · 463 unmodified lines
464	{	464	{
465	struct drm_device *dev = crtc->dev;	465	struct drm_device *dev = crtc->dev;
466	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);	466	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
		467	unsigned long flags;
467		468
468	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));	469	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
469	mutex_lock(&tilcdc_crtc->enable_lock);	470	mutex_lock(&tilcdc_crtc->enable_lock);
@@ -484,7 +485,17 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc) · 14 unmodified lines
484	tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,	485	tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
485	LCDC_PALETTE_LOAD_MODE(DATA_ONLY),	486	LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
486	LCDC_PALETTE_LOAD_MODE_MASK);	487	LCDC_PALETTE_LOAD_MODE_MASK);
		488
		489	/* There is no real chance for a race here as the time stamp
		490	* is taken before the raster DMA is started. The spin-lock is
		491	* taken to have a memory barrier after taking the time-stamp
		492	* and to avoid a context switch between taking the stamp and
		493	* enabling the raster.
		494	*/
		495	spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
		496	tilcdc_crtc->last_vblank = ktime_get();
487	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);	497	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
		498	spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
488		499
489	drm_crtc_vblank_on(crtc);	500	drm_crtc_vblank_on(crtc);
490		501
@@ -539,7 +550,6 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) · 48 unmodified lines
539	}	550	}
540		551
541	drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);	552	drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
542	tilcdc_crtc->last_vblank = 0;
543		553
544	tilcdc_crtc->enabled = false;	554	tilcdc_crtc->enabled = false;
545	mutex_unlock(&tilcdc_crtc->enable_lock);	555	mutex_unlock(&tilcdc_crtc->enable_lock);
@@ -602,7 +612,6 @@ int tilcdc_crtc_update_fb(struct drm_crtc *crtc, · 56 unmodified lines
602	{	612	{
603	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);	613	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
604	struct drm_device *dev = crtc->dev;	614	struct drm_device *dev = crtc->dev;
605	unsigned long flags;
606		615
607	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));	616	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
608		617
@@ -614,28 +623,30 @@ int tilcdc_crtc_update_fb(struct drm_crtc *crtc, · 5 unmodified lines
614	drm_framebuffer_reference(fb);	623	drm_framebuffer_reference(fb);
615		624
616	crtc->primary->fb = fb;	625	crtc->primary->fb = fb;
		626	tilcdc_crtc->event = event;
617		627
618	spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);	628	mutex_lock(&tilcdc_crtc->enable_lock);
619		629
620	if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {	630	if (tilcdc_crtc->enabled) {
		631	unsigned long flags;
621	ktime_t next_vblank;	632	ktime_t next_vblank;
622	s64 tdiff;	633	s64 tdiff;
623		634
624	next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,	635	spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
625	1000000 / crtc->hwmode.vrefresh);
626		636
		637	next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
		638	1000000 / crtc->hwmode.vrefresh);
627	tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));	639	tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
628		640
629	if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)	641	if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
630	tilcdc_crtc->next_fb = fb;	642	tilcdc_crtc->next_fb = fb;
631	}	643	else
632		644	set_scanout(crtc, fb);
633	if (tilcdc_crtc->next_fb != fb)
634	set_scanout(crtc, fb);
635		645
636	tilcdc_crtc->event = event;	646	spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
		647	}
637		648
638	spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);	649	mutex_unlock(&tilcdc_crtc->enable_lock);
639		650
640	return 0;	651	return 0;
641	}	652	}
@@ -1036,5 +1047,5 @@ int tilcdc_crtc_create(struct drm_device *dev) · 394 unmodified lines
1036		1047
1037	fail:	1048	fail:
1038	tilcdc_crtc_destroy(crtc);	1049	tilcdc_crtc_destroy(crtc);
1039	return -ENOMEM;	1050	return ret;
1040	}	1051	}

drivers/hid/Kconfig+3−2

 	Support for Cherry Cymotion keyboard.
 config HID_CHICONY
-	tristate "Chicony Tactical pad"
+	tristate "Chicony devices"
 	depends on HID
 	default !EXPERT
 	---help---
-	Support for Chicony Tactical pad.
+	Support for Chicony Tactical pad and special keys on Chicony keyboards.
 config HID_CORSAIR
 	tristate "Corsair devices"
 	Supported devices:
 	- Vengeance K90
+	- Scimitar PRO RGB
 config HID_PRODIKEYS
 	tristate "Prodikeys PC-MIDI Keyboard support"

drivers/hid/hid-chicony.c+1−0

@@ -86,6 +86,7 @@ static const struct hid_device_id ch_devices[] = { · 85 unmodified lines
86	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS2) },	86	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS2) },
87	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_AK1D) },	87	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_AK1D) },
88	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_ACER_SWITCH12) },	88	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_ACER_SWITCH12) },
		89	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS, USB_DEVICE_ID_JESS_ZEN_AIO_KBD) },
89	{ }	90	{ }
90	};	91	};
91	MODULE_DEVICE_TABLE(hid, ch_devices);	92	MODULE_DEVICE_TABLE(hid, ch_devices);

drivers/hid/hid-core.c+2−0

 	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_AK1D) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_ACER_SWITCH12) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K90) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_PRODIKEYS_PCMIDI) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_CYGNAL, USB_DEVICE_ID_CYGNAL_CP2112) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_1) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A081) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A0C2) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_HUION, USB_DEVICE_ID_HUION_TABLET) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS, USB_DEVICE_ID_JESS_ZEN_AIO_KBD) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_JESS2, USB_DEVICE_ID_JESS2_COLOR_RUMBLE_PAD) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ION, USB_DEVICE_ID_ICADE) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_KENSINGTON, USB_DEVICE_ID_KS_SLIMBLADE) },

drivers/hid/hid-corsair.c+47−0

@@ -3,8 +3,10 @@ · 2 unmodified lines
3	*	3	*
4	* Supported devices:	4	* Supported devices:
5	* - Vengeance K90 Keyboard	5	* - Vengeance K90 Keyboard
		6	* - Scimitar PRO RGB Gaming Mouse
6	*	7	*
7	* Copyright (c) 2015 Clement Vuchener	8	* Copyright (c) 2015 Clement Vuchener
		9	* Copyright (c) 2017 Oscar Campos
8	*/	10	*/
9		11
10	/*	12	/*
@@ -670,10 +672,51 @@ static int corsair_input_mapping(struct hid_device *dev, · 659 unmodified lines
670	return 0;	672	return 0;
671	}	673	}
672		674
		675	/*
		676	* The report descriptor of Corsair Scimitar RGB Pro gaming mouse is
		677	* non parseable as they define two consecutive Logical Minimum for
		678	* the Usage Page (Consumer) in rdescs bytes 75 and 77 being 77 0x16
		679	* that should be obviousy 0x26 for Logical Magimum of 16 bits. This
		680	* prevents poper parsing of the report descriptor due Logical
		681	* Minimum being larger than Logical Maximum.
		682	*
		683	* This driver fixes the report descriptor for:
		684	* - USB ID b1c:1b3e, sold as Scimitar RGB Pro Gaming mouse
		685	*/
		686
		687	static __u8 corsair_mouse_report_fixup(struct hid_device hdev, __u8 *rdesc,
		688	unsigned int *rsize)
		689	{
		690	struct usb_interface *intf = to_usb_interface(hdev->dev.parent);
		691
		692	if (intf->cur_altsetting->desc.bInterfaceNumber == 1) {
		693	/*
		694	* Corsair Scimitar RGB Pro report descriptor is broken and
		695	* defines two different Logical Minimum for the Consumer
		696	* Application. The byte 77 should be a 0x26 defining a 16
		697	* bits integer for the Logical Maximum but it is a 0x16
		698	* instead (Logical Minimum)
		699	*/
		700	switch (hdev->product) {
		701	case USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB:
		702	if (*rsize >= 172 && rdesc[75] == 0x15 && rdesc[77] == 0x16
		703	&& rdesc[78] == 0xff && rdesc[79] == 0x0f) {
		704	hid_info(hdev, "Fixing up report descriptor\n");
		705	rdesc[77] = 0x26;
		706	}
		707	break;
		708	}
		709
		710	}
		711	return rdesc;
		712	}
		713
673	static const struct hid_device_id corsair_devices[] = {	714	static const struct hid_device_id corsair_devices[] = {
674	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K90),	715	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K90),
675	.driver_data = CORSAIR_USE_K90_MACRO \|	716	.driver_data = CORSAIR_USE_K90_MACRO \|
676	CORSAIR_USE_K90_BACKLIGHT },	717	CORSAIR_USE_K90_BACKLIGHT },
		718	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR,
		719	USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB) },
677	{}	720	{}
678	};	721	};
679		722
@@ -686,10 +729,14 @@ static struct hid_driver corsair_driver = { · 6 unmodified lines
686	.event = corsair_event,	729	.event = corsair_event,
687	.remove = corsair_remove,	730	.remove = corsair_remove,
688	.input_mapping = corsair_input_mapping,	731	.input_mapping = corsair_input_mapping,
		732	.report_fixup = corsair_mouse_report_fixup,
689	};	733	};
690		734
691	module_hid_driver(corsair_driver);	735	module_hid_driver(corsair_driver);
692		736
693	MODULE_LICENSE("GPL");	737	MODULE_LICENSE("GPL");
		738	/* Original K90 driver author */
694	MODULE_AUTHOR("Clement Vuchener");	739	MODULE_AUTHOR("Clement Vuchener");
		740	/* Scimitar PRO RGB driver author */
		741	MODULE_AUTHOR("Oscar Campos");
695	MODULE_DESCRIPTION("HID driver for Corsair devices");	742	MODULE_DESCRIPTION("HID driver for Corsair devices");

drivers/hid/hid-ids.h+4−0

 #define USB_DEVICE_ID_CORSAIR_K70RGB    0x1b13
 #define USB_DEVICE_ID_CORSAIR_STRAFE    0x1b15
 #define USB_DEVICE_ID_CORSAIR_K65RGB    0x1b17
+#define USB_DEVICE_ID_CORSAIR_K70RGB_RAPIDFIRE  0x1b38
+#define USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE  0x1b39
+#define USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB  0x1b3e
 #define USB_VENDOR_ID_CREATIVELABS	0x041e
 #define USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51	0x322c
 #define USB_VENDOR_ID_JESS		0x0c45
 #define USB_DEVICE_ID_JESS_YUREX	0x1010
+#define USB_DEVICE_ID_JESS_ZEN_AIO_KBD	0x5112
 #define USB_VENDOR_ID_JESS2		0x0f30
 #define USB_DEVICE_ID_JESS2_COLOR_RUMBLE_PAD 0x0111

drivers/hid/hid-sony.c+2−0

 		sony_leds_remove(sc);
 	if (sc->quirks & SONY_BATTERY_SUPPORT)
 		sony_battery_remove(sc);
+	if (sc->touchpad)
+		sony_unregister_touchpad(sc);
 	sony_cancel_work_sync(sc);
 	kfree(sc->output_report_dmabuf);
 	sony_remove_dev_list(sc);

drivers/hid/usbhid/hid-quirks.c+3−0

 	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K70RGB, HID_QUIRK_NO_INIT_REPORTS },
 	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K65RGB, HID_QUIRK_NO_INIT_REPORTS },
 	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_STRAFE, HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
+	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K70RGB_RAPIDFIRE, HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
+	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE, HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
+	{ USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB, HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
 	{ USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51, HID_QUIRK_NOGET },
 	{ USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC, HID_QUIRK_NOGET },
 	{ USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_WIIU, HID_QUIRK_MULTI_INPUT },

drivers/hid/wacom_sys.c+3−1

@@ -2579,7 +2579,9 @@ static void wacom_remove(struct hid_device *hdev) · 2578 unmodified lines
2579		2579
2580	/* make sure we don't trigger the LEDs */	2580	/* make sure we don't trigger the LEDs */
2581	wacom_led_groups_release(wacom);	2581	wacom_led_groups_release(wacom);
2582	wacom_release_resources(wacom);	2582
		2583	if (wacom->wacom_wac.features.type != REMOTE)
		2584	wacom_release_resources(wacom);
2583		2585
2584	hid_set_drvdata(hdev, NULL);	2586	hid_set_drvdata(hdev, NULL);
2585	}	2587	}

drivers/hid/wacom_wac.c+6−4

 		input_set_capability(input, EV_KEY, BTN_TOOL_BRUSH);
 		input_set_capability(input, EV_KEY, BTN_TOOL_PENCIL);
 		input_set_capability(input, EV_KEY, BTN_TOOL_AIRBRUSH);
-		input_set_capability(input, EV_KEY, BTN_TOOL_MOUSE);
+		if (!(features->device_type & WACOM_DEVICETYPE_DIRECT)) {
-		input_set_capability(input, EV_KEY, BTN_TOOL_LENS);
+			input_set_capability(input, EV_KEY, BTN_TOOL_MOUSE);
+			input_set_capability(input, EV_KEY, BTN_TOOL_LENS);
+		}
 		break;
 	case WACOM_HID_WD_FINGERWHEEL:
 		wacom_map_usage(input, usage, field, EV_ABS, ABS_WHEEL, 0);
 	  WACOM_DTU_OFFSET, WACOM_DTU_OFFSET };
 static const struct wacom_features wacom_features_0x360 =
 	{ "Wacom Intuos Pro M", 44800, 29600, 8191, 63,
-	  INTUOSP2_BT, WACOM_INTUOS_RES, WACOM_INTUOS_RES, 9, .touch_max = 10 };
+	  INTUOSP2_BT, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 9, .touch_max = 10 };
 static const struct wacom_features wacom_features_0x361 =
 	{ "Wacom Intuos Pro L", 62200, 43200, 8191, 63,
-	  INTUOSP2_BT, WACOM_INTUOS_RES, WACOM_INTUOS_RES, 9, .touch_max = 10 };
+	  INTUOSP2_BT, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 9, .touch_max = 10 };
 static const struct wacom_features wacom_features_HID_ANY_ID =
 	{ "Wacom HID", .type = HID_GENERIC, .oVid = HID_ANY_ID, .oPid = HID_ANY_ID };

drivers/hv/channel.c+12−13

 	wait_for_completion(&info->waitevent);
-	if (channel->rescind) {
-		ret = -ENODEV;
-		goto post_msg_err;
-	}
 post_msg_err:
+	/*
+	 * If the channel has been rescinded;
+	 * we will be awakened by the rescind
+	 * handler; set the error code to zero so we don't leak memory.
+	 */
+	if (channel->rescind)
+		ret = 0;
 	spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
 	list_del(&info->msglistentry);
 	spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
 	int ret;
 	/*
-	 * vmbus_on_event(), running in the tasklet, can race
+	 * vmbus_on_event(), running in the per-channel tasklet, can race
 	 * with vmbus_close_internal() in the case of SMP guest, e.g., when
 	 * the former is accessing channel->inbound.ring_buffer, the latter
-	 * could be freeing the ring_buffer pages.
+	 * could be freeing the ring_buffer pages, so here we must stop it
-	 *
+	 * first.
-	 * To resolve the race, we can serialize them by disabling the
-	 * tasklet when the latter is running here.
 	 */
-	hv_event_tasklet_disable(channel);
+	tasklet_disable(&channel->callback_event);
 	/*
 	 * In case a device driver's probe() fails (e.g.,
 		get_order(channel->ringbuffer_pagecount * PAGE_SIZE));
 out:
-	hv_event_tasklet_enable(channel);
 	return ret;
 }

drivers/hv/channel_mgmt.c+5−22

@@ -350,7 +350,8 @@ static struct vmbus_channel *alloc_channel(void) · 349 unmodified lines
350	static void free_channel(struct vmbus_channel *channel)	350	static void free_channel(struct vmbus_channel *channel)
351	{	351	{
352	tasklet_kill(&channel->callback_event);	352	tasklet_kill(&channel->callback_event);
353	kfree(channel);	353
		354	kfree_rcu(channel, rcu);
354	}	355	}
355		356
356	static void percpu_channel_enq(void *arg)	357	static void percpu_channel_enq(void *arg)
@@ -359,14 +360,14 @@ static void percpu_channel_enq(void *arg) · 2 unmodified lines
359	struct hv_per_cpu_context *hv_cpu	360	struct hv_per_cpu_context *hv_cpu
360	= this_cpu_ptr(hv_context.cpu_context);	361	= this_cpu_ptr(hv_context.cpu_context);
361		362
362	list_add_tail(&channel->percpu_list, &hv_cpu->chan_list);	363	list_add_tail_rcu(&channel->percpu_list, &hv_cpu->chan_list);
363	}	364	}
364		365
365	static void percpu_channel_deq(void *arg)	366	static void percpu_channel_deq(void *arg)
366	{	367	{
367	struct vmbus_channel *channel = arg;	368	struct vmbus_channel *channel = arg;
368		369
369	list_del(&channel->percpu_list);	370	list_del_rcu(&channel->percpu_list);
370	}	371	}
371		372
372		373
@@ -381,19 +382,6 @@ static void vmbus_release_relid(u32 relid) · 8 unmodified lines
381	true);	382	true);
382	}	383	}
383		384
384	void hv_event_tasklet_disable(struct vmbus_channel *channel)
385	{
386	tasklet_disable(&channel->callback_event);
387	}
388
389	void hv_event_tasklet_enable(struct vmbus_channel *channel)
390	{
391	tasklet_enable(&channel->callback_event);
392
393	/* In case there is any pending event */
394	tasklet_schedule(&channel->callback_event);
395	}
396
397	void hv_process_channel_removal(struct vmbus_channel *channel, u32 relid)	385	void hv_process_channel_removal(struct vmbus_channel *channel, u32 relid)
398	{	386	{
399	unsigned long flags;	387	unsigned long flags;
@@ -402,7 +390,6 @@ void hv_process_channel_removal(struct vmbus_channel *channel, u32 relid) · 2 unmodified lines
402	BUG_ON(!channel->rescind);	390	BUG_ON(!channel->rescind);
403	BUG_ON(!mutex_is_locked(&vmbus_connection.channel_mutex));	391	BUG_ON(!mutex_is_locked(&vmbus_connection.channel_mutex));
404		392
405	hv_event_tasklet_disable(channel);
406	if (channel->target_cpu != get_cpu()) {	393	if (channel->target_cpu != get_cpu()) {
407	put_cpu();	394	put_cpu();
408	smp_call_function_single(channel->target_cpu,	395	smp_call_function_single(channel->target_cpu,
@@ -411,7 +398,6 @@ void hv_process_channel_removal(struct vmbus_channel *channel, u32 relid) · 2 unmodified lines
411	percpu_channel_deq(channel);	398	percpu_channel_deq(channel);
412	put_cpu();	399	put_cpu();
413	}	400	}
414	hv_event_tasklet_enable(channel);
415		401
416	if (channel->primary_channel == NULL) {	402	if (channel->primary_channel == NULL) {
417	list_del(&channel->listentry);	403	list_del(&channel->listentry);
@@ -505,7 +491,6 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 87 unmodified lines
505		491
506	init_vp_index(newchannel, dev_type);	492	init_vp_index(newchannel, dev_type);
507		493
508	hv_event_tasklet_disable(newchannel);
509	if (newchannel->target_cpu != get_cpu()) {	494	if (newchannel->target_cpu != get_cpu()) {
510	put_cpu();	495	put_cpu();
511	smp_call_function_single(newchannel->target_cpu,	496	smp_call_function_single(newchannel->target_cpu,
@@ -515,7 +500,6 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) · 3 unmodified lines
515	percpu_channel_enq(newchannel);	500	percpu_channel_enq(newchannel);
516	put_cpu();	501	put_cpu();
517	}	502	}
518	hv_event_tasklet_enable(newchannel);
519		503
520	/*	504	/*
521	* This state is used to indicate a successful open	505	* This state is used to indicate a successful open
@@ -565,7 +549,6 @@ err_deq_chan: · 43 unmodified lines
565	list_del(&newchannel->listentry);	549	list_del(&newchannel->listentry);
566	mutex_unlock(&vmbus_connection.channel_mutex);	550	mutex_unlock(&vmbus_connection.channel_mutex);
567		551
568	hv_event_tasklet_disable(newchannel);
569	if (newchannel->target_cpu != get_cpu()) {	552	if (newchannel->target_cpu != get_cpu()) {
570	put_cpu();	553	put_cpu();
571	smp_call_function_single(newchannel->target_cpu,	554	smp_call_function_single(newchannel->target_cpu,
@@ -574,7 +557,6 @@ err_deq_chan: · 2 unmodified lines
574	percpu_channel_deq(newchannel);	557	percpu_channel_deq(newchannel);
575	put_cpu();	558	put_cpu();
576	}	559	}
577	hv_event_tasklet_enable(newchannel);
578		560
579	vmbus_release_relid(newchannel->offermsg.child_relid);	561	vmbus_release_relid(newchannel->offermsg.child_relid);
580		562
@@ -814,6 +796,7 @@ static void vmbus_onoffer(struct vmbus_channel_message_header *hdr) · 233 unmodified lines
814	/* Allocate the channel object and save this offer. */	796	/* Allocate the channel object and save this offer. */
815	newchannel = alloc_channel();	797	newchannel = alloc_channel();
816	if (!newchannel) {	798	if (!newchannel) {
		799	vmbus_release_relid(offer->child_relid);
817	pr_err("Unable to allocate channel object\n");	800	pr_err("Unable to allocate channel object\n");
818	return;	801	return;
819	}	802	}

drivers/hv/hv_fcopy.c+0−4

 static const char fcopy_devname[] = "vmbus/hv_fcopy";
 static u8 *recv_buffer;
 static struct hvutil_transport *hvt;
-static struct completion release_event;
 /*
  * This state maintains the version number registered by the daemon.
  */
 	if (cancel_delayed_work_sync(&fcopy_timeout_work))
 		fcopy_respond_to_host(HV_E_FAIL);
-	complete(&release_event);
 }
 int hv_fcopy_init(struct hv_util_service *srv)
 	recv_buffer = srv->recv_buffer;
 	fcopy_transaction.recv_channel = srv->channel;
-	init_completion(&release_event);
 	/*
 	 * When this driver loads, the user level daemon that
 	 * processes the host requests may not yet be running.
 	fcopy_transaction.state = HVUTIL_DEVICE_DYING;
 	cancel_delayed_work_sync(&fcopy_timeout_work);
 	hvutil_transport_destroy(hvt);
-	wait_for_completion(&release_event);
 }

drivers/hv/hv_kvp.c+0−4

 static const char kvp_devname[] = "vmbus/hv_kvp";
 static u8 *recv_buffer;
 static struct hvutil_transport *hvt;
-static struct completion release_event;
 /*
  * Register the kernel component with the user-level daemon.
  * As part of this registration, pass the LIC version number.
 	if (cancel_delayed_work_sync(&kvp_timeout_work))
 		kvp_respond_to_host(NULL, HV_E_FAIL);
 	kvp_transaction.state = HVUTIL_DEVICE_INIT;
-	complete(&release_event);
 }
 int
 	recv_buffer = srv->recv_buffer;
 	kvp_transaction.recv_channel = srv->channel;
-	init_completion(&release_event);
 	/*
 	 * When this driver loads, the user level daemon that
 	 * processes the host requests may not yet be running.
 	cancel_delayed_work_sync(&kvp_timeout_work);
 	cancel_work_sync(&kvp_sendkey_work);
 	hvutil_transport_destroy(hvt);
-	wait_for_completion(&release_event);
 }

drivers/hv/hv_snapshot.c+0−4

 static const char vss_devname[] = "vmbus/hv_vss";
 static __u8 *recv_buffer;
 static struct hvutil_transport *hvt;
-static struct completion release_event;
 static void vss_timeout_func(struct work_struct *dummy);
 static void vss_handle_request(struct work_struct *dummy);
 	if (cancel_delayed_work_sync(&vss_timeout_work))
 		vss_respond_to_host(HV_E_FAIL);
 	vss_transaction.state = HVUTIL_DEVICE_INIT;
-	complete(&release_event);
 }
 int
 hv_vss_init(struct hv_util_service *srv)
 {
-	init_completion(&release_event);
 	if (vmbus_proto_version < VERSION_WIN8_1) {
 		pr_warn("Integration service 'Backup (volume snapshot)'"
 			" not supported on this host version.\n");
 	cancel_delayed_work_sync(&vss_timeout_work);
 	cancel_work_sync(&vss_handle_request_work);
 	hvutil_transport_destroy(hvt);
-	wait_for_completion(&release_event);
 }

drivers/hv/hv_util.c+2−0

@@ -590,6 +590,8 @@ static int hv_timesync_init(struct hv_util_service *srv) · 589 unmodified lines
590	if (!hyperv_cs)	590	if (!hyperv_cs)
591	return -ENODEV;	591	return -ENODEV;
592		592
		593	spin_lock_init(&host_ts.lock);
		594
593	INIT_WORK(&wrk.work, hv_set_host_time);	595	INIT_WORK(&wrk.work, hv_set_host_time);
594		596
595	/*	597	/*

drivers/hv/hv_utils_transport.c+8−4

 	 * connects back.
 	 */
 	hvt_reset(hvt);
-	mutex_unlock(&hvt->lock);
 	if (mode_old == HVUTIL_TRANSPORT_DESTROY)
-		hvt_transport_free(hvt);
+		complete(&hvt->release);
+	mutex_unlock(&hvt->lock);
 	return 0;
 }
 	init_waitqueue_head(&hvt->outmsg_q);
 	mutex_init(&hvt->lock);
+	init_completion(&hvt->release);
 	spin_lock(&hvt_list_lock);
 	list_add(&hvt->list, &hvt_list);
 	if (hvt->cn_id.idx > 0 && hvt->cn_id.val > 0)
 		cn_del_callback(&hvt->cn_id);
-	if (mode_old != HVUTIL_TRANSPORT_CHARDEV)
+	if (mode_old == HVUTIL_TRANSPORT_CHARDEV)
-		hvt_transport_free(hvt);
+		wait_for_completion(&hvt->release);
+	hvt_transport_free(hvt);
 }

drivers/hv/hv_utils_transport.h+1−0

@@ -41,6 +41,7 @@ struct hvutil_transport { · 40 unmodified lines
41	int outmsg_len; /* its length */	41	int outmsg_len; /* its length */
42	wait_queue_head_t outmsg_q; /* poll/read wait queue */	42	wait_queue_head_t outmsg_q; /* poll/read wait queue */
43	struct mutex lock; /* protects struct members */	43	struct mutex lock; /* protects struct members */
		44	struct completion release; /* synchronize with fd release */
44	};	45	};
45		46
46	struct hvutil_transport hvutil_transport_init(const char name,	47	struct hvutil_transport hvutil_transport_init(const char name,

drivers/hv/vmbus_drv.c+5−1

 		if (relid == 0)
 			continue;
+		rcu_read_lock();
 		/* Find channel based on relid */
-		list_for_each_entry(channel, &hv_cpu->chan_list, percpu_list) {
+		list_for_each_entry_rcu(channel, &hv_cpu->chan_list, percpu_list) {
 			if (channel->offermsg.child_relid != relid)
 				continue;
 				tasklet_schedule(&channel->callback_event);
 			}
 		}
+		rcu_read_unlock();
 	}
 }

drivers/hwmon/asus_atk0110.c+3−0

@@ -646,6 +646,9 @@ static int atk_read_value(struct atk_sensor_data sensor, u64 value) · 645 unmodified lines
646	else	646	else
647	err = atk_read_value_new(sensor, value);	647	err = atk_read_value_new(sensor, value);
648		648
		649	if (err)
		650	return err;
		651
649	sensor->is_valid = true;	652	sensor->is_valid = true;
650	sensor->last_updated = jiffies;	653	sensor->last_updated = jiffies;
651	sensor->cached_value = *value;	654	sensor->cached_value = *value;

drivers/hwmon/it87.c+19−5

 {
 	int sioaddr[2] = { REG_2E, REG_4E };
 	struct it87_sio_data sio_data;
-	unsigned short isa_address;
+	unsigned short isa_address[2];
 	bool found = false;
 	int i, err;
 	for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
 		memset(&sio_data, 0, sizeof(struct it87_sio_data));
-		isa_address = 0;
+		isa_address[i] = 0;
-		err = it87_find(sioaddr[i], &isa_address, &sio_data);
+		err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
-		if (err || isa_address == 0)
+		if (err || isa_address[i] == 0)
 			continue;
+		/*
+		 * Don't register second chip if its ISA address matches
+		 * the first chip's ISA address.
+		 */
+		if (i && isa_address[i] == isa_address[0])
+			break;
-		err = it87_device_add(i, isa_address, &sio_data);
+		err = it87_device_add(i, isa_address[i], &sio_data);
 		if (err)
 			goto exit_dev_unregister;
 		found = true;
+		/*
+		 * IT8705F may respond on both SIO addresses.
+		 * Stop probing after finding one.
+		 */
+		if (sio_data.type == it87)
+			break;
 	}
 	if (!found) {

drivers/hwmon/max31790.c+1−1

@@ -311,7 +311,7 @@ static int max31790_write_pwm(struct device *dev, u32 attr, int channel, · 310 unmodified lines
311	data->pwm[channel] = val << 8;	311	data->pwm[channel] = val << 8;
312	err = i2c_smbus_write_word_swapped(client,	312	err = i2c_smbus_write_word_swapped(client,
313	MAX31790_REG_PWMOUT(channel),	313	MAX31790_REG_PWMOUT(channel),
314	val);	314	data->pwm[channel]);
315	break;	315	break;
316	case hwmon_pwm_enable:	316	case hwmon_pwm_enable:
317	fan_config = data->fan_config[channel];	317	fan_config = data->fan_config[channel];

drivers/hwtracing/intel_th/core.c+3−1

 	else
 		intel_th_trace_enable(thdev);
-	if (ret)
+	if (ret) {
 		pm_runtime_put(&thdev->dev);
+		module_put(thdrv->driver.owner);
+	}
 	return ret;
 }

drivers/hwtracing/intel_th/pci.c+10−0

@@ -85,6 +85,16 @@ static const struct pci_device_id intel_th_pci_id_table[] = { · 84 unmodified lines
85	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),	85	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
86	.driver_data = (kernel_ulong_t)0,	86	.driver_data = (kernel_ulong_t)0,
87	},	87	},
		88	{
		89	/* Denverton */
		90	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
		91	.driver_data = (kernel_ulong_t)0,
		92	},
		93	{
		94	/* Gemini Lake */
		95	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
		96	.driver_data = (kernel_ulong_t)0,
		97	},
88	{ 0 },	98	{ 0 },
89	};	99	};
90		100

drivers/iio/adc/ti_am335x_adc.c+12−1

 {
 	struct iio_dev *indio_dev = private;
 	struct tiadc_device *adc_dev = iio_priv(indio_dev);
-	unsigned int status, config;
+	unsigned int status, config, adc_fsm;
+	unsigned short count = 0;
 	status = tiadc_readl(adc_dev, REG_IRQSTATUS);
 	/*
 		tiadc_writel(adc_dev, REG_CTRL, config);
 		tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
 				| IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
+		/* wait for idle state.
+		 * ADC needs to finish the current conversion
+		 * before disabling the module
+		 */
+		do {
+			adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
+		} while (adc_fsm != 0x10 && count++ < 100);
 		tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
 		return IRQ_HANDLED;
 	} else if (status & IRQENB_FIFO1THRES) {

drivers/iio/common/hid-sensors/hid-sensor-trigger.c+3−3

 			st->report_state.report_id,
 			st->report_state.index,
 			HID_USAGE_SENSOR_PROP_REPORTING_STATE_ALL_EVENTS_ENUM);
-		poll_value = hid_sensor_read_poll_value(st);
 	} else {
 		int val;
 	sensor_hub_get_feature(st->hsdev, st->power_state.report_id,
 			       st->power_state.index,
 			       sizeof(state_val), &state_val);
-	if (state && poll_value)
+	if (state)
+		poll_value = hid_sensor_read_poll_value(st);
+	if (poll_value > 0)
 		msleep_interruptible(poll_value * 2);
 	return 0;

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c+2−2

@@ -193,8 +193,8 @@ int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor, u16 watermark) · 192 unmodified lines
193	if (err < 0)	193	if (err < 0)
194	goto out;	194	goto out;
195		195
196	fifo_watermark = ((data & ~ST_LSM6DSX_FIFO_TH_MASK) << 8) \|	196	fifo_watermark = ((data << 8) & ~ST_LSM6DSX_FIFO_TH_MASK) \|
197	(fifo_watermark & ST_LSM6DSX_FIFO_TH_MASK);	197	(fifo_watermark & ST_LSM6DSX_FIFO_TH_MASK);
198		198
199	wdata = cpu_to_le16(fifo_watermark);	199	wdata = cpu_to_le16(fifo_watermark);
200	err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_FIFO_THL_ADDR,	200	err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_FIFO_THL_ADDR,

drivers/iio/magnetometer/ak8974.c+2−2

@@ -763,7 +763,7 @@ power_off: · 762 unmodified lines
763	return ret;	763	return ret;
764	}	764	}
765		765
766	static int __exit ak8974_remove(struct i2c_client *i2c)	766	static int ak8974_remove(struct i2c_client *i2c)
767	{	767	{
768	struct iio_dev *indio_dev = i2c_get_clientdata(i2c);	768	struct iio_dev *indio_dev = i2c_get_clientdata(i2c);
769	struct ak8974 *ak8974 = iio_priv(indio_dev);	769	struct ak8974 *ak8974 = iio_priv(indio_dev);
@@ -845,7 +845,7 @@ static struct i2c_driver ak8974_driver = { · 75 unmodified lines
845	.of_match_table = of_match_ptr(ak8974_of_match),	845	.of_match_table = of_match_ptr(ak8974_of_match),
846	},	846	},
847	.probe = ak8974_probe,	847	.probe = ak8974_probe,
848	.remove = __exit_p(ak8974_remove),	848	.remove = ak8974_remove,
849	.id_table = ak8974_id,	849	.id_table = ak8974_id,
850	};	850	};
851	module_i2c_driver(ak8974_driver);	851	module_i2c_driver(ak8974_driver);

drivers/infiniband/core/cq.c+8−2

 {
 	int i, n, completed = 0;
-	while ((n = ib_poll_cq(cq, IB_POLL_BATCH, cq->wc)) > 0) {
+	/*
+	 * budget might be (-1) if the caller does not
+	 * want to bound this call, thus we need unsigned
+	 * minimum here.
+	 */
+	while ((n = ib_poll_cq(cq, min_t(u32, IB_POLL_BATCH,
+			budget - completed), cq->wc)) > 0) {
 		for (i = 0; i < n; i++) {
 			struct ib_wc *wc = &cq->wc[i];
 		irq_poll_disable(&cq->iop);
 		break;
 	case IB_POLL_WORKQUEUE:
-		flush_work(&cq->work);
+		cancel_work_sync(&cq->work);
 		break;
 	default:
 		WARN_ON_ONCE(1);

drivers/infiniband/core/device.c+21−8

 	struct device *parent = device->dev.parent;
 	WARN_ON_ONCE(!parent);
-	if (!device->dev.dma_ops)
+	WARN_ON_ONCE(device->dma_device);
-		device->dev.dma_ops = parent->dma_ops;
+	if (device->dev.dma_ops) {
-	if (!device->dev.dma_mask)
+		/*
-		device->dev.dma_mask = parent->dma_mask;
+		 * The caller provided custom DMA operations. Copy the
-	if (!device->dev.coherent_dma_mask)
+		 * DMA-related fields that are used by e.g. dma_alloc_coherent()
-		device->dev.coherent_dma_mask = parent->coherent_dma_mask;
+		 * into device->dev.
+		 */
+		device->dma_device = &device->dev;
+		if (!device->dev.dma_mask)
+			device->dev.dma_mask = parent->dma_mask;
+		if (!device->dev.coherent_dma_mask)
+			device->dev.coherent_dma_mask =
+				parent->coherent_dma_mask;
+	} else {
+		/*
+		 * The caller did not provide custom DMA operations. Use the
+		 * DMA mapping operations of the parent device.
+		 */
+		device->dma_device = parent;
+	}
 	mutex_lock(&device_mutex);
 		return -ENOMEM;
 	ib_comp_wq = alloc_workqueue("ib-comp-wq",
-			WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
+			WQ_HIGHPRI | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
-			WQ_UNBOUND_MAX_ACTIVE);
 	if (!ib_comp_wq) {
 		ret = -ENOMEM;
 		goto err;

drivers/infiniband/hw/i40iw/i40iw_utils.c+8−0

 		return NOTIFY_DONE;
 	iwdev = &hdl->device;
+	if (iwdev->init_state < INET_NOTIFIER)
+		return NOTIFY_DONE;
 	netdev = iwdev->ldev->netdev;
 	upper_dev = netdev_master_upper_dev_get(netdev);
 	if (netdev != event_netdev)
 		return NOTIFY_DONE;
 	iwdev = &hdl->device;
+	if (iwdev->init_state < INET_NOTIFIER)
+		return NOTIFY_DONE;
 	netdev = iwdev->ldev->netdev;
 	if (netdev != event_netdev)
 		return NOTIFY_DONE;
 		if (!iwhdl)
 			return NOTIFY_DONE;
 		iwdev = &iwhdl->device;
+		if (iwdev->init_state < INET_NOTIFIER)
+			return NOTIFY_DONE;
 		p = (__be32 *)neigh->primary_key;
 		i40iw_copy_ip_ntohl(local_ipaddr, p);
 		if (neigh->nud_state & NUD_VALID) {

drivers/infiniband/hw/ocrdma/ocrdma_verbs.c+1−1

@@ -372,7 +372,7 @@ static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id, · 371 unmodified lines
372	return 0;	372	return 0;
373	}	373	}
374		374
375	static u8 ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,	375	static int ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
376	bool dpp_pool)	376	bool dpp_pool)
377	{	377	{
378	int status;	378	int status;

drivers/infiniband/hw/qib/qib_iba7322.c+1−1

@@ -7068,7 +7068,7 @@ static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, · 7067 unmodified lines
7068	unsigned long flags;	7068	unsigned long flags;
7069		7069
7070	while (wait) {	7070	while (wait) {
7071	unsigned long shadow;	7071	unsigned long shadow = 0;
7072	int cstart, previ = -1;	7072	int cstart, previ = -1;
7073		7073
7074	/*	7074	/*

drivers/infiniband/hw/vmw_pvrdma/pvrdma.h+3−0

@@ -69,6 +69,9 @@ · 68 unmodified lines
69	*/	69	*/
70	#define PCI_DEVICE_ID_VMWARE_PVRDMA 0x0820	70	#define PCI_DEVICE_ID_VMWARE_PVRDMA 0x0820
71		71
		72	#define PVRDMA_NUM_RING_PAGES 4
		73	#define PVRDMA_QP_NUM_HEADER_PAGES 1
		74
72	struct pvrdma_dev;	75	struct pvrdma_dev;
73		76
74	struct pvrdma_page_dir {	77	struct pvrdma_page_dir {

drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h+1−1

@@ -132,7 +132,7 @@ enum pvrdma_pci_resource { · 131 unmodified lines
132		132
133	enum pvrdma_device_ctl {	133	enum pvrdma_device_ctl {
134	PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */	134	PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
135	PVRDMA_DEVICE_CTL_QUIESCE, /* Quiesce device. */	135	PVRDMA_DEVICE_CTL_UNQUIESCE, /* Unquiesce device. */
136	PVRDMA_DEVICE_CTL_RESET, /* Reset device. */	136	PVRDMA_DEVICE_CTL_RESET, /* Reset device. */
137	};	137	};
138		138

drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c+13−4

 #include "pvrdma.h"
 #define DRV_NAME	"vmw_pvrdma"
-#define DRV_VERSION	"1.0.0.0-k"
+#define DRV_VERSION	"1.0.1.0-k"
 static DEFINE_MUTEX(pvrdma_device_list_lock);
 static LIST_HEAD(pvrdma_device_list);
 		pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 		break;
 	case NETDEV_UP:
-		pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
+		pvrdma_write_reg(dev, PVRDMA_REG_CTL,
+				 PVRDMA_DEVICE_CTL_UNQUIESCE);
+		mb();
+		if (pvrdma_read_reg(dev, PVRDMA_REG_ERR))
+			dev_err(&dev->pdev->dev,
+				"failed to activate device during link up\n");
+		else
+			pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 		break;
 	default:
 		dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
 	dev->dsr->resp_slot_dma = (u64)slot_dma;
 	/* Async event ring */
-	dev->dsr->async_ring_pages.num_pages = 4;
+	dev->dsr->async_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
 	ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
 				   dev->dsr->async_ring_pages.num_pages, true);
 	if (ret)
 	dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
 	/* CQ notification ring */
-	dev->dsr->cq_ring_pages.num_pages = 4;
+	dev->dsr->cq_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
 	ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
 				   dev->dsr->cq_ring_pages.num_pages, true);
 	if (ret)

drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c+18−24

 					     sizeof(struct pvrdma_sge) *
 					     qp->sq.max_sg);
 	/* Note: one extra page for the header. */
-	qp->npages_send = 1 + (qp->sq.wqe_cnt * qp->sq.wqe_size +
+	qp->npages_send = PVRDMA_QP_NUM_HEADER_PAGES +
-			       PAGE_SIZE - 1) / PAGE_SIZE;
+			  (qp->sq.wqe_cnt * qp->sq.wqe_size + PAGE_SIZE - 1) /
+								PAGE_SIZE;
 	return 0;
 }
 			qp->npages = qp->npages_send + qp->npages_recv;
 			/* Skip header page. */
-			qp->sq.offset = PAGE_SIZE;
+			qp->sq.offset = PVRDMA_QP_NUM_HEADER_PAGES * PAGE_SIZE;
 			/* Recv queue pages are after send pages. */
 			qp->rq.offset = qp->npages_send * PAGE_SIZE;
 	cmd->qp_type = ib_qp_type_to_pvrdma(init_attr->qp_type);
 	cmd->access_flags = IB_ACCESS_LOCAL_WRITE;
 	cmd->total_chunks = qp->npages;
-	cmd->send_chunks = qp->npages_send - 1;
+	cmd->send_chunks = qp->npages_send - PVRDMA_QP_NUM_HEADER_PAGES;
 	cmd->pdir_dma = qp->pdir.dir_dma;
 	dev_dbg(&dev->pdev->dev, "create queuepair with %d, %d, %d, %d\n",
 	return ret;
 }
-static inline void *get_sq_wqe(struct pvrdma_qp *qp, int n)
+static inline void *get_sq_wqe(struct pvrdma_qp *qp, unsigned int n)
 {
 	return pvrdma_page_dir_get_ptr(&qp->pdir,
 				       qp->sq.offset + n * qp->sq.wqe_size);
 }
-static inline void *get_rq_wqe(struct pvrdma_qp *qp, int n)
+static inline void *get_rq_wqe(struct pvrdma_qp *qp, unsigned int n)
 {
 	return pvrdma_page_dir_get_ptr(&qp->pdir,
 				       qp->rq.offset + n * qp->rq.wqe_size);
 	unsigned long flags;
 	struct pvrdma_sq_wqe_hdr *wqe_hdr;
 	struct pvrdma_sge *sge;
-	int i, index;
+	int i, ret;
-	int nreq;
-	int ret;
 	/*
 	 * In states lower than RTS, we can fail immediately. In other states,
 	spin_lock_irqsave(&qp->sq.lock, flags);
-	index = pvrdma_idx(&qp->sq.ring->prod_tail, qp->sq.wqe_cnt);
+	while (wr) {
-	for (nreq = 0; wr; nreq++, wr = wr->next) {
+		unsigned int tail = 0;
-		unsigned int tail;
 		if (unlikely(!pvrdma_idx_ring_has_space(
 				qp->sq.ring, qp->sq.wqe_cnt, &tail))) {
 			}
 		}
-		wqe_hdr = (struct pvrdma_sq_wqe_hdr *)get_sq_wqe(qp, index);
+		wqe_hdr = (struct pvrdma_sq_wqe_hdr *)get_sq_wqe(qp, tail);
 		memset(wqe_hdr, 0, sizeof(*wqe_hdr));
 		wqe_hdr->wr_id = wr->wr_id;
 		wqe_hdr->num_sge = wr->num_sge;
 		/* Make sure wqe is written before index update */
 		smp_wmb();
-		index++;
-		if (unlikely(index >= qp->sq.wqe_cnt))
-			index = 0;
 		/* Update shared sq ring */
 		pvrdma_idx_ring_inc(&qp->sq.ring->prod_tail,
 				    qp->sq.wqe_cnt);
+		wr = wr->next;
 	}
 	ret = 0;
 	struct pvrdma_qp *qp = to_vqp(ibqp);
 	struct pvrdma_rq_wqe_hdr *wqe_hdr;
 	struct pvrdma_sge *sge;
-	int index, nreq;
 	int ret = 0;
 	int i;
 	spin_lock_irqsave(&qp->rq.lock, flags);
-	index = pvrdma_idx(&qp->rq.ring->prod_tail, qp->rq.wqe_cnt);
+	while (wr) {
-	for (nreq = 0; wr; nreq++, wr = wr->next) {
+		unsigned int tail = 0;
-		unsigned int tail;
 		if (unlikely(wr->num_sge > qp->rq.max_sg ||
 			     wr->num_sge < 0)) {
 			goto out;
 		}
-		wqe_hdr = (struct pvrdma_rq_wqe_hdr *)get_rq_wqe(qp, index);
+		wqe_hdr = (struct pvrdma_rq_wqe_hdr *)get_rq_wqe(qp, tail);
 		wqe_hdr->wr_id = wr->wr_id;
 		wqe_hdr->num_sge = wr->num_sge;
 		wqe_hdr->total_len = 0;
 		/* Make sure wqe is written before index update */
 		smp_wmb();
-		index++;
-		if (unlikely(index >= qp->rq.wqe_cnt))
-			index = 0;
 		/* Update shared rq ring */
 		pvrdma_idx_ring_inc(&qp->rq.ring->prod_tail,
 				    qp->rq.wqe_cnt);
+		wr = wr->next;
 	}
 	spin_unlock_irqrestore(&qp->rq.lock, flags);

drivers/infiniband/sw/rdmavt/mmap.c+2−2

@@ -170,9 +170,9 @@ struct rvt_mmap_info rvt_create_mmap_info(struct rvt_dev_info rdi, · 169 unmodified lines
170		170
171	spin_lock_irq(&rdi->mmap_offset_lock);	171	spin_lock_irq(&rdi->mmap_offset_lock);
172	if (rdi->mmap_offset == 0)	172	if (rdi->mmap_offset == 0)
173	rdi->mmap_offset = PAGE_SIZE;	173	rdi->mmap_offset = ALIGN(PAGE_SIZE, SHMLBA);
174	ip->offset = rdi->mmap_offset;	174	ip->offset = rdi->mmap_offset;
175	rdi->mmap_offset += size;	175	rdi->mmap_offset += ALIGN(size, SHMLBA);
176	spin_unlock_irq(&rdi->mmap_offset_lock);	176	spin_unlock_irq(&rdi->mmap_offset_lock);
177		177
178	INIT_LIST_HEAD(&ip->pending_mmaps);	178	INIT_LIST_HEAD(&ip->pending_mmaps);

drivers/infiniband/sw/rxe/Kconfig+1−1

@@ -22,4 +22,4 @@ config RDMA_RXE · 21 unmodified lines
22	To configure and work with soft-RoCE driver please use the	22	To configure and work with soft-RoCE driver please use the
23	following wiki page under "configure Soft-RoCE (RXE)" section:	23	following wiki page under "configure Soft-RoCE (RXE)" section:
24		24
25	https://github.com/SoftRoCE/rxe-dev/wiki/rxe-dev:-Home	25	https://github.com/linux-rdma/rdma-core/blob/master/Documentation/rxe.md

drivers/infiniband/sw/rxe/rxe_mmap.c+2−2

@@ -156,10 +156,10 @@ struct rxe_mmap_info rxe_create_mmap_info(struct rxe_dev rxe, · 155 unmodified lines
156	spin_lock_bh(&rxe->mmap_offset_lock);	156	spin_lock_bh(&rxe->mmap_offset_lock);
157		157
158	if (rxe->mmap_offset == 0)	158	if (rxe->mmap_offset == 0)
159	rxe->mmap_offset = PAGE_SIZE;	159	rxe->mmap_offset = ALIGN(PAGE_SIZE, SHMLBA);
160		160
161	ip->info.offset = rxe->mmap_offset;	161	ip->info.offset = rxe->mmap_offset;
162	rxe->mmap_offset += size;	162	rxe->mmap_offset += ALIGN(size, SHMLBA);
163		163
164	spin_unlock_bh(&rxe->mmap_offset_lock);	164	spin_unlock_bh(&rxe->mmap_offset_lock);
165		165

drivers/infiniband/sw/rxe/rxe_req.c+1−1

 	ret = rxe_xmit_packet(to_rdev(qp->ibqp.device), qp, &pkt, skb);
 	if (ret) {
 		qp->need_req_skb = 1;
-		kfree_skb(skb);
 		rollback_state(wqe, qp, &rollback_wqe, rollback_psn);
 		if (ret == -EAGAIN) {
+			kfree_skb(skb);
 			rxe_run_task(&qp->req.task, 1);
 			goto exit;
 		}

drivers/infiniband/sw/rxe/rxe_resp.c+4−5

 		WARN_ON_ONCE(1);
 	}
-	/* We successfully processed this new request. */
-	qp->resp.msn++;
 	/* next expected psn, read handles this separately */
 	qp->resp.psn = (pkt->psn + 1) & BTH_PSN_MASK;
 	qp->resp.opcode = pkt->opcode;
 	qp->resp.status = IB_WC_SUCCESS;
-	if (pkt->mask & RXE_COMP_MASK)
+	if (pkt->mask & RXE_COMP_MASK) {
+		/* We successfully processed this new request. */
+		qp->resp.msn++;
 		return RESPST_COMPLETE;
-	else if (qp_type(qp) == IB_QPT_RC)
+	} else if (qp_type(qp) == IB_QPT_RC)
 		return RESPST_ACKNOWLEDGE;
 	else
 		return RESPST_CLEANUP;

drivers/infiniband/ulp/iser/iscsi_iser.h+2−0

 	struct list_head		  list;
 	struct iser_reg_resources	  rsc;
 	struct iser_pi_context		 *pi_ctx;
+	struct list_head                  all_list;
 };
 /**
 	struct list_head        list;
 	spinlock_t              lock;
 	int                     size;
+	struct list_head        all_list;
 };
 /**

drivers/infiniband/ulp/iser/iser_verbs.c+5−3

 	int i, ret;
 	INIT_LIST_HEAD(&fr_pool->list);
+	INIT_LIST_HEAD(&fr_pool->all_list);
 	spin_lock_init(&fr_pool->lock);
 	fr_pool->size = 0;
 	for (i = 0; i < cmds_max; i++) {
 		}
 		list_add_tail(&desc->list, &fr_pool->list);
+		list_add_tail(&desc->all_list, &fr_pool->all_list);
 		fr_pool->size++;
 	}
 	struct iser_fr_desc *desc, *tmp;
 	int i = 0;
-	if (list_empty(&fr_pool->list))
+	if (list_empty(&fr_pool->all_list))
 		return;
 	iser_info("freeing conn %p fr pool\n", ib_conn);
-	list_for_each_entry_safe(desc, tmp, &fr_pool->list, list) {
+	list_for_each_entry_safe(desc, tmp, &fr_pool->all_list, all_list) {
-		list_del(&desc->list);
+		list_del(&desc->all_list);
 		iser_free_reg_res(&desc->rsc);
 		if (desc->pi_ctx)
 			iser_free_pi_ctx(desc->pi_ctx);

drivers/input/joystick/iforce/iforce-usb.c+3−0

@@ -141,6 +141,9 @@ static int iforce_usb_probe(struct usb_interface *intf, · 140 unmodified lines
141		141
142	interface = intf->cur_altsetting;	142	interface = intf->cur_altsetting;
143		143
		144	if (interface->desc.bNumEndpoints < 2)
		145	return -ENODEV;
		146
144	epirq = &interface->endpoint[0].desc;	147	epirq = &interface->endpoint[0].desc;
145	epout = &interface->endpoint[1].desc;	148	epout = &interface->endpoint[1].desc;
146		149

drivers/input/misc/cm109.c+4−0

@@ -700,6 +700,10 @@ static int cm109_usb_probe(struct usb_interface *intf, · 699 unmodified lines
700	int error = -ENOMEM;	700	int error = -ENOMEM;
701		701
702	interface = intf->cur_altsetting;	702	interface = intf->cur_altsetting;
		703
		704	if (interface->desc.bNumEndpoints < 1)
		705	return -ENODEV;
		706
703	endpoint = &interface->endpoint[0].desc;	707	endpoint = &interface->endpoint[0].desc;
704		708
705	if (!usb_endpoint_is_int_in(endpoint))	709	if (!usb_endpoint_is_int_in(endpoint))

drivers/input/misc/ims-pcu.c+4−0

@@ -1667,6 +1667,10 @@ static int ims_pcu_parse_cdc_data(struct usb_interface intf, struct ims_pcu pc · 1666 unmodified lines
1667	return -EINVAL;	1667	return -EINVAL;
1668		1668
1669	alt = pcu->ctrl_intf->cur_altsetting;	1669	alt = pcu->ctrl_intf->cur_altsetting;
		1670
		1671	if (alt->desc.bNumEndpoints < 1)
		1672	return -ENODEV;
		1673
1670	pcu->ep_ctrl = &alt->endpoint[0].desc;	1674	pcu->ep_ctrl = &alt->endpoint[0].desc;
1671	pcu->max_ctrl_size = usb_endpoint_maxp(pcu->ep_ctrl);	1675	pcu->max_ctrl_size = usb_endpoint_maxp(pcu->ep_ctrl);
1672		1676

drivers/input/misc/yealink.c+4−0

@@ -875,6 +875,10 @@ static int usb_probe(struct usb_interface intf, const struct usb_device_id id) · 874 unmodified lines
875	int ret, pipe, i;	875	int ret, pipe, i;
876		876
877	interface = intf->cur_altsetting;	877	interface = intf->cur_altsetting;
		878
		879	if (interface->desc.bNumEndpoints < 1)
		880	return -ENODEV;
		881
878	endpoint = &interface->endpoint[0].desc;	882	endpoint = &interface->endpoint[0].desc;
879	if (!usb_endpoint_is_int_in(endpoint))	883	if (!usb_endpoint_is_int_in(endpoint))
880	return -ENODEV;	884	return -ENODEV;

drivers/input/mouse/alps.c+52−20

 	/* handle buttons */
 	if (pkt_id == SS4_PACKET_ID_STICK) {
 		f->ts_left = !!(SS4_BTN_V2(p) & 0x01);
-		if (!(priv->flags & ALPS_BUTTONPAD)) {
+		f->ts_right = !!(SS4_BTN_V2(p) & 0x02);
-			f->ts_right = !!(SS4_BTN_V2(p) & 0x02);
+		f->ts_middle = !!(SS4_BTN_V2(p) & 0x04);
-			f->ts_middle = !!(SS4_BTN_V2(p) & 0x04);
-		}
 	} else {
 		f->left = !!(SS4_BTN_V2(p) & 0x01);
 		if (!(priv->flags & ALPS_BUTTONPAD)) {
 	int num_y_electrode;
 	int x_pitch, y_pitch, x_phys, y_phys;
-	num_x_electrode = SS4_NUMSENSOR_XOFFSET + (otp[1][0] & 0x0F);
+	if (IS_SS4PLUS_DEV(priv->dev_id)) {
-	num_y_electrode = SS4_NUMSENSOR_YOFFSET + ((otp[1][0] >> 4) & 0x0F);
+		num_x_electrode =
+			SS4PLUS_NUMSENSOR_XOFFSET + (otp[0][2] & 0x0F);
+		num_y_electrode =
+			SS4PLUS_NUMSENSOR_YOFFSET + ((otp[0][2] >> 4) & 0x0F);
+		priv->x_max =
+			(num_x_electrode - 1) * SS4PLUS_COUNT_PER_ELECTRODE;
+		priv->y_max =
+			(num_y_electrode - 1) * SS4PLUS_COUNT_PER_ELECTRODE;
-	priv->x_max = (num_x_electrode - 1) * SS4_COUNT_PER_ELECTRODE;
+		x_pitch = (otp[0][1] & 0x0F) + SS4PLUS_MIN_PITCH_MM;
-	priv->y_max = (num_y_electrode - 1) * SS4_COUNT_PER_ELECTRODE;
+		y_pitch = ((otp[0][1] >> 4) & 0x0F) + SS4PLUS_MIN_PITCH_MM;
-	x_pitch = ((otp[1][2] >> 2) & 0x07) + SS4_MIN_PITCH_MM;
+	} else {
-	y_pitch = ((otp[1][2] >> 5) & 0x07) + SS4_MIN_PITCH_MM;
+		num_x_electrode =
+			SS4_NUMSENSOR_XOFFSET + (otp[1][0] & 0x0F);
+		num_y_electrode =
+			SS4_NUMSENSOR_YOFFSET + ((otp[1][0] >> 4) & 0x0F);
+		priv->x_max =
+			(num_x_electrode - 1) * SS4_COUNT_PER_ELECTRODE;
+		priv->y_max =
+			(num_y_electrode - 1) * SS4_COUNT_PER_ELECTRODE;
+		x_pitch = ((otp[1][2] >> 2) & 0x07) + SS4_MIN_PITCH_MM;
+		y_pitch = ((otp[1][2] >> 5) & 0x07) + SS4_MIN_PITCH_MM;
+	}
 	x_phys = x_pitch * (num_x_electrode - 1); /* In 0.1 mm units */
 	y_phys = y_pitch * (num_y_electrode - 1); /* In 0.1 mm units */
 {
 	unsigned char is_btnless;
-	is_btnless = (otp[1][1] >> 3) & 0x01;
+	if (IS_SS4PLUS_DEV(priv->dev_id))
+		is_btnless = (otp[1][0] >> 1) & 0x01;
+	else
+		is_btnless = (otp[1][1] >> 3) & 0x01;
 	if (is_btnless)
 		priv->flags |= ALPS_BUTTONPAD;
 	return 0;
 }
+static int alps_update_dual_info_ss4_v2(unsigned char otp[][4],
+				       struct alps_data *priv)
+{
+	bool is_dual = false;
+	if (IS_SS4PLUS_DEV(priv->dev_id))
+		is_dual = (otp[0][0] >> 4) & 0x01;
+	if (is_dual)
+		priv->flags |= ALPS_DUALPOINT |
+					ALPS_DUALPOINT_WITH_PRESSURE;
+	return 0;
+}
 static int alps_set_defaults_ss4_v2(struct psmouse *psmouse,
 				    struct alps_data *priv)
 {
 	alps_update_btn_info_ss4_v2(otp, priv);
+	alps_update_dual_info_ss4_v2(otp, priv);
 	return 0;
 }
 		if (alps_set_defaults_ss4_v2(psmouse, priv))
 			return -EIO;
-		if (priv->fw_ver[1] == 0x1)
-			priv->flags |= ALPS_DUALPOINT |
-					ALPS_DUALPOINT_WITH_PRESSURE;
 		break;
 	}
 			   ec[2] >= 0x90 && ec[2] <= 0x9d) {
 			protocol = &alps_v3_protocol_data;
 		} else if (e7[0] == 0x73 && e7[1] == 0x03 &&
-			   e7[2] == 0x14 && ec[1] == 0x02) {
+			   (e7[2] == 0x14 || e7[2] == 0x28)) {
-			protocol = &alps_v8_protocol_data;
-		} else if (e7[0] == 0x73 && e7[1] == 0x03 &&
-			   e7[2] == 0x28 && ec[1] == 0x01) {
 			protocol = &alps_v8_protocol_data;
 		} else {
 			psmouse_dbg(psmouse,
 	}
 	if (priv) {
-		/* Save the Firmware version */
+		/* Save Device ID and Firmware version */
+		memcpy(priv->dev_id, e7, 3);
 		memcpy(priv->fw_ver, ec, 3);
 		error = alps_set_protocol(psmouse, priv, protocol);
 		if (error)

drivers/input/mouse/alps.h+11−0

 #define SS4_MASK_NORMAL_BUTTONS		0x07
+#define SS4PLUS_COUNT_PER_ELECTRODE	128
+#define SS4PLUS_NUMSENSOR_XOFFSET	16
+#define SS4PLUS_NUMSENSOR_YOFFSET	5
+#define SS4PLUS_MIN_PITCH_MM		37
+#define IS_SS4PLUS_DEV(_b)	(((_b[0]) == 0x73) &&	\
+				 ((_b[1]) == 0x03) &&	\
+				 ((_b[2]) == 0x28)		\
+				)
 #define SS4_IS_IDLE_V2(_b)	(((_b[0]) == 0x18) &&		\
 				 ((_b[1]) == 0x10) &&		\
 				 ((_b[2]) == 0x00) &&		\
 	int addr_command;
 	u16 proto_version;
 	u8 byte0, mask0;
+	u8 dev_id[3];
 	u8 fw_ver[3];
 	int flags;
 	int x_max;

drivers/input/mouse/elan_i2c_core.c+11−9

@@ -218,17 +218,19 @@ static int elan_query_product(struct elan_tp_data *data) · 217 unmodified lines
218		218
219	static int elan_check_ASUS_special_fw(struct elan_tp_data *data)	219	static int elan_check_ASUS_special_fw(struct elan_tp_data *data)
220	{	220	{
221	if (data->ic_type != 0x0E)	221	if (data->ic_type == 0x0E) {
222	return false;	222	switch (data->product_id) {
223		223	case 0x05 ... 0x07:
224	switch (data->product_id) {	224	case 0x09:
225	case 0x05 ... 0x07:	225	case 0x13:
226	case 0x09:	226	return true;
227	case 0x13:	227	}
		228	} else if (data->ic_type == 0x08 && data->product_id == 0x26) {
		229	/* ASUS EeeBook X205TA */
228	return true;	230	return true;
229	default:
230	return false;
231	}	231	}
		232
		233	return false;
232	}	234	}
233		235
234	static int __elan_initialize(struct elan_tp_data *data)	236	static int __elan_initialize(struct elan_tp_data *data)

drivers/input/rmi4/rmi_f30.c+4−0

 				rmi_get_platform_data(fn->rmi_dev);
 	int error;
+	/* can happen if f30_data.disable is set */
+	if (!f30)
+		return 0;
 	if (pdata->f30_data.trackstick_buttons) {
 		/* Try [re-]establish link to F03. */
 		f30->f03 = rmi_find_function(fn->rmi_dev, 0x03);

drivers/input/serio/i8042-x86ia64io.h+14−0

@@ -119,6 +119,13 @@ static const struct dmi_system_id __initconst i8042_dmi_noloop_table[] = { · 118 unmodified lines
119	DMI_MATCH(DMI_PRODUCT_VERSION, "DL760"),	119	DMI_MATCH(DMI_PRODUCT_VERSION, "DL760"),
120	},	120	},
121	},	121	},
		122	{
		123	/* Dell Embedded Box PC 3000 */
		124	.matches = {
		125	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		126	DMI_MATCH(DMI_PRODUCT_NAME, "Embedded Box PC 3000"),
		127	},
		128	},
122	{	129	{
123	/* OQO Model 01 */	130	/* OQO Model 01 */
124	.matches = {	131	.matches = {
@@ -513,6 +520,13 @@ static const struct dmi_system_id __initconst i8042_dmi_nomux_table[] = { · 388 unmodified lines
513	DMI_MATCH(DMI_PRODUCT_NAME, "IC4I"),	520	DMI_MATCH(DMI_PRODUCT_NAME, "IC4I"),
514	},	521	},
515	},	522	},
		523	{
		524	/* TUXEDO BU1406 */
		525	.matches = {
		526	DMI_MATCH(DMI_SYS_VENDOR, "Notebook"),
		527	DMI_MATCH(DMI_PRODUCT_NAME, "N24_25BU"),
		528	},
		529	},
516	{ }	530	{ }
517	};	531	};
518		532

drivers/input/tablet/hanwang.c+3−0

@@ -340,6 +340,9 @@ static int hanwang_probe(struct usb_interface *intf, const struct usb_device_id · 339 unmodified lines
340	int error;	340	int error;
341	int i;	341	int i;
342		342
		343	if (intf->cur_altsetting->desc.bNumEndpoints < 1)
		344	return -ENODEV;
		345
343	hanwang = kzalloc(sizeof(struct hanwang), GFP_KERNEL);	346	hanwang = kzalloc(sizeof(struct hanwang), GFP_KERNEL);
344	input_dev = input_allocate_device();	347	input_dev = input_allocate_device();
345	if (!hanwang \|\| !input_dev) {	348	if (!hanwang \|\| !input_dev) {

drivers/input/tablet/kbtab.c+3−0

@@ -122,6 +122,9 @@ static int kbtab_probe(struct usb_interface intf, const struct usb_device_id i · 121 unmodified lines
122	struct input_dev *input_dev;	122	struct input_dev *input_dev;
123	int error = -ENOMEM;	123	int error = -ENOMEM;
124		124
		125	if (intf->cur_altsetting->desc.bNumEndpoints < 1)
		126	return -ENODEV;
		127
125	kbtab = kzalloc(sizeof(struct kbtab), GFP_KERNEL);	128	kbtab = kzalloc(sizeof(struct kbtab), GFP_KERNEL);
126	input_dev = input_allocate_device();	129	input_dev = input_allocate_device();
127	if (!kbtab \|\| !input_dev)	130	if (!kbtab \|\| !input_dev)

drivers/input/touchscreen/sur40.c+3−0

@@ -527,6 +527,9 @@ static int sur40_probe(struct usb_interface *interface, · 526 unmodified lines
527	if (iface_desc->desc.bInterfaceClass != 0xFF)	527	if (iface_desc->desc.bInterfaceClass != 0xFF)
528	return -ENODEV;	528	return -ENODEV;
529		529
		530	if (iface_desc->desc.bNumEndpoints < 5)
		531	return -ENODEV;
		532
530	/* Use endpoint #4 (0x86). */	533	/* Use endpoint #4 (0x86). */
531	endpoint = &iface_desc->endpoint[4].desc;	534	endpoint = &iface_desc->endpoint[4].desc;
532	if (endpoint->bEndpointAddress != TOUCH_ENDPOINT)	535	if (endpoint->bEndpointAddress != TOUCH_ENDPOINT)

drivers/iommu/amd_iommu.c+1−1

@@ -3202,7 +3202,7 @@ static void amd_iommu_get_resv_regions(struct device *dev, · 3201 unmodified lines
3202		3202
3203	region = iommu_alloc_resv_region(MSI_RANGE_START,	3203	region = iommu_alloc_resv_region(MSI_RANGE_START,
3204	MSI_RANGE_END - MSI_RANGE_START + 1,	3204	MSI_RANGE_END - MSI_RANGE_START + 1,
3205	0, IOMMU_RESV_RESERVED);	3205	0, IOMMU_RESV_MSI);
3206	if (!region)	3206	if (!region)
3207	return;	3207	return;
3208	list_add_tail(&region->list, head);	3208	list_add_tail(&region->list, head);

drivers/iommu/arm-smmu-v3.c+1−1

@@ -1888,7 +1888,7 @@ static void arm_smmu_get_resv_regions(struct device *dev, · 1887 unmodified lines
1888	int prot = IOMMU_WRITE \| IOMMU_NOEXEC \| IOMMU_MMIO;	1888	int prot = IOMMU_WRITE \| IOMMU_NOEXEC \| IOMMU_MMIO;
1889		1889
1890	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,	1890	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
1891	prot, IOMMU_RESV_MSI);	1891	prot, IOMMU_RESV_SW_MSI);
1892	if (!region)	1892	if (!region)
1893	return;	1893	return;
1894		1894

drivers/iommu/arm-smmu.c+1−1

@@ -1608,7 +1608,7 @@ static void arm_smmu_get_resv_regions(struct device *dev, · 1607 unmodified lines
1608	int prot = IOMMU_WRITE \| IOMMU_NOEXEC \| IOMMU_MMIO;	1608	int prot = IOMMU_WRITE \| IOMMU_NOEXEC \| IOMMU_MMIO;
1609		1609
1610	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,	1610	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
1611	prot, IOMMU_RESV_MSI);	1611	prot, IOMMU_RESV_SW_MSI);
1612	if (!region)	1612	if (!region)
1613	return;	1613	return;
1614		1614

drivers/iommu/exynos-iommu.c+7−1

 	spin_lock_irqsave(&data->lock, flags);
 	if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
 		clk_enable(data->clk_master);
-		__sysmmu_tlb_invalidate_entry(data, iova, 1);
+		if (sysmmu_block(data)) {
+			if (data->version >= MAKE_MMU_VER(5, 0))
+				__sysmmu_tlb_invalidate(data);
+			else
+				__sysmmu_tlb_invalidate_entry(data, iova, 1);
+			sysmmu_unblock(data);
+		}
 		clk_disable(data->clk_master);
 	}
 	spin_unlock_irqrestore(&data->lock, flags);

drivers/iommu/intel-iommu.c+2−2

@@ -916,7 +916,7 @@ static struct intel_iommu device_to_iommu(struct device dev, u8 bus, u8 devf · 915 unmodified lines
916	* which we used for the IOMMU lookup. Strictly speaking	916	* which we used for the IOMMU lookup. Strictly speaking
917	* we could do this for all PCI devices; we only need to	917	* we could do this for all PCI devices; we only need to
918	* get the BDF# from the scope table for ACPI matches. */	918	* get the BDF# from the scope table for ACPI matches. */
919	if (pdev->is_virtfn)	919	if (pdev && pdev->is_virtfn)
920	goto got_pdev;	920	goto got_pdev;
921		921
922	*bus = drhd->devices[i].bus;	922	*bus = drhd->devices[i].bus;
@@ -5249,7 +5249,7 @@ static void intel_iommu_get_resv_regions(struct device *device, · 4326 unmodified lines
5249		5249
5250	reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,	5250	reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,
5251	IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,	5251	IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,
5252	0, IOMMU_RESV_RESERVED);	5252	0, IOMMU_RESV_MSI);
5253	if (!reg)	5253	if (!reg)
5254	return;	5254	return;
5255	list_add_tail(&reg->list, head);	5255	list_add_tail(&reg->list, head);

drivers/iommu/io-pgtable-arm-v7s.c+5−1

 			pte |= ARM_V7S_ATTR_NS_TABLE;
 		__arm_v7s_set_pte(ptep, pte, 1, cfg);
-	} else {
+	} else if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
 		cptep = iopte_deref(pte, lvl);
+	} else {
+		/* We require an unmap first */
+		WARN_ON(!selftest_running);
+		return -EEXIST;
 	}
 	/* Rinse, repeat */

drivers/iommu/io-pgtable-arm.c+5−1

 		if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
 			pte |= ARM_LPAE_PTE_NSTABLE;
 		__arm_lpae_set_pte(ptep, pte, cfg);
-	} else {
+	} else if (!iopte_leaf(pte, lvl)) {
 		cptep = iopte_deref(pte, data);
+	} else {
+		/* We require an unmap first */
+		WARN_ON(!selftest_running);
+		return -EEXIST;
 	}
 	/* Rinse, repeat */

drivers/iommu/iommu.c+3−2

 	[IOMMU_RESV_DIRECT]	= "direct",
 	[IOMMU_RESV_RESERVED]	= "reserved",
 	[IOMMU_RESV_MSI]	= "msi",
+	[IOMMU_RESV_SW_MSI]	= "msi",
 };
 #define IOMMU_GROUP_ATTR(_name, _mode, _show, _store)		\
 }
 struct iommu_resv_region *iommu_alloc_resv_region(phys_addr_t start,
-						  size_t length,
+						  size_t length, int prot,
-						  int prot, int type)
+						  enum iommu_resv_type type)
 {
 	struct iommu_resv_region *region;

drivers/isdn/gigaset/bas-gigaset.c+3−0

@@ -2317,6 +2317,9 @@ static int gigaset_probe(struct usb_interface *interface, · 2316 unmodified lines
2317	return -ENODEV;	2317	return -ENODEV;
2318	}	2318	}
2319		2319
		2320	if (hostif->desc.bNumEndpoints < 1)
		2321	return -ENODEV;
		2322
2320	dev_info(&udev->dev,	2323	dev_info(&udev->dev,
2321	"%s: Device matched (Vendor: 0x%x, Product: 0x%x)\n",	2324	"%s: Device matched (Vendor: 0x%x, Product: 0x%x)\n",
2322	__func__, le16_to_cpu(udev->descriptor.idVendor),	2325	__func__, le16_to_cpu(udev->descriptor.idVendor),

drivers/macintosh/macio_asic.c+1−0

@@ -392,6 +392,7 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip, · 391 unmodified lines
392	* To get all the fields, copy all archdata	392	* To get all the fields, copy all archdata
393	*/	393	*/
394	dev->ofdev.dev.archdata = chip->lbus.pdev->dev.archdata;	394	dev->ofdev.dev.archdata = chip->lbus.pdev->dev.archdata;
		395	dev->ofdev.dev.dma_ops = chip->lbus.pdev->dev.dma_ops;
395	#endif /* CONFIG_PCI */	396	#endif /* CONFIG_PCI */
396		397
397	#ifdef DEBUG	398	#ifdef DEBUG

drivers/md/dm.c+16−13

@@ -989,26 +989,29 @@ static void flush_current_bio_list(struct blk_plug_cb *cb, bool from_schedule) · 988 unmodified lines
989	struct dm_offload *o = container_of(cb, struct dm_offload, cb);	989	struct dm_offload *o = container_of(cb, struct dm_offload, cb);
990	struct bio_list list;	990	struct bio_list list;
991	struct bio *bio;	991	struct bio *bio;
		992	int i;
992		993
993	INIT_LIST_HEAD(&o->cb.list);	994	INIT_LIST_HEAD(&o->cb.list);
994		995
995	if (unlikely(!current->bio_list))	996	if (unlikely(!current->bio_list))
996	return;	997	return;
997		998
998	list = *current->bio_list;	999	for (i = 0; i < 2; i++) {
999	bio_list_init(current->bio_list);	1000	list = current->bio_list[i];
1000		1001	bio_list_init(&current->bio_list[i]);
1001	while ((bio = bio_list_pop(&list))) {	1002
1002	struct bio_set *bs = bio->bi_pool;	1003	while ((bio = bio_list_pop(&list))) {
1003	if (unlikely(!bs) \|\| bs == fs_bio_set) {	1004	struct bio_set *bs = bio->bi_pool;
1004	bio_list_add(current->bio_list, bio);	1005	if (unlikely(!bs) \|\| bs == fs_bio_set) {
1005	continue;	1006	bio_list_add(&current->bio_list[i], bio);
		1007	continue;
		1008	}
		1009
		1010	spin_lock(&bs->rescue_lock);
		1011	bio_list_add(&bs->rescue_list, bio);
		1012	queue_work(bs->rescue_workqueue, &bs->rescue_work);
		1013	spin_unlock(&bs->rescue_lock);
1006	}	1014	}
1007
1008	spin_lock(&bs->rescue_lock);
1009	bio_list_add(&bs->rescue_list, bio);
1010	queue_work(bs->rescue_workqueue, &bs->rescue_work);
1011	spin_unlock(&bs->rescue_lock);
1012	}	1015	}
1013	}	1016	}
1014		1017

drivers/md/md-cluster.c+1−1

 		bm_lockres->flags |= DLM_LKF_NOQUEUE;
 		ret = dlm_lock_sync(bm_lockres, DLM_LOCK_PW);
 		if (ret == -EAGAIN) {
-			memset(bm_lockres->lksb.sb_lvbptr, '\0', LVB_SIZE);
 			s = read_resync_info(mddev, bm_lockres);
 			if (s) {
 				pr_info("%s:%d Resync[%llu..%llu] in progress on %d\n",
 	lockres_free(cinfo->bitmap_lockres);
 	unlock_all_bitmaps(mddev);
 	dlm_release_lockspace(cinfo->lockspace, 2);
+	kfree(cinfo);
 	return 0;
 }

drivers/md/md.c+11−16

 }
 EXPORT_SYMBOL(md_flush_request);
-void md_unplug(struct blk_plug_cb *cb, bool from_schedule)
-{
-	struct mddev *mddev = cb->data;
-	md_wakeup_thread(mddev->thread);
-	kfree(cb);
-}
-EXPORT_SYMBOL(md_unplug);
 static inline struct mddev *mddev_get(struct mddev *mddev)
 {
 	atomic_inc(&mddev->active);
 	}
 	sb = page_address(rdev->sb_page);
 	sb->data_size = cpu_to_le64(num_sectors);
-	sb->super_offset = rdev->sb_start;
+	sb->super_offset = cpu_to_le64(rdev->sb_start);
 	sb->sb_csum = calc_sb_1_csum(sb);
 	do {
 		md_super_write(rdev->mddev, rdev, rdev->sb_start, rdev->sb_size,
 	/* Check if any mddev parameters have changed */
 	if ((mddev->dev_sectors != le64_to_cpu(sb->size)) ||
 	    (mddev->reshape_position != le64_to_cpu(sb->reshape_position)) ||
-	    (mddev->layout != le64_to_cpu(sb->layout)) ||
+	    (mddev->layout != le32_to_cpu(sb->layout)) ||
 	    (mddev->raid_disks != le32_to_cpu(sb->raid_disks)) ||
 	    (mddev->chunk_sectors != le32_to_cpu(sb->chunksize)))
 		return true;
 	mddev->layout        = info->layout;
 	mddev->chunk_sectors = info->chunk_size >> 9;
-	mddev->max_disks     = MD_SB_DISKS;
 	if (mddev->persistent) {
-		mddev->flags         = 0;
+		mddev->max_disks = MD_SB_DISKS;
-		mddev->sb_flags         = 0;
+		mddev->flags = 0;
+		mddev->sb_flags = 0;
 	}
 	set_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags);
 			return -ENOSPC;
 	}
 	rv = mddev->pers->resize(mddev, num_sectors);
-	if (!rv)
+	if (!rv) {
-		revalidate_disk(mddev->gendisk);
+		if (mddev->queue) {
+			set_capacity(mddev->gendisk, mddev->array_sectors);
+			revalidate_disk(mddev->gendisk);
+		}
+	}
 	return rv;
 }

drivers/md/md.h+0−6

 extern struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,
 				   struct mddev *mddev);
-extern void md_unplug(struct blk_plug_cb *cb, bool from_schedule);
 extern void md_reload_sb(struct mddev *mddev, int raid_disk);
 extern void md_update_sb(struct mddev *mddev, int force);
 extern void md_kick_rdev_from_array(struct md_rdev * rdev);
 struct md_rdev *md_find_rdev_nr_rcu(struct mddev *mddev, int nr);
-static inline int mddev_check_plugged(struct mddev *mddev)
-{
-	return !!blk_check_plugged(md_unplug, mddev,
-				   sizeof(struct blk_plug_cb));
-}
 static inline void rdev_dec_pending(struct md_rdev *rdev, struct mddev *mddev)
 {

drivers/md/raid1.c+24−5

@@ -1027,7 +1027,7 @@ static int get_unqueued_pending(struct r1conf *conf) · 1026 unmodified lines
1027	static void freeze_array(struct r1conf *conf, int extra)	1027	static void freeze_array(struct r1conf *conf, int extra)
1028	{	1028	{
1029	/* Stop sync I/O and normal I/O and wait for everything to	1029	/* Stop sync I/O and normal I/O and wait for everything to
1030	* go quite.	1030	* go quiet.
1031	* This is called in two situations:	1031	* This is called in two situations:
1032	* 1) management command handlers (reshape, remove disk, quiesce).	1032	* 1) management command handlers (reshape, remove disk, quiesce).
1033	* 2) one normal I/O request failed.	1033	* 2) one normal I/O request failed.
@@ -1587,9 +1587,30 @@ static void raid1_make_request(struct mddev mddev, struct bio bio) · 553 unmodified lines
1587	split = bio;	1587	split = bio;
1588	}	1588	}
1589		1589
1590	if (bio_data_dir(split) == READ)	1590	if (bio_data_dir(split) == READ) {
1591	raid1_read_request(mddev, split);	1591	raid1_read_request(mddev, split);
1592	else	1592
		1593	/*
		1594	* If a bio is splitted, the first part of bio will
		1595	* pass barrier but the bio is queued in
		1596	* current->bio_list (see generic_make_request). If
		1597	* there is a raise_barrier() called here, the second
		1598	* part of bio can't pass barrier. But since the first
		1599	* part bio isn't dispatched to underlaying disks yet,
		1600	* the barrier is never released, hence raise_barrier
		1601	* will alays wait. We have a deadlock.
		1602	* Note, this only happens in read path. For write
		1603	* path, the first part of bio is dispatched in a
		1604	* schedule() call (because of blk plug) or offloaded
		1605	* to raid10d.
		1606	* Quitting from the function immediately can change
		1607	* the bio order queued in bio_list and avoid the deadlock.
		1608	*/
		1609	if (split != bio) {
		1610	generic_make_request(bio);
		1611	break;
		1612	}
		1613	} else
1593	raid1_write_request(mddev, split);	1614	raid1_write_request(mddev, split);
1594	} while (split != bio);	1615	} while (split != bio);
1595	}	1616	}
@@ -3246,8 +3267,6 @@ static int raid1_resize(struct mddev *mddev, sector_t sectors) · 1650 unmodified lines
3246	return ret;	3267	return ret;
3247	}	3268	}
3248	md_set_array_sectors(mddev, newsize);	3269	md_set_array_sectors(mddev, newsize);
3249	set_capacity(mddev->gendisk, mddev->array_sectors);
3250	revalidate_disk(mddev->gendisk);
3251	if (sectors > mddev->dev_sectors &&	3270	if (sectors > mddev->dev_sectors &&
3252	mddev->recovery_cp > mddev->dev_sectors) {	3271	mddev->recovery_cp > mddev->dev_sectors) {
3253	mddev->recovery_cp = mddev->dev_sectors;	3272	mddev->recovery_cp = mddev->dev_sectors;

drivers/md/raid10.c+36−8

 				    !conf->barrier ||
 				    (atomic_read(&conf->nr_pending) &&
 				     current->bio_list &&
-				     !bio_list_empty(current->bio_list)),
+				     (!bio_list_empty(&current->bio_list[0]) ||
+				      !bio_list_empty(&current->bio_list[1]))),
 				    conf->resync_lock);
 		conf->nr_waiting--;
 		if (!conf->nr_waiting)
 			mbio->bi_bdev = (void*)rdev;
 			atomic_inc(&r10_bio->remaining);
+			cb = blk_check_plugged(raid10_unplug, mddev,
+					       sizeof(*plug));
+			if (cb)
+				plug = container_of(cb, struct raid10_plug_cb,
+						    cb);
+			else
+				plug = NULL;
 			spin_lock_irqsave(&conf->device_lock, flags);
-			bio_list_add(&conf->pending_bio_list, mbio);
+			if (plug) {
-			conf->pending_count++;
+				bio_list_add(&plug->pending, mbio);
+				plug->pending_cnt++;
+			} else {
+				bio_list_add(&conf->pending_bio_list, mbio);
+				conf->pending_count++;
+			}
 			spin_unlock_irqrestore(&conf->device_lock, flags);
-			if (!mddev_check_plugged(mddev))
+			if (!plug)
 				md_wakeup_thread(mddev->thread);
 		}
 	}
 			split = bio;
 		}
+		/*
+		 * If a bio is splitted, the first part of bio will pass
+		 * barrier but the bio is queued in current->bio_list (see
+		 * generic_make_request). If there is a raise_barrier() called
+		 * here, the second part of bio can't pass barrier. But since
+		 * the first part bio isn't dispatched to underlaying disks
+		 * yet, the barrier is never released, hence raise_barrier will
+		 * alays wait. We have a deadlock.
+		 * Note, this only happens in read path. For write path, the
+		 * first part of bio is dispatched in a schedule() call
+		 * (because of blk plug) or offloaded to raid10d.
+		 * Quitting from the function immediately can change the bio
+		 * order queued in bio_list and avoid the deadlock.
+		 */
 		__make_request(mddev, split);
+		if (split != bio && bio_data_dir(bio) == READ) {
+			generic_make_request(bio);
+			break;
+		}
 	} while (split != bio);
 	/* In case raid10d snuck in to freeze_array */
 			return ret;
 	}
 	md_set_array_sectors(mddev, size);
-	if (mddev->queue) {
-		set_capacity(mddev->gendisk, mddev->array_sectors);
-		revalidate_disk(mddev->gendisk);
-	}
 	if (sectors > mddev->dev_sectors &&
 	    mddev->recovery_cp > oldsize) {
 		mddev->recovery_cp = oldsize;

drivers/md/raid5.c+2−3

 		     (test_bit(R5_Wantdrain, &dev->flags) ||
 		      test_bit(R5_InJournal, &dev->flags))) ||
 		    (srctype == SYNDROME_SRC_WRITTEN &&
-		     dev->written)) {
+		     (dev->written ||
+		      test_bit(R5_InJournal, &dev->flags)))) {
 			if (test_bit(R5_InJournal, &dev->flags))
 				srcs[slot] = sh->dev[i].orig_page;
 			else
 			return ret;
 	}
 	md_set_array_sectors(mddev, newsize);
-	set_capacity(mddev->gendisk, mddev->array_sectors);
-	revalidate_disk(mddev->gendisk);
 	if (sectors > mddev->dev_sectors &&
 	    mddev->recovery_cp > mddev->dev_sectors) {
 		mddev->recovery_cp = mddev->dev_sectors;

drivers/media/platform/coda/imx-vdoa.c+1−1

@@ -321,7 +321,7 @@ static const struct of_device_id vdoa_dt_ids[] = { · 320 unmodified lines
321	};	321	};
322	MODULE_DEVICE_TABLE(of, vdoa_dt_ids);	322	MODULE_DEVICE_TABLE(of, vdoa_dt_ids);
323		323
324	static const struct platform_driver vdoa_driver = {	324	static struct platform_driver vdoa_driver = {
325	.probe = vdoa_probe,	325	.probe = vdoa_probe,
326	.remove = vdoa_remove,	326	.remove = vdoa_remove,
327	.driver = {	327	.driver = {

drivers/media/platform/exynos-gsc/gsc-core.c+0−2

@@ -861,9 +861,7 @@ int gsc_prepare_addr(struct gsc_ctx ctx, struct vb2_buffer vb, · 860 unmodified lines
861		861
862	if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) \|\|	862	if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) \|\|
863	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) \|\|	863	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) \|\|
864	(frame->fmt->pixelformat == V4L2_PIX_FMT_NV61) \|\|
865	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) \|\|	864	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) \|\|
866	(frame->fmt->pixelformat == V4L2_PIX_FMT_NV21) \|\|
867	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))	865	(frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))
868	swap(addr->cb, addr->cr);	866	swap(addr->cb, addr->cr);
869		867

drivers/media/platform/sti/bdisp/bdisp-v4l2.c+1−1

 error_ctrls:
 	bdisp_ctrls_delete(ctx);
-error_fh:
 	v4l2_fh_del(&ctx->fh);
+error_fh:
 	v4l2_fh_exit(&ctx->fh);
 	bdisp_hw_free_nodes(ctx);
 mem_ctx:

drivers/media/usb/dvb-usb/dvb-usb-firmware.c+12−10

 int usb_cypress_load_firmware(struct usb_device *udev, const struct firmware *fw, int type)
 {
 	struct hexline *hx;
-	u8 reset;
+	u8 *buf;
-	int ret,pos=0;
+	int ret, pos = 0;
+	u16 cpu_cs_register = cypress[type].cpu_cs_register;
-	hx = kmalloc(sizeof(*hx), GFP_KERNEL);
+	buf = kmalloc(sizeof(*hx), GFP_KERNEL);
-	if (!hx)
+	if (!buf)
 		return -ENOMEM;
+	hx = (struct hexline *)buf;
 	/* stop the CPU */
-	reset = 1;
+	buf[0] = 1;
-	if ((ret = usb_cypress_writemem(udev,cypress[type].cpu_cs_register,&reset,1)) != 1)
+	if (usb_cypress_writemem(udev, cpu_cs_register, buf, 1) != 1)
 		err("could not stop the USB controller CPU.");
 	while ((ret = dvb_usb_get_hexline(fw, hx, &pos)) > 0) {
 	}
 	if (ret < 0) {
 		err("firmware download failed at %d with %d",pos,ret);
-		kfree(hx);
+		kfree(buf);
 		return ret;
 	}
 	if (ret == 0) {
 		/* restart the CPU */
-		reset = 0;
+		buf[0] = 0;
-		if (ret || usb_cypress_writemem(udev,cypress[type].cpu_cs_register,&reset,1) != 1) {
+		if (usb_cypress_writemem(udev, cpu_cs_register, buf, 1) != 1) {
 			err("could not restart the USB controller CPU.");
 			ret = -EINVAL;
 		}
 	} else
 		ret = -EIO;
-	kfree(hx);
+	kfree(buf);
 	return ret;
 }

drivers/memory/omap-gpmc.c+1−3

@@ -1947,9 +1947,7 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev, · 1946 unmodified lines
1947	if (!of_property_read_u32(child, "dma-channel", &val))	1947	if (!of_property_read_u32(child, "dma-channel", &val))
1948	gpmc_onenand_data->dma_channel = val;	1948	gpmc_onenand_data->dma_channel = val;
1949		1949
1950	gpmc_onenand_init(gpmc_onenand_data);	1950	return gpmc_onenand_init(gpmc_onenand_data);
1951
1952	return 0;
1953	}	1951	}
1954	#else	1952	#else
1955	static int gpmc_probe_onenand_child(struct platform_device *pdev,	1953	static int gpmc_probe_onenand_child(struct platform_device *pdev,

drivers/misc/cxl/pci.c+6−7

 	/* If we're permanently dead, give up. */
 	if (state == pci_channel_io_perm_failure) {
-		/* Tell the AFU drivers; but we don't care what they
-		 * say, we're going away.
-		 */
 		for (i = 0; i < adapter->slices; i++) {
 			afu = adapter->afu[i];
-			/* Only participate in EEH if we are on a virtual PHB */
+			/*
-			if (afu->phb == NULL)
+			 * Tell the AFU drivers; but we don't care what they
-				return PCI_ERS_RESULT_NONE;
+			 * say, we're going away.
-			cxl_vphb_error_detected(afu, state);
+			 */
+			if (afu->phb != NULL)
+				cxl_vphb_error_detected(afu, state);
 		}
 		return PCI_ERS_RESULT_DISCONNECT;
 	}

drivers/misc/mei/bus-fixup.c+2−12

 static int mei_osver(struct mei_cl_device *cldev)
 {
-	int ret;
 	const size_t size = sizeof(struct mkhi_msg_hdr) +
 			    sizeof(struct mkhi_fwcaps) +
 			    sizeof(struct mei_os_ver);
-	size_t length = 8;
 	char buf[size];
 	struct mkhi_msg *req;
 	struct mkhi_fwcaps *fwcaps;
 	os_ver = (struct mei_os_ver *)fwcaps->data;
 	os_ver->os_type = OSTYPE_LINUX;
-	ret = __mei_cl_send(cldev->cl, buf, size, mode);
+	return __mei_cl_send(cldev->cl, buf, size, mode);
-	if (ret < 0)
-		return ret;
-	ret = __mei_cl_recv(cldev->cl, buf, length, 0);
-	if (ret < 0)
-		return ret;
-	return 0;
 }
 static void mei_mkhi_fix(struct mei_cl_device *cldev)
 		return;
 	ret = mei_osver(cldev);
-	if (ret)
+	if (ret < 0)
 		dev_err(&cldev->dev, "OS version command failed %d\n", ret);
 	mei_cldev_disable(cldev);

drivers/misc/mei/init.c+6−2

 	mei_clear_interrupts(dev);
-	mei_synchronize_irq(dev);
 	/* we're already in reset, cancel the init timer
 	 * if the reset was called due the hbm protocol error
 	 * we need to call it before hw start
 		container_of(work, struct mei_device,  reset_work);
 	int ret;
+	mei_clear_interrupts(dev);
+	mei_synchronize_irq(dev);
 	mutex_lock(&dev->device_lock);
 	ret = mei_reset(dev);
 	mei_cancel_work(dev);
+	mei_clear_interrupts(dev);
+	mei_synchronize_irq(dev);
 	mutex_lock(&dev->device_lock);
 	dev->dev_state = MEI_DEV_POWER_DOWN;

drivers/misc/vmw_vmci/vmci_guest.c+2−2

@@ -566,10 +566,10 @@ static int vmci_guest_probe_device(struct pci_dev *pdev, · 565 unmodified lines
566	*/	566	*/
567	error = pci_alloc_irq_vectors(pdev, VMCI_MAX_INTRS, VMCI_MAX_INTRS,	567	error = pci_alloc_irq_vectors(pdev, VMCI_MAX_INTRS, VMCI_MAX_INTRS,
568	PCI_IRQ_MSIX);	568	PCI_IRQ_MSIX);
569	if (error) {	569	if (error < 0) {
570	error = pci_alloc_irq_vectors(pdev, 1, 1,	570	error = pci_alloc_irq_vectors(pdev, 1, 1,
571	PCI_IRQ_MSIX \| PCI_IRQ_MSI \| PCI_IRQ_LEGACY);	571	PCI_IRQ_MSIX \| PCI_IRQ_MSI \| PCI_IRQ_LEGACY);
572	if (error)	572	if (error < 0)
573	goto err_remove_bitmap;	573	goto err_remove_bitmap;
574	} else {	574	} else {
575	vmci_dev->exclusive_vectors = true;	575	vmci_dev->exclusive_vectors = true;

drivers/mmc/core/block.c+3−4

 			       struct mmc_blk_request *brq, struct request *req,
 			       bool old_req_pending)
 {
-	struct mmc_queue_req *mq_rq;
 	bool req_pending;
-	mq_rq = container_of(brq, struct mmc_queue_req, brq);
 	/*
 	 * If this is an SD card and we're writing, we can first
 	 * mark the known good sectors as ok.
 		case MMC_BLK_CMD_ERR:
 			req_pending = mmc_blk_rw_cmd_err(md, card, brq, old_req, req_pending);
 			if (mmc_blk_reset(md, card->host, type)) {
-				mmc_blk_rw_cmd_abort(card, old_req);
+				if (req_pending)
+					mmc_blk_rw_cmd_abort(card, old_req);
 				mmc_blk_rw_try_restart(mq, new_req);
 				return;
 			}
 		mmc_blk_issue_flush(mq, req);
 	} else {
 		mmc_blk_issue_rw_rq(mq, req);
+		card->host->context_info.is_waiting_last_req = false;
 	}
 out:

drivers/mmc/core/mmc.c+1−1

@@ -1730,7 +1730,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, · 1729 unmodified lines
1730	err = mmc_select_hs400(card);	1730	err = mmc_select_hs400(card);
1731	if (err)	1731	if (err)
1732	goto free_card;	1732	goto free_card;
1733	} else {	1733	} else if (!mmc_card_hs400es(card)) {
1734	/* Select the desired bus width optionally */	1734	/* Select the desired bus width optionally */
1735	err = mmc_select_bus_width(card);	1735	err = mmc_select_bus_width(card);
1736	if (err > 0 && mmc_card_hs(card)) {	1736	if (err > 0 && mmc_card_hs(card)) {

drivers/mmc/host/mtk-sd.c+2−2

@@ -580,7 +580,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) · 579 unmodified lines
580	}	580	}
581	}	581	}
582	sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD \| MSDC_CFG_CKDIV,	582	sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD \| MSDC_CFG_CKDIV,
583	(mode << 8) \| (div % 0xff));	583	(mode << 8) \| div);
584	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);	584	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
585	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))	585	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
586	cpu_relax();	586	cpu_relax();
@@ -1559,7 +1559,7 @@ static int msdc_drv_probe(struct platform_device *pdev) · 972 unmodified lines
1559	host->src_clk_freq = clk_get_rate(host->src_clk);	1559	host->src_clk_freq = clk_get_rate(host->src_clk);
1560	/* Set host parameters to mmc */	1560	/* Set host parameters to mmc */
1561	mmc->ops = &mt_msdc_ops;	1561	mmc->ops = &mt_msdc_ops;
1562	mmc->f_min = host->src_clk_freq / (4 * 255);	1562	mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1563		1563
1564	mmc->caps \|= MMC_CAP_ERASE \| MMC_CAP_CMD23;	1564	mmc->caps \|= MMC_CAP_ERASE \| MMC_CAP_CMD23;
1565	/* MMC core transfer sizes tunable parameters */	1565	/* MMC core transfer sizes tunable parameters */

drivers/mmc/host/sdhci-of-arasan.c+5−9

 #include "sdhci-pltfm.h"
 #include <linux/of.h>
-#define SDHCI_ARASAN_CLK_CTRL_OFFSET	0x2c
 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
 #define VENDOR_ENHANCED_STROBE		BIT(0)
-#define CLK_CTRL_TIMEOUT_SHIFT		16
-#define CLK_CTRL_TIMEOUT_MASK		(0xf << CLK_CTRL_TIMEOUT_SHIFT)
-#define CLK_CTRL_TIMEOUT_MIN_EXP	13
 #define PHY_CLK_TOO_SLOW_HZ		400000
 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
 {
-	u32 div;
 	unsigned long freq;
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-	div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
+	/* SDHCI timeout clock is in kHz */
-	div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
+	freq = DIV_ROUND_UP(clk_get_rate(pltfm_host->clk), 1000);
-	freq = clk_get_rate(pltfm_host->clk);
+	/* or in MHz */
-	freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
+	if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
+		freq = DIV_ROUND_UP(freq, 1000);
 	return freq;
 }

drivers/mmc/host/sdhci-of-at91.c+19−0

@@ -85,11 +85,30 @@ static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) · 84 unmodified lines
85	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);	85	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86	}	86	}
87		87
		88	/*
		89	* In this specific implementation of the SDHCI controller, the power register
		90	* needs to have a valid voltage set even when the power supply is managed by
		91	* an external regulator.
		92	*/
		93	static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
		94	unsigned short vdd)
		95	{
		96	if (!IS_ERR(host->mmc->supply.vmmc)) {
		97	struct mmc_host *mmc = host->mmc;
		98
		99	spin_unlock_irq(&host->lock);
		100	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
		101	spin_lock_irq(&host->lock);
		102	}
		103	sdhci_set_power_noreg(host, mode, vdd);
		104	}
		105
88	static const struct sdhci_ops sdhci_at91_sama5d2_ops = {	106	static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
89	.set_clock = sdhci_at91_set_clock,	107	.set_clock = sdhci_at91_set_clock,
90	.set_bus_width = sdhci_set_bus_width,	108	.set_bus_width = sdhci_set_bus_width,
91	.reset = sdhci_reset,	109	.reset = sdhci_reset,
92	.set_uhs_signaling = sdhci_set_uhs_signaling,	110	.set_uhs_signaling = sdhci_set_uhs_signaling,
		111	.set_power = sdhci_at91_set_power,
93	};	112	};
94		113
95	static const struct sdhci_pltfm_data soc_data_sama5d2 = {	114	static const struct sdhci_pltfm_data soc_data_sama5d2 = {

drivers/mmc/host/sdhci-pci-core.c+4−0

 	if (mode == MMC_POWER_OFF)
 		return;
+	spin_unlock_irq(&host->lock);
 	/*
 	 * Bus power might not enable after D3 -> D0 transition due to the
 	 * present state not yet having propagated. Retry for up to 2ms.
 		reg |= SDHCI_POWER_ON;
 		sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 	}
+	spin_lock_irq(&host->lock);
 }
 static const struct sdhci_ops sdhci_intel_byt_ops = {

drivers/mmc/host/sdhci.c+3−1

 			return;
 		}
 		timeout--;
-		mdelay(1);
+		spin_unlock_irq(&host->lock);
+		usleep_range(900, 1100);
+		spin_lock_irq(&host->lock);
 	}
 	clk |= SDHCI_CLOCK_CARD_EN;

drivers/mmc/host/ushc.c+3−0

@@ -426,6 +426,9 @@ static int ushc_probe(struct usb_interface intf, const struct usb_device_id id · 425 unmodified lines
426	struct ushc_data *ushc;	426	struct ushc_data *ushc;
427	int ret;	427	int ret;
428		428
		429	if (intf->cur_altsetting->desc.bNumEndpoints < 1)
		430	return -ENODEV;
		431
429	mmc = mmc_alloc_host(sizeof(struct ushc_data), &intf->dev);	432	mmc = mmc_alloc_host(sizeof(struct ushc_data), &intf->dev);
430	if (mmc == NULL)	433	if (mmc == NULL)
431	return -ENOMEM;	434	return -ENOMEM;

drivers/net/ethernet/amd/xgbe/xgbe-common.h+16−14

 #define XP_ECC_CNT1_DESC_DED_WIDTH		8
 #define XP_ECC_CNT1_DESC_SEC_INDEX		0
 #define XP_ECC_CNT1_DESC_SEC_WIDTH		8
-#define XP_ECC_IER_DESC_DED_INDEX		0
+#define XP_ECC_IER_DESC_DED_INDEX		5
 #define XP_ECC_IER_DESC_DED_WIDTH		1
-#define XP_ECC_IER_DESC_SEC_INDEX		1
+#define XP_ECC_IER_DESC_SEC_INDEX		4
 #define XP_ECC_IER_DESC_SEC_WIDTH		1
-#define XP_ECC_IER_RX_DED_INDEX			2
+#define XP_ECC_IER_RX_DED_INDEX			3
 #define XP_ECC_IER_RX_DED_WIDTH			1
-#define XP_ECC_IER_RX_SEC_INDEX			3
+#define XP_ECC_IER_RX_SEC_INDEX			2
 #define XP_ECC_IER_RX_SEC_WIDTH			1
-#define XP_ECC_IER_TX_DED_INDEX			4
+#define XP_ECC_IER_TX_DED_INDEX			1
 #define XP_ECC_IER_TX_DED_WIDTH			1
-#define XP_ECC_IER_TX_SEC_INDEX			5
+#define XP_ECC_IER_TX_SEC_INDEX			0
 #define XP_ECC_IER_TX_SEC_WIDTH			1
-#define XP_ECC_ISR_DESC_DED_INDEX		0
+#define XP_ECC_ISR_DESC_DED_INDEX		5
 #define XP_ECC_ISR_DESC_DED_WIDTH		1
-#define XP_ECC_ISR_DESC_SEC_INDEX		1
+#define XP_ECC_ISR_DESC_SEC_INDEX		4
 #define XP_ECC_ISR_DESC_SEC_WIDTH		1
-#define XP_ECC_ISR_RX_DED_INDEX			2
+#define XP_ECC_ISR_RX_DED_INDEX			3
 #define XP_ECC_ISR_RX_DED_WIDTH			1
-#define XP_ECC_ISR_RX_SEC_INDEX			3
+#define XP_ECC_ISR_RX_SEC_INDEX			2
 #define XP_ECC_ISR_RX_SEC_WIDTH			1
-#define XP_ECC_ISR_TX_DED_INDEX			4
+#define XP_ECC_ISR_TX_DED_INDEX			1
 #define XP_ECC_ISR_TX_DED_WIDTH			1
-#define XP_ECC_ISR_TX_SEC_INDEX			5
+#define XP_ECC_ISR_TX_SEC_INDEX			0
 #define XP_ECC_ISR_TX_SEC_WIDTH			1
 #define XP_I2C_MUTEX_BUSY_INDEX			31
 #define XP_I2C_MUTEX_BUSY_WIDTH			1
 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH	1
 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	1
 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1
-#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX	2
+#define RX_PACKET_ATTRIBUTES_LAST_INDEX		2
-#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH	1
+#define RX_PACKET_ATTRIBUTES_LAST_WIDTH		1
 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX	3
 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH	1
 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX	4
 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH	1
 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX	6
 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH	1
+#define RX_PACKET_ATTRIBUTES_FIRST_INDEX	7
+#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH	1
 #define RX_NORMAL_DESC0_OVT_INDEX		0
 #define RX_NORMAL_DESC0_OVT_WIDTH		16

drivers/net/ethernet/amd/xgbe/xgbe-dev.c+11−9

 	/* Get the header length */
 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
+		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+			       FIRST, 1);
 		rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
 						      RX_NORMAL_DESC2, HL);
 		if (rdata->rx.hdr_len)
 			pdata->ext_stats.rx_split_header_packets++;
+	} else {
+		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+			       FIRST, 0);
 	}
 	/* Get the RSS hash */
 		}
 	}
-	/* Get the packet length */
+	/* Not all the data has been transferred for this packet */
-	rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
+	if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD))
-	if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
-		/* Not all the data has been transferred for this packet */
-		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
-			       INCOMPLETE, 1);
 		return 0;
-	}
 	/* This is the last of the data for this packet */
 	XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
-		       INCOMPLETE, 0);
+		       LAST, 1);
+	/* Get the packet length */
+	rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
 	/* Set checksum done indicator as appropriate */
 	if (netdev->features & NETIF_F_RXCSUM)

drivers/net/ethernet/amd/xgbe/xgbe-drv.c+65−47

 {
 	struct sk_buff *skb;
 	u8 *packet;
-	unsigned int copy_len;
 	skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
 	if (!skb)
 		return NULL;
-	/* Start with the header buffer which may contain just the header
+	/* Pull in the header buffer which may contain just the header
 	 * or the header plus data
 	 */
 	dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
 	packet = page_address(rdata->rx.hdr.pa.pages) +
 		 rdata->rx.hdr.pa.pages_offset;
-	copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len;
+	skb_copy_to_linear_data(skb, packet, len);
-	copy_len = min(rdata->rx.hdr.dma_len, copy_len);
+	skb_put(skb, len);
-	skb_copy_to_linear_data(skb, packet, copy_len);
-	skb_put(skb, copy_len);
-	len -= copy_len;
-	if (len) {
-		/* Add the remaining data as a frag */
-		dma_sync_single_range_for_cpu(pdata->dev,
-					      rdata->rx.buf.dma_base,
-					      rdata->rx.buf.dma_off,
-					      rdata->rx.buf.dma_len,
-					      DMA_FROM_DEVICE);
-		skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
-				rdata->rx.buf.pa.pages,
-				rdata->rx.buf.pa.pages_offset,
-				len, rdata->rx.buf.dma_len);
-		rdata->rx.buf.pa.pages = NULL;
-	}
 	return skb;
 }
+static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
+				     struct xgbe_packet_data *packet)
+{
+	/* Always zero if not the first descriptor */
+	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
+		return 0;
+	/* First descriptor with split header, return header length */
+	if (rdata->rx.hdr_len)
+		return rdata->rx.hdr_len;
+	/* First descriptor but not the last descriptor and no split header,
+	 * so the full buffer was used
+	 */
+	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
+		return rdata->rx.hdr.dma_len;
+	/* First descriptor and last descriptor and no split header, so
+	 * calculate how much of the buffer was used
+	 */
+	return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
+}
+static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
+				     struct xgbe_packet_data *packet,
+				     unsigned int len)
+{
+	/* Always the full buffer if not the last descriptor */
+	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
+		return rdata->rx.buf.dma_len;
+	/* Last descriptor so calculate how much of the buffer was used
+	 * for the last bit of data
+	 */
+	return rdata->rx.len - len;
+}
 static int xgbe_tx_poll(struct xgbe_channel *channel)
 {
 	struct xgbe_prv_data *pdata = channel->pdata;
 	struct napi_struct *napi;
 	struct sk_buff *skb;
 	struct skb_shared_hwtstamps *hwtstamps;
-	unsigned int incomplete, error, context_next, context;
+	unsigned int last, error, context_next, context;
-	unsigned int len, rdesc_len, max_len;
+	unsigned int len, buf1_len, buf2_len, max_len;
 	unsigned int received = 0;
 	int packet_count = 0;
 	if (!ring)
 		return 0;
-	incomplete = 0;
+	last = 0;
 	context_next = 0;
 	napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 		received++;
 		ring->cur++;
-		incomplete = XGMAC_GET_BITS(packet->attributes,
+		last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
-					    RX_PACKET_ATTRIBUTES,
+				      LAST);
-					    INCOMPLETE);
 		context_next = XGMAC_GET_BITS(packet->attributes,
 					      RX_PACKET_ATTRIBUTES,
 					      CONTEXT_NEXT);
 					 CONTEXT);
 		/* Earlier error, just drain the remaining data */
-		if ((incomplete || context_next) && error)
+		if ((!last || context_next) && error)
 			goto read_again;
 		if (error || packet->errors) {
 		}
 		if (!context) {
-			/* Length is cumulative, get this descriptor's length */
+			/* Get the data length in the descriptor buffers */
-			rdesc_len = rdata->rx.len - len;
+			buf1_len = xgbe_rx_buf1_len(rdata, packet);
-			len += rdesc_len;
+			len += buf1_len;
+			buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
+			len += buf2_len;
-			if (rdesc_len && !skb) {
+			if (!skb) {
 				skb = xgbe_create_skb(pdata, napi, rdata,
-						      rdesc_len);
+						      buf1_len);
-				if (!skb)
+				if (!skb) {
 					error = 1;
-			} else if (rdesc_len) {
+					goto skip_data;
+				}
+			}
+			if (buf2_len) {
 				dma_sync_single_range_for_cpu(pdata->dev,
 							rdata->rx.buf.dma_base,
 							rdata->rx.buf.dma_off,
 				skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 						rdata->rx.buf.pa.pages,
 						rdata->rx.buf.pa.pages_offset,
-						rdesc_len,
+						buf2_len,
 						rdata->rx.buf.dma_len);
 				rdata->rx.buf.pa.pages = NULL;
 			}
 		}
-		if (incomplete || context_next)
+skip_data:
+		if (!last || context_next)
 			goto read_again;
 		if (!skb)
 	}
 	/* Check if we need to save state before leaving */
-	if (received && (incomplete || context_next)) {
+	if (received && (!last || context_next)) {
 		rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
 		rdata->state_saved = 1;
 		rdata->state.skb = skb;
 	processed = xgbe_rx_poll(channel, budget);
 	/* If we processed everything, we are done */
-	if (processed < budget) {
+	if ((processed < budget) && napi_complete_done(napi, processed)) {
-		/* Turn off polling */
-		napi_complete_done(napi, processed);
 		/* Enable Tx and Rx interrupts */
 		if (pdata->channel_irq_mode)
 			xgbe_enable_rx_tx_int(pdata, channel);
 	} while ((processed < budget) && (processed != last_processed));
 	/* If we processed everything, we are done */
-	if (processed < budget) {
+	if ((processed < budget) && napi_complete_done(napi, processed)) {
-		/* Turn off polling */
-		napi_complete_done(napi, processed);
 		/* Enable Tx and Rx interrupts */
 		xgbe_enable_rx_tx_ints(pdata);
 	}

drivers/net/ethernet/aquantia/atlantic/aq_main.c+1−0

@@ -98,6 +98,7 @@ static int aq_ndev_change_mtu(struct net_device *ndev, int new_mtu) · 97 unmodified lines
98		98
99	if (err < 0)	99	if (err < 0)
100	goto err_exit;	100	goto err_exit;
		101	ndev->mtu = new_mtu;
101		102
102	if (netif_running(ndev)) {	103	if (netif_running(ndev)) {
103	aq_ndev_close(ndev);	104	aq_ndev_close(ndev);

drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c+1−1

 		if (!((1U << i) & self->msix_entry_mask))
 			continue;
-		free_irq(pci_irq_vector(pdev, i), self->aq_vec[i]);
 		if (pdev->msix_enabled)
 			irq_set_affinity_hint(pci_irq_vector(pdev, i), NULL);
+		free_irq(pci_irq_vector(pdev, i), self->aq_vec[i]);
 		self->msix_entry_mask &= ~(1U << i);
 	}
 }

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h+1−0

@@ -137,6 +137,7 @@ static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = { · 136 unmodified lines
137	.tx_rings = HW_ATL_A0_TX_RINGS,	137	.tx_rings = HW_ATL_A0_TX_RINGS,
138	.rx_rings = HW_ATL_A0_RX_RINGS,	138	.rx_rings = HW_ATL_A0_RX_RINGS,
139	.hw_features = NETIF_F_HW_CSUM \|	139	.hw_features = NETIF_F_HW_CSUM \|
		140	NETIF_F_RXCSUM \|
140	NETIF_F_RXHASH \|	141	NETIF_F_RXHASH \|
141	NETIF_F_SG \|	142	NETIF_F_SG \|
142	NETIF_F_TSO,	143	NETIF_F_TSO,

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h+1−0

@@ -188,6 +188,7 @@ static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = { · 187 unmodified lines
188	.tx_rings = HW_ATL_B0_TX_RINGS,	188	.tx_rings = HW_ATL_B0_TX_RINGS,
189	.rx_rings = HW_ATL_B0_RX_RINGS,	189	.rx_rings = HW_ATL_B0_RX_RINGS,
190	.hw_features = NETIF_F_HW_CSUM \|	190	.hw_features = NETIF_F_HW_CSUM \|
		191	NETIF_F_RXCSUM \|
191	NETIF_F_RXHASH \|	192	NETIF_F_RXHASH \|
192	NETIF_F_SG \|	193	NETIF_F_SG \|
193	NETIF_F_TSO \|	194	NETIF_F_TSO \|

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c+30−6

 	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 		NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
-	/* VF with OLD Hypervisor or old PF do not support filtering */
 	if (IS_PF(bp)) {
 		if (chip_is_e1x)
 			bp->accept_any_vlan = true;
 		else
 			dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
-#ifdef CONFIG_BNX2X_SRIOV
-	} else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
-		dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
-#endif
 	}
+	/* For VF we'll know whether to enable VLAN filtering after
+	 * getting a response to CHANNEL_TLV_ACQUIRE from PF.
+	 */
 	dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
 	dev->features |= NETIF_F_HIGHDMA;
 	if (!netif_running(bp->dev)) {
 		DP(BNX2X_MSG_PTP,
 		   "PTP adjfreq called while the interface is down\n");
-		return -EFAULT;
+		return -ENETDOWN;
 	}
 	if (ppb < 0) {
 {
 	struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+	if (!netif_running(bp->dev)) {
+		DP(BNX2X_MSG_PTP,
+		   "PTP adjtime called while the interface is down\n");
+		return -ENETDOWN;
+	}
 	DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
 	timecounter_adjtime(&bp->timecounter, delta);
 	struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
 	u64 ns;
+	if (!netif_running(bp->dev)) {
+		DP(BNX2X_MSG_PTP,
+		   "PTP gettime called while the interface is down\n");
+		return -ENETDOWN;
+	}
 	ns = timecounter_read(&bp->timecounter);
 	DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
 	struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
 	u64 ns;
+	if (!netif_running(bp->dev)) {
+		DP(BNX2X_MSG_PTP,
+		   "PTP settime called while the interface is down\n");
+		return -ENETDOWN;
+	}
 	ns = timespec64_to_ns(ts);
 	DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
 		rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
 		if (rc)
 			goto init_one_freemem;
+#ifdef CONFIG_BNX2X_SRIOV
+		/* VF with OLD Hypervisor or old PF do not support filtering */
+		if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
+			dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+			dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+		}
+#endif
 	}
 	/* Enable SRIOV if capability found in configuration space */

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c+16−8

 	/* Add/Remove the filter */
 	rc = bnx2x_config_vlan_mac(bp, &ramrod);
-	if (rc && rc != -EEXIST) {
+	if (rc == -EEXIST)
+		return 0;
+	if (rc) {
 		BNX2X_ERR("Failed to %s %s\n",
 			  filter->add ? "add" : "delete",
 			  (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ?
 		return rc;
 	}
+	filter->applied = true;
 	return 0;
 }
 	/* Rollback if needed */
 	if (i != filters->count) {
 		BNX2X_ERR("Managed only %d/%d filters - rolling back\n",
-			  i, filters->count + 1);
+			  i, filters->count);
 		while (--i >= 0) {
+			if (!filters->filters[i].applied)
+				continue;
 			filters->filters[i].add = !filters->filters[i].add;
 			bnx2x_vf_mac_vlan_config(bp, vf, qid,
 						 &filters->filters[i],
 			continue;
 		}
-		DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid);
+		DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
+		       "add addresses for vf %d\n", vf->abs_vfid);
 		for_each_vfq(vf, j) {
 			struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
 				cpu_to_le32(U64_HI(q_stats_addr));
 			cur_query_entry->address.lo =
 				cpu_to_le32(U64_LO(q_stats_addr));
-			DP(BNX2X_MSG_IOV,
+			DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
-			   "added address %x %x for vf %d queue %d client %d\n",
+			       "added address %x %x for vf %d queue %d client %d\n",
-			   cur_query_entry->address.hi,
+			       cur_query_entry->address.hi,
-			   cur_query_entry->address.lo, cur_query_entry->funcID,
+			       cur_query_entry->address.lo,
-			   j, cur_query_entry->index);
+			       cur_query_entry->funcID,
+			       j, cur_query_entry->index);
 			cur_query_entry++;
 			cur_data_offset += sizeof(struct per_queue_stats);
 			stats_count++;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h+1−0

@@ -114,6 +114,7 @@ struct bnx2x_vf_mac_vlan_filter { · 113 unmodified lines
114	(BNX2X_VF_FILTER_MAC \| BNX2X_VF_FILTER_VLAN) /shortcut/	114	(BNX2X_VF_FILTER_MAC \| BNX2X_VF_FILTER_VLAN) /shortcut/
115		115
116	bool add;	116	bool add;
		117	bool applied;
117	u8 *mac;	118	u8 *mac;
118	u16 vid;	119	u16 vid;
119	};	120	};

drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c+28−12

 	struct bnx2x *bp = netdev_priv(dev);
 	struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
 	struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
-	int rc, i = 0;
+	int rc = 0, i = 0;
 	struct netdev_hw_addr *ha;
 	if (bp->state != BNX2X_STATE_OPEN) {
 	/* Get Rx mode requested */
 	DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
+	/* We support PFVF_MAX_MULTICAST_PER_VF mcast addresses tops */
+	if (netdev_mc_count(dev) > PFVF_MAX_MULTICAST_PER_VF) {
+		DP(NETIF_MSG_IFUP,
+		   "VF supports not more than %d multicast MAC addresses\n",
+		   PFVF_MAX_MULTICAST_PER_VF);
+		rc = -EINVAL;
+		goto out;
+	}
 	netdev_for_each_mc_addr(ha, dev) {
 		DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
 		   bnx2x_mc_addr(ha));
 		i++;
 	}
-	/* We support four PFVF_MAX_MULTICAST_PER_VF mcast
-	  * addresses tops
-	  */
-	if (i >= PFVF_MAX_MULTICAST_PER_VF) {
-		DP(NETIF_MSG_IFUP,
-		   "VF supports not more than %d multicast MAC addresses\n",
-		   PFVF_MAX_MULTICAST_PER_VF);
-		return -EINVAL;
-	}
 	req->n_multicast = i;
 	req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED;
 	req->vf_qid = 0;
 out:
 	bnx2x_vfpf_finalize(bp, &req->first_tlv);
-	return 0;
+	return rc;
 }
 /* request pf to add a vlan for the vf */
 				goto op_err;
 		}
+		/* build vlan list */
+		fl = NULL;
+		rc = bnx2x_vf_mbx_macvlan_list(bp, vf, msg, &fl,
+					       VFPF_VLAN_FILTER);
+		if (rc)
+			goto op_err;
+		if (fl) {
+			/* set vlan list */
+			rc = bnx2x_vf_mac_vlan_config_list(bp, vf, fl,
+							   msg->vf_qid,
+							   false);
+			if (rc)
+				goto op_err;
+		}
 	}
 	if (msg->flags & VFPF_SET_Q_FILTERS_RX_MASK_CHANGED) {

drivers/net/ethernet/broadcom/bnxt/bnxt.c+18−7

 		vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
 	}
 #endif
+	if (BNXT_PF(bp) && (le16_to_cpu(resp->flags) &
+			    FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED))
+		bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
 	switch (resp->port_partition_type) {
 	case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
 	case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
 		bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
 				 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
 	}
-	link_info->support_auto_speeds =
+	if (resp->supported_speeds_auto_mode)
-		le16_to_cpu(resp->supported_speeds_auto_mode);
+		link_info->support_auto_speeds =
+			le16_to_cpu(resp->supported_speeds_auto_mode);
 hwrm_phy_qcaps_exit:
 	mutex_unlock(&bp->hwrm_cmd_lock);
 	if (!silent)
 		bnxt_dbg_dump_states(bp);
 	if (netif_running(bp->dev)) {
+		int rc;
+		if (!silent)
+			bnxt_ulp_stop(bp);
 		bnxt_close_nic(bp, false, false);
-		bnxt_open_nic(bp, false, false);
+		rc = bnxt_open_nic(bp, false, false);
+		if (!silent && !rc)
+			bnxt_ulp_start(bp);
 	}
 }
 	if (rc)
 		goto init_err_pci_clean;
+	rc = bnxt_hwrm_func_reset(bp);
+	if (rc)
+		goto init_err_pci_clean;
 	bnxt_hwrm_fw_set_time(bp);
 	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
 	if (rc)
 		goto init_err_pci_clean;
-	rc = bnxt_hwrm_func_reset(bp);
-	if (rc)
-		goto init_err_pci_clean;
 	rc = bnxt_init_int_mode(bp);
 	if (rc)
 		goto init_err_pci_clean;

drivers/net/ethernet/broadcom/bnxt/bnxt.h+1−0

@@ -993,6 +993,7 @@ struct bnxt { · 992 unmodified lines
993	BNXT_FLAG_ROCEV2_CAP)	993	BNXT_FLAG_ROCEV2_CAP)
994	#define BNXT_FLAG_NO_AGG_RINGS 0x20000	994	#define BNXT_FLAG_NO_AGG_RINGS 0x20000
995	#define BNXT_FLAG_RX_PAGE_MODE 0x40000	995	#define BNXT_FLAG_RX_PAGE_MODE 0x40000
		996	#define BNXT_FLAG_FW_LLDP_AGENT 0x80000
996	#define BNXT_FLAG_CHIP_NITRO_A0 0x1000000	997	#define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
997		998
998	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA \| \	999	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA \| \

drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c+1−1

@@ -474,7 +474,7 @@ void bnxt_dcb_init(struct bnxt *bp) · 473 unmodified lines
474	return;	474	return;
475		475
476	bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE;	476	bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE;
477	if (BNXT_PF(bp))	477	if (BNXT_PF(bp) && !(bp->flags & BNXT_FLAG_FW_LLDP_AGENT))
478	bp->dcbx_cap \|= DCB_CAP_DCBX_HOST;	478	bp->dcbx_cap \|= DCB_CAP_DCBX_HOST;
479	else	479	else
480	bp->dcbx_cap \|= DCB_CAP_DCBX_LLD_MANAGED;	480	bp->dcbx_cap \|= DCB_CAP_DCBX_LLD_MANAGED;

drivers/net/ethernet/broadcom/genet/bcmgenet.c+151−61

 /*
  * Broadcom GENET (Gigabit Ethernet) controller driver
  *
- * Copyright (c) 2014 Broadcom Corporation
+ * Copyright (c) 2014-2017 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 			genet_dma_ring_regs[r]);
 }
+static int bcmgenet_begin(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	/* Turn on the clock */
+	return clk_prepare_enable(priv->clk);
+}
+static void bcmgenet_complete(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	/* Turn off the clock */
+	clk_disable_unprepare(priv->clk);
+}
 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 				       struct ethtool_link_ksettings *cmd)
 {
 	STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 	/* Misc UniMAC counters */
 	STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
-			UMAC_RBUF_OVFL_CNT),
+			UMAC_RBUF_OVFL_CNT_V1),
-	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
+	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
+			UMAC_RBUF_ERR_CNT_V1),
 	STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 	STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 	STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 	}
 }
+static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
+{
+	u16 new_offset;
+	u32 val;
+	switch (offset) {
+	case UMAC_RBUF_OVFL_CNT_V1:
+		if (GENET_IS_V2(priv))
+			new_offset = RBUF_OVFL_CNT_V2;
+		else
+			new_offset = RBUF_OVFL_CNT_V3PLUS;
+		val = bcmgenet_rbuf_readl(priv,	new_offset);
+		/* clear if overflowed */
+		if (val == ~0)
+			bcmgenet_rbuf_writel(priv, 0, new_offset);
+		break;
+	case UMAC_RBUF_ERR_CNT_V1:
+		if (GENET_IS_V2(priv))
+			new_offset = RBUF_ERR_CNT_V2;
+		else
+			new_offset = RBUF_ERR_CNT_V3PLUS;
+		val = bcmgenet_rbuf_readl(priv,	new_offset);
+		/* clear if overflowed */
+		if (val == ~0)
+			bcmgenet_rbuf_writel(priv, 0, new_offset);
+		break;
+	default:
+		val = bcmgenet_umac_readl(priv, offset);
+		/* clear if overflowed */
+		if (val == ~0)
+			bcmgenet_umac_writel(priv, 0, offset);
+		break;
+	}
+	return val;
+}
 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 {
 	int i, j = 0;
 		case BCMGENET_STAT_NETDEV:
 		case BCMGENET_STAT_SOFT:
 			continue;
-		case BCMGENET_STAT_MIB_RX:
-		case BCMGENET_STAT_MIB_TX:
 		case BCMGENET_STAT_RUNT:
-			if (s->type != BCMGENET_STAT_MIB_RX)
+			offset += BCMGENET_STAT_OFFSET;
-				offset = BCMGENET_STAT_OFFSET;
+			/* fall through */
+		case BCMGENET_STAT_MIB_TX:
+			offset += BCMGENET_STAT_OFFSET;
+			/* fall through */
+		case BCMGENET_STAT_MIB_RX:
 			val = bcmgenet_umac_readl(priv,
 						  UMAC_MIB_START + j + offset);
+			offset = 0;	/* Reset Offset */
 			break;
 		case BCMGENET_STAT_MISC:
-			val = bcmgenet_umac_readl(priv, s->reg_offset);
+			if (GENET_IS_V1(priv)) {
-			/* clear if overflowed */
+				val = bcmgenet_umac_readl(priv, s->reg_offset);
-			if (val == ~0)
+				/* clear if overflowed */
-				bcmgenet_umac_writel(priv, 0, s->reg_offset);
+				if (val == ~0)
+					bcmgenet_umac_writel(priv, 0,
+							     s->reg_offset);
+			} else {
+				val = bcmgenet_update_stat_misc(priv,
+								s->reg_offset);
+			}
 			break;
 		}
 /* standard ethtool support functions. */
 static const struct ethtool_ops bcmgenet_ethtool_ops = {
+	.begin			= bcmgenet_begin,
+	.complete		= bcmgenet_complete,
 	.get_strings		= bcmgenet_get_strings,
 	.get_sset_count		= bcmgenet_get_sset_count,
 	.get_ethtool_stats	= bcmgenet_get_ethtool_stats,
 	struct bcmgenet_priv *priv = netdev_priv(dev);
 	struct device *kdev = &priv->pdev->dev;
 	struct enet_cb *tx_cb_ptr;
-	struct netdev_queue *txq;
 	unsigned int pkts_compl = 0;
 	unsigned int bytes_compl = 0;
 	unsigned int c_index;
 	dev->stats.tx_packets += pkts_compl;
 	dev->stats.tx_bytes += bytes_compl;
-	txq = netdev_get_tx_queue(dev, ring->queue);
+	netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
-	netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
+				  pkts_compl, bytes_compl);
-	if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
-		if (netif_tx_queue_stopped(txq))
-			netif_tx_wake_queue(txq);
-	}
 	return pkts_compl;
 }
 	struct bcmgenet_tx_ring *ring =
 		container_of(napi, struct bcmgenet_tx_ring, napi);
 	unsigned int work_done = 0;
+	struct netdev_queue *txq;
+	unsigned long flags;
-	work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
+	spin_lock_irqsave(&ring->lock, flags);
+	work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
+	if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
+		txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
+		netif_tx_wake_queue(txq);
+	}
+	spin_unlock_irqrestore(&ring->lock, flags);
 	if (work_done == 0) {
 		napi_complete(napi);
 /* Interrupt bottom half */
 static void bcmgenet_irq_task(struct work_struct *work)
 {
+	unsigned long flags;
+	unsigned int status;
 	struct bcmgenet_priv *priv = container_of(
 			work, struct bcmgenet_priv, bcmgenet_irq_work);
 	netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
-	if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
+	spin_lock_irqsave(&priv->lock, flags);
-		priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
+	status = priv->irq0_stat;
+	priv->irq0_stat = 0;
+	spin_unlock_irqrestore(&priv->lock, flags);
+	if (status & UMAC_IRQ_MPD_R) {
 		netif_dbg(priv, wol, priv->dev,
 			  "magic packet detected, waking up\n");
 		bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
 	}
 	/* Link UP/DOWN event */
-	if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
+	if (status & UMAC_IRQ_LINK_EVENT)
 		phy_mac_interrupt(priv->phydev,
-				  !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
+				  !!(status & UMAC_IRQ_LINK_UP));
-		priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
-	}
 }
 /* bcmgenet_isr1: handle Rx and Tx priority queues */
 	struct bcmgenet_priv *priv = dev_id;
 	struct bcmgenet_rx_ring *rx_ring;
 	struct bcmgenet_tx_ring *tx_ring;
-	unsigned int index;
+	unsigned int index, status;
-	/* Save irq status for bottom-half processing. */
+	/* Read irq status */
-	priv->irq1_stat =
+	status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
-		bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
 		~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
 	/* clear interrupts */
-	bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
+	bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
 	netif_dbg(priv, intr, priv->dev,
-		  "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
+		  "%s: IRQ=0x%x\n", __func__, status);
 	/* Check Rx priority queue interrupts */
 	for (index = 0; index < priv->hw_params->rx_queues; index++) {
-		if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
+		if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
 			continue;
 		rx_ring = &priv->rx_rings[index];
 	/* Check Tx priority queue interrupts */
 	for (index = 0; index < priv->hw_params->tx_queues; index++) {
-		if (!(priv->irq1_stat & BIT(index)))
+		if (!(status & BIT(index)))
 			continue;
 		tx_ring = &priv->tx_rings[index];
 	struct bcmgenet_priv *priv = dev_id;
 	struct bcmgenet_rx_ring *rx_ring;
 	struct bcmgenet_tx_ring *tx_ring;
+	unsigned int status;
+	unsigned long flags;
-	/* Save irq status for bottom-half processing. */
+	/* Read irq status */
-	priv->irq0_stat =
+	status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
-		bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
 		~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
 	/* clear interrupts */
-	bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
+	bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
 	netif_dbg(priv, intr, priv->dev,
-		  "IRQ=0x%x\n", priv->irq0_stat);
+		  "IRQ=0x%x\n", status);
-	if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
+	if (status & UMAC_IRQ_RXDMA_DONE) {
 		rx_ring = &priv->rx_rings[DESC_INDEX];
 		if (likely(napi_schedule_prep(&rx_ring->napi))) {
 		}
 	}
-	if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
+	if (status & UMAC_IRQ_TXDMA_DONE) {
 		tx_ring = &priv->tx_rings[DESC_INDEX];
 		if (likely(napi_schedule_prep(&tx_ring->napi))) {
 		}
 	}
-	if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
-				UMAC_IRQ_PHY_DET_F |
-				UMAC_IRQ_LINK_EVENT |
-				UMAC_IRQ_HFB_SM |
-				UMAC_IRQ_HFB_MM |
-				UMAC_IRQ_MPD_R)) {
-		/* all other interested interrupts handled in bottom half */
-		schedule_work(&priv->bcmgenet_irq_work);
-	}
 	if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
-	    priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
+		status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
-		priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
 		wake_up(&priv->wq);
 	}
+	/* all other interested interrupts handled in bottom half */
+	status &= (UMAC_IRQ_LINK_EVENT |
+		   UMAC_IRQ_MPD_R);
+	if (status) {
+		/* Save irq status for bottom-half processing. */
+		spin_lock_irqsave(&priv->lock, flags);
+		priv->irq0_stat |= status;
+		spin_unlock_irqrestore(&priv->lock, flags);
+		schedule_work(&priv->bcmgenet_irq_work);
+	}
 	return IRQ_HANDLED;
 }
 err_fini_dma:
 	bcmgenet_fini_dma(priv);
 err_clk_disable:
+	if (priv->internal_phy)
+		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
 	clk_disable_unprepare(priv->clk);
 	return ret;
 }
 	 */
 	gphy_rev = reg & 0xffff;
+	/* This is reserved so should require special treatment */
+	if (gphy_rev == 0 || gphy_rev == 0x01ff) {
+		pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
+		return;
+	}
 	/* This is the good old scheme, just GPHY major, no minor nor patch */
 	if ((gphy_rev & 0xf0) != 0)
 		priv->gphy_rev = gphy_rev << 8;
 	else if ((gphy_rev & 0xff00) != 0)
 		priv->gphy_rev = gphy_rev;
-	/* This is reserved so should require special treatment */
-	else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
-		pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
-		return;
-	}
 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 	if (!(params->flags & GENET_HAS_40BITS))
 		pr_warn("GENET does not support 40-bits PA\n");
 	const void *macaddr;
 	struct resource *r;
 	int err = -EIO;
+	const char *phy_mode_str;
 	/* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
 	dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
 		goto err;
 	}
+	spin_lock_init(&priv->lock);
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	dev_set_drvdata(&pdev->dev, dev);
 	ether_addr_copy(dev->dev_addr, macaddr);
 		priv->clk_eee = NULL;
 	}
+	/* If this is an internal GPHY, power it on now, before UniMAC is
+	 * brought out of reset as absolutely no UniMAC activity is allowed
+	 */
+	if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
+	    !strcasecmp(phy_mode_str, "internal"))
+		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
 	err = reset_umac(priv);
 	if (err)
 		goto err_clk_disable;
 	bcmgenet_netif_stop(dev);
-	phy_suspend(priv->phydev);
+	if (!device_may_wakeup(d))
+		phy_suspend(priv->phydev);
 	netif_device_detach(dev);
 	netif_device_attach(dev);
-	phy_resume(priv->phydev);
+	if (!device_may_wakeup(d))
+		phy_resume(priv->phydev);
 	if (priv->eee.eee_enabled)
 		bcmgenet_eee_enable_set(dev, true);
 	return 0;
 out_clk_disable:
+	if (priv->internal_phy)
+		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
 	clk_disable_unprepare(priv->clk);
 	return ret;
 }

drivers/net/ethernet/broadcom/genet/bcmgenet.h+11−5

 /*
- * Copyright (c) 2014 Broadcom Corporation
+ * Copyright (c) 2014-2017 Broadcom
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #define  MDIO_REG_SHIFT			16
 #define  MDIO_REG_MASK			0x1F
-#define UMAC_RBUF_OVFL_CNT		0x61C
+#define UMAC_RBUF_OVFL_CNT_V1		0x61C
+#define RBUF_OVFL_CNT_V2		0x80
+#define RBUF_OVFL_CNT_V3PLUS		0x94
 #define UMAC_MPD_CTRL			0x620
 #define  MPD_EN				(1 << 0)
 #define UMAC_MPD_PW_MS			0x624
 #define UMAC_MPD_PW_LS			0x628
-#define UMAC_RBUF_ERR_CNT		0x634
+#define UMAC_RBUF_ERR_CNT_V1		0x634
+#define RBUF_ERR_CNT_V2			0x84
+#define RBUF_ERR_CNT_V3PLUS		0x98
 #define UMAC_MDF_ERR_CNT		0x638
 #define UMAC_MDF_CTRL			0x650
 #define UMAC_MDF_ADDR			0x654
 	struct work_struct bcmgenet_irq_work;
 	int irq0;
 	int irq1;
-	unsigned int irq0_stat;
-	unsigned int irq1_stat;
 	int wol_irq;
 	bool wol_irq_disabled;
+	/* shared status */
+	spinlock_t lock;
+	unsigned int irq0_stat;
 	/* HW descriptors/checksum variables */
 	bool desc_64b_en;
 	bool desc_rxchk_en;

drivers/net/ethernet/broadcom/genet/bcmmii.c+0−15

@@ -220,20 +220,6 @@ void bcmgenet_phy_power_set(struct net_device *dev, bool enable) · 219 unmodified lines
220	udelay(60);	220	udelay(60);
221	}	221	}
222		222
223	static void bcmgenet_internal_phy_setup(struct net_device *dev)
224	{
225	struct bcmgenet_priv *priv = netdev_priv(dev);
226	u32 reg;
227
228	/* Power up PHY */
229	bcmgenet_phy_power_set(dev, true);
230	/* enable APD */
231	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
232	reg \|= EXT_PWR_DN_EN_LD;
233	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
234	bcmgenet_mii_reset(dev);
235	}
236
237	static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)	223	static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
238	{	224	{
239	u32 reg;	225	u32 reg;
@@ -281,7 +267,6 @@ int bcmgenet_mii_config(struct net_device *dev) · 41 unmodified lines
281		267
282	if (priv->internal_phy) {	268	if (priv->internal_phy) {
283	phy_name = "internal PHY";	269	phy_name = "internal PHY";
284	bcmgenet_internal_phy_setup(dev);
285	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {	270	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
286	phy_name = "MoCA";	271	phy_name = "MoCA";
287	bcmgenet_moca_phy_setup(priv);	272	bcmgenet_moca_phy_setup(priv);

drivers/net/ethernet/brocade/bna/bnad_debugfs.c+1−1

@@ -325,7 +325,7 @@ bnad_debugfs_write_regrd(struct file file, const char __user buf, · 324 unmodified lines
325	return PTR_ERR(kern_buf);	325	return PTR_ERR(kern_buf);
326		326
327	rc = sscanf(kern_buf, "%x:%x", &addr, &len);	327	rc = sscanf(kern_buf, "%x:%x", &addr, &len);
328	if (rc < 2) {	328	if (rc < 2 \|\| len > UINT_MAX >> 2) {
329	netdev_warn(bnad->netdev, "failed to read user buffer\n");	329	netdev_warn(bnad->netdev, "failed to read user buffer\n");
330	kfree(kern_buf);	330	kfree(kern_buf);
331	return -EINVAL;	331	return -EINVAL;

drivers/net/ethernet/cavium/liquidio/lio_main.c+55−55

 	 */
 	struct octeon_sg_entry *sg;
-	u64 sg_dma_ptr;
+	dma_addr_t sg_dma_ptr;
 };
 struct handshake {
 	struct octnic_gather *g;
 	int i;
+	kfree(lio->glist_lock);
+	lio->glist_lock = NULL;
 	if (!lio->glist)
 		return;
 		do {
 			g = (struct octnic_gather *)
 				list_delete_head(&lio->glist[i]);
-			if (g) {
+			if (g)
-				if (g->sg) {
-					dma_unmap_single(&lio->oct_dev->
-							 pci_dev->dev,
-							 g->sg_dma_ptr,
-							 g->sg_size,
-							 DMA_TO_DEVICE);
-					kfree((void *)((unsigned long)g->sg -
-						       g->adjust));
-				}
 				kfree(g);
-			}
 		} while (g);
+		if (lio->glists_virt_base && lio->glists_virt_base[i]) {
+			lio_dma_free(lio->oct_dev,
+				     lio->glist_entry_size * lio->tx_qsize,
+				     lio->glists_virt_base[i],
+				     lio->glists_dma_base[i]);
+		}
 	}
-	kfree((void *)lio->glist);
+	kfree(lio->glists_virt_base);
-	kfree((void *)lio->glist_lock);
+	lio->glists_virt_base = NULL;
+	kfree(lio->glists_dma_base);
+	lio->glists_dma_base = NULL;
+	kfree(lio->glist);
+	lio->glist = NULL;
 }
 /**
 	lio->glist_lock = kcalloc(num_iqs, sizeof(*lio->glist_lock),
 				  GFP_KERNEL);
 	if (!lio->glist_lock)
-		return 1;
+		return -ENOMEM;
 	lio->glist = kcalloc(num_iqs, sizeof(*lio->glist),
 			     GFP_KERNEL);
 	if (!lio->glist) {
-		kfree((void *)lio->glist_lock);
+		kfree(lio->glist_lock);
-		return 1;
+		lio->glist_lock = NULL;
+		return -ENOMEM;
+	}
+	lio->glist_entry_size =
+		ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
+	/* allocate memory to store virtual and dma base address of
+	 * per glist consistent memory
+	 */
+	lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
+					GFP_KERNEL);
+	lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
+				       GFP_KERNEL);
+	if (!lio->glists_virt_base || !lio->glists_dma_base) {
+		delete_glists(lio);
+		return -ENOMEM;
 	}
 	for (i = 0; i < num_iqs; i++) {
 		INIT_LIST_HEAD(&lio->glist[i]);
+		lio->glists_virt_base[i] =
+			lio_dma_alloc(oct,
+				      lio->glist_entry_size * lio->tx_qsize,
+				      &lio->glists_dma_base[i]);
+		if (!lio->glists_virt_base[i]) {
+			delete_glists(lio);
+			return -ENOMEM;
+		}
 		for (j = 0; j < lio->tx_qsize; j++) {
 			g = kzalloc_node(sizeof(*g), GFP_KERNEL,
 					 numa_node);
 			if (!g)
 				break;
-			g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
+			g->sg = lio->glists_virt_base[i] +
-				      OCT_SG_ENTRY_SIZE);
+				(j * lio->glist_entry_size);
-			g->sg = kmalloc_node(g->sg_size + 8,
+			g->sg_dma_ptr = lio->glists_dma_base[i] +
-					     GFP_KERNEL, numa_node);
+					(j * lio->glist_entry_size);
-			if (!g->sg)
-				g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
-			if (!g->sg) {
-				kfree(g);
-				break;
-			}
-			/* The gather component should be aligned on 64-bit
-			 * boundary
-			 */
-			if (((unsigned long)g->sg) & 7) {
-				g->adjust = 8 - (((unsigned long)g->sg) & 7);
-				g->sg = (struct octeon_sg_entry *)
-					((unsigned long)g->sg + g->adjust);
-			}
-			g->sg_dma_ptr = dma_map_single(&oct->pci_dev->dev,
-						       g->sg, g->sg_size,
-						       DMA_TO_DEVICE);
-			if (dma_mapping_error(&oct->pci_dev->dev,
-					      g->sg_dma_ptr)) {
-				kfree((void *)((unsigned long)g->sg -
-					       g->adjust));
-				kfree(g);
-				break;
-			}
 			list_add_tail(&g->list, &lio->glist[i]);
 		}
 		if (j != lio->tx_qsize) {
 			delete_glists(lio);
-			return 1;
+			return -ENOMEM;
 		}
 	}
 		i++;
 	}
-	dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
-				g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
 	iq = skb_iq(lio, skb);
 	spin_lock(&lio->glist_lock[iq]);
 	list_add_tail(&g->list, &lio->glist[iq]);
 		i++;
 	}
-	dma_sync_single_for_cpu(&lio->oct_dev->pci_dev->dev,
-				g->sg_dma_ptr, g->sg_size, DMA_TO_DEVICE);
 	iq = skb_iq(lio, skb);
 	spin_lock(&lio->glist_lock[iq]);
 			i++;
 		}
-		dma_sync_single_for_device(&oct->pci_dev->dev, g->sg_dma_ptr,
-					   g->sg_size, DMA_TO_DEVICE);
 		dptr = g->sg_dma_ptr;
 		if (OCTEON_CN23XX_PF(oct))

drivers/net/ethernet/cavium/liquidio/lio_vf_main.c+55−49

 	 * received from the IP layer.
 	 */
 	struct octeon_sg_entry *sg;
+	dma_addr_t sg_dma_ptr;
 };
 struct octeon_device_priv {
 	struct octnic_gather *g;
 	int i;
+	kfree(lio->glist_lock);
+	lio->glist_lock = NULL;
 	if (!lio->glist)
 		return;
 		do {
 			g = (struct octnic_gather *)
 			    list_delete_head(&lio->glist[i]);
-			if (g) {
+			if (g)
-				if (g->sg)
-					kfree((void *)((unsigned long)g->sg -
-							g->adjust));
 				kfree(g);
-			}
 		} while (g);
+		if (lio->glists_virt_base && lio->glists_virt_base[i]) {
+			lio_dma_free(lio->oct_dev,
+				     lio->glist_entry_size * lio->tx_qsize,
+				     lio->glists_virt_base[i],
+				     lio->glists_dma_base[i]);
+		}
 	}
+	kfree(lio->glists_virt_base);
+	lio->glists_virt_base = NULL;
+	kfree(lio->glists_dma_base);
+	lio->glists_dma_base = NULL;
 	kfree(lio->glist);
-	kfree(lio->glist_lock);
+	lio->glist = NULL;
 }
 /**
 	lio->glist_lock =
 	    kzalloc(sizeof(*lio->glist_lock) * num_iqs, GFP_KERNEL);
 	if (!lio->glist_lock)
-		return 1;
+		return -ENOMEM;
 	lio->glist =
 	    kzalloc(sizeof(*lio->glist) * num_iqs, GFP_KERNEL);
 	if (!lio->glist) {
 		kfree(lio->glist_lock);
-		return 1;
+		lio->glist_lock = NULL;
+		return -ENOMEM;
+	}
+	lio->glist_entry_size =
+		ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
+	/* allocate memory to store virtual and dma base address of
+	 * per glist consistent memory
+	 */
+	lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
+					GFP_KERNEL);
+	lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
+				       GFP_KERNEL);
+	if (!lio->glists_virt_base || !lio->glists_dma_base) {
+		delete_glists(lio);
+		return -ENOMEM;
 	}
 	for (i = 0; i < num_iqs; i++) {
 		INIT_LIST_HEAD(&lio->glist[i]);
+		lio->glists_virt_base[i] =
+			lio_dma_alloc(lio->oct_dev,
+				      lio->glist_entry_size * lio->tx_qsize,
+				      &lio->glists_dma_base[i]);
+		if (!lio->glists_virt_base[i]) {
+			delete_glists(lio);
+			return -ENOMEM;
+		}
 		for (j = 0; j < lio->tx_qsize; j++) {
 			g = kzalloc(sizeof(*g), GFP_KERNEL);
 			if (!g)
 				break;
-			g->sg_size = ((ROUNDUP4(OCTNIC_MAX_SG) >> 2) *
+			g->sg = lio->glists_virt_base[i] +
-				      OCT_SG_ENTRY_SIZE);
+				(j * lio->glist_entry_size);
-			g->sg = kmalloc(g->sg_size + 8, GFP_KERNEL);
+			g->sg_dma_ptr = lio->glists_dma_base[i] +
-			if (!g->sg) {
+					(j * lio->glist_entry_size);
-				kfree(g);
-				break;
-			}
-			/* The gather component should be aligned on 64-bit
-			 * boundary
-			 */
-			if (((unsigned long)g->sg) & 7) {
-				g->adjust = 8 - (((unsigned long)g->sg) & 7);
-				g->sg = (struct octeon_sg_entry *)
-					((unsigned long)g->sg + g->adjust);
-			}
 			list_add_tail(&g->list, &lio->glist[i]);
 		}
 		if (j != lio->tx_qsize) {
 			delete_glists(lio);
-			return 1;
+			return -ENOMEM;
 		}
 	}
 		i++;
 	}
-	dma_unmap_single(&lio->oct_dev->pci_dev->dev,
-			 finfo->dptr, g->sg_size,
-			 DMA_TO_DEVICE);
 	iq = skb_iq(lio, skb);
 	spin_lock(&lio->glist_lock[iq]);
 		i++;
 	}
-	dma_unmap_single(&lio->oct_dev->pci_dev->dev,
-			 finfo->dptr, g->sg_size,
-			 DMA_TO_DEVICE);
 	iq = skb_iq(lio, skb);
 	spin_lock(&lio->glist_lock[iq]);
 			i++;
 		}
-		dptr = dma_map_single(&oct->pci_dev->dev,
+		dptr = g->sg_dma_ptr;
-				      g->sg, g->sg_size,
-				      DMA_TO_DEVICE);
-		if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
-			dev_err(&oct->pci_dev->dev, "%s DMA mapping error 4\n",
-				__func__);
-			dma_unmap_single(&oct->pci_dev->dev, g->sg[0].ptr[0],
-					 skb->len - skb->data_len,
-					 DMA_TO_DEVICE);
-			for (j = 1; j <= frags; j++) {
-				frag = &skb_shinfo(skb)->frags[j - 1];
-				dma_unmap_page(&oct->pci_dev->dev,
-					       g->sg[j >> 2].ptr[j & 3],
-					       frag->size, DMA_TO_DEVICE);
-			}
-			return NETDEV_TX_BUSY;
-		}
 		ndata.cmd.cmd3.dptr = dptr;
 		finfo->dptr = dptr;

drivers/net/ethernet/cavium/liquidio/octeon_config.h+3−3

@@ -71,17 +71,17 @@ · 70 unmodified lines
71	#define CN23XX_MAX_RINGS_PER_VF 8	71	#define CN23XX_MAX_RINGS_PER_VF 8
72		72
73	#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF	73	#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
74	#define CN23XX_MAX_IQ_DESCRIPTORS 2048	74	#define CN23XX_MAX_IQ_DESCRIPTORS 512
75	#define CN23XX_DB_MIN 1	75	#define CN23XX_DB_MIN 1
76	#define CN23XX_DB_MAX 8	76	#define CN23XX_DB_MAX 8
77	#define CN23XX_DB_TIMEOUT 1	77	#define CN23XX_DB_TIMEOUT 1
78		78
79	#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF	79	#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
80	#define CN23XX_MAX_OQ_DESCRIPTORS 2048	80	#define CN23XX_MAX_OQ_DESCRIPTORS 512
81	#define CN23XX_OQ_BUF_SIZE 1536	81	#define CN23XX_OQ_BUF_SIZE 1536
82	#define CN23XX_OQ_PKTSPER_INTR 128	82	#define CN23XX_OQ_PKTSPER_INTR 128
83	/#define CAVIUM_ONLY_CN23XX_RX_PERF/	83	/#define CAVIUM_ONLY_CN23XX_RX_PERF/
84	#define CN23XX_OQ_REFIL_THRESHOLD 128	84	#define CN23XX_OQ_REFIL_THRESHOLD 16
85		85
86	#define CN23XX_OQ_INTR_PKT 64	86	#define CN23XX_OQ_INTR_PKT 64
87	#define CN23XX_OQ_INTR_TIME 100	87	#define CN23XX_OQ_INTR_TIME 100

drivers/net/ethernet/cavium/liquidio/octeon_droq.c+2−15

 			recv_buffer_destroy(droq->recv_buf_list[i].buffer,
 					    pg_info);
-		if (droq->desc_ring && droq->desc_ring[i].info_ptr)
-			lio_unmap_ring_info(oct->pci_dev,
-					    (u64)droq->
-					    desc_ring[i].info_ptr,
-					    OCT_DROQ_INFO_SIZE);
 		droq->recv_buf_list[i].buffer = NULL;
 	}
 	vfree(droq->recv_buf_list);
 	if (droq->info_base_addr)
-		cnnic_free_aligned_dma(oct->pci_dev, droq->info_list,
+		lio_free_info_buffer(oct, droq);
-				       droq->info_alloc_size,
-				       droq->info_base_addr,
-				       droq->info_list_dma);
 	if (droq->desc_ring)
 		lio_dma_free(oct, (droq->max_count * OCT_DROQ_DESC_SIZE),
 	dev_dbg(&oct->pci_dev->dev, "droq[%d]: num_desc: %d\n", q_no,
 		droq->max_count);
-	droq->info_list =
+	droq->info_list = lio_alloc_info_buffer(oct, droq);
-		cnnic_numa_alloc_aligned_dma((droq->max_count *
-					      OCT_DROQ_INFO_SIZE),
-					     &droq->info_alloc_size,
-					     &droq->info_base_addr,
-					     numa_node);
 	if (!droq->info_list) {
 		dev_err(&oct->pci_dev->dev, "Cannot allocate memory for info list.\n");
 		lio_dma_free(oct, (droq->max_count * OCT_DROQ_DESC_SIZE),

drivers/net/ethernet/cavium/liquidio/octeon_droq.h+2−2

@@ -325,10 +325,10 @@ struct octeon_droq { · 324 unmodified lines
325	size_t desc_ring_dma;	325	size_t desc_ring_dma;
326		326
327	/** Info ptr list are allocated at this virtual address. */	327	/** Info ptr list are allocated at this virtual address. */
328	size_t info_base_addr;	328	void *info_base_addr;
329		329
330	/** DMA mapped address of the info list */	330	/** DMA mapped address of the info list */
331	size_t info_list_dma;	331	dma_addr_t info_list_dma;
332		332
333	/** Allocated size of info list. */	333	/** Allocated size of info list. */
334	u32 info_alloc_size;	334	u32 info_alloc_size;

drivers/net/ethernet/cavium/liquidio/octeon_main.h+0−42

@@ -140,48 +140,6 @@ err_release_region: · 139 unmodified lines
140	return 1;	140	return 1;
141	}	141	}
142		142
143	static inline void *
144	cnnic_numa_alloc_aligned_dma(u32 size,
145	u32 *alloc_size,
146	size_t *orig_ptr,
147	int numa_node)
148	{
149	int retries = 0;
150	void *ptr = NULL;
151
152	#define OCTEON_MAX_ALLOC_RETRIES 1
153	do {
154	struct page *page = NULL;
155
156	page = alloc_pages_node(numa_node,
157	GFP_KERNEL,
158	get_order(size));
159	if (!page)
160	page = alloc_pages(GFP_KERNEL,
161	get_order(size));
162	ptr = (void *)page_address(page);
163	if ((unsigned long)ptr & 0x07) {
164	__free_pages(page, get_order(size));
165	ptr = NULL;
166	/* Increment the size required if the first
167	* attempt failed.
168	*/
169	if (!retries)
170	size += 7;
171	}
172	retries++;
173	} while ((retries <= OCTEON_MAX_ALLOC_RETRIES) && !ptr);
174
175	*alloc_size = size;
176	*orig_ptr = (unsigned long)ptr;
177	if ((unsigned long)ptr & 0x07)
178	ptr = (void *)(((unsigned long)ptr + 7) & ~(7UL));
179	return ptr;
180	}
181
182	#define cnnic_free_aligned_dma(pci_dev, ptr, size, orig_ptr, dma_addr) \
183	free_pages(orig_ptr, get_order(size))
184
185	static inline int	143	static inline int
186	sleep_cond(wait_queue_head_t wait_queue, int condition)	144	sleep_cond(wait_queue_head_t wait_queue, int condition)
187	{	145	{

drivers/net/ethernet/cavium/liquidio/octeon_network.h+27−16

 	/** Array of gather component linked lists */
 	struct list_head *glist;
+	void **glists_virt_base;
+	dma_addr_t *glists_dma_base;
+	u32 glist_entry_size;
 	/** Pointer to the NIC properties for the Octeon device this network
 	 *  interface is associated with.
 #define lio_dma_free(oct, size, virt_addr, dma_addr) \
 	dma_free_coherent(&(oct)->pci_dev->dev, size, virt_addr, dma_addr)
+static inline void *
+lio_alloc_info_buffer(struct octeon_device *oct,
+		      struct octeon_droq *droq)
+{
+	void *virt_ptr;
+	virt_ptr = lio_dma_alloc(oct, (droq->max_count * OCT_DROQ_INFO_SIZE),
+				 &droq->info_list_dma);
+	if (virt_ptr) {
+		droq->info_alloc_size = droq->max_count * OCT_DROQ_INFO_SIZE;
+		droq->info_base_addr = virt_ptr;
+	}
+	return virt_ptr;
+}
+static inline void lio_free_info_buffer(struct octeon_device *oct,
+					struct octeon_droq *droq)
+{
+	lio_dma_free(oct, droq->info_alloc_size, droq->info_base_addr,
+		     droq->info_list_dma);
+}
 static inline
 void *get_rbd(struct sk_buff *skb)
 {
 static inline u64
 lio_map_ring_info(struct octeon_droq *droq, u32 i)
 {
-	dma_addr_t dma_addr;
+	return droq->info_list_dma + (i * sizeof(struct octeon_droq_info));
-	struct octeon_device *oct = droq->oct_dev;
-	dma_addr = dma_map_single(&oct->pci_dev->dev, &droq->info_list[i],
-				  OCT_DROQ_INFO_SIZE, DMA_FROM_DEVICE);
-	WARN_ON(dma_mapping_error(&oct->pci_dev->dev, dma_addr));
-	return (u64)dma_addr;
-}
-static inline void
-lio_unmap_ring_info(struct pci_dev *pci_dev,
-		    u64 info_ptr, u32 size)
-{
-	dma_unmap_single(&pci_dev->dev, info_ptr, size, DMA_FROM_DEVICE);
 }
 static inline u64

drivers/net/ethernet/cavium/thunder/nic.h+1−0

@@ -269,6 +269,7 @@ struct nicvf { · 268 unmodified lines
269	#define MAX_QUEUES_PER_QSET 8	269	#define MAX_QUEUES_PER_QSET 8
270	struct queue_set *qs;	270	struct queue_set *qs;
271	struct nicvf_cq_poll *napi[8];	271	struct nicvf_cq_poll *napi[8];
		272	void *iommu_domain;
272	u8 vf_id;	273	u8 vf_id;
273	u8 sqs_id;	274	u8 sqs_id;
274	bool sqs_mode;	275	bool sqs_mode;

drivers/net/ethernet/cavium/thunder/nicvf_main.c+11−1

 #include <linux/log2.h>
 #include <linux/prefetch.h>
 #include <linux/irq.h>
+#include <linux/iommu.h>
 #include "nic_reg.h"
 #include "nic.h"
 			/* Get actual TSO descriptors and free them */
 			tso_sqe =
 			 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
+			nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
+						 tso_sqe->subdesc_cnt);
 			nicvf_put_sq_desc(sq, tso_sqe->subdesc_cnt + 1);
+		} else {
+			nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr,
+						 hdr->subdesc_cnt);
 		}
 		nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
 		prefetch(skb);
 {
 	struct sk_buff *skb;
 	struct nicvf *nic = netdev_priv(netdev);
+	struct nicvf *snic = nic;
 	int err = 0;
 	int rq_idx;
 	if (err && !cqe_rx->rb_cnt)
 		return;
-	skb = nicvf_get_rcv_skb(nic, cqe_rx);
+	skb = nicvf_get_rcv_skb(snic, cqe_rx);
 	if (!skb) {
 		netdev_dbg(nic->netdev, "Packet not received\n");
 		return;
 	if (!pass1_silicon(nic->pdev))
 		nic->hw_tso = true;
+	/* Get iommu domain for iova to physical addr conversion */
+	nic->iommu_domain = iommu_get_domain_for_dev(dev);
 	pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
 	if (sdevid == 0xA134)
 		nic->t88 = true;

drivers/net/ethernet/cavium/thunder/nicvf_queues.c+145−39

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	#include <linux/netdevice.h>	10	#include <linux/netdevice.h>
11	#include <linux/ip.h>	11	#include <linux/ip.h>
12	#include <linux/etherdevice.h>	12	#include <linux/etherdevice.h>
		13	#include <linux/iommu.h>
13	#include <net/ip.h>	14	#include <net/ip.h>
14	#include <net/tso.h>	15	#include <net/tso.h>
15		16
@@ -18,6 +19,16 @@ · 2 unmodified lines
18	#include "q_struct.h"	19	#include "q_struct.h"
19	#include "nicvf_queues.h"	20	#include "nicvf_queues.h"
20		21
		22	#define NICVF_PAGE_ORDER ((PAGE_SIZE <= 4096) ? PAGE_ALLOC_COSTLY_ORDER : 0)
		23
		24	static inline u64 nicvf_iova_to_phys(struct nicvf *nic, dma_addr_t dma_addr)
		25	{
		26	/* Translation is installed only when IOMMU is present */
		27	if (nic->iommu_domain)
		28	return iommu_iova_to_phys(nic->iommu_domain, dma_addr);
		29	return dma_addr;
		30	}
		31
21	static void nicvf_get_page(struct nicvf *nic)	32	static void nicvf_get_page(struct nicvf *nic)
22	{	33	{
23	if (!nic->rb_pageref \|\| !nic->rb_page)	34	if (!nic->rb_pageref \|\| !nic->rb_page)
@@ -87,7 +98,7 @@ static void nicvf_free_q_desc_mem(struct nicvf nic, struct q_desc_mem dmem) · 63 unmodified lines
87	static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp,	98	static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp,
88	u32 buf_len, u64 **rbuf)	99	u32 buf_len, u64 **rbuf)
89	{	100	{
90	int order = (PAGE_SIZE <= 4096) ? PAGE_ALLOC_COSTLY_ORDER : 0;	101	int order = NICVF_PAGE_ORDER;
91		102
92	/* Check if request can be accomodated in previous allocated page */	103	/* Check if request can be accomodated in previous allocated page */
93	if (nic->rb_page &&	104	if (nic->rb_page &&
@@ -97,22 +108,27 @@ static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp, · 3 unmodified lines
97	}	108	}
98		109
99	nicvf_get_page(nic);	110	nicvf_get_page(nic);
100	nic->rb_page = NULL;
101		111
102	/* Allocate a new page */	112	/* Allocate a new page */
		113	nic->rb_page = alloc_pages(gfp \| __GFP_COMP \| __GFP_NOWARN,
		114	order);
103	if (!nic->rb_page) {	115	if (!nic->rb_page) {
104	nic->rb_page = alloc_pages(gfp \| __GFP_COMP \| __GFP_NOWARN,	116	this_cpu_inc(nic->pnicvf->drv_stats->rcv_buffer_alloc_failures);
105	order);	117	return -ENOMEM;
106	if (!nic->rb_page) {
107	this_cpu_inc(nic->pnicvf->drv_stats->
108	rcv_buffer_alloc_failures);
109	return -ENOMEM;
110	}
111	nic->rb_page_offset = 0;
112	}	118	}
113		119	nic->rb_page_offset = 0;
114	ret:	120	ret:
115	rbuf = (u64 )((u64)page_address(nic->rb_page) + nic->rb_page_offset);	121	/* HW will ensure data coherency, CPU sync not required */
		122	rbuf = (u64 )((u64)dma_map_page_attrs(&nic->pdev->dev, nic->rb_page,
		123	nic->rb_page_offset, buf_len,
		124	DMA_FROM_DEVICE,
		125	DMA_ATTR_SKIP_CPU_SYNC));
		126	if (dma_mapping_error(&nic->pdev->dev, (dma_addr_t)*rbuf)) {
		127	if (!nic->rb_page_offset)
		128	__free_pages(nic->rb_page, order);
		129	nic->rb_page = NULL;
		130	return -ENOMEM;
		131	}
116	nic->rb_page_offset += buf_len;	132	nic->rb_page_offset += buf_len;
117		133
118	return 0;	134	return 0;
@@ -158,16 +174,21 @@ static int nicvf_init_rbdr(struct nicvf nic, struct rbdr rbdr, · 39 unmodified lines
158	rbdr->dma_size = buf_size;	174	rbdr->dma_size = buf_size;
159	rbdr->enable = true;	175	rbdr->enable = true;
160	rbdr->thresh = RBDR_THRESH;	176	rbdr->thresh = RBDR_THRESH;
		177	rbdr->head = 0;
		178	rbdr->tail = 0;
161		179
162	nic->rb_page = NULL;	180	nic->rb_page = NULL;
163	for (idx = 0; idx < ring_len; idx++) {	181	for (idx = 0; idx < ring_len; idx++) {
164	err = nicvf_alloc_rcv_buffer(nic, GFP_KERNEL, RCV_FRAG_LEN,	182	err = nicvf_alloc_rcv_buffer(nic, GFP_KERNEL, RCV_FRAG_LEN,
165	&rbuf);	183	&rbuf);
166	if (err)	184	if (err) {
		185	/* To free already allocated and mapped ones */
		186	rbdr->tail = idx - 1;
167	return err;	187	return err;
		188	}
168		189
169	desc = GET_RBDR_DESC(rbdr, idx);	190	desc = GET_RBDR_DESC(rbdr, idx);
170	desc->buf_addr = virt_to_phys(rbuf) >> NICVF_RCV_BUF_ALIGN;	191	desc->buf_addr = (u64)rbuf >> NICVF_RCV_BUF_ALIGN;
171	}	192	}
172		193
173	nicvf_get_page(nic);	194	nicvf_get_page(nic);
@@ -179,7 +200,7 @@ static int nicvf_init_rbdr(struct nicvf nic, struct rbdr rbdr, · 5 unmodified lines
179	static void nicvf_free_rbdr(struct nicvf nic, struct rbdr rbdr)	200	static void nicvf_free_rbdr(struct nicvf nic, struct rbdr rbdr)
180	{	201	{
181	int head, tail;	202	int head, tail;
182	u64 buf_addr;	203	u64 buf_addr, phys_addr;
183	struct rbdr_entry_t *desc;	204	struct rbdr_entry_t *desc;
184		205
185	if (!rbdr)	206	if (!rbdr)
@@ -192,18 +213,26 @@ static void nicvf_free_rbdr(struct nicvf nic, struct rbdr rbdr) · 6 unmodified lines
192	head = rbdr->head;	213	head = rbdr->head;
193	tail = rbdr->tail;	214	tail = rbdr->tail;
194		215
195	/* Free SKBs */	216	/* Release page references */
196	while (head != tail) {	217	while (head != tail) {
197	desc = GET_RBDR_DESC(rbdr, head);	218	desc = GET_RBDR_DESC(rbdr, head);
198	buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN;	219	buf_addr = ((u64)desc->buf_addr) << NICVF_RCV_BUF_ALIGN;
199	put_page(virt_to_page(phys_to_virt(buf_addr)));	220	phys_addr = nicvf_iova_to_phys(nic, buf_addr);
		221	dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
		222	DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
		223	if (phys_addr)
		224	put_page(virt_to_page(phys_to_virt(phys_addr)));
200	head++;	225	head++;
201	head &= (rbdr->dmem.q_len - 1);	226	head &= (rbdr->dmem.q_len - 1);
202	}	227	}
203	/* Free SKB of tail desc */	228	/* Release buffer of tail desc */
204	desc = GET_RBDR_DESC(rbdr, tail);	229	desc = GET_RBDR_DESC(rbdr, tail);
205	buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN;	230	buf_addr = ((u64)desc->buf_addr) << NICVF_RCV_BUF_ALIGN;
206	put_page(virt_to_page(phys_to_virt(buf_addr)));	231	phys_addr = nicvf_iova_to_phys(nic, buf_addr);
		232	dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
		233	DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
		234	if (phys_addr)
		235	put_page(virt_to_page(phys_to_virt(phys_addr)));
207		236
208	/* Free RBDR ring */	237	/* Free RBDR ring */
209	nicvf_free_q_desc_mem(nic, &rbdr->dmem);	238	nicvf_free_q_desc_mem(nic, &rbdr->dmem);
@@ -250,7 +279,7 @@ refill: · 40 unmodified lines
250	break;	279	break;
251		280
252	desc = GET_RBDR_DESC(rbdr, tail);	281	desc = GET_RBDR_DESC(rbdr, tail);
253	desc->buf_addr = virt_to_phys(rbuf) >> NICVF_RCV_BUF_ALIGN;	282	desc->buf_addr = (u64)rbuf >> NICVF_RCV_BUF_ALIGN;
254	refill_rb_cnt--;	283	refill_rb_cnt--;
255	new_rb++;	284	new_rb++;
256	}	285	}
@@ -361,9 +390,29 @@ static int nicvf_init_snd_queue(struct nicvf *nic, · 104 unmodified lines
361	return 0;	390	return 0;
362	}	391	}
363		392
		393	void nicvf_unmap_sndq_buffers(struct nicvf nic, struct snd_queue sq,
		394	int hdr_sqe, u8 subdesc_cnt)
		395	{
		396	u8 idx;
		397	struct sq_gather_subdesc *gather;
		398
		399	/* Unmap DMA mapped skb data buffers */
		400	for (idx = 0; idx < subdesc_cnt; idx++) {
		401	hdr_sqe++;
		402	hdr_sqe &= (sq->dmem.q_len - 1);
		403	gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, hdr_sqe);
		404	/* HW will ensure data coherency, CPU sync not required */
		405	dma_unmap_page_attrs(&nic->pdev->dev, gather->addr,
		406	gather->size, DMA_TO_DEVICE,
		407	DMA_ATTR_SKIP_CPU_SYNC);
		408	}
		409	}
		410
364	static void nicvf_free_snd_queue(struct nicvf nic, struct snd_queue sq)	411	static void nicvf_free_snd_queue(struct nicvf nic, struct snd_queue sq)
365	{	412	{
366	struct sk_buff *skb;	413	struct sk_buff *skb;
		414	struct sq_hdr_subdesc *hdr;
		415	struct sq_hdr_subdesc *tso_sqe;
367		416
368	if (!sq)	417	if (!sq)
369	return;	418	return;
@@ -379,8 +428,22 @@ static void nicvf_free_snd_queue(struct nicvf nic, struct snd_queue sq) · 9 unmodified lines
379	smp_rmb();	428	smp_rmb();
380	while (sq->head != sq->tail) {	429	while (sq->head != sq->tail) {
381	skb = (struct sk_buff *)sq->skbuff[sq->head];	430	skb = (struct sk_buff *)sq->skbuff[sq->head];
382	if (skb)	431	if (!skb)
383	dev_kfree_skb_any(skb);	432	goto next;
		433	hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
		434	/* Check for dummy descriptor used for HW TSO offload on 88xx */
		435	if (hdr->dont_send) {
		436	/* Get actual TSO descriptors and unmap them */
		437	tso_sqe =
		438	(struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
		439	nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
		440	tso_sqe->subdesc_cnt);
		441	} else {
		442	nicvf_unmap_sndq_buffers(nic, sq, sq->head,
		443	hdr->subdesc_cnt);
		444	}
		445	dev_kfree_skb_any(skb);
		446	next:
384	sq->head++;	447	sq->head++;
385	sq->head &= (sq->dmem.q_len - 1);	448	sq->head &= (sq->dmem.q_len - 1);
386	}	449	}
@@ -559,9 +622,11 @@ static void nicvf_rcv_queue_config(struct nicvf nic, struct queue_set qs, · 172 unmodified lines
559	nicvf_send_msg_to_pf(nic, &mbx);	622	nicvf_send_msg_to_pf(nic, &mbx);
560		623
561	if (!nic->sqs_mode && (qidx == 0)) {	624	if (!nic->sqs_mode && (qidx == 0)) {
562	/* Enable checking L3/L4 length and TCP/UDP checksums */	625	/* Enable checking L3/L4 length and TCP/UDP checksums
		626	* Also allow IPv6 pkts with zero UDP checksum.
		627	*/
563	nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,	628	nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,
564	(BIT(24) \| BIT(23) \| BIT(21)));	629	(BIT(24) \| BIT(23) \| BIT(21) \| BIT(20)));
565	nicvf_config_vlan_stripping(nic, nic->netdev->features);	630	nicvf_config_vlan_stripping(nic, nic->netdev->features);
566	}	631	}
567		632
@@ -882,6 +947,14 @@ static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt) · 314 unmodified lines
882	return qentry;	947	return qentry;
883	}	948	}
884		949
		950	/* Rollback to previous tail pointer when descriptors not used */
		951	static inline void nicvf_rollback_sq_desc(struct snd_queue *sq,
		952	int qentry, int desc_cnt)
		953	{
		954	sq->tail = qentry;
		955	atomic_add(desc_cnt, &sq->free_cnt);
		956	}
		957
885	/* Free descriptor back to SQ for future use */	958	/* Free descriptor back to SQ for future use */
886	void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)	959	void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)
887	{	960	{
@@ -1207,8 +1280,9 @@ int nicvf_sq_append_skb(struct nicvf nic, struct snd_queue sq, · 319 unmodified lines
1207	struct sk_buff *skb, u8 sq_num)	1280	struct sk_buff *skb, u8 sq_num)
1208	{	1281	{
1209	int i, size;	1282	int i, size;
1210	int subdesc_cnt, tso_sqe = 0;	1283	int subdesc_cnt, hdr_sqe = 0;
1211	int qentry;	1284	int qentry;
		1285	u64 dma_addr;
1212		1286
1213	subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);	1287	subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);
1214	if (subdesc_cnt > atomic_read(&sq->free_cnt))	1288	if (subdesc_cnt > atomic_read(&sq->free_cnt))
@@ -1223,12 +1297,21 @@ int nicvf_sq_append_skb(struct nicvf nic, struct snd_queue sq, · 8 unmodified lines
1223	/* Add SQ header subdesc */	1297	/* Add SQ header subdesc */
1224	nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1,	1298	nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1,
1225	skb, skb->len);	1299	skb, skb->len);
1226	tso_sqe = qentry;	1300	hdr_sqe = qentry;
1227		1301
1228	/* Add SQ gather subdescs */	1302	/* Add SQ gather subdescs */
1229	qentry = nicvf_get_nxt_sqentry(sq, qentry);	1303	qentry = nicvf_get_nxt_sqentry(sq, qentry);
1230	size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;	1304	size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1231	nicvf_sq_add_gather_subdesc(sq, qentry, size, virt_to_phys(skb->data));	1305	/* HW will ensure data coherency, CPU sync not required */
		1306	dma_addr = dma_map_page_attrs(&nic->pdev->dev, virt_to_page(skb->data),
		1307	offset_in_page(skb->data), size,
		1308	DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
		1309	if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
		1310	nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
		1311	return 0;
		1312	}
		1313
		1314	nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
1232		1315
1233	/* Check for scattered buffer */	1316	/* Check for scattered buffer */
1234	if (!skb_is_nonlinear(skb))	1317	if (!skb_is_nonlinear(skb))
@@ -1241,15 +1324,26 @@ int nicvf_sq_append_skb(struct nicvf nic, struct snd_queue sq, · 6 unmodified lines
1241		1324
1242	qentry = nicvf_get_nxt_sqentry(sq, qentry);	1325	qentry = nicvf_get_nxt_sqentry(sq, qentry);
1243	size = skb_frag_size(frag);	1326	size = skb_frag_size(frag);
1244	nicvf_sq_add_gather_subdesc(sq, qentry, size,	1327	dma_addr = dma_map_page_attrs(&nic->pdev->dev,
1245	virt_to_phys(	1328	skb_frag_page(frag),
1246	skb_frag_address(frag)));	1329	frag->page_offset, size,
		1330	DMA_TO_DEVICE,
		1331	DMA_ATTR_SKIP_CPU_SYNC);
		1332	if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
		1333	/* Free entire chain of mapped buffers
		1334	* here 'i' = frags mapped + above mapped skb->data
		1335	*/
		1336	nicvf_unmap_sndq_buffers(nic, sq, hdr_sqe, i);
		1337	nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
		1338	return 0;
		1339	}
		1340	nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
1247	}	1341	}
1248		1342
1249	doorbell:	1343	doorbell:
1250	if (nic->t88 && skb_shinfo(skb)->gso_size) {	1344	if (nic->t88 && skb_shinfo(skb)->gso_size) {
1251	qentry = nicvf_get_nxt_sqentry(sq, qentry);	1345	qentry = nicvf_get_nxt_sqentry(sq, qentry);
1252	nicvf_sq_add_cqe_subdesc(sq, qentry, tso_sqe, skb);	1346	nicvf_sq_add_cqe_subdesc(sq, qentry, hdr_sqe, skb);
1253	}	1347	}
1254		1348
1255	nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt);	1349	nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt);
@@ -1282,6 +1376,7 @@ struct sk_buff nicvf_get_rcv_skb(struct nicvf nic, struct cqe_rx_t *cqe_rx) · 26 unmodified lines
1282	int offset;	1376	int offset;
1283	u16 *rb_lens = NULL;	1377	u16 *rb_lens = NULL;
1284	u64 *rb_ptrs = NULL;	1378	u64 *rb_ptrs = NULL;
		1379	u64 phys_addr;
1285		1380
1286	rb_lens = (void )cqe_rx + (3 sizeof(u64));	1381	rb_lens = (void )cqe_rx + (3 sizeof(u64));
1287	/* Except 88xx pass1 on all other chips CQE_RX2_S is added to	1382	/* Except 88xx pass1 on all other chips CQE_RX2_S is added to
@@ -1296,15 +1391,23 @@ struct sk_buff nicvf_get_rcv_skb(struct nicvf nic, struct cqe_rx_t *cqe_rx) · 8 unmodified lines
1296	else	1391	else
1297	rb_ptrs = (void )cqe_rx + (7 sizeof(u64));	1392	rb_ptrs = (void )cqe_rx + (7 sizeof(u64));
1298		1393
1299	netdev_dbg(nic->netdev, "%s rb_cnt %d rb0_ptr %llx rb0_sz %d\n",
1300	__func__, cqe_rx->rb_cnt, cqe_rx->rb0_ptr, cqe_rx->rb0_sz);
1301
1302	for (frag = 0; frag < cqe_rx->rb_cnt; frag++) {	1394	for (frag = 0; frag < cqe_rx->rb_cnt; frag++) {
1303	payload_len = rb_lens[frag_num(frag)];	1395	payload_len = rb_lens[frag_num(frag)];
		1396	phys_addr = nicvf_iova_to_phys(nic, *rb_ptrs);
		1397	if (!phys_addr) {
		1398	if (skb)
		1399	dev_kfree_skb_any(skb);
		1400	return NULL;
		1401	}
		1402
1304	if (!frag) {	1403	if (!frag) {
1305	/* First fragment */	1404	/* First fragment */
		1405	dma_unmap_page_attrs(&nic->pdev->dev,
		1406	*rb_ptrs - cqe_rx->align_pad,
		1407	RCV_FRAG_LEN, DMA_FROM_DEVICE,
		1408	DMA_ATTR_SKIP_CPU_SYNC);
1306	skb = nicvf_rb_ptr_to_skb(nic,	1409	skb = nicvf_rb_ptr_to_skb(nic,
1307	*rb_ptrs - cqe_rx->align_pad,	1410	phys_addr - cqe_rx->align_pad,
1308	payload_len);	1411	payload_len);
1309	if (!skb)	1412	if (!skb)
1310	return NULL;	1413	return NULL;
@@ -1312,8 +1415,11 @@ struct sk_buff nicvf_get_rcv_skb(struct nicvf nic, struct cqe_rx_t *cqe_rx) · 1 unmodified line
1312	skb_put(skb, payload_len);	1415	skb_put(skb, payload_len);
1313	} else {	1416	} else {
1314	/* Add fragments */	1417	/* Add fragments */
1315	page = virt_to_page(phys_to_virt(*rb_ptrs));	1418	dma_unmap_page_attrs(&nic->pdev->dev, *rb_ptrs,
1316	offset = phys_to_virt(*rb_ptrs) - page_address(page);	1419	RCV_FRAG_LEN, DMA_FROM_DEVICE,
		1420	DMA_ATTR_SKIP_CPU_SYNC);
		1421	page = virt_to_page(phys_to_virt(phys_addr));
		1422	offset = phys_to_virt(phys_addr) - page_address(page);
1317	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,	1423	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1318	offset, payload_len, RCV_FRAG_LEN);	1424	offset, payload_len, RCV_FRAG_LEN);
1319	}	1425	}

drivers/net/ethernet/cavium/thunder/nicvf_queues.h+3−1

 #define RCV_BUF_COUNT		(1ULL << (RBDR_SIZE + 13))
 #define MAX_RCV_BUF_COUNT	(1ULL << (RBDR_SIZE6 + 13))
 #define RBDR_THRESH		(RCV_BUF_COUNT / 2)
-#define DMA_BUFFER_LEN		2048 /* In multiples of 128bytes */
+#define DMA_BUFFER_LEN		1536 /* In multiples of 128bytes */
 #define RCV_FRAG_LEN	 (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
 			 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
 #define	CQ_ERR_MASK	(CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
+void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
+			      int hdr_sqe, u8 subdesc_cnt);
 void nicvf_config_vlan_stripping(struct nicvf *nic,
 				 netdev_features_t features);
 int nicvf_set_qset_resources(struct nicvf *nic);

drivers/net/ethernet/cavium/thunder/thunder_bgx.c+45−19

 	return 1;
 }
+static int max_bgx_per_node;
+static void set_max_bgx_per_node(struct pci_dev *pdev)
+{
+	u16 sdevid;
+	if (max_bgx_per_node)
+		return;
+	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
+	switch (sdevid) {
+	case PCI_SUBSYS_DEVID_81XX_BGX:
+		max_bgx_per_node = MAX_BGX_PER_CN81XX;
+		break;
+	case PCI_SUBSYS_DEVID_83XX_BGX:
+		max_bgx_per_node = MAX_BGX_PER_CN83XX;
+		break;
+	case PCI_SUBSYS_DEVID_88XX_BGX:
+	default:
+		max_bgx_per_node = MAX_BGX_PER_CN88XX;
+		break;
+	}
+}
+static struct bgx *get_bgx(int node, int bgx_idx)
+{
+	int idx = (node * max_bgx_per_node) + bgx_idx;
+	return bgx_vnic[idx];
+}
 /* Return number of BGX present in HW */
 unsigned bgx_get_map(int node)
 {
 	int i;
 	unsigned map = 0;
-	for (i = 0; i < MAX_BGX_PER_NODE; i++) {
+	for (i = 0; i < max_bgx_per_node; i++) {
-		if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
+		if (bgx_vnic[(node * max_bgx_per_node) + i])
 			map |= (1 << i);
 	}
 {
 	struct bgx *bgx;
-	bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	bgx = get_bgx(node, bgx_idx);
 	if (bgx)
 		return bgx->lmac_count;
 	struct bgx *bgx;
 	struct lmac *lmac;
-	bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	bgx = get_bgx(node, bgx_idx);
 	if (!bgx)
 		return;
 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
 {
-	struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	struct bgx *bgx = get_bgx(node, bgx_idx);
 	if (bgx)
 		return bgx->lmac[lmacid].mac;
 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
 {
-	struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	struct bgx *bgx = get_bgx(node, bgx_idx);
 	if (!bgx)
 		return;
 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
 {
-	struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	struct bgx *bgx = get_bgx(node, bgx_idx);
 	struct lmac *lmac;
 	u64 cfg;
 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
 {
 	struct pfc *pfc = (struct pfc *)pause;
-	struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
+	struct bgx *bgx = get_bgx(node, bgx_idx);
 	struct lmac *lmac;
 	u64 cfg;
 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
 {
 	struct pfc *pfc = (struct pfc *)pause;
-	struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
+	struct bgx *bgx = get_bgx(node, bgx_idx);
 	struct lmac *lmac;
 	u64 cfg;
 {
 	struct bgx *bgx;
-	bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	bgx = get_bgx(node, bgx_idx);
 	if (!bgx)
 		return 0;
 {
 	struct bgx *bgx;
-	bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	bgx = get_bgx(node, bgx_idx);
 	if (!bgx)
 		return 0;
 	struct lmac *lmac;
 	u64    cfg;
-	bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+	bgx = get_bgx(node, bgx_idx);
 	if (!bgx)
 		return;
 			dev_info(dev, "%s: 40G_KR4\n", (char *)str);
 		break;
 	case BGX_MODE_QSGMII:
-		if ((lmacid == 0) &&
-		    (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
-			return;
-		if ((lmacid == 2) &&
-		    (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
-			return;
 		dev_info(dev, "%s: QSGMII\n", (char *)str);
 		break;
 	case BGX_MODE_RGMII:
 		goto err_release_regions;
 	}
+	set_max_bgx_per_node(pdev);
 	pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
 	if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
 		bgx->bgx_id = (pci_resource_start(pdev,
 			PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
-		bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
+		bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
 		bgx->max_lmac = MAX_LMAC_PER_BGX;
 		bgx_vnic[bgx->bgx_id] = bgx;
 	} else {

drivers/net/ethernet/cavium/thunder/thunder_bgx.h+0−1

@@ -22,7 +22,6 @@ · 21 unmodified lines
22	#define MAX_BGX_PER_CN88XX 2	22	#define MAX_BGX_PER_CN88XX 2
23	#define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */	23	#define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */
24	#define MAX_BGX_PER_CN83XX 4	24	#define MAX_BGX_PER_CN83XX 4
25	#define MAX_BGX_PER_NODE 4
26	#define MAX_LMAC_PER_BGX 4	25	#define MAX_LMAC_PER_BGX 4
27	#define MAX_BGX_CHANS_PER_LMAC 16	26	#define MAX_BGX_CHANS_PER_LMAC 16
28	#define MAX_DMAC_PER_LMAC 8	27	#define MAX_DMAC_PER_LMAC 8

drivers/net/ethernet/ibm/emac/core.c+17−8

 static int emac_dt_phy_connect(struct emac_instance *dev,
 			       struct device_node *phy_handle)
 {
-	int res;
 	dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
 				    GFP_KERNEL);
 	if (!dev->phy.def)
 {
 	struct device_node *np = dev->ofdev->dev.of_node;
 	struct device_node *phy_handle;
-	int res = 0;
+	int res = 1;
 	phy_handle = of_parse_phandle(np, "phy-handle", 0);
 	if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
 		int res = emac_dt_phy_probe(dev);
-		mutex_unlock(&emac_phy_map_lock);
+		switch (res) {
-		if (!res)
+		case 1:
+			/* No phy-handle property configured.
+			 * Continue with the existing phy probe
+			 * and setup code.
+			 */
+			break;
+		case 0:
+			mutex_unlock(&emac_phy_map_lock);
 			goto init_phy;
-		dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
+		default:
-			res);
+			mutex_unlock(&emac_phy_map_lock);
-		return res;
+			dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
+				res);
+			return res;
+		}
 	}
 	if (dev->phy_address != 0xffffffff)

drivers/net/ethernet/ibm/ibmvnic.c+36−9

 	send_map_query(adapter);
 	for (i = 0; i < rxadd_subcrqs; i++) {
 		init_rx_pool(adapter, &adapter->rx_pool[i],
-			     IBMVNIC_BUFFS_PER_POOL, i,
+			     adapter->req_rx_add_entries_per_subcrq, i,
 			     be64_to_cpu(size_array[i]), 1);
 		if (alloc_rx_pool(adapter, &adapter->rx_pool[i])) {
 			dev_err(dev, "Couldn't alloc rx pool\n");
 	for (i = 0; i < tx_subcrqs; i++) {
 		tx_pool = &adapter->tx_pool[i];
 		tx_pool->tx_buff =
-		    kcalloc(adapter->max_tx_entries_per_subcrq,
+		    kcalloc(adapter->req_tx_entries_per_subcrq,
 			    sizeof(struct ibmvnic_tx_buff), GFP_KERNEL);
 		if (!tx_pool->tx_buff)
 			goto tx_pool_alloc_failed;
 		if (alloc_long_term_buff(adapter, &tx_pool->long_term_buff,
-					 adapter->max_tx_entries_per_subcrq *
+					 adapter->req_tx_entries_per_subcrq *
 					 adapter->req_mtu))
 			goto tx_ltb_alloc_failed;
 		tx_pool->free_map =
-		    kcalloc(adapter->max_tx_entries_per_subcrq,
+		    kcalloc(adapter->req_tx_entries_per_subcrq,
 			    sizeof(int), GFP_KERNEL);
 		if (!tx_pool->free_map)
 			goto tx_fm_alloc_failed;
-		for (j = 0; j < adapter->max_tx_entries_per_subcrq; j++)
+		for (j = 0; j < adapter->req_tx_entries_per_subcrq; j++)
 			tx_pool->free_map[j] = j;
 		tx_pool->consumer_index = 0;
 	u8 *hdrs = (u8 *)&adapter->tx_rx_desc_req;
 	struct device *dev = &adapter->vdev->dev;
 	struct ibmvnic_tx_buff *tx_buff = NULL;
+	struct ibmvnic_sub_crq_queue *tx_scrq;
 	struct ibmvnic_tx_pool *tx_pool;
 	unsigned int tx_send_failed = 0;
 	unsigned int tx_map_failed = 0;
 	int ret = 0;
 	tx_pool = &adapter->tx_pool[queue_num];
+	tx_scrq = adapter->tx_scrq[queue_num];
 	txq = netdev_get_tx_queue(netdev, skb_get_queue_mapping(skb));
 	handle_array = (u64 *)((u8 *)(adapter->login_rsp_buf) +
 				   be32_to_cpu(adapter->login_rsp_buf->
 	tx_pool->consumer_index =
 	    (tx_pool->consumer_index + 1) %
-		adapter->max_tx_entries_per_subcrq;
+		adapter->req_tx_entries_per_subcrq;
 	tx_buff = &tx_pool->tx_buff[index];
 	tx_buff->skb = skb;
 		if (tx_pool->consumer_index == 0)
 			tx_pool->consumer_index =
-				adapter->max_tx_entries_per_subcrq - 1;
+				adapter->req_tx_entries_per_subcrq - 1;
 		else
 			tx_pool->consumer_index--;
 		ret = NETDEV_TX_BUSY;
 		goto out;
 	}
+	atomic_inc(&tx_scrq->used);
+	if (atomic_read(&tx_scrq->used) >= adapter->req_tx_entries_per_subcrq) {
+		netdev_info(netdev, "Stopping queue %d\n", queue_num);
+		netif_stop_subqueue(netdev, queue_num);
+	}
 	tx_packets++;
 	tx_bytes += skb->len;
 	txq->trans_start = jiffies;
 	scrq->adapter = adapter;
 	scrq->size = 4 * PAGE_SIZE / sizeof(*scrq->msgs);
 	scrq->cur = 0;
+	atomic_set(&scrq->used, 0);
 	scrq->rx_skb_top = NULL;
 	spin_lock_init(&scrq->lock);
 				release_sub_crq_queue(adapter,
 						      adapter->tx_scrq[i]);
 			}
+		kfree(adapter->tx_scrq);
 		adapter->tx_scrq = NULL;
 	}
 				release_sub_crq_queue(adapter,
 						      adapter->rx_scrq[i]);
 			}
+		kfree(adapter->rx_scrq);
 		adapter->rx_scrq = NULL;
 	}
 }
 						 DMA_TO_DEVICE);
 			}
-			if (txbuff->last_frag)
+			if (txbuff->last_frag) {
+				atomic_dec(&scrq->used);
+				if (atomic_read(&scrq->used) <=
+				    (adapter->req_tx_entries_per_subcrq / 2) &&
+				    netif_subqueue_stopped(adapter->netdev,
+							   txbuff->skb)) {
+					netif_wake_subqueue(adapter->netdev,
+							    scrq->pool_index);
+					netdev_dbg(adapter->netdev,
+						   "Started queue %d\n",
+						   scrq->pool_index);
+				}
 				dev_kfree_skb_any(txbuff->skb);
+			}
 			adapter->tx_pool[pool].free_map[adapter->tx_pool[pool].
 						     producer_index] = index;
 			adapter->tx_pool[pool].producer_index =
 			    (adapter->tx_pool[pool].producer_index + 1) %
-			    adapter->max_tx_entries_per_subcrq;
+			    adapter->req_tx_entries_per_subcrq;
 		}
 		/* remove tx_comp scrq*/
 		next->tx_comp.first = 0;

drivers/net/ethernet/ibm/ibmvnic.h+1−0

@@ -863,6 +863,7 @@ struct ibmvnic_sub_crq_queue { · 862 unmodified lines
863	spinlock_t lock;	863	spinlock_t lock;
864	struct sk_buff *rx_skb_top;	864	struct sk_buff *rx_skb_top;
865	struct ibmvnic_adapter *adapter;	865	struct ibmvnic_adapter *adapter;
		866	atomic_t used;
866	};	867	};
867		868
868	struct ibmvnic_long_term_buff {	869	struct ibmvnic_long_term_buff {

drivers/net/ethernet/mellanox/mlx4/cmd.c+11−0

@@ -2305,6 +2305,17 @@ static int sync_toggles(struct mlx4_dev *dev) · 2304 unmodified lines
2305	rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));	2305	rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2306	if (wr_toggle == 0xffffffff \|\| rd_toggle == 0xffffffff) {	2306	if (wr_toggle == 0xffffffff \|\| rd_toggle == 0xffffffff) {
2307	/* PCI might be offline */	2307	/* PCI might be offline */
		2308
		2309	/* If device removal has been requested,
		2310	* do not continue retrying.
		2311	*/
		2312	if (dev->persist->interface_state &
		2313	MLX4_INTERFACE_STATE_NOWAIT) {
		2314	mlx4_warn(dev,
		2315	"communication channel is offline\n");
		2316	return -EIO;
		2317	}
		2318
2308	msleep(100);	2319	msleep(100);
2309	wr_toggle = swab32(readl(&priv->mfunc.comm->	2320	wr_toggle = swab32(readl(&priv->mfunc.comm->
2310	slave_write));	2321	slave_write));

drivers/net/ethernet/mellanox/mlx4/main.c+11−0

 			       (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
 		if (!offline_bit)
 			return 0;
+		/* If device removal has been requested,
+		 * do not continue retrying.
+		 */
+		if (dev->persist->interface_state &
+		    MLX4_INTERFACE_STATE_NOWAIT)
+			break;
 		/* There are cases as part of AER/Reset flow that PF needs
 		 * around 100 msec to load. We therefore sleep for 100 msec
 		 * to allow other tasks to make use of that CPU during this
 	struct devlink *devlink = priv_to_devlink(priv);
 	int active_vfs = 0;
+	if (mlx4_is_slave(dev))
+		persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
 	mutex_lock(&persist->interface_state_mutex);
 	persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
 	mutex_unlock(&persist->interface_state_mutex);

drivers/net/ethernet/mellanox/mlx5/core/Kconfig+1−0

@@ -14,6 +14,7 @@ config MLX5_CORE · 13 unmodified lines
14	config MLX5_CORE_EN	14	config MLX5_CORE_EN
15	bool "Mellanox Technologies ConnectX-4 Ethernet support"	15	bool "Mellanox Technologies ConnectX-4 Ethernet support"
16	depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE	16	depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
		17	depends on IPV6=y \|\| IPV6=n \|\| MLX5_CORE=m
17	imply PTP_1588_CLOCK	18	imply PTP_1588_CLOCK
18	default n	19	default n
19	---help---	20	---help---

drivers/net/ethernet/mellanox/mlx5/core/cmd.c+4−0

 	case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 	case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 	case MLX5_CMD_OP_QUERY_Q_COUNTER:
+	case MLX5_CMD_OP_SET_RATE_LIMIT:
+	case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 	case MLX5_CMD_OP_ALLOC_PD:
 	case MLX5_CMD_OP_ALLOC_UAR:
 	case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 	MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 	MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 	MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
+	MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);
+	MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 	MLX5_COMMAND_STR_CASE(ALLOC_PD);
 	MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 	MLX5_COMMAND_STR_CASE(ALLOC_UAR);

drivers/net/ethernet/mellanox/mlx5/core/en.h+0−4

 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
-void mlx5e_add_vxlan_port(struct net_device *netdev,
-			  struct udp_tunnel_info *ti);
-void mlx5e_del_vxlan_port(struct net_device *netdev,
-			  struct udp_tunnel_info *ti);
 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
 			    void *sp);

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c+5−5

 	struct mlx5e_priv *priv = netdev_priv(dev);
 	struct mlx5e_dcbx *dcbx = &priv->dcbx;
+	if (mode & DCB_CAP_DCBX_LLD_MANAGED)
+		return 1;
 	if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
 		if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
 			return 0;
 		return 1;
 	}
-	if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
+	if (!(mode & DCB_CAP_DCBX_HOST))
 		return 1;
-	if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
+	if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
-	    !(mode & DCB_CAP_DCBX_VER_CEE) ||
-	    !(mode & DCB_CAP_DCBX_VER_IEEE) ||
-	    !(mode & DCB_CAP_DCBX_HOST))
 		return 1;
 	return 0;

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+4−4

@@ -3100,8 +3100,8 @@ static int mlx5e_get_vf_stats(struct net_device *dev, · 3099 unmodified lines
3100	vf_stats);	3100	vf_stats);
3101	}	3101	}
3102		3102
3103	void mlx5e_add_vxlan_port(struct net_device *netdev,	3103	static void mlx5e_add_vxlan_port(struct net_device *netdev,
3104	struct udp_tunnel_info *ti)	3104	struct udp_tunnel_info *ti)
3105	{	3105	{
3106	struct mlx5e_priv *priv = netdev_priv(netdev);	3106	struct mlx5e_priv *priv = netdev_priv(netdev);
3107		3107
@@ -3114,8 +3114,8 @@ void mlx5e_add_vxlan_port(struct net_device *netdev, · 6 unmodified lines
3114	mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);	3114	mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3115	}	3115	}
3116		3116
3117	void mlx5e_del_vxlan_port(struct net_device *netdev,	3117	static void mlx5e_del_vxlan_port(struct net_device *netdev,
3118	struct udp_tunnel_info *ti)	3118	struct udp_tunnel_info *ti)
3119	{	3119	{
3120	struct mlx5e_priv *priv = netdev_priv(netdev);	3120	struct mlx5e_priv *priv = netdev_priv(netdev);
3121		3121

drivers/net/ethernet/mellanox/mlx5/core/en_rep.c+0−2

 	.ndo_get_phys_port_name  = mlx5e_rep_get_phys_port_name,
 	.ndo_setup_tc            = mlx5e_rep_ndo_setup_tc,
 	.ndo_get_stats64         = mlx5e_rep_get_stats,
-	.ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
-	.ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
 	.ndo_has_offload_stats	 = mlx5e_has_offload_stats,
 	.ndo_get_offload_stats	 = mlx5e_get_offload_stats,
 };

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+4−0

 	if (lro_num_seg > 1) {
 		mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 		skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
+		/* Subtract one since we already counted this as one
+		 * "regular" packet in mlx5e_complete_rx_cqe()
+		 */
+		rq->stats.packets += lro_num_seg - 1;
 		rq->stats.lro_packets++;
 		rq->stats.lro_bytes += cqe_bcnt;
 	}

drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c+1−4

 	struct iphdr *iph;
 	/* We are only going to peek, no need to clone the SKB */
-	if (skb->protocol != htons(ETH_P_IP))
-		goto out;
 	if (MLX5E_TEST_PKT_SIZE - ETH_HLEN > skb_headlen(skb))
 		goto out;
 	lbtp->loopback_ok = false;
 	init_completion(&lbtp->comp);
-	lbtp->pt.type = htons(ETH_P_ALL);
+	lbtp->pt.type = htons(ETH_P_IP);
 	lbtp->pt.func = mlx5e_test_loopback_validate;
 	lbtp->pt.dev = priv->netdev;
 	lbtp->pt.af_packet_priv = lbtp;

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+67−38

@@ -48,9 +48,14 @@ · 47 unmodified lines
48	#include "eswitch.h"	48	#include "eswitch.h"
49	#include "vxlan.h"	49	#include "vxlan.h"
50		50
		51	enum {
		52	MLX5E_TC_FLOW_ESWITCH = BIT(0),
		53	};
		54
51	struct mlx5e_tc_flow {	55	struct mlx5e_tc_flow {
52	struct rhash_head node;	56	struct rhash_head node;
53	u64 cookie;	57	u64 cookie;
		58	u8 flags;
54	struct mlx5_flow_handle *rule;	59	struct mlx5_flow_handle *rule;
55	struct list_head encap; /* flows sharing the same encap */	60	struct list_head encap; /* flows sharing the same encap */
56	struct mlx5_esw_flow_attr *attr;	61	struct mlx5_esw_flow_attr *attr;
@@ -128,6 +133,23 @@ err_create_ft: · 71 unmodified lines
128	return rule;	133	return rule;
129	}	134	}
130		135
		136	static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
		137	struct mlx5e_tc_flow *flow)
		138	{
		139	struct mlx5_fc *counter = NULL;
		140
		141	if (!IS_ERR(flow->rule)) {
		142	counter = mlx5_flow_rule_counter(flow->rule);
		143	mlx5_del_flow_rules(flow->rule);
		144	mlx5_fc_destroy(priv->mdev, counter);
		145	}
		146
		147	if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
		148	mlx5_destroy_flow_table(priv->fs.tc.t);
		149	priv->fs.tc.t = NULL;
		150	}
		151	}
		152
131	static struct mlx5_flow_handle *	153	static struct mlx5_flow_handle *
132	mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,	154	mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
133	struct mlx5_flow_spec *spec,	155	struct mlx5_flow_spec *spec,
@@ -144,7 +166,24 @@ mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv, · 10 unmodified lines
144	}	166	}
145		167
146	static void mlx5e_detach_encap(struct mlx5e_priv *priv,	168	static void mlx5e_detach_encap(struct mlx5e_priv *priv,
147	struct mlx5e_tc_flow *flow) {	169	struct mlx5e_tc_flow *flow);
		170
		171	static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
		172	struct mlx5e_tc_flow *flow)
		173	{
		174	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
		175
		176	mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->attr);
		177
		178	mlx5_eswitch_del_vlan_action(esw, flow->attr);
		179
		180	if (flow->attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
		181	mlx5e_detach_encap(priv, flow);
		182	}
		183
		184	static void mlx5e_detach_encap(struct mlx5e_priv *priv,
		185	struct mlx5e_tc_flow *flow)
		186	{
148	struct list_head *next = flow->encap.next;	187	struct list_head *next = flow->encap.next;
149		188
150	list_del(&flow->encap);	189	list_del(&flow->encap);
@@ -168,25 +207,10 @@ static void mlx5e_detach_encap(struct mlx5e_priv *priv, · 17 unmodified lines
168	static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,	207	static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
169	struct mlx5e_tc_flow *flow)	208	struct mlx5e_tc_flow *flow)
170	{	209	{
171	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;	210	if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
172	struct mlx5_fc *counter = NULL;	211	mlx5e_tc_del_fdb_flow(priv, flow);
173		212	else
174	if (!IS_ERR(flow->rule)) {	213	mlx5e_tc_del_nic_flow(priv, flow);
175	counter = mlx5_flow_rule_counter(flow->rule);
176	mlx5_del_flow_rules(flow->rule);
177	mlx5_fc_destroy(priv->mdev, counter);
178	}
179
180	if (esw && esw->mode == SRIOV_OFFLOADS) {
181	mlx5_eswitch_del_vlan_action(esw, flow->attr);
182	if (flow->attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
183	mlx5e_detach_encap(priv, flow);
184	}
185
186	if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
187	mlx5_destroy_flow_table(priv->fs.tc.t);
188	priv->fs.tc.t = NULL;
189	}
190	}	214	}
191		215
192	static void parse_vxlan_attr(struct mlx5_flow_spec *spec,	216	static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
@@ -243,12 +267,15 @@ static int parse_tunnel_attr(struct mlx5e_priv *priv, · 50 unmodified lines
243	skb_flow_dissector_target(f->dissector,	267	skb_flow_dissector_target(f->dissector,
244	FLOW_DISSECTOR_KEY_ENC_PORTS,	268	FLOW_DISSECTOR_KEY_ENC_PORTS,
245	f->mask);	269	f->mask);
		270	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
		271	struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
		272	struct mlx5e_priv *up_priv = netdev_priv(up_dev);
246		273
247	/* Full udp dst port must be given */	274	/* Full udp dst port must be given */
248	if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))	275	if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
249	goto vxlan_match_offload_err;	276	goto vxlan_match_offload_err;
250		277
251	if (mlx5e_vxlan_lookup_port(priv, be16_to_cpu(key->dst)) &&	278	if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
252	MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))	279	MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
253	parse_vxlan_attr(spec, f);	280	parse_vxlan_attr(spec, f);
254	else {	281	else {
@@ -598,6 +625,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv, · 343 unmodified lines
598	}	625	}
599		626
600	static int parse_cls_flower(struct mlx5e_priv *priv,	627	static int parse_cls_flower(struct mlx5e_priv *priv,
		628	struct mlx5e_tc_flow *flow,
601	struct mlx5_flow_spec *spec,	629	struct mlx5_flow_spec *spec,
602	struct tc_cls_flower_offload *f)	630	struct tc_cls_flower_offload *f)
603	{	631	{
@@ -609,7 +637,7 @@ static int parse_cls_flower(struct mlx5e_priv *priv, · 5 unmodified lines
609		637
610	err = __parse_cls_flower(priv, spec, f, &min_inline);	638	err = __parse_cls_flower(priv, spec, f, &min_inline);
611		639
612	if (!err && esw->mode == SRIOV_OFFLOADS &&	640	if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH) &&
613	rep->vport != FDB_UPLINK_VPORT) {	641	rep->vport != FDB_UPLINK_VPORT) {
614	if (min_inline > esw->offloads.inline_mode) {	642	if (min_inline > esw->offloads.inline_mode) {
615	netdev_warn(priv->netdev,	643	netdev_warn(priv->netdev,
@@ -970,6 +998,8 @@ static int mlx5e_attach_encap(struct mlx5e_priv *priv, · 354 unmodified lines
970	struct mlx5_esw_flow_attr *attr)	998	struct mlx5_esw_flow_attr *attr)
971	{	999	{
972	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;	1000	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
		1001	struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
		1002	struct mlx5e_priv *up_priv = netdev_priv(up_dev);
973	unsigned short family = ip_tunnel_info_af(tun_info);	1003	unsigned short family = ip_tunnel_info_af(tun_info);
974	struct ip_tunnel_key *key = &tun_info->key;	1004	struct ip_tunnel_key *key = &tun_info->key;
975	struct mlx5_encap_entry *e;	1005	struct mlx5_encap_entry *e;
@@ -990,7 +1020,7 @@ vxlan_encap_offload_err: · 14 unmodified lines
990	return -EOPNOTSUPP;	1020	return -EOPNOTSUPP;
991	}	1021	}
992		1022
993	if (mlx5e_vxlan_lookup_port(priv, be16_to_cpu(key->tp_dst)) &&	1023	if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
994	MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {	1024	MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
995	tunnel_type = MLX5_HEADER_TYPE_VXLAN;	1025	tunnel_type = MLX5_HEADER_TYPE_VXLAN;
996	} else {	1026	} else {
@@ -1106,14 +1136,16 @@ static int parse_tc_fdb_actions(struct mlx5e_priv priv, struct tcf_exts exts, · 109 unmodified lines
1106	}	1136	}
1107		1137
1108	if (is_tcf_vlan(a)) {	1138	if (is_tcf_vlan(a)) {
1109	if (tcf_vlan_action(a) == VLAN_F_POP) {	1139	if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
1110	attr->action \|= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;	1140	attr->action \|= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
1111	} else if (tcf_vlan_action(a) == VLAN_F_PUSH) {	1141	} else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
1112	if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))	1142	if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1113	return -EOPNOTSUPP;	1143	return -EOPNOTSUPP;
1114		1144
1115	attr->action \|= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;	1145	attr->action \|= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1116	attr->vlan = tcf_vlan_push_vid(a);	1146	attr->vlan = tcf_vlan_push_vid(a);
		1147	} else { /* action is TCA_VLAN_ACT_MODIFY */
		1148	return -EOPNOTSUPP;
1117	}	1149	}
1118	continue;	1150	continue;
1119	}	1151	}
@@ -1132,23 +1164,19 @@ int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol, · 12 unmodified lines
1132	struct tc_cls_flower_offload *f)	1164	struct tc_cls_flower_offload *f)
1133	{	1165	{
1134	struct mlx5e_tc_table *tc = &priv->fs.tc;	1166	struct mlx5e_tc_table *tc = &priv->fs.tc;
1135	int err = 0;	1167	int err, attr_size = 0;
1136	bool fdb_flow = false;
1137	u32 flow_tag, action;	1168	u32 flow_tag, action;
1138	struct mlx5e_tc_flow *flow;	1169	struct mlx5e_tc_flow *flow;
1139	struct mlx5_flow_spec *spec;	1170	struct mlx5_flow_spec *spec;
1140	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;	1171	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
		1172	u8 flow_flags = 0;
1141		1173
1142	if (esw && esw->mode == SRIOV_OFFLOADS)	1174	if (esw && esw->mode == SRIOV_OFFLOADS) {
1143	fdb_flow = true;	1175	flow_flags = MLX5E_TC_FLOW_ESWITCH;
1144		1176	attr_size = sizeof(struct mlx5_esw_flow_attr);
1145	if (fdb_flow)	1177	}
1146	flow = kzalloc(sizeof(*flow) +
1147	sizeof(struct mlx5_esw_flow_attr),
1148	GFP_KERNEL);
1149	else
1150	flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1151		1178
		1179	flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1152	spec = mlx5_vzalloc(sizeof(*spec));	1180	spec = mlx5_vzalloc(sizeof(*spec));
1153	if (!spec \|\| !flow) {	1181	if (!spec \|\| !flow) {
1154	err = -ENOMEM;	1182	err = -ENOMEM;
@@ -1156,12 +1184,13 @@ int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol, · 1 unmodified line
1156	}	1184	}
1157		1185
1158	flow->cookie = f->cookie;	1186	flow->cookie = f->cookie;
		1187	flow->flags = flow_flags;
1159		1188
1160	err = parse_cls_flower(priv, spec, f);	1189	err = parse_cls_flower(priv, flow, spec, f);
1161	if (err < 0)	1190	if (err < 0)
1162	goto err_free;	1191	goto err_free;
1163		1192
1164	if (fdb_flow) {	1193	if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1165	flow->attr = (struct mlx5_esw_flow_attr *)(flow + 1);	1194	flow->attr = (struct mlx5_esw_flow_attr *)(flow + 1);
1166	err = parse_tc_fdb_actions(priv, f->exts, flow);	1195	err = parse_tc_fdb_actions(priv, f->exts, flow);
1167	if (err < 0)	1196	if (err < 0)

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+3−2

 			sq->stats.tso_bytes += skb->len - ihs;
 		}
+		sq->stats.packets += skb_shinfo(skb)->gso_segs;
 		num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
 	} else {
 		bf = sq->bf_budget &&
 		     !skb->xmit_more &&
 		     !skb_shinfo(skb)->nr_frags;
 		ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
+		sq->stats.packets++;
 		num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 	}
+	sq->stats.bytes += num_bytes;
 	wi->num_bytes = num_bytes;
 	ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
 	if (bf)
 		sq->bf_budget--;
-	sq->stats.packets++;
-	sq->stats.bytes += num_bytes;
 	return NETDEV_TX_OK;
 dma_unmap_wqe_err:

drivers/net/ethernet/mellanox/mlx5/core/eswitch.h+6−0

 	struct mlx5_eswitch_rep *vport_reps;
 	DECLARE_HASHTABLE(encap_tbl, 8);
 	u8 inline_mode;
+	u64 num_flows;
 };
 struct mlx5_eswitch {
 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
 				struct mlx5_flow_spec *spec,
 				struct mlx5_esw_flow_attr *attr);
+void
+mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
+				struct mlx5_flow_handle *rule,
+				struct mlx5_esw_flow_attr *attr);
 struct mlx5_flow_handle *
 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+22−0

@@ -93,10 +93,27 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, · 92 unmodified lines
93	spec, &flow_act, dest, i);	93	spec, &flow_act, dest, i);
94	if (IS_ERR(rule))	94	if (IS_ERR(rule))
95	mlx5_fc_destroy(esw->dev, counter);	95	mlx5_fc_destroy(esw->dev, counter);
		96	else
		97	esw->offloads.num_flows++;
96		98
97	return rule;	99	return rule;
98	}	100	}
99		101
		102	void
		103	mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
		104	struct mlx5_flow_handle *rule,
		105	struct mlx5_esw_flow_attr *attr)
		106	{
		107	struct mlx5_fc *counter = NULL;
		108
		109	if (!IS_ERR(rule)) {
		110	counter = mlx5_flow_rule_counter(rule);
		111	mlx5_del_flow_rules(rule);
		112	mlx5_fc_destroy(esw->dev, counter);
		113	esw->offloads.num_flows--;
		114	}
		115	}
		116
100	static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)	117	static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
101	{	118	{
102	struct mlx5_eswitch_rep *rep;	119	struct mlx5_eswitch_rep *rep;
@@ -908,6 +925,11 @@ int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode) · 805 unmodified lines
908	MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)	925	MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
909	return -EOPNOTSUPP;	926	return -EOPNOTSUPP;
910		927
		928	if (esw->offloads.num_flows > 0) {
		929	esw_warn(dev, "Can't set inline mode when flows are configured\n");
		930	return -EOPNOTSUPP;
		931	}
		932
911	err = esw_inline_mode_from_devlink(mode, &mlx5_mode);	933	err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
912	if (err)	934	if (err)
913	goto out;	935	goto out;

drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+1−1

@@ -1136,7 +1136,7 @@ static struct mlx5_flow_group create_autogroup(struct mlx5_flow_table ft, · 1135 unmodified lines
1136	u32 *match_criteria)	1136	u32 *match_criteria)
1137	{	1137	{
1138	int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);	1138	int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1139	struct list_head *prev = ft->node.children.prev;	1139	struct list_head *prev = &ft->node.children;
1140	unsigned int candidate_index = 0;	1140	unsigned int candidate_index = 0;
1141	struct mlx5_flow_group *fg;	1141	struct mlx5_flow_group *fg;
1142	void *match_criteria_addr;	1142	void *match_criteria_addr;

drivers/net/ethernet/mellanox/mlx5/core/main.c+4−3

 	[2] = {
 		.mask		= MLX5_PROF_MASK_QP_SIZE |
 				  MLX5_PROF_MASK_MR_CACHE,
-		.log_max_qp	= 17,
+		.log_max_qp	= 18,
 		.mr_cache[0]	= {
 			.size	= 500,
 			.limit	= 250
 	if (err)
 		goto clean_load;
+	pci_save_state(pdev);
 	return 0;
 clean_load:
 	mlx5_enter_error_state(dev);
 	mlx5_unload_one(dev, priv, false);
-	/* In case of kernel call save the pci state and drain the health wq */
+	/* In case of kernel call drain the health wq */
 	if (state) {
-		pci_save_state(pdev);
 		mlx5_drain_health_wq(dev);
 		mlx5_pci_disable_device(dev);
 	}
 	pci_set_master(pdev);
 	pci_restore_state(pdev);
+	pci_save_state(pdev);
 	if (wait_vital(pdev)) {
 		dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);

drivers/net/ethernet/mellanox/mlxsw/reg.h+2−2

drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c+2−2

@@ -303,11 +303,11 @@ void mlxsw_sp_flower_destroy(struct mlxsw_sp_port *mlxsw_sp_port, bool ingress, · 302 unmodified lines
303	ruleset = mlxsw_sp_acl_ruleset_get(mlxsw_sp, mlxsw_sp_port->dev,	303	ruleset = mlxsw_sp_acl_ruleset_get(mlxsw_sp, mlxsw_sp_port->dev,
304	ingress,	304	ingress,
305	MLXSW_SP_ACL_PROFILE_FLOWER);	305	MLXSW_SP_ACL_PROFILE_FLOWER);
306	if (WARN_ON(IS_ERR(ruleset)))	306	if (IS_ERR(ruleset))
307	return;	307	return;
308		308
309	rule = mlxsw_sp_acl_rule_lookup(mlxsw_sp, ruleset, f->cookie);	309	rule = mlxsw_sp_acl_rule_lookup(mlxsw_sp, ruleset, f->cookie);
310	if (!WARN_ON(!rule)) {	310	if (rule) {
311	mlxsw_sp_acl_rule_del(mlxsw_sp, rule);	311	mlxsw_sp_acl_rule_del(mlxsw_sp, rule);
312	mlxsw_sp_acl_rule_destroy(mlxsw_sp, rule);	312	mlxsw_sp_acl_rule_destroy(mlxsw_sp, rule);
313	}	313	}

drivers/net/ethernet/qlogic/qed/qed_cxt.c+2−1

@@ -422,8 +422,9 @@ static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, · 421 unmodified lines
422	u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;	422	u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
423	u32 cxt_size = CONN_CXT_SIZE(p_hwfn);	423	u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
424	u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;	424	u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
		425	u32 align = elems_per_page * DQ_RANGE_ALIGN;
425		426
426	p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);	427	p_conn->cid_count = roundup(p_conn->cid_count, align);
427	}	428	}
428	}	429	}
429		430

drivers/net/ethernet/qlogic/qed/qed_dev.c+2−3

 	 * size/capacity fields are of a u32 type.
 	 */
 	if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
-	     chain_size > 0x10000) ||
+	     chain_size > ((u32)U16_MAX + 1)) ||
-	    (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
+	    (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
-	     chain_size > 0x100000000ULL)) {
 		DP_NOTICE(cdev,
 			  "The actual chain size (0x%llx) is larger than the maximal possible value\n",
 			  chain_size);

drivers/net/ethernet/qlogic/qed/qed_iscsi.c+31−0

@@ -190,6 +190,9 @@ qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn, · 189 unmodified lines
190	p_init->num_sq_pages_in_ring = p_params->num_sq_pages_in_ring;	190	p_init->num_sq_pages_in_ring = p_params->num_sq_pages_in_ring;
191	p_init->num_r2tq_pages_in_ring = p_params->num_r2tq_pages_in_ring;	191	p_init->num_r2tq_pages_in_ring = p_params->num_r2tq_pages_in_ring;
192	p_init->num_uhq_pages_in_ring = p_params->num_uhq_pages_in_ring;	192	p_init->num_uhq_pages_in_ring = p_params->num_uhq_pages_in_ring;
		193	p_init->ooo_enable = p_params->ooo_enable;
		194	p_init->ll2_rx_queue_id = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] +
		195	p_params->ll2_ooo_queue_id;
193	p_init->func_params.log_page_size = p_params->log_page_size;	196	p_init->func_params.log_page_size = p_params->log_page_size;
194	val = p_params->num_tasks;	197	val = p_params->num_tasks;
195	p_init->func_params.num_tasks = cpu_to_le16(val);	198	p_init->func_params.num_tasks = cpu_to_le16(val);
@@ -786,6 +789,23 @@ static void qed_iscsi_release_connection(struct qed_hwfn *p_hwfn, · 590 unmodified lines
786	spin_unlock_bh(&p_hwfn->p_iscsi_info->lock);	789	spin_unlock_bh(&p_hwfn->p_iscsi_info->lock);
787	}	790	}
788		791
		792	void qed_iscsi_free_connection(struct qed_hwfn *p_hwfn,
		793	struct qed_iscsi_conn *p_conn)
		794	{
		795	qed_chain_free(p_hwfn->cdev, &p_conn->xhq);
		796	qed_chain_free(p_hwfn->cdev, &p_conn->uhq);
		797	qed_chain_free(p_hwfn->cdev, &p_conn->r2tq);
		798	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
		799	sizeof(struct tcp_upload_params),
		800	p_conn->tcp_upload_params_virt_addr,
		801	p_conn->tcp_upload_params_phys_addr);
		802	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
		803	sizeof(struct scsi_terminate_extra_params),
		804	p_conn->queue_cnts_virt_addr,
		805	p_conn->queue_cnts_phys_addr);
		806	kfree(p_conn);
		807	}
		808
789	struct qed_iscsi_info qed_iscsi_alloc(struct qed_hwfn p_hwfn)	809	struct qed_iscsi_info qed_iscsi_alloc(struct qed_hwfn p_hwfn)
790	{	810	{
791	struct qed_iscsi_info *p_iscsi_info;	811	struct qed_iscsi_info *p_iscsi_info;
@@ -807,6 +827,17 @@ void qed_iscsi_setup(struct qed_hwfn *p_hwfn, · 15 unmodified lines
807	void qed_iscsi_free(struct qed_hwfn *p_hwfn,	827	void qed_iscsi_free(struct qed_hwfn *p_hwfn,
808	struct qed_iscsi_info *p_iscsi_info)	828	struct qed_iscsi_info *p_iscsi_info)
809	{	829	{
		830	struct qed_iscsi_conn *p_conn = NULL;
		831
		832	while (!list_empty(&p_hwfn->p_iscsi_info->free_list)) {
		833	p_conn = list_first_entry(&p_hwfn->p_iscsi_info->free_list,
		834	struct qed_iscsi_conn, list_entry);
		835	if (p_conn) {
		836	list_del(&p_conn->list_entry);
		837	qed_iscsi_free_connection(p_hwfn, p_conn);
		838	}
		839	}
		840
810	kfree(p_iscsi_info);	841	kfree(p_iscsi_info);
811	}	842	}
812		843

drivers/net/ethernet/qlogic/qed/qed_ll2.c+8−5

 	/* If need to reuse or there's no replacement buffer, repost this */
 	if (rc)
 		goto out_post;
+	dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
+			 cdev->ll2->rx_size, DMA_FROM_DEVICE);
 	skb = build_skb(buffer->data, 0);
 	if (!skb) {
 static int qed_ll2_rxq_completion_reg(struct qed_hwfn *p_hwfn,
 				      struct qed_ll2_info *p_ll2_conn,
 				      union core_rx_cqe_union *p_cqe,
-				      unsigned long lock_flags,
+				      unsigned long *p_lock_flags,
 				      bool b_last_cqe)
 {
 	struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
 			  "Mismatch between active_descq and the LL2 Rx chain\n");
 	list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
-	spin_unlock_irqrestore(&p_rx->lock, lock_flags);
+	spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
 	qed_ll2b_complete_rx_packet(p_hwfn, p_ll2_conn->my_id,
 				    p_pkt, &p_cqe->rx_cqe_fp, b_last_cqe);
-	spin_lock_irqsave(&p_rx->lock, lock_flags);
+	spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
 	return 0;
 }
 			break;
 		case CORE_RX_CQE_TYPE_REGULAR:
 			rc = qed_ll2_rxq_completion_reg(p_hwfn, p_ll2_conn,
-							cqe, flags, b_last_cqe);
+							cqe, &flags,
+							b_last_cqe);
 			break;
 		default:
 			rc = -EIO;
 {
 	struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
 	u8 *handle = &hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
-	struct qed_ll2_conn ll2_info;
+	struct qed_ll2_conn ll2_info = { 0 };
 	int rc;
 	ll2_info.conn_type = QED_LL2_TYPE_ISCSI_OOO;

drivers/net/ethernet/qlogic/qed/qed_ooo.c+2−0

@@ -159,6 +159,8 @@ struct qed_ooo_info qed_ooo_alloc(struct qed_hwfn p_hwfn) · 158 unmodified lines
159	if (!p_ooo_info->ooo_history.p_cqes)	159	if (!p_ooo_info->ooo_history.p_cqes)
160	goto no_history_mem;	160	goto no_history_mem;
161		161
		162	p_ooo_info->ooo_history.num_of_cqes = QED_MAX_NUM_OOO_HISTORY_ENTRIES;
		163
162	return p_ooo_info;	164	return p_ooo_info;
163		165
164	no_history_mem:	166	no_history_mem:

drivers/net/ethernet/sfc/efx.c+1−1

@@ -2404,7 +2404,7 @@ static void efx_udp_tunnel_del(struct net_device dev, struct udp_tunnel_info t · 2403 unmodified lines
2404	tnl.type = (u16)efx_tunnel_type;	2404	tnl.type = (u16)efx_tunnel_type;
2405	tnl.port = ti->port;	2405	tnl.port = ti->port;
2406		2406
2407	if (efx->type->udp_tnl_add_port)	2407	if (efx->type->udp_tnl_del_port)
2408	(void)efx->type->udp_tnl_del_port(efx, tnl);	2408	(void)efx->type->udp_tnl_del_port(efx, tnl);
2409	}	2409	}
2410		2410

drivers/net/ethernet/smsc/smc91x.c+25−22

  * Ethtool support
  */
 static int
-smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
+smc_ethtool_get_link_ksettings(struct net_device *dev,
+			       struct ethtool_link_ksettings *cmd)
 {
 	struct smc_local *lp = netdev_priv(dev);
 	int ret;
-	cmd->maxtxpkt = 1;
-	cmd->maxrxpkt = 1;
 	if (lp->phy_type != 0) {
 		spin_lock_irq(&lp->lock);
-		ret = mii_ethtool_gset(&lp->mii, cmd);
+		ret = mii_ethtool_get_link_ksettings(&lp->mii, cmd);
 		spin_unlock_irq(&lp->lock);
 	} else {
-		cmd->supported = SUPPORTED_10baseT_Half |
+		u32 supported = SUPPORTED_10baseT_Half |
 				 SUPPORTED_10baseT_Full |
 				 SUPPORTED_TP | SUPPORTED_AUI;
 		if (lp->ctl_rspeed == 10)
-			ethtool_cmd_speed_set(cmd, SPEED_10);
+			cmd->base.speed = SPEED_10;
 		else if (lp->ctl_rspeed == 100)
-			ethtool_cmd_speed_set(cmd, SPEED_100);
+			cmd->base.speed = SPEED_100;
+		cmd->base.autoneg = AUTONEG_DISABLE;
+		cmd->base.port = 0;
+		cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ?
+			DUPLEX_FULL : DUPLEX_HALF;
-		cmd->autoneg = AUTONEG_DISABLE;
+		ethtool_convert_legacy_u32_to_link_mode(
-		cmd->transceiver = XCVR_INTERNAL;
+			cmd->link_modes.supported, supported);
-		cmd->port = 0;
-		cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
 		ret = 0;
 	}
 }
 static int
-smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
+smc_ethtool_set_link_ksettings(struct net_device *dev,
+			       const struct ethtool_link_ksettings *cmd)
 {
 	struct smc_local *lp = netdev_priv(dev);
 	int ret;
 	if (lp->phy_type != 0) {
 		spin_lock_irq(&lp->lock);
-		ret = mii_ethtool_sset(&lp->mii, cmd);
+		ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd);
 		spin_unlock_irq(&lp->lock);
 	} else {
-		if (cmd->autoneg != AUTONEG_DISABLE ||
+		if (cmd->base.autoneg != AUTONEG_DISABLE ||
-		    cmd->speed != SPEED_10 ||
+		    cmd->base.speed != SPEED_10 ||
-		    (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
+		    (cmd->base.duplex != DUPLEX_HALF &&
-		    (cmd->port != PORT_TP && cmd->port != PORT_AUI))
+		     cmd->base.duplex != DUPLEX_FULL) ||
+		    (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI))
 			return -EINVAL;
-//		lp->port = cmd->port;
+//		lp->port = cmd->base.port;
-		lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
+		lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL;
 //		if (netif_running(dev))
 //			smc_set_port(dev);
 static const struct ethtool_ops smc_ethtool_ops = {
-	.get_settings	= smc_ethtool_getsettings,
-	.set_settings	= smc_ethtool_setsettings,
 	.get_drvinfo	= smc_ethtool_getdrvinfo,
 	.get_msglevel	= smc_ethtool_getmsglevel,
 	.get_eeprom_len = smc_ethtool_geteeprom_len,
 	.get_eeprom	= smc_ethtool_geteeprom,
 	.set_eeprom	= smc_ethtool_seteeprom,
+	.get_link_ksettings	= smc_ethtool_get_link_ksettings,
+	.set_link_ksettings	= smc_ethtool_set_link_ksettings,
 };
 static const struct net_device_ops smc_netdev_ops = {

drivers/net/ethernet/ti/Kconfig+8−2

 	  will be called cpsw.
 config TI_CPTS
-	tristate "TI Common Platform Time Sync (CPTS) Support"
+	bool "TI Common Platform Time Sync (CPTS) Support"
 	depends on TI_CPSW || TI_KEYSTONE_NETCP
-	imply PTP_1588_CLOCK
+	depends on PTP_1588_CLOCK
 	---help---
 	  This driver supports the Common Platform Time Sync unit of
 	  the CPSW Ethernet Switch and Keystone 2 1g/10g Switch Subsystem.
 	  The unit can time stamp PTP UDP/IPv4 and Layer 2 packets, and the
 	  driver offers a PTP Hardware Clock.
+config TI_CPTS_MOD
+	tristate
+	depends on TI_CPTS
+	default y if TI_CPSW=y || TI_KEYSTONE_NETCP=y
+	default m
 config TI_KEYSTONE_NETCP
 	tristate "TI Keystone NETCP Core Support"
 	select TI_CPSW_ALE

drivers/net/ethernet/ti/Makefile+1−1

@@ -12,7 +12,7 @@ obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o · 11 unmodified lines
12	obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o	12	obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
13	obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o	13	obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o
14	obj-$(CONFIG_TI_CPSW_ALE) += cpsw_ale.o	14	obj-$(CONFIG_TI_CPSW_ALE) += cpsw_ale.o
15	obj-$(CONFIG_TI_CPTS) += cpts.o	15	obj-$(CONFIG_TI_CPTS_MOD) += cpts.o
16	obj-$(CONFIG_TI_CPSW) += ti_cpsw.o	16	obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
17	ti_cpsw-y := cpsw.o	17	ti_cpsw-y := cpsw.o
18		18

drivers/net/fjes/fjes_main.c+72−6

@@ -45,6 +45,8 @@ MODULE_DESCRIPTION("FUJITSU Extended Socket Network Device Driver"); · 44 unmodified lines
45	MODULE_LICENSE("GPL");	45	MODULE_LICENSE("GPL");
46	MODULE_VERSION(DRV_VERSION);	46	MODULE_VERSION(DRV_VERSION);
47		47
		48	#define ACPI_MOTHERBOARD_RESOURCE_HID "PNP0C02"
		49
48	static int fjes_request_irq(struct fjes_adapter *);	50	static int fjes_request_irq(struct fjes_adapter *);
49	static void fjes_free_irq(struct fjes_adapter *);	51	static void fjes_free_irq(struct fjes_adapter *);
50		52
@@ -78,7 +80,7 @@ static void fjes_rx_irq(struct fjes_adapter *, int); · 27 unmodified lines
78	static int fjes_poll(struct napi_struct *, int);	80	static int fjes_poll(struct napi_struct *, int);
79		81
80	static const struct acpi_device_id fjes_acpi_ids[] = {	82	static const struct acpi_device_id fjes_acpi_ids[] = {
81	{"PNP0C02", 0},	83	{ACPI_MOTHERBOARD_RESOURCE_HID, 0},
82	{"", 0},	84	{"", 0},
83	};	85	};
84	MODULE_DEVICE_TABLE(acpi, fjes_acpi_ids);	86	MODULE_DEVICE_TABLE(acpi, fjes_acpi_ids);
@@ -115,18 +117,17 @@ static struct resource fjes_resource[] = { · 30 unmodified lines
115	},	117	},
116	};	118	};
117		119
118	static int fjes_acpi_add(struct acpi_device *device)	120	static bool is_extended_socket_device(struct acpi_device *device)
119	{	121	{
120	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};	122	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
121	char str_buf[sizeof(FJES_ACPI_SYMBOL) + 1];	123	char str_buf[sizeof(FJES_ACPI_SYMBOL) + 1];
122	struct platform_device *plat_dev;
123	union acpi_object *str;	124	union acpi_object *str;
124	acpi_status status;	125	acpi_status status;
125	int result;	126	int result;
126		127
127	status = acpi_evaluate_object(device->handle, "_STR", NULL, &buffer);	128	status = acpi_evaluate_object(device->handle, "_STR", NULL, &buffer);
128	if (ACPI_FAILURE(status))	129	if (ACPI_FAILURE(status))
129	return -ENODEV;	130	return false;
130		131
131	str = buffer.pointer;	132	str = buffer.pointer;
132	result = utf16s_to_utf8s((wchar_t *)str->string.pointer,	133	result = utf16s_to_utf8s((wchar_t *)str->string.pointer,
@@ -136,10 +137,42 @@ static int fjes_acpi_add(struct acpi_device *device) · 3 unmodified lines
136		137
137	if (strncmp(FJES_ACPI_SYMBOL, str_buf, strlen(FJES_ACPI_SYMBOL)) != 0) {	138	if (strncmp(FJES_ACPI_SYMBOL, str_buf, strlen(FJES_ACPI_SYMBOL)) != 0) {
138	kfree(buffer.pointer);	139	kfree(buffer.pointer);
139	return -ENODEV;	140	return false;
140	}	141	}
141	kfree(buffer.pointer);	142	kfree(buffer.pointer);
142		143
		144	return true;
		145	}
		146
		147	static int acpi_check_extended_socket_status(struct acpi_device *device)
		148	{
		149	unsigned long long sta;
		150	acpi_status status;
		151
		152	status = acpi_evaluate_integer(device->handle, "_STA", NULL, &sta);
		153	if (ACPI_FAILURE(status))
		154	return -ENODEV;
		155
		156	if (!((sta & ACPI_STA_DEVICE_PRESENT) &&
		157	(sta & ACPI_STA_DEVICE_ENABLED) &&
		158	(sta & ACPI_STA_DEVICE_UI) &&
		159	(sta & ACPI_STA_DEVICE_FUNCTIONING)))
		160	return -ENODEV;
		161
		162	return 0;
		163	}
		164
		165	static int fjes_acpi_add(struct acpi_device *device)
		166	{
		167	struct platform_device *plat_dev;
		168	acpi_status status;
		169
		170	if (!is_extended_socket_device(device))
		171	return -ENODEV;
		172
		173	if (acpi_check_extended_socket_status(device))
		174	return -ENODEV;
		175
143	status = acpi_walk_resources(device->handle, METHOD_NAME__CRS,	176	status = acpi_walk_resources(device->handle, METHOD_NAME__CRS,
144	fjes_get_acpi_resource, fjes_resource);	177	fjes_get_acpi_resource, fjes_resource);
145	if (ACPI_FAILURE(status))	178	if (ACPI_FAILURE(status))
@@ -1316,7 +1349,7 @@ static void fjes_netdev_setup(struct net_device *netdev) · 1170 unmodified lines
1316	netdev->min_mtu = fjes_support_mtu[0];	1349	netdev->min_mtu = fjes_support_mtu[0];
1317	netdev->max_mtu = fjes_support_mtu[3];	1350	netdev->max_mtu = fjes_support_mtu[3];
1318	netdev->flags \|= IFF_BROADCAST;	1351	netdev->flags \|= IFF_BROADCAST;
1319	netdev->features \|= NETIF_F_HW_CSUM \| NETIF_F_HW_VLAN_CTAG_FILTER;	1352	netdev->features \|= NETIF_F_HW_VLAN_CTAG_FILTER;
1320	}	1353	}
1321		1354
1322	static void fjes_irq_watch_task(struct work_struct *work)	1355	static void fjes_irq_watch_task(struct work_struct *work)
@@ -1473,11 +1506,44 @@ static void fjes_watch_unshare_task(struct work_struct *work) · 150 unmodified lines
1473	}	1506	}
1474	}	1507	}
1475		1508
		1509	static acpi_status
		1510	acpi_find_extended_socket_device(acpi_handle obj_handle, u32 level,
		1511	void context, void *return_value)
		1512	{
		1513	struct acpi_device *device;
		1514	bool *found = context;
		1515	int result;
		1516
		1517	result = acpi_bus_get_device(obj_handle, &device);
		1518	if (result)
		1519	return AE_OK;
		1520
		1521	if (strcmp(acpi_device_hid(device), ACPI_MOTHERBOARD_RESOURCE_HID))
		1522	return AE_OK;
		1523
		1524	if (!is_extended_socket_device(device))
		1525	return AE_OK;
		1526
		1527	if (acpi_check_extended_socket_status(device))
		1528	return AE_OK;
		1529
		1530	*found = true;
		1531	return AE_CTRL_TERMINATE;
		1532	}
		1533
1476	/* fjes_init_module - Driver Registration Routine */	1534	/* fjes_init_module - Driver Registration Routine */
1477	static int __init fjes_init_module(void)	1535	static int __init fjes_init_module(void)
1478	{	1536	{
		1537	bool found = false;
1479	int result;	1538	int result;
1480		1539
		1540	acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
		1541	acpi_find_extended_socket_device, NULL, &found,
		1542	NULL);
		1543
		1544	if (!found)
		1545	return -ENODEV;
		1546
1481	pr_info("%s - version %s - %s\n",	1547	pr_info("%s - version %s - %s\n",
1482	fjes_driver_string, fjes_driver_version, fjes_copyright);	1548	fjes_driver_string, fjes_driver_version, fjes_copyright);
1483		1549

drivers/net/hyperv/hyperv_net.h+2−1

 	u32 tx_checksum_mask;
+	u32 tx_send_table[VRSS_SEND_TAB_SIZE];
 	/* Ethtool settings */
 	u8 duplex;
 	u32 speed;
 	struct nvsp_message revoke_packet;
-	u32 send_table[VRSS_SEND_TAB_SIZE];
 	u32 max_chn;
 	u32 num_chn;
 	spinlock_t sc_lock; /* Protects num_sc_offered variable */

drivers/net/hyperv/netvsc.c+7−8

 static void netvsc_send_table(struct hv_device *hdev,
 			      struct nvsp_message *nvmsg)
 {
-	struct netvsc_device *nvscdev;
 	struct net_device *ndev = hv_get_drvdata(hdev);
+	struct net_device_context *net_device_ctx = netdev_priv(ndev);
 	int i;
 	u32 count, *tab;
-	nvscdev = get_outbound_net_device(hdev);
-	if (!nvscdev)
-		return;
 	count = nvmsg->msg.v5_msg.send_table.count;
 	if (count != VRSS_SEND_TAB_SIZE) {
 		netdev_err(ndev, "Received wrong send-table size:%u\n", count);
 		      nvmsg->msg.v5_msg.send_table.offset);
 	for (i = 0; i < count; i++)
-		nvscdev->send_table[i] = tab[i];
+		net_device_ctx->tx_send_table[i] = tab[i];
 }
 static void netvsc_send_vf(struct net_device_context *net_device_ctx,
 		return;
 	net_device = net_device_to_netvsc_device(ndev);
-	if (unlikely(net_device->destroy) &&
+	if (unlikely(!net_device))
-	    netvsc_channel_idle(net_device, q_idx))
+		return;
+	if (unlikely(net_device->destroy &&
+		     netvsc_channel_idle(net_device, q_idx)))
 		return;
 	/* commit_rd_index() -> hv_signal_on_read() needs this. */

drivers/net/hyperv/netvsc_drv.c+3−8

 			void *accel_priv, select_queue_fallback_t fallback)
 {
 	struct net_device_context *net_device_ctx = netdev_priv(ndev);
-	struct netvsc_device *nvsc_dev = net_device_ctx->nvdev;
+	unsigned int num_tx_queues = ndev->real_num_tx_queues;
 	struct sock *sk = skb->sk;
 	int q_idx = sk_tx_queue_get(sk);
-	if (q_idx < 0 || skb->ooo_okay ||
+	if (q_idx < 0 || skb->ooo_okay || q_idx >= num_tx_queues) {
-	    q_idx >= ndev->real_num_tx_queues) {
 		u16 hash = __skb_tx_hash(ndev, skb, VRSS_SEND_TAB_SIZE);
 		int new_idx;
-		new_idx = nvsc_dev->send_table[hash]
+		new_idx = net_device_ctx->tx_send_table[hash] % num_tx_queues;
-			% nvsc_dev->num_chn;
 		if (q_idx != new_idx && sk &&
 		    sk_fullsock(sk) && rcu_access_pointer(sk->sk_dst_cache))
 		q_idx = new_idx;
 	}
-	if (unlikely(!nvsc_dev->chan_table[q_idx].channel))
-		q_idx = 0;
 	return q_idx;
 }

drivers/net/phy/marvell.c+0−15

 	return m88e1510_hwmon_probe(phydev);
 }
-static void marvell_remove(struct phy_device *phydev)
-{
-#ifdef CONFIG_HWMON
-	struct marvell_priv *priv = phydev->priv;
-	if (priv && priv->hwmon_dev)
-		hwmon_device_unregister(priv->hwmon_dev);
-#endif
-}
 static struct phy_driver marvell_drivers[] = {
 	{
 		.phy_id = MARVELL_PHY_ID_88E1101,
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
 		.probe = &m88e1121_probe,
-		.remove = &marvell_remove,
 		.config_init = &m88e1121_config_init,
 		.config_aneg = &m88e1121_config_aneg,
 		.read_status = &marvell_read_status,
 		.features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
 		.flags = PHY_HAS_INTERRUPT,
 		.probe = &m88e1510_probe,
-		.remove = &marvell_remove,
 		.config_init = &m88e1510_config_init,
 		.config_aneg = &m88e1510_config_aneg,
 		.read_status = &marvell_read_status,
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
 		.probe = m88e1510_probe,
-		.remove = &marvell_remove,
 		.config_init = &marvell_config_init,
 		.config_aneg = &m88e1510_config_aneg,
 		.read_status = &marvell_read_status,
 		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1545",
 		.probe = m88e1510_probe,
-		.remove = &marvell_remove,
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
 		.config_init = &marvell_config_init,

drivers/net/phy/phy_device.c+1−1

@@ -1864,7 +1864,7 @@ static struct phy_driver genphy_driver[] = { · 1863 unmodified lines
1864	.phy_id = 0xffffffff,	1864	.phy_id = 0xffffffff,
1865	.phy_id_mask = 0xffffffff,	1865	.phy_id_mask = 0xffffffff,
1866	.name = "Generic PHY",	1866	.name = "Generic PHY",
1867	.soft_reset = genphy_soft_reset,	1867	.soft_reset = genphy_no_soft_reset,
1868	.config_init = genphy_config_init,	1868	.config_init = genphy_config_init,
1869	.features = PHY_GBIT_FEATURES \| SUPPORTED_MII \|	1869	.features = PHY_GBIT_FEATURES \| SUPPORTED_MII \|
1870	SUPPORTED_AUI \| SUPPORTED_FIBRE \|	1870	SUPPORTED_AUI \| SUPPORTED_FIBRE \|

drivers/net/phy/spi_ks8995.c+2−1

 	if (err)
 		return err;
-	ks->regs_attr.size = ks->chip->regs_size;
 	memcpy(&ks->regs_attr, &ks8995_registers_attr, sizeof(ks->regs_attr));
+	ks->regs_attr.size = ks->chip->regs_size;
 	err = ks8995_reset(ks);
 	if (err)
 		return err;
+	sysfs_attr_init(&ks->regs_attr.attr);
 	err = sysfs_create_bin_file(&spi->dev.kobj, &ks->regs_attr);
 	if (err) {
 		dev_err(&spi->dev, "unable to create sysfs file, err=%d\n",

drivers/net/team/team.c+1−0

@@ -2072,6 +2072,7 @@ static int team_dev_type_check_change(struct net_device *dev, · 2071 unmodified lines
2072	static void team_setup(struct net_device *dev)	2072	static void team_setup(struct net_device *dev)
2073	{	2073	{
2074	ether_setup(dev);	2074	ether_setup(dev);
		2075	dev->max_mtu = ETH_MAX_MTU;
2075		2076
2076	dev->netdev_ops = &team_netdev_ops;	2077	dev->netdev_ops = &team_netdev_ops;
2077	dev->ethtool_ops = &team_ethtool_ops;	2078	dev->ethtool_ops = &team_ethtool_ops;

drivers/net/tun.c+17−4

 /* Net device open. */
 static int tun_net_open(struct net_device *dev)
 {
+	struct tun_struct *tun = netdev_priv(dev);
+	int i;
 	netif_tx_start_all_queues(dev);
+	for (i = 0; i < tun->numqueues; i++) {
+		struct tun_file *tfile;
+		tfile = rtnl_dereference(tun->tfiles[i]);
+		tfile->socket.sk->sk_write_space(tfile->socket.sk);
+	}
 	return 0;
 }
 	if (!skb_array_empty(&tfile->tx_array))
 		mask |= POLLIN | POLLRDNORM;
-	if (sock_writeable(sk) ||
+	if (tun->dev->flags & IFF_UP &&
-	    (!test_and_set_bit(SOCKWQ_ASYNC_NOSPACE, &sk->sk_socket->flags) &&
+	    (sock_writeable(sk) ||
-	     sock_writeable(sk)))
+	     (!test_and_set_bit(SOCKWQ_ASYNC_NOSPACE, &sk->sk_socket->flags) &&
+	      sock_writeable(sk))))
 		mask |= POLLOUT | POLLWRNORM;
 	if (tun->dev->reg_state != NETREG_REGISTERED)
 		return -EINVAL;
 	tun->set_features = features;
+	tun->dev->wanted_features &= ~TUN_USER_FEATURES;
+	tun->dev->wanted_features |= features;
 	netdev_update_features(tun->dev);
 	return 0;
 	int ret = 0;
 	pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
-	pr_info("%s\n", DRV_COPYRIGHT);
 	ret = rtnl_link_register(&tun_link_ops);
 	if (ret) {

drivers/net/usb/qmi_wwan.c+6−0

 		USB_VENDOR_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, USB_CLASS_VENDOR_SPEC, 0x01, 0x69),
 		.driver_info        = (unsigned long)&qmi_wwan_info,
 	},
+	{	/* Motorola Mapphone devices with MDM6600 */
+		USB_VENDOR_AND_INTERFACE_INFO(0x22b8, USB_CLASS_VENDOR_SPEC, 0xfb, 0xff),
+		.driver_info        = (unsigned long)&qmi_wwan_info,
+	},
 	/* 2. Combined interface devices matching on class+protocol */
 	{	/* Huawei E367 and possibly others in "Windows mode" */
 	{QMI_FIXED_INTF(0x413c, 0x81a9, 8)},	/* Dell Wireless 5808e Gobi(TM) 4G LTE Mobile Broadband Card */
 	{QMI_FIXED_INTF(0x413c, 0x81b1, 8)},	/* Dell Wireless 5809e Gobi(TM) 4G LTE Mobile Broadband Card */
 	{QMI_FIXED_INTF(0x413c, 0x81b3, 8)},	/* Dell Wireless 5809e Gobi(TM) 4G LTE Mobile Broadband Card (rev3) */
+	{QMI_FIXED_INTF(0x413c, 0x81b6, 8)},	/* Dell Wireless 5811e */
+	{QMI_FIXED_INTF(0x413c, 0x81b6, 10)},	/* Dell Wireless 5811e */
 	{QMI_FIXED_INTF(0x03f0, 0x4e1d, 8)},	/* HP lt4111 LTE/EV-DO/HSPA+ Gobi 4G Module */
 	{QMI_FIXED_INTF(0x22de, 0x9061, 3)},	/* WeTelecom WPD-600N */
 	{QMI_FIXED_INTF(0x1e0e, 0x9001, 5)},	/* SIMCom 7230E */

drivers/net/usb/r8152.c+17−7

 #define NETNEXT_VERSION		"08"
 /* Information for net */
-#define NET_VERSION		"8"
+#define NET_VERSION		"9"
 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
 #define RTL8153_RMS		RTL8153_MAX_PACKET
 #define RTL8152_TX_TIMEOUT	(5 * HZ)
 #define RTL8152_NAPI_WEIGHT	64
+#define rx_reserved_size(x)	((x) + VLAN_ETH_HLEN + CRC_SIZE + \
+				 sizeof(struct rx_desc) + RX_ALIGN)
 /* rtl8152 flags */
 enum rtl8152_flags {
 	spin_lock_init(&tp->rx_lock);
 	spin_lock_init(&tp->tx_lock);
 	INIT_LIST_HEAD(&tp->tx_free);
+	INIT_LIST_HEAD(&tp->rx_done);
 	skb_queue_head_init(&tp->tx_queue);
 	skb_queue_head_init(&tp->rx_queue);
 static void r8153_set_rx_early_size(struct r8152 *tp)
 {
-	u32 mtu = tp->netdev->mtu;
+	u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4;
-	u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
 	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
 }
 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
-	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
+	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
+	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
 		usleep_range(1000, 2000);
 	}
-	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
+	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
+	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
 	ocp_data &= ~TEREDO_WAKE_MASK;
 	dev->mtu = new_mtu;
-	if (netif_running(dev) && netif_carrier_ok(dev))
+	if (netif_running(dev)) {
-		r8153_set_rx_early_size(tp);
+		u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE;
+		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
+		if (netif_carrier_ok(dev))
+			r8153_set_rx_early_size(tp);
+	}
 	mutex_unlock(&tp->control);

drivers/net/vrf.c+5−2

 static netdev_tx_t vrf_xmit(struct sk_buff *skb, struct net_device *dev)
 {
+	int len = skb->len;
 	netdev_tx_t ret = is_ip_tx_frame(skb, dev);
 	if (likely(ret == NET_XMIT_SUCCESS || ret == NET_XMIT_CN)) {
 		u64_stats_update_begin(&dstats->syncp);
 		dstats->tx_pkts++;
-		dstats->tx_bytes += skb->len;
+		dstats->tx_bytes += len;
 		u64_stats_update_end(&dstats->syncp);
 	} else {
 		this_cpu_inc(dev->dstats->tx_drps);
 	}
 	if (rt6_local) {
-		if (rt6_local->rt6i_idev)
+		if (rt6_local->rt6i_idev) {
 			in6_dev_put(rt6_local->rt6i_idev);
+			rt6_local->rt6i_idev = NULL;
+		}
 		dst = &rt6_local->dst;
 		dev_put(dst->dev);

drivers/net/vxlan.c+40−33

 	return 0;
 }
+static int __vxlan_dev_create(struct net *net, struct net_device *dev,
+			      struct vxlan_config *conf)
+{
+	struct vxlan_net *vn = net_generic(net, vxlan_net_id);
+	struct vxlan_dev *vxlan = netdev_priv(dev);
+	int err;
+	err = vxlan_dev_configure(net, dev, conf, false);
+	if (err)
+		return err;
+	dev->ethtool_ops = &vxlan_ethtool_ops;
+	/* create an fdb entry for a valid default destination */
+	if (!vxlan_addr_any(&vxlan->default_dst.remote_ip)) {
+		err = vxlan_fdb_create(vxlan, all_zeros_mac,
+				       &vxlan->default_dst.remote_ip,
+				       NUD_REACHABLE | NUD_PERMANENT,
+				       NLM_F_EXCL | NLM_F_CREATE,
+				       vxlan->cfg.dst_port,
+				       vxlan->default_dst.remote_vni,
+				       vxlan->default_dst.remote_vni,
+				       vxlan->default_dst.remote_ifindex,
+				       NTF_SELF);
+		if (err)
+			return err;
+	}
+	err = register_netdevice(dev);
+	if (err) {
+		vxlan_fdb_delete_default(vxlan, vxlan->default_dst.remote_vni);
+		return err;
+	}
+	list_add(&vxlan->next, &vn->vxlan_list);
+	return 0;
+}
 static int vxlan_nl2conf(struct nlattr *tb[], struct nlattr *data[],
 			 struct net_device *dev, struct vxlan_config *conf,
 			 bool changelink)
 static int vxlan_newlink(struct net *src_net, struct net_device *dev,
 			 struct nlattr *tb[], struct nlattr *data[])
 {
-	struct vxlan_net *vn = net_generic(src_net, vxlan_net_id);
-	struct vxlan_dev *vxlan = netdev_priv(dev);
 	struct vxlan_config conf;
 	int err;
 	if (err)
 		return err;
-	err = vxlan_dev_configure(src_net, dev, &conf, false);
+	return __vxlan_dev_create(src_net, dev, &conf);
-	if (err)
-		return err;
-	dev->ethtool_ops = &vxlan_ethtool_ops;
-	/* create an fdb entry for a valid default destination */
-	if (!vxlan_addr_any(&vxlan->default_dst.remote_ip)) {
-		err = vxlan_fdb_create(vxlan, all_zeros_mac,
-				       &vxlan->default_dst.remote_ip,
-				       NUD_REACHABLE | NUD_PERMANENT,
-				       NLM_F_EXCL | NLM_F_CREATE,
-				       vxlan->cfg.dst_port,
-				       vxlan->default_dst.remote_vni,
-				       vxlan->default_dst.remote_vni,
-				       vxlan->default_dst.remote_ifindex,
-				       NTF_SELF);
-		if (err)
-			return err;
-	}
-	err = register_netdevice(dev);
-	if (err) {
-		vxlan_fdb_delete_default(vxlan, vxlan->default_dst.remote_vni);
-		return err;
-	}
-	list_add(&vxlan->next, &vn->vxlan_list);
-	return 0;
 }
 static int vxlan_changelink(struct net_device *dev, struct nlattr *tb[],
 	if (IS_ERR(dev))
 		return dev;
-	err = vxlan_dev_configure(net, dev, conf, false);
+	err = __vxlan_dev_create(net, dev, conf);
 	if (err < 0) {
 		free_netdev(dev);
 		return ERR_PTR(err);

drivers/net/wan/fsl_ucc_hdlc.c+2−2

 	/* set bd status and length */
 	bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
-	iowrite16be(bd_status, &bd->status);
 	iowrite16be(skb->len, &bd->length);
+	iowrite16be(bd_status, &bd->status);
 	/* Move to next BD in the ring */
 	if (!(bd_status & T_W_S))
 	struct sk_buff *skb;
 	hdlc_device *hdlc = dev_to_hdlc(dev);
 	struct qe_bd *bd;
-	u32 bd_status;
+	u16 bd_status;
 	u16 length, howmany = 0;
 	u8 *bdbuffer;
 	int i;

drivers/net/wimax/i2400m/usb.c+3−0

@@ -467,6 +467,9 @@ int i2400mu_probe(struct usb_interface *iface, · 466 unmodified lines
467	struct i2400mu *i2400mu;	467	struct i2400mu *i2400mu;
468	struct usb_device *usb_dev = interface_to_usbdev(iface);	468	struct usb_device *usb_dev = interface_to_usbdev(iface);
469		469
		470	if (iface->cur_altsetting->desc.bNumEndpoints < 4)
		471	return -ENODEV;
		472
470	if (usb_dev->speed != USB_SPEED_HIGH)	473	if (usb_dev->speed != USB_SPEED_HIGH)
471	dev_err(dev, "device not connected as high speed\n");	474	dev_err(dev, "device not connected as high speed\n");
472		475

drivers/net/wireless/ath/ath10k/hw.c+1−1

@@ -51,7 +51,7 @@ const struct ath10k_hw_regs qca6174_regs = { · 50 unmodified lines
51	.rtc_soc_base_address = 0x00000800,	51	.rtc_soc_base_address = 0x00000800,
52	.rtc_wmac_base_address = 0x00001000,	52	.rtc_wmac_base_address = 0x00001000,
53	.soc_core_base_address = 0x0003a000,	53	.soc_core_base_address = 0x0003a000,
54	.wlan_mac_base_address = 0x00020000,	54	.wlan_mac_base_address = 0x00010000,
55	.ce_wrapper_base_address = 0x00034000,	55	.ce_wrapper_base_address = 0x00034000,
56	.ce0_base_address = 0x00034400,	56	.ce0_base_address = 0x00034400,
57	.ce1_base_address = 0x00034800,	57	.ce1_base_address = 0x00034800,

drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c+3−2

 {
 	struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
-	/* Called when we need to transmit (a) frame(s) from agg queue */
+	/* Called when we need to transmit (a) frame(s) from agg or dqa queue */
 	iwl_mvm_sta_modify_sleep_tx_count(mvm, sta, reason, num_frames,
 					  tids, more_data, true);
 	for (tid = 0; tid < IWL_MAX_TID_COUNT; tid++) {
 		struct iwl_mvm_tid_data *tid_data = &mvmsta->tid_data[tid];
-		if (tid_data->state != IWL_AGG_ON &&
+		if (!iwl_mvm_is_dqa_supported(mvm) &&
+		    tid_data->state != IWL_AGG_ON &&
 		    tid_data->state != IWL_EMPTYING_HW_QUEUE_DELBA)
 			continue;

drivers/net/wireless/intel/iwlwifi/mvm/sta.c+6−5

 				       struct ieee80211_sta *sta,
 				       enum ieee80211_frame_release_type reason,
 				       u16 cnt, u16 tids, bool more_data,
-				       bool agg)
+				       bool single_sta_queue)
 {
 	struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
 	struct iwl_mvm_add_sta_cmd cmd = {
 	for_each_set_bit(tid, &_tids, IWL_MAX_TID_COUNT)
 		cmd.awake_acs |= BIT(tid_to_ucode_ac[tid]);
-	/* If we're releasing frames from aggregation queues then check if the
+	/* If we're releasing frames from aggregation or dqa queues then check
-	 * all queues combined that we're releasing frames from have
+	 * if all the queues that we're releasing frames from, combined, have:
 	 *  - more frames than the service period, in which case more_data
 	 *    needs to be set
 	 *  - fewer than 'cnt' frames, in which case we need to adjust the
 	 *    firmware command (but do that unconditionally)
 	 */
-	if (agg) {
+	if (single_sta_queue) {
 		int remaining = cnt;
 		int sleep_tx_count;
 			u16 n_queued;
 			tid_data = &mvmsta->tid_data[tid];
-			if (WARN(tid_data->state != IWL_AGG_ON &&
+			if (WARN(!iwl_mvm_is_dqa_supported(mvm) &&
+				 tid_data->state != IWL_AGG_ON &&
 				 tid_data->state != IWL_EMPTYING_HW_QUEUE_DELBA,
 				 "TID %d state is %d\n",
 				 tid, tid_data->state)) {

drivers/net/wireless/intel/iwlwifi/mvm/sta.h+1−1

@@ -547,7 +547,7 @@ void iwl_mvm_sta_modify_sleep_tx_count(struct iwl_mvm *mvm, · 546 unmodified lines
547	struct ieee80211_sta *sta,	547	struct ieee80211_sta *sta,
548	enum ieee80211_frame_release_type reason,	548	enum ieee80211_frame_release_type reason,
549	u16 cnt, u16 tids, bool more_data,	549	u16 cnt, u16 tids, bool more_data,
550	bool agg);	550	bool single_sta_queue);
551	int iwl_mvm_drain_sta(struct iwl_mvm mvm, struct iwl_mvm_sta mvmsta,	551	int iwl_mvm_drain_sta(struct iwl_mvm mvm, struct iwl_mvm_sta mvmsta,
552	bool drain);	552	bool drain);
553	void iwl_mvm_sta_modify_disable_tx(struct iwl_mvm *mvm,	553	void iwl_mvm_sta_modify_disable_tx(struct iwl_mvm *mvm,

drivers/net/wireless/intel/iwlwifi/mvm/tx.c+18−23

  *
  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
- * Copyright(c) 2016        Intel Deutschland GmbH
+ * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of version 2 of the GNU General Public License as
  *
  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
+ * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 	 * values.
 	 * Note that we don't need to make sure it isn't agg'd, since we're
 	 * TXing non-sta
+	 * For DQA mode - we shouldn't increase it though
 	 */
-	atomic_inc(&mvm->pending_frames[sta_id]);
+	if (!iwl_mvm_is_dqa_supported(mvm))
+		atomic_inc(&mvm->pending_frames[sta_id]);
 	return 0;
 }
 	spin_unlock(&mvmsta->lock);
-	/* Increase pending frames count if this isn't AMPDU */
+	/* Increase pending frames count if this isn't AMPDU or DQA queue */
-	if ((iwl_mvm_is_dqa_supported(mvm) &&
+	if (!iwl_mvm_is_dqa_supported(mvm) && !is_ampdu)
-	     mvmsta->tid_data[tx_cmd->tid_tspec].state != IWL_AGG_ON &&
-	     mvmsta->tid_data[tx_cmd->tid_tspec].state != IWL_AGG_STARTING) ||
-	    (!iwl_mvm_is_dqa_supported(mvm) && !is_ampdu))
 		atomic_inc(&mvm->pending_frames[mvmsta->sta_id]);
 	return 0;
 	lockdep_assert_held(&mvmsta->lock);
 	if ((tid_data->state == IWL_AGG_ON ||
-	     tid_data->state == IWL_EMPTYING_HW_QUEUE_DELBA) &&
+	     tid_data->state == IWL_EMPTYING_HW_QUEUE_DELBA ||
+	     iwl_mvm_is_dqa_supported(mvm)) &&
 	    iwl_mvm_tid_queued(tid_data) == 0) {
 		/*
-		 * Now that this aggregation queue is empty tell mac80211 so it
+		 * Now that this aggregation or DQA queue is empty tell
-		 * knows we no longer have frames buffered for the station on
+		 * mac80211 so it knows we no longer have frames buffered for
-		 * this TID (for the TIM bitmap calculation.)
+		 * the station on this TID (for the TIM bitmap calculation.)
 		 */
 		ieee80211_sta_set_buffered(sta, tid, false);
 	}
 	u8 skb_freed = 0;
 	u16 next_reclaimed, seq_ctl;
 	bool is_ndp = false;
-	bool txq_agg = false; /* Is this TXQ aggregated */
 	__skb_queue_head_init(&skbs);
 			info->flags |= IEEE80211_TX_STAT_ACK;
 			break;
 		case TX_STATUS_FAIL_DEST_PS:
+			/* In DQA, the FW should have stopped the queue and not
+			 * return this status
+			 */
+			WARN_ON(iwl_mvm_is_dqa_supported(mvm));
 			info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
 			break;
 		default:
 			bool send_eosp_ndp = false;
 			spin_lock_bh(&mvmsta->lock);
-			if (iwl_mvm_is_dqa_supported(mvm)) {
-				enum iwl_mvm_agg_state state;
-				state = mvmsta->tid_data[tid].state;
-				txq_agg = (state == IWL_AGG_ON ||
-					state == IWL_EMPTYING_HW_QUEUE_DELBA);
-			} else {
-				txq_agg = txq_id >= mvm->first_agg_queue;
-			}
 			if (!is_ndp) {
 				tid_data->next_reclaimed = next_reclaimed;
 	 * If the txq is not an AMPDU queue, there is no chance we freed
 	 * several skbs. Check that out...
 	 */
-	if (txq_agg)
+	if (iwl_mvm_is_dqa_supported(mvm) || txq_id >= mvm->first_agg_queue)
 		goto out;
 	/* We can't free more than one frame at once on a shared queue */
-	WARN_ON(!iwl_mvm_is_dqa_supported(mvm) && (skb_freed > 1));
+	WARN_ON(skb_freed > 1);
 	/* If we have still frames for this STA nothing to do here */
 	if (!atomic_sub_and_test(skb_freed, &mvm->pending_frames[sta_id]))

drivers/net/wireless/marvell/mwifiex/main.c+7−4

  * In case of any errors during inittialization, this function also ensures
  * proper cleanup before exiting.
  */
-static int mwifiex_register(void *card, struct mwifiex_if_ops *if_ops,
+static int mwifiex_register(void *card, struct device *dev,
-			    void **padapter)
+			    struct mwifiex_if_ops *if_ops, void **padapter)
 {
 	struct mwifiex_adapter *adapter;
 	int i;
 		return -ENOMEM;
 	*padapter = adapter;
+	adapter->dev = dev;
 	adapter->card = card;
 	/* Save interface specific operations in adapter */
 {
 	struct mwifiex_adapter *adapter;
-	if (mwifiex_register(card, if_ops, (void **)&adapter)) {
+	if (mwifiex_register(card, dev, if_ops, (void **)&adapter)) {
 		pr_err("%s: software init failed\n", __func__);
 		goto err_init_sw;
 	}
-	adapter->dev = dev;
 	mwifiex_probe_of(adapter);
 	adapter->iface_type = iface_type;
 	wiphy_unregister(adapter->wiphy);
 	wiphy_free(adapter->wiphy);
+	if (adapter->irq_wakeup >= 0)
+		device_init_wakeup(adapter->dev, false);
 	/* Unregister device */
 	mwifiex_dbg(adapter, INFO,
 		    "info: unregister device\n");

drivers/net/wireless/marvell/mwifiex/pcie.c+19−19

 	schedule_work(&card->work);
 }
+static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter)
+{
+	struct pcie_service_card *card = adapter->card;
+	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
+	if (reg->sleep_cookie)
+		mwifiex_pcie_delete_sleep_cookie_buf(adapter);
+	mwifiex_pcie_delete_cmdrsp_buf(adapter);
+	mwifiex_pcie_delete_evtbd_ring(adapter);
+	mwifiex_pcie_delete_rxbd_ring(adapter);
+	mwifiex_pcie_delete_txbd_ring(adapter);
+	card->cmdrsp_buf = NULL;
+}
 /*
  * This function initializes the PCI-E host memory space, WCB rings, etc.
  *
 /*
  * This function cleans up the allocated card buffers.
- *
- * The following are freed by this function -
- *      - TXBD ring buffers
- *      - RXBD ring buffers
- *      - Event BD ring buffers
- *      - Command response ring buffer
- *      - Sleep cookie buffer
  */
 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter)
 {
 				    "Failed to write driver not-ready signature\n");
 	}
+	mwifiex_pcie_free_buffers(adapter);
 	if (pdev) {
 		pci_iounmap(pdev, card->pci_mmap);
 		pci_iounmap(pdev, card->pci_mmap1);
 	pci_iounmap(pdev, card->pci_mmap1);
 }
-/* This function cleans up the PCI-E host memory space.
+/* This function cleans up the PCI-E host memory space. */
- * Some code is extracted from mwifiex_unregister_dev()
- *
- */
 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter)
 {
 	struct pcie_service_card *card = adapter->card;
 	adapter->seq_num = 0;
-	if (reg->sleep_cookie)
+	mwifiex_pcie_free_buffers(adapter);
-		mwifiex_pcie_delete_sleep_cookie_buf(adapter);
-	mwifiex_pcie_delete_cmdrsp_buf(adapter);
-	mwifiex_pcie_delete_evtbd_ring(adapter);
-	mwifiex_pcie_delete_rxbd_ring(adapter);
-	mwifiex_pcie_delete_txbd_ring(adapter);
-	card->cmdrsp_buf = NULL;
 }
 static struct mwifiex_if_ops pcie_ops = {

drivers/net/xen-netback/interface.c+17−9

 {
 	struct xenvif *vif = netdev_priv(dev);
 	struct xenvif_queue *queue = NULL;
-	unsigned int num_queues = vif->num_queues;
+	unsigned int num_queues;
 	u16 index;
 	struct xenvif_rx_cb *cb;
 	BUG_ON(skb->dev != dev);
-	/* Drop the packet if queues are not set up */
+	/* Drop the packet if queues are not set up.
+	 * This handler should be called inside an RCU read section
+	 * so we don't need to enter it here explicitly.
+	 */
+	num_queues = READ_ONCE(vif->num_queues);
 	if (num_queues < 1)
 		goto drop;
 {
 	struct xenvif *vif = netdev_priv(dev);
 	struct xenvif_queue *queue = NULL;
+	unsigned int num_queues;
 	u64 rx_bytes = 0;
 	u64 rx_packets = 0;
 	u64 tx_bytes = 0;
 	u64 tx_packets = 0;
 	unsigned int index;
-	spin_lock(&vif->lock);
+	rcu_read_lock();
-	if (vif->queues == NULL)
+	num_queues = READ_ONCE(vif->num_queues);
-		goto out;
 	/* Aggregate tx and rx stats from each queue */
-	for (index = 0; index < vif->num_queues; ++index) {
+	for (index = 0; index < num_queues; ++index) {
 		queue = &vif->queues[index];
 		rx_bytes += queue->stats.rx_bytes;
 		rx_packets += queue->stats.rx_packets;
 		tx_packets += queue->stats.tx_packets;
 	}
-out:
+	rcu_read_unlock();
-	spin_unlock(&vif->lock);
 	vif->dev->stats.rx_bytes = rx_bytes;
 	vif->dev->stats.rx_packets = rx_packets;
 				     struct ethtool_stats *stats, u64 * data)
 {
 	struct xenvif *vif = netdev_priv(dev);
-	unsigned int num_queues = vif->num_queues;
+	unsigned int num_queues;
 	int i;
 	unsigned int queue_index;
+	rcu_read_lock();
+	num_queues = READ_ONCE(vif->num_queues);
 	for (i = 0; i < ARRAY_SIZE(xenvif_stats); i++) {
 		unsigned long accum = 0;
 		for (queue_index = 0; queue_index < num_queues; ++queue_index) {
 		}
 		data[i] = accum;
 	}
+	rcu_read_unlock();
 }
 static void xenvif_get_strings(struct net_device *dev, u32 stringset, u8 * data)

drivers/net/xen-netback/netback.c+1−1

@@ -214,7 +214,7 @@ static void xenvif_fatal_tx_err(struct xenvif *vif) · 213 unmodified lines
214	netdev_err(vif->dev, "fatal error; disabling device\n");	214	netdev_err(vif->dev, "fatal error; disabling device\n");
215	vif->disabled = true;	215	vif->disabled = true;
216	/* Disable the vif from queue 0's kthread */	216	/* Disable the vif from queue 0's kthread */
217	if (vif->queues)	217	if (vif->num_queues)
218	xenvif_kick_thread(&vif->queues[0]);	218	xenvif_kick_thread(&vif->queues[0]);
219	}	219	}
220		220

drivers/net/xen-netback/xenbus.c+10−10

 	struct xenvif *vif = be->vif;
 	if (vif) {
+		unsigned int num_queues = vif->num_queues;
 		unsigned int queue_index;
-		struct xenvif_queue *queues;
 		xen_unregister_watchers(vif);
 #ifdef CONFIG_DEBUG_FS
 		xenvif_debugfs_delif(vif);
 #endif /* CONFIG_DEBUG_FS */
 		xenvif_disconnect_data(vif);
-		for (queue_index = 0;
-		     queue_index < vif->num_queues;
-		     ++queue_index)
-			xenvif_deinit_queue(&vif->queues[queue_index]);
-		spin_lock(&vif->lock);
+		/* At this point some of the handlers may still be active
-		queues = vif->queues;
+		 * so we need to have additional synchronization here.
+		 */
 		vif->num_queues = 0;
-		vif->queues = NULL;
+		synchronize_net();
-		spin_unlock(&vif->lock);
-		vfree(queues);
+		for (queue_index = 0; queue_index < num_queues; ++queue_index)
+			xenvif_deinit_queue(&vif->queues[queue_index]);
+		vfree(vif->queues);
+		vif->queues = NULL;
 		xenvif_disconnect_ctrl(vif);
 	}

drivers/nvdimm/bus.c+6−0

 	rc = nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, NULL);
 	if (rc < 0)
 		goto out_unlock;
+	nvdimm_bus_unlock(&nvdimm_bus->dev);
 	if (copy_to_user(p, buf, buf_len))
 		rc = -EFAULT;
+	vfree(buf);
+	return rc;
  out_unlock:
 	nvdimm_bus_unlock(&nvdimm_bus->dev);
  out:

drivers/nvdimm/claim.c+9−1

@@ -243,7 +243,15 @@ static int nsio_rw_bytes(struct nd_namespace_common *ndns, · 242 unmodified lines
243	}	243	}
244		244
245	if (unlikely(is_bad_pmem(&nsio->bb, sector, sz_align))) {	245	if (unlikely(is_bad_pmem(&nsio->bb, sector, sz_align))) {
246	if (IS_ALIGNED(offset, 512) && IS_ALIGNED(size, 512)) {	246	/*
		247	* FIXME: nsio_rw_bytes() may be called from atomic
		248	* context in the btt case and nvdimm_clear_poison()
		249	* takes a sleeping lock. Until the locking can be
		250	* reworked this capability requires that the namespace
		251	* is not claimed by btt.
		252	*/
		253	if (IS_ALIGNED(offset, 512) && IS_ALIGNED(size, 512)
		254	&& (!ndns->claim \|\| !is_nd_btt(ndns->claim))) {
247	long cleared;	255	long cleared;
248		256
249	cleared = nvdimm_clear_poison(&ndns->dev, offset, size);	257	cleared = nvdimm_clear_poison(&ndns->dev, offset, size);

drivers/nvdimm/dimm_devs.c+11−66

@@ -395,7 +395,7 @@ EXPORT_SYMBOL_GPL(nvdimm_create); · 394 unmodified lines
395		395
396	int alias_dpa_busy(struct device dev, void data)	396	int alias_dpa_busy(struct device dev, void data)
397	{	397	{
398	resource_size_t map_end, blk_start, new, busy;	398	resource_size_t map_end, blk_start, new;
399	struct blk_alloc_info *info = data;	399	struct blk_alloc_info *info = data;
400	struct nd_mapping *nd_mapping;	400	struct nd_mapping *nd_mapping;
401	struct nd_region *nd_region;	401	struct nd_region *nd_region;
@@ -436,29 +436,19 @@ int alias_dpa_busy(struct device dev, void data) · 34 unmodified lines
436	retry:	436	retry:
437	/*	437	/*
438	* Find the free dpa from the end of the last pmem allocation to	438	* Find the free dpa from the end of the last pmem allocation to
439	* the end of the interleave-set mapping that is not already	439	* the end of the interleave-set mapping.
440	* covered by a blk allocation.
441	*/	440	*/
442	busy = 0;
443	for_each_dpa_resource(ndd, res) {	441	for_each_dpa_resource(ndd, res) {
		442	if (strncmp(res->name, "pmem", 4) != 0)
		443	continue;
444	if ((res->start >= blk_start && res->start < map_end)	444	if ((res->start >= blk_start && res->start < map_end)
445	\|\| (res->end >= blk_start	445	\|\| (res->end >= blk_start
446	&& res->end <= map_end)) {	446	&& res->end <= map_end)) {
447	if (strncmp(res->name, "pmem", 4) == 0) {	447	new = max(blk_start, min(map_end + 1, res->end + 1));
448	new = max(blk_start, min(map_end + 1,	448	if (new != blk_start) {
449	res->end + 1));	449	blk_start = new;
450	if (new != blk_start) {	450	goto retry;
451	blk_start = new;	451	}
452	goto retry;
453	}
454	} else
455	busy += min(map_end, res->end)
456	- max(nd_mapping->start, res->start) + 1;
457	} else if (nd_mapping->start > res->start
458	&& map_end < res->end) {
459	/* total eclipse of the PMEM region mapping */
460	busy += nd_mapping->size;
461	break;
462	}	452	}
463	}	453	}
464		454
@@ -470,52 +460,11 @@ int alias_dpa_busy(struct device dev, void data) · 5 unmodified lines
470	return 1;	460	return 1;
471	}	461	}
472		462
473	info->available -= blk_start - nd_mapping->start + busy;	463	info->available -= blk_start - nd_mapping->start;
474		464
475	return 0;	465	return 0;
476	}	466	}
477		467
478	static int blk_dpa_busy(struct device dev, void data)
479	{
480	struct blk_alloc_info *info = data;
481	struct nd_mapping *nd_mapping;
482	struct nd_region *nd_region;
483	resource_size_t map_end;
484	int i;
485
486	if (!is_nd_pmem(dev))
487	return 0;
488
489	nd_region = to_nd_region(dev);
490	for (i = 0; i < nd_region->ndr_mappings; i++) {
491	nd_mapping = &nd_region->mapping[i];
492	if (nd_mapping->nvdimm == info->nd_mapping->nvdimm)
493	break;
494	}
495
496	if (i >= nd_region->ndr_mappings)
497	return 0;
498
499	map_end = nd_mapping->start + nd_mapping->size - 1;
500	if (info->res->start >= nd_mapping->start
501	&& info->res->start < map_end) {
502	if (info->res->end <= map_end) {
503	info->busy = 0;
504	return 1;
505	} else {
506	info->busy -= info->res->end - map_end;
507	return 0;
508	}
509	} else if (info->res->end >= nd_mapping->start
510	&& info->res->end <= map_end) {
511	info->busy -= nd_mapping->start - info->res->start;
512	return 0;
513	} else {
514	info->busy -= nd_mapping->size;
515	return 0;
516	}
517	}
518
519	/**	468	/**
520	* nd_blk_available_dpa - account the unused dpa of BLK region	469	* nd_blk_available_dpa - account the unused dpa of BLK region
521	* @nd_mapping: container of dpa-resource-root + labels	470	* @nd_mapping: container of dpa-resource-root + labels
@@ -545,11 +494,7 @@ resource_size_t nd_blk_available_dpa(struct nd_region *nd_region) · 23 unmodified lines
545	for_each_dpa_resource(ndd, res) {	494	for_each_dpa_resource(ndd, res) {
546	if (strncmp(res->name, "blk", 3) != 0)	495	if (strncmp(res->name, "blk", 3) != 0)
547	continue;	496	continue;
548		497	info.available -= resource_size(res);
549	info.res = res;
550	info.busy = resource_size(res);
551	device_for_each_child(&nvdimm_bus->dev, &info, blk_dpa_busy);
552	info.available -= info.busy;
553	}	498	}
554		499
555	return info.available;	500	return info.available;

drivers/nvme/host/rdma.c+14−14

 	struct ib_device *ibdev = dev->dev;
 	int ret;
-	BUG_ON(queue_idx >= ctrl->queue_count);
 	ret = nvme_rdma_alloc_qe(ibdev, &req->sqe, sizeof(struct nvme_command),
 			DMA_TO_DEVICE);
 	if (ret)
 static int nvme_rdma_init_io_queues(struct nvme_rdma_ctrl *ctrl)
 {
+	struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
+	unsigned int nr_io_queues;
 	int i, ret;
+	nr_io_queues = min(opts->nr_io_queues, num_online_cpus());
+	ret = nvme_set_queue_count(&ctrl->ctrl, &nr_io_queues);
+	if (ret)
+		return ret;
+	ctrl->queue_count = nr_io_queues + 1;
+	if (ctrl->queue_count < 2)
+		return 0;
+	dev_info(ctrl->ctrl.device,
+		"creating %d I/O queues.\n", nr_io_queues);
 	for (i = 1; i < ctrl->queue_count; i++) {
 		ret = nvme_rdma_init_queue(ctrl, i,
 					   ctrl->ctrl.opts->queue_size);
 static int nvme_rdma_create_io_queues(struct nvme_rdma_ctrl *ctrl)
 {
-	struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
 	int ret;
-	ret = nvme_set_queue_count(&ctrl->ctrl, &opts->nr_io_queues);
-	if (ret)
-		return ret;
-	ctrl->queue_count = opts->nr_io_queues + 1;
-	if (ctrl->queue_count < 2)
-		return 0;
-	dev_info(ctrl->ctrl.device,
-		"creating %d I/O queues.\n", opts->nr_io_queues);
 	ret = nvme_rdma_init_io_queues(ctrl);
 	if (ret)
 		return ret;

drivers/nvme/target/core.c+10−1

 	ctrl->sqs[qid] = sq;
 }
+static void nvmet_confirm_sq(struct percpu_ref *ref)
+{
+	struct nvmet_sq *sq = container_of(ref, struct nvmet_sq, ref);
+	complete(&sq->confirm_done);
+}
 void nvmet_sq_destroy(struct nvmet_sq *sq)
 {
 	/*
 	 */
 	if (sq->ctrl && sq->ctrl->sqs && sq->ctrl->sqs[0] == sq)
 		nvmet_async_events_free(sq->ctrl);
-	percpu_ref_kill(&sq->ref);
+	percpu_ref_kill_and_confirm(&sq->ref, nvmet_confirm_sq);
+	wait_for_completion(&sq->confirm_done);
 	wait_for_completion(&sq->free_done);
 	percpu_ref_exit(&sq->ref);
 		return ret;
 	}
 	init_completion(&sq->free_done);
+	init_completion(&sq->confirm_done);
 	return 0;
 }

drivers/nvme/target/loop.c+51−39

@@ -223,8 +223,6 @@ static void nvme_loop_submit_async_event(struct nvme_ctrl *arg, int aer_idx) · 222 unmodified lines
223	static int nvme_loop_init_iod(struct nvme_loop_ctrl *ctrl,	223	static int nvme_loop_init_iod(struct nvme_loop_ctrl *ctrl,
224	struct nvme_loop_iod *iod, unsigned int queue_idx)	224	struct nvme_loop_iod *iod, unsigned int queue_idx)
225	{	225	{
226	BUG_ON(queue_idx >= ctrl->queue_count);
227
228	iod->req.cmd = &iod->cmd;	226	iod->req.cmd = &iod->cmd;
229	iod->req.rsp = &iod->rsp;	227	iod->req.rsp = &iod->rsp;
230	iod->queue = &ctrl->queues[queue_idx];	228	iod->queue = &ctrl->queues[queue_idx];
@@ -288,9 +286,9 @@ static struct blk_mq_ops nvme_loop_admin_mq_ops = { · 57 unmodified lines
288		286
289	static void nvme_loop_destroy_admin_queue(struct nvme_loop_ctrl *ctrl)	287	static void nvme_loop_destroy_admin_queue(struct nvme_loop_ctrl *ctrl)
290	{	288	{
		289	nvmet_sq_destroy(&ctrl->queues[0].nvme_sq);
291	blk_cleanup_queue(ctrl->ctrl.admin_q);	290	blk_cleanup_queue(ctrl->ctrl.admin_q);
292	blk_mq_free_tag_set(&ctrl->admin_tag_set);	291	blk_mq_free_tag_set(&ctrl->admin_tag_set);
293	nvmet_sq_destroy(&ctrl->queues[0].nvme_sq);
294	}	292	}
295		293
296	static void nvme_loop_free_ctrl(struct nvme_ctrl *nctrl)	294	static void nvme_loop_free_ctrl(struct nvme_ctrl *nctrl)
@@ -314,6 +312,43 @@ free_ctrl: · 17 unmodified lines
314	kfree(ctrl);	312	kfree(ctrl);
315	}	313	}
316		314
		315	static void nvme_loop_destroy_io_queues(struct nvme_loop_ctrl *ctrl)
		316	{
		317	int i;
		318
		319	for (i = 1; i < ctrl->queue_count; i++)
		320	nvmet_sq_destroy(&ctrl->queues[i].nvme_sq);
		321	}
		322
		323	static int nvme_loop_init_io_queues(struct nvme_loop_ctrl *ctrl)
		324	{
		325	struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
		326	unsigned int nr_io_queues;
		327	int ret, i;
		328
		329	nr_io_queues = min(opts->nr_io_queues, num_online_cpus());
		330	ret = nvme_set_queue_count(&ctrl->ctrl, &nr_io_queues);
		331	if (ret \|\| !nr_io_queues)
		332	return ret;
		333
		334	dev_info(ctrl->ctrl.device, "creating %d I/O queues.\n", nr_io_queues);
		335
		336	for (i = 1; i <= nr_io_queues; i++) {
		337	ctrl->queues[i].ctrl = ctrl;
		338	ret = nvmet_sq_init(&ctrl->queues[i].nvme_sq);
		339	if (ret)
		340	goto out_destroy_queues;
		341
		342	ctrl->queue_count++;
		343	}
		344
		345	return 0;
		346
		347	out_destroy_queues:
		348	nvme_loop_destroy_io_queues(ctrl);
		349	return ret;
		350	}
		351
317	static int nvme_loop_configure_admin_queue(struct nvme_loop_ctrl *ctrl)	352	static int nvme_loop_configure_admin_queue(struct nvme_loop_ctrl *ctrl)
318	{	353	{
319	int error;	354	int error;
@@ -385,17 +420,13 @@ out_free_sq: · 65 unmodified lines
385		420
386	static void nvme_loop_shutdown_ctrl(struct nvme_loop_ctrl *ctrl)	421	static void nvme_loop_shutdown_ctrl(struct nvme_loop_ctrl *ctrl)
387	{	422	{
388	int i;
389
390	nvme_stop_keep_alive(&ctrl->ctrl);	423	nvme_stop_keep_alive(&ctrl->ctrl);
391		424
392	if (ctrl->queue_count > 1) {	425	if (ctrl->queue_count > 1) {
393	nvme_stop_queues(&ctrl->ctrl);	426	nvme_stop_queues(&ctrl->ctrl);
394	blk_mq_tagset_busy_iter(&ctrl->tag_set,	427	blk_mq_tagset_busy_iter(&ctrl->tag_set,
395	nvme_cancel_request, &ctrl->ctrl);	428	nvme_cancel_request, &ctrl->ctrl);
396		429	nvme_loop_destroy_io_queues(ctrl);
397	for (i = 1; i < ctrl->queue_count; i++)
398	nvmet_sq_destroy(&ctrl->queues[i].nvme_sq);
399	}	430	}
400		431
401	if (ctrl->ctrl.state == NVME_CTRL_LIVE)	432	if (ctrl->ctrl.state == NVME_CTRL_LIVE)
@@ -467,19 +498,14 @@ static void nvme_loop_reset_ctrl_work(struct work_struct *work) · 65 unmodified lines
467	if (ret)	498	if (ret)
468	goto out_disable;	499	goto out_disable;
469		500
470	for (i = 1; i <= ctrl->ctrl.opts->nr_io_queues; i++) {	501	ret = nvme_loop_init_io_queues(ctrl);
471	ctrl->queues[i].ctrl = ctrl;	502	if (ret)
472	ret = nvmet_sq_init(&ctrl->queues[i].nvme_sq);	503	goto out_destroy_admin;
473	if (ret)
474	goto out_free_queues;
475
476	ctrl->queue_count++;
477	}
478		504
479	for (i = 1; i <= ctrl->ctrl.opts->nr_io_queues; i++) {	505	for (i = 1; i < ctrl->queue_count; i++) {
480	ret = nvmf_connect_io_queue(&ctrl->ctrl, i);	506	ret = nvmf_connect_io_queue(&ctrl->ctrl, i);
481	if (ret)	507	if (ret)
482	goto out_free_queues;	508	goto out_destroy_io;
483	}	509	}
484		510
485	changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);	511	changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);
@@ -492,9 +518,9 @@ static void nvme_loop_reset_ctrl_work(struct work_struct *work) · 6 unmodified lines
492		518
493	return;	519	return;
494		520
495	out_free_queues:	521	out_destroy_io:
496	for (i = 1; i < ctrl->queue_count; i++)	522	nvme_loop_destroy_io_queues(ctrl);
497	nvmet_sq_destroy(&ctrl->queues[i].nvme_sq);	523	out_destroy_admin:
498	nvme_loop_destroy_admin_queue(ctrl);	524	nvme_loop_destroy_admin_queue(ctrl);
499	out_disable:	525	out_disable:
500	dev_warn(ctrl->ctrl.device, "Removing after reset failure\n");	526	dev_warn(ctrl->ctrl.device, "Removing after reset failure\n");
@@ -533,25 +559,12 @@ static const struct nvme_ctrl_ops nvme_loop_ctrl_ops = { · 32 unmodified lines
533		559
534	static int nvme_loop_create_io_queues(struct nvme_loop_ctrl *ctrl)	560	static int nvme_loop_create_io_queues(struct nvme_loop_ctrl *ctrl)
535	{	561	{
536	struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
537	int ret, i;	562	int ret, i;
538		563
539	ret = nvme_set_queue_count(&ctrl->ctrl, &opts->nr_io_queues);	564	ret = nvme_loop_init_io_queues(ctrl);
540	if (ret \|\| !opts->nr_io_queues)	565	if (ret)
541	return ret;	566	return ret;
542		567
543	dev_info(ctrl->ctrl.device, "creating %d I/O queues.\n",
544	opts->nr_io_queues);
545
546	for (i = 1; i <= opts->nr_io_queues; i++) {
547	ctrl->queues[i].ctrl = ctrl;
548	ret = nvmet_sq_init(&ctrl->queues[i].nvme_sq);
549	if (ret)
550	goto out_destroy_queues;
551
552	ctrl->queue_count++;
553	}
554
555	memset(&ctrl->tag_set, 0, sizeof(ctrl->tag_set));	568	memset(&ctrl->tag_set, 0, sizeof(ctrl->tag_set));
556	ctrl->tag_set.ops = &nvme_loop_mq_ops;	569	ctrl->tag_set.ops = &nvme_loop_mq_ops;
557	ctrl->tag_set.queue_depth = ctrl->ctrl.opts->queue_size;	570	ctrl->tag_set.queue_depth = ctrl->ctrl.opts->queue_size;
@@ -575,7 +588,7 @@ static int nvme_loop_create_io_queues(struct nvme_loop_ctrl *ctrl) · 17 unmodified lines
575	goto out_free_tagset;	588	goto out_free_tagset;
576	}	589	}
577		590
578	for (i = 1; i <= opts->nr_io_queues; i++) {	591	for (i = 1; i < ctrl->queue_count; i++) {
579	ret = nvmf_connect_io_queue(&ctrl->ctrl, i);	592	ret = nvmf_connect_io_queue(&ctrl->ctrl, i);
580	if (ret)	593	if (ret)
581	goto out_cleanup_connect_q;	594	goto out_cleanup_connect_q;
@@ -588,8 +601,7 @@ out_cleanup_connect_q: · 6 unmodified lines
588	out_free_tagset:	601	out_free_tagset:
589	blk_mq_free_tag_set(&ctrl->tag_set);	602	blk_mq_free_tag_set(&ctrl->tag_set);
590	out_destroy_queues:	603	out_destroy_queues:
591	for (i = 1; i < ctrl->queue_count; i++)	604	nvme_loop_destroy_io_queues(ctrl);
592	nvmet_sq_destroy(&ctrl->queues[i].nvme_sq);
593	return ret;	605	return ret;
594	}	606	}
595		607

drivers/nvme/target/nvmet.h+1−0

@@ -73,6 +73,7 @@ struct nvmet_sq { · 72 unmodified lines
73	u16 qid;	73	u16 qid;
74	u16 size;	74	u16 size;
75	struct completion free_done;	75	struct completion free_done;
		76	struct completion confirm_done;
76	};	77	};
77		78
78	/**	79	/**

drivers/nvme/target/rdma.c+3−5

 {
 	u16 status;
-	cmd->queue = queue;
-	cmd->n_rdma = 0;
-	cmd->req.port = queue->port;
 	ib_dma_sync_single_for_cpu(queue->dev->device,
 		cmd->cmd->sge[0].addr, cmd->cmd->sge[0].length,
 		DMA_FROM_DEVICE);
 	cmd->queue = queue;
 	rsp = nvmet_rdma_get_rsp(queue);
+	rsp->queue = queue;
 	rsp->cmd = cmd;
 	rsp->flags = 0;
 	rsp->req.cmd = cmd->nvme_cmd;
+	rsp->req.port = queue->port;
+	rsp->n_rdma = 0;
 	if (unlikely(queue->state != NVMET_RDMA_Q_LIVE)) {
 		unsigned long flags;

drivers/parport/share.c+4−2

 	 * pardevice fields. -arca
 	 */
 	port->ops->init_state(par_dev, par_dev->state);
-	port->proc_device = par_dev;
+	if (!test_and_set_bit(PARPORT_DEVPROC_REGISTERED, &port->devflags)) {
-	parport_device_proc_register(par_dev);
+		port->proc_device = par_dev;
+		parport_device_proc_register(par_dev);
+	}
 	return par_dev;

drivers/phy/Kconfig+1−8

 config PHY_QCOM_USB_HS
 	tristate "Qualcomm USB HS PHY module"
 	depends on USB_ULPI_BUS
+	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
 	select GENERIC_PHY
 	help
 	  Support for the USB high-speed ULPI compliant phy on Qualcomm
 	  and GXBB SoCs.
 	  If unsure, say N.
-config PHY_NSP_USB3
-	tristate "Broadcom NorthStar plus USB3 PHY driver"
-	depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
-	select GENERIC_PHY
-	default ARCH_BCM_NSP
-	help
-	  Enable this to support the Broadcom Northstar plus USB3 PHY.
-	  If unsure, say N.
 endmenu

drivers/phy/Makefile+0−1

@@ -62,4 +62,3 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o · 61 unmodified lines
62	obj-$(CONFIG_ARCH_TEGRA) += tegra/	62	obj-$(CONFIG_ARCH_TEGRA) += tegra/
63	obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o	63	obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
64	obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o	64	obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
65	obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o

drivers/phy/phy-bcm-nsp-usb3.c+0−177

@@ -1,177 +0,0 @@
1	/*
2	* Copyright (C) 2016 Broadcom
3	*
4	* This program is free software; you can redistribute it and/or
5	* modify it under the terms of the GNU General Public License as
6	* published by the Free Software Foundation version 2.
7	*
8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
9	* kind, whether express or implied; without even the implied warranty
10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11	* GNU General Public License for more details.
12	*/
13
14	#include <linux/delay.h>
15	#include <linux/io.h>
16	#include <linux/kernel.h>
17	#include <linux/mfd/syscon.h>
18	#include <linux/mdio.h>
19	#include <linux/module.h>
20	#include <linux/of.h>
21	#include <linux/of_address.h>
22	#include <linux/phy/phy.h>
23	#include <linux/regmap.h>
24
25	#define NSP_USB3_RST_CTRL_OFFSET 0x3f8
26
27	/* mdio reg access */
28	#define NSP_USB3_PHY_BASE_ADDR_REG 0x1f
29
30	#define NSP_USB3_PHY_PLL30_BLOCK 0x8000
31	#define NSP_USB3_PLL_CONTROL 0x01
32	#define NSP_USB3_PLLA_CONTROL0 0x0a
33	#define NSP_USB3_PLLA_CONTROL1 0x0b
34
35	#define NSP_USB3_PHY_TX_PMD_BLOCK 0x8040
36	#define NSP_USB3_TX_PMD_CONTROL1 0x01
37
38	#define NSP_USB3_PHY_PIPE_BLOCK 0x8060
39	#define NSP_USB3_LFPS_CMP 0x02
40	#define NSP_USB3_LFPS_DEGLITCH 0x03
41
42	struct nsp_usb3_phy {
43	struct regmap *usb3_ctrl;
44	struct phy *phy;
45	struct mdio_device *mdiodev;
46	};
47
48	static int nsp_usb3_phy_init(struct phy *phy)
49	{
50	struct nsp_usb3_phy *iphy = phy_get_drvdata(phy);
51	struct mii_bus *bus = iphy->mdiodev->bus;
52	int addr = iphy->mdiodev->addr;
53	u32 data;
54	int rc;
55
56	rc = regmap_read(iphy->usb3_ctrl, 0, &data);
57	if (rc)
58	return rc;
59	data \|= 1;
60	rc = regmap_write(iphy->usb3_ctrl, 0, data);
61	if (rc)
62	return rc;
63
64	rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 1);
65	if (rc)
66	return rc;
67
68	rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
69	NSP_USB3_PHY_PLL30_BLOCK);
70	if (rc)
71	return rc;
72
73	rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x1000);
74	if (rc)
75	return rc;
76
77	rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL0, 0x6400);
78	if (rc)
79	return rc;
80
81	rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0xc000);
82	if (rc)
83	return rc;
84
85	rc = mdiobus_write(bus, addr, NSP_USB3_PLLA_CONTROL1, 0x8000);
86	if (rc)
87	return rc;
88
89	rc = regmap_write(iphy->usb3_ctrl, NSP_USB3_RST_CTRL_OFFSET, 0);
90	if (rc)
91	return rc;
92
93	rc = mdiobus_write(bus, addr, NSP_USB3_PLL_CONTROL, 0x9000);
94	if (rc)
95	return rc;
96
97	rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
98	NSP_USB3_PHY_PIPE_BLOCK);
99	if (rc)
100	return rc;
101
102	rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_CMP, 0xf30d);
103	if (rc)
104	return rc;
105
106	rc = mdiobus_write(bus, addr, NSP_USB3_LFPS_DEGLITCH, 0x6302);
107	if (rc)
108	return rc;
109
110	rc = mdiobus_write(bus, addr, NSP_USB3_PHY_BASE_ADDR_REG,
111	NSP_USB3_PHY_TX_PMD_BLOCK);
112	if (rc)
113	return rc;
114
115	rc = mdiobus_write(bus, addr, NSP_USB3_TX_PMD_CONTROL1, 0x1003);
116
117	return rc;
118	}
119
120	static struct phy_ops nsp_usb3_phy_ops = {
121	.init = nsp_usb3_phy_init,
122	.owner = THIS_MODULE,
123	};
124
125	static int nsp_usb3_phy_probe(struct mdio_device *mdiodev)
126	{
127	struct device *dev = &mdiodev->dev;
128	struct phy_provider *provider;
129	struct nsp_usb3_phy *iphy;
130
131	iphy = devm_kzalloc(dev, sizeof(*iphy), GFP_KERNEL);
132	if (!iphy)
133	return -ENOMEM;
134	iphy->mdiodev = mdiodev;
135
136	iphy->usb3_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
137	"usb3-ctrl-syscon");
138	if (IS_ERR(iphy->usb3_ctrl))
139	return PTR_ERR(iphy->usb3_ctrl);
140
141	iphy->phy = devm_phy_create(dev, dev->of_node, &nsp_usb3_phy_ops);
142	if (IS_ERR(iphy->phy)) {
143	dev_err(dev, "failed to create PHY\n");
144	return PTR_ERR(iphy->phy);
145	}
146
147	phy_set_drvdata(iphy->phy, iphy);
148
149	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
150	if (IS_ERR(provider)) {
151	dev_err(dev, "could not register PHY provider\n");
152	return PTR_ERR(provider);
153	}
154
155	return 0;
156	}
157
158	static const struct of_device_id nsp_usb3_phy_of_match[] = {
159	{.compatible = "brcm,nsp-usb3-phy",},
160	{ /* sentinel */ }
161	};
162
163	static struct mdio_driver nsp_usb3_phy_driver = {
164	.mdiodrv = {
165	.driver = {
166	.name = "nsp-usb3-phy",
167	.of_match_table = nsp_usb3_phy_of_match,
168	},
169	},
170	.probe = nsp_usb3_phy_probe,
171	};
172
173	mdio_module_driver(nsp_usb3_phy_driver);
174
175	MODULE_DESCRIPTION("Broadcom NSP USB3 PHY driver");
176	MODULE_LICENSE("GPL v2");
177	MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com");

drivers/phy/phy-exynos-pcie.c+2−2

@@ -254,8 +254,8 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev) · 253 unmodified lines
254		254
255	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);	255	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
256	exynos_phy->blk_base = devm_ioremap_resource(dev, res);	256	exynos_phy->blk_base = devm_ioremap_resource(dev, res);
257	if (IS_ERR(exynos_phy->phy_base))	257	if (IS_ERR(exynos_phy->blk_base))
258	return PTR_ERR(exynos_phy->phy_base);	258	return PTR_ERR(exynos_phy->blk_base);
259		259
260	exynos_phy->drv_data = drv_data;	260	exynos_phy->drv_data = drv_data;
261		261

drivers/platform/x86/asus-nb-wmi.c+2−47

@@ -103,15 +103,6 @@ static struct quirk_entry quirk_asus_x200ca = { · 102 unmodified lines
103	.wapf = 2,	103	.wapf = 2,
104	};	104	};
105		105
106	static struct quirk_entry quirk_no_rfkill = {
107	.no_rfkill = true,
108	};
109
110	static struct quirk_entry quirk_no_rfkill_wapf4 = {
111	.wapf = 4,
112	.no_rfkill = true,
113	};
114
115	static struct quirk_entry quirk_asus_ux303ub = {	106	static struct quirk_entry quirk_asus_ux303ub = {
116	.wmi_backlight_native = true,	107	.wmi_backlight_native = true,
117	};	108	};
@@ -194,7 +185,7 @@ static const struct dmi_system_id asus_quirks[] = { · 76 unmodified lines
194	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),	185	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
195	DMI_MATCH(DMI_PRODUCT_NAME, "X456UA"),	186	DMI_MATCH(DMI_PRODUCT_NAME, "X456UA"),
196	},	187	},
197	.driver_data = &quirk_no_rfkill_wapf4,	188	.driver_data = &quirk_asus_wapf4,
198	},	189	},
199	{	190	{
200	.callback = dmi_matched,	191	.callback = dmi_matched,
@@ -203,7 +194,7 @@ static const struct dmi_system_id asus_quirks[] = { · 2 unmodified lines
203	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),	194	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
204	DMI_MATCH(DMI_PRODUCT_NAME, "X456UF"),	195	DMI_MATCH(DMI_PRODUCT_NAME, "X456UF"),
205	},	196	},
206	.driver_data = &quirk_no_rfkill_wapf4,	197	.driver_data = &quirk_asus_wapf4,
207	},	198	},
208	{	199	{
209	.callback = dmi_matched,	200	.callback = dmi_matched,
@@ -367,42 +358,6 @@ static const struct dmi_system_id asus_quirks[] = { · 157 unmodified lines
367	},	358	},
368	.driver_data = &quirk_asus_x200ca,	359	.driver_data = &quirk_asus_x200ca,
369	},	360	},
370	{
371	.callback = dmi_matched,
372	.ident = "ASUSTeK COMPUTER INC. X555UB",
373	.matches = {
374	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
375	DMI_MATCH(DMI_PRODUCT_NAME, "X555UB"),
376	},
377	.driver_data = &quirk_no_rfkill,
378	},
379	{
380	.callback = dmi_matched,
381	.ident = "ASUSTeK COMPUTER INC. N552VW",
382	.matches = {
383	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
384	DMI_MATCH(DMI_PRODUCT_NAME, "N552VW"),
385	},
386	.driver_data = &quirk_no_rfkill,
387	},
388	{
389	.callback = dmi_matched,
390	.ident = "ASUSTeK COMPUTER INC. U303LB",
391	.matches = {
392	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
393	DMI_MATCH(DMI_PRODUCT_NAME, "U303LB"),
394	},
395	.driver_data = &quirk_no_rfkill,
396	},
397	{
398	.callback = dmi_matched,
399	.ident = "ASUSTeK COMPUTER INC. Z550MA",
400	.matches = {
401	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
402	DMI_MATCH(DMI_PRODUCT_NAME, "Z550MA"),
403	},
404	.driver_data = &quirk_no_rfkill,
405	},
406	{	361	{
407	.callback = dmi_matched,	362	.callback = dmi_matched,
408	.ident = "ASUSTeK COMPUTER INC. UX303UB",	363	.ident = "ASUSTeK COMPUTER INC. UX303UB",

drivers/platform/x86/asus-wmi.c+17−5

 #define USB_INTEL_XUSB2PR		0xD0
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
+static const char * const ashs_ids[] = { "ATK4001", "ATK4002", NULL };
 struct bios_args {
 	u32 arg0;
 	u32 arg1;
 	return 0;
 }
+static bool ashs_present(void)
+{
+	int i = 0;
+	while (ashs_ids[i]) {
+		if (acpi_dev_found(ashs_ids[i++]))
+			return true;
+	}
+	return false;
+}
 /*
  * WMI Driver
  */
 	if (err)
 		goto fail_leds;
-	if (!asus->driver->quirks->no_rfkill) {
+	asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_WLAN, &result);
+	if (result & (ASUS_WMI_DSTS_PRESENCE_BIT | ASUS_WMI_DSTS_USER_BIT))
+		asus->driver->wlan_ctrl_by_user = 1;
+	if (!(asus->driver->wlan_ctrl_by_user && ashs_present())) {
 		err = asus_wmi_rfkill_init(asus);
 		if (err)
 			goto fail_rfkill;
 	if (err)
 		goto fail_debugfs;
-	asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_WLAN, &result);
-	if (result & (ASUS_WMI_DSTS_PRESENCE_BIT | ASUS_WMI_DSTS_USER_BIT))
-		asus->driver->wlan_ctrl_by_user = 1;
 	return 0;
 fail_debugfs:

drivers/platform/x86/asus-wmi.h+0−1

@@ -39,7 +39,6 @@ struct key_entry; · 38 unmodified lines
39	struct asus_wmi;	39	struct asus_wmi;
40		40
41	struct quirk_entry {	41	struct quirk_entry {
42	bool no_rfkill;
43	bool hotplug_wireless;	42	bool hotplug_wireless;
44	bool scalar_panel_brightness;	43	bool scalar_panel_brightness;
45	bool store_backlight_power;	44	bool store_backlight_power;

drivers/platform/x86/fujitsu-laptop.c+222−229

 #define FUJITSU_LCD_N_LEVELS 8
-#define ACPI_FUJITSU_CLASS              "fujitsu"
+#define ACPI_FUJITSU_CLASS		"fujitsu"
-#define ACPI_FUJITSU_HID                "FUJ02B1"
+#define ACPI_FUJITSU_BL_HID		"FUJ02B1"
-#define ACPI_FUJITSU_DRIVER_NAME	"Fujitsu laptop FUJ02B1 ACPI brightness driver"
+#define ACPI_FUJITSU_BL_DRIVER_NAME	"Fujitsu laptop FUJ02B1 ACPI brightness driver"
-#define ACPI_FUJITSU_DEVICE_NAME        "Fujitsu FUJ02B1"
+#define ACPI_FUJITSU_BL_DEVICE_NAME	"Fujitsu FUJ02B1"
-#define ACPI_FUJITSU_HOTKEY_HID 	"FUJ02E3"
+#define ACPI_FUJITSU_LAPTOP_HID		"FUJ02E3"
-#define ACPI_FUJITSU_HOTKEY_DRIVER_NAME "Fujitsu laptop FUJ02E3 ACPI hotkeys driver"
+#define ACPI_FUJITSU_LAPTOP_DRIVER_NAME	"Fujitsu laptop FUJ02E3 ACPI hotkeys driver"
-#define ACPI_FUJITSU_HOTKEY_DEVICE_NAME "Fujitsu FUJ02E3"
+#define ACPI_FUJITSU_LAPTOP_DEVICE_NAME	"Fujitsu FUJ02E3"
 #define ACPI_FUJITSU_NOTIFY_CODE1     0x80
 /* FUNC interface - command values */
-#define FUNC_RFKILL	0x1000
+#define FUNC_FLAGS	0x1000
 #define FUNC_LEDS	0x1001
 #define FUNC_BUTTONS	0x1002
 #define FUNC_BACKLIGHT  0x1004
 /* FUNC interface - responses */
 #define UNSUPPORTED_CMD 0x80000000
+/* FUNC interface - status flags */
+#define FLAG_RFKILL	0x020
+#define FLAG_LID	0x100
+#define FLAG_DOCK	0x200
 #if IS_ENABLED(CONFIG_LEDS_CLASS)
 /* FUNC interface - LED control */
 #define FUNC_LED_OFF	0x1
 #endif
 /* Device controlling the backlight and associated keys */
-struct fujitsu_t {
+struct fujitsu_bl {
 	acpi_handle acpi_handle;
 	struct acpi_device *dev;
 	struct input_dev *input;
 	unsigned int brightness_level;
 };
-static struct fujitsu_t *fujitsu;
+static struct fujitsu_bl *fujitsu_bl;
 static int use_alt_lcd_levels = -1;
 static int disable_brightness_adjust = -1;
-/* Device used to access other hotkeys on the laptop */
+/* Device used to access hotkeys and other features on the laptop */
-struct fujitsu_hotkey_t {
+struct fujitsu_laptop {
 	acpi_handle acpi_handle;
 	struct acpi_device *dev;
 	struct input_dev *input;
 	struct platform_device *pf_device;
 	struct kfifo fifo;
 	spinlock_t fifo_lock;
-	int rfkill_supported;
+	int flags_supported;
-	int rfkill_state;
+	int flags_state;
 	int logolamp_registered;
 	int kblamps_registered;
 	int radio_led_registered;
 	int eco_led_registered;
 };
-static struct fujitsu_hotkey_t *fujitsu_hotkey;
+static struct fujitsu_laptop *fujitsu_laptop;
-static void acpi_fujitsu_hotkey_notify(struct acpi_device *device, u32 event);
 #if IS_ENABLED(CONFIG_LEDS_CLASS)
 static enum led_brightness logolamp_get(struct led_classdev *cdev);
 static u32 dbg_level = 0x03;
 #endif
-static void acpi_fujitsu_notify(struct acpi_device *device, u32 event);
 /* Fujitsu ACPI interface function */
 static int call_fext_func(int cmd, int arg0, int arg1, int arg2)
 	unsigned long long value;
 	acpi_handle handle = NULL;
-	status = acpi_get_handle(fujitsu_hotkey->acpi_handle, "FUNC", &handle);
+	status = acpi_get_handle(fujitsu_laptop->acpi_handle, "FUNC", &handle);
 	if (ACPI_FAILURE(status)) {
 		vdbg_printk(FUJLAPTOP_DBG_ERROR,
 				"FUNC interface is not present\n");
 				enum led_brightness brightness)
 {
 	if (brightness >= LED_FULL)
-		return call_fext_func(FUNC_RFKILL, 0x5, RADIO_LED_ON, RADIO_LED_ON);
+		return call_fext_func(FUNC_FLAGS, 0x5, RADIO_LED_ON, RADIO_LED_ON);
 	else
-		return call_fext_func(FUNC_RFKILL, 0x5, RADIO_LED_ON, 0x0);
+		return call_fext_func(FUNC_FLAGS, 0x5, RADIO_LED_ON, 0x0);
 }
 static int eco_led_set(struct led_classdev *cdev,
 {
 	enum led_brightness brightness = LED_OFF;
-	if (call_fext_func(FUNC_RFKILL, 0x4, 0x0, 0x0) & RADIO_LED_ON)
+	if (call_fext_func(FUNC_FLAGS, 0x4, 0x0, 0x0) & RADIO_LED_ON)
 		brightness = LED_FULL;
 	return brightness;
 	vdbg_printk(FUJLAPTOP_DBG_TRACE, "set lcd level via SBLL [%d]\n",
 		    level);
-	if (level < 0 || level >= fujitsu->max_brightness)
+	if (level < 0 || level >= fujitsu_bl->max_brightness)
 		return -EINVAL;
-	status = acpi_get_handle(fujitsu->acpi_handle, "SBLL", &handle);
+	status = acpi_get_handle(fujitsu_bl->acpi_handle, "SBLL", &handle);
 	if (ACPI_FAILURE(status)) {
 		vdbg_printk(FUJLAPTOP_DBG_ERROR, "SBLL not present\n");
 		return -ENODEV;
 	vdbg_printk(FUJLAPTOP_DBG_TRACE, "set lcd level via SBL2 [%d]\n",
 		    level);
-	if (level < 0 || level >= fujitsu->max_brightness)
+	if (level < 0 || level >= fujitsu_bl->max_brightness)
 		return -EINVAL;
-	status = acpi_get_handle(fujitsu->acpi_handle, "SBL2", &handle);
+	status = acpi_get_handle(fujitsu_bl->acpi_handle, "SBL2", &handle);
 	if (ACPI_FAILURE(status)) {
 		vdbg_printk(FUJLAPTOP_DBG_ERROR, "SBL2 not present\n");
 		return -ENODEV;
 	vdbg_printk(FUJLAPTOP_DBG_TRACE, "get lcd level via GBLL\n");
-	status =
+	status = acpi_evaluate_integer(fujitsu_bl->acpi_handle, "GBLL", NULL,
-	    acpi_evaluate_integer(fujitsu->acpi_handle, "GBLL", NULL, &state);
+				       &state);
 	if (ACPI_FAILURE(status))
 		return 0;
-	fujitsu->brightness_level = state & 0x0fffffff;
+	fujitsu_bl->brightness_level = state & 0x0fffffff;
 	if (state & 0x80000000)
-		fujitsu->brightness_changed = 1;
+		fujitsu_bl->brightness_changed = 1;
 	else
-		fujitsu->brightness_changed = 0;
+		fujitsu_bl->brightness_changed = 0;
-	return fujitsu->brightness_level;
+	return fujitsu_bl->brightness_level;
 }
 static int get_max_brightness(void)
 	vdbg_printk(FUJLAPTOP_DBG_TRACE, "get max lcd level via RBLL\n");
-	status =
+	status = acpi_evaluate_integer(fujitsu_bl->acpi_handle, "RBLL", NULL,
-	    acpi_evaluate_integer(fujitsu->acpi_handle, "RBLL", NULL, &state);
+				       &state);
 	if (ACPI_FAILURE(status))
 		return -1;
-	fujitsu->max_brightness = state;
+	fujitsu_bl->max_brightness = state;
-	return fujitsu->max_brightness;
+	return fujitsu_bl->max_brightness;
 }
 /* Backlight device stuff */
 	return ret;
 }
-static const struct backlight_ops fujitsubl_ops = {
+static const struct backlight_ops fujitsu_bl_ops = {
 	.get_brightness = bl_get_brightness,
 	.update_status = bl_update_status,
 };
 	int ret;
-	ret = fujitsu->brightness_changed;
+	ret = fujitsu_bl->brightness_changed;
 	if (ret < 0)
 		return ret;
 	int level, ret;
 	if (sscanf(buf, "%i", &level) != 1
-	    || (level < 0 || level >= fujitsu->max_brightness))
+	    || (level < 0 || level >= fujitsu_bl->max_brightness))
 		return -EINVAL;
 	if (use_alt_lcd_levels)
 show_lid_state(struct device *dev,
 			struct device_attribute *attr, char *buf)
 {
-	if (!(fujitsu_hotkey->rfkill_supported & 0x100))
+	if (!(fujitsu_laptop->flags_supported & FLAG_LID))
 		return sprintf(buf, "unknown\n");
-	if (fujitsu_hotkey->rfkill_state & 0x100)
+	if (fujitsu_laptop->flags_state & FLAG_LID)
 		return sprintf(buf, "open\n");
 	else
 		return sprintf(buf, "closed\n");
 show_dock_state(struct device *dev,
 			struct device_attribute *attr, char *buf)
 {
-	if (!(fujitsu_hotkey->rfkill_supported & 0x200))
+	if (!(fujitsu_laptop->flags_supported & FLAG_DOCK))
 		return sprintf(buf, "unknown\n");
-	if (fujitsu_hotkey->rfkill_state & 0x200)
+	if (fujitsu_laptop->flags_state & FLAG_DOCK)
 		return sprintf(buf, "docked\n");
 	else
 		return sprintf(buf, "undocked\n");
 show_radios_state(struct device *dev,
 			struct device_attribute *attr, char *buf)
 {
-	if (!(fujitsu_hotkey->rfkill_supported & 0x20))
+	if (!(fujitsu_laptop->flags_supported & FLAG_RFKILL))
 		return sprintf(buf, "unknown\n");
-	if (fujitsu_hotkey->rfkill_state & 0x20)
+	if (fujitsu_laptop->flags_state & FLAG_RFKILL)
 		return sprintf(buf, "on\n");
 	else
 		return sprintf(buf, "killed\n");
 static DEVICE_ATTR(dock, 0444, show_dock_state, ignore_store);
 static DEVICE_ATTR(radios, 0444, show_radios_state, ignore_store);
-static struct attribute *fujitsupf_attributes[] = {
+static struct attribute *fujitsu_pf_attributes[] = {
 	&dev_attr_brightness_changed.attr,
 	&dev_attr_max_brightness.attr,
 	&dev_attr_lcd_level.attr,
 	NULL
 };
-static struct attribute_group fujitsupf_attribute_group = {
+static struct attribute_group fujitsu_pf_attribute_group = {
-	.attrs = fujitsupf_attributes
+	.attrs = fujitsu_pf_attributes
 };
-static struct platform_driver fujitsupf_driver = {
+static struct platform_driver fujitsu_pf_driver = {
 	.driver = {
 		   .name = "fujitsu-laptop",
 		   }
 static void __init dmi_check_cb_common(const struct dmi_system_id *id)
 {
 	pr_info("Identified laptop model '%s'\n", id->ident);
-	if (use_alt_lcd_levels == -1) {
-		if (acpi_has_method(NULL,
-				"\\_SB.PCI0.LPCB.FJEX.SBL2"))
-			use_alt_lcd_levels = 1;
-		else
-			use_alt_lcd_levels = 0;
-		vdbg_printk(FUJLAPTOP_DBG_TRACE, "auto-detected usealt as "
-			"%i\n", use_alt_lcd_levels);
-	}
 }
 static int __init dmi_check_cb_s6410(const struct dmi_system_id *id)
 {
 	dmi_check_cb_common(id);
-	fujitsu->keycode1 = KEY_SCREENLOCK;	/* "Lock" */
+	fujitsu_bl->keycode1 = KEY_SCREENLOCK;	/* "Lock" */
-	fujitsu->keycode2 = KEY_HELP;	/* "Mobility Center" */
+	fujitsu_bl->keycode2 = KEY_HELP;	/* "Mobility Center" */
 	return 1;
 }
 static int __init dmi_check_cb_s6420(const struct dmi_system_id *id)
 {
 	dmi_check_cb_common(id);
-	fujitsu->keycode1 = KEY_SCREENLOCK;	/* "Lock" */
+	fujitsu_bl->keycode1 = KEY_SCREENLOCK;	/* "Lock" */
-	fujitsu->keycode2 = KEY_HELP;	/* "Mobility Center" */
+	fujitsu_bl->keycode2 = KEY_HELP;	/* "Mobility Center" */
 	return 1;
 }
 static int __init dmi_check_cb_p8010(const struct dmi_system_id *id)
 {
 	dmi_check_cb_common(id);
-	fujitsu->keycode1 = KEY_HELP;	/* "Support" */
+	fujitsu_bl->keycode1 = KEY_HELP;		/* "Support" */
-	fujitsu->keycode3 = KEY_SWITCHVIDEOMODE;	/* "Presentation" */
+	fujitsu_bl->keycode3 = KEY_SWITCHVIDEOMODE;	/* "Presentation" */
-	fujitsu->keycode4 = KEY_WWW;	/* "Internet" */
+	fujitsu_bl->keycode4 = KEY_WWW;			/* "Internet" */
 	return 1;
 }
 /* ACPI device for LCD brightness control */
-static int acpi_fujitsu_add(struct acpi_device *device)
+static int acpi_fujitsu_bl_add(struct acpi_device *device)
 {
 	int state = 0;
 	struct input_dev *input;
 	if (!device)
 		return -EINVAL;
-	fujitsu->acpi_handle = device->handle;
+	fujitsu_bl->acpi_handle = device->handle;
-	sprintf(acpi_device_name(device), "%s", ACPI_FUJITSU_DEVICE_NAME);
+	sprintf(acpi_device_name(device), "%s", ACPI_FUJITSU_BL_DEVICE_NAME);
 	sprintf(acpi_device_class(device), "%s", ACPI_FUJITSU_CLASS);
-	device->driver_data = fujitsu;
+	device->driver_data = fujitsu_bl;
-	fujitsu->input = input = input_allocate_device();
+	fujitsu_bl->input = input = input_allocate_device();
 	if (!input) {
 		error = -ENOMEM;
 		goto err_stop;
 	}
-	snprintf(fujitsu->phys, sizeof(fujitsu->phys),
+	snprintf(fujitsu_bl->phys, sizeof(fujitsu_bl->phys),
 		 "%s/video/input0", acpi_device_hid(device));
 	input->name = acpi_device_name(device);
-	input->phys = fujitsu->phys;
+	input->phys = fujitsu_bl->phys;
 	input->id.bustype = BUS_HOST;
 	input->id.product = 0x06;
 	input->dev.parent = &device->dev;
 	if (error)
 		goto err_free_input_dev;
-	error = acpi_bus_update_power(fujitsu->acpi_handle, &state);
+	error = acpi_bus_update_power(fujitsu_bl->acpi_handle, &state);
 	if (error) {
 		pr_err("Error reading power state\n");
 		goto err_unregister_input_dev;
 	       acpi_device_name(device), acpi_device_bid(device),
 	       !device->power.state ? "on" : "off");
-	fujitsu->dev = device;
+	fujitsu_bl->dev = device;
 	if (acpi_has_method(device->handle, METHOD_NAME__INI)) {
 		vdbg_printk(FUJLAPTOP_DBG_INFO, "Invoking _INI\n");
 			pr_err("_INI Method failed\n");
 	}
+	if (use_alt_lcd_levels == -1) {
+		if (acpi_has_method(NULL, "\\_SB.PCI0.LPCB.FJEX.SBL2"))
+			use_alt_lcd_levels = 1;
+		else
+			use_alt_lcd_levels = 0;
+		vdbg_printk(FUJLAPTOP_DBG_TRACE, "auto-detected usealt as %i\n",
+			    use_alt_lcd_levels);
+	}
 	/* do config (detect defaults) */
 	use_alt_lcd_levels = use_alt_lcd_levels == 1 ? 1 : 0;
 	disable_brightness_adjust = disable_brightness_adjust == 1 ? 1 : 0;
 		    use_alt_lcd_levels, disable_brightness_adjust);
 	if (get_max_brightness() <= 0)
-		fujitsu->max_brightness = FUJITSU_LCD_N_LEVELS;
+		fujitsu_bl->max_brightness = FUJITSU_LCD_N_LEVELS;
 	get_lcd_level();
 	return 0;
 	return error;
 }
-static int acpi_fujitsu_remove(struct acpi_device *device)
+static int acpi_fujitsu_bl_remove(struct acpi_device *device)
 {
-	struct fujitsu_t *fujitsu = acpi_driver_data(device);
+	struct fujitsu_bl *fujitsu_bl = acpi_driver_data(device);
-	struct input_dev *input = fujitsu->input;
+	struct input_dev *input = fujitsu_bl->input;
 	input_unregister_device(input);
-	fujitsu->acpi_handle = NULL;
+	fujitsu_bl->acpi_handle = NULL;
 	return 0;
 }
 /* Brightness notify */
-static void acpi_fujitsu_notify(struct acpi_device *device, u32 event)
+static void acpi_fujitsu_bl_notify(struct acpi_device *device, u32 event)
 {
 	struct input_dev *input;
 	int keycode;
 	int oldb, newb;
-	input = fujitsu->input;
+	input = fujitsu_bl->input;
 	switch (event) {
 	case ACPI_FUJITSU_NOTIFY_CODE1:
 		keycode = 0;
-		oldb = fujitsu->brightness_level;
+		oldb = fujitsu_bl->brightness_level;
 		get_lcd_level();
-		newb = fujitsu->brightness_level;
+		newb = fujitsu_bl->brightness_level;
 		vdbg_printk(FUJLAPTOP_DBG_TRACE,
 			    "brightness button event [%i -> %i (%i)]\n",
-			    oldb, newb, fujitsu->brightness_changed);
+			    oldb, newb, fujitsu_bl->brightness_changed);
 		if (oldb < newb) {
 			if (disable_brightness_adjust != 1) {
 /* ACPI device for hotkey handling */
-static int acpi_fujitsu_hotkey_add(struct acpi_device *device)
+static int acpi_fujitsu_laptop_add(struct acpi_device *device)
 {
 	int result = 0;
 	int state = 0;
 	if (!device)
 		return -EINVAL;
-	fujitsu_hotkey->acpi_handle = device->handle;
+	fujitsu_laptop->acpi_handle = device->handle;
 	sprintf(acpi_device_name(device), "%s",
-		ACPI_FUJITSU_HOTKEY_DEVICE_NAME);
+		ACPI_FUJITSU_LAPTOP_DEVICE_NAME);
 	sprintf(acpi_device_class(device), "%s", ACPI_FUJITSU_CLASS);
-	device->driver_data = fujitsu_hotkey;
+	device->driver_data = fujitsu_laptop;
 	/* kfifo */
-	spin_lock_init(&fujitsu_hotkey->fifo_lock);
+	spin_lock_init(&fujitsu_laptop->fifo_lock);
-	error = kfifo_alloc(&fujitsu_hotkey->fifo, RINGBUFFERSIZE * sizeof(int),
+	error = kfifo_alloc(&fujitsu_laptop->fifo, RINGBUFFERSIZE * sizeof(int),
 			GFP_KERNEL);
 	if (error) {
 		pr_err("kfifo_alloc failed\n");
 		goto err_stop;
 	}
-	fujitsu_hotkey->input = input = input_allocate_device();
+	fujitsu_laptop->input = input = input_allocate_device();
 	if (!input) {
 		error = -ENOMEM;
 		goto err_free_fifo;
 	}
-	snprintf(fujitsu_hotkey->phys, sizeof(fujitsu_hotkey->phys),
+	snprintf(fujitsu_laptop->phys, sizeof(fujitsu_laptop->phys),
 		 "%s/video/input0", acpi_device_hid(device));
 	input->name = acpi_device_name(device);
-	input->phys = fujitsu_hotkey->phys;
+	input->phys = fujitsu_laptop->phys;
 	input->id.bustype = BUS_HOST;
 	input->id.product = 0x06;
 	input->dev.parent = &device->dev;
 	set_bit(EV_KEY, input->evbit);
-	set_bit(fujitsu->keycode1, input->keybit);
+	set_bit(fujitsu_bl->keycode1, input->keybit);
-	set_bit(fujitsu->keycode2, input->keybit);
+	set_bit(fujitsu_bl->keycode2, input->keybit);
-	set_bit(fujitsu->keycode3, input->keybit);
+	set_bit(fujitsu_bl->keycode3, input->keybit);
-	set_bit(fujitsu->keycode4, input->keybit);
+	set_bit(fujitsu_bl->keycode4, input->keybit);
-	set_bit(fujitsu->keycode5, input->keybit);
+	set_bit(fujitsu_bl->keycode5, input->keybit);
 	set_bit(KEY_TOUCHPAD_TOGGLE, input->keybit);
 	set_bit(KEY_UNKNOWN, input->keybit);
 	if (error)
 		goto err_free_input_dev;
-	error = acpi_bus_update_power(fujitsu_hotkey->acpi_handle, &state);
+	error = acpi_bus_update_power(fujitsu_laptop->acpi_handle, &state);
 	if (error) {
 		pr_err("Error reading power state\n");
 		goto err_unregister_input_dev;
 		acpi_device_name(device), acpi_device_bid(device),
 		!device->power.state ? "on" : "off");
-	fujitsu_hotkey->dev = device;
+	fujitsu_laptop->dev = device;
 	if (acpi_has_method(device->handle, METHOD_NAME__INI)) {
 		vdbg_printk(FUJLAPTOP_DBG_INFO, "Invoking _INI\n");
 		; /* No action, result is discarded */
 	vdbg_printk(FUJLAPTOP_DBG_INFO, "Discarded %i ringbuffer entries\n", i);
-	fujitsu_hotkey->rfkill_supported =
+	fujitsu_laptop->flags_supported =
-		call_fext_func(FUNC_RFKILL, 0x0, 0x0, 0x0);
+		call_fext_func(FUNC_FLAGS, 0x0, 0x0, 0x0);
 	/* Make sure our bitmask of supported functions is cleared if the
 	   RFKILL function block is not implemented, like on the S7020. */
-	if (fujitsu_hotkey->rfkill_supported == UNSUPPORTED_CMD)
+	if (fujitsu_laptop->flags_supported == UNSUPPORTED_CMD)
-		fujitsu_hotkey->rfkill_supported = 0;
+		fujitsu_laptop->flags_supported = 0;
-	if (fujitsu_hotkey->rfkill_supported)
+	if (fujitsu_laptop->flags_supported)
-		fujitsu_hotkey->rfkill_state =
+		fujitsu_laptop->flags_state =
-			call_fext_func(FUNC_RFKILL, 0x4, 0x0, 0x0);
+			call_fext_func(FUNC_FLAGS, 0x4, 0x0, 0x0);
 	/* Suspect this is a keymap of the application panel, print it */
 	pr_info("BTNI: [0x%x]\n", call_fext_func(FUNC_BUTTONS, 0x0, 0x0, 0x0));
 #if IS_ENABLED(CONFIG_LEDS_CLASS)
 	if (call_fext_func(FUNC_LEDS, 0x0, 0x0, 0x0) & LOGOLAMP_POWERON) {
-		result = led_classdev_register(&fujitsu->pf_device->dev,
+		result = led_classdev_register(&fujitsu_bl->pf_device->dev,
 						&logolamp_led);
 		if (result == 0) {
-			fujitsu_hotkey->logolamp_registered = 1;
+			fujitsu_laptop->logolamp_registered = 1;
 		} else {
 			pr_err("Could not register LED handler for logo lamp, error %i\n",
 			       result);
 	if ((call_fext_func(FUNC_LEDS, 0x0, 0x0, 0x0) & KEYBOARD_LAMPS) &&
 	   (call_fext_func(FUNC_BUTTONS, 0x0, 0x0, 0x0) == 0x0)) {
-		result = led_classdev_register(&fujitsu->pf_device->dev,
+		result = led_classdev_register(&fujitsu_bl->pf_device->dev,
 						&kblamps_led);
 		if (result == 0) {
-			fujitsu_hotkey->kblamps_registered = 1;
+			fujitsu_laptop->kblamps_registered = 1;
 		} else {
 			pr_err("Could not register LED handler for keyboard lamps, error %i\n",
 			       result);
 	 * that an RF LED is present.
 	 */
 	if (call_fext_func(FUNC_BUTTONS, 0x0, 0x0, 0x0) & BIT(24)) {
-		result = led_classdev_register(&fujitsu->pf_device->dev,
+		result = led_classdev_register(&fujitsu_bl->pf_device->dev,
 						&radio_led);
 		if (result == 0) {
-			fujitsu_hotkey->radio_led_registered = 1;
+			fujitsu_laptop->radio_led_registered = 1;
 		} else {
 			pr_err("Could not register LED handler for radio LED, error %i\n",
 			       result);
 	*/
 	if ((call_fext_func(FUNC_LEDS, 0x0, 0x0, 0x0) & BIT(14)) &&
 	   (call_fext_func(FUNC_LEDS, 0x2, ECO_LED, 0x0) != UNSUPPORTED_CMD)) {
-		result = led_classdev_register(&fujitsu->pf_device->dev,
+		result = led_classdev_register(&fujitsu_bl->pf_device->dev,
 						&eco_led);
 		if (result == 0) {
-			fujitsu_hotkey->eco_led_registered = 1;
+			fujitsu_laptop->eco_led_registered = 1;
 		} else {
 			pr_err("Could not register LED handler for eco LED, error %i\n",
 			       result);
 err_free_input_dev:
 	input_free_device(input);
 err_free_fifo:
-	kfifo_free(&fujitsu_hotkey->fifo);
+	kfifo_free(&fujitsu_laptop->fifo);
 err_stop:
 	return error;
 }
-static int acpi_fujitsu_hotkey_remove(struct acpi_device *device)
+static int acpi_fujitsu_laptop_remove(struct acpi_device *device)
 {
-	struct fujitsu_hotkey_t *fujitsu_hotkey = acpi_driver_data(device);
+	struct fujitsu_laptop *fujitsu_laptop = acpi_driver_data(device);
-	struct input_dev *input = fujitsu_hotkey->input;
+	struct input_dev *input = fujitsu_laptop->input;
 #if IS_ENABLED(CONFIG_LEDS_CLASS)
-	if (fujitsu_hotkey->logolamp_registered)
+	if (fujitsu_laptop->logolamp_registered)
 		led_classdev_unregister(&logolamp_led);
-	if (fujitsu_hotkey->kblamps_registered)
+	if (fujitsu_laptop->kblamps_registered)
 		led_classdev_unregister(&kblamps_led);
-	if (fujitsu_hotkey->radio_led_registered)
+	if (fujitsu_laptop->radio_led_registered)
 		led_classdev_unregister(&radio_led);
-	if (fujitsu_hotkey->eco_led_registered)
+	if (fujitsu_laptop->eco_led_registered)
 		led_classdev_unregister(&eco_led);
 #endif
 	input_unregister_device(input);
-	kfifo_free(&fujitsu_hotkey->fifo);
+	kfifo_free(&fujitsu_laptop->fifo);
-	fujitsu_hotkey->acpi_handle = NULL;
+	fujitsu_laptop->acpi_handle = NULL;
 	return 0;
 }
-static void acpi_fujitsu_hotkey_press(int keycode)
+static void acpi_fujitsu_laptop_press(int keycode)
 {
-	struct input_dev *input = fujitsu_hotkey->input;
+	struct input_dev *input = fujitsu_laptop->input;
 	int status;
-	status = kfifo_in_locked(&fujitsu_hotkey->fifo,
+	status = kfifo_in_locked(&fujitsu_laptop->fifo,
 				 (unsigned char *)&keycode, sizeof(keycode),
-				 &fujitsu_hotkey->fifo_lock);
+				 &fujitsu_laptop->fifo_lock);
 	if (status != sizeof(keycode)) {
 		vdbg_printk(FUJLAPTOP_DBG_WARN,
 			    "Could not push keycode [0x%x]\n", keycode);
 		    "Push keycode into ringbuffer [%d]\n", keycode);
 }
-static void acpi_fujitsu_hotkey_release(void)
+static void acpi_fujitsu_laptop_release(void)
 {
-	struct input_dev *input = fujitsu_hotkey->input;
+	struct input_dev *input = fujitsu_laptop->input;
 	int keycode, status;
 	while (true) {
-		status = kfifo_out_locked(&fujitsu_hotkey->fifo,
+		status = kfifo_out_locked(&fujitsu_laptop->fifo,
 					  (unsigned char *)&keycode,
 					  sizeof(keycode),
-					  &fujitsu_hotkey->fifo_lock);
+					  &fujitsu_laptop->fifo_lock);
 		if (status != sizeof(keycode))
 			return;
 		input_report_key(input, keycode, 0);
 	}
 }
-static void acpi_fujitsu_hotkey_notify(struct acpi_device *device, u32 event)
+static void acpi_fujitsu_laptop_notify(struct acpi_device *device, u32 event)
 {
 	struct input_dev *input;
 	int keycode;
 	unsigned int irb = 1;
 	int i;
-	input = fujitsu_hotkey->input;
+	input = fujitsu_laptop->input;
 	if (event != ACPI_FUJITSU_NOTIFY_CODE1) {
 		keycode = KEY_UNKNOWN;
 		return;
 	}
-	if (fujitsu_hotkey->rfkill_supported)
+	if (fujitsu_laptop->flags_supported)
-		fujitsu_hotkey->rfkill_state =
+		fujitsu_laptop->flags_state =
-			call_fext_func(FUNC_RFKILL, 0x4, 0x0, 0x0);
+			call_fext_func(FUNC_FLAGS, 0x4, 0x0, 0x0);
 	i = 0;
 	while ((irb =
 			&& (i++) < MAX_HOTKEY_RINGBUFFER_SIZE) {
 		switch (irb & 0x4ff) {
 		case KEY1_CODE:
-			keycode = fujitsu->keycode1;
+			keycode = fujitsu_bl->keycode1;
 			break;
 		case KEY2_CODE:
-			keycode = fujitsu->keycode2;
+			keycode = fujitsu_bl->keycode2;
 			break;
 		case KEY3_CODE:
-			keycode = fujitsu->keycode3;
+			keycode = fujitsu_bl->keycode3;
 			break;
 		case KEY4_CODE:
-			keycode = fujitsu->keycode4;
+			keycode = fujitsu_bl->keycode4;
 			break;
 		case KEY5_CODE:
-			keycode = fujitsu->keycode5;
+			keycode = fujitsu_bl->keycode5;
 			break;
 		case 0:
 			keycode = 0;
 		}
 		if (keycode > 0)
-			acpi_fujitsu_hotkey_press(keycode);
+			acpi_fujitsu_laptop_press(keycode);
 		else if (keycode == 0)
-			acpi_fujitsu_hotkey_release();
+			acpi_fujitsu_laptop_release();
 	}
 	/* On some models (first seen on the Skylake-based Lifebook
 	 * E736/E746/E756), the touchpad toggle hotkey (Fn+F4) is
-	 * handled in software; its state is queried using FUNC_RFKILL
+	 * handled in software; its state is queried using FUNC_FLAGS
 	 */
-	if ((fujitsu_hotkey->rfkill_supported & BIT(26)) &&
+	if ((fujitsu_laptop->flags_supported & BIT(26)) &&
-	    (call_fext_func(FUNC_RFKILL, 0x1, 0x0, 0x0) & BIT(26))) {
+	    (call_fext_func(FUNC_FLAGS, 0x1, 0x0, 0x0) & BIT(26))) {
 		keycode = KEY_TOUCHPAD_TOGGLE;
 		input_report_key(input, keycode, 1);
 		input_sync(input);
 /* Initialization */
-static const struct acpi_device_id fujitsu_device_ids[] = {
+static const struct acpi_device_id fujitsu_bl_device_ids[] = {
-	{ACPI_FUJITSU_HID, 0},
+	{ACPI_FUJITSU_BL_HID, 0},
 	{"", 0},
 };
-static struct acpi_driver acpi_fujitsu_driver = {
+static struct acpi_driver acpi_fujitsu_bl_driver = {
-	.name = ACPI_FUJITSU_DRIVER_NAME,
+	.name = ACPI_FUJITSU_BL_DRIVER_NAME,
 	.class = ACPI_FUJITSU_CLASS,
-	.ids = fujitsu_device_ids,
+	.ids = fujitsu_bl_device_ids,
 	.ops = {
-		.add = acpi_fujitsu_add,
+		.add = acpi_fujitsu_bl_add,
-		.remove = acpi_fujitsu_remove,
+		.remove = acpi_fujitsu_bl_remove,
-		.notify = acpi_fujitsu_notify,
+		.notify = acpi_fujitsu_bl_notify,
 		},
 };
-static const struct acpi_device_id fujitsu_hotkey_device_ids[] = {
+static const struct acpi_device_id fujitsu_laptop_device_ids[] = {
-	{ACPI_FUJITSU_HOTKEY_HID, 0},
+	{ACPI_FUJITSU_LAPTOP_HID, 0},
 	{"", 0},
 };
-static struct acpi_driver acpi_fujitsu_hotkey_driver = {
+static struct acpi_driver acpi_fujitsu_laptop_driver = {
-	.name = ACPI_FUJITSU_HOTKEY_DRIVER_NAME,
+	.name = ACPI_FUJITSU_LAPTOP_DRIVER_NAME,
 	.class = ACPI_FUJITSU_CLASS,
-	.ids = fujitsu_hotkey_device_ids,
+	.ids = fujitsu_laptop_device_ids,
 	.ops = {
-		.add = acpi_fujitsu_hotkey_add,
+		.add = acpi_fujitsu_laptop_add,
-		.remove = acpi_fujitsu_hotkey_remove,
+		.remove = acpi_fujitsu_laptop_remove,
-		.notify = acpi_fujitsu_hotkey_notify,
+		.notify = acpi_fujitsu_laptop_notify,
 		},
 };
 static const struct acpi_device_id fujitsu_ids[] __used = {
-	{ACPI_FUJITSU_HID, 0},
+	{ACPI_FUJITSU_BL_HID, 0},
-	{ACPI_FUJITSU_HOTKEY_HID, 0},
+	{ACPI_FUJITSU_LAPTOP_HID, 0},
 	{"", 0}
 };
 MODULE_DEVICE_TABLE(acpi, fujitsu_ids);
 static int __init fujitsu_init(void)
 {
-	int ret, result, max_brightness;
+	int ret, max_brightness;
 	if (acpi_disabled)
 		return -ENODEV;
-	fujitsu = kzalloc(sizeof(struct fujitsu_t), GFP_KERNEL);
+	fujitsu_bl = kzalloc(sizeof(struct fujitsu_bl), GFP_KERNEL);
-	if (!fujitsu)
+	if (!fujitsu_bl)
 		return -ENOMEM;
-	fujitsu->keycode1 = KEY_PROG1;
+	fujitsu_bl->keycode1 = KEY_PROG1;
-	fujitsu->keycode2 = KEY_PROG2;
+	fujitsu_bl->keycode2 = KEY_PROG2;
-	fujitsu->keycode3 = KEY_PROG3;
+	fujitsu_bl->keycode3 = KEY_PROG3;
-	fujitsu->keycode4 = KEY_PROG4;
+	fujitsu_bl->keycode4 = KEY_PROG4;
-	fujitsu->keycode5 = KEY_RFKILL;
+	fujitsu_bl->keycode5 = KEY_RFKILL;
 	dmi_check_system(fujitsu_dmi_table);
-	result = acpi_bus_register_driver(&acpi_fujitsu_driver);
+	ret = acpi_bus_register_driver(&acpi_fujitsu_bl_driver);
-	if (result < 0) {
+	if (ret)
-		ret = -ENODEV;
 		goto fail_acpi;
-	}
 	/* Register platform stuff */
-	fujitsu->pf_device = platform_device_alloc("fujitsu-laptop", -1);
+	fujitsu_bl->pf_device = platform_device_alloc("fujitsu-laptop", -1);
-	if (!fujitsu->pf_device) {
+	if (!fujitsu_bl->pf_device) {
 		ret = -ENOMEM;
 		goto fail_platform_driver;
 	}
-	ret = platform_device_add(fujitsu->pf_device);
+	ret = platform_device_add(fujitsu_bl->pf_device);
 	if (ret)
 		goto fail_platform_device1;
 	ret =
-	    sysfs_create_group(&fujitsu->pf_device->dev.kobj,
+	    sysfs_create_group(&fujitsu_bl->pf_device->dev.kobj,
-			       &fujitsupf_attribute_group);
+			       &fujitsu_pf_attribute_group);
 	if (ret)
 		goto fail_platform_device2;
 		struct backlight_properties props;
 		memset(&props, 0, sizeof(struct backlight_properties));
-		max_brightness = fujitsu->max_brightness;
+		max_brightness = fujitsu_bl->max_brightness;
 		props.type = BACKLIGHT_PLATFORM;
 		props.max_brightness = max_brightness - 1;
-		fujitsu->bl_device = backlight_device_register("fujitsu-laptop",
+		fujitsu_bl->bl_device = backlight_device_register("fujitsu-laptop",
-							       NULL, NULL,
+								  NULL, NULL,
-							       &fujitsubl_ops,
+								  &fujitsu_bl_ops,
-							       &props);
+								  &props);
-		if (IS_ERR(fujitsu->bl_device)) {
+		if (IS_ERR(fujitsu_bl->bl_device)) {
-			ret = PTR_ERR(fujitsu->bl_device);
+			ret = PTR_ERR(fujitsu_bl->bl_device);
-			fujitsu->bl_device = NULL;
+			fujitsu_bl->bl_device = NULL;
 			goto fail_sysfs_group;
 		}
-		fujitsu->bl_device->props.brightness = fujitsu->brightness_level;
+		fujitsu_bl->bl_device->props.brightness = fujitsu_bl->brightness_level;
 	}
-	ret = platform_driver_register(&fujitsupf_driver);
+	ret = platform_driver_register(&fujitsu_pf_driver);
 	if (ret)
 		goto fail_backlight;
-	/* Register hotkey driver */
+	/* Register laptop driver */
-	fujitsu_hotkey = kzalloc(sizeof(struct fujitsu_hotkey_t), GFP_KERNEL);
+	fujitsu_laptop = kzalloc(sizeof(struct fujitsu_laptop), GFP_KERNEL);
-	if (!fujitsu_hotkey) {
+	if (!fujitsu_laptop) {
 		ret = -ENOMEM;
-		goto fail_hotkey;
+		goto fail_laptop;
 	}
-	result = acpi_bus_register_driver(&acpi_fujitsu_hotkey_driver);
+	ret = acpi_bus_register_driver(&acpi_fujitsu_laptop_driver);
-	if (result < 0) {
+	if (ret)
-		ret = -ENODEV;
+		goto fail_laptop1;
-		goto fail_hotkey1;
-	}
 	/* Sync backlight power status (needs FUJ02E3 device, hence deferred) */
 	if (acpi_video_get_backlight_type() == acpi_backlight_vendor) {
 		if (call_fext_func(FUNC_BACKLIGHT, 0x2, 0x4, 0x0) == 3)
-			fujitsu->bl_device->props.power = FB_BLANK_POWERDOWN;
+			fujitsu_bl->bl_device->props.power = FB_BLANK_POWERDOWN;
 		else
-			fujitsu->bl_device->props.power = FB_BLANK_UNBLANK;
+			fujitsu_bl->bl_device->props.power = FB_BLANK_UNBLANK;
 	}
 	pr_info("driver " FUJITSU_DRIVER_VERSION " successfully loaded\n");
 	return 0;
-fail_hotkey1:
+fail_laptop1:
-	kfree(fujitsu_hotkey);
+	kfree(fujitsu_laptop);
-fail_hotkey:
+fail_laptop:
-	platform_driver_unregister(&fujitsupf_driver);
+	platform_driver_unregister(&fujitsu_pf_driver);
 fail_backlight:
-	backlight_device_unregister(fujitsu->bl_device);
+	backlight_device_unregister(fujitsu_bl->bl_device);
 fail_sysfs_group:
-	sysfs_remove_group(&fujitsu->pf_device->dev.kobj,
+	sysfs_remove_group(&fujitsu_bl->pf_device->dev.kobj,
-			   &fujitsupf_attribute_group);
+			   &fujitsu_pf_attribute_group);
 fail_platform_device2:
-	platform_device_del(fujitsu->pf_device);
+	platform_device_del(fujitsu_bl->pf_device);
 fail_platform_device1:
-	platform_device_put(fujitsu->pf_device);
+	platform_device_put(fujitsu_bl->pf_device);
 fail_platform_driver:
-	acpi_bus_unregister_driver(&acpi_fujitsu_driver);
+	acpi_bus_unregister_driver(&acpi_fujitsu_bl_driver);
 fail_acpi:
-	kfree(fujitsu);
+	kfree(fujitsu_bl);
 	return ret;
 }
 static void __exit fujitsu_cleanup(void)
 {
-	acpi_bus_unregister_driver(&acpi_fujitsu_hotkey_driver);
+	acpi_bus_unregister_driver(&acpi_fujitsu_laptop_driver);
-	kfree(fujitsu_hotkey);
+	kfree(fujitsu_laptop);
-	platform_driver_unregister(&fujitsupf_driver);
+	platform_driver_unregister(&fujitsu_pf_driver);
-	backlight_device_unregister(fujitsu->bl_device);
+	backlight_device_unregister(fujitsu_bl->bl_device);
-	sysfs_remove_group(&fujitsu->pf_device->dev.kobj,
+	sysfs_remove_group(&fujitsu_bl->pf_device->dev.kobj,
-			   &fujitsupf_attribute_group);
+			   &fujitsu_pf_attribute_group);
-	platform_device_unregister(fujitsu->pf_device);
+	platform_device_unregister(fujitsu_bl->pf_device);
-	acpi_bus_unregister_driver(&acpi_fujitsu_driver);
+	acpi_bus_unregister_driver(&acpi_fujitsu_bl_driver);
-	kfree(fujitsu);
+	kfree(fujitsu_bl);
 	pr_info("driver unloaded\n");
 }
 MODULE_DESCRIPTION("Fujitsu laptop extras support");
 MODULE_VERSION(FUJITSU_DRIVER_VERSION);
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("dmi:*:svnFUJITSUSIEMENS:*:pvr:rvnFUJITSU:rnFJNB1D3:*:cvrS6410:*");
-MODULE_ALIAS("dmi:*:svnFUJITSUSIEMENS:*:pvr:rvnFUJITSU:rnFJNB1E6:*:cvrS6420:*");
-MODULE_ALIAS("dmi:*:svnFUJITSU:*:pvr:rvnFUJITSU:rnFJNB19C:*:cvrS7020:*");

drivers/remoteproc/Kconfig+3−3

@@ -76,7 +76,7 @@ config QCOM_ADSP_PIL · 75 unmodified lines
76	depends on OF && ARCH_QCOM	76	depends on OF && ARCH_QCOM
77	depends on REMOTEPROC	77	depends on REMOTEPROC
78	depends on QCOM_SMEM	78	depends on QCOM_SMEM
79	depends on QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n)	79	depends on RPMSG_QCOM_SMD \|\| QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n && RPMSG_QCOM_SMD=n)
80	select MFD_SYSCON	80	select MFD_SYSCON
81	select QCOM_MDT_LOADER	81	select QCOM_MDT_LOADER
82	select QCOM_RPROC_COMMON	82	select QCOM_RPROC_COMMON
@@ -93,7 +93,7 @@ config QCOM_Q6V5_PIL · 10 unmodified lines
93	depends on OF && ARCH_QCOM	93	depends on OF && ARCH_QCOM
94	depends on QCOM_SMEM	94	depends on QCOM_SMEM
95	depends on REMOTEPROC	95	depends on REMOTEPROC
96	depends on QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n)	96	depends on RPMSG_QCOM_SMD \|\| QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n && RPMSG_QCOM_SMD=n)
97	select MFD_SYSCON	97	select MFD_SYSCON
98	select QCOM_RPROC_COMMON	98	select QCOM_RPROC_COMMON
99	select QCOM_SCM	99	select QCOM_SCM
@@ -104,7 +104,7 @@ config QCOM_Q6V5_PIL · 4 unmodified lines
104	config QCOM_WCNSS_PIL	104	config QCOM_WCNSS_PIL
105	tristate "Qualcomm WCNSS Peripheral Image Loader"	105	tristate "Qualcomm WCNSS Peripheral Image Loader"
106	depends on OF && ARCH_QCOM	106	depends on OF && ARCH_QCOM
107	depends on QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n)	107	depends on RPMSG_QCOM_SMD \|\| QCOM_SMD \|\| (COMPILE_TEST && QCOM_SMD=n && RPMSG_QCOM_SMD=n)
108	depends on QCOM_SMEM	108	depends on QCOM_SMEM
109	depends on REMOTEPROC	109	depends on REMOTEPROC
110	select QCOM_MDT_LOADER	110	select QCOM_MDT_LOADER

drivers/scsi/Kconfig+2−3

 	tristate "Emulex LightPulse Fibre Channel Support"
 	depends on PCI && SCSI
 	depends on SCSI_FC_ATTRS
-	depends on NVME_FC && NVME_TARGET_FC
 	select CRC_T10DIF
-	help
+	---help---
           This lpfc driver supports the Emulex LightPulse
           Family of Fibre Channel PCI host adapters.
 config SCSI_LPFC_DEBUG_FS
 	bool "Emulex LightPulse Fibre Channel debugfs Support"
 	depends on SCSI_LPFC && DEBUG_FS
-	help
+	---help---
 	  This makes debugging information from the lpfc driver
 	  available via the debugfs filesystem.

drivers/scsi/aacraid/src.c+1−1

@@ -468,7 +468,7 @@ err_out: · 467 unmodified lines
468	return -1;	468	return -1;
469		469
470	err_blink:	470	err_blink:
471	return (status > 16) & 0xFF;	471	return (status >> 16) & 0xFF;
472	}	472	}
473		473
474	static inline u32 aac_get_vector(struct aac_dev *dev)	474	static inline u32 aac_get_vector(struct aac_dev *dev)

drivers/scsi/hpsa.c+32−21

 	/* fill_cmd can't fail here, no data buffer to map. */
 	(void) fill_cmd(c, reset_type, h, NULL, 0, 0,
 			scsi3addr, TYPE_MSG);
-	rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
+	rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
 	if (rc) {
 		dev_warn(&h->pdev->dev, "Failed to send reset command\n");
 		goto out;
  *  # (integer code indicating one of several NOT READY states
  *     describing why a volume is to be kept offline)
  */
-static int hpsa_volume_offline(struct ctlr_info *h,
+static unsigned char hpsa_volume_offline(struct ctlr_info *h,
 					unsigned char scsi3addr[])
 {
 	struct CommandList *c;
 					DEFAULT_TIMEOUT);
 	if (rc) {
 		cmd_free(h, c);
-		return 0;
+		return HPSA_VPD_LV_STATUS_UNSUPPORTED;
 	}
 	sense = c->err_info->SenseInfo;
 	if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
 	cmd_status = c->err_info->CommandStatus;
 	scsi_status = c->err_info->ScsiStatus;
 	cmd_free(h, c);
-	/* Is the volume 'not ready'? */
-	if (cmd_status != CMD_TARGET_STATUS ||
-		scsi_status != SAM_STAT_CHECK_CONDITION ||
-		sense_key != NOT_READY ||
-		asc != ASC_LUN_NOT_READY)  {
-		return 0;
-	}
 	/* Determine the reason for not ready state */
 	ldstat = hpsa_get_volume_status(h, scsi3addr);
 	/* Keep volume offline in certain cases: */
 	switch (ldstat) {
+	case HPSA_LV_FAILED:
 	case HPSA_LV_UNDERGOING_ERASE:
 	case HPSA_LV_NOT_AVAILABLE:
 	case HPSA_LV_UNDERGOING_RPI:
 	default:
 		break;
 	}
-	return 0;
+	return HPSA_LV_OK;
 }
 /*
 	/* Do an inquiry to the device to see what it is. */
 	if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
 		(unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
-		/* Inquiry failed (msg printed already) */
 		dev_err(&h->pdev->dev,
-			"hpsa_update_device_info: inquiry failed\n");
+			"%s: inquiry failed, device will be skipped.\n",
-		rc = -EIO;
+			__func__);
+		rc = HPSA_INQUIRY_FAILED;
 		goto bail_out;
 	}
 	if ((this_device->devtype == TYPE_DISK ||
 		this_device->devtype == TYPE_ZBC) &&
 		is_logical_dev_addr_mode(scsi3addr)) {
-		int volume_offline;
+		unsigned char volume_offline;
 		hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
 		if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
 			hpsa_get_ioaccel_status(h, scsi3addr, this_device);
 		volume_offline = hpsa_volume_offline(h, scsi3addr);
-		if (volume_offline < 0 || volume_offline > 0xff)
+		if (volume_offline == HPSA_LV_FAILED) {
-			volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
+			rc = HPSA_LV_FAILED;
-		this_device->volume_offline = volume_offline & 0xff;
+			dev_err(&h->pdev->dev,
+				"%s: LV failed, device will be skipped.\n",
+				__func__);
+			goto bail_out;
+		}
 	} else {
 		this_device->raid_level = RAID_UNKNOWN;
 		this_device->offload_config = 0;
 			goto out;
 		}
 		if (rc) {
-			dev_warn(&h->pdev->dev,
+			h->drv_req_rescan = 1;
-				"Inquiry failed, skipping device.\n");
 			continue;
 		}
 	spin_lock_irqsave(&h->scan_lock, flags);
 	h->scan_finished = 1;
-	wake_up_all(&h->scan_wait_queue);
+	wake_up(&h->scan_wait_queue);
 	spin_unlock_irqrestore(&h->scan_lock, flags);
 }
 	if (unlikely(lockup_detected(h)))
 		return hpsa_scan_complete(h);
+	/*
+	 * If a scan is already waiting to run, no need to add another
+	 */
+	spin_lock_irqsave(&h->scan_lock, flags);
+	if (h->scan_waiting) {
+		spin_unlock_irqrestore(&h->scan_lock, flags);
+		return;
+	}
+	spin_unlock_irqrestore(&h->scan_lock, flags);
 	/* wait until any scan already in progress is finished. */
 	while (1) {
 		spin_lock_irqsave(&h->scan_lock, flags);
 		if (h->scan_finished)
 			break;
+		h->scan_waiting = 1;
 		spin_unlock_irqrestore(&h->scan_lock, flags);
 		wait_event(h->scan_wait_queue, h->scan_finished);
 		/* Note: We don't need to worry about a race between this
 		 */
 	}
 	h->scan_finished = 0; /* mark scan as in progress */
+	h->scan_waiting = 0;
 	spin_unlock_irqrestore(&h->scan_lock, flags);
 	if (unlikely(lockup_detected(h)))
 	init_waitqueue_head(&h->event_sync_wait_queue);
 	mutex_init(&h->reset_mutex);
 	h->scan_finished = 1; /* no scan currently in progress */
+	h->scan_waiting = 0;
 	pci_set_drvdata(pdev, h);
 	h->ndevices = 0;

drivers/scsi/hpsa.h+1−0

@@ -201,6 +201,7 @@ struct ctlr_info { · 200 unmodified lines
201	dma_addr_t errinfo_pool_dhandle;	201	dma_addr_t errinfo_pool_dhandle;
202	unsigned long *cmd_pool_bits;	202	unsigned long *cmd_pool_bits;
203	int scan_finished;	203	int scan_finished;
		204	u8 scan_waiting : 1;
204	spinlock_t scan_lock;	205	spinlock_t scan_lock;
205	wait_queue_head_t scan_wait_queue;	206	wait_queue_head_t scan_wait_queue;
206		207

drivers/scsi/hpsa_cmd.h+2−0

 #define CFGTBL_BusType_Fibre2G  0x00000200l
 /* VPD Inquiry types */
+#define HPSA_INQUIRY_FAILED		0x02
 #define HPSA_VPD_SUPPORTED_PAGES        0x00
 #define HPSA_VPD_LV_DEVICE_ID           0x83
 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
 /* Logical volume states */
 #define HPSA_VPD_LV_STATUS_UNSUPPORTED			0xff
 #define HPSA_LV_OK                                      0x0
+#define HPSA_LV_FAILED					0x01
 #define HPSA_LV_NOT_AVAILABLE				0x0b
 #define HPSA_LV_UNDERGOING_ERASE			0x0F
 #define HPSA_LV_UNDERGOING_RPI				0x12

drivers/scsi/libiscsi.c+25−1

 	WARN_ON_ONCE(task->state == ISCSI_TASK_FREE);
 	task->state = state;
-	if (!list_empty(&task->running))
+	spin_lock_bh(&conn->taskqueuelock);
+	if (!list_empty(&task->running)) {
+		pr_debug_once("%s while task on list", __func__);
 		list_del_init(&task->running);
+	}
+	spin_unlock_bh(&conn->taskqueuelock);
 	if (conn->task == task)
 		conn->task = NULL;
 		if (session->tt->xmit_task(task))
 			goto free_task;
 	} else {
+		spin_lock_bh(&conn->taskqueuelock);
 		list_add_tail(&task->running, &conn->mgmtqueue);
+		spin_unlock_bh(&conn->taskqueuelock);
 		iscsi_conn_queue_work(conn);
 	}
 	 * this may be on the requeue list already if the xmit_task callout
 	 * is handling the r2ts while we are adding new ones
 	 */
+	spin_lock_bh(&conn->taskqueuelock);
 	if (list_empty(&task->running))
 		list_add_tail(&task->running, &conn->requeue);
+	spin_unlock_bh(&conn->taskqueuelock);
 	iscsi_conn_queue_work(conn);
 }
 EXPORT_SYMBOL_GPL(iscsi_requeue_task);
 	 * only have one nop-out as a ping from us and targets should not
 	 * overflow us with nop-ins
 	 */
+	spin_lock_bh(&conn->taskqueuelock);
 check_mgmt:
 	while (!list_empty(&conn->mgmtqueue)) {
 		conn->task = list_entry(conn->mgmtqueue.next,
 					 struct iscsi_task, running);
 		list_del_init(&conn->task->running);
+		spin_unlock_bh(&conn->taskqueuelock);
 		if (iscsi_prep_mgmt_task(conn, conn->task)) {
 			/* regular RX path uses back_lock */
 			spin_lock_bh(&conn->session->back_lock);
 			__iscsi_put_task(conn->task);
 			spin_unlock_bh(&conn->session->back_lock);
 			conn->task = NULL;
+			spin_lock_bh(&conn->taskqueuelock);
 			continue;
 		}
 		rc = iscsi_xmit_task(conn);
 		if (rc)
 			goto done;
+		spin_lock_bh(&conn->taskqueuelock);
 	}
 	/* process pending command queue */
 		conn->task = list_entry(conn->cmdqueue.next, struct iscsi_task,
 					running);
 		list_del_init(&conn->task->running);
+		spin_unlock_bh(&conn->taskqueuelock);
 		if (conn->session->state == ISCSI_STATE_LOGGING_OUT) {
 			fail_scsi_task(conn->task, DID_IMM_RETRY);
+			spin_lock_bh(&conn->taskqueuelock);
 			continue;
 		}
 		rc = iscsi_prep_scsi_cmd_pdu(conn->task);
 		if (rc) {
 			if (rc == -ENOMEM || rc == -EACCES) {
+				spin_lock_bh(&conn->taskqueuelock);
 				list_add_tail(&conn->task->running,
 					      &conn->cmdqueue);
 				conn->task = NULL;
+				spin_unlock_bh(&conn->taskqueuelock);
 				goto done;
 			} else
 				fail_scsi_task(conn->task, DID_ABORT);
+			spin_lock_bh(&conn->taskqueuelock);
 			continue;
 		}
 		rc = iscsi_xmit_task(conn);
 		 * we need to check the mgmt queue for nops that need to
 		 * be sent to aviod starvation
 		 */
+		spin_lock_bh(&conn->taskqueuelock);
 		if (!list_empty(&conn->mgmtqueue))
 			goto check_mgmt;
 	}
 		conn->task = task;
 		list_del_init(&conn->task->running);
 		conn->task->state = ISCSI_TASK_RUNNING;
+		spin_unlock_bh(&conn->taskqueuelock);
 		rc = iscsi_xmit_task(conn);
 		if (rc)
 			goto done;
+		spin_lock_bh(&conn->taskqueuelock);
 		if (!list_empty(&conn->mgmtqueue))
 			goto check_mgmt;
 	}
+	spin_unlock_bh(&conn->taskqueuelock);
 	spin_unlock_bh(&conn->session->frwd_lock);
 	return -ENODATA;
 			goto prepd_reject;
 		}
 	} else {
+		spin_lock_bh(&conn->taskqueuelock);
 		list_add_tail(&task->running, &conn->cmdqueue);
+		spin_unlock_bh(&conn->taskqueuelock);
 		iscsi_conn_queue_work(conn);
 	}
 	INIT_LIST_HEAD(&conn->mgmtqueue);
 	INIT_LIST_HEAD(&conn->cmdqueue);
 	INIT_LIST_HEAD(&conn->requeue);
+	spin_lock_init(&conn->taskqueuelock);
 	INIT_WORK(&conn->xmitwork, iscsi_xmitworker);
 	/* allocate login_task used for the login/text sequences */

drivers/scsi/lpfc/lpfc.h+3−1

 #define FC_MAX_ADPTMSG		64
 #define MAX_HBAEVT	32
+#define MAX_HBAS_NO_RESET 16
 /* Number of MSI-X vectors the driver uses */
 #define LPFC_MSIX_VECTORS	2
 /* lpfc wait event data ready flag */
-#define LPFC_DATA_READY		(1<<0)
+#define LPFC_DATA_READY		0	/* bit 0 */
 /* queue dump line buffer size */
 #define LPFC_LBUF_SZ		128
 					 * capability
 					 */
 #define HBA_NVME_IOQ_FLUSH      0x80000 /* NVME IO queues flushed. */
+#define NVME_XRI_ABORT_EVENT	0x100000
 	uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
 	struct lpfc_dmabuf slim2p;

drivers/scsi/lpfc/lpfc_attr.c+10−3

@@ -3010,6 +3010,12 @@ MODULE_PARM_DESC(lpfc_poll, "FCP ring polling mode control:" · 3009 unmodified lines
3010	static DEVICE_ATTR(lpfc_poll, S_IRUGO \| S_IWUSR,	3010	static DEVICE_ATTR(lpfc_poll, S_IRUGO \| S_IWUSR,
3011	lpfc_poll_show, lpfc_poll_store);	3011	lpfc_poll_show, lpfc_poll_store);
3012		3012
		3013	int lpfc_no_hba_reset_cnt;
		3014	unsigned long lpfc_no_hba_reset[MAX_HBAS_NO_RESET] = {
		3015	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
		3016	module_param_array(lpfc_no_hba_reset, ulong, &lpfc_no_hba_reset_cnt, 0444);
		3017	MODULE_PARM_DESC(lpfc_no_hba_reset, "WWPN of HBAs that should not be reset");
		3018
3013	LPFC_ATTR(sli_mode, 0, 0, 3,	3019	LPFC_ATTR(sli_mode, 0, 0, 3,
3014	"SLI mode selector:"	3020	"SLI mode selector:"
3015	" 0 - auto (SLI-3 if supported),"	3021	" 0 - auto (SLI-3 if supported),"
@@ -3309,9 +3315,9 @@ LPFC_ATTR_R(nvmet_mrq_post, LPFC_DEF_MRQ_POST, · 293 unmodified lines
3309	* lpfc_enable_fc4_type: Defines what FC4 types are supported.	3315	* lpfc_enable_fc4_type: Defines what FC4 types are supported.
3310	* Supported Values: 1 - register just FCP	3316	* Supported Values: 1 - register just FCP
3311	* 3 - register both FCP and NVME	3317	* 3 - register both FCP and NVME
3312	* Supported values are [1,3]. Default value is 3	3318	* Supported values are [1,3]. Default value is 1
3313	*/	3319	*/
3314	LPFC_ATTR_R(enable_fc4_type, LPFC_ENABLE_BOTH,	3320	LPFC_ATTR_R(enable_fc4_type, LPFC_ENABLE_FCP,
3315	LPFC_ENABLE_FCP, LPFC_ENABLE_BOTH,	3321	LPFC_ENABLE_FCP, LPFC_ENABLE_BOTH,
3316	"Define fc4 type to register with fabric.");	3322	"Define fc4 type to register with fabric.");
3317		3323
@@ -4451,7 +4457,8 @@ lpfc_fcp_imax_store(struct device dev, struct device_attribute attr, · 1133 unmodified lines
4451	return -EINVAL;	4457	return -EINVAL;
4452		4458
4453	phba->cfg_fcp_imax = (uint32_t)val;	4459	phba->cfg_fcp_imax = (uint32_t)val;
4454	for (i = 0; i < phba->io_channel_irqs; i++)	4460
		4461	for (i = 0; i < phba->io_channel_irqs; i += LPFC_MAX_EQ_DELAY_EQID_CNT)
4455	lpfc_modify_hba_eq_delay(phba, i);	4462	lpfc_modify_hba_eq_delay(phba, i);
4456		4463
4457	return strlen(buf);	4464	return strlen(buf);

drivers/scsi/lpfc/lpfc_crtn.h+3−1

 extern struct device_attribute *lpfc_hba_attrs[];
 extern struct device_attribute *lpfc_vport_attrs[];
 extern struct scsi_host_template lpfc_template;
-extern struct scsi_host_template lpfc_template_s3;
+extern struct scsi_host_template lpfc_template_no_hr;
 extern struct scsi_host_template lpfc_template_nvme;
 extern struct scsi_host_template lpfc_vport_template;
 extern struct fc_function_template lpfc_transport_functions;
 				struct lpfc_wcqe_complete *abts_cmpl);
 extern int lpfc_enable_nvmet_cnt;
 extern unsigned long long lpfc_enable_nvmet[];
+extern int lpfc_no_hba_reset_cnt;
+extern unsigned long lpfc_no_hba_reset[];

drivers/scsi/lpfc/lpfc_ct.c+1−1

 					 "FC4 x%08x, Data: x%08x x%08x\n",
 					 ndlp, did, ndlp->nlp_fc4_type,
 					 FC_TYPE_FCP, FC_TYPE_NVME);
+			ndlp->nlp_prev_state = NLP_STE_REG_LOGIN_ISSUE;
 		}
-		ndlp->nlp_prev_state = NLP_STE_REG_LOGIN_ISSUE;
 		lpfc_nlp_set_state(vport, ndlp, NLP_STE_PRLI_ISSUE);
 		lpfc_issue_els_prli(vport, ndlp, 0);
 	} else

drivers/scsi/lpfc/lpfc_debugfs.c+0−22

@@ -3653,17 +3653,6 @@ lpfc_idiag_queacc_write(struct file file, const char __user buf, · 3652 unmodified lines
3653	idiag.ptr_private = phba->sli4_hba.nvmels_cq;	3653	idiag.ptr_private = phba->sli4_hba.nvmels_cq;
3654	goto pass_check;	3654	goto pass_check;
3655	}	3655	}
3656	/* NVME LS complete queue */
3657	if (phba->sli4_hba.nvmels_cq &&
3658	phba->sli4_hba.nvmels_cq->queue_id == queid) {
3659	/* Sanity check */
3660	rc = lpfc_idiag_que_param_check(
3661	phba->sli4_hba.nvmels_cq, index, count);
3662	if (rc)
3663	goto error_out;
3664	idiag.ptr_private = phba->sli4_hba.nvmels_cq;
3665	goto pass_check;
3666	}
3667	/* FCP complete queue */	3656	/* FCP complete queue */
3668	if (phba->sli4_hba.fcp_cq) {	3657	if (phba->sli4_hba.fcp_cq) {
3669	for (qidx = 0; qidx < phba->cfg_fcp_io_channel;	3658	for (qidx = 0; qidx < phba->cfg_fcp_io_channel;
@@ -3738,17 +3727,6 @@ lpfc_idiag_queacc_write(struct file file, const char __user buf, · 68 unmodified lines
3738	idiag.ptr_private = phba->sli4_hba.nvmels_wq;	3727	idiag.ptr_private = phba->sli4_hba.nvmels_wq;
3739	goto pass_check;	3728	goto pass_check;
3740	}	3729	}
3741	/* NVME LS work queue */
3742	if (phba->sli4_hba.nvmels_wq &&
3743	phba->sli4_hba.nvmels_wq->queue_id == queid) {
3744	/* Sanity check */
3745	rc = lpfc_idiag_que_param_check(
3746	phba->sli4_hba.nvmels_wq, index, count);
3747	if (rc)
3748	goto error_out;
3749	idiag.ptr_private = phba->sli4_hba.nvmels_wq;
3750	goto pass_check;
3751	}
3752	/* FCP work queue */	3730	/* FCP work queue */
3753	if (phba->sli4_hba.fcp_wq) {	3731	if (phba->sli4_hba.fcp_wq) {
3754	for (qidx = 0; qidx < phba->cfg_fcp_io_channel;	3732	for (qidx = 0; qidx < phba->cfg_fcp_io_channel;

drivers/scsi/lpfc/lpfc_els.c+14−8

 static uint32_t
 lpfc_rdp_res_diag_port_names(struct fc_rdp_port_name_desc *desc,
-		struct lpfc_hba *phba)
+		struct lpfc_vport *vport)
 {
 	desc->tag = cpu_to_be32(RDP_PORT_NAMES_DESC_TAG);
-	memcpy(desc->port_names.wwnn, phba->wwnn,
+	memcpy(desc->port_names.wwnn, &vport->fc_nodename,
 			sizeof(desc->port_names.wwnn));
-	memcpy(desc->port_names.wwpn, phba->wwpn,
+	memcpy(desc->port_names.wwpn, &vport->fc_portname,
 			sizeof(desc->port_names.wwpn));
 	desc->length = cpu_to_be32(sizeof(desc->port_names));
 	len += lpfc_rdp_res_link_error((struct fc_rdp_link_error_status_desc *)
 				       (len + pcmd), &rdp_context->link_stat);
 	len += lpfc_rdp_res_diag_port_names((struct fc_rdp_port_name_desc *)
-					     (len + pcmd), phba);
+					     (len + pcmd), vport);
 	len += lpfc_rdp_res_attach_port_names((struct fc_rdp_port_name_desc *)
 					(len + pcmd), vport, ndlp);
 	len += lpfc_rdp_res_fec_desc((struct fc_fec_rdp_desc *)(len + pcmd),
 			spin_lock_irq(shost->host_lock);
 			vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
 			spin_unlock_irq(shost->host_lock);
-			if (vport->port_type == LPFC_PHYSICAL_PORT
+			if (mb->mbxStatus == MBX_NOT_FINISHED)
-				&& !(vport->fc_flag & FC_LOGO_RCVD_DID_CHNG))
+				break;
-				lpfc_issue_init_vfi(vport);
+			if ((vport->port_type == LPFC_PHYSICAL_PORT) &&
-			else
+			    !(vport->fc_flag & FC_LOGO_RCVD_DID_CHNG)) {
+				if (phba->sli_rev == LPFC_SLI_REV4)
+					lpfc_issue_init_vfi(vport);
+				else
+					lpfc_initial_flogi(vport);
+			} else {
 				lpfc_initial_fdisc(vport);
+			}
 			break;
 		}
 	} else {

drivers/scsi/lpfc/lpfc_hbadisc.c+13−11

 				 ndlp->nlp_state, ndlp->nlp_rpi);
 	}
-	if (!(vport->load_flag & FC_UNLOADING) &&
+	if (!(ndlp->nlp_flag & NLP_DELAY_TMO) &&
-	    !(ndlp->nlp_flag & NLP_DELAY_TMO) &&
 	    !(ndlp->nlp_flag & NLP_NPR_2B_DISC) &&
 	    (ndlp->nlp_state != NLP_STE_UNMAPPED_NODE) &&
 	    (ndlp->nlp_state != NLP_STE_REG_LOGIN_ISSUE) &&
 			lpfc_handle_rrq_active(phba);
 		if (phba->hba_flag & FCP_XRI_ABORT_EVENT)
 			lpfc_sli4_fcp_xri_abort_event_proc(phba);
+		if (phba->hba_flag & NVME_XRI_ABORT_EVENT)
+			lpfc_sli4_nvme_xri_abort_event_proc(phba);
 		if (phba->hba_flag & ELS_XRI_ABORT_EVENT)
 			lpfc_sli4_els_xri_abort_event_proc(phba);
 		if (phba->hba_flag & ASYNC_EVENT)
 	uint32_t boot_flag, addr_mode;
 	uint16_t fcf_index, next_fcf_index;
 	struct lpfc_fcf_rec *fcf_rec = NULL;
-	uint16_t vlan_id;
+	uint16_t vlan_id = LPFC_FCOE_NULL_VID;
 	bool select_new_fcf;
 	int rc;
 		rdata = rport->dd_data;
 		/* break the link before dropping the ref */
 		ndlp->rport = NULL;
-		if (rdata && rdata->pnode == ndlp)
+		if (rdata) {
-			lpfc_nlp_put(ndlp);
+			if (rdata->pnode == ndlp)
-		rdata->pnode = NULL;
+				lpfc_nlp_put(ndlp);
+			rdata->pnode = NULL;
+		}
 		/* drop reference for earlier registeration */
 		put_device(&rport->dev);
 	}
 {
 	INIT_LIST_HEAD(&ndlp->els_retry_evt.evt_listp);
 	INIT_LIST_HEAD(&ndlp->dev_loss_evt.evt_listp);
-	init_timer(&ndlp->nlp_delayfunc);
+	setup_timer(&ndlp->nlp_delayfunc, lpfc_els_retry_delay,
-	ndlp->nlp_delayfunc.function = lpfc_els_retry_delay;
+			(unsigned long)ndlp);
-	ndlp->nlp_delayfunc.data = (unsigned long)ndlp;
 	ndlp->nlp_DID = did;
 	ndlp->vport = vport;
 	ndlp->phba = vport->phba;
 		pring = qp->pring;
 		if (!pring)
 			continue;
-		spin_lock_irq(&pring->ring_lock);
+		spin_lock(&pring->ring_lock);
 		__lpfc_dequeue_nport_iocbs(phba, ndlp, pring, dequeue_list);
-		spin_unlock_irq(&pring->ring_lock);
+		spin_unlock(&pring->ring_lock);
 	}
 	spin_unlock_irq(&phba->hbalock);
 }

drivers/scsi/lpfc/lpfc_hw4.h+2−2

@@ -1001,7 +1001,7 @@ struct eq_delay_info { · 1000 unmodified lines
1001	uint32_t phase;	1001	uint32_t phase;
1002	uint32_t delay_multi;	1002	uint32_t delay_multi;
1003	};	1003	};
1004	#define LPFC_MAX_EQ_DELAY 8	1004	#define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1005		1005
1006	struct sgl_page_pairs {	1006	struct sgl_page_pairs {
1007	uint32_t sgl_pg0_addr_lo;	1007	uint32_t sgl_pg0_addr_lo;
@@ -1070,7 +1070,7 @@ struct lpfc_mbx_modify_eq_delay { · 62 unmodified lines
1070	union {	1070	union {
1071	struct {	1071	struct {
1072	uint32_t num_eq;	1072	uint32_t num_eq;
1073	struct eq_delay_info eq[LPFC_MAX_EQ_DELAY];	1073	struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1074	} request;	1074	} request;
1075	struct {	1075	struct {
1076	uint32_t word0;	1076	uint32_t word0;

drivers/scsi/lpfc/lpfc_init.c+92−43

 	return rc;
 }
+static uint64_t
+lpfc_get_wwpn(struct lpfc_hba *phba)
+{
+	uint64_t wwn;
+	int rc;
+	LPFC_MBOXQ_t *mboxq;
+	MAILBOX_t *mb;
+	mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
+						GFP_KERNEL);
+	if (!mboxq)
+		return (uint64_t)-1;
+	/* First get WWN of HBA instance */
+	lpfc_read_nv(phba, mboxq);
+	rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
+	if (rc != MBX_SUCCESS) {
+		lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+				"6019 Mailbox failed , mbxCmd x%x "
+				"READ_NV, mbxStatus x%x\n",
+				bf_get(lpfc_mqe_command, &mboxq->u.mqe),
+				bf_get(lpfc_mqe_status, &mboxq->u.mqe));
+		mempool_free(mboxq, phba->mbox_mem_pool);
+		return (uint64_t) -1;
+	}
+	mb = &mboxq->u.mb;
+	memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
+	/* wwn is WWPN of HBA instance */
+	mempool_free(mboxq, phba->mbox_mem_pool);
+	if (phba->sli_rev == LPFC_SLI_REV4)
+		return be64_to_cpu(wwn);
+	else
+		return (((wwn & 0xffffffff00000000) >> 32) |
+			((wwn & 0x00000000ffffffff) << 32));
+}
 /**
  * lpfc_sli4_nvme_sgl_update - update xri-sgl sizing and mapping
  * @phba: pointer to lpfc hba data structure.
 	struct lpfc_vport *vport;
 	struct Scsi_Host  *shost = NULL;
 	int error = 0;
+	int i;
+	uint64_t wwn;
+	bool use_no_reset_hba = false;
+	wwn = lpfc_get_wwpn(phba);
+	for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
+		if (wwn == lpfc_no_hba_reset[i]) {
+			lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+					"6020 Setting use_no_reset port=%llx\n",
+					wwn);
+			use_no_reset_hba = true;
+			break;
+		}
+	}
 	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
 		if (dev != &phba->pcidev->dev) {
 			shost = scsi_host_alloc(&lpfc_vport_template,
 						sizeof(struct lpfc_vport));
 		} else {
-			if (phba->sli_rev == LPFC_SLI_REV4)
+			if (!use_no_reset_hba)
 				shost = scsi_host_alloc(&lpfc_template,
 						sizeof(struct lpfc_vport));
 			else
-				shost = scsi_host_alloc(&lpfc_template_s3,
+				shost = scsi_host_alloc(&lpfc_template_no_hr,
 						sizeof(struct lpfc_vport));
 		}
 	} else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
 	INIT_LIST_HEAD(&vport->rcv_buffer_list);
 	spin_lock_init(&vport->work_port_lock);
-	init_timer(&vport->fc_disctmo);
+	setup_timer(&vport->fc_disctmo, lpfc_disc_timeout,
-	vport->fc_disctmo.function = lpfc_disc_timeout;
+			(unsigned long)vport);
-	vport->fc_disctmo.data = (unsigned long)vport;
-	init_timer(&vport->els_tmofunc);
+	setup_timer(&vport->els_tmofunc, lpfc_els_timeout,
-	vport->els_tmofunc.function = lpfc_els_timeout;
+			(unsigned long)vport);
-	vport->els_tmofunc.data = (unsigned long)vport;
-	init_timer(&vport->delayed_disc_tmo);
+	setup_timer(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo,
-	vport->delayed_disc_tmo.function = lpfc_delayed_disc_tmo;
+			(unsigned long)vport);
-	vport->delayed_disc_tmo.data = (unsigned long)vport;
 	error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
 	if (error)
 	INIT_LIST_HEAD(&phba->luns);
 	/* MBOX heartbeat timer */
-	init_timer(&psli->mbox_tmo);
+	setup_timer(&psli->mbox_tmo, lpfc_mbox_timeout, (unsigned long)phba);
-	psli->mbox_tmo.function = lpfc_mbox_timeout;
-	psli->mbox_tmo.data = (unsigned long) phba;
 	/* Fabric block timer */
-	init_timer(&phba->fabric_block_timer);
+	setup_timer(&phba->fabric_block_timer, lpfc_fabric_block_timeout,
-	phba->fabric_block_timer.function = lpfc_fabric_block_timeout;
+			(unsigned long)phba);
-	phba->fabric_block_timer.data = (unsigned long) phba;
 	/* EA polling mode timer */
-	init_timer(&phba->eratt_poll);
+	setup_timer(&phba->eratt_poll, lpfc_poll_eratt,
-	phba->eratt_poll.function = lpfc_poll_eratt;
+			(unsigned long)phba);
-	phba->eratt_poll.data = (unsigned long) phba;
 	/* Heartbeat timer */
-	init_timer(&phba->hb_tmofunc);
+	setup_timer(&phba->hb_tmofunc, lpfc_hb_timeout, (unsigned long)phba);
-	phba->hb_tmofunc.function = lpfc_hb_timeout;
-	phba->hb_tmofunc.data = (unsigned long)phba;
 	return 0;
 }
 	 */
 	/* FCP polling mode timer */
-	init_timer(&phba->fcp_poll_timer);
+	setup_timer(&phba->fcp_poll_timer, lpfc_poll_timeout,
-	phba->fcp_poll_timer.function = lpfc_poll_timeout;
+			(unsigned long)phba);
-	phba->fcp_poll_timer.data = (unsigned long) phba;
 	/* Host attention work mask setup */
 	phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
 	/* Initialize the host templates the configured values. */
 	lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
-	lpfc_template_s3.sg_tablesize = phba->cfg_sg_seg_cnt;
+	lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
+	lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
 	/* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
 	if (phba->cfg_enable_bg) {
 	 * Initialize timers used by driver
 	 */
-	init_timer(&phba->rrq_tmr);
+	setup_timer(&phba->rrq_tmr, lpfc_rrq_timeout, (unsigned long)phba);
-	phba->rrq_tmr.function = lpfc_rrq_timeout;
-	phba->rrq_tmr.data = (unsigned long)phba;
 	/* FCF rediscover timer */
-	init_timer(&phba->fcf.redisc_wait);
+	setup_timer(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo,
-	phba->fcf.redisc_wait.function = lpfc_sli4_fcf_redisc_wait_tmo;
+			(unsigned long)phba);
-	phba->fcf.redisc_wait.data = (unsigned long)phba;
 	/*
 	 * Control structure for handling external multi-buffer mailbox
 	/* Initialize the host templates with the updated values. */
 	lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
 	lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
+	lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
 	if (phba->cfg_sg_dma_buf_size  <= LPFC_MIN_SG_SLI4_BUF_SZ)
 		phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
 		/* Initialize the Abort nvme buffer list used by driver */
 		spin_lock_init(&phba->sli4_hba.abts_nvme_buf_list_lock);
 		INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvme_buf_list);
+		/* Fast-path XRI aborted CQ Event work queue list */
+		INIT_LIST_HEAD(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue);
 	}
 	/* This abort list used by worker thread */
 		/* Check to see if it matches any module parameter */
 		for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
 			if (wwn == lpfc_enable_nvmet[i]) {
+#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
 				lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
 						"6017 NVME Target %016llx\n",
 						wwn);
 				phba->nvmet_support = 1; /* a match */
+#else
+				lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
+						"6021 Can't enable NVME Target."
+						" NVME_TARGET_FC infrastructure"
+						" is not in kernel\n");
+#endif
 			}
 		}
 	}
 		}
 	}
-	/*
+	for (qidx = 0; qidx < io_channel; qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
-	 * Configure EQ delay multipier for interrupt coalescing using
-	 * MODIFY_EQ_DELAY for all EQs created, LPFC_MAX_EQ_DELAY at a time.
-	 */
-	for (qidx = 0; qidx < io_channel; qidx += LPFC_MAX_EQ_DELAY)
 		lpfc_modify_hba_eq_delay(phba, qidx);
 	return 0;
 out_destroy:
 	/* Pending ELS XRI abort events */
 	list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
 			 &cqelist);
+	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
+		/* Pending NVME XRI abort events */
+		list_splice_init(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue,
+				 &cqelist);
+	}
 	/* Pending asynnc events */
 	list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
 			 &cqelist);
 	fc_remove_host(shost);
 	scsi_remove_host(shost);
-	/* Perform ndlp cleanup on the physical port.  The nvme and nvmet
-	 * localports are destroyed after to cleanup all transport memory.
-	 */
 	lpfc_cleanup(vport);
-	lpfc_nvmet_destroy_targetport(phba);
-	lpfc_nvme_destroy_localport(vport);
 	/*
 	 * Bring down the SLI Layer. This step disable all interrupts,
 	.id_table	= lpfc_id_table,
 	.probe		= lpfc_pci_probe_one,
 	.remove		= lpfc_pci_remove_one,
+	.shutdown	= lpfc_pci_remove_one,
 	.suspend        = lpfc_pci_suspend_one,
 	.resume		= lpfc_pci_resume_one,
 	.err_handler    = &lpfc_err_handler,

drivers/scsi/lpfc/lpfc_mem.c+1−1

 	}
 	dma_buf->iocbq = lpfc_sli_get_iocbq(phba);
-	dma_buf->iocbq->iocb_flag = LPFC_IO_NVMET;
 	if (!dma_buf->iocbq) {
 		kfree(dma_buf->context);
 		pci_pool_free(phba->lpfc_drb_pool, dma_buf->dbuf.virt,
 				"2621 Ran out of nvmet iocb/WQEs\n");
 		return NULL;
 	}
+	dma_buf->iocbq->iocb_flag = LPFC_IO_NVMET;
 	nvmewqe = dma_buf->iocbq;
 	wqe = (union lpfc_wqe128 *)&nvmewqe->wqe;
 	/* Initialize WQE */

drivers/scsi/lpfc/lpfc_nvme.c+82−25

 	bf_set(wqe_dfctl, &wqe->gen_req.wge_ctl, 0);
 	bf_set(wqe_si, &wqe->gen_req.wge_ctl, 1);
 	bf_set(wqe_la, &wqe->gen_req.wge_ctl, 1);
-	bf_set(wqe_rctl, &wqe->gen_req.wge_ctl, FC_RCTL_DD_UNSOL_CTL);
+	bf_set(wqe_rctl, &wqe->gen_req.wge_ctl, FC_RCTL_ELS4_REQ);
 	bf_set(wqe_type, &wqe->gen_req.wge_ctl, FC_TYPE_NVME);
 	/* Word 6 */
 	 * Embed the payload in the last half of the WQE
 	 * WQE words 16-30 get the NVME CMD IU payload
 	 *
-	 * WQE Word 16 is already setup with flags
+	 * WQE words 16-19 get payload Words 1-4
-	 * WQE words 17-19 get payload Words 2-4
 	 * WQE words 20-21 get payload Words 6-7
 	 * WQE words 22-29 get payload Words 16-23
 	 */
-	wptr = &wqe->words[17];  /* WQE ptr */
+	wptr = &wqe->words[16];  /* WQE ptr */
 	dptr = (uint32_t *)nCmd->cmdaddr;  /* payload ptr */
-	dptr += 2;		/* Skip Words 0-1 in payload */
+	dptr++;			/* Skip Word 0 in payload */
+	*wptr++ = *dptr++;	/* Word 1 */
 	*wptr++ = *dptr++;	/* Word 2 */
 	*wptr++ = *dptr++;	/* Word 3 */
 	*wptr++ = *dptr++;	/* Word 4 */
 			bf_set(wqe_cmd_type, &wqe->generic.wqe_com,
 			       NVME_WRITE_CMD);
-			/* Word 16 */
-			wqe->words[16] = LPFC_NVME_EMBED_WRITE;
 			phba->fc4NvmeOutputRequests++;
 		} else {
 			/* Word 7 */
 			bf_set(wqe_cmd_type, &wqe->generic.wqe_com,
 			       NVME_READ_CMD);
-			/* Word 16 */
-			wqe->words[16] = LPFC_NVME_EMBED_READ;
 			phba->fc4NvmeInputRequests++;
 		}
 	} else {
 		/* Word 11 */
 		bf_set(wqe_cmd_type, &wqe->generic.wqe_com, NVME_READ_CMD);
-		/* Word 16 */
-		wqe->words[16] = LPFC_NVME_EMBED_CMD;
 		phba->fc4NvmeControlRequests++;
 	}
 	/*
 	pnvme_fcreq->private = (void *)lpfc_ncmd;
 	lpfc_ncmd->nvmeCmd = pnvme_fcreq;
 	lpfc_ncmd->nrport = rport;
+	lpfc_ncmd->ndlp = ndlp;
 	lpfc_ncmd->start_time = jiffies;
 	lpfc_nvme_prep_io_cmd(vport, lpfc_ncmd, ndlp);
 				 "sid: x%x did: x%x oxid: x%x\n",
 				 ret, vport->fc_myDID, ndlp->nlp_DID,
 				 lpfc_ncmd->cur_iocbq.sli4_xritag);
-		ret = -EINVAL;
+		ret = -EBUSY;
 		goto out_free_nvme_buf;
 	}
 						pdma_phys_sgl1, cur_xritag);
 				if (status) {
 					/* failure, put on abort nvme list */
-					lpfc_ncmd->exch_busy = 1;
+					lpfc_ncmd->flags |= LPFC_SBUF_XBUSY;
 				} else {
 					/* success, put on NVME buffer list */
-					lpfc_ncmd->exch_busy = 0;
+					lpfc_ncmd->flags &= ~LPFC_SBUF_XBUSY;
 					lpfc_ncmd->status = IOSTAT_SUCCESS;
 					num_posted++;
 				}
 					 struct lpfc_nvme_buf, list);
 			if (status) {
 				/* failure, put on abort nvme list */
-				lpfc_ncmd->exch_busy = 1;
+				lpfc_ncmd->flags |= LPFC_SBUF_XBUSY;
 			} else {
 				/* success, put on NVME buffer list */
-				lpfc_ncmd->exch_busy = 0;
+				lpfc_ncmd->flags &= ~LPFC_SBUF_XBUSY;
 				lpfc_ncmd->status = IOSTAT_SUCCESS;
 				num_posted++;
 			}
 	unsigned long iflag = 0;
 	lpfc_ncmd->nonsg_phys = 0;
-	if (lpfc_ncmd->exch_busy) {
+	if (lpfc_ncmd->flags & LPFC_SBUF_XBUSY) {
 		spin_lock_irqsave(&phba->sli4_hba.abts_nvme_buf_list_lock,
 					iflag);
 		lpfc_ncmd->nvmeCmd = NULL;
 int
 lpfc_nvme_create_localport(struct lpfc_vport *vport)
 {
+	int ret = 0;
 	struct lpfc_hba  *phba = vport->phba;
 	struct nvme_fc_port_info nfcp_info;
 	struct nvme_fc_local_port *localport;
 	struct lpfc_nvme_lport *lport;
-	int len, ret = 0;
+	int len;
 	/* Initialize this localport instance.  The vport wwn usage ensures
 	 * that NPIV is accounted for.
 	/* localport is allocated from the stack, but the registration
 	 * call allocates heap memory as well as the private area.
 	 */
+#if (IS_ENABLED(CONFIG_NVME_FC))
 	ret = nvme_fc_register_localport(&nfcp_info, &lpfc_nvme_template,
 					 &vport->phba->pcidev->dev, &localport);
+#else
+	ret = -ENOMEM;
+#endif
 	if (!ret) {
 		lpfc_printf_vlog(vport, KERN_INFO, LOG_NVME | LOG_NVME_DISC,
 				 "6005 Successfully registered local "
 		lport->vport = vport;
 		INIT_LIST_HEAD(&lport->rport_list);
 		vport->nvmei_support = 1;
+		len  = lpfc_new_nvme_buf(vport, phba->sli4_hba.nvme_xri_max);
+		vport->phba->total_nvme_bufs += len;
 	}
-	len  = lpfc_new_nvme_buf(vport, phba->sli4_hba.nvme_xri_max);
-	vport->phba->total_nvme_bufs += len;
 	return ret;
 }
 void
 lpfc_nvme_destroy_localport(struct lpfc_vport *vport)
 {
+#if (IS_ENABLED(CONFIG_NVME_FC))
 	struct nvme_fc_local_port *localport;
 	struct lpfc_nvme_lport *lport;
 	struct lpfc_nvme_rport *rport = NULL, *rport_next = NULL;
 	lpfc_printf_vlog(vport, KERN_INFO, LOG_NVME,
 			 "6011 Destroying NVME localport %p\n",
 			 localport);
 	list_for_each_entry_safe(rport, rport_next, &lport->rport_list, list) {
 		/* The last node ref has to get released now before the rport
 		 * private memory area is released by the transport.
 					 "6008 rport fail destroy %x\n", ret);
 		wait_for_completion_timeout(&rport->rport_unreg_done, 5);
 	}
 	/* lport's rport list is clear.  Unregister
 	 * lport and release resources.
 	 */
 				 "Failed, status x%x\n",
 				 ret);
 	}
+#endif
 }
 void
 int
 lpfc_nvme_register_port(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp)
 {
+#if (IS_ENABLED(CONFIG_NVME_FC))
 	int ret = 0;
 	struct nvme_fc_local_port *localport;
 	struct lpfc_nvme_lport *lport;
 			rpinfo.port_role |= FC_PORT_ROLE_NVME_INITIATOR;
 		rpinfo.port_name = wwn_to_u64(ndlp->nlp_portname.u.wwn);
 		rpinfo.node_name = wwn_to_u64(ndlp->nlp_nodename.u.wwn);
 		ret = nvme_fc_register_remoteport(localport, &rpinfo,
 						  &remote_port);
 		if (!ret) {
 				 ndlp->nlp_type, ndlp->nlp_DID, ndlp);
 	}
 	return ret;
+#else
+	return 0;
+#endif
 }
 /* lpfc_nvme_unregister_port - unbind the DID and port_role from this rport.
 void
 lpfc_nvme_unregister_port(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp)
 {
+#if (IS_ENABLED(CONFIG_NVME_FC))
 	int ret;
 	struct nvme_fc_local_port *localport;
 	struct lpfc_nvme_lport *lport;
 	return;
  input_err:
+#endif
 	lpfc_printf_vlog(vport, KERN_ERR, LOG_NVME_DISC,
 			 "6168: State error: lport %p, rport%p FCID x%06x\n",
 			 vport->localport, ndlp->rport, ndlp->nlp_DID);
 }
+/**
+ * lpfc_sli4_nvme_xri_aborted - Fast-path process of NVME xri abort
+ * @phba: pointer to lpfc hba data structure.
+ * @axri: pointer to the fcp xri abort wcqe structure.
+ *
+ * This routine is invoked by the worker thread to process a SLI4 fast-path
+ * FCP aborted xri.
+ **/
+void
+lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
+			   struct sli4_wcqe_xri_aborted *axri)
+{
+	uint16_t xri = bf_get(lpfc_wcqe_xa_xri, axri);
+	uint16_t rxid = bf_get(lpfc_wcqe_xa_remote_xid, axri);
+	struct lpfc_nvme_buf *lpfc_ncmd, *next_lpfc_ncmd;
+	struct lpfc_nodelist *ndlp;
+	unsigned long iflag = 0;
+	int rrq_empty = 0;
+	if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME))
+		return;
+	spin_lock_irqsave(&phba->hbalock, iflag);
+	spin_lock(&phba->sli4_hba.abts_nvme_buf_list_lock);
+	list_for_each_entry_safe(lpfc_ncmd, next_lpfc_ncmd,
+				 &phba->sli4_hba.lpfc_abts_nvme_buf_list,
+				 list) {
+		if (lpfc_ncmd->cur_iocbq.sli4_xritag == xri) {
+			list_del(&lpfc_ncmd->list);
+			lpfc_ncmd->flags &= ~LPFC_SBUF_XBUSY;
+			lpfc_ncmd->status = IOSTAT_SUCCESS;
+			spin_unlock(
+				&phba->sli4_hba.abts_nvme_buf_list_lock);
+			rrq_empty = list_empty(&phba->active_rrq_list);
+			spin_unlock_irqrestore(&phba->hbalock, iflag);
+			ndlp = lpfc_ncmd->ndlp;
+			if (ndlp) {
+				lpfc_set_rrq_active(
+					phba, ndlp,
+					lpfc_ncmd->cur_iocbq.sli4_lxritag,
+					rxid, 1);
+				lpfc_sli4_abts_err_handler(phba, ndlp, axri);
+			}
+			lpfc_release_nvme_buf(phba, lpfc_ncmd);
+			if (rrq_empty)
+				lpfc_worker_wake_up(phba);
+			return;
+		}
+	}
+	spin_unlock(&phba->sli4_hba.abts_nvme_buf_list_lock);
+	spin_unlock_irqrestore(&phba->hbalock, iflag);
+}

drivers/scsi/lpfc/lpfc_nvme.h+1−0

@@ -57,6 +57,7 @@ struct lpfc_nvme_buf { · 56 unmodified lines
57	struct list_head list;	57	struct list_head list;
58	struct nvmefc_fcp_req *nvmeCmd;	58	struct nvmefc_fcp_req *nvmeCmd;
59	struct lpfc_nvme_rport *nrport;	59	struct lpfc_nvme_rport *nrport;
		60	struct lpfc_nodelist *ndlp;
60		61
61	uint32_t timeout;	62	uint32_t timeout;
62		63

drivers/scsi/lpfc/lpfc_nvmet.c+35−8

 		lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
 				"6102 Bad state IO x%x aborted\n",
 				ctxp->oxid);
+		rc = -ENXIO;
 		goto aerr;
 	}
 		lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
 				"6152 FCP Drop IO x%x: Prep\n",
 				ctxp->oxid);
+		rc = -ENXIO;
 		goto aerr;
 	}
 	ctxp->wqeq->hba_wqidx = 0;
 	nvmewqeq->context2 = NULL;
 	nvmewqeq->context3 = NULL;
+	rc = -EBUSY;
 aerr:
-	return -ENXIO;
+	return rc;
 }
 static void
 	lpfc_tgttemplate.target_features = NVMET_FCTGTFEAT_READDATA_RSP |
 					   NVMET_FCTGTFEAT_NEEDS_CMD_CPUSCHED;
+#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
 	error = nvmet_fc_register_targetport(&pinfo, &lpfc_tgttemplate,
 					     &phba->pcidev->dev,
 					     &phba->targetport);
+#else
+	error = -ENOMEM;
+#endif
 	if (error) {
 		lpfc_printf_log(phba, KERN_ERR, LOG_NVME_DISC,
 				"6025 Cannot register NVME targetport "
 	return 0;
 }
+/**
+ * lpfc_sli4_nvmet_xri_aborted - Fast-path process of nvmet xri abort
+ * @phba: pointer to lpfc hba data structure.
+ * @axri: pointer to the nvmet xri abort wcqe structure.
+ *
+ * This routine is invoked by the worker thread to process a SLI4 fast-path
+ * NVMET aborted xri.
+ **/
+void
+lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
+			    struct sli4_wcqe_xri_aborted *axri)
+{
+	/* TODO: work in progress */
+}
 void
 lpfc_nvmet_destroy_targetport(struct lpfc_hba *phba)
 {
+#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
 	struct lpfc_nvmet_tgtport *tgtp;
 	if (phba->nvmet_support == 0)
 		wait_for_completion_timeout(&tgtp->tport_unreg_done, 5);
 	}
 	phba->targetport = NULL;
+#endif
 }
 /**
 lpfc_nvmet_unsol_ls_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
 			   struct hbq_dmabuf *nvmebuf)
 {
+#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
 	struct lpfc_nvmet_tgtport *tgtp;
 	struct fc_frame_header *fc_hdr;
 	struct lpfc_nvmet_rcv_ctx *ctxp;
 	atomic_inc(&tgtp->xmt_ls_abort);
 	lpfc_nvmet_unsol_ls_issue_abort(phba, ctxp, sid, oxid);
+#endif
 }
 /**
 			    struct rqb_dmabuf *nvmebuf,
 			    uint64_t isr_timestamp)
 {
+#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
 	struct lpfc_nvmet_rcv_ctx *ctxp;
 	struct lpfc_nvmet_tgtport *tgtp;
 	struct fc_frame_header *fc_hdr;
 	atomic_inc(&tgtp->rcv_fcp_cmd_drop);
 	lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
-			"6159 FCP Drop IO x%x: nvmet_fc_rcv_fcp_req x%x\n",
+			"6159 FCP Drop IO x%x: err x%x\n",
 			ctxp->oxid, rc);
 dropit:
 	lpfc_nvmeio_data(phba, "NVMET FCP DROP: xri x%x sz %d from %06x\n",
 		/* We assume a rcv'ed cmd ALWAYs fits into 1 buffer */
 		lpfc_nvmet_rq_post(phba, NULL, &nvmebuf->hbuf);
 	}
+#endif
 }
 /**
 	bf_set(wqe_dfctl, &wqe->xmit_sequence.wge_ctl, 0);
 	bf_set(wqe_ls, &wqe->xmit_sequence.wge_ctl, 1);
 	bf_set(wqe_la, &wqe->xmit_sequence.wge_ctl, 0);
-	bf_set(wqe_rctl, &wqe->xmit_sequence.wge_ctl, FC_RCTL_DD_SOL_CTL);
+	bf_set(wqe_rctl, &wqe->xmit_sequence.wge_ctl, FC_RCTL_ELS4_REP);
 	bf_set(wqe_type, &wqe->xmit_sequence.wge_ctl, FC_TYPE_NVME);
 	/* Word 6 */
 	case NVMET_FCOP_RSP:
 		/* Words 0 - 2 */
-		sgel = &rsp->sg[0];
 		physaddr = rsp->rspdma;
 		wqe->fcp_trsp.bde.tus.f.bdeFlags = BUFF_TYPE_BDE_64;
 		wqe->fcp_trsp.bde.tus.f.bdeSize = rsp->rsplen;
 	struct lpfc_nodelist *ndlp;
 	lpfc_printf_log(phba, KERN_INFO, LOG_NVME_ABTS,
-			"6067 %s: Entrypoint: sid %x xri %x\n", __func__,
+			"6067 Abort: sid %x xri x%x/x%x\n",
-			sid, xri);
+			sid, xri, ctxp->wqeq->sli4_xritag);
 	tgtp = (struct lpfc_nvmet_tgtport *)phba->targetport->private;
 		atomic_inc(&tgtp->xmt_abort_rsp_error);
 		lpfc_printf_log(phba, KERN_WARNING, LOG_NVME_ABTS,
 				"6134 Drop ABTS - wrong NDLP state x%x.\n",
-				ndlp->nlp_state);
+				(ndlp) ? ndlp->nlp_state : NLP_STE_MAX_STATE);
 		/* No failure to an ABTS request. */
 		return 0;
 		atomic_inc(&tgtp->xmt_abort_rsp_error);
 		lpfc_printf_log(phba, KERN_WARNING, LOG_NVME_ABTS,
 				"6160 Drop ABTS - wrong NDLP state x%x.\n",
-				ndlp->nlp_state);
+				(ndlp) ? ndlp->nlp_state : NLP_STE_MAX_STATE);
 		/* No failure to an ABTS request. */
 		return 0;

drivers/scsi/lpfc/lpfc_scsi.c+2−2

 	.track_queue_depth	= 0,
 };
-struct scsi_host_template lpfc_template_s3 = {
+struct scsi_host_template lpfc_template_no_hr = {
 	.module			= THIS_MODULE,
 	.name			= LPFC_DRIVER_NAME,
 	.proc_name		= LPFC_DRIVER_NAME,
 	.info			= lpfc_info,
 	.queuecommand		= lpfc_queuecommand,
+	.eh_timed_out		= fc_eh_timed_out,
 	.eh_abort_handler	= lpfc_abort_handler,
 	.eh_device_reset_handler = lpfc_device_reset_handler,
 	.eh_target_reset_handler = lpfc_target_reset_handler,
 	.eh_abort_handler	= lpfc_abort_handler,
 	.eh_device_reset_handler = lpfc_device_reset_handler,
 	.eh_target_reset_handler = lpfc_target_reset_handler,
-	.eh_bus_reset_handler	= lpfc_bus_reset_handler,
 	.slave_alloc		= lpfc_slave_alloc,
 	.slave_configure	= lpfc_slave_configure,
 	.slave_destroy		= lpfc_slave_destroy,

drivers/scsi/lpfc/lpfc_sli.c+59−9

 /*******************************************************************
  * This file is part of the Emulex Linux Device Driver for         *
  * Fibre Channel Host Bus Adapters.                                *
 	start_sglq = sglq;
 	while (!found) {
 		if (!sglq)
-			return NULL;
+			break;
 		if (ndlp && ndlp->active_rrqs_xri_bitmap &&
 		    test_bit(sglq->sli4_lxritag,
 		    ndlp->active_rrqs_xri_bitmap)) {
 	}
 }
+/**
+ * lpfc_sli4_nvme_xri_abort_event_proc - Process nvme xri abort event
+ * @phba: pointer to lpfc hba data structure.
+ *
+ * This routine is invoked by the worker thread to process all the pending
+ * SLI4 NVME abort XRI events.
+ **/
+void lpfc_sli4_nvme_xri_abort_event_proc(struct lpfc_hba *phba)
+{
+	struct lpfc_cq_event *cq_event;
+	/* First, declare the fcp xri abort event has been handled */
+	spin_lock_irq(&phba->hbalock);
+	phba->hba_flag &= ~NVME_XRI_ABORT_EVENT;
+	spin_unlock_irq(&phba->hbalock);
+	/* Now, handle all the fcp xri abort events */
+	while (!list_empty(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue)) {
+		/* Get the first event from the head of the event queue */
+		spin_lock_irq(&phba->hbalock);
+		list_remove_head(&phba->sli4_hba.sp_nvme_xri_aborted_work_queue,
+				 cq_event, struct lpfc_cq_event, list);
+		spin_unlock_irq(&phba->hbalock);
+		/* Notify aborted XRI for NVME work queue */
+		if (phba->nvmet_support) {
+			lpfc_sli4_nvmet_xri_aborted(phba,
+						    &cq_event->cqe.wcqe_axri);
+		} else {
+			lpfc_sli4_nvme_xri_aborted(phba,
+						   &cq_event->cqe.wcqe_axri);
+		}
+		/* Free the event processed back to the free pool */
+		lpfc_sli4_cq_event_release(phba, cq_event);
+	}
+}
 /**
  * lpfc_sli4_els_xri_abort_event_proc - Process els xri abort event
  * @phba: pointer to lpfc hba data structure.
 		spin_unlock_irqrestore(&phba->hbalock, iflags);
 		workposted = true;
 		break;
+	case LPFC_NVME:
+		spin_lock_irqsave(&phba->hbalock, iflags);
+		list_add_tail(&cq_event->list,
+			      &phba->sli4_hba.sp_nvme_xri_aborted_work_queue);
+		/* Set the nvme xri abort event flag */
+		phba->hba_flag |= NVME_XRI_ABORT_EVENT;
+		spin_unlock_irqrestore(&phba->hbalock, iflags);
+		workposted = true;
+		break;
 	default:
 		lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
-				"0603 Invalid work queue CQE subtype (x%x)\n",
+				"0603 Invalid CQ subtype %d: "
-				cq->subtype);
+				"%08x %08x %08x %08x\n",
+				cq->subtype, wcqe->word0, wcqe->parameter,
+				wcqe->word2, wcqe->word3);
+		lpfc_sli4_cq_event_release(phba, cq_event);
 		workposted = false;
 		break;
 	}
  * @startq: The starting FCP EQ to modify
  *
  * This function sends an MODIFY_EQ_DELAY mailbox command to the HBA.
+ * The command allows up to LPFC_MAX_EQ_DELAY_EQID_CNT EQ ID's to be
+ * updated in one mailbox command.
  *
  * The @phba struct is used to send mailbox command to HBA. The @startq
  * is used to get the starting FCP EQ to change.
 		eq_delay->u.request.eq[cnt].phase = 0;
 		eq_delay->u.request.eq[cnt].delay_multi = dmult;
 		cnt++;
-		if (cnt >= LPFC_MAX_EQ_DELAY)
+		if (cnt >= LPFC_MAX_EQ_DELAY_EQID_CNT)
 			break;
 	}
 	eq_delay->u.request.num_eq = cnt;
 		drq = drqp[idx];
 		cq  = cqp[idx];
-		if (hrq->entry_count != drq->entry_count) {
-			status = -EINVAL;
-			goto out;
-		}
 		/* sanity check on queue memory */
 		if (!hrq || !drq || !cq) {
 			status = -ENODEV;
 			goto out;
 		}
+		if (hrq->entry_count != drq->entry_count) {
+			status = -EINVAL;
+			goto out;
+		}
 		if (idx == 0) {
 			bf_set(lpfc_mbx_rq_create_num_pages,
 			       &rq_create->u.request,

drivers/scsi/lpfc/lpfc_sli4.h+6−0

 	struct list_head sp_asynce_work_queue;
 	struct list_head sp_fcp_xri_aborted_work_queue;
 	struct list_head sp_els_xri_aborted_work_queue;
+	struct list_head sp_nvme_xri_aborted_work_queue;
 	struct list_head sp_unsol_work_queue;
 	struct lpfc_sli4_link link_state;
 	struct lpfc_sli4_lnk_info lnk_info;
 int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
 			void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
 void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
+void lpfc_sli4_nvme_xri_abort_event_proc(struct lpfc_hba *phba);
 void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
 void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *,
 			       struct sli4_wcqe_xri_aborted *);
+void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
+				struct sli4_wcqe_xri_aborted *axri);
+void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
+				 struct sli4_wcqe_xri_aborted *axri);
 void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
 			       struct sli4_wcqe_xri_aborted *);
 void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);

drivers/scsi/lpfc/lpfc_version.h+1−1

@@ -20,7 +20,7 @@ · 19 unmodified lines
20	* included with this package. *	20	* included with this package. *
21	*******************************************************************/	21	*******************************************************************/
22		22
23	#define LPFC_DRIVER_VERSION "11.2.0.7"	23	#define LPFC_DRIVER_VERSION "11.2.0.10"
24	#define LPFC_DRIVER_NAME "lpfc"	24	#define LPFC_DRIVER_NAME "lpfc"
25		25
26	/* Used for SLI 2/3 */	26	/* Used for SLI 2/3 */

drivers/scsi/megaraid/megaraid_sas.h+2−2

@@ -35,8 +35,8 @@ · 34 unmodified lines
35	/*	35	/*
36	* MegaRAID SAS Driver meta data	36	* MegaRAID SAS Driver meta data
37	*/	37	*/
38	#define MEGASAS_VERSION "07.701.16.00-rc1"	38	#define MEGASAS_VERSION "07.701.17.00-rc1"
39	#define MEGASAS_RELDATE "February 2, 2017"	39	#define MEGASAS_RELDATE "March 2, 2017"
40		40
41	/*	41	/*
42	* Device IDs	42	* Device IDs

drivers/scsi/megaraid/megaraid_sas_base.c+12−5

 	if (!mr_device_priv_data)
 		return -ENOMEM;
 	sdev->hostdata = mr_device_priv_data;
+	atomic_set(&mr_device_priv_data->r1_ldio_hint,
+		   instance->r1_ldio_hint_default);
 	return 0;
 }
 					 &instance->irq_context[j]);
 			/* Retry irq register for IO_APIC*/
 			instance->msix_vectors = 0;
-			if (is_probe)
+			if (is_probe) {
+				pci_free_irq_vectors(instance->pdev);
 				return megasas_setup_irqs_ioapic(instance);
-			else
+			} else {
 				return -1;
+			}
 		}
 	}
 	return 0;
 			MPI2_REPLY_POST_HOST_INDEX_OFFSET);
 	}
-	i = pci_alloc_irq_vectors(instance->pdev, 1, 1, PCI_IRQ_LEGACY);
+	if (!instance->msix_vectors) {
-	if (i < 0)
+		i = pci_alloc_irq_vectors(instance->pdev, 1, 1, PCI_IRQ_LEGACY);
-		goto fail_setup_irqs;
+		if (i < 0)
+			goto fail_setup_irqs;
+	}
 	dev_info(&instance->pdev->dev,
 		"firmware supports msix\t: (%d)", fw_msix_count);

drivers/scsi/megaraid/megaraid_sas_fusion.c+2−2

drivers/scsi/mpt3sas/mpt3sas_base.h+0−3

 	u64 sas_address, u16 handle, u8 phy_number, u8 link_rate);
 extern struct sas_function_template mpt3sas_transport_functions;
 extern struct scsi_transport_template *mpt3sas_transport_template;
-extern int scsi_internal_device_block(struct scsi_device *sdev);
-extern int scsi_internal_device_unblock(struct scsi_device *sdev,
-				enum scsi_device_state new_state);
 /* trigger data externs */
 void mpt3sas_send_trigger_data_event(struct MPT3SAS_ADAPTER *ioc,
 	struct SL_WH_TRIGGERS_EVENT_DATA_T *event_data);

drivers/scsi/mpt3sas/mpt3sas_scsih.c+2−17

 	    sas_device_priv_data->sas_target->handle);
 	sas_device_priv_data->block = 1;
-	r = scsi_internal_device_block(sdev);
+	r = scsi_internal_device_block(sdev, false);
 	if (r == -EINVAL)
 		sdev_printk(KERN_WARNING, sdev,
 		    "device_block failed with return(%d) for handle(0x%04x)\n",
 		    "performing a block followed by an unblock\n",
 		    r, sas_device_priv_data->sas_target->handle);
 		sas_device_priv_data->block = 1;
-		r = scsi_internal_device_block(sdev);
+		r = scsi_internal_device_block(sdev, false);
 		if (r)
 			sdev_printk(KERN_WARNING, sdev, "retried device_block "
 			    "failed with return(%d) for handle(0x%04x)\n",
 	struct MPT3SAS_DEVICE *sas_device_priv_data;
 	u32 response_code = 0;
 	unsigned long flags;
-	unsigned int sector_sz;
 	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 	}
 	xfer_cnt = le32_to_cpu(mpi_reply->TransferCount);
-	/* In case of bogus fw or device, we could end up having
-	 * unaligned partial completion. We can force alignment here,
-	 * then scsi-ml does not need to handle this misbehavior.
-	 */
-	sector_sz = scmd->device->sector_size;
-	if (unlikely(!blk_rq_is_passthrough(scmd->request) && sector_sz &&
-		     xfer_cnt % sector_sz)) {
-		sdev_printk(KERN_INFO, scmd->device,
-		    "unaligned partial completion avoided (xfer_cnt=%u, sector_sz=%u)\n",
-			    xfer_cnt, sector_sz);
-		xfer_cnt = round_down(xfer_cnt, sector_sz);
-	}
 	scsi_set_resid(scmd, scsi_bufflen(scmd) - xfer_cnt);
 	if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
 		log_info =  le32_to_cpu(mpi_reply->IOCLogInfo);

drivers/scsi/qedf/qedf_dbg.h+8−5

@@ -81,14 +81,17 @@ struct qedf_dbg_ctx { · 80 unmodified lines
81	#define QEDF_INFO(pdev, level, fmt, ...) \	81	#define QEDF_INFO(pdev, level, fmt, ...) \
82	qedf_dbg_info(pdev, __func__, __LINE__, level, fmt, \	82	qedf_dbg_info(pdev, __func__, __LINE__, level, fmt, \
83	## __VA_ARGS__)	83	## __VA_ARGS__)
84		84	__printf(4, 5)
85	extern void qedf_dbg_err(struct qedf_dbg_ctx qedf, const char func, u32 line,	85	void qedf_dbg_err(struct qedf_dbg_ctx qedf, const char func, u32 line,
86	const char *fmt, ...);	86	const char *fmt, ...);
87	extern void qedf_dbg_warn(struct qedf_dbg_ctx qedf, const char func, u32 line,	87	__printf(4, 5)
		88	void qedf_dbg_warn(struct qedf_dbg_ctx qedf, const char func, u32 line,
88	const char *, ...);	89	const char *, ...);
89	extern void qedf_dbg_notice(struct qedf_dbg_ctx qedf, const char func,	90	__printf(4, 5)
		91	void qedf_dbg_notice(struct qedf_dbg_ctx qedf, const char func,
90	u32 line, const char *, ...);	92	u32 line, const char *, ...);
91	extern void qedf_dbg_info(struct qedf_dbg_ctx qedf, const char func, u32 line,	93	__printf(5, 6)
		94	void qedf_dbg_info(struct qedf_dbg_ctx qedf, const char func, u32 line,
92	u32 info, const char *fmt, ...);	95	u32 info, const char *fmt, ...);
93		96
94	/* GRC Dump related defines */	97	/* GRC Dump related defines */

drivers/scsi/qedf/qedf_fip.c+1−1

@@ -203,7 +203,7 @@ void qedf_fip_recv(struct qedf_ctx qedf, struct sk_buff skb) · 202 unmodified lines
203	case FIP_DT_MAC:	203	case FIP_DT_MAC:
204	mp = (struct fip_mac_desc *)desc;	204	mp = (struct fip_mac_desc *)desc;
205	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_LL2,	205	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_LL2,
206	"fd_mac=%pM.\n", __func__, mp->fd_mac);	206	"fd_mac=%pM\n", mp->fd_mac);
207	ether_addr_copy(cvl_mac, mp->fd_mac);	207	ether_addr_copy(cvl_mac, mp->fd_mac);
208	break;	208	break;
209	case FIP_DT_NAME:	209	case FIP_DT_NAME:

drivers/scsi/qedf/qedf_io.c+2−2

drivers/scsi/qedf/qedf_main.c+2−2

@@ -2456,8 +2456,8 @@ static int qedf_alloc_bdq(struct qedf_ctx *qedf) · 2455 unmodified lines
2456	}	2456	}
2457		2457
2458	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_DISC,	2458	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_DISC,
2459	"BDQ PBL addr=0x%p dma=0x%llx.\n", qedf->bdq_pbl,	2459	"BDQ PBL addr=0x%p dma=%pad\n",
2460	qedf->bdq_pbl_dma);	2460	qedf->bdq_pbl, &qedf->bdq_pbl_dma);
2461		2461
2462	/*	2462	/*
2463	* Populate BDQ PBL with physical and virtual address of individual	2463	* Populate BDQ PBL with physical and virtual address of individual

drivers/scsi/qedi/qedi_debugfs.c+8−8

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	#include <linux/debugfs.h>	14	#include <linux/debugfs.h>
15	#include <linux/module.h>	15	#include <linux/module.h>
16		16
17	int do_not_recover;	17	int qedi_do_not_recover;
18	static struct dentry *qedi_dbg_root;	18	static struct dentry *qedi_dbg_root;
19		19
20	void	20	void
@@ -74,22 +74,22 @@ qedi_dbg_exit(void) · 53 unmodified lines
74	static ssize_t	74	static ssize_t
75	qedi_dbg_do_not_recover_enable(struct qedi_dbg_ctx *qedi_dbg)	75	qedi_dbg_do_not_recover_enable(struct qedi_dbg_ctx *qedi_dbg)
76	{	76	{
77	if (!do_not_recover)	77	if (!qedi_do_not_recover)
78	do_not_recover = 1;	78	qedi_do_not_recover = 1;
79		79
80	QEDI_INFO(qedi_dbg, QEDI_LOG_DEBUGFS, "do_not_recover=%d\n",	80	QEDI_INFO(qedi_dbg, QEDI_LOG_DEBUGFS, "do_not_recover=%d\n",
81	do_not_recover);	81	qedi_do_not_recover);
82	return 0;	82	return 0;
83	}	83	}
84		84
85	static ssize_t	85	static ssize_t
86	qedi_dbg_do_not_recover_disable(struct qedi_dbg_ctx *qedi_dbg)	86	qedi_dbg_do_not_recover_disable(struct qedi_dbg_ctx *qedi_dbg)
87	{	87	{
88	if (do_not_recover)	88	if (qedi_do_not_recover)
89	do_not_recover = 0;	89	qedi_do_not_recover = 0;
90		90
91	QEDI_INFO(qedi_dbg, QEDI_LOG_DEBUGFS, "do_not_recover=%d\n",	91	QEDI_INFO(qedi_dbg, QEDI_LOG_DEBUGFS, "do_not_recover=%d\n",
92	do_not_recover);	92	qedi_do_not_recover);
93	return 0;	93	return 0;
94	}	94	}
95		95
@@ -141,7 +141,7 @@ qedi_dbg_do_not_recover_cmd_read(struct file filp, char __user buffer, · 45 unmodified lines
141	if (*ppos)	141	if (*ppos)
142	return 0;	142	return 0;
143		143
144	cnt = sprintf(buffer, "do_not_recover=%d\n", do_not_recover);	144	cnt = sprintf(buffer, "do_not_recover=%d\n", qedi_do_not_recover);
145	cnt = min_t(int, count, cnt - *ppos);	145	cnt = min_t(int, count, cnt - *ppos);
146	*ppos += cnt;	146	*ppos += cnt;
147	return cnt;	147	return cnt;

drivers/scsi/qedi/qedi_fw.c+2−2

@@ -1461,9 +1461,9 @@ static void qedi_tmf_work(struct work_struct *work) · 1460 unmodified lines
1461	get_itt(tmf_hdr->rtt), get_itt(ctask->itt), cmd->task_id,	1461	get_itt(tmf_hdr->rtt), get_itt(ctask->itt), cmd->task_id,
1462	qedi_conn->iscsi_conn_id);	1462	qedi_conn->iscsi_conn_id);
1463		1463
1464	if (do_not_recover) {	1464	if (qedi_do_not_recover) {
1465	QEDI_ERR(&qedi->dbg_ctx, "DONT SEND CLEANUP/ABORT %d\n",	1465	QEDI_ERR(&qedi->dbg_ctx, "DONT SEND CLEANUP/ABORT %d\n",
1466	do_not_recover);	1466	qedi_do_not_recover);
1467	goto abort_ret;	1467	goto abort_ret;
1468	}	1468	}
1469		1469

drivers/scsi/qedi/qedi_gbl.h+7−1

@@ -12,8 +12,14 @@ · 11 unmodified lines
12		12
13	#include "qedi_iscsi.h"	13	#include "qedi_iscsi.h"
14		14
		15	#ifdef CONFIG_DEBUG_FS
		16	extern int qedi_do_not_recover;
		17	#else
		18	#define qedi_do_not_recover (0)
		19	#endif
		20
15	extern uint qedi_io_tracing;	21	extern uint qedi_io_tracing;
16	extern int do_not_recover;	22
17	extern struct scsi_host_template qedi_host_template;	23	extern struct scsi_host_template qedi_host_template;
18	extern struct iscsi_transport qedi_iscsi_transport;	24	extern struct iscsi_transport qedi_iscsi_transport;
19	extern const struct qed_iscsi_ops *qedi_ops;	25	extern const struct qed_iscsi_ops *qedi_ops;

drivers/scsi/qedi/qedi_iscsi.c+4−4

@@ -833,7 +833,7 @@ qedi_ep_connect(struct Scsi_Host shost, struct sockaddr dst_addr, · 832 unmodified lines
833	return ERR_PTR(ret);	833	return ERR_PTR(ret);
834	}	834	}
835		835
836	if (do_not_recover) {	836	if (qedi_do_not_recover) {
837	ret = -ENOMEM;	837	ret = -ENOMEM;
838	return ERR_PTR(ret);	838	return ERR_PTR(ret);
839	}	839	}
@@ -957,7 +957,7 @@ static int qedi_ep_poll(struct iscsi_endpoint *ep, int timeout_ms) · 117 unmodified lines
957	struct qedi_endpoint *qedi_ep;	957	struct qedi_endpoint *qedi_ep;
958	int ret = 0;	958	int ret = 0;
959		959
960	if (do_not_recover)	960	if (qedi_do_not_recover)
961	return 1;	961	return 1;
962		962
963	qedi_ep = ep->dd_data;	963	qedi_ep = ep->dd_data;
@@ -1025,7 +1025,7 @@ static void qedi_ep_disconnect(struct iscsi_endpoint *ep) · 61 unmodified lines
1025	}	1025	}
1026		1026
1027	if (test_bit(QEDI_IN_RECOVERY, &qedi->flags)) {	1027	if (test_bit(QEDI_IN_RECOVERY, &qedi->flags)) {
1028	if (do_not_recover) {	1028	if (qedi_do_not_recover) {
1029	QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_INFO,	1029	QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_INFO,
1030	"Do not recover cid=0x%x\n",	1030	"Do not recover cid=0x%x\n",
1031	qedi_ep->iscsi_cid);	1031	qedi_ep->iscsi_cid);
@@ -1039,7 +1039,7 @@ static void qedi_ep_disconnect(struct iscsi_endpoint *ep) · 7 unmodified lines
1039	}	1039	}
1040	}	1040	}
1041		1041
1042	if (do_not_recover)	1042	if (qedi_do_not_recover)
1043	goto ep_exit_recover;	1043	goto ep_exit_recover;
1044		1044
1045	switch (qedi_ep->state) {	1045	switch (qedi_ep->state) {

drivers/scsi/qedi/qedi_main.c+1−1

@@ -1805,7 +1805,7 @@ static int __qedi_probe(struct pci_dev *pdev, int mode) · 1804 unmodified lines
1805	*/	1805	*/
1806	qedi_ops->common->update_pf_params(qedi->cdev, &qedi->pf_params);	1806	qedi_ops->common->update_pf_params(qedi->cdev, &qedi->pf_params);
1807		1807
1808	qedi_setup_int(qedi);	1808	rc = qedi_setup_int(qedi);
1809	if (rc)	1809	if (rc)
1810	goto stop_iscsi_func;	1810	goto stop_iscsi_func;
1811		1811

drivers/scsi/qla2xxx/Kconfig+1−0

@@ -3,6 +3,7 @@ config SCSI_QLA_FC · 2 unmodified lines
3	depends on PCI && SCSI	3	depends on PCI && SCSI
4	depends on SCSI_FC_ATTRS	4	depends on SCSI_FC_ATTRS
5	select FW_LOADER	5	select FW_LOADER
		6	select BTREE
6	---help---	7	---help---
7	This qla2xxx driver supports all QLogic Fibre Channel	8	This qla2xxx driver supports all QLogic Fibre Channel
8	PCI and PCIe host adapters.	9	PCI and PCIe host adapters.

drivers/scsi/qla2xxx/qla_attr.c+1−3

 		    "Timer for the VP[%d] has stopped\n", vha->vp_idx);
 	}
-	BUG_ON(atomic_read(&vha->vref_count));
 	qla2x00_free_fcports(vha);
 	mutex_lock(&ha->vport_lock);
 	dma_free_coherent(&ha->pdev->dev, vha->gnl.size, vha->gnl.l,
 	    vha->gnl.ldma);
-	if (vha->qpair->vp_idx == vha->vp_idx) {
+	if (vha->qpair && vha->qpair->vp_idx == vha->vp_idx) {
 		if (qla2xxx_delete_qpair(vha, vha->qpair) != QLA_SUCCESS)
 			ql_log(ql_log_warn, vha, 0x7087,
 			    "Queue Pair delete failed.\n");

drivers/scsi/qla2xxx/qla_dbg.c+4−8

 	    "%-+5d  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F\n", size);
 	ql_dbg(level, vha, id,
 	    "----- -----------------------------------------------\n");
-	for (cnt = 0; cnt < size; cnt++, buf++) {
+	for (cnt = 0; cnt < size; cnt += 16) {
-		if (cnt % 16 == 0)
+		ql_dbg(level, vha, id, "%04x: ", cnt);
-			ql_dbg(level, vha, id, "%04x:", cnt & ~0xFU);
+		print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1,
-		printk(" %02x", *buf);
+			       buf + cnt, min(16U, size - cnt), false);
-		if (cnt % 16 == 15)
-			printk("\n");
 	}
-	if (cnt % 16 != 0)
-		printk("\n");
 }

drivers/scsi/qla2xxx/qla_dbg.h+1−0

@@ -348,6 +348,7 @@ ql_log_pci(uint32_t, struct pci_dev pdev, int32_t, const char fmt, ...); · 347 unmodified lines
348	#define ql_dbg_tgt 0x00004000 /* Target mode */	348	#define ql_dbg_tgt 0x00004000 /* Target mode */
349	#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */	349	#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
350	#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */	350	#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
		351	#define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
351		352
352	extern int qla27xx_dump_mpi_ram(struct qla_hw_data , uint32_t, uint32_t ,	353	extern int qla27xx_dump_mpi_ram(struct qla_hw_data , uint32_t, uint32_t ,
353	uint32_t, void **);	354	uint32_t, void **);

drivers/scsi/qla2xxx/qla_def.h+50−6

@@ -25,6 +25,7 @@ · 24 unmodified lines
25	#include <linux/firmware.h>	25	#include <linux/firmware.h>
26	#include <linux/aer.h>	26	#include <linux/aer.h>
27	#include <linux/mutex.h>	27	#include <linux/mutex.h>
		28	#include <linux/btree.h>
28		29
29	#include <scsi/scsi.h>	30	#include <scsi/scsi.h>
30	#include <scsi/scsi_host.h>	31	#include <scsi/scsi_host.h>
@@ -395,11 +396,15 @@ struct srb_iocb { · 364 unmodified lines
395	struct completion comp;	396	struct completion comp;
396	} abt;	397	} abt;
397	struct ct_arg ctarg;	398	struct ct_arg ctarg;
		399	#define MAX_IOCB_MB_REG 28
		400	#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
398	struct {	401	struct {
399	__le16 in_mb[28]; /* fr fw */	402	__le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
400	__le16 out_mb[28]; /* to fw */	403	__le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
401	void out, in;	404	void out, in;
402	dma_addr_t out_dma, in_dma;	405	dma_addr_t out_dma, in_dma;
		406	struct completion comp;
		407	int rc;
403	} mbx;	408	} mbx;
404	struct {	409	struct {
405	struct imm_ntfy_from_isp *ntfy;	410	struct imm_ntfy_from_isp *ntfy;
@@ -437,7 +442,7 @@ typedef struct srb { · 31 unmodified lines
437	uint32_t handle;	442	uint32_t handle;
438	uint16_t flags;	443	uint16_t flags;
439	uint16_t type;	444	uint16_t type;
440	char *name;	445	const char *name;
441	int iocbs;	446	int iocbs;
442	struct qla_qpair *qpair;	447	struct qla_qpair *qpair;
443	u32 gen1; /* scratch */	448	u32 gen1; /* scratch */
@@ -2300,6 +2305,8 @@ typedef struct fc_port { · 1856 unmodified lines
2300	struct ct_sns_desc ct_desc;	2305	struct ct_sns_desc ct_desc;
2301	enum discovery_state disc_state;	2306	enum discovery_state disc_state;
2302	enum login_state fw_login_state;	2307	enum login_state fw_login_state;
		2308	unsigned long plogi_nack_done_deadline;
		2309
2303	u32 login_gen, last_login_gen;	2310	u32 login_gen, last_login_gen;
2304	u32 rscn_gen, last_rscn_gen;	2311	u32 rscn_gen, last_rscn_gen;
2305	u32 chip_reset;	2312	u32 chip_reset;
@@ -3106,6 +3113,16 @@ struct qla_chip_state_84xx { · 800 unmodified lines
3106	uint32_t gold_fw_version;	3113	uint32_t gold_fw_version;
3107	};	3114	};
3108		3115
		3116	struct qla_dif_statistics {
		3117	uint64_t dif_input_bytes;
		3118	uint64_t dif_output_bytes;
		3119	uint64_t dif_input_requests;
		3120	uint64_t dif_output_requests;
		3121	uint32_t dif_guard_err;
		3122	uint32_t dif_ref_tag_err;
		3123	uint32_t dif_app_tag_err;
		3124	};
		3125
3109	struct qla_statistics {	3126	struct qla_statistics {
3110	uint32_t total_isp_aborts;	3127	uint32_t total_isp_aborts;
3111	uint64_t input_bytes;	3128	uint64_t input_bytes;
@@ -3118,6 +3135,8 @@ struct qla_statistics { · 6 unmodified lines
3118	uint32_t stat_max_pend_cmds;	3135	uint32_t stat_max_pend_cmds;
3119	uint32_t stat_max_qfull_cmds_alloc;	3136	uint32_t stat_max_qfull_cmds_alloc;
3120	uint32_t stat_max_qfull_cmds_dropped;	3137	uint32_t stat_max_qfull_cmds_dropped;
		3138
		3139	struct qla_dif_statistics qla_dif_stats;
3121	};	3140	};
3122		3141
3123	struct bidi_statistics {	3142	struct bidi_statistics {
@@ -3125,6 +3144,16 @@ struct bidi_statistics { · 1 unmodified line
3125	unsigned long long transfer_bytes;	3144	unsigned long long transfer_bytes;
3126	};	3145	};
3127		3146
		3147	struct qla_tc_param {
		3148	struct scsi_qla_host *vha;
		3149	uint32_t blk_sz;
		3150	uint32_t bufflen;
		3151	struct scatterlist *sg;
		3152	struct scatterlist *prot_sg;
		3153	struct crc_context *ctx;
		3154	uint8_t *ctx_dsd_alloced;
		3155	};
		3156
3128	/* Multi queue support */	3157	/* Multi queue support */
3129	#define MBC_INITIALIZE_MULTIQ 0x1f	3158	#define MBC_INITIALIZE_MULTIQ 0x1f
3130	#define QLA_QUE_PAGE 0X1000	3159	#define QLA_QUE_PAGE 0X1000
@@ -3272,6 +3301,8 @@ struct qlt_hw_data { · 141 unmodified lines
3272	uint8_t tgt_node_name[WWN_SIZE];	3301	uint8_t tgt_node_name[WWN_SIZE];
3273		3302
3274	struct dentry *dfs_tgt_sess;	3303	struct dentry *dfs_tgt_sess;
		3304	struct dentry *dfs_tgt_port_database;
		3305
3275	struct list_head q_full_list;	3306	struct list_head q_full_list;
3276	uint32_t num_pend_cmds;	3307	uint32_t num_pend_cmds;
3277	uint32_t num_qfull_cmds_alloc;	3308	uint32_t num_qfull_cmds_alloc;
@@ -3281,6 +3312,7 @@ struct qlt_hw_data { · 3 unmodified lines
3281	spinlock_t sess_lock;	3312	spinlock_t sess_lock;
3282	int rspq_vector_cpuid;	3313	int rspq_vector_cpuid;
3283	spinlock_t atio_lock ____cacheline_aligned;	3314	spinlock_t atio_lock ____cacheline_aligned;
		3315	struct btree_head32 host_map;
3284	};	3316	};
3285		3317
3286	#define MAX_QFULL_CMDS_ALLOC 8192	3318	#define MAX_QFULL_CMDS_ALLOC 8192
@@ -3290,6 +3322,10 @@ struct qlt_hw_data { · 3 unmodified lines
3290		3322
3291	#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */	3323	#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3292		3324
		3325	#define QLA_EARLY_LINKUP(_ha) \
		3326	((_ha->flags.n2n_ae \|\| _ha->flags.lip_ae) && \
		3327	_ha->flags.fw_started && !_ha->flags.fw_init_done)
		3328
3293	/*	3329	/*
3294	* Qlogic host adapter specific data structure.	3330	* Qlogic host adapter specific data structure.
3295	*/	3331	*/
@@ -3339,7 +3375,11 @@ struct qla_hw_data { · 43 unmodified lines
3339	uint32_t fawwpn_enabled:1;	3375	uint32_t fawwpn_enabled:1;
3340	uint32_t exlogins_enabled:1;	3376	uint32_t exlogins_enabled:1;
3341	uint32_t exchoffld_enabled:1;	3377	uint32_t exchoffld_enabled:1;
3342	/* 35 bits */	3378
		3379	uint32_t lip_ae:1;
		3380	uint32_t n2n_ae:1;
		3381	uint32_t fw_started:1;
		3382	uint32_t fw_init_done:1;
3343	} flags;	3383	} flags;
3344		3384
3345	/* This spinlock is used to protect "io transactions", you must	3385	/* This spinlock is used to protect "io transactions", you must
@@ -3432,7 +3472,6 @@ struct qla_hw_data { · 86 unmodified lines
3432	#define P2P_LOOP 3	3472	#define P2P_LOOP 3
3433	uint8_t interrupts_on;	3473	uint8_t interrupts_on;
3434	uint32_t isp_abort_cnt;	3474	uint32_t isp_abort_cnt;
3435
3436	#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532	3475	#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3437	#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432	3476	#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3438	#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001	3477	#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
@@ -3913,6 +3952,7 @@ typedef struct scsi_qla_host { · 474 unmodified lines
3913	struct list_head vp_fcports; /* list of fcports */	3952	struct list_head vp_fcports; /* list of fcports */
3914	struct list_head work_list;	3953	struct list_head work_list;
3915	spinlock_t work_lock;	3954	spinlock_t work_lock;
		3955	struct work_struct iocb_work;
3916		3956
3917	/* Commonly used flags and state information. */	3957	/* Commonly used flags and state information. */
3918	struct Scsi_Host *host;	3958	struct Scsi_Host *host;
@@ -4076,6 +4116,7 @@ typedef struct scsi_qla_host { · 157 unmodified lines
4076	/* Count of active session/fcport */	4116	/* Count of active session/fcport */
4077	int fcport_count;	4117	int fcport_count;
4078	wait_queue_head_t fcport_waitQ;	4118	wait_queue_head_t fcport_waitQ;
		4119	wait_queue_head_t vref_waitq;
4079	} scsi_qla_host_t;	4120	} scsi_qla_host_t;
4080		4121
4081	struct qla27xx_image_status {	4122	struct qla27xx_image_status {
@@ -4131,14 +4172,17 @@ struct qla2_sgx { · 49 unmodified lines
4131	mb(); \	4172	mb(); \
4132	if (__vha->flags.delete_progress) { \	4173	if (__vha->flags.delete_progress) { \
4133	atomic_dec(&__vha->vref_count); \	4174	atomic_dec(&__vha->vref_count); \
		4175	wake_up(&__vha->vref_waitq); \
4134	__bail = 1; \	4176	__bail = 1; \
4135	} else { \	4177	} else { \
4136	__bail = 0; \	4178	__bail = 0; \
4137	} \	4179	} \
4138	} while (0)	4180	} while (0)
4139		4181
4140	#define QLA_VHA_MARK_NOT_BUSY(__vha) \	4182	#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4141	atomic_dec(&__vha->vref_count); \	4183	atomic_dec(&__vha->vref_count); \
		4184	wake_up(&__vha->vref_waitq); \
		4185	} while (0) \
4142		4186
4143	#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \	4187	#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4144	atomic_inc(&__qpair->ref_count); \	4188	atomic_inc(&__qpair->ref_count); \

drivers/scsi/qla2xxx/qla_dfs.c+103−4

@@ -19,11 +19,11 @@ qla2x00_dfs_tgt_sess_show(struct seq_file s, void unused) · 18 unmodified lines
19	struct qla_hw_data *ha = vha->hw;	19	struct qla_hw_data *ha = vha->hw;
20	unsigned long flags;	20	unsigned long flags;
21	struct fc_port *sess = NULL;	21	struct fc_port *sess = NULL;
22	struct qla_tgt *tgt= vha->vha_tgt.qla_tgt;	22	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
23		23
24	seq_printf(s, "%s\n",vha->host_str);	24	seq_printf(s, "%s\n", vha->host_str);
25	if (tgt) {	25	if (tgt) {
26	seq_printf(s, "Port ID Port Name Handle\n");	26	seq_puts(s, "Port ID Port Name Handle\n");
27		27
28	spin_lock_irqsave(&ha->tgt.sess_lock, flags);	28	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
29	list_for_each_entry(sess, &vha->vp_fcports, list)	29	list_for_each_entry(sess, &vha->vp_fcports, list)
@@ -44,7 +44,6 @@ qla2x00_dfs_tgt_sess_open(struct inode inode, struct file file) · 14 unmodified lines
44	return single_open(file, qla2x00_dfs_tgt_sess_show, vha);	44	return single_open(file, qla2x00_dfs_tgt_sess_show, vha);
45	}	45	}
46		46
47
48	static const struct file_operations dfs_tgt_sess_ops = {	47	static const struct file_operations dfs_tgt_sess_ops = {
49	.open = qla2x00_dfs_tgt_sess_open,	48	.open = qla2x00_dfs_tgt_sess_open,
50	.read = seq_read,	49	.read = seq_read,
@@ -52,6 +51,78 @@ static const struct file_operations dfs_tgt_sess_ops = { · 1 unmodified line
52	.release = single_release,	51	.release = single_release,
53	};	52	};
54		53
		54	static int
		55	qla2x00_dfs_tgt_port_database_show(struct seq_file s, void unused)
		56	{
		57	scsi_qla_host_t *vha = s->private;
		58	struct qla_hw_data *ha = vha->hw;
		59	struct gid_list_info *gid_list;
		60	dma_addr_t gid_list_dma;
		61	fc_port_t fc_port;
		62	char *id_iter;
		63	int rc, i;
		64	uint16_t entries, loop_id;
		65	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
		66
		67	seq_printf(s, "%s\n", vha->host_str);
		68	if (tgt) {
		69	gid_list = dma_alloc_coherent(&ha->pdev->dev,
		70	qla2x00_gid_list_size(ha),
		71	&gid_list_dma, GFP_KERNEL);
		72	if (!gid_list) {
		73	ql_dbg(ql_dbg_user, vha, 0x705c,
		74	"DMA allocation failed for %u\n",
		75	qla2x00_gid_list_size(ha));
		76	return 0;
		77	}
		78
		79	rc = qla24xx_gidlist_wait(vha, gid_list, gid_list_dma,
		80	&entries);
		81	if (rc != QLA_SUCCESS)
		82	goto out_free_id_list;
		83
		84	id_iter = (char *)gid_list;
		85
		86	seq_puts(s, "Port Name Port ID Loop ID\n");
		87
		88	for (i = 0; i < entries; i++) {
		89	struct gid_list_info *gid =
		90	(struct gid_list_info *)id_iter;
		91	loop_id = le16_to_cpu(gid->loop_id);
		92	memset(&fc_port, 0, sizeof(fc_port_t));
		93
		94	fc_port.loop_id = loop_id;
		95
		96	rc = qla24xx_gpdb_wait(vha, &fc_port, 0);
		97	seq_printf(s, "%8phC %02x%02x%02x %d\n",
		98	fc_port.port_name, fc_port.d_id.b.domain,
		99	fc_port.d_id.b.area, fc_port.d_id.b.al_pa,
		100	fc_port.loop_id);
		101	id_iter += ha->gid_list_info_size;
		102	}
		103	out_free_id_list:
		104	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
		105	gid_list, gid_list_dma);
		106	}
		107
		108	return 0;
		109	}
		110
		111	static int
		112	qla2x00_dfs_tgt_port_database_open(struct inode inode, struct file file)
		113	{
		114	scsi_qla_host_t *vha = inode->i_private;
		115
		116	return single_open(file, qla2x00_dfs_tgt_port_database_show, vha);
		117	}
		118
		119	static const struct file_operations dfs_tgt_port_database_ops = {
		120	.open = qla2x00_dfs_tgt_port_database_open,
		121	.read = seq_read,
		122	.llseek = seq_lseek,
		123	.release = single_release,
		124	};
		125
55	static int	126	static int
56	qla_dfs_fw_resource_cnt_show(struct seq_file s, void unused)	127	qla_dfs_fw_resource_cnt_show(struct seq_file s, void unused)
57	{	128	{
@@ -114,6 +185,21 @@ qla_dfs_tgt_counters_show(struct seq_file s, void unused) · 56 unmodified lines
114	seq_printf(s, "num Q full sent = %lld\n",	185	seq_printf(s, "num Q full sent = %lld\n",
115	vha->tgt_counters.num_q_full_sent);	186	vha->tgt_counters.num_q_full_sent);
116		187
		188	/* DIF stats */
		189	seq_printf(s, "DIF Inp Bytes = %lld\n",
		190	vha->qla_stats.qla_dif_stats.dif_input_bytes);
		191	seq_printf(s, "DIF Outp Bytes = %lld\n",
		192	vha->qla_stats.qla_dif_stats.dif_output_bytes);
		193	seq_printf(s, "DIF Inp Req = %lld\n",
		194	vha->qla_stats.qla_dif_stats.dif_input_requests);
		195	seq_printf(s, "DIF Outp Req = %lld\n",
		196	vha->qla_stats.qla_dif_stats.dif_output_requests);
		197	seq_printf(s, "DIF Guard err = %d\n",
		198	vha->qla_stats.qla_dif_stats.dif_guard_err);
		199	seq_printf(s, "DIF Ref tag err = %d\n",
		200	vha->qla_stats.qla_dif_stats.dif_ref_tag_err);
		201	seq_printf(s, "DIF App tag err = %d\n",
		202	vha->qla_stats.qla_dif_stats.dif_app_tag_err);
117	return 0;	203	return 0;
118	}	204	}
119		205
@@ -281,6 +367,14 @@ create_nodes: · 161 unmodified lines
281	goto out;	367	goto out;
282	}	368	}
283		369
		370	ha->tgt.dfs_tgt_port_database = debugfs_create_file("tgt_port_database",
		371	S_IRUSR, ha->dfs_dir, vha, &dfs_tgt_port_database_ops);
		372	if (!ha->tgt.dfs_tgt_port_database) {
		373	ql_log(ql_log_warn, vha, 0xffff,
		374	"Unable to create debugFS tgt_port_database node.\n");
		375	goto out;
		376	}
		377
284	ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, vha,	378	ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, vha,
285	&dfs_fce_ops);	379	&dfs_fce_ops);
286	if (!ha->dfs_fce) {	380	if (!ha->dfs_fce) {
@@ -311,6 +405,11 @@ qla2x00_dfs_remove(scsi_qla_host_t *vha) · 24 unmodified lines
311	ha->tgt.dfs_tgt_sess = NULL;	405	ha->tgt.dfs_tgt_sess = NULL;
312	}	406	}
313		407
		408	if (ha->tgt.dfs_tgt_port_database) {
		409	debugfs_remove(ha->tgt.dfs_tgt_port_database);
		410	ha->tgt.dfs_tgt_port_database = NULL;
		411	}
		412
314	if (ha->dfs_fw_resource_cnt) {	413	if (ha->dfs_fw_resource_cnt) {
315	debugfs_remove(ha->dfs_fw_resource_cnt);	414	debugfs_remove(ha->dfs_fw_resource_cnt);
316	ha->dfs_fw_resource_cnt = NULL;	415	ha->dfs_fw_resource_cnt = NULL;

drivers/scsi/qla2xxx/qla_gbl.h+14−4

 void qla2x00_handle_login_done_event(struct scsi_qla_host *, fc_port_t *,
 	uint16_t *);
 int qla24xx_post_gnl_work(struct scsi_qla_host *, fc_port_t *);
+int qla24xx_async_abort_cmd(srb_t *);
 /*
  * Global Functions in qla_mid.c source file.
 extern void *qla2x00_alloc_iocbs(scsi_qla_host_t *, srb_t *);
 extern int qla2x00_issue_marker(scsi_qla_host_t *, int);
 extern int qla24xx_walk_and_build_sglist_no_difb(struct qla_hw_data *, srb_t *,
-	uint32_t *, uint16_t, struct qla_tgt_cmd *);
+	uint32_t *, uint16_t, struct qla_tc_param *);
 extern int qla24xx_walk_and_build_sglist(struct qla_hw_data *, srb_t *,
-	uint32_t *, uint16_t, struct qla_tgt_cmd *);
+	uint32_t *, uint16_t, struct qla_tc_param *);
 extern int qla24xx_walk_and_build_prot_sglist(struct qla_hw_data *, srb_t *,
-	uint32_t *, uint16_t, struct qla_tgt_cmd *);
+	uint32_t *, uint16_t, struct qla_tc_param *);
 extern int qla24xx_get_one_block_sg(uint32_t, struct qla2_sgx *, uint32_t *);
 extern int qla24xx_configure_prot_mode(srb_t *, uint16_t *);
 extern int qla24xx_build_scsi_crc_2_iocbs(srb_t *,
 extern int
 qla24xx_get_isp_stats(scsi_qla_host_t *, struct link_statistics *,
-    dma_addr_t, uint);
+    dma_addr_t, uint16_t);
 extern int qla24xx_abort_command(srb_t *);
 extern int qla24xx_async_abort_command(srb_t *);
 extern int
 qla26xx_dport_diagnostics(scsi_qla_host_t *, void *, uint, uint);
+int qla24xx_send_mb_cmd(struct scsi_qla_host *, mbx_cmd_t *);
+int qla24xx_gpdb_wait(struct scsi_qla_host *, fc_port_t *, u8);
+int qla24xx_gidlist_wait(struct scsi_qla_host *, void *, dma_addr_t,
+    uint16_t *);
+int __qla24xx_parse_gpdb(struct scsi_qla_host *, fc_port_t *,
+	struct port_database_24xx *);
 /*
  * Global Function Prototypes in qla_isr.c source file.
  */
 	uint64_t wwn, port_id_t port_id, uint16_t loop_id, struct fc_port **);
 void qla24xx_delete_sess_fn(struct work_struct *);
 void qlt_unknown_atio_work_fn(struct work_struct *);
+void qlt_update_host_map(struct scsi_qla_host *, port_id_t);
+void qlt_remove_target_resources(struct qla_hw_data *);
 #endif /* _QLA_GBL_H */

drivers/scsi/qla2xxx/qla_init.c+31−54

@@ -629,7 +629,6 @@ void qla24xx_async_gpdb_sp_done(void *s, int res) · 628 unmodified lines
629	struct srb *sp = s;	629	struct srb *sp = s;
630	struct scsi_qla_host *vha = sp->vha;	630	struct scsi_qla_host *vha = sp->vha;
631	struct qla_hw_data *ha = vha->hw;	631	struct qla_hw_data *ha = vha->hw;
632	uint64_t zero = 0;
633	struct port_database_24xx *pd;	632	struct port_database_24xx *pd;
634	fc_port_t *fcport = sp->fcport;	633	fc_port_t *fcport = sp->fcport;
635	u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;	634	u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
@@ -649,48 +648,7 @@ void qla24xx_async_gpdb_sp_done(void *s, int res) · 13 unmodified lines
649		648
650	pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;	649	pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
651		650
652	/* Check for logged in state. */	651	rval = __qla24xx_parse_gpdb(vha, fcport, pd);
653	if (pd->current_login_state != PDS_PRLI_COMPLETE &&
654	pd->last_login_state != PDS_PRLI_COMPLETE) {
655	ql_dbg(ql_dbg_mbx, vha, 0xffff,
656	"Unable to verify login-state (%x/%x) for "
657	"loop_id %x.\n", pd->current_login_state,
658	pd->last_login_state, fcport->loop_id);
659	rval = QLA_FUNCTION_FAILED;
660	goto gpd_error_out;
661	}
662
663	if (fcport->loop_id == FC_NO_LOOP_ID \|\|
664	(memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
665	memcmp(fcport->port_name, pd->port_name, 8))) {
666	/* We lost the device mid way. */
667	rval = QLA_NOT_LOGGED_IN;
668	goto gpd_error_out;
669	}
670
671	/* Names are little-endian. */
672	memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
673
674	/* Get port_id of device. */
675	fcport->d_id.b.domain = pd->port_id[0];
676	fcport->d_id.b.area = pd->port_id[1];
677	fcport->d_id.b.al_pa = pd->port_id[2];
678	fcport->d_id.b.rsvd_1 = 0;
679
680	/* If not target must be initiator or unknown type. */
681	if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
682	fcport->port_type = FCT_INITIATOR;
683	else
684	fcport->port_type = FCT_TARGET;
685
686	/* Passback COS information. */
687	fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
688	FC_COS_CLASS2 : FC_COS_CLASS3;
689
690	if (pd->prli_svc_param_word_3[0] & BIT_7) {
691	fcport->flags \|= FCF_CONF_COMP_SUPPORTED;
692	fcport->conf_compl_supported = 1;
693	}
694		652
695	gpd_error_out:	653	gpd_error_out:
696	memset(&ea, 0, sizeof(ea));	654	memset(&ea, 0, sizeof(ea));
@@ -876,10 +834,14 @@ int qla24xx_fcport_handle_login(struct scsi_qla_host vha, fc_port_t fcport) · 179 unmodified lines
876	fcport->login_retry--;	834	fcport->login_retry--;
877		835
878	if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) \|\|	836	if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) \|\|
879	(fcport->fw_login_state == DSC_LS_PLOGI_COMP) \|\|
880	(fcport->fw_login_state == DSC_LS_PRLI_PEND))	837	(fcport->fw_login_state == DSC_LS_PRLI_PEND))
881	return 0;	838	return 0;
882		839
		840	if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
		841	if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
		842	return 0;
		843	}
		844
883	/* for pure Target Mode. Login will not be initiated */	845	/* for pure Target Mode. Login will not be initiated */
884	if (vha->host->active_mode == MODE_TARGET)	846	if (vha->host->active_mode == MODE_TARGET)
885	return 0;	847	return 0;
@@ -1041,10 +1003,14 @@ void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, · 155 unmodified lines
1041	fcport->flags);	1003	fcport->flags);
1042		1004
1043	if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) \|\|	1005	if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) \|\|
1044	(fcport->fw_login_state == DSC_LS_PLOGI_COMP) \|\|
1045	(fcport->fw_login_state == DSC_LS_PRLI_PEND))	1006	(fcport->fw_login_state == DSC_LS_PRLI_PEND))
1046	return;	1007	return;
1047		1008
		1009	if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
		1010	if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
		1011	return;
		1012	}
		1013
1048	if (fcport->flags & FCF_ASYNC_SENT) {	1014	if (fcport->flags & FCF_ASYNC_SENT) {
1049	fcport->login_retry++;	1015	fcport->login_retry++;
1050	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);	1016	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
@@ -1258,7 +1224,7 @@ qla24xx_abort_sp_done(void *ptr, int res) · 207 unmodified lines
1258	complete(&abt->u.abt.comp);	1224	complete(&abt->u.abt.comp);
1259	}	1225	}
1260		1226
1261	static int	1227	int
1262	qla24xx_async_abort_cmd(srb_t *cmd_sp)	1228	qla24xx_async_abort_cmd(srb_t *cmd_sp)
1263	{	1229	{
1264	scsi_qla_host_t *vha = cmd_sp->vha;	1230	scsi_qla_host_t *vha = cmd_sp->vha;
@@ -3212,6 +3178,7 @@ next_check: · 1947 unmodified lines
3212	} else {	3178	} else {
3213	ql_dbg(ql_dbg_init, vha, 0x00d3,	3179	ql_dbg(ql_dbg_init, vha, 0x00d3,
3214	"Init Firmware -- success.\n");	3180	"Init Firmware -- success.\n");
		3181	ha->flags.fw_started = 1;
3215	}	3182	}
3216		3183
3217	return (rval);	3184	return (rval);
@@ -3374,8 +3341,8 @@ qla2x00_configure_hba(scsi_qla_host_t *vha) · 156 unmodified lines
3374	uint8_t domain;	3341	uint8_t domain;
3375	char connect_type[22];	3342	char connect_type[22];
3376	struct qla_hw_data *ha = vha->hw;	3343	struct qla_hw_data *ha = vha->hw;
3377	unsigned long flags;
3378	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);	3344	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
		3345	port_id_t id;
3379		3346
3380	/* Get host addresses. */	3347	/* Get host addresses. */
3381	rval = qla2x00_get_adapter_id(vha,	3348	rval = qla2x00_get_adapter_id(vha,
@@ -3453,13 +3420,11 @@ qla2x00_configure_hba(scsi_qla_host_t *vha) · 71 unmodified lines
3453		3420
3454	/* Save Host port and loop ID. */	3421	/* Save Host port and loop ID. */
3455	/* byte order - Big Endian */	3422	/* byte order - Big Endian */
3456	vha->d_id.b.domain = domain;	3423	id.b.domain = domain;
3457	vha->d_id.b.area = area;	3424	id.b.area = area;
3458	vha->d_id.b.al_pa = al_pa;	3425	id.b.al_pa = al_pa;
3459		3426	id.b.rsvd_1 = 0;
3460	spin_lock_irqsave(&ha->vport_slock, flags);	3427	qlt_update_host_map(vha, id);
3461	qlt_update_vp_map(vha, SET_AL_PA);
3462	spin_unlock_irqrestore(&ha->vport_slock, flags);
3463		3428
3464	if (!vha->flags.init_done)	3429	if (!vha->flags.init_done)
3465	ql_log(ql_log_info, vha, 0x2010,	3430	ql_log(ql_log_info, vha, 0x2010,
@@ -4036,6 +4001,7 @@ qla2x00_configure_loop(scsi_qla_host_t *vha) · 570 unmodified lines
4036	atomic_set(&vha->loop_state, LOOP_READY);	4001	atomic_set(&vha->loop_state, LOOP_READY);
4037	ql_dbg(ql_dbg_disc, vha, 0x2069,	4002	ql_dbg(ql_dbg_disc, vha, 0x2069,
4038	"LOOP READY.\n");	4003	"LOOP READY.\n");
		4004	ha->flags.fw_init_done = 1;
4039		4005
4040	/*	4006	/*
4041	* Process any ATIO queue entries that came in	4007	* Process any ATIO queue entries that came in
@@ -5148,6 +5114,7 @@ qla2x00_update_fcports(scsi_qla_host_t *base_vha) · 1106 unmodified lines
5148	}	5114	}
5149	}	5115	}
5150	atomic_dec(&vha->vref_count);	5116	atomic_dec(&vha->vref_count);
		5117	wake_up(&vha->vref_waitq);
5151	}	5118	}
5152	spin_unlock_irqrestore(&ha->vport_slock, flags);	5119	spin_unlock_irqrestore(&ha->vport_slock, flags);
5153	}	5120	}
@@ -5526,6 +5493,11 @@ qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) · 372 unmodified lines
5526	if (!(IS_P3P_TYPE(ha)))	5493	if (!(IS_P3P_TYPE(ha)))
5527	ha->isp_ops->reset_chip(vha);	5494	ha->isp_ops->reset_chip(vha);
5528		5495
		5496	ha->flags.n2n_ae = 0;
		5497	ha->flags.lip_ae = 0;
		5498	ha->current_topology = 0;
		5499	ha->flags.fw_started = 0;
		5500	ha->flags.fw_init_done = 0;
5529	ha->chip_reset++;	5501	ha->chip_reset++;
5530		5502
5531	atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);	5503	atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
@@ -6802,6 +6774,8 @@ qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) · 1270 unmodified lines
6802	return;	6774	return;
6803	if (!ha->fw_major_version)	6775	if (!ha->fw_major_version)
6804	return;	6776	return;
		6777	if (!ha->flags.fw_started)
		6778	return;
6805		6779
6806	ret = qla2x00_stop_firmware(vha);	6780	ret = qla2x00_stop_firmware(vha);
6807	for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&	6781	for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
@@ -6815,6 +6789,9 @@ qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) · 7 unmodified lines
6815	"Attempting retry of stop-firmware command.\n");	6789	"Attempting retry of stop-firmware command.\n");
6816	ret = qla2x00_stop_firmware(vha);	6790	ret = qla2x00_stop_firmware(vha);
6817	}	6791	}
		6792
		6793	ha->flags.fw_started = 0;
		6794	ha->flags.fw_init_done = 0;
6818	}	6795	}
6819		6796
6820	int	6797	int

drivers/scsi/qla2xxx/qla_iocb.c+6−7

@@ -889,7 +889,7 @@ qla24xx_get_one_block_sg(uint32_t blk_sz, struct qla2_sgx *sgx, · 888 unmodified lines
889		889
890	int	890	int
891	qla24xx_walk_and_build_sglist_no_difb(struct qla_hw_data ha, srb_t sp,	891	qla24xx_walk_and_build_sglist_no_difb(struct qla_hw_data ha, srb_t sp,
892	uint32_t dsd, uint16_t tot_dsds, struct qla_tgt_cmd tc)	892	uint32_t dsd, uint16_t tot_dsds, struct qla_tc_param tc)
893	{	893	{
894	void *next_dsd;	894	void *next_dsd;
895	uint8_t avail_dsds = 0;	895	uint8_t avail_dsds = 0;
@@ -898,7 +898,6 @@ qla24xx_walk_and_build_sglist_no_difb(struct qla_hw_data ha, srb_t sp, · 2 unmodified lines
898	struct scatterlist *sg_prot;	898	struct scatterlist *sg_prot;
899	uint32_t *cur_dsd = dsd;	899	uint32_t *cur_dsd = dsd;
900	uint16_t used_dsds = tot_dsds;	900	uint16_t used_dsds = tot_dsds;
901
902	uint32_t prot_int; /* protection interval */	901	uint32_t prot_int; /* protection interval */
903	uint32_t partial;	902	uint32_t partial;
904	struct qla2_sgx sgx;	903	struct qla2_sgx sgx;
@@ -966,7 +965,7 @@ alloc_and_fill: · 61 unmodified lines
966	} else {	965	} else {
967	list_add_tail(&dsd_ptr->list,	966	list_add_tail(&dsd_ptr->list,
968	&(tc->ctx->dsd_list));	967	&(tc->ctx->dsd_list));
969	tc->ctx_dsd_alloced = 1;	968	*tc->ctx_dsd_alloced = 1;
970	}	969	}
971		970
972		971
@@ -1005,7 +1004,7 @@ alloc_and_fill: · 32 unmodified lines
1005		1004
1006	int	1005	int
1007	qla24xx_walk_and_build_sglist(struct qla_hw_data ha, srb_t sp, uint32_t *dsd,	1006	qla24xx_walk_and_build_sglist(struct qla_hw_data ha, srb_t sp, uint32_t *dsd,
1008	uint16_t tot_dsds, struct qla_tgt_cmd *tc)	1007	uint16_t tot_dsds, struct qla_tc_param *tc)
1009	{	1008	{
1010	void *next_dsd;	1009	void *next_dsd;
1011	uint8_t avail_dsds = 0;	1010	uint8_t avail_dsds = 0;
@@ -1066,7 +1065,7 @@ qla24xx_walk_and_build_sglist(struct qla_hw_data ha, srb_t sp, uint32_t *dsd, · 54 unmodified lines
1066	} else {	1065	} else {
1067	list_add_tail(&dsd_ptr->list,	1066	list_add_tail(&dsd_ptr->list,
1068	&(tc->ctx->dsd_list));	1067	&(tc->ctx->dsd_list));
1069	tc->ctx_dsd_alloced = 1;	1068	*tc->ctx_dsd_alloced = 1;
1070	}	1069	}
1071		1070
1072	/* add new list to cmd iocb or last list */	1071	/* add new list to cmd iocb or last list */
@@ -1092,7 +1091,7 @@ qla24xx_walk_and_build_sglist(struct qla_hw_data ha, srb_t sp, uint32_t *dsd, · 19 unmodified lines
1092		1091
1093	int	1092	int
1094	qla24xx_walk_and_build_prot_sglist(struct qla_hw_data ha, srb_t sp,	1093	qla24xx_walk_and_build_prot_sglist(struct qla_hw_data ha, srb_t sp,
1095	uint32_t dsd, uint16_t tot_dsds, struct qla_tgt_cmd tc)	1094	uint32_t dsd, uint16_t tot_dsds, struct qla_tc_param tc)
1096	{	1095	{
1097	void *next_dsd;	1096	void *next_dsd;
1098	uint8_t avail_dsds = 0;	1097	uint8_t avail_dsds = 0;
@@ -1158,7 +1157,7 @@ qla24xx_walk_and_build_prot_sglist(struct qla_hw_data ha, srb_t sp, · 59 unmodified lines
1158	} else {	1157	} else {
1159	list_add_tail(&dsd_ptr->list,	1158	list_add_tail(&dsd_ptr->list,
1160	&(tc->ctx->dsd_list));	1159	&(tc->ctx->dsd_list));
1161	tc->ctx_dsd_alloced = 1;	1160	*tc->ctx_dsd_alloced = 1;
1162	}	1161	}
1163		1162
1164	/* add new list to cmd iocb or last list */	1163	/* add new list to cmd iocb or last list */

drivers/scsi/qla2xxx/qla_isr.c+33−8

 		    "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
 		ha->isp_ops->fw_dump(vha, 1);
+		ha->flags.fw_init_done = 0;
+		ha->flags.fw_started = 0;
 		if (IS_FWI2_CAPABLE(ha)) {
 			if (mb[1] == 0 && mb[2] == 0) {
 		break;
 	case MBA_LIP_OCCURRED:		/* Loop Initialization Procedure */
+		ha->flags.lip_ae = 1;
+		ha->flags.n2n_ae = 0;
 		ql_dbg(ql_dbg_async, vha, 0x5009,
 		    "LIP occurred (%x).\n", mb[1]);
 		break;
 	case MBA_LOOP_DOWN:		/* Loop Down Event */
+		ha->flags.n2n_ae = 0;
+		ha->flags.lip_ae = 0;
+		ha->current_topology = 0;
 		mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
 			? RD_REG_WORD(&reg24->mailbox4) : 0;
 		mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
 	/* case MBA_DCBX_COMPLETE: */
 	case MBA_POINT_TO_POINT:	/* Point-to-Point */
+		ha->flags.lip_ae = 0;
+		ha->flags.n2n_ae = 1;
 		if (IS_QLA2100(ha))
 			break;
 		QLA_LOGIO_LOGIN_RETRIED : 0;
 	if (logio->entry_status) {
 		ql_log(ql_log_warn, fcport->vha, 0x5034,
-		    "Async-%s error entry - hdl=%x"
+		    "Async-%s error entry - %8phC hdl=%x"
 		    "portid=%02x%02x%02x entry-status=%x.\n",
-		    type, sp->handle, fcport->d_id.b.domain,
+		    type, fcport->port_name, sp->handle, fcport->d_id.b.domain,
 		    fcport->d_id.b.area, fcport->d_id.b.al_pa,
 		    logio->entry_status);
 		ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
 	if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
 		ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
-		    "Async-%s complete - hdl=%x portid=%02x%02x%02x "
+		    "Async-%s complete - %8phC hdl=%x portid=%02x%02x%02x "
-		    "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
+		    "iop0=%x.\n", type, fcport->port_name, sp->handle,
+		    fcport->d_id.b.domain,
 		    fcport->d_id.b.area, fcport->d_id.b.al_pa,
 		    le32_to_cpu(logio->io_parameter[0]));
 	case LSC_SCODE_NPORT_USED:
 		data[0] = MBS_LOOP_ID_USED;
 		break;
+	case LSC_SCODE_CMD_FAILED:
+		if (iop[1] == 0x0606) {
+			/*
+			 * PLOGI/PRLI Completed. We must have Recv PLOGI/PRLI,
+			 * Target side acked.
+			 */
+			data[0] = MBS_COMMAND_COMPLETE;
+			goto logio_done;
+		}
+		data[0] = MBS_COMMAND_ERROR;
+		break;
 	case LSC_SCODE_NOXCB:
 		vha->hw->exch_starvation++;
 		if (vha->hw->exch_starvation > 5) {
 	}
 	ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
-	    "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
+	    "Async-%s failed - %8phC hdl=%x portid=%02x%02x%02x comp=%x "
-	    "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
+	    "iop0=%x iop1=%x.\n", type, fcport->port_name,
+		sp->handle, fcport->d_id.b.domain,
 	    fcport->d_id.b.area, fcport->d_id.b.al_pa,
 	    le16_to_cpu(logio->comp_status),
 	    le32_to_cpu(logio->io_parameter[0]),
 		return;
 	abt = &sp->u.iocb_cmd;
-	abt->u.abt.comp_status = le32_to_cpu(pkt->nport_handle);
+	abt->u.abt.comp_status = le16_to_cpu(pkt->nport_handle);
 	sp->done(sp, 0);
 }
 	struct sts_entry_24xx *pkt;
 	struct qla_hw_data *ha = vha->hw;
-	if (!vha->flags.online)
+	if (!ha->flags.fw_started)
 		return;
 	while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {

drivers/scsi/qla2xxx/qla_mbx.c+268−36

@@ -10,6 +10,28 @@ · 9 unmodified lines
10	#include <linux/delay.h>	10	#include <linux/delay.h>
11	#include <linux/gfp.h>	11	#include <linux/gfp.h>
12		12
		13	static struct mb_cmd_name {
		14	uint16_t cmd;
		15	const char *str;
		16	} mb_str[] = {
		17	{MBC_GET_PORT_DATABASE, "GPDB"},
		18	{MBC_GET_ID_LIST, "GIDList"},
		19	{MBC_GET_LINK_PRIV_STATS, "Stats"},
		20	};
		21
		22	static const char *mb_to_str(uint16_t cmd)
		23	{
		24	int i;
		25	struct mb_cmd_name *e;
		26
		27	for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
		28	e = mb_str + i;
		29	if (cmd == e->cmd)
		30	return e->str;
		31	}
		32	return "unknown";
		33	}
		34
13	static struct rom_cmd {	35	static struct rom_cmd {
14	uint16_t cmd;	36	uint16_t cmd;
15	} rom_cmds[] = {	37	} rom_cmds[] = {
@@ -2818,7 +2840,7 @@ qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, · 2802 unmodified lines
2818		2840
2819	int	2841	int
2820	qla24xx_get_isp_stats(scsi_qla_host_t vha, struct link_statistics stats,	2842	qla24xx_get_isp_stats(scsi_qla_host_t vha, struct link_statistics stats,
2821	dma_addr_t stats_dma, uint options)	2843	dma_addr_t stats_dma, uint16_t options)
2822	{	2844	{
2823	int rval;	2845	int rval;
2824	mbx_cmd_t mc;	2846	mbx_cmd_t mc;
@@ -2828,19 +2850,17 @@ qla24xx_get_isp_stats(scsi_qla_host_t vha, struct link_statistics stats, · 3 unmodified lines
2828	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,	2850	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2829	"Entered %s.\n", __func__);	2851	"Entered %s.\n", __func__);
2830		2852
2831	mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;	2853	memset(&mc, 0, sizeof(mc));
2832	mcp->mb[2] = MSW(stats_dma);	2854	mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
2833	mcp->mb[3] = LSW(stats_dma);	2855	mc.mb[2] = MSW(stats_dma);
2834	mcp->mb[6] = MSW(MSD(stats_dma));	2856	mc.mb[3] = LSW(stats_dma);
2835	mcp->mb[7] = LSW(MSD(stats_dma));	2857	mc.mb[6] = MSW(MSD(stats_dma));
2836	mcp->mb[8] = sizeof(struct link_statistics) / 4;	2858	mc.mb[7] = LSW(MSD(stats_dma));
2837	mcp->mb[9] = vha->vp_idx;	2859	mc.mb[8] = sizeof(struct link_statistics) / 4;
2838	mcp->mb[10] = options;	2860	mc.mb[9] = cpu_to_le16(vha->vp_idx);
2839	mcp->out_mb = MBX_10\|MBX_9\|MBX_8\|MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_0;	2861	mc.mb[10] = cpu_to_le16(options);
2840	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;	2862
2841	mcp->tov = MBX_TOV_SECONDS;	2863	rval = qla24xx_send_mb_cmd(vha, &mc);
2842	mcp->flags = IOCTL_CMD;
2843	rval = qla2x00_mailbox_command(vha, mcp);
2844		2864
2845	if (rval == QLA_SUCCESS) {	2865	if (rval == QLA_SUCCESS) {
2846	if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {	2866	if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
@@ -3603,6 +3623,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, · 756 unmodified lines
3603	scsi_qla_host_t *vp = NULL;	3623	scsi_qla_host_t *vp = NULL;
3604	unsigned long flags;	3624	unsigned long flags;
3605	int found;	3625	int found;
		3626	port_id_t id;
3606		3627
3607	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,	3628	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3608	"Entered %s.\n", __func__);	3629	"Entered %s.\n", __func__);
@@ -3610,28 +3631,27 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, · 1 unmodified line
3610	if (rptid_entry->entry_status != 0)	3631	if (rptid_entry->entry_status != 0)
3611	return;	3632	return;
3612		3633
		3634	id.b.domain = rptid_entry->port_id[2];
		3635	id.b.area = rptid_entry->port_id[1];
		3636	id.b.al_pa = rptid_entry->port_id[0];
		3637	id.b.rsvd_1 = 0;
		3638
3613	if (rptid_entry->format == 0) {	3639	if (rptid_entry->format == 0) {
3614	/* loop */	3640	/* loop */
3615	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,	3641	ql_dbg(ql_dbg_async, vha, 0x10b7,
3616	"Format 0 : Number of VPs setup %d, number of "	3642	"Format 0 : Number of VPs setup %d, number of "
3617	"VPs acquired %d.\n", rptid_entry->vp_setup,	3643	"VPs acquired %d.\n", rptid_entry->vp_setup,
3618	rptid_entry->vp_acquired);	3644	rptid_entry->vp_acquired);
3619	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,	3645	ql_dbg(ql_dbg_async, vha, 0x10b8,
3620	"Primary port id %02x%02x%02x.\n",	3646	"Primary port id %02x%02x%02x.\n",
3621	rptid_entry->port_id[2], rptid_entry->port_id[1],	3647	rptid_entry->port_id[2], rptid_entry->port_id[1],
3622	rptid_entry->port_id[0]);	3648	rptid_entry->port_id[0]);
3623		3649
3624	vha->d_id.b.domain = rptid_entry->port_id[2];	3650	qlt_update_host_map(vha, id);
3625	vha->d_id.b.area = rptid_entry->port_id[1];
3626	vha->d_id.b.al_pa = rptid_entry->port_id[0];
3627
3628	spin_lock_irqsave(&ha->vport_slock, flags);
3629	qlt_update_vp_map(vha, SET_AL_PA);
3630	spin_unlock_irqrestore(&ha->vport_slock, flags);
3631		3651
3632	} else if (rptid_entry->format == 1) {	3652	} else if (rptid_entry->format == 1) {
3633	/* fabric */	3653	/* fabric */
3634	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,	3654	ql_dbg(ql_dbg_async, vha, 0x10b9,
3635	"Format 1: VP[%d] enabled - status %d - with "	3655	"Format 1: VP[%d] enabled - status %d - with "
3636	"port id %02x%02x%02x.\n", rptid_entry->vp_idx,	3656	"port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3637	rptid_entry->vp_status,	3657	rptid_entry->vp_status,
@@ -3653,12 +3673,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, · 15 unmodified lines
3653	WWN_SIZE);	3673	WWN_SIZE);
3654	}	3674	}
3655		3675
3656	vha->d_id.b.domain = rptid_entry->port_id[2];	3676	qlt_update_host_map(vha, id);
3657	vha->d_id.b.area = rptid_entry->port_id[1];
3658	vha->d_id.b.al_pa = rptid_entry->port_id[0];
3659	spin_lock_irqsave(&ha->vport_slock, flags);
3660	qlt_update_vp_map(vha, SET_AL_PA);
3661	spin_unlock_irqrestore(&ha->vport_slock, flags);
3662	}	3677	}
3663		3678
3664	fc_host_port_name(vha->host) =	3679	fc_host_port_name(vha->host) =
@@ -3694,12 +3709,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, · 29 unmodified lines
3694	if (!found)	3709	if (!found)
3695	return;	3710	return;
3696		3711
3697	vp->d_id.b.domain = rptid_entry->port_id[2];	3712	qlt_update_host_map(vp, id);
3698	vp->d_id.b.area = rptid_entry->port_id[1];
3699	vp->d_id.b.al_pa = rptid_entry->port_id[0];
3700	spin_lock_irqsave(&ha->vport_slock, flags);
3701	qlt_update_vp_map(vp, SET_AL_PA);
3702	spin_unlock_irqrestore(&ha->vport_slock, flags);
3703		3713
3704	/*	3714	/*
3705	* Cannot configure here as we are still sitting on the	3715	* Cannot configure here as we are still sitting on the
@@ -5827,3 +5837,225 @@ qla26xx_dport_diagnostics(scsi_qla_host_t *vha, · 2121 unmodified lines
5827		5837
5828	return rval;	5838	return rval;
5829	}	5839	}
		5840
		5841	static void qla2x00_async_mb_sp_done(void *s, int res)
		5842	{
		5843	struct srb *sp = s;
		5844
		5845	sp->u.iocb_cmd.u.mbx.rc = res;
		5846
		5847	complete(&sp->u.iocb_cmd.u.mbx.comp);
		5848	/* don't free sp here. Let the caller do the free */
		5849	}
		5850
		5851	/*
		5852	* This mailbox uses the iocb interface to send MB command.
		5853	* This allows non-critial (non chip setup) command to go
		5854	* out in parrallel.
		5855	*/
		5856	int qla24xx_send_mb_cmd(struct scsi_qla_host vha, mbx_cmd_t mcp)
		5857	{
		5858	int rval = QLA_FUNCTION_FAILED;
		5859	srb_t *sp;
		5860	struct srb_iocb *c;
		5861
		5862	if (!vha->hw->flags.fw_started)
		5863	goto done;
		5864
		5865	sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
		5866	if (!sp)
		5867	goto done;
		5868
		5869	sp->type = SRB_MB_IOCB;
		5870	sp->name = mb_to_str(mcp->mb[0]);
		5871
		5872	qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
		5873
		5874	memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
		5875
		5876	c = &sp->u.iocb_cmd;
		5877	c->timeout = qla2x00_async_iocb_timeout;
		5878	init_completion(&c->u.mbx.comp);
		5879
		5880	sp->done = qla2x00_async_mb_sp_done;
		5881
		5882	rval = qla2x00_start_sp(sp);
		5883	if (rval != QLA_SUCCESS) {
		5884	ql_dbg(ql_dbg_mbx, vha, 0xffff,
		5885	"%s: %s Failed submission. %x.\n",
		5886	__func__, sp->name, rval);
		5887	goto done_free_sp;
		5888	}
		5889
		5890	ql_dbg(ql_dbg_mbx, vha, 0xffff, "MB:%s hndl %x submitted\n",
		5891	sp->name, sp->handle);
		5892
		5893	wait_for_completion(&c->u.mbx.comp);
		5894	memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
		5895
		5896	rval = c->u.mbx.rc;
		5897	switch (rval) {
		5898	case QLA_FUNCTION_TIMEOUT:
		5899	ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s Timeout. %x.\n",
		5900	__func__, sp->name, rval);
		5901	break;
		5902	case QLA_SUCCESS:
		5903	ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s done.\n",
		5904	__func__, sp->name);
		5905	sp->free(sp);
		5906	break;
		5907	default:
		5908	ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s Failed. %x.\n",
		5909	__func__, sp->name, rval);
		5910	sp->free(sp);
		5911	break;
		5912	}
		5913
		5914	return rval;
		5915
		5916	done_free_sp:
		5917	sp->free(sp);
		5918	done:
		5919	return rval;
		5920	}
		5921
		5922	/*
		5923	* qla24xx_gpdb_wait
		5924	* NOTE: Do not call this routine from DPC thread
		5925	*/
		5926	int qla24xx_gpdb_wait(struct scsi_qla_host vha, fc_port_t fcport, u8 opt)
		5927	{
		5928	int rval = QLA_FUNCTION_FAILED;
		5929	dma_addr_t pd_dma;
		5930	struct port_database_24xx *pd;
		5931	struct qla_hw_data *ha = vha->hw;
		5932	mbx_cmd_t mc;
		5933
		5934	if (!vha->hw->flags.fw_started)
		5935	goto done;
		5936
		5937	pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
		5938	if (pd == NULL) {
		5939	ql_log(ql_log_warn, vha, 0xffff,
		5940	"Failed to allocate port database structure.\n");
		5941	goto done_free_sp;
		5942	}
		5943	memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
		5944
		5945	memset(&mc, 0, sizeof(mc));
		5946	mc.mb[0] = MBC_GET_PORT_DATABASE;
		5947	mc.mb[1] = cpu_to_le16(fcport->loop_id);
		5948	mc.mb[2] = MSW(pd_dma);
		5949	mc.mb[3] = LSW(pd_dma);
		5950	mc.mb[6] = MSW(MSD(pd_dma));
		5951	mc.mb[7] = LSW(MSD(pd_dma));
		5952	mc.mb[9] = cpu_to_le16(vha->vp_idx);
		5953	mc.mb[10] = cpu_to_le16((uint16_t)opt);
		5954
		5955	rval = qla24xx_send_mb_cmd(vha, &mc);
		5956	if (rval != QLA_SUCCESS) {
		5957	ql_dbg(ql_dbg_mbx, vha, 0xffff,
		5958	"%s: %8phC fail\n", __func__, fcport->port_name);
		5959	goto done_free_sp;
		5960	}
		5961
		5962	rval = __qla24xx_parse_gpdb(vha, fcport, pd);
		5963
		5964	ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %8phC done\n",
		5965	__func__, fcport->port_name);
		5966
		5967	done_free_sp:
		5968	if (pd)
		5969	dma_pool_free(ha->s_dma_pool, pd, pd_dma);
		5970	done:
		5971	return rval;
		5972	}
		5973
		5974	int __qla24xx_parse_gpdb(struct scsi_qla_host vha, fc_port_t fcport,
		5975	struct port_database_24xx *pd)
		5976	{
		5977	int rval = QLA_SUCCESS;
		5978	uint64_t zero = 0;
		5979
		5980	/* Check for logged in state. */
		5981	if (pd->current_login_state != PDS_PRLI_COMPLETE &&
		5982	pd->last_login_state != PDS_PRLI_COMPLETE) {
		5983	ql_dbg(ql_dbg_mbx, vha, 0xffff,
		5984	"Unable to verify login-state (%x/%x) for "
		5985	"loop_id %x.\n", pd->current_login_state,
		5986	pd->last_login_state, fcport->loop_id);
		5987	rval = QLA_FUNCTION_FAILED;
		5988	goto gpd_error_out;
		5989	}
		5990
		5991	if (fcport->loop_id == FC_NO_LOOP_ID \|\|
		5992	(memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
		5993	memcmp(fcport->port_name, pd->port_name, 8))) {
		5994	/* We lost the device mid way. */
		5995	rval = QLA_NOT_LOGGED_IN;
		5996	goto gpd_error_out;
		5997	}
		5998
		5999	/* Names are little-endian. */
		6000	memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
		6001	memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
		6002
		6003	/* Get port_id of device. */
		6004	fcport->d_id.b.domain = pd->port_id[0];
		6005	fcport->d_id.b.area = pd->port_id[1];
		6006	fcport->d_id.b.al_pa = pd->port_id[2];
		6007	fcport->d_id.b.rsvd_1 = 0;
		6008
		6009	/* If not target must be initiator or unknown type. */
		6010	if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
		6011	fcport->port_type = FCT_INITIATOR;
		6012	else
		6013	fcport->port_type = FCT_TARGET;
		6014
		6015	/* Passback COS information. */
		6016	fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
		6017	FC_COS_CLASS2 : FC_COS_CLASS3;
		6018
		6019	if (pd->prli_svc_param_word_3[0] & BIT_7) {
		6020	fcport->flags \|= FCF_CONF_COMP_SUPPORTED;
		6021	fcport->conf_compl_supported = 1;
		6022	}
		6023
		6024	gpd_error_out:
		6025	return rval;
		6026	}
		6027
		6028	/*
		6029	* qla24xx_gidlist__wait
		6030	* NOTE: don't call this routine from DPC thread.
		6031	*/
		6032	int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
		6033	void id_list, dma_addr_t id_list_dma, uint16_t entries)
		6034	{
		6035	int rval = QLA_FUNCTION_FAILED;
		6036	mbx_cmd_t mc;
		6037
		6038	if (!vha->hw->flags.fw_started)
		6039	goto done;
		6040
		6041	memset(&mc, 0, sizeof(mc));
		6042	mc.mb[0] = MBC_GET_ID_LIST;
		6043	mc.mb[2] = MSW(id_list_dma);
		6044	mc.mb[3] = LSW(id_list_dma);
		6045	mc.mb[6] = MSW(MSD(id_list_dma));
		6046	mc.mb[7] = LSW(MSD(id_list_dma));
		6047	mc.mb[8] = 0;
		6048	mc.mb[9] = cpu_to_le16(vha->vp_idx);
		6049
		6050	rval = qla24xx_send_mb_cmd(vha, &mc);
		6051	if (rval != QLA_SUCCESS) {
		6052	ql_dbg(ql_dbg_mbx, vha, 0xffff,
		6053	"%s: fail\n", __func__);
		6054	} else {
		6055	*entries = mc.mb[1];
		6056	ql_dbg(ql_dbg_mbx, vha, 0xffff,
		6057	"%s: done\n", __func__);
		6058	}
		6059	done:
		6060	return rval;
		6061	}

drivers/scsi/qla2xxx/qla_mid.c+8−6

 	 * ensures no active vp_list traversal while the vport is removed
 	 * from the queue)
 	 */
-	spin_lock_irqsave(&ha->vport_slock, flags);
+	wait_event_timeout(vha->vref_waitq, atomic_read(&vha->vref_count),
-	while (atomic_read(&vha->vref_count)) {
+	    10*HZ);
-		spin_unlock_irqrestore(&ha->vport_slock, flags);
-		msleep(500);
-		spin_lock_irqsave(&ha->vport_slock, flags);
+	spin_lock_irqsave(&ha->vport_slock, flags);
+	if (atomic_read(&vha->vref_count)) {
+		ql_dbg(ql_dbg_vport, vha, 0xfffa,
+		    "vha->vref_count=%u timeout\n", vha->vref_count.counter);
+		vha->vref_count = (atomic_t)ATOMIC_INIT(0);
 	}
 	list_del(&vha->list);
 	qlt_update_vp_map(vha, RESET_VP_IDX);
 			spin_lock_irqsave(&ha->vport_slock, flags);
 			atomic_dec(&vha->vref_count);
+			wake_up(&vha->vref_waitq);
 		}
 		i++;
 	}

drivers/scsi/qla2xxx/qla_os.c+22−1

@@ -2560,6 +2560,20 @@ qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) · 2559 unmodified lines
2560	return atomic_read(&vha->loop_state) == LOOP_READY;	2560	return atomic_read(&vha->loop_state) == LOOP_READY;
2561	}	2561	}
2562		2562
		2563	static void qla2x00_iocb_work_fn(struct work_struct *work)
		2564	{
		2565	struct scsi_qla_host *vha = container_of(work,
		2566	struct scsi_qla_host, iocb_work);
		2567	int cnt = 0;

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@@ -769,7 +769,7 @@ static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) · 768 unmodified lines
769	#define MLXSW_REG_SPVM_ID 0x200F	769	#define MLXSW_REG_SPVM_ID 0x200F
770	#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */	770	#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
771	#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */	771	#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
772	#define MLXSW_REG_SPVM_REC_MAX_COUNT 256	772	#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
773	#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \	773	#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
774	MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)	774	MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
775		775
@@ -1702,7 +1702,7 @@ static inline void mlxsw_reg_sfmr_pack(char *payload, · 926 unmodified lines
1702	#define MLXSW_REG_SPVMLR_ID 0x2020	1702	#define MLXSW_REG_SPVMLR_ID 0x2020
1703	#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */	1703	#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1704	#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */	1704	#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1705	#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256	1705	#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1706	#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \	1706	#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1707	MLXSW_REG_SPVMLR_REC_LEN * \	1707	MLXSW_REG_SPVMLR_REC_LEN * \
1708	MLXSW_REG_SPVMLR_REC_MAX_COUNT)	1708	MLXSW_REG_SPVMLR_REC_MAX_COUNT)

@@ -2159,7 +2159,7 @@ megasas_set_raidflag_cpu_affinity(union RAID_CONTEXT_UNION *praid_context, · 2158 unmodified lines
2159	cpu_sel = MR_RAID_CTX_CPUSEL_1;	2159	cpu_sel = MR_RAID_CTX_CPUSEL_1;
2160		2160
2161	if (is_stream_detected(rctx_g35) &&	2161	if (is_stream_detected(rctx_g35) &&
2162	(raid->level == 5) &&	2162	((raid->level == 5) \|\| (raid->level == 6)) &&
2163	(raid->writeMode == MR_RL_WRITE_THROUGH_MODE) &&	2163	(raid->writeMode == MR_RL_WRITE_THROUGH_MODE) &&
2164	(cpu_sel == MR_RAID_CTX_CPUSEL_FCFS))	2164	(cpu_sel == MR_RAID_CTX_CPUSEL_FCFS))
2165	cpu_sel = MR_RAID_CTX_CPUSEL_0;	2165	cpu_sel = MR_RAID_CTX_CPUSEL_0;
@@ -2338,7 +2338,7 @@ megasas_build_ldio_fusion(struct megasas_instance *instance, · 172 unmodified lines
2338	fp_possible = false;	2338	fp_possible = false;
2339	atomic_dec(&instance->fw_outstanding);	2339	atomic_dec(&instance->fw_outstanding);
2340	} else if ((scsi_buff_len > MR_LARGE_IO_MIN_SIZE) \|\|	2340	} else if ((scsi_buff_len > MR_LARGE_IO_MIN_SIZE) \|\|
2341	atomic_dec_if_positive(&mrdev_priv->r1_ldio_hint)) {	2341	(atomic_dec_if_positive(&mrdev_priv->r1_ldio_hint) > 0)) {
2342	fp_possible = false;	2342	fp_possible = false;
2343	atomic_dec(&instance->fw_outstanding);	2343	atomic_dec(&instance->fw_outstanding);
2344	if (scsi_buff_len > MR_LARGE_IO_MIN_SIZE)	2344	if (scsi_buff_len > MR_LARGE_IO_MIN_SIZE)

@@ -1342,7 +1342,7 @@ void qedf_scsi_completion(struct qedf_ctx qedf, struct fcoe_cqe cqe, · 1341 unmodified lines
1342	} else {	1342	} else {
1343	refcount = kref_read(&io_req->refcount);	1343	refcount = kref_read(&io_req->refcount);
1344	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_IO,	1344	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_IO,
1345	"%d:0:%d:%d xid=0x%0x op=0x%02x "	1345	"%d:0:%d:%lld xid=0x%0x op=0x%02x "
1346	"lba=%02x%02x%02x%02x cdb_status=%d "	1346	"lba=%02x%02x%02x%02x cdb_status=%d "
1347	"fcp_resid=0x%x refcount=%d.\n",	1347	"fcp_resid=0x%x refcount=%d.\n",
1348	qedf->lport->host->host_no, sc_cmd->device->id,	1348	qedf->lport->host->host_no, sc_cmd->device->id,
@@ -1426,7 +1426,7 @@ void qedf_scsi_done(struct qedf_ctx qedf, struct qedf_ioreq io_req, · 77 unmodified lines
1426		1426
1427	sc_cmd->result = result << 16;	1427	sc_cmd->result = result << 16;
1428	refcount = kref_read(&io_req->refcount);	1428	refcount = kref_read(&io_req->refcount);
1429	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_IO, "%d:0:%d:%d: Completing "	1429	QEDF_INFO(&(qedf->dbg_ctx), QEDF_LOG_IO, "%d:0:%d:%lld: Completing "
1430	"sc_cmd=%p result=0x%08x op=0x%02x lba=0x%02x%02x%02x%02x, "	1430	"sc_cmd=%p result=0x%08x op=0x%02x lba=0x%02x%02x%02x%02x, "
1431	"allowed=%d retries=%d refcount=%d.\n",	1431	"allowed=%d retries=%d refcount=%d.\n",
1432	qedf->lport->host->host_no, sc_cmd->device->id,	1432	qedf->lport->host->host_no, sc_cmd->device->id,