Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt: - A fix to avoid pt_regs aliasing with idle thread stacks on secondary harts. - HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot issues on XIP systems with huge pages. - An update to the uABI documentation clarifying that only scalar misaligned accesses were grandfathered in as supported, as the vector extension did not exist at the time the uABI was frozen. - A fix for the recently-added byte/half atomics to avoid losing the fully ordered decorations. * tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fix fully ordered LR/SC xchg[8|16]() implementations Documentation: RISC-V: uabi: Only scalar misaligned loads are supported riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel riscv: prevent pt_regs corruption for secondary idle threads

Linus Torvalds committed 2 years ago

Commit c6cc9792 parents ff9bce3 1d84afa5 files · +18 −15Browse files

Unified · Split

5 files

Documentation/arch/riscv/uabi.rst +3 −1
arch/riscv/Kconfig +1 −1
arch/riscv/include/asm/cmpxchg.h +12 −10
arch/riscv/kernel/cpu_ops_sbi.c +1 −1
arch/riscv/kernel/cpu_ops_spinwait.c +1 −2

Documentation/arch/riscv/uabi.rst+3−1

@@ -65,4 +65,6 @@ the extension, or may have deliberately removed it from the listing. · 64 unmodified lines
65	65	Misaligned accesses
66	66	-------------------
67	67
68		−Misaligned accesses are supported in userspace, but they may perform poorly.
	68	+Misaligned scalar accesses are supported in userspace, but they may perform
	69	+poorly. Misaligned vector accesses are only supported if the Zicclsm extension
	70	+is supported.

arch/riscv/Kconfig+1−1

@@ -106,7 +106,7 @@ config RISCV · 105 unmodified lines
106	106	select HAS_IOPORT if MMU
107	107	select HAVE_ARCH_AUDITSYSCALL
108	108	select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP
109		− select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT && !XIP_KERNEL
	109	+ select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT
110	110	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
111	111	select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
112	112	select HAVE_ARCH_KASAN if MMU && 64BIT

arch/riscv/include/asm/cmpxchg.h+12−10

@@ -10,7 +10,7 @@ · 9 unmodified lines
10	10
11	11	#include <asm/fence.h>
12	12
13		−#define __arch_xchg_masked(prepend, append, r, p, n) \
	13	+#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \
14	14	({ \
15	15	u32 __ptr32b = (u32 )((ulong)(p) & ~0x3); \
16	16	ulong __s = ((ulong)(p) & (0x4 - sizeof(p))) BITS_PER_BYTE; \
@@ -25,7 +25,7 @@ · 8 unmodified lines
25	25	"0: lr.w %0, %2\n" \
26	26	" and %1, %0, %z4\n" \
27	27	" or %1, %1, %z3\n" \
28		− " sc.w %1, %1, %2\n" \
	28	+ " sc.w" sc_sfx " %1, %1, %2\n" \
29	29	" bnez %1, 0b\n" \
30	30	append \
31	31	: "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
@@ -46,7 +46,8 @@ · 14 unmodified lines
46	46	: "memory"); \
47	47	})
48	48
49		−#define _arch_xchg(ptr, new, sfx, prepend, append) \
	49	+#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, \
	50	+ sc_append, swap_append) \
50	51	({ \
51	52	__typeof__(ptr) __ptr = (ptr); \
52	53	__typeof__(*(__ptr)) __new = (new); \
@@ -55,15 +56,15 @@ · 2 unmodified lines
55	56	switch (sizeof(*__ptr)) { \
56	57	case 1: \
57	58	case 2: \
58		− __arch_xchg_masked(prepend, append, \
	59	+ __arch_xchg_masked(sc_sfx, prepend, sc_append, \
59	60	__ret, __ptr, __new); \
60	61	break; \
61	62	case 4: \
62		− __arch_xchg(".w" sfx, prepend, append, \
	63	+ __arch_xchg(".w" swap_sfx, prepend, swap_append, \
63	64	__ret, __ptr, __new); \
64	65	break; \
65	66	case 8: \
66		− __arch_xchg(".d" sfx, prepend, append, \
	67	+ __arch_xchg(".d" swap_sfx, prepend, swap_append, \
67	68	__ret, __ptr, __new); \
68	69	break; \
69	70	default: \
@@ -73,16 +74,17 @@ · 3 unmodified lines
73	74	})
74	75
75	76	#define arch_xchg_relaxed(ptr, x) \
76		− _arch_xchg(ptr, x, "", "", "")
	77	+ _arch_xchg(ptr, x, "", "", "", "", "")
77	78
78	79	#define arch_xchg_acquire(ptr, x) \
79		− _arch_xchg(ptr, x, "", "", RISCV_ACQUIRE_BARRIER)
	80	+ _arch_xchg(ptr, x, "", "", "", \
	81	+ RISCV_ACQUIRE_BARRIER, RISCV_ACQUIRE_BARRIER)
80	82
81	83	#define arch_xchg_release(ptr, x) \
82		− _arch_xchg(ptr, x, "", RISCV_RELEASE_BARRIER, "")
	84	+ _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "", "")
83	85
84	86	#define arch_xchg(ptr, x) \
85		− _arch_xchg(ptr, x, ".aqrl", "", "")
	87	+ _arch_xchg(ptr, x, ".rl", ".aqrl", "", RISCV_FULL_BARRIER, "")
86	88
87	89	#define xchg32(ptr, x) \
88	90	({ \

arch/riscv/kernel/cpu_ops_sbi.c+1−1

@@ -72,7 +72,7 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) · 71 unmodified lines
72	72	/* Make sure tidle is updated */
73	73	smp_mb();
74	74	bdata->task_ptr = tidle;
75		− bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE;
	75	+ bdata->stack_ptr = task_pt_regs(tidle);
76	76	/* Make sure boot data is updated */
77	77	smp_mb();
78	78	hsm_data = __pa(bdata);

arch/riscv/kernel/cpu_ops_spinwait.c+1−2

@@ -34,8 +34,7 @@ static void cpu_update_secondary_bootdata(unsigned int cpuid, · 33 unmodified lines
34	34
35	35	/* Make sure tidle is updated */
36	36	smp_mb();
37		− WRITE_ONCE(__cpu_spinwait_stack_pointer[hartid],
38		− task_stack_page(tidle) + THREAD_SIZE);
	37	+ WRITE_ONCE(__cpu_spinwait_stack_pointer[hartid], task_pt_regs(tidle));
39	38	WRITE_ONCE(__cpu_spinwait_task_pointer[hartid], tidle);
40	39	}
41	40

Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

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