Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd: "A handful of clk driver fixes: - Fix an OOB issue in the Mediatek mt8365 driver where arrays of clks are mismatched in size - Use the proper clk_ops for a few clks in the Mediatek mt8365 driver - Stop using abs() in clk_composite_determine_rate() because 64-bit math goes wrong on large unsigned long numbers that are subtracted and passed into abs() - Zero initialize a struct clk_init_data in clk-loongson2 to avoid stack junk confusing clk_hw_register() - Actually use a pointer to __iomem for writel() in pxa3xx_clk_update_accr() so we don't oops" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: pxa: fix NULL pointer dereference in pxa3xx_clk_update_accr clk: clk-loongson2: Zero init clk_init_data clk: mediatek: mt8365: Fix inverted topclk operations clk: composite: Fix handling of high clock rates clk: mediatek: mt8365: Fix index issue

Linus Torvalds committed 3 years ago

Commit c6cf6be2 parents 1639fae 23200a44 files · +21 −6Browse files

Unified · Split

4 files

drivers/clk/clk-composite.c +4 −1
drivers/clk/clk-loongson2.c +1 −1
drivers/clk/mediatek/clk-mt8365.c +15 −3
drivers/clk/pxa/clk-pxa3xx.c +1 −1

drivers/clk/clk-composite.c+4−1

@@ -119,7 +119,10 @@ static int clk_composite_determine_rate(struct clk_hw *hw, · 118 unmodified lines
119	119	if (ret)
120	120	continue;
121	121
122		− rate_diff = abs(req->rate - tmp_req.rate);
	122	+ if (req->rate >= tmp_req.rate)
	123	+ rate_diff = req->rate - tmp_req.rate;
	124	+ else
	125	+ rate_diff = tmp_req.rate - req->rate;
123	126
124	127	if (!rate_diff \|\| !req->best_parent_hw
125	128	\|\| best_rate_diff > rate_diff) {

drivers/clk/clk-loongson2.c+1−1

@@ -40,7 +40,7 @@ static struct clk_hw loongson2_clk_register(struct device dev, · 39 unmodified lines
40	40	{
41	41	int ret;
42	42	struct clk_hw *hw;
43		− struct clk_init_data init;
	43	+ struct clk_init_data init = { };
44	44
45	45	hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
46	46	if (!hw)

drivers/clk/mediatek/clk-mt8365.c+15−3

@@ -23,6 +23,7 @@ · 22 unmodified lines
23	23	static DEFINE_SPINLOCK(mt8365_clk_lock);
24	24
25	25	static const struct mtk_fixed_clk top_fixed_clks[] = {
	26	+ FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
26	27	FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000),
27	28	FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m",
28	29	75000000),
@@ -559,6 +560,14 @@ static const struct mtk_clk_divider top_adj_divs[] = { · 530 unmodified lines
559	560	0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
560	561	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel",
561	562	0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
	563	+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
	564	+ 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
	565	+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel",
	566	+ 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
	567	+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel",
	568	+ 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
	569	+ DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel",
	570	+ 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
562	571	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel",
563	572	0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
564	573	};
@@ -583,15 +592,15 @@ static const struct mtk_gate_regs top2_cg_regs = { · 18 unmodified lines
583	592
584	593	#define GATE_TOP0(_id, _name, _parent, _shift) \
585	594	GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
586		− _shift, &mtk_clk_gate_ops_no_setclr_inv)
	595	+ _shift, &mtk_clk_gate_ops_no_setclr)
587	596
588	597	#define GATE_TOP1(_id, _name, _parent, _shift) \
589	598	GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
590		− _shift, &mtk_clk_gate_ops_no_setclr)
	599	+ _shift, &mtk_clk_gate_ops_no_setclr_inv)
591	600
592	601	#define GATE_TOP2(_id, _name, _parent, _shift) \
593	602	GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
594		− _shift, &mtk_clk_gate_ops_no_setclr)
	603	+ _shift, &mtk_clk_gate_ops_no_setclr_inv)
595	604
596	605	static const struct mtk_gate top_clk_gates[] = {
597	606	GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
@@ -696,6 +705,7 @@ static const struct mtk_gate ifr_clks[] = { · 98 unmodified lines
696	705	GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8),
697	706	GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9),
698	707	GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10),
	708	+ GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11),
699	709	GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14),
700	710	GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18),
701	711	GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24),
@@ -717,6 +727,8 @@ static const struct mtk_gate ifr_clks[] = { · 15 unmodified lines
717	727	GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12),
718	728	GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13),
719	729	GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14),
	730	+ GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs,
	731	+ 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED),
720	732	GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22),
721	733	GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23),
722	734	GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),

drivers/clk/pxa/clk-pxa3xx.c+1−1

@@ -164,7 +164,7 @@ void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask) · 163 unmodified lines
164	164	accr &= ~disable;
165	165	accr \|= enable;
166	166
167		− writel(accr, ACCR);
	167	+ writel(accr, clk_regs + ACCR);
168	168	if (xclkcfg)
169	169	__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
170	170