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drm/i915: Remove last traces of exec-id (GEM_BUSY)

As we allow per-context engine allows the legacy concept of I915_EXEC_RING no longer applies universally. We are still exposing the unrelated exec-id in GEM_BUSY, so transition this ioctl (once more slightly changing its ABI, but no one cares) over to only reporting the uabi-class (not instance as we can not foreseeably fit those into the small bitmask). The only user of the extended ring information from GEM_BUSY is ddx/sna, which tries to use the non-rcs business information to guide which engine to use for subsequent operations on foreign bo. All that matters for it is the decision between rcs and !rcs, so it is unaffected by the change in higher bits.

Chris Wilson committed 7 years ago

Commit c8b50241 parent 62acc7e4 files · +34 −41Browse files

Unified · Split

4 files
  1. drivers/gpu/drm/i915/i915_gem.c +17 −15
  2. drivers/gpu/drm/i915/intel_engine_cs.c +0 −10
  3. drivers/gpu/drm/i915/intel_ringbuffer.h +0 −1
  4. include/uapi/drm/i915_drm.h +17 −15
drivers/gpu/drm/i915/i915_gem.c+17−15
@@ -3825,20 +3825,17 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, · 3824 unmodified lines
3825 3825
3826static __always_inline unsigned int __busy_read_flag(unsigned int id)3826static __always_inline unsigned int __busy_read_flag(unsigned int id)
3827{3827{
3828 /* Note that we could alias engines in the execbuf API, but3828 if (id == I915_ENGINE_CLASS_INVALID)
3829 * that would be very unwise as it prevents userspace from3829 return 0xffff0000;
3830 * fine control over engine selection. Ahem.3830
3831 *3831 GEM_BUG_ON(id >= 16);
3832 * This should be something like EXEC_MAX_ENGINE instead of
3833 * I915_NUM_ENGINES.
3834 */
3835 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3836 return 0x10000 << id;3832 return 0x10000 << id;
3837}3833}
3838 3834
3839static __always_inline unsigned int __busy_write_id(unsigned int id)3835static __always_inline unsigned int __busy_write_id(unsigned int id)
3840{3836{
3841 /* The uABI guarantees an active writer is also amongst the read3837 /*
3838 * The uABI guarantees an active writer is also amongst the read
3842 * engines. This would be true if we accessed the activity tracking3839 * engines. This would be true if we accessed the activity tracking
3843 * under the lock, but as we perform the lookup of the object and3840 * under the lock, but as we perform the lookup of the object and
3844 * its activity locklessly we can not guarantee that the last_write3841 * its activity locklessly we can not guarantee that the last_write
@@ -3846,16 +3843,20 @@ static __always_inline unsigned int __busy_write_id(unsigned int id) · 1 unmodified line
3846 * last_read - hence we always set both read and write busy for3843 * last_read - hence we always set both read and write busy for
3847 * last_write.3844 * last_write.
3848 */3845 */
3849 return id | __busy_read_flag(id);3846 if (id == I915_ENGINE_CLASS_INVALID)
3847 return 0xffffffff;
3848
3849 return (id + 1) | __busy_read_flag(id);
3850}3850}
3851 3851
3852static __always_inline unsigned int3852static __always_inline unsigned int
3853__busy_set_if_active(const struct dma_fence *fence,3853__busy_set_if_active(const struct dma_fence *fence,
3854 unsigned int (*flag)(unsigned int id))3854 unsigned int (*flag)(unsigned int id))
3855{3855{
3856 struct i915_request *rq;3856 const struct i915_request *rq;
3857 3857
3858 /* We have to check the current hw status of the fence as the uABI3858 /*
3859 * We have to check the current hw status of the fence as the uABI
3859 * guarantees forward progress. We could rely on the idle worker3860 * guarantees forward progress. We could rely on the idle worker
3860 * to eventually flush us, but to minimise latency just ask the3861 * to eventually flush us, but to minimise latency just ask the
3861 * hardware.3862 * hardware.
@@ -3866,11 +3867,11 @@ __busy_set_if_active(const struct dma_fence *fence, · 4 unmodified lines
3866 return 0;3867 return 0;
3867 3868
3868 /* opencode to_request() in order to avoid const warnings */3869 /* opencode to_request() in order to avoid const warnings */
3869 rq = container_of(fence, struct i915_request, fence);3870 rq = container_of(fence, const struct i915_request, fence);
3870 if (i915_request_completed(rq))3871 if (i915_request_completed(rq))
3871 return 0;3872 return 0;
3872 3873
3873 return flag(rq->engine->uabi_id);3874 return flag(rq->engine->uabi_class);
3874}3875}
3875 3876
3876static __always_inline unsigned int3877static __always_inline unsigned int
@@ -3904,7 +3905,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, · 27 unmodified lines
3904 if (!obj)3905 if (!obj)
3905 goto out;3906 goto out;
3906 3907
3907 /* A discrepancy here is that we do not report the status of3908 /*
3909 * A discrepancy here is that we do not report the status of
3908 * non-i915 fences, i.e. even though we may report the object as idle,3910 * non-i915 fences, i.e. even though we may report the object as idle,
3909 * a call to set-domain may still stall waiting for foreign rendering.3911 * a call to set-domain may still stall waiting for foreign rendering.
3910 * This also means that wait-ioctl may report an object as busy,3912 * This also means that wait-ioctl may report an object as busy,
drivers/gpu/drm/i915/intel_engine_cs.c+0−10
@@ -84,7 +84,6 @@ static const struct engine_class_info intel_engine_classes[] = { · 83 unmodified lines
84#define MAX_MMIO_BASES 384#define MAX_MMIO_BASES 3
85struct engine_info {85struct engine_info {
86 unsigned int hw_id;86 unsigned int hw_id;
87 unsigned int uabi_id;
88 u8 class;87 u8 class;
89 u8 instance;88 u8 instance;
90 /* mmio bases table *must* be sorted in reverse gen order */89 /* mmio bases table *must* be sorted in reverse gen order */
@@ -97,7 +96,6 @@ struct engine_info { · 6 unmodified lines
97static const struct engine_info intel_engines[] = {96static const struct engine_info intel_engines[] = {
98 [RCS] = {97 [RCS] = {
99 .hw_id = RCS_HW,98 .hw_id = RCS_HW,
100 .uabi_id = I915_EXEC_RENDER,
101 .class = RENDER_CLASS,99 .class = RENDER_CLASS,
102 .instance = 0,100 .instance = 0,
103 .mmio_bases = {101 .mmio_bases = {
@@ -106,7 +104,6 @@ static const struct engine_info intel_engines[] = { · 2 unmodified lines
106 },104 },
107 [BCS] = {105 [BCS] = {
108 .hw_id = BCS_HW,106 .hw_id = BCS_HW,
109 .uabi_id = I915_EXEC_BLT,
110 .class = COPY_ENGINE_CLASS,107 .class = COPY_ENGINE_CLASS,
111 .instance = 0,108 .instance = 0,
112 .mmio_bases = {109 .mmio_bases = {
@@ -115,7 +112,6 @@ static const struct engine_info intel_engines[] = { · 2 unmodified lines
115 },112 },
116 [VCS] = {113 [VCS] = {
117 .hw_id = VCS_HW,114 .hw_id = VCS_HW,
118 .uabi_id = I915_EXEC_BSD,
119 .class = VIDEO_DECODE_CLASS,115 .class = VIDEO_DECODE_CLASS,
120 .instance = 0,116 .instance = 0,
121 .mmio_bases = {117 .mmio_bases = {
@@ -126,7 +122,6 @@ static const struct engine_info intel_engines[] = { · 4 unmodified lines
126 },122 },
127 [VCS2] = {123 [VCS2] = {
128 .hw_id = VCS2_HW,124 .hw_id = VCS2_HW,
129 .uabi_id = I915_EXEC_BSD,
130 .class = VIDEO_DECODE_CLASS,125 .class = VIDEO_DECODE_CLASS,
131 .instance = 1,126 .instance = 1,
132 .mmio_bases = {127 .mmio_bases = {
@@ -136,7 +131,6 @@ static const struct engine_info intel_engines[] = { · 3 unmodified lines
136 },131 },
137 [VCS3] = {132 [VCS3] = {
138 .hw_id = VCS3_HW,133 .hw_id = VCS3_HW,
139 .uabi_id = I915_EXEC_BSD,
140 .class = VIDEO_DECODE_CLASS,134 .class = VIDEO_DECODE_CLASS,
141 .instance = 2,135 .instance = 2,
142 .mmio_bases = {136 .mmio_bases = {
@@ -145,7 +139,6 @@ static const struct engine_info intel_engines[] = { · 2 unmodified lines
145 },139 },
146 [VCS4] = {140 [VCS4] = {
147 .hw_id = VCS4_HW,141 .hw_id = VCS4_HW,
148 .uabi_id = I915_EXEC_BSD,
149 .class = VIDEO_DECODE_CLASS,142 .class = VIDEO_DECODE_CLASS,
150 .instance = 3,143 .instance = 3,
151 .mmio_bases = {144 .mmio_bases = {
@@ -154,7 +147,6 @@ static const struct engine_info intel_engines[] = { · 2 unmodified lines
154 },147 },
155 [VECS] = {148 [VECS] = {
156 .hw_id = VECS_HW,149 .hw_id = VECS_HW,
157 .uabi_id = I915_EXEC_VEBOX,
158 .class = VIDEO_ENHANCEMENT_CLASS,150 .class = VIDEO_ENHANCEMENT_CLASS,
159 .instance = 0,151 .instance = 0,
160 .mmio_bases = {152 .mmio_bases = {
@@ -164,7 +156,6 @@ static const struct engine_info intel_engines[] = { · 3 unmodified lines
164 },156 },
165 [VECS2] = {157 [VECS2] = {
166 .hw_id = VECS2_HW,158 .hw_id = VECS2_HW,
167 .uabi_id = I915_EXEC_VEBOX,
168 .class = VIDEO_ENHANCEMENT_CLASS,159 .class = VIDEO_ENHANCEMENT_CLASS,
169 .instance = 1,160 .instance = 1,
170 .mmio_bases = {161 .mmio_bases = {
@@ -321,7 +312,6 @@ intel_engine_setup(struct drm_i915_private *dev_priv, · 150 unmodified lines
321 engine->class = info->class;312 engine->class = info->class;
322 engine->instance = info->instance;313 engine->instance = info->instance;
323 314
324 engine->uabi_id = info->uabi_id;
325 engine->uabi_class = intel_engine_classes[info->class].uabi_class;315 engine->uabi_class = intel_engine_classes[info->class].uabi_class;
326 316
327 engine->context_size = __intel_engine_context_size(dev_priv,317 engine->context_size = __intel_engine_context_size(dev_priv,
drivers/gpu/drm/i915/intel_ringbuffer.h+0−1
@@ -335,7 +335,6 @@ struct intel_engine_cs { · 334 unmodified lines
335 unsigned int hw_id;335 unsigned int hw_id;
336 unsigned int guc_id;336 unsigned int guc_id;
337 337
338 u8 uabi_id;
339 u8 uabi_class;338 u8 uabi_class;
340 339
341 u8 class;340 u8 class;
include/uapi/drm/i915_drm.h+17−15
@@ -1127,32 +1127,34 @@ struct drm_i915_gem_busy { · 1126 unmodified lines
1127 * as busy may become idle before the ioctl is completed.1127 * as busy may become idle before the ioctl is completed.
1128 *1128 *
1129 * Furthermore, if the object is busy, which engine is busy is only1129 * Furthermore, if the object is busy, which engine is busy is only
1130 * provided as a guide. There are race conditions which prevent the1130 * provided as a guide and only indirectly by reporting its class
1131 * report of which engines are busy from being always accurate.1131 * (there may be more than one engine in each class). There are race
1132 * However, the converse is not true. If the object is idle, the1132 * conditions which prevent the report of which engines are busy from
1133 * result of the ioctl, that all engines are idle, is accurate.1133 * being always accurate. However, the converse is not true. If the
1134 * object is idle, the result of the ioctl, that all engines are idle,
1135 * is accurate.
1134 *1136 *
1135 * The returned dword is split into two fields to indicate both1137 * The returned dword is split into two fields to indicate both
1136 * the engines on which the object is being read, and the1138 * the engine classess on which the object is being read, and the
1137 * engine on which it is currently being written (if any).1139 * engine class on which it is currently being written (if any).
1138 *1140 *
1139 * The low word (bits 0:15) indicate if the object is being written1141 * The low word (bits 0:15) indicate if the object is being written
1140 * to by any engine (there can only be one, as the GEM implicit1142 * to by any engine (there can only be one, as the GEM implicit
1141 * synchronisation rules force writes to be serialised). Only the1143 * synchronisation rules force writes to be serialised). Only the
1142 * engine for the last write is reported.1144 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1145 * 1 not 0 etc) for the last write is reported.
1143 *1146 *
1144 * The high word (bits 16:31) are a bitmask of which engines are1147 * The high word (bits 16:31) are a bitmask of which engines classes
1145 * currently reading from the object. Multiple engines may be1148 * are currently reading from the object. Multiple engines may be
1146 * reading from the object simultaneously.1149 * reading from the object simultaneously.
1147 *1150 *
1148 * The value of each engine is the same as specified in the1151 * The value of each engine class is the same as specified in the
1149 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.1152 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1150 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to1153 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1151 * the I915_EXEC_RENDER engine for execution, and so it is never
1152 * reported as active itself. Some hardware may have parallel1154 * reported as active itself. Some hardware may have parallel
1153 * execution engines, e.g. multiple media engines, which are1155 * execution engines, e.g. multiple media engines, which are
1154 * mapped to the same identifier in the EXECBUFFER2 ioctl and1156 * mapped to the same class identifier and so are not separately
1155 * so are not separately reported for busyness.1157 * reported for busyness.
1156 *1158 *
1157 * Caveat emptor:1159 * Caveat emptor:
1158 * Only the boolean result of this query is reliable; that is whether1160 * Only the boolean result of this query is reliable; that is whether