Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "New Years fixes! Mostly amdgpu with a light smattering of arm graphics, and two AGP warning fixes. Quiet as expected, hopefully we don't get a post holiday rush. agp: - two unused variable removed amdgpu: - ATPX regression fix - SMU metrics table locking fixes - gfxoff fix for raven - RLC firmware loading stability fix mediatek: - external display fix - dsi timing fix sun4i: - Fix double-free in connector/encoder cleanup (Stefan) maildp: - Make vtable static (Ben)" * tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm: agp: remove unused variable arqsz in agp_3_5_enable() agp: remove unused variable mcapndx drm/amdgpu: correct RLC firmwares loading sequence drm/amdgpu: enable gfxoff for raven1 refresh drm/amdgpu/smu: add metrics table lock for vega20 (v2) drm/amdgpu/smu: add metrics table lock for navi (v2) drm/amdgpu/smu: add metrics table lock for arcturus (v2) drm/amdgpu/smu: add metrics table lock Revert "drm/amdgpu: simplify ATPX detection" drm/arm/mali: make malidp_mw_connector_helper_funcs static drm/sun4i: hdmi: Remove duplicate cleanup calls drm/mediatek: reduce the hbp and hfp for phy timing drm/mediatek: Fix can't get component for external display plane. drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane.

Linus Torvalds committed 6 years ago

Commit ca78fde2 parents 15f0ec9 a6204fc14 files · +80 −60Browse files

Unified · Split

14 files

drivers/char/agp/isoch.c +1 −8
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +11 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +1 −1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +4 −11
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +1 −0
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +3 −0
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +1 −0
drivers/gpu/drm/amd/powerplay/navi10_ppt.c +3 −0
drivers/gpu/drm/amd/powerplay/vega20_ppt.c +3 −0
drivers/gpu/drm/arm/malidp_mw.c +1 −1
drivers/gpu/drm/mediatek/mtk_drm_crtc.c +12 −6
drivers/gpu/drm/mediatek/mtk_dsi.c +38 −29
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +0 −2

drivers/char/agp/isoch.c+1−8

@@ -84,7 +84,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, · 83 unmodified lines
84	84	unsigned int cdev = 0;
85	85	u32 mnistat, tnistat, tstatus, mcmd;
86	86	u16 tnicmd, mnicmd;
87		− u8 mcapndx;
88	87	u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async;
89	88	u32 step, rem, rem_isoch, rem_async;
90	89	int ret = 0;
@@ -138,8 +137,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, · 47 unmodified lines
138	137	cur = list_entry(pos, struct agp_3_5_dev, list);
139	138	dev = cur->dev;
140	139
141		− mcapndx = cur->capndx;
142		−
143	140	pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat);
144	141
145	142	master[cdev].maxbw = (mnistat >> 16) & 0xff;
@@ -251,8 +248,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, · 105 unmodified lines
251	248	cur = master[cdev].dev;
252	249	dev = cur->dev;
253	250
254		− mcapndx = cur->capndx;
255		−
256	251	master[cdev].rq += (cdev == ndevs - 1)
257	252	? (rem_async + rem_isoch) : step;
258	253
@@ -319,7 +314,7 @@ int agp_3_5_enable(struct agp_bridge_data *bridge) · 60 unmodified lines
319	314	{
320	315	struct pci_dev td = bridge->dev, dev = NULL;
321	316	u8 mcapndx;
322		− u32 isoch, arqsz;
	317	+ u32 isoch;
323	318	u32 tstatus, mstatus, ncapid;
324	319	u32 mmajor;
325	320	u16 mpstat;
@@ -334,8 +329,6 @@ int agp_3_5_enable(struct agp_bridge_data *bridge) · 8 unmodified lines
334	329	if (isoch == 0) /* isoch xfers not available, bail out. */
335	330	return -ENODEV;
336	331
337		− arqsz = (tstatus >> 13) & 0x7;
338		−
339	332	/*
340	333	* Allocate a head for our AGP 3.5 device list
341	334	* (multiple AGP v3 devices are allowed behind a single bridge).

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+11−1

@@ -613,7 +613,17 @@ static bool amdgpu_atpx_detect(void) · 612 unmodified lines
613	613	bool d3_supported = false;
614	614	struct pci_dev *parent_pdev;
615	615
616		− while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
	616	+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
	617	+ vga_count++;
	618	+
	619	+ has_atpx \|= (amdgpu_atpx_pci_probe_handle(pdev) == true);
	620	+
	621	+ parent_pdev = pci_upstream_bridge(pdev);
	622	+ d3_supported \|= parent_pdev && parent_pdev->bridge_d3;
	623	+ amdgpu_atpx_get_quirks(pdev);
	624	+ }
	625	+
	626	+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
617	627	vga_count++;
618	628
619	629	has_atpx \|= (amdgpu_atpx_pci_probe_handle(pdev) == true);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+1−1

@@ -1488,7 +1488,7 @@ out: · 1487 unmodified lines
1488	1488
1489	1489	/* Start rlc autoload after psp recieved all the gfx firmware */
1490	1490	if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1491		− AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
	1491	+ AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1492	1492	ret = psp_rlc_autoload(psp);
1493	1493	if (ret) {
1494	1494	DRM_ERROR("Failed to start rlc autoload\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+1−1

@@ -292,10 +292,10 @@ enum AMDGPU_UCODE_ID { · 291 unmodified lines
292	292	AMDGPU_UCODE_ID_CP_MEC2_JT,
293	293	AMDGPU_UCODE_ID_CP_MES,
294	294	AMDGPU_UCODE_ID_CP_MES_DATA,
295		− AMDGPU_UCODE_ID_RLC_G,
296	295	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
297	296	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
298	297	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
	298	+ AMDGPU_UCODE_ID_RLC_G,
299	299	AMDGPU_UCODE_ID_STORAGE,
300	300	AMDGPU_UCODE_ID_SMC,
301	301	AMDGPU_UCODE_ID_UVD,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+4−11

@@ -1052,17 +1052,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) · 1051 unmodified lines
1052	1052	case CHIP_VEGA20:
1053	1053	break;
1054	1054	case CHIP_RAVEN:
1055		− /* Disable GFXOFF on original raven. There are combinations
1056		− * of sbios and platforms that are not stable.
1057		− */
1058		− if (!(adev->rev_id >= 0x8 \|\| adev->pdev->device == 0x15d8))
1059		− adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1060		− else if (!(adev->rev_id >= 0x8 \|\| adev->pdev->device == 0x15d8)
1061		− &&((adev->gfx.rlc_fw_version != 106 &&
1062		− adev->gfx.rlc_fw_version < 531) \|\|
1063		− (adev->gfx.rlc_fw_version == 53815) \|\|
1064		− (adev->gfx.rlc_feature_version < 1) \|\|
1065		− !adev->gfx.rlc.is_rlc_v2_1))
	1055	+ if (!(adev->rev_id >= 0x8 \|\|
	1056	+ adev->pdev->device == 0x15d8) &&
	1057	+ (adev->pm.fw_version < 0x41e2b \|\| /* not raven1 fresh */
	1058	+ !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
1066	1059	adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1067	1060
1068	1061	if (adev->pm.pp_feature & PP_GFXOFF_MASK)

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c+1−0

@@ -866,6 +866,7 @@ static int smu_sw_init(void *handle) · 865 unmodified lines
866	866	smu->smu_baco.platform_support = false;
867	867
868	868	mutex_init(&smu->sensor_lock);
	869	+ mutex_init(&smu->metrics_lock);
869	870
870	871	smu->watermarks_bitmap = 0;
871	872	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c+3−0

@@ -862,18 +862,21 @@ static int arcturus_get_metrics_table(struct smu_context *smu, · 861 unmodified lines
862	862	struct smu_table_context *smu_table= &smu->smu_table;
863	863	int ret = 0;
864	864
	865	+ mutex_lock(&smu->metrics_lock);
865	866	if (!smu_table->metrics_time \|\|
866	867	time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
867	868	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
868	869	(void *)smu_table->metrics_table, false);
869	870	if (ret) {
870	871	pr_info("Failed to export SMU metrics table!\n");
	872	+ mutex_unlock(&smu->metrics_lock);
871	873	return ret;
872	874	}
873	875	smu_table->metrics_time = jiffies;
874	876	}
875	877
876	878	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
	879	+ mutex_unlock(&smu->metrics_lock);
877	880
878	881	return ret;
879	882	}

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h+1−0

@@ -349,6 +349,7 @@ struct smu_context · 348 unmodified lines
349	349	const struct pptable_funcs *ppt_funcs;
350	350	struct mutex mutex;
351	351	struct mutex sensor_lock;
	352	+ struct mutex metrics_lock;
352	353	uint64_t pool_size;
353	354
354	355	struct smu_table_context smu_table;

drivers/gpu/drm/amd/powerplay/navi10_ppt.c+3−0

@@ -562,17 +562,20 @@ static int navi10_get_metrics_table(struct smu_context *smu, · 561 unmodified lines
562	562	struct smu_table_context *smu_table= &smu->smu_table;
563	563	int ret = 0;
564	564
	565	+ mutex_lock(&smu->metrics_lock);
565	566	if (!smu_table->metrics_time \|\| time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
566	567	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
567	568	(void *)smu_table->metrics_table, false);
568	569	if (ret) {
569	570	pr_info("Failed to export SMU metrics table!\n");
	571	+ mutex_unlock(&smu->metrics_lock);
570	572	return ret;
571	573	}
572	574	smu_table->metrics_time = jiffies;
573	575	}
574	576
575	577	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
	578	+ mutex_unlock(&smu->metrics_lock);
576	579
577	580	return ret;
578	581	}

drivers/gpu/drm/amd/powerplay/vega20_ppt.c+3−0

@@ -1678,17 +1678,20 @@ static int vega20_get_metrics_table(struct smu_context *smu, · 1677 unmodified lines
1678	1678	struct smu_table_context *smu_table= &smu->smu_table;
1679	1679	int ret = 0;
1680	1680
	1681	+ mutex_lock(&smu->metrics_lock);
1681	1682	if (!smu_table->metrics_time \|\| time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1682	1683	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1683	1684	(void *)smu_table->metrics_table, false);
1684	1685	if (ret) {
1685	1686	pr_info("Failed to export SMU metrics table!\n");
	1687	+ mutex_unlock(&smu->metrics_lock);
1686	1688	return ret;
1687	1689	}
1688	1690	smu_table->metrics_time = jiffies;
1689	1691	}
1690	1692
1691	1693	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
	1694	+ mutex_unlock(&smu->metrics_lock);
1692	1695
1693	1696	return ret;
1694	1697	}

drivers/gpu/drm/arm/malidp_mw.c+1−1

@@ -56,7 +56,7 @@ malidp_mw_connector_mode_valid(struct drm_connector *connector, · 55 unmodified lines
56	56	return MODE_OK;
57	57	}
58	58
59		−const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
	59	+static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
60	60	.get_modes = malidp_mw_connector_get_modes,
61	61	.mode_valid = malidp_mw_connector_mode_valid,
62	62	};

drivers/gpu/drm/mediatek/mtk_drm_crtc.c+12−6

@@ -215,11 +215,12 @@ struct mtk_ddp_comp mtk_drm_ddp_comp_for_plane(struct drm_crtc crtc, · 214 unmodified lines
215	215	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
216	216	struct mtk_ddp_comp *comp;
217	217	int i, count = 0;
	218	+ unsigned int local_index = plane - mtk_crtc->planes;
218	219
219	220	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
220	221	comp = mtk_crtc->ddp_comp[i];
221		− if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) {
222		− *local_layer = plane->index - count;
	222	+ if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
	223	+ *local_layer = local_index - count;
223	224	return comp;
224	225	}
225	226	count += mtk_ddp_comp_layer_nr(comp);
@@ -310,7 +311,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) · 84 unmodified lines
310	311
311	312	plane_state = to_mtk_plane_state(plane->state);
312	313	comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
313		− mtk_ddp_comp_layer_config(comp, local_layer, plane_state);
	314	+ if (comp)
	315	+ mtk_ddp_comp_layer_config(comp, local_layer,
	316	+ plane_state);
314	317	}
315	318
316	319	return 0;
@@ -386,8 +389,9 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) · 69 unmodified lines
386	389	comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
387	390	&local_layer);
388	391
389		− mtk_ddp_comp_layer_config(comp, local_layer,
390		− plane_state);
	392	+ if (comp)
	393	+ mtk_ddp_comp_layer_config(comp, local_layer,
	394	+ plane_state);
391	395	plane_state->pending.config = false;
392	396	}
393	397	mtk_crtc->pending_planes = false;
@@ -401,7 +405,9 @@ int mtk_drm_crtc_plane_check(struct drm_crtc crtc, struct drm_plane plane, · 7 unmodified lines
401	405	struct mtk_ddp_comp *comp;
402	406
403	407	comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
404		− return mtk_ddp_comp_layer_check(comp, local_layer, state);
	408	+ if (comp)
	409	+ return mtk_ddp_comp_layer_check(comp, local_layer, state);
	410	+ return 0;
405	411	}
406	412
407	413	static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,

drivers/gpu/drm/mediatek/mtk_dsi.c+38−29

@@ -230,28 +230,25 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) · 229 unmodified lines
230	230	static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
231	231	{
232	232	u32 timcon0, timcon1, timcon2, timcon3;
233		− u32 ui, cycle_time;
	233	+ u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
234	234	struct mtk_phy_timing *timing = &dsi->phy_timing;
235	235
236		− ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
237		− cycle_time = div_u64(8000000000ULL, dsi->data_rate);
	236	+ timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
	237	+ timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
	238	+ timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
	239	+ timing->da_hs_prepare;
	240	+ timing->da_hs_trail = timing->da_hs_prepare + 1;
238	241
239		− timing->lpx = NS_TO_CYCLE(60, cycle_time);
240		− timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
241		− timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
242		− timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
	242	+ timing->ta_go = 4 * timing->lpx - 2;
	243	+ timing->ta_sure = timing->lpx + 2;
	244	+ timing->ta_get = 4 * timing->lpx;
	245	+ timing->da_hs_exit = 2 * timing->lpx + 1;
243	246
244		− timing->ta_go = 4 * timing->lpx;
245		− timing->ta_sure = 3 * timing->lpx / 2;
246		− timing->ta_get = 5 * timing->lpx;
247		− timing->da_hs_exit = 2 * timing->lpx;
248		−
249		− timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
250		− timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
251		−
252		− timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
253		− timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
254		− timing->clk_hs_exit = 2 * timing->lpx;
	247	+ timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
	248	+ timing->clk_hs_post = timing->clk_hs_prepare + 8;
	249	+ timing->clk_hs_trail = timing->clk_hs_prepare;
	250	+ timing->clk_hs_zero = timing->clk_hs_trail * 4;
	251	+ timing->clk_hs_exit = 2 * timing->clk_hs_trail;
255	252
256	253	timcon0 = timing->lpx \| timing->da_hs_prepare << 8 \|
257	254	timing->da_hs_zero << 16 \| timing->da_hs_trail << 24;
@@ -482,27 +479,39 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) · 224 unmodified lines
482	479	dsi_tmp_buf_bpp - 10);
483	480
484	481	data_phy_cycles = timing->lpx + timing->da_hs_prepare +
485		− timing->da_hs_zero + timing->da_hs_exit + 2;
	482	+ timing->da_hs_zero + timing->da_hs_exit + 3;
486	483
487	484	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
488		− if (vm->hfront_porch * dsi_tmp_buf_bpp >
	485	+ if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
489	486	data_phy_cycles * dsi->lanes + 18) {
490		− horizontal_frontporch_byte = vm->hfront_porch *
491		− dsi_tmp_buf_bpp -
492		− data_phy_cycles *
493		− dsi->lanes - 18;
	487	+ horizontal_frontporch_byte =
	488	+ vm->hfront_porch * dsi_tmp_buf_bpp -
	489	+ (data_phy_cycles * dsi->lanes + 18) *
	490	+ vm->hfront_porch /
	491	+ (vm->hfront_porch + vm->hback_porch);
	492	+
	493	+ horizontal_backporch_byte =
	494	+ horizontal_backporch_byte -
	495	+ (data_phy_cycles * dsi->lanes + 18) *
	496	+ vm->hback_porch /
	497	+ (vm->hfront_porch + vm->hback_porch);
494	498	} else {
495	499	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
496	500	horizontal_frontporch_byte = vm->hfront_porch *
497	501	dsi_tmp_buf_bpp;
498	502	}
499	503	} else {
500		− if (vm->hfront_porch * dsi_tmp_buf_bpp >
	504	+ if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
501	505	data_phy_cycles * dsi->lanes + 12) {
502		− horizontal_frontporch_byte = vm->hfront_porch *
503		− dsi_tmp_buf_bpp -
504		− data_phy_cycles *
505		− dsi->lanes - 12;
	506	+ horizontal_frontporch_byte =
	507	+ vm->hfront_porch * dsi_tmp_buf_bpp -
	508	+ (data_phy_cycles * dsi->lanes + 12) *
	509	+ vm->hfront_porch /
	510	+ (vm->hfront_porch + vm->hback_porch);
	511	+ horizontal_backporch_byte = horizontal_backporch_byte -
	512	+ (data_phy_cycles * dsi->lanes + 12) *
	513	+ vm->hback_porch /
	514	+ (vm->hfront_porch + vm->hback_porch);
506	515	} else {
507	516	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
508	517	horizontal_frontporch_byte = vm->hfront_porch *

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c+0−2

@@ -685,8 +685,6 @@ static void sun4i_hdmi_unbind(struct device dev, struct device master, · 684 unmodified lines
685	685	struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
686	686
687	687	cec_unregister_adapter(hdmi->cec_adap);
688		− drm_connector_cleanup(&hdmi->connector);
689		− drm_encoder_cleanup(&hdmi->encoder);
690	688	i2c_del_adapter(hdmi->i2c);
691	689	i2c_put_adapter(hdmi->ddc_i2c);
692	690	clk_disable_unprepare(hdmi->mod_clk);

Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

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