Linux 4.13-rc7
Unified · Split
| @@ -237,6 +237,14 @@ are the following: · 236 unmodified lines | ||
| 237 | 237 | This attribute is not present if the scaling driver in use does not |
| 238 | 238 | support it. |
| 239 | 239 | |
| 240 | +``cpuinfo_cur_freq`` | |
| 241 | + Current frequency of the CPUs belonging to this policy as obtained from | |
| 242 | + the hardware (in KHz). | |
| 243 | + | |
| 244 | + This is expected to be the frequency the hardware actually runs at. | |
| 245 | + If that frequency cannot be determined, this attribute should not | |
| 246 | + be present. | |
| 247 | + | |
| 240 | 248 | ``cpuinfo_max_freq`` |
| 241 | 249 | Maximum possible operating frequency the CPUs belonging to this policy |
| 242 | 250 | can run at (in kHz). |
| @@ -1,14 +1,22 @@ | ||
| 1 | 1 | * Renesas R-Car SATA |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | −- compatible : should contain one of the following: | |
| 4 | +- compatible : should contain one or more of the following: | |
| 5 | 5 | - "renesas,sata-r8a7779" for R-Car H1 |
| 6 | − ("renesas,rcar-sata" is deprecated) | |
| 7 | 6 | - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 |
| 8 | 7 | - "renesas,sata-r8a7790" for R-Car H2 other than ES1 |
| 9 | 8 | - "renesas,sata-r8a7791" for R-Car M2-W |
| 10 | 9 | - "renesas,sata-r8a7793" for R-Car M2-N |
| 11 | 10 | - "renesas,sata-r8a7795" for R-Car H3 |
| 11 | + - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device | |
| 12 | + - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device | |
| 13 | + - "renesas,rcar-sata" is deprecated | |
| 14 | + | |
| 15 | + When compatible with the generic version nodes | |
| 16 | + must list the SoC-specific version corresponding | |
| 17 | + to the platform first followed by the generic | |
| 18 | + version. | |
| 19 | + | |
| 12 | 20 | - reg : address and length of the SATA registers; |
| 13 | 21 | - interrupts : must consist of one interrupt specifier. |
| 14 | 22 | - clocks : must contain a reference to the functional clock. |
| @@ -16,7 +24,7 @@ Required properties: · 1 unmodified line | ||
| 16 | 24 | Example: |
| 17 | 25 | |
| 18 | 26 | sata0: sata@ee300000 { |
| 19 | − compatible = "renesas,sata-r8a7791"; | |
| 27 | + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; | |
| 20 | 28 | reg = <0 0xee300000 0 0x2000>; |
| 21 | 29 | interrupt-parent = <&gic>; |
| 22 | 30 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -0,0 +1,5 @@ | ||
| 1 | +Exportable MPIO interface of Exar UART chips | |
| 2 | + | |
| 3 | +Required properties of the device: | |
| 4 | + - exar,first-pin: first exportable pins (0..15) | |
| 5 | + - ngpios: number of exportable pins (1..16) | |
| @@ -40,7 +40,7 @@ Optional properties: · 39 unmodified lines | ||
| 40 | 40 | Example for a Mali-T760: |
| 41 | 41 | |
| 42 | 42 | gpu@ffa30000 { |
| 43 | − compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; | |
| 43 | + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; | |
| 44 | 44 | reg = <0xffa30000 0x10000>; |
| 45 | 45 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 46 | 46 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -27,5 +27,11 @@ You have to add the following kernel parameters in your elilo.conf: · 26 unmodified lines | ||
| 27 | 27 | Macbook Pro 17", iMac 20" : |
| 28 | 28 | video=efifb:i20 |
| 29 | 29 | |
| 30 | +Accepted options: | |
| 31 | + | |
| 32 | +nowc Don't map the framebuffer write combined. This can be used | |
| 33 | + to workaround side-effects and slowdowns on other CPU cores | |
| 34 | + when large amounts of console data are written. | |
| 35 | + | |
| 30 | 36 | -- |
| 31 | 37 | Edgar Hucek <gimli@dark-green.com> |
| @@ -459,7 +459,7 @@ pin controller? · 458 unmodified lines | ||
| 459 | 459 | |
| 460 | 460 | This is done by registering "ranges" of pins, which are essentially |
| 461 | 461 | cross-reference tables. These are described in |
| 462 | −Documentation/pinctrl.txt | |
| 462 | +Documentation/driver-api/pinctl.rst | |
| 463 | 463 | |
| 464 | 464 | While the pin allocation is totally managed by the pinctrl subsystem, |
| 465 | 465 | gpio (under gpiolib) is still maintained by gpio drivers. It may happen |
| @@ -1,6 +1,31 @@ | ||
| 1 | 1 | Digital TV (DVB) devices |
| 2 | 2 | ------------------------ |
| 3 | 3 | |
| 4 | +Digital TV devices are implemented by several different drivers: | |
| 5 | + | |
| 6 | +- A bridge driver that is responsible to talk with the bus where the other | |
| 7 | + devices are connected (PCI, USB, SPI), bind to the other drivers and | |
| 8 | + implement the digital demux logic (either in software or in hardware); | |
| 9 | + | |
| 10 | +- Frontend drivers that are usually implemented as two separate drivers: | |
| 11 | + | |
| 12 | + - A tuner driver that implements the logic with commands the part of the | |
| 13 | + hardware with is reponsible to tune into a digital TV transponder or | |
| 14 | + physical channel. The output of a tuner is usually a baseband or | |
| 15 | + Intermediate Frequency (IF) signal; | |
| 16 | + | |
| 17 | + - A demodulator driver (a.k.a "demod") that implements the logic with | |
| 18 | + commands the digital TV decoding hardware. The output of a demod is | |
| 19 | + a digital stream, with multiple audio, video and data channels typically | |
| 20 | + multiplexed using MPEG Transport Stream [#f1]_. | |
| 21 | + | |
| 22 | +On most hardware, the frontend drivers talk with the bridge driver using an | |
| 23 | +I2C bus. | |
| 24 | + | |
| 25 | +.. [#f1] Some standards use TCP/IP for multiplexing data, like DVB-H (an | |
| 26 | + abandoned standard, not used anymore) and ATSC version 3.0 current | |
| 27 | + proposals. Currently, the DVB subsystem doesn't implement those standards. | |
| 28 | + | |
| 4 | 29 | Digital TV Common functions |
| 5 | 30 | --------------------------- |
| 6 | 31 | |
| @@ -55,8 +80,141 @@ Digital TV Frontend · 48 unmodified lines | ||
| 55 | 80 | The Digital TV Frontend kABI defines a driver-internal interface for |
| 56 | 81 | registering low-level, hardware specific driver to a hardware independent |
| 57 | 82 | frontend layer. It is only of interest for Digital TV device driver writers. |
| 58 | −The header file for this API is named dvb_frontend.h and located in | |
| 59 | −drivers/media/dvb-core. | |
| 83 | +The header file for this API is named ``dvb_frontend.h`` and located in | |
| 84 | +``drivers/media/dvb-core``. | |
| 85 | + | |
| 86 | +Demodulator driver | |
| 87 | +^^^^^^^^^^^^^^^^^^ | |
| 88 | + | |
| 89 | +The demodulator driver is responsible to talk with the decoding part of the | |
| 90 | +hardware. Such driver should implement :c:type:`dvb_frontend_ops`, with | |
| 91 | +tells what type of digital TV standards are supported, and points to a | |
| 92 | +series of functions that allow the DVB core to command the hardware via | |
| 93 | +the code under ``drivers/media/dvb-core/dvb_frontend.c``. | |
| 94 | + | |
| 95 | +A typical example of such struct in a driver ``foo`` is:: | |
| 96 | + | |
| 97 | + static struct dvb_frontend_ops foo_ops = { | |
| 98 | + .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A }, | |
| 99 | + .info = { | |
| 100 | + .name = "foo DVB-T/T2/C driver", | |
| 101 | + .caps = FE_CAN_FEC_1_2 | | |
| 102 | + FE_CAN_FEC_2_3 | | |
| 103 | + FE_CAN_FEC_3_4 | | |
| 104 | + FE_CAN_FEC_5_6 | | |
| 105 | + FE_CAN_FEC_7_8 | | |
| 106 | + FE_CAN_FEC_AUTO | | |
| 107 | + FE_CAN_QPSK | | |
| 108 | + FE_CAN_QAM_16 | | |
| 109 | + FE_CAN_QAM_32 | | |
| 110 | + FE_CAN_QAM_64 | | |
| 111 | + FE_CAN_QAM_128 | | |
| 112 | + FE_CAN_QAM_256 | | |
| 113 | + FE_CAN_QAM_AUTO | | |
| 114 | + FE_CAN_TRANSMISSION_MODE_AUTO | | |
| 115 | + FE_CAN_GUARD_INTERVAL_AUTO | | |
| 116 | + FE_CAN_HIERARCHY_AUTO | | |
| 117 | + FE_CAN_MUTE_TS | | |
| 118 | + FE_CAN_2G_MODULATION, | |
| 119 | + .frequency_min = 42000000, /* Hz */ | |
| 120 | + .frequency_max = 1002000000, /* Hz */ | |
| 121 | + .symbol_rate_min = 870000, | |
| 122 | + .symbol_rate_max = 11700000 | |
| 123 | + }, | |
| 124 | + .init = foo_init, | |
| 125 | + .sleep = foo_sleep, | |
| 126 | + .release = foo_release, | |
| 127 | + .set_frontend = foo_set_frontend, | |
| 128 | + .get_frontend = foo_get_frontend, | |
| 129 | + .read_status = foo_get_status_and_stats, | |
| 130 | + .tune = foo_tune, | |
| 131 | + .i2c_gate_ctrl = foo_i2c_gate_ctrl, | |
| 132 | + .get_frontend_algo = foo_get_algo, | |
| 133 | + }; | |
| 134 | + | |
| 135 | +A typical example of such struct in a driver ``bar`` meant to be used on | |
| 136 | +Satellite TV reception is:: | |
| 137 | + | |
| 138 | + static const struct dvb_frontend_ops bar_ops = { | |
| 139 | + .delsys = { SYS_DVBS, SYS_DVBS2 }, | |
| 140 | + .info = { | |
| 141 | + .name = "Bar DVB-S/S2 demodulator", | |
| 142 | + .frequency_min = 500000, /* KHz */ | |
| 143 | + .frequency_max = 2500000, /* KHz */ | |
| 144 | + .frequency_stepsize = 0, | |
| 145 | + .symbol_rate_min = 1000000, | |
| 146 | + .symbol_rate_max = 45000000, | |
| 147 | + .symbol_rate_tolerance = 500, | |
| 148 | + .caps = FE_CAN_INVERSION_AUTO | | |
| 149 | + FE_CAN_FEC_AUTO | | |
| 150 | + FE_CAN_QPSK, | |
| 151 | + }, | |
| 152 | + .init = bar_init, | |
| 153 | + .sleep = bar_sleep, | |
| 154 | + .release = bar_release, | |
| 155 | + .set_frontend = bar_set_frontend, | |
| 156 | + .get_frontend = bar_get_frontend, | |
| 157 | + .read_status = bar_get_status_and_stats, | |
| 158 | + .i2c_gate_ctrl = bar_i2c_gate_ctrl, | |
| 159 | + .get_frontend_algo = bar_get_algo, | |
| 160 | + .tune = bar_tune, | |
| 161 | + | |
| 162 | + /* Satellite-specific */ | |
| 163 | + .diseqc_send_master_cmd = bar_send_diseqc_msg, | |
| 164 | + .diseqc_send_burst = bar_send_burst, | |
| 165 | + .set_tone = bar_set_tone, | |
| 166 | + .set_voltage = bar_set_voltage, | |
| 167 | + }; | |
| 168 | + | |
| 169 | +.. note:: | |
| 170 | + | |
| 171 | + #) For satellite digital TV standards (DVB-S, DVB-S2, ISDB-S), the | |
| 172 | + frequencies are specified in kHz, while, for terrestrial and cable | |
| 173 | + standards, they're specified in Hz. Due to that, if the same frontend | |
| 174 | + supports both types, you'll need to have two separate | |
| 175 | + :c:type:`dvb_frontend_ops` structures, one for each standard. | |
| 176 | + #) The ``.i2c_gate_ctrl`` field is present only when the hardware has | |
| 177 | + allows controlling an I2C gate (either directly of via some GPIO pin), | |
| 178 | + in order to remove the tuner from the I2C bus after a channel is | |
| 179 | + tuned. | |
| 180 | + #) All new drivers should implement the | |
| 181 | + :ref:`DVBv5 statistics <dvbv5_stats>` via ``.read_status``. | |
| 182 | + Yet, there are a number of callbacks meant to get statistics for | |
| 183 | + signal strength, S/N and UCB. Those are there to provide backward | |
| 184 | + compatibility with legacy applications that don't support the DVBv5 | |
| 185 | + API. Implementing those callbacks are optional. Those callbacks may be | |
| 186 | + removed in the future, after we have all existing drivers supporting | |
| 187 | + DVBv5 stats. | |
| 188 | + #) Other callbacks are required for satellite TV standards, in order to | |
| 189 | + control LNBf and DiSEqC: ``.diseqc_send_master_cmd``, | |
| 190 | + ``.diseqc_send_burst``, ``.set_tone``, ``.set_voltage``. | |
| 191 | + | |
| 192 | +.. |delta| unicode:: U+00394 | |
| 193 | + | |
| 194 | +The ``drivers/media/dvb-core/dvb_frontend.c`` has a kernel thread with is | |
| 195 | +responsible for tuning the device. It supports multiple algoritms to | |
| 196 | +detect a channel, as defined at enum :c:func:`dvbfe_algo`. | |
| 197 | + | |
| 198 | +The algorithm to be used is obtained via ``.get_frontend_algo``. If the driver | |
| 199 | +doesn't fill its field at struct :c:type:`dvb_frontend_ops`, it will default to | |
| 200 | +``DVBFE_ALGO_SW``, meaning that the dvb-core will do a zigzag when tuning, | |
| 201 | +e. g. it will try first to use the specified center frequency ``f``, | |
| 202 | +then, it will do ``f`` + |delta|, ``f`` - |delta|, ``f`` + 2 x |delta|, | |
| 203 | +``f`` - 2 x |delta| and so on. | |
| 204 | + | |
| 205 | +If the hardware has internally a some sort of zigzag algorithm, you should | |
| 206 | +define a ``.get_frontend_algo`` function that would return ``DVBFE_ALGO_HW``. | |
| 207 | + | |
| 208 | +.. note:: | |
| 209 | + | |
| 210 | + The core frontend support also supports | |
| 211 | + a third type (``DVBFE_ALGO_CUSTOM``), in order to allow the driver to | |
| 212 | + define its own hardware-assisted algorithm. Very few hardware need to | |
| 213 | + use it nowadays. Using ``DVBFE_ALGO_CUSTOM`` require to provide other | |
| 214 | + function callbacks at struct :c:type:`dvb_frontend_ops`. | |
| 215 | + | |
| 216 | +Attaching frontend driver to the bridge driver | |
| 217 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
| 60 | 218 | |
| 61 | 219 | Before using the Digital TV frontend core, the bridge driver should attach |
| 62 | 220 | the frontend demod, tuner and SEC devices and call |
| @@ -74,6 +232,287 @@ part of their handler for :c:type:`device_driver`.\ ``resume()``. · 11 unmodified lines | ||
| 74 | 232 | |
| 75 | 233 | A few other optional functions are provided to handle some special cases. |
| 76 | 234 | |
| 235 | +.. _dvbv5_stats: | |
| 236 | + | |
| 237 | +Digital TV Frontend statistics | |
| 238 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 239 | + | |
| 240 | +Introduction | |
| 241 | +^^^^^^^^^^^^ | |
| 242 | + | |
| 243 | +Digital TV frontends provide a range of | |
| 244 | +:ref:`statistics <frontend-stat-properties>` meant to help tuning the device | |
| 245 | +and measuring the quality of service. | |
| 246 | + | |
| 247 | +For each statistics measurement, the driver should set the type of scale used, | |
| 248 | +or ``FE_SCALE_NOT_AVAILABLE`` if the statistics is not available on a given | |
| 249 | +time. Drivers should also provide the number of statistics for each type. | |
| 250 | +that's usually 1 for most video standards [#f2]_. | |
| 251 | + | |
| 252 | +Drivers should initialize each statistic counters with length and | |
| 253 | +scale at its init code. For example, if the frontend provides signal | |
| 254 | +strength, it should have, on its init code:: | |
| 255 | + | |
| 256 | + struct dtv_frontend_properties *c = &state->fe.dtv_property_cache; | |
| 257 | + | |
| 258 | + c->strength.len = 1; | |
| 259 | + c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
| 260 | + | |
| 261 | +And, when the statistics got updated, set the scale:: | |
| 262 | + | |
| 263 | + c->strength.stat[0].scale = FE_SCALE_DECIBEL; | |
| 264 | + c->strength.stat[0].uvalue = strength; | |
| 265 | + | |
| 266 | +.. [#f2] For ISDB-T, it may provide both a global statistics and a per-layer | |
| 267 | + set of statistics. On such cases, len should be equal to 4. The first | |
| 268 | + value corresponds to the global stat; the other ones to each layer, e. g.: | |
| 269 | + | |
| 270 | + - c->cnr.stat[0] for global S/N carrier ratio, | |
| 271 | + - c->cnr.stat[1] for Layer A S/N carrier ratio, | |
| 272 | + - c->cnr.stat[2] for layer B S/N carrier ratio, | |
| 273 | + - c->cnr.stat[3] for layer C S/N carrier ratio. | |
| 274 | + | |
| 275 | +.. note:: Please prefer to use ``FE_SCALE_DECIBEL`` instead of | |
| 276 | + ``FE_SCALE_RELATIVE`` for signal strength and CNR measurements. | |
| 277 | + | |
| 278 | +Groups of statistics | |
| 279 | +^^^^^^^^^^^^^^^^^^^^ | |
| 280 | + | |
| 281 | +There are several groups of statistics currently supported: | |
| 282 | + | |
| 283 | +Signal strength (:ref:`DTV-STAT-SIGNAL-STRENGTH`) | |
| 284 | + - Measures the signal strength level at the analog part of the tuner or | |
| 285 | + demod. | |
| 286 | + | |
| 287 | + - Typically obtained from the gain applied to the tuner and/or frontend | |
| 288 | + in order to detect the carrier. When no carrier is detected, the gain is | |
| 289 | + at the maximum value (so, strength is on its minimal). | |
| 290 | + | |
| 291 | + - As the gain is visible through the set of registers that adjust the gain, | |
| 292 | + typically, this statistics is always available [#f3]_. | |
| 293 | + | |
| 294 | + - Drivers should try to make it available all the times, as this statistics | |
| 295 | + can be used when adjusting an antenna position and to check for troubles | |
| 296 | + at the cabling. | |
| 297 | + | |
| 298 | + .. [#f3] On a few devices, the gain keeps floating if no carrier. | |
| 299 | + On such devices, strength report should check first if carrier is | |
| 300 | + detected at the tuner (``FE_HAS_CARRIER``, see :c:type:`fe_status`), | |
| 301 | + and otherwise return the lowest possible value. | |
| 302 | + | |
| 303 | +Carrier Signal to Noise ratio (:ref:`DTV-STAT-CNR`) | |
| 304 | + - Signal to Noise ratio for the main carrier. | |
| 305 | + | |
| 306 | + - Signal to Noise measurement depends on the device. On some hardware, is | |
| 307 | + available when the main carrier is detected. On those hardware, CNR | |
| 308 | + measurement usually comes from the tuner (e. g. after ``FE_HAS_CARRIER``, | |
| 309 | + see :c:type:`fe_status`). | |
| 310 | + | |
| 311 | + On other devices, it requires inner FEC decoding, | |
| 312 | + as the frontend measures it indirectly from other parameters (e. g. after | |
| 313 | + ``FE_HAS_VITERBI``, see :c:type:`fe_status`). | |
| 314 | + | |
| 315 | + Having it available after inner FEC is more common. | |
| 316 | + | |
| 317 | +Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`) | |
| 318 | + - Those counters measure the number of bits and bit errors errors after | |
| 319 | + the forward error correction (FEC) on the inner coding block | |
| 320 | + (after Viterbi, LDPC or other inner code). | |
| 321 | + | |
| 322 | + - Due to its nature, those statistics depend on full coding lock | |
| 323 | + (e. g. after ``FE_HAS_SYNC`` or after ``FE_HAS_LOCK``, | |
| 324 | + see :c:type:`fe_status`). | |
| 325 | + | |
| 326 | +Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`) | |
| 327 | + - Those counters measure the number of bits and bit errors errors before | |
| 328 | + the forward error correction (FEC) on the inner coding block | |
| 329 | + (before Viterbi, LDPC or other inner code). | |
| 330 | + | |
| 331 | + - Not all frontends provide this kind of statistics. | |
| 332 | + | |
| 333 | + - Due to its nature, those statistics depend on inner coding lock (e. g. | |
| 334 | + after ``FE_HAS_VITERBI``, see :c:type:`fe_status`). | |
| 335 | + | |
| 336 | +Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`) | |
| 337 | + - Those counters measure the number of blocks and block errors errors after | |
| 338 | + the forward error correction (FEC) on the inner coding block | |
| 339 | + (before Viterbi, LDPC or other inner code). | |
| 340 | + | |
| 341 | + - Due to its nature, those statistics depend on full coding lock | |
| 342 | + (e. g. after ``FE_HAS_SYNC`` or after | |
| 343 | + ``FE_HAS_LOCK``, see :c:type:`fe_status`). | |
| 344 | + | |
| 345 | +.. note:: All counters should be monotonically increased as they're | |
| 346 | + collected from the hardware. | |
| 347 | + | |
| 348 | +A typical example of the logic that handle status and statistics is:: | |
| 349 | + | |
| 350 | + static int foo_get_status_and_stats(struct dvb_frontend *fe) | |
| 351 | + { | |
| 352 | + struct foo_state *state = fe->demodulator_priv; | |
| 353 | + struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
| 354 | + | |
| 355 | + int rc; | |
| 356 | + enum fe_status *status; | |
| 357 | + | |
| 358 | + /* Both status and strength are always available */ | |
| 359 | + rc = foo_read_status(fe, &status); | |
| 360 | + if (rc < 0) | |
| 361 | + return rc; | |
| 362 | + | |
| 363 | + rc = foo_read_strength(fe); | |
| 364 | + if (rc < 0) | |
| 365 | + return rc; | |
| 366 | + | |
| 367 | + /* Check if CNR is available */ | |
| 368 | + if (!(fe->status & FE_HAS_CARRIER)) | |
| 369 | + return 0; | |
| 370 | + | |
| 371 | + rc = foo_read_cnr(fe); | |
| 372 | + if (rc < 0) | |
| 373 | + return rc; | |
| 374 | + | |
| 375 | + /* Check if pre-BER stats are available */ | |
| 376 | + if (!(fe->status & FE_HAS_VITERBI)) | |
| 377 | + return 0; | |
| 378 | + | |
| 379 | + rc = foo_get_pre_ber(fe); | |
| 380 | + if (rc < 0) | |
| 381 | + return rc; | |
| 382 | + | |
| 383 | + /* Check if post-BER stats are available */ | |
| 384 | + if (!(fe->status & FE_HAS_SYNC)) | |
| 385 | + return 0; | |
| 386 | + | |
| 387 | + rc = foo_get_post_ber(fe); | |
| 388 | + if (rc < 0) | |
| 389 | + return rc; | |
| 390 | + } | |
| 391 | + | |
| 392 | + static const struct dvb_frontend_ops ops = { | |
| 393 | + /* ... */ | |
| 394 | + .read_status = foo_get_status_and_stats, | |
| 395 | + }; | |
| 396 | + | |
| 397 | +Statistics collect | |
| 398 | +^^^^^^^^^^^^^^^^^^ | |
| 399 | + | |
| 400 | +On almost all frontend hardware, the bit and byte counts are stored by | |
| 401 | +the hardware after a certain amount of time or after the total bit/block | |
| 402 | +counter reaches a certain value (usually programable), for example, on | |
| 403 | +every 1000 ms or after receiving 1,000,000 bits. | |
| 404 | + | |
| 405 | +So, if you read the registers too soon, you'll end by reading the same | |
| 406 | +value as in the previous reading, causing the monotonic value to be | |
| 407 | +incremented too often. | |
| 408 | + | |
| 409 | +Drivers should take the responsibility to avoid too often reads. That | |
| 410 | +can be done using two approaches: | |
| 411 | + | |
| 412 | +if the driver have a bit that indicates when a collected data is ready | |
| 413 | +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | |
| 414 | + | |
| 415 | +Driver should check such bit before making the statistics available. | |
| 416 | + | |
| 417 | +An example of such behavior can be found at this code snippet (adapted | |
| 418 | +from mb86a20s driver's logic):: | |
| 419 | + | |
| 420 | + static int foo_get_pre_ber(struct dvb_frontend *fe) | |
| 421 | + { | |
| 422 | + struct foo_state *state = fe->demodulator_priv; | |
| 423 | + struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
| 424 | + int rc, bit_error; | |
| 425 | + | |
| 426 | + /* Check if the BER measures are already available */ | |
| 427 | + rc = foo_read_u8(state, 0x54); | |
| 428 | + if (rc < 0) | |
| 429 | + return rc; | |
| 430 | + | |
| 431 | + if (!rc) | |
| 432 | + return 0; | |
| 433 | + | |
| 434 | + /* Read Bit Error Count */ | |
| 435 | + bit_error = foo_read_u32(state, 0x55); | |
| 436 | + if (bit_error < 0) | |
| 437 | + return bit_error; | |
| 438 | + | |
| 439 | + /* Read Total Bit Count */ | |
| 440 | + rc = foo_read_u32(state, 0x51); | |
| 441 | + if (rc < 0) | |
| 442 | + return rc; | |
| 443 | + | |
| 444 | + c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
| 445 | + c->pre_bit_error.stat[0].uvalue += bit_error; | |
| 446 | + c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
| 447 | + c->pre_bit_count.stat[0].uvalue += rc; | |
| 448 | + | |
| 449 | + return 0; | |
| 450 | + } | |
| 451 | + | |
| 452 | +If the driver doesn't provide a statistics available check bit | |
| 453 | +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | |
| 454 | + | |
| 455 | +A few devices, however, may not provide a way to check if the stats are | |
| 456 | +available (or the way to check it is unknown). They may not even provide | |
| 457 | +a way to directly read the total number of bits or blocks. | |
| 458 | + | |
| 459 | +On those devices, the driver need to ensure that it won't be reading from | |
| 460 | +the register too often and/or estimate the total number of bits/blocks. | |
| 461 | + | |
| 462 | +On such drivers, a typical routine to get statistics would be like | |
| 463 | +(adapted from dib8000 driver's logic):: | |
| 464 | + | |
| 465 | + struct foo_state { | |
| 466 | + /* ... */ | |
| 467 | + | |
| 468 | + unsigned long per_jiffies_stats; | |
| 469 | + } | |
| 470 | + | |
| 471 | + static int foo_get_pre_ber(struct dvb_frontend *fe) | |
| 472 | + { | |
| 473 | + struct foo_state *state = fe->demodulator_priv; | |
| 474 | + struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
| 475 | + int rc, bit_error; | |
| 476 | + u64 bits; | |
| 477 | + | |
| 478 | + /* Check if time for stats was elapsed */ | |
| 479 | + if (!time_after(jiffies, state->per_jiffies_stats)) | |
| 480 | + return 0; | |
| 481 | + | |
| 482 | + /* Next stat should be collected in 1000 ms */ | |
| 483 | + state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); | |
| 484 | + | |
| 485 | + /* Read Bit Error Count */ | |
| 486 | + bit_error = foo_read_u32(state, 0x55); | |
| 487 | + if (bit_error < 0) | |
| 488 | + return bit_error; | |
| 489 | + | |
| 490 | + /* | |
| 491 | + * On this particular frontend, there's no register that | |
| 492 | + * would provide the number of bits per 1000ms sample. So, | |
| 493 | + * some function would calculate it based on DTV properties | |
| 494 | + */ | |
| 495 | + bits = get_number_of_bits_per_1000ms(fe); | |
| 496 | + | |
| 497 | + c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
| 498 | + c->pre_bit_error.stat[0].uvalue += bit_error; | |
| 499 | + c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
| 500 | + c->pre_bit_count.stat[0].uvalue += bits; | |
| 501 | + | |
| 502 | + return 0; | |
| 503 | + } | |
| 504 | + | |
| 505 | +Please notice that, on both cases, we're getting the statistics using the | |
| 506 | +:c:type:`dvb_frontend_ops` ``.read_status`` callback. The rationale is that | |
| 507 | +the frontend core will automatically call this function periodically | |
| 508 | +(usually, 3 times per second, when the frontend is locked). | |
| 509 | + | |
| 510 | +That warrants that we won't miss to collect a counter and increment the | |
| 511 | +monotonic stats at the right time. | |
| 512 | + | |
| 513 | +Digital TV Frontend functions and types | |
| 514 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 515 | + | |
| 77 | 516 | .. kernel-doc:: drivers/media/dvb-core/dvb_frontend.h |
| 78 | 517 | |
| 79 | 518 | |
| @@ -1,2948 +1,106 @@ | ||
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| 4 | +fill="#000000" font-family="Serif, serif" font-size="493.88px">Audio decoder</tspan></tspan></tspan></text> | |
| 5 | +<path id="path37" d="m2371.5 9608h-2260v-1270h4520v1270h-2260z" fill="#ff8080" style=""/><path id="path39" d="m2371.5 9608h-2260v-1270h4520v1270h-2260z" fill="none" stroke="#3465af" style=""/><text id="text41" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan43" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan45" class="TextPosition" x="527.5459" y="9189.0127" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan47" fill="#000000" font-family="Serif, serif" font-size="493.88px">Video decoder</tspan></tspan></tspan></text> | |
| 6 | +<path id="path51" d="m2363.5 8053h-2269v-1224h4537v1224h-2268z" fill="#ff8080" style=""/><path id="path53" d="m2363.5 8053h-2269v-1224h4537v1224h-2268z" fill="none" stroke="#3465af" style=""/><text id="text55" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan57" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan59" class="TextPosition" x="481.5459" y="7657.0132" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan61" fill="#000000" font-family="Serif, serif" font-size="493.88px">Audio encoder</tspan></tspan></tspan></text> | |
| 7 | +<path id="path65" d="m13622 10386h-3810v-1281h7620v1281h-3810z" fill="#cfc" style=""/><path id="path67" d="m13622 10386h-3810v-1281h7620v1281h-3810z" fill="none" stroke="#3465af" style=""/><text id="text69" class="TextShape" x="-2089.4541" y="-2446.187" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan71" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan73" class="TextPosition" x="10287.546" y="9960.8135" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan75" fill="#000000" font-family="Serif, serif" font-size="493.88px">Button Key/IR input logic</tspan></tspan></tspan></text> | |
| 8 | +<path id="path79" d="m12080 12182h-2268v-1412h4536v1412h-2268z" fill="#cfe7f5" style=""/><path id="path81" d="m12080 12182h-2268v-1412h4536v1412h-2268z" fill="none" stroke="#3465af" style=""/><text id="text83" class="TextShape" x="-2089.4541" y="-2389.7871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan85" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan87" class="TextPosition" x="10792.546" y="11692.213" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan89" fill="#000000" font-family="Serif, serif" font-size="493.88px">EEPROM</tspan></tspan></tspan></text> | |
| 9 | +<path id="path93" d="m3050.5 15498h-1563v-1715h3126v1715h-1563z" fill="#fc9" style=""/><path id="path95" d="m3050.5 15498h-1563v-1715h3126v1715h-1563z" fill="none" stroke="#3465af" style=""/><text id="text97" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan99" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan101" class="TextPosition" x="2186.5459" y="14856.013" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan103" fill="#000000" font-family="Serif, serif" font-size="493.88px">Sensor</tspan></tspan></tspan></text> | |
| 10 | +<path id="path107" d="m4629.5 5866 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="#729fcf" style=""/><path id="path109" d="m4629.5 5866 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path113" d="m4629.5 7448 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="#729fcf" style=""/><path id="path115" d="m4629.5 7448 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path119" d="m4631.5 8936 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="#729fcf" style=""/><path id="path121" d="m4631.5 8936 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path125" d="m7872.5 11464 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" | |
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| 12 | +840.89-978.49 840.89v-420.86h-2960.5v420.86l-979.49-840.89 979.49-840.89v420.03h2960.5v-420.03z" fill="none" stroke="#3465af" stroke-width="25.77" style=""/><text id="text149" class="TextShape" x="-9922.1533" y="-644.58704" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan151" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan153" class="TextPosition" transform="matrix(0,-1,1,0,8509,40173)" x="14418.847" y="15187.413" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan155" fill="#000000" font-family="Serif, serif" font-size="493.88px">System Bus</tspan></tspan></tspan></text> | |
| 13 | +<path id="path159" d="m11062 7098h-1250v-875h2499v875h-1249z" fill="#cff" style=""/><path id="path161" d="m11062 7098h-1250v-875h2499v875h-1249z" fill="none" stroke="#3465af" style=""/><text id="text163" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan165" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan167" class="TextPosition" x="10125.546" y="6876.0132" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan169" fill="#000000" font-family="Serif, serif" font-size="493.88px">Demux</tspan></tspan></tspan></text> | |
| 14 | +<path id="path173" d="m7906.5 6601 373-357v178h1130v-178l374 357-374 358v-179h-1130v179l-373-358z" fill="#729fcf" style=""/><path id="path175" d="m7906.5 6601 373-357v178h1130v-178l374 357-374 358v-179h-1130v179l-373-358z" fill="none" stroke="#3465af" style=""/><path id="path179" d="m7906.5 5214 373-358v179h1130v-179l374 358-374 358v-179h-1130v179l-373-358z" fill="#729fcf" style=""/><path id="path181" d="m7906.5 5214 373-358v179h1130v-179l374 358-374 358v-179h-1130v179l-373-358z" fill="none" stroke="#3465af" style=""/><path id="path185" d="m14233 5828h-4421v-1270h8841v1270h-4420z" fill="#cff" style=""/><path id="path187" d="m14233 5828h-4421v-1270h8841v1270h-4420z" fill="none" stroke="#3465af" style=""/><text id="text189" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan191" class="TextParagraph" font-family="Serif, serif" | |
| 15 | +font-size="493.88px"><tspan id="tspan193" class="TextPosition" x="10696.546" y="5409.0132" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan195" fill="#000000" font-family="Serif, serif" font-size="493.88px">Conditional Access Module</tspan></tspan></tspan></text> | |
| 16 | +<path id="path199" d="m2355.5 11123h-2269v-1224h4537v1224h-2268z" fill="#ff8080" style=""/><path id="path201" d="m2355.5 11123h-2269v-1224h4537v1224h-2268z" fill="none" stroke="#3465af" style=""/><text id="text203" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan205" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan207" class="TextPosition" x="511.5459" y="10727.013" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan209" fill="#000000" font-family="Serif, serif" font-size="493.88px">Video encoder</tspan></tspan></tspan></text> | |
| 17 | +<path id="path213" d="m4631.5 10470 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="#729fcf" style=""/><path id="path215" d="m4631.5 10470 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path219" d="m18702 5381 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="#729fcf" style=""/><path id="path221" d="m18702 5381 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="none" stroke="#3465af" style=""/><text id="text225" class="TextShape" x="-1976.5541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan227" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan229" class="TextPosition" x="13.4459" y="12314.013" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan231" fill="#000000" | |
| 18 | +font-family="Serif, serif" font-size="493.88px">Radio / Analog TV</tspan></tspan></tspan></text> | |
| 19 | +<text id="text235" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan237" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan239" class="TextPosition" x="12866.546" y="8560.0127" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan241" fill="#000000" font-family="Serif, serif" font-size="493.88px">Digital TV</tspan></tspan></tspan></text> | |
| 20 | +<text id="text245" class="TextShape" x="-8919.0537" y="-1373.787" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan247" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan249" class="TextPosition" x="5804.9458" y="17793.213" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan251" fill="#000000" font-family="Serif, serif" font-size="493.88px">PS.: picture is not complete: other blocks may be present</tspan></tspan></tspan></text> | |
| 21 | +<text id="text255" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan257" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan259" class="TextPosition" x="2109.5459" y="16397.014" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan261" fill="#000000" font-family="Serif, serif" font-size="493.88px">Webcam</tspan></tspan></tspan></text> | |
| 22 | +<path id="path265" d="m12463 13926h-2650v-1412h5299v1412h-2649z" fill="#f90" style=""/><path id="path267" d="m12463 13926h-2650v-1412h5299v1412h-2649z" fill="none" stroke="#3465af" style=""/><text id="text269" class="TextShape" x="-2089.4541" y="-2446.187" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan271" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan273" class="TextPosition" x="10175.546" y="13435.813" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan275" fill="#000000" font-family="Serif, serif" font-size="493.88px">Processing blocks</tspan></tspan></tspan></text> | |
| 23 | +<path id="path279" d="m7872.5 13208 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="#729fcf" style=""/><path id="path281" d="m7872.5 13208 385-353v176h1166v-176l386 353-386 354v-177h-1166v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path285" d="m4612.5 14790 397-353v176h1201v-176l398 353-398 354v-177h-1201v177l-397-354z" fill="#729fcf" style=""/><path id="path287" d="m4612.5 14790 397-353v176h1201v-176l398 353-398 354v-177h-1201v177l-397-354z" fill="none" stroke="#3465af" style=""/><text id="text291" class="TextShape" x="-2428.0542" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan293" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan295" class="TextPosition" x="20421.945" y="6628.0132" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan297" fill="#000000" | |
| 24 | +font-family="Serif, serif" font-size="493.88px">Smartcard</tspan></tspan></tspan></text> | |
| 25 | +<path id="path301" d="m623.32 436.01c-334.6 0-669.2 333-669.2 666v2668c0 333 334.6 666 669.2 666h18456c334.6 0 670.2-333 670.2-666v-2668c0-333-335.6-666-670.2-666h-18456z" fill="#fcf" style=""/><path id="path305" d="m3031.5 2991h-1614v-1816h3227v1816h-1613z" fill="#ff8080" style=""/><path id="path307" d="m3031.5 2991h-1614v-1816h3227v1816h-1613z" fill="none" stroke="#3465af" style=""/><text id="text309" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan311" class="TextParagraph"><tspan id="tspan313" class="TextPosition" x="2284.5459" y="1947.0129" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan315" fill="#000000" font-family="Serif, serif" font-size="493.88px">Tuner</tspan></tspan></tspan><tspan id="tspan317" class="TextParagraph"><tspan id="tspan319" class="TextPosition" x="2061.5459" y="2650.0129" | |
| 26 | +font-family="Serif, serif" font-size="493.88px"><tspan id="tspan321" fill="#000000" font-family="Serif, serif" font-size="493.88px">FM/TV</tspan></tspan></tspan></text> | |
| 27 | +<path id="path325" d="m812.55 1538c0 111 40 202 88 202h530c48 0 89-91 89-202 0-110-41-202-89-202h-530c-48 0-88 92-88 202z" fill="#ff8080" style=""/><path id="path327" d="m812.55 1538c0 111 40 202 88 202h530c48 0 89-91 89-202 0-110-41-202-89-202h-530c-48 0-88 92-88 202z" fill="none" stroke="#3465af" style=""/><path id="path329" d="m812.55 1538c0 111 40 202 88 202s88-91 88-202c0-110-40-202-88-202s-88 92-88 202z" fill="#ffb3b3" style=""/><path id="path331" d="m812.55 1538c0 111 40 202 88 202s88-91 88-202c0-110-40-202-88-202s-88 92-88 202z" fill="none" stroke="#3465af" style=""/><path id="path335" d="m813.55 2103c0 110 40 202 88 202h530c48 0 89-92 89-202s-41-203-89-203h-530c-48 0-88 93-88 203z" fill="#ff8080" style=""/><path id="path337" d="m813.55 2103c0 110 40 202 88 202h530c48 0 89-92 89-202s-41-203-89-203h-530c-48 0-88 93-88 203z" fill="none" stroke="#3465af" style=""/><path | |
| 28 | +id="path339" d="m813.55 2103c0 110 40 202 88 202s88-92 88-202-40-203-88-203-88 93-88 203z" fill="#ffb3b3" style=""/><path id="path341" d="m813.55 2103c0 110 40 202 88 202s88-92 88-202-40-203-88-203-88 93-88 203z" fill="none" stroke="#3465af" style=""/><path id="path345" d="m4629.5 2032 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="#729fcf" style=""/><path id="path347" d="m4629.5 2032 385-353v176h1167v-176l386 353-386 354v-177h-1167v177l-385-354z" fill="none" stroke="#3465af" style=""/><path id="path351" d="m7889.5 1986 402-368v184h1217v-184l403 368-403 369v-185h-1217v185l-402-369z" fill="#729fcf" style=""/><path id="path353" d="m7889.5 1986 402-368v184h1217v-184l403 368-403 369v-185h-1217v185l-402-369z" fill="none" stroke="#3465af" style=""/><path id="path357" d="m14411 4025h-4500v-1389h9e3v1389h-4500z" fill="#cff" style=""/><path id="path359" d="m14411 | |
| 29 | +4025h-4500v-1389h9e3v1389h-4500z" fill="none" stroke="#3465af" style=""/><text id="text361" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan363" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan365" class="TextPosition" x="9961.5459" y="3546.0129" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan367" fill="#000000" font-family="Serif, serif" font-size="493.88px">Satellite Equipment Control (SEC)</tspan></tspan></tspan></text> | |
| 30 | +<path id="path371" d="m11311 2436h-1400v-1e3h2800v1e3h-1400z" fill="#cff" style=""/><path id="path373" d="m11311 2436h-1400v-1e3h2800v1e3h-1400z" fill="none" stroke="#3465af" style=""/><text id="text375" class="TextShape" x="-2089.4541" y="-2163.9871" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan377" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan379" class="TextPosition" x="10375.546" y="2152.0129" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan381" fill="#000000" font-family="Serif, serif" font-size="493.88px">Demod</tspan></tspan></tspan></text> | |
| 31 | +<path id="path385" d="m7889.5 3287 402-368v184h1217v-184l403 368-403 369v-185h-1217v185l-402-369z" fill="#729fcf" style=""/><path id="path387" d="m7889.5 3287 402-368v184h1217v-184l403 368-403 369v-185h-1217v185l-402-369z" fill="none" stroke="#3465af" style=""/><path id="path389" d="m7906.5 9121v7302h-1270v-14605h1270v7303z" fill="#ff9" style=""/><path id="path391" d="m7906.5 9121v7302h-1270v-14605h1270v7303z" fill="none" stroke="#3465af" style=""/><text id="text393" class="TextShape" transform="rotate(-90)" x="-20792.584" y="-6589.021" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan395" class="TextParagraph" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan397" class="TextPosition" transform="matrix(0,-1,1,0,-4473,23627)" x="-11215.646" y="7460.9849" font-family="Serif, serif" font-size="493.88px"><tspan id="tspan399" fill="#000000" font-family="Serif, | |
| 32 | +serif" font-size="493.88px">I2C Bus (control bus)</tspan></tspan></tspan></text> | |
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| 178 | − clip-path="url(#clipPath84)" | |
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| 180 | − inkscape:connector-curvature="0" | |
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| 182 | − style="fill:none;stroke:#000000;stroke-width:2.36249995;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1" | |
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| 179 | + clip-path="url(#clipPath84)" | |
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| 181 | + inkscape:connector-curvature="0" | |
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| 185 | 186 | transform="matrix(0.14375794,0,0,0.14375794,-0.12334269,-0.08856738)"><path |
| 186 | − inkscape:connector-curvature="0" | |
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| 204 | − clip-path="url(#clipPath104)" | |
| 205 | − id="g102"><path | |
| 206 | − inkscape:connector-curvature="0" | |
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| 208 | − style="fill:none;stroke:#000000;stroke-width:2.36249995;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1" | |
| 209 | − d="m 1492.37,1607.5 1559.25,141.75" /></g></g><path | |
| 205 | + clip-path="url(#clipPath104)" | |
| 206 | + id="g102"><path | |
| 207 | + inkscape:connector-curvature="0" | |
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| 209 | + style="fill:none;stroke:#000000;stroke-width:2.36249995;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1" | |
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| @@ -225,43 +226,43 @@ · 12 unmodified lines | ||
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| 227 | 228 | transform="matrix(1.4375794,0,0,1.4375794,-0.12334269,-0.08856738)"><text |
| 228 | − transform="matrix(1,0,0,-1,204.52,9.07751)" | |
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| 232 | − y="0" | |
| 233 | − sodipodi:role="line" | |
| 234 | − id="tspan124">v4l2_cropcap.bounds</tspan></text> | |
| 229 | + transform="matrix(1,0,0,-1,204.52,9.07751)" | |
| 230 | + style="font-variant:normal;font-weight:normal;font-size:6.61499977px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#d10000;fill-opacity:1;fill-rule:nonzero;stroke:none" | |
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| 233 | + y="0" | |
| 234 | + sodipodi:role="line" | |
| 235 | + id="tspan124">v4l2_cropcap.bounds</tspan></text> | |
| 235 | 236 | </g><g |
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| 237 | 238 | transform="matrix(1.4375794,0,0,1.4375794,-0.12334269,-0.08856738)"><text |
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| 242 | − y="0" | |
| 243 | − sodipodi:role="line" | |
| 244 | − id="tspan130">v4l2_cropcap.defrect</tspan></text> | |
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| 243 | + y="0" | |
| 244 | + sodipodi:role="line" | |
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| 253 | − sodipodi:role="line" | |
| 254 | − id="tspan136">v4l2_crop.c</tspan></text> | |
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| 254 | + sodipodi:role="line" | |
| 255 | + id="tspan136">v4l2_crop.c</tspan></text> | |
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| 262 | − y="0" | |
| 263 | − sodipodi:role="line" | |
| 264 | − id="tspan142">v4l2_format</tspan></text> | |
| 259 | + transform="matrix(1,0,0,-1,309.415,30.34)" | |
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| 263 | + y="0" | |
| 264 | + sodipodi:role="line" | |
| 265 | + id="tspan142">v4l2_format</tspan></text> | |
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| @@ -270,12 +271,12 @@ · 2 unmodified lines | ||
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| 271 | 272 | sodipodi:linespacing="125%" |
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| 273 | − sodipodi:role="line" | |
| 274 | − id="tspan3398" | |
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| 276 | − y="-239.49893"></tspan><tspan | |
| 277 | − sodipodi:role="line" | |
| 278 | − x="-99.291145" | |
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| 274 | + sodipodi:role="line" | |
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| 277 | + y="-239.49893"></tspan><tspan | |
| 278 | + sodipodi:role="line" | |
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| @@ -42,15 +42,15 @@ · 41 unmodified lines | ||
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| 51 | + inkscape:connector-curvature="0" | |
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| @@ -1390,13 +1390,13 @@ · 1333 unmodified lines | ||
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| 1394 | + clip-path="url(#clipPath4301)" | |
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| @@ -2466,148 +2466,148 @@ · 1063 unmodified lines | ||
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| 2471 | − y="-533.07098" | |
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| 2473 | − id="tspan4845" | |
| 2474 | − sodipodi:role="line" | |
| 2475 | − y="-465.04559" | |
| 2476 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan><tspan | |
| 2477 | − id="tspan4847" | |
| 2478 | − sodipodi:role="line" | |
| 2479 | − y="-397.0202" | |
| 2480 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2469 | + id="tspan4843" | |
| 2470 | + sodipodi:role="line" | |
| 2471 | + y="-533.07098" | |
| 2472 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464">V4L2_FIELD_TOP</tspan><tspan | |
| 2473 | + id="tspan4845" | |
| 2474 | + sodipodi:role="line" | |
| 2475 | + y="-465.04559" | |
| 2476 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan><tspan | |
| 2477 | + id="tspan4847" | |
| 2478 | + sodipodi:role="line" | |
| 2479 | + y="-397.0202" | |
| 2480 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2481 | 2481 | <text |
| 2482 | 2482 | y="-316.23969" |
| 2483 | 2483 | x="103.58983" |
| 2484 | 2484 | id="text4849" |
| 2485 | 2485 | style="font-variant:normal;font-weight:normal;font-size:8.2495203px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2486 | 2486 | transform="scale(1,-1)"><tspan |
| 2487 | − id="tspan4851" | |
| 2488 | − sodipodi:role="line" | |
| 2489 | − y="-316.23969" | |
| 2490 | − x="103.58983 109.09226 113.67899 118.26572 122.85246 127.43919 132.47964 134.77301 140.27545 144.86218 150.81833 155.40506 160.44553 166.86365 188.62184 194.12427 198.711 203.29774 207.88448 212.47121 217.51166 219.80502 225.30746 229.8942 235.85034 240.43707 245.9395 252.35764 257.3981 262.43854 268.85669 375.69293 381.19534 385.78207 390.3688 394.95554 399.54227 404.58273 406.8761 412.37854 416.96527 422.92142 427.50815 433.01059 439.42871 444.46918 449.50961 455.92776 1.551828 7.0542617 11.640993 16.227724 20.814463 25.401194 30.441652 32.735016 38.237442 42.824177 48.780331 53.367065 58.869492 65.287621 70.328079 75.368538 81.786659">V4L2_FIELD_TOPV4L2_FIELD_BOTTOMV4L2_FIELD_BOTTOMV4L2_FIELD_BOTTOM</tspan><tspan | |
| 2491 | − id="tspan4853" | |
| 2492 | − sodipodi:role="line" | |
| 2493 | − y="-328.99481" | |
| 2494 | − x="10.054964 14.17972 18.766451 20.597849 25.18458 29.771311 34.358047 38.944778 41.238144 43.531509 48.118244 50.865334 53.158699 55.452068 57.283459 61.870193 63.701588 68.288322">v4l2_buffer.field:</tspan></text> | |
| 2487 | + id="tspan4851" | |
| 2488 | + sodipodi:role="line" | |
| 2489 | + y="-316.23969" | |
| 2490 | + x="103.58983 109.09226 113.67899 118.26572 122.85246 127.43919 132.47964 134.77301 140.27545 144.86218 150.81833 155.40506 160.44553 166.86365 188.62184 194.12427 198.711 203.29774 207.88448 212.47121 217.51166 219.80502 225.30746 229.8942 235.85034 240.43707 245.9395 252.35764 257.3981 262.43854 268.85669 375.69293 381.19534 385.78207 390.3688 394.95554 399.54227 404.58273 406.8761 412.37854 416.96527 422.92142 427.50815 433.01059 439.42871 444.46918 449.50961 455.92776 1.551828 7.0542617 11.640993 16.227724 20.814463 25.401194 30.441652 32.735016 38.237442 42.824177 48.780331 53.367065 58.869492 65.287621 70.328079 75.368538 81.786659">V4L2_FIELD_TOPV4L2_FIELD_BOTTOMV4L2_FIELD_BOTTOMV4L2_FIELD_BOTTOM</tspan><tspan | |
| 2491 | + id="tspan4853" | |
| 2492 | + sodipodi:role="line" | |
| 2493 | + y="-328.99481" | |
| 2494 | + x="10.054964 14.17972 18.766451 20.597849 25.18458 29.771311 34.358047 38.944778 41.238144 43.531509 48.118244 50.865334 53.158699 55.452068 57.283459 61.870193 63.701588 68.288322">v4l2_buffer.field:</tspan></text> | |
| 2495 | 2495 | <text |
| 2496 | 2496 | y="-592.59381" |
| 2497 | 2497 | x="5.8034" |
| 2498 | 2498 | id="text4855" |
| 2499 | 2499 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2500 | 2500 | transform="scale(1,-1)"><tspan |
| 2501 | − id="tspan4857" | |
| 2502 | − sodipodi:role="line" | |
| 2503 | − y="-592.59381" | |
| 2504 | − x="5.8034 13.134789 19.806232 29.801399 36.472843 43.144287 47.139954 53.811398 56.475174 59.810898 66.482346 70.478004 77.149452 83.820892 87.816566 91.152283 94.488007 101.15945 107.83089 111.16662 114.50233 121.17377 131.16895 134.50468 137.84041 140.50418 147.17563 149.8394 156.51085 159.84657 163.1823 165.84607 169.84174 175.84123 179.17696 182.51268 185.8484 189.84407 196.51552 203.18695 209.18646 219.18163 221.8454 225.18112 228.51685 235.18829 241.85973 245.19545 249.19112 255.86256 259.19827 265.86972 269.20544 272.54117 282.53635 285.87207 294.53534 301.86673 309.87006 318.53336">Temporal order, bottom field first transmitted (e.g. M/NTSC)</tspan></text> | |
| 2501 | + id="tspan4857" | |
| 2502 | + sodipodi:role="line" | |
| 2503 | + y="-592.59381" | |
| 2504 | + x="5.8034 13.134789 19.806232 29.801399 36.472843 43.144287 47.139954 53.811398 56.475174 59.810898 66.482346 70.478004 77.149452 83.820892 87.816566 91.152283 94.488007 101.15945 107.83089 111.16662 114.50233 121.17377 131.16895 134.50468 137.84041 140.50418 147.17563 149.8394 156.51085 159.84657 163.1823 165.84607 169.84174 175.84123 179.17696 182.51268 185.8484 189.84407 196.51552 203.18695 209.18646 219.18163 221.8454 225.18112 228.51685 235.18829 241.85973 245.19545 249.19112 255.86256 259.19827 265.86972 269.20544 272.54117 282.53635 285.87207 294.53534 301.86673 309.87006 318.53336">Temporal order, bottom field first transmitted (e.g. M/NTSC)</tspan></text> | |
| 2505 | 2505 | <text |
| 2506 | 2506 | y="-316.23981" |
| 2507 | 2507 | x="290.6604" |
| 2508 | 2508 | id="text4859" |
| 2509 | 2509 | style="font-variant:normal;font-weight:normal;font-size:8.2495203px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2510 | 2510 | transform="scale(1,-1)"><tspan |
| 2511 | − id="tspan4861" | |
| 2512 | − sodipodi:role="line" | |
| 2513 | − y="-316.23981" | |
| 2514 | − x="290.6604 296.16284 300.74957 305.3363 309.92303 314.50977 319.55023 321.8436 327.34601 331.93274 337.88889 342.47565 347.51608 353.9342 477.73062 483.23306 487.81979 492.40652 496.99326 501.57999 506.62045 508.91382 514.41626 519.00299 524.95911 529.5459 534.5863 541.00446">V4L2_FIELD_TOPV4L2_FIELD_TOP</tspan></text> | |
| 2511 | + id="tspan4861" | |
| 2512 | + sodipodi:role="line" | |
| 2513 | + y="-316.23981" | |
| 2514 | + x="290.6604 296.16284 300.74957 305.3363 309.92303 314.50977 319.55023 321.8436 327.34601 331.93274 337.88889 342.47565 347.51608 353.9342 477.73062 483.23306 487.81979 492.40652 496.99326 501.57999 506.62045 508.91382 514.41626 519.00299 524.95911 529.5459 534.5863 541.00446">V4L2_FIELD_TOPV4L2_FIELD_TOP</tspan></text> | |
| 2515 | 2515 | <text |
| 2516 | 2516 | y="-299.23349" |
| 2517 | 2517 | x="5.8034" |
| 2518 | 2518 | id="text4863" |
| 2519 | 2519 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2520 | 2520 | transform="scale(1,-1)"><tspan |
| 2521 | − id="tspan4865" | |
| 2522 | − sodipodi:role="line" | |
| 2523 | − y="-299.23349" | |
| 2524 | − x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 84.504837 93.168114 100.4995 108.50284 117.16611 123.83755 131.8409 140.50418 148.50751 157.17079 160.50652 163.84224 167.17796 175.18129 181.85274 188.52419 195.19562 201.86707 209.19846 212.53418 220.53751 227.20895 235.87224 242.54367 245.87939 254.54268 261.87405 269.87741 278.54068 285.21213 293.21545 301.87872 309.88205 318.54535 325.2168 333.22012">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_BT</tspan><tspan | |
| 2525 | − id="tspan4867" | |
| 2526 | − sodipodi:role="line" | |
| 2527 | − y="-192.9435" | |
| 2528 | − x="1.5518398 9.5551729 16.226616 22.898062 29.569506 36.240948 43.572334 46.908058 54.911392 61.582836 70.246117 76.917557 80.253281 88.916557 96.247948 104.25128 112.91456 119.586 127.58932 136.25262 144.25595 152.91924 159.59067 166.92206 174.9254 178.26112 182.25679 192.25195 194.91573 200.91524 207.58667 210.25046 212.91423 219.58568 226.25713 232.92856 239.60001">V4L2_FIELD_INTERLACED_TB (misaligned)</tspan><tspan | |
| 2529 | − id="tspan4869" | |
| 2530 | − sodipodi:role="line" | |
| 2531 | − y="-86.653496" | |
| 2532 | − x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 89.172447 97.175781 106.511 113.18245 121.18579">V4L2_FIELD_SEQ_BT</tspan></text> | |
| 2521 | + id="tspan4865" | |
| 2522 | + sodipodi:role="line" | |
| 2523 | + y="-299.23349" | |
| 2524 | + x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 84.504837 93.168114 100.4995 108.50284 117.16611 123.83755 131.8409 140.50418 148.50751 157.17079 160.50652 163.84224 167.17796 175.18129 181.85274 188.52419 195.19562 201.86707 209.19846 212.53418 220.53751 227.20895 235.87224 242.54367 245.87939 254.54268 261.87405 269.87741 278.54068 285.21213 293.21545 301.87872 309.88205 318.54535 325.2168 333.22012">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_BT</tspan><tspan | |
| 2525 | + id="tspan4867" | |
| 2526 | + sodipodi:role="line" | |
| 2527 | + y="-192.9435" | |
| 2528 | + x="1.5518398 9.5551729 16.226616 22.898062 29.569506 36.240948 43.572334 46.908058 54.911392 61.582836 70.246117 76.917557 80.253281 88.916557 96.247948 104.25128 112.91456 119.586 127.58932 136.25262 144.25595 152.91924 159.59067 166.92206 174.9254 178.26112 182.25679 192.25195 194.91573 200.91524 207.58667 210.25046 212.91423 219.58568 226.25713 232.92856 239.60001">V4L2_FIELD_INTERLACED_TB (misaligned)</tspan><tspan | |
| 2529 | + id="tspan4869" | |
| 2530 | + sodipodi:role="line" | |
| 2531 | + y="-86.653496" | |
| 2532 | + x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 89.172447 97.175781 106.511 113.18245 121.18579">V4L2_FIELD_SEQ_BT</tspan></text> | |
| 2533 | 2533 | <text |
| 2534 | 2534 | y="-533.07098" |
| 2535 | 2535 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464" |
| 2536 | 2536 | id="text4592" |
| 2537 | 2537 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2538 | 2538 | transform="scale(1,-1)"><tspan |
| 2539 | − id="tspan4594" | |
| 2540 | − sodipodi:role="line" | |
| 2541 | − y="-533.07098" | |
| 2542 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464">V4L2_FIELD_TOP</tspan></text> | |
| 2539 | + id="tspan4594" | |
| 2540 | + sodipodi:role="line" | |
| 2541 | + y="-533.07098" | |
| 2542 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464">V4L2_FIELD_TOP</tspan></text> | |
| 2543 | 2543 | <text |
| 2544 | 2544 | y="-465.04559" |
| 2545 | 2545 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054" |
| 2546 | 2546 | id="text4596" |
| 2547 | 2547 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2548 | 2548 | transform="scale(1,-1)"><tspan |
| 2549 | − id="tspan4598" | |
| 2550 | − sodipodi:role="line" | |
| 2551 | − y="-465.04559" | |
| 2552 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan></text> | |
| 2549 | + id="tspan4598" | |
| 2550 | + sodipodi:role="line" | |
| 2551 | + y="-465.04559" | |
| 2552 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan></text> | |
| 2553 | 2553 | <text |
| 2554 | 2554 | y="-397.0202" |
| 2555 | 2555 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963" |
| 2556 | 2556 | id="text4600" |
| 2557 | 2557 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2558 | 2558 | transform="scale(1,-1)"><tspan |
| 2559 | − id="tspan4602" | |
| 2560 | − sodipodi:role="line" | |
| 2561 | − y="-397.0202" | |
| 2562 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2559 | + id="tspan4602" | |
| 2560 | + sodipodi:role="line" | |
| 2561 | + y="-397.0202" | |
| 2562 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2563 | 2563 | <text |
| 2564 | 2564 | y="-299.23349" |
| 2565 | 2565 | x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 84.504837 93.168114 100.4995 108.50284 117.16611 123.83755 131.8409 140.50418 148.50751 157.17079 160.50652 163.84224 167.17796 175.18129 181.85274 188.52419 195.19562 201.86707 209.19846 212.53418 220.53751 227.20895 235.87224 242.54367 245.87939 254.54268 261.87405 269.87741 278.54068 285.21213 293.21545 301.87872 309.88205 318.54535 325.2168 333.22012" |
| 2566 | 2566 | id="text5862" |
| 2567 | 2567 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2568 | 2568 | transform="scale(1,-1)"><tspan |
| 2569 | − id="tspan5864" | |
| 2570 | − sodipodi:role="line" | |
| 2571 | − y="-299.23349" | |
| 2572 | − x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 84.504837 93.168114 100.4995 108.50284 117.16611 123.83755 131.8409 140.50418 148.50751 157.17079 160.50652 163.84224 167.17796 175.18129 181.85274 188.52419 195.19562 201.86707 209.19846 212.53418 220.53751 227.20895 235.87224 242.54367 245.87939 254.54268 261.87405 269.87741 278.54068 285.21213 293.21545 301.87872 309.88205 318.54535 325.2168 333.22012">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_BT</tspan></text> | |
| 2569 | + id="tspan5864" | |
| 2570 | + sodipodi:role="line" | |
| 2571 | + y="-299.23349" | |
| 2572 | + x="5.8034 13.806733 20.478176 27.149622 33.821064 40.492508 47.823895 51.159618 59.162952 65.834396 74.497673 81.169121 84.504837 93.168114 100.4995 108.50284 117.16611 123.83755 131.8409 140.50418 148.50751 157.17079 160.50652 163.84224 167.17796 175.18129 181.85274 188.52419 195.19562 201.86707 209.19846 212.53418 220.53751 227.20895 235.87224 242.54367 245.87939 254.54268 261.87405 269.87741 278.54068 285.21213 293.21545 301.87872 309.88205 318.54535 325.2168 333.22012">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_BT</tspan></text> | |
| 2573 | 2573 | <text |
| 2574 | 2574 | y="-192.9435" |
| 2575 | 2575 | x="1.5518398 9.5551729 16.226616 22.898062 29.569506 36.240948 43.572334 46.908058 54.911392 61.582836 70.246117 76.917557 80.253281 88.916557 96.247948 104.25128 112.91456 119.586 127.58932 136.25262 144.25595 152.91924 159.59067 166.92206 174.9254 178.26112 182.25679 192.25195 194.91573 200.91524 207.58667 210.25046 212.91423 219.58568 226.25713 232.92856 239.60001" |
| 2576 | 2576 | id="text5866" |
| 2577 | 2577 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2578 | 2578 | transform="scale(1,-1)"><tspan |
| 2579 | − id="tspan5868" | |
| 2580 | − sodipodi:role="line" | |
| 2581 | − y="-192.9435" | |
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| 2583 | 2583 | <text |
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| 2506 | + id="tspan6783" | |
| 2507 | + sodipodi:role="line" | |
| 2508 | + y="-86.604706" | |
| 2509 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 97.175514 106.51073 113.18218 120.51357">V4L2_FIELD_SEQ_TB</tspan><tspan | |
| 2510 | + id="tspan6785" | |
| 2511 | + sodipodi:role="line" | |
| 2512 | + y="-192.89471" | |
| 2513 | + x="10.05469 18.058023 24.729465 31.400909 38.072357 44.743801 52.075188 55.410912 63.414246 70.085686 78.748962 85.42041 88.756134 97.419411 104.7508 112.75413 121.41741 128.08885 136.09219 144.75546 152.7588 161.42207 168.09352 176.09685 183.42824 186.76396 190.75963 200.75479 203.41858 209.41808 216.08952 218.7533 221.41707 228.08852 234.75996 241.43141 248.10286">V4L2_FIELD_INTERLACED_BT (misaligned)</tspan><tspan | |
| 2514 | + id="tspan6787" | |
| 2515 | + sodipodi:role="line" | |
| 2516 | + y="-294.93271" | |
| 2517 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 84.50457 93.167847 100.49924 108.50257 117.16585 123.83729 131.84062 140.50391 148.50723 157.17052 160.50624 163.84196 167.17769 175.18102 181.85246 188.52391 195.19534 201.86679 209.19818 212.53391 220.53723 227.20868 235.87196 242.5434 245.87912 254.5424 261.87378 269.87714 278.54041 285.21185 293.21518 301.87845 309.88177 318.54507 325.21652 332.54791">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_TB</tspan></text> | |
| 2517 | 2518 | <text |
| 2518 | 2519 | y="-528.771" |
| 2519 | 2520 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464" |
| 2520 | 2521 | id="text4583" |
| 2521 | 2522 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2522 | 2523 | transform="scale(1,-1)"><tspan |
| 2523 | − id="tspan4585" | |
| 2524 | − sodipodi:role="line" | |
| 2525 | − y="-528.771" | |
| 2526 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464">V4L2_FIELD_TOP</tspan></text> | |
| 2524 | + id="tspan4585" | |
| 2525 | + sodipodi:role="line" | |
| 2526 | + y="-528.771" | |
| 2527 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 88.500237 97.835464">V4L2_FIELD_TOP</tspan></text> | |
| 2527 | 2528 | <text |
| 2528 | 2529 | y="-460.74561" |
| 2529 | 2530 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054" |
| 2530 | 2531 | id="text4587" |
| 2531 | 2532 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2532 | 2533 | transform="scale(1,-1)"><tspan |
| 2533 | − id="tspan4589" | |
| 2534 | − sodipodi:role="line" | |
| 2535 | − y="-460.74561" | |
| 2536 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan></text> | |
| 2534 | + id="tspan4589" | |
| 2535 | + sodipodi:role="line" | |
| 2536 | + y="-460.74561" | |
| 2537 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 98.507408 105.83879 113.17018 122.5054">V4L2_FIELD_BOTTOM</tspan></text> | |
| 2537 | 2538 | <text |
| 2538 | 2539 | y="-392.72021" |
| 2539 | 2540 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963" |
| 2540 | 2541 | id="text4591" |
| 2541 | 2542 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2542 | 2543 | transform="scale(1,-1)"><tspan |
| 2543 | − id="tspan4593" | |
| 2544 | − sodipodi:role="line" | |
| 2545 | − y="-392.72021" | |
| 2546 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2544 | + id="tspan4593" | |
| 2545 | + sodipodi:role="line" | |
| 2546 | + y="-392.72021" | |
| 2547 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 95.843628 103.17502 111.17835 119.84163 128.5049 136.50824 143.83963">V4L2_FIELD_ALTERNATE</tspan></text> | |
| 2547 | 2548 | <text |
| 2548 | 2549 | y="-588.2937" |
| 2549 | 2550 | x="5.8031301 13.134519 19.805964 29.801128 36.472572 43.14402 47.139687 53.811131 56.474907 59.810631 66.482071 70.477737 77.149185 83.820625 87.816299 91.152016 94.48774 97.823463 104.4949 111.16635 114.50207 117.83779 120.50157 127.17302 129.83679 136.50824 139.84396 143.17969 145.84346 149.83913 155.83862 159.17435 162.51007 165.84579 169.84146 176.51291 183.18434 189.18385 199.17902 201.84279 205.17851 208.51424 215.18568 221.85713 225.19284 229.18851 235.85995 239.19568 245.86713 249.20285 252.53857 260.5419 269.87714 273.21286 281.21619 289.21951 295.89096" |
| 2550 | 2551 | id="text5847" |
| 2551 | 2552 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2552 | 2553 | transform="scale(1,-1)"><tspan |
| 2553 | − id="tspan5849" | |
| 2554 | − sodipodi:role="line" | |
| 2555 | − y="-588.2937" | |
| 2556 | − x="5.8031301 13.134519 19.805964 29.801128 36.472572 43.14402 47.139687 53.811131 56.474907 59.810631 66.482071 70.477737 77.149185 83.820625 87.816299 91.152016 94.48774 97.823463 104.4949 111.16635 114.50207 117.83779 120.50157 127.17302 129.83679 136.50824 139.84396 143.17969 145.84346 149.83913 155.83862 159.17435 162.51007 165.84579 169.84146 176.51291 183.18434 189.18385 199.17902 201.84279 205.17851 208.51424 215.18568 221.85713 225.19284 229.18851 235.85995 239.19568 245.86713 249.20285 252.53857 260.5419 269.87714 273.21286 281.21619 289.21951 295.89096">Temporal order, top field first transmitted (e.g. BG/PAL)</tspan></text> | |
| 2554 | + id="tspan5849" | |
| 2555 | + sodipodi:role="line" | |
| 2556 | + y="-588.2937" | |
| 2557 | + x="5.8031301 13.134519 19.805964 29.801128 36.472572 43.14402 47.139687 53.811131 56.474907 59.810631 66.482071 70.477737 77.149185 83.820625 87.816299 91.152016 94.48774 97.823463 104.4949 111.16635 114.50207 117.83779 120.50157 127.17302 129.83679 136.50824 139.84396 143.17969 145.84346 149.83913 155.83862 159.17435 162.51007 165.84579 169.84146 176.51291 183.18434 189.18385 199.17902 201.84279 205.17851 208.51424 215.18568 221.85713 225.19284 229.18851 235.85995 239.19568 245.86713 249.20285 252.53857 260.5419 269.87714 273.21286 281.21619 289.21951 295.89096">Temporal order, top field first transmitted (e.g. BG/PAL)</tspan></text> | |
| 2557 | 2558 | <text |
| 2558 | 2559 | y="-86.604706" |
| 2559 | 2560 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 97.175514 106.51073 113.18218 120.51357" |
| 2560 | 2561 | id="text5851" |
| 2561 | 2562 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2562 | 2563 | transform="scale(1,-1)"><tspan |
| 2563 | − id="tspan5853" | |
| 2564 | − sodipodi:role="line" | |
| 2565 | − y="-86.604706" | |
| 2566 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 97.175514 106.51073 113.18218 120.51357">V4L2_FIELD_SEQ_TB</tspan></text> | |
| 2564 | + id="tspan5853" | |
| 2565 | + sodipodi:role="line" | |
| 2566 | + y="-86.604706" | |
| 2567 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 89.17218 97.175514 106.51073 113.18218 120.51357">V4L2_FIELD_SEQ_TB</tspan></text> | |
| 2567 | 2568 | <text |
| 2568 | 2569 | y="-192.89471" |
| 2569 | 2570 | x="10.05469 18.058023 24.729465 31.400909 38.072357 44.743801 52.075188 55.410912 63.414246 70.085686 78.748962 85.42041 88.756134 97.419411 104.7508 112.75413 121.41741 128.08885 136.09219 144.75546 152.7588 161.42207 168.09352 176.09685 183.42824 186.76396 190.75963 200.75479 203.41858 209.41808 216.08952 218.7533 221.41707 228.08852 234.75996 241.43141 248.10286" |
| 2570 | 2571 | id="text5855" |
| 2571 | 2572 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2572 | 2573 | transform="scale(1,-1)"><tspan |
| 2573 | − id="tspan5857" | |
| 2574 | − sodipodi:role="line" | |
| 2575 | − y="-192.89471" | |
| 2576 | − x="10.05469 18.058023 24.729465 31.400909 38.072357 44.743801 52.075188 55.410912 63.414246 70.085686 78.748962 85.42041 88.756134 97.419411 104.7508 112.75413 121.41741 128.08885 136.09219 144.75546 152.7588 161.42207 168.09352 176.09685 183.42824 186.76396 190.75963 200.75479 203.41858 209.41808 216.08952 218.7533 221.41707 228.08852 234.75996 241.43141 248.10286">V4L2_FIELD_INTERLACED_BT (misaligned)</tspan></text> | |
| 2574 | + id="tspan5857" | |
| 2575 | + sodipodi:role="line" | |
| 2576 | + y="-192.89471" | |
| 2577 | + x="10.05469 18.058023 24.729465 31.400909 38.072357 44.743801 52.075188 55.410912 63.414246 70.085686 78.748962 85.42041 88.756134 97.419411 104.7508 112.75413 121.41741 128.08885 136.09219 144.75546 152.7588 161.42207 168.09352 176.09685 183.42824 186.76396 190.75963 200.75479 203.41858 209.41808 216.08952 218.7533 221.41707 228.08852 234.75996 241.43141 248.10286">V4L2_FIELD_INTERLACED_BT (misaligned)</tspan></text> | |
| 2577 | 2578 | <text |
| 2578 | 2579 | y="-294.93271" |
| 2579 | 2580 | x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 84.50457 93.167847 100.49924 108.50257 117.16585 123.83729 131.84062 140.50391 148.50723 157.17052 160.50624 163.84196 167.17769 175.18102 181.85246 188.52391 195.19534 201.86679 209.19818 212.53391 220.53723 227.20868 235.87196 242.5434 245.87912 254.5424 261.87378 269.87714 278.54041 285.21185 293.21518 301.87845 309.88177 318.54507 325.21652 332.54791" |
| 2580 | 2581 | id="text5859" |
| 2581 | 2582 | style="font-variant:normal;font-weight:normal;font-size:11.9989996px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2582 | 2583 | transform="scale(1,-1)"><tspan |
| 2583 | − id="tspan5861" | |
| 2584 | − sodipodi:role="line" | |
| 2585 | − y="-294.93271" | |
| 2586 | − x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 84.50457 93.167847 100.49924 108.50257 117.16585 123.83729 131.84062 140.50391 148.50723 157.17052 160.50624 163.84196 167.17769 175.18102 181.85246 188.52391 195.19534 201.86679 209.19818 212.53391 220.53723 227.20868 235.87196 242.5434 245.87912 254.5424 261.87378 269.87714 278.54041 285.21185 293.21518 301.87845 309.88177 318.54507 325.21652 332.54791">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_TB</tspan></text> | |
| 2584 | + id="tspan5861" | |
| 2585 | + sodipodi:role="line" | |
| 2586 | + y="-294.93271" | |
| 2587 | + x="5.8031301 13.806463 20.477907 27.149351 33.820797 40.492241 47.823627 51.159351 59.162685 65.834129 74.497406 81.168854 84.50457 93.167847 100.49924 108.50257 117.16585 123.83729 131.84062 140.50391 148.50723 157.17052 160.50624 163.84196 167.17769 175.18102 181.85246 188.52391 195.19534 201.86679 209.19818 212.53391 220.53723 227.20868 235.87196 242.5434 245.87912 254.5424 261.87378 269.87714 278.54041 285.21185 293.21518 301.87845 309.88177 318.54507 325.21652 332.54791">V4L2_FIELD_INTERLACED / V4L2_FIELD_INTERLACED_TB</tspan></text> | |
| 2587 | 2588 | <text |
| 2588 | 2589 | y="-324.69479" |
| 2589 | 2590 | x="10.05469 14.17945 18.766184 20.597576 25.184309 29.771042 34.357777 38.944508 41.237877 43.531242 48.117977 50.865067 53.158432 55.451801 57.283192 61.869926 63.701321 68.288048" |
| 2590 | 2591 | id="text7131" |
| 2591 | 2592 | style="font-variant:normal;font-weight:normal;font-size:8.2495203px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2592 | 2593 | transform="scale(1,-1)"><tspan |
| 2593 | − id="tspan7133" | |
| 2594 | − sodipodi:role="line" | |
| 2595 | − y="-324.69479" | |
| 2596 | − x="10.05469 14.17945 18.766184 20.597576 25.184309 29.771042 34.357777 38.944508 41.237877 43.531242 48.117977 50.865067 53.158432 55.451801 57.283192 61.869926 63.701321 68.288048">v4l2_buffer.field:</tspan></text> | |
| 2594 | + id="tspan7133" | |
| 2595 | + sodipodi:role="line" | |
| 2596 | + y="-324.69479" | |
| 2597 | + x="10.05469 14.17945 18.766184 20.597576 25.184309 29.771042 34.357777 38.944508 41.237877 43.531242 48.117977 50.865067 53.158432 55.451801 57.283192 61.869926 63.701321 68.288048">v4l2_buffer.field:</tspan></text> | |
| 2597 | 2598 | <text |
| 2598 | 2599 | y="-311.9397" |
| 2599 | − x="10.05469 15.55712 20.143852 24.730585 29.317318 33.904053 38.944508 41.237877 46.740307 51.327042 57.283192 61.869926 66.910378 73.328506 95.0867 100.58913 105.17586 109.7626 114.34933 118.93606 123.97652 126.26987 131.77232 136.35905 142.3152 146.90193 152.40436 158.82249 163.86295 168.9034 175.32153 197.12534 202.62778 207.21451 211.80124 216.38797 220.9747 226.01515 228.30853 233.81096 238.39769 244.35384 248.94058 253.98103 260.39917 282.15695 287.65936 292.24609 296.83282 301.41956 306.00629 311.04675 313.34012 318.84256 323.42929 329.38544 333.97217 339.47461 345.89273 350.9332 355.97363 362.39175 384.19559 389.698 394.28473 398.87149 403.45822 408.04495 413.08539 415.37875 420.8812 425.46793 431.42407 436.0108 441.05127 447.46939 469.2276 474.73001 479.31674 483.90347 488.49023 493.07697 498.1174 500.41077 505.91321 510.49994 516.45612 521.04285 526.54523 532.96338 538.00385 543.04431 549.4624" | |
| 2600 | + x="10.05469 15.55712 20.143852 24.730585 29.317318 33.904053 38.944508 41.237877 46.740307 51.327042 57.283192 61.869926 66.910378 73.328506 95.0867 100.58913 105.17586 109.7626 114.34933 118.93606 123.97652 126.26987 131.77232 136.35905 142.3152 146.90193 152.40436 158.82249 163.86295 168.9034 175.32153 197.12534 202.62778 207.21451 211.80124 216.38797 220.9747 226.01515 228.30853 233.81096 238.39769 244.35384 248.94058 253.98103 260.39917 282.15695 287.65936 292.24609 296.83282 301.41956 306.00629 311.04675 313.34012 318.84256 323.42929 329.38544 333.97217 339.47461 345.89273 350.9332 355.97363 362.39175 384.19559 389.698 394.28473 398.87149 403.45822 408.04495 413.08539 415.37875 420.8812 425.46793 431.42407 436.0108 441.05127 447.46939 469.2276 474.73001 479.31674 483.90347 488.49023 493.07697 498.1174 500.41077 505.91321 510.49994 516.45612 521.04285 526.54523 532.96338 | |
| 2601 | +538.00385 543.04431 549.4624" | |
| 2600 | 2602 | id="text7135" |
| 2601 | 2603 | style="font-variant:normal;font-weight:normal;font-size:8.2495203px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 2602 | 2604 | transform="scale(1,-1)"><tspan |
| 2603 | − id="tspan7137" | |
| 2604 | − sodipodi:role="line" | |
| 2605 | − y="-311.9397" | |
| 2606 | − x="10.05469 15.55712 20.143852 24.730585 29.317318 33.904053 38.944508 41.237877 46.740307 51.327042 57.283192 61.869926 66.910378 73.328506 95.0867 100.58913 105.17586 109.7626 114.34933 118.93606 123.97652 126.26987 131.77232 136.35905 142.3152 146.90193 152.40436 158.82249 163.86295 168.9034 175.32153 197.12534 202.62778 207.21451 211.80124 216.38797 220.9747 226.01515 228.30853 233.81096 238.39769 244.35384 248.94058 253.98103 260.39917 282.15695 287.65936 292.24609 296.83282 301.41956 306.00629 311.04675 313.34012 318.84256 323.42929 329.38544 333.97217 339.47461 345.89273 350.9332 355.97363 362.39175 384.19559 389.698 394.28473 398.87149 403.45822 408.04495 413.08539 415.37875 420.8812 425.46793 431.42407 436.0108 441.05127 447.46939 469.2276 474.73001 479.31674 483.90347 488.49023 493.07697 498.1174 500.41077 505.91321 510.49994 516.45612 521.04285 526.54523 532.96338 538.00385 543.04431 549.4624">V4L2_FIELD_TOPV4L2_FIELD_BOTTOMV4L2_FIELD_TOPV4L2_FIELD_BOTTOMV4L2_FIELD_TOPV4L2_FIELD_BOTTOM</tspan></text> | |
| 2605 | + id="tspan7137" | |
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| 282 | + x="100.80776 112.39354 117.01952 128.60529 140.19107 145.98395 157.56973 162.19569 173.78148 185.36726 195.78612 200.41209 211.99788">Line blanking</tspan></text> | |
| 283 | 283 | <text |
| 284 | 284 | id="text3607" |
| 285 | 285 | style="font-variant:normal;font-weight:normal;font-size:20.83772659px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 286 | 286 | transform="scale(1,-1)" |
| 287 | 287 | x="438.29504 452.19382 456.81979 468.40555 478.82443 489.24329 495.03619 506.62195 518.2077 528.62659 540.21234" |
| 288 | 288 | y="-187.28558"><tspan |
| 289 | − id="tspan3609" | |
| 290 | − sodipodi:role="line" | |
| 291 | − y="-187.28558" | |
| 292 | − x="438.29504 452.19382 456.81979 468.40555 478.82443 489.24329 495.03619 506.62195 518.2077 528.62659 540.21234">Black Level</tspan></text> | |
| 289 | + id="tspan3609" | |
| 290 | + sodipodi:role="line" | |
| 291 | + y="-187.28558" | |
| 292 | + x="438.29504 452.19382 456.81979 468.40555 478.82443 489.24329 495.03619 506.62195 518.2077 528.62659 540.21234">Black Level</tspan></text> | |
| 293 | 293 | <text |
| 294 | 294 | id="text3611" |
| 295 | 295 | style="font-variant:normal;font-weight:normal;font-size:20.83772659px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 296 | 296 | transform="scale(1,-1)" |
| 297 | 297 | x="438.29504 452.19382 462.61267 474.19846 484.61731 490.41019 501.99597 513.58173 524.00061 535.58636" |
| 298 | 298 | y="-83.096947"><tspan |
| 299 | − id="tspan3613" | |
| 300 | − sodipodi:role="line" | |
| 301 | − y="-83.096947" | |
| 302 | − x="438.29504 452.19382 462.61267 474.19846 484.61731 490.41019 501.99597 513.58173 524.00061 535.58636">Sync Level</tspan></text> | |
| 299 | + id="tspan3613" | |
| 300 | + sodipodi:role="line" | |
| 301 | + y="-83.096947" | |
| 302 | + x="438.29504 452.19382 462.61267 474.19846 484.61731 490.41019 501.99597 513.58173 524.00061 535.58636">Sync Level</tspan></text> | |
| 303 | 303 | <text |
| 304 | 304 | id="text3615" |
| 305 | 305 | style="font-variant:normal;font-weight:normal;font-size:20.83772659px;font-family:sans-serif;-inkscape-font-specification:sans-serif;writing-mode:lr-tb;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-style:normal;font-stretch:normal;" |
| 306 | 306 | transform="scale(1,-1)" |
| 307 | 307 | x="438.29504 457.96585 469.55164 474.17761 479.97049 491.55627 497.34915 508.93494 520.52069 530.93958 542.52533" |
| 308 | 308 | y="-395.66284"><tspan |
| 309 | − id="tspan3617" | |
| 310 | − sodipodi:role="line" | |
| 311 | − y="-395.66284" | |
| 312 | − x="438.29504 457.96585 469.55164 474.17761 479.97049 491.55627 497.34915 508.93494 520.52069 530.93958 542.52533">White Level</tspan></text> | |
| 309 | + id="tspan3617" | |
| 310 | + sodipodi:role="line" | |
| 311 | + y="-395.66284" | |
| 312 | + x="438.29504 457.96585 469.55164 474.17761 479.97049 491.55627 497.34915 508.93494 520.52069 530.93958 542.52533">White Level</tspan></text> | |
| 313 | 313 | </g></svg> |
| @@ -147,3 +147,9 @@ appropriately. The generic error codes are described at the · 146 unmodified lines | ||
| 147 | 147 | EINVAL |
| 148 | 148 | The struct :c:type:`v4l2_format` ``type`` field is |
| 149 | 149 | invalid or the requested buffer type not supported. |
| 150 | + | |
| 151 | +EBUSY | |
| 152 | + The device is busy and cannot change the format. This could be | |
| 153 | + because or the device is streaming or buffers are allocated or | |
| 154 | + queued to the driver. Relevant for :ref:`VIDIOC_S_FMT | |
| 155 | + <VIDIOC_G_FMT>` only. | |
| @@ -607,8 +607,9 @@ References · 606 unmodified lines | ||
| 607 | 607 | |
| 608 | 608 | Authors |
| 609 | 609 | ------- |
| 610 | −Steve Longerbeam <steve_longerbeam@mentor.com> | |
| 611 | −Philipp Zabel <kernel@pengutronix.de> | |
| 612 | −Russell King <linux@armlinux.org.uk> | |
| 610 | + | |
| 611 | +- Steve Longerbeam <steve_longerbeam@mentor.com> | |
| 612 | +- Philipp Zabel <kernel@pengutronix.de> | |
| 613 | +- Russell King <linux@armlinux.org.uk> | |
| 613 | 614 | |
| 614 | 615 | Copyright (C) 2012-2017 Mentor Graphics Inc. |
| @@ -41,6 +41,7 @@ For more details see the file COPYING in the source distribution of Linux. · 40 unmodified lines | ||
| 41 | 41 | cx88 |
| 42 | 42 | davinci-vpbe |
| 43 | 43 | fimc |
| 44 | + imx | |
| 44 | 45 | ivtv |
| 45 | 46 | max2175 |
| 46 | 47 | meye |
| @@ -228,7 +228,7 @@ Learning on the device port should be enabled, as well as learning_sync: · 227 unmodified lines | ||
| 228 | 228 | bridge link set dev DEV learning on self |
| 229 | 229 | bridge link set dev DEV learning_sync on self |
| 230 | 230 | |
| 231 | −Learning_sync attribute enables syncing of the learned/forgotton FDB entry to | |
| 231 | +Learning_sync attribute enables syncing of the learned/forgotten FDB entry to | |
| 232 | 232 | the bridge's FDB. It's possible, but not optimal, to enable learning on the |
| 233 | 233 | device port and on the bridge port, and disable learning_sync. |
| 234 | 234 | |
| @@ -245,7 +245,7 @@ the responsibility of the port driver/device to age out these entries. If the · 10 unmodified lines | ||
| 245 | 245 | port device supports ageing, when the FDB entry expires, it will notify the |
| 246 | 246 | driver which in turn will notify the bridge with SWITCHDEV_FDB_DEL. If the |
| 247 | 247 | device does not support ageing, the driver can simulate ageing using a |
| 248 | −garbage collection timer to monitor FBD entries. Expired entries will be | |
| 248 | +garbage collection timer to monitor FDB entries. Expired entries will be | |
| 249 | 249 | notified to the bridge using SWITCHDEV_FDB_DEL. See rocker driver for |
| 250 | 250 | example of driver running ageing timer. |
| 251 | 251 | |
| @@ -435,7 +435,8 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h: · 434 unmodified lines | ||
| 435 | 435 | PM status to 'suspended' and update its parent's counter of 'active' |
| 436 | 436 | children as appropriate (it is only valid to use this function if |
| 437 | 437 | 'power.runtime_error' is set or 'power.disable_depth' is greater than |
| 438 | − zero) | |
| 438 | + zero); it will fail and return an error code if the device has a child | |
| 439 | + which is active and the 'power.ignore_children' flag is unset | |
| 439 | 440 | |
| 440 | 441 | bool pm_runtime_active(struct device *dev); |
| 441 | 442 | - return true if the device's runtime PM status is 'active' or its |
| @@ -58,20 +58,23 @@ Symbols/Function Pointers · 57 unmodified lines | ||
| 58 | 58 | %ps versatile_init |
| 59 | 59 | %pB prev_fn_of_versatile_init+0x88/0x88 |
| 60 | 60 | |
| 61 | −For printing symbols and function pointers. The ``S`` and ``s`` specifiers | |
| 62 | −result in the symbol name with (``S``) or without (``s``) offsets. Where | |
| 63 | −this is used on a kernel without KALLSYMS - the symbol address is | |
| 64 | −printed instead. | |
| 61 | +The ``F`` and ``f`` specifiers are for printing function pointers, | |
| 62 | +for example, f->func, &gettimeofday. They have the same result as | |
| 63 | +``S`` and ``s`` specifiers. But they do an extra conversion on | |
| 64 | +ia64, ppc64 and parisc64 architectures where the function pointers | |
| 65 | +are actually function descriptors. | |
| 66 | + | |
| 67 | +The ``S`` and ``s`` specifiers can be used for printing symbols | |
| 68 | +from direct addresses, for example, __builtin_return_address(0), | |
| 69 | +(void *)regs->ip. They result in the symbol name with (``S``) or | |
| 70 | +without (``s``) offsets. If KALLSYMS are disabled then the symbol | |
| 71 | +address is printed instead. | |
| 65 | 72 | |
| 66 | 73 | The ``B`` specifier results in the symbol name with offsets and should be |
| 67 | 74 | used when printing stack backtraces. The specifier takes into |
| 68 | 75 | consideration the effect of compiler optimisations which may occur |
| 69 | 76 | when tail-call``s are used and marked with the noreturn GCC attribute. |
| 70 | 77 | |
| 71 | −On ia64, ppc64 and parisc64 architectures function pointers are | |
| 72 | −actually function descriptors which must first be resolved. The ``F`` and | |
| 73 | −``f`` specifiers perform this resolution and then provide the same | |
| 74 | −functionality as the ``S`` and ``s`` specifiers. | |
| 75 | 78 | |
| 76 | 79 | Kernel Pointers |
| 77 | 80 | =============== |
| @@ -35,9 +35,34 @@ Table : Subdirectories in /proc/sys/net · 34 unmodified lines | ||
| 35 | 35 | bpf_jit_enable |
| 36 | 36 | -------------- |
| 37 | 37 | |
| 38 | −This enables Berkeley Packet Filter Just in Time compiler. | |
| 39 | −Currently supported on x86_64 architecture, bpf_jit provides a framework | |
| 40 | −to speed packet filtering, the one used by tcpdump/libpcap for example. | |
| 38 | +This enables the BPF Just in Time (JIT) compiler. BPF is a flexible | |
| 39 | +and efficient infrastructure allowing to execute bytecode at various | |
| 40 | +hook points. It is used in a number of Linux kernel subsystems such | |
| 41 | +as networking (e.g. XDP, tc), tracing (e.g. kprobes, uprobes, tracepoints) | |
| 42 | +and security (e.g. seccomp). LLVM has a BPF back end that can compile | |
| 43 | +restricted C into a sequence of BPF instructions. After program load | |
| 44 | +through bpf(2) and passing a verifier in the kernel, a JIT will then | |
| 45 | +translate these BPF proglets into native CPU instructions. There are | |
| 46 | +two flavors of JITs, the newer eBPF JIT currently supported on: | |
| 47 | + - x86_64 | |
| 48 | + - arm64 | |
| 49 | + - ppc64 | |
| 50 | + - sparc64 | |
| 51 | + - mips64 | |
| 52 | + - s390x | |
| 53 | + | |
| 54 | +And the older cBPF JIT supported on the following archs: | |
| 55 | + - arm | |
| 56 | + - mips | |
| 57 | + - ppc | |
| 58 | + - sparc | |
| 59 | + | |
| 60 | +eBPF JITs are a superset of cBPF JITs, meaning the kernel will | |
| 61 | +migrate cBPF instructions into eBPF instructions and then JIT | |
| 62 | +compile them transparently. Older cBPF JITs can only translate | |
| 63 | +tcpdump filters, seccomp rules, etc, but not mentioned eBPF | |
| 64 | +programs loaded through bpf(2). | |
| 65 | + | |
| 41 | 66 | Values : |
| 42 | 67 | 0 - disable the JIT (default value) |
| 43 | 68 | 1 - enable the JIT |
| @@ -46,9 +71,9 @@ Values : · 2 unmodified lines | ||
| 46 | 71 | bpf_jit_harden |
| 47 | 72 | -------------- |
| 48 | 73 | |
| 49 | −This enables hardening for the Berkeley Packet Filter Just in Time compiler. | |
| 50 | −Supported are eBPF JIT backends. Enabling hardening trades off performance, | |
| 51 | −but can mitigate JIT spraying. | |
| 74 | +This enables hardening for the BPF JIT compiler. Supported are eBPF | |
| 75 | +JIT backends. Enabling hardening trades off performance, but can | |
| 76 | +mitigate JIT spraying. | |
| 52 | 77 | Values : |
| 53 | 78 | 0 - disable JIT hardening (default value) |
| 54 | 79 | 1 - enable JIT hardening for unprivileged users only |
| @@ -57,11 +82,11 @@ Values : · 2 unmodified lines | ||
| 57 | 82 | bpf_jit_kallsyms |
| 58 | 83 | ---------------- |
| 59 | 84 | |
| 60 | −When Berkeley Packet Filter Just in Time compiler is enabled, then compiled | |
| 61 | −images are unknown addresses to the kernel, meaning they neither show up in | |
| 62 | −traces nor in /proc/kallsyms. This enables export of these addresses, which | |
| 63 | −can be used for debugging/tracing. If bpf_jit_harden is enabled, this feature | |
| 64 | −is disabled. | |
| 85 | +When BPF JIT compiler is enabled, then compiled images are unknown | |
| 86 | +addresses to the kernel, meaning they neither show up in traces nor | |
| 87 | +in /proc/kallsyms. This enables export of these addresses, which can | |
| 88 | +be used for debugging/tracing. If bpf_jit_harden is enabled, this | |
| 89 | +feature is disabled. | |
| 65 | 90 | Values : |
| 66 | 91 | 0 - disable JIT kallsyms export (default value) |
| 67 | 92 | 1 - enable JIT kallsyms export for privileged users only |
| @@ -1161,7 +1161,7 @@ M: Brendan Higgins <brendanhiggins@google.com> · 1160 unmodified lines | ||
| 1161 | 1161 | R: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 1162 | 1162 | R: Joel Stanley <joel@jms.id.au> |
| 1163 | 1163 | L: linux-i2c@vger.kernel.org |
| 1164 | −L: openbmc@lists.ozlabs.org | |
| 1164 | +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) | |
| 1165 | 1165 | S: Maintained |
| 1166 | 1166 | F: drivers/irqchip/irq-aspeed-i2c-ic.c |
| 1167 | 1167 | F: drivers/i2c/busses/i2c-aspeed.c |
| @@ -5090,12 +5090,20 @@ M: Andrew Lunn <andrew@lunn.ch> · 3922 unmodified lines | ||
| 5090 | 5090 | M: Florian Fainelli <f.fainelli@gmail.com> |
| 5091 | 5091 | L: netdev@vger.kernel.org |
| 5092 | 5092 | S: Maintained |
| 5093 | −F: include/linux/phy.h | |
| 5094 | −F: include/linux/phy_fixed.h | |
| 5095 | −F: drivers/net/phy/ | |
| 5093 | +F: Documentation/ABI/testing/sysfs-bus-mdio | |
| 5094 | +F: Documentation/devicetree/bindings/net/mdio* | |
| 5096 | 5095 | F: Documentation/networking/phy.txt |
| 5096 | +F: drivers/net/phy/ | |
| 5097 | 5097 | F: drivers/of/of_mdio.c |
| 5098 | 5098 | F: drivers/of/of_net.c |
| 5099 | +F: include/linux/*mdio*.h | |
| 5100 | +F: include/linux/of_net.h | |
| 5101 | +F: include/linux/phy.h | |
| 5102 | +F: include/linux/phy_fixed.h | |
| 5103 | +F: include/linux/platform_data/mdio-gpio.h | |
| 5104 | +F: include/trace/events/mdio.h | |
| 5105 | +F: include/uapi/linux/mdio.h | |
| 5106 | +F: include/uapi/linux/mii.h | |
| 5099 | 5107 | |
| 5100 | 5108 | EXT2 FILE SYSTEM |
| 5101 | 5109 | M: Jan Kara <jack@suse.com> |
| @@ -5826,7 +5834,7 @@ F: drivers/staging/greybus/spi.c · 724 unmodified lines | ||
| 5826 | 5834 | F: drivers/staging/greybus/spilib.c |
| 5827 | 5835 | F: drivers/staging/greybus/spilib.h |
| 5828 | 5836 | |
| 5829 | −GREYBUS LOOBACK/TIME PROTOCOLS DRIVERS | |
| 5837 | +GREYBUS LOOPBACK/TIME PROTOCOLS DRIVERS | |
| 5830 | 5838 | M: Bryan O'Donoghue <pure.logic@nexus-software.ie> |
| 5831 | 5839 | S: Maintained |
| 5832 | 5840 | F: drivers/staging/greybus/loopback.c |
| @@ -7102,7 +7110,6 @@ M: Marc Zyngier <marc.zyngier@arm.com> · 1269 unmodified lines | ||
| 7102 | 7110 | L: linux-kernel@vger.kernel.org |
| 7103 | 7111 | S: Maintained |
| 7104 | 7112 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core |
| 7105 | −T: git git://git.infradead.org/users/jcooper/linux.git irqchip/core | |
| 7106 | 7113 | F: Documentation/devicetree/bindings/interrupt-controller/ |
| 7107 | 7114 | F: drivers/irqchip/ |
| 7108 | 7115 | |
| @@ -10375,7 +10382,7 @@ L: linux-gpio@vger.kernel.org · 3266 unmodified lines | ||
| 10375 | 10382 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git |
| 10376 | 10383 | S: Maintained |
| 10377 | 10384 | F: Documentation/devicetree/bindings/pinctrl/ |
| 10378 | −F: Documentation/pinctrl.txt | |
| 10385 | +F: Documentation/driver-api/pinctl.rst | |
| 10379 | 10386 | F: drivers/pinctrl/ |
| 10380 | 10387 | F: include/linux/pinctrl/ |
| 10381 | 10388 | |
| @@ -14002,6 +14009,7 @@ F: drivers/block/virtio_blk.c · 3620 unmodified lines | ||
| 14002 | 14009 | F: include/linux/virtio*.h |
| 14003 | 14010 | F: include/uapi/linux/virtio_*.h |
| 14004 | 14011 | F: drivers/crypto/virtio/ |
| 14012 | +F: mm/balloon_compaction.c | |
| 14005 | 14013 | |
| 14006 | 14014 | VIRTIO CRYPTO DRIVER |
| 14007 | 14015 | M: Gonglei <arei.gonglei@huawei.com> |
| @@ -14216,6 +14224,12 @@ F: drivers/watchdog/ · 208 unmodified lines | ||
| 14216 | 14224 | F: include/linux/watchdog.h |
| 14217 | 14225 | F: include/uapi/linux/watchdog.h |
| 14218 | 14226 | |
| 14227 | +WHISKEYCOVE PMIC GPIO DRIVER | |
| 14228 | +M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> | |
| 14229 | +L: linux-gpio@vger.kernel.org | |
| 14230 | +S: Maintained | |
| 14231 | +F: drivers/gpio/gpio-wcove.c | |
| 14232 | + | |
| 14219 | 14233 | WIIMOTE HID DRIVER |
| 14220 | 14234 | M: David Herrmann <dh.herrmann@googlemail.com> |
| 14221 | 14235 | L: linux-input@vger.kernel.org |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | VERSION = 4 |
| 2 | 2 | PATCHLEVEL = 13 |
| 3 | 3 | SUBLEVEL = 0 |
| 4 | −EXTRAVERSION = -rc2 | |
| 4 | +EXTRAVERSION = -rc7 | |
| 5 | 5 | NAME = Fearless Coyote |
| 6 | 6 | |
| 7 | 7 | # *DOCUMENTATION* |
| @@ -396,7 +396,7 @@ LINUXINCLUDE := \ · 388 unmodified lines | ||
| 396 | 396 | KBUILD_CPPFLAGS := -D__KERNEL__ |
| 397 | 397 | |
| 398 | 398 | KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ |
| 399 | − -fno-strict-aliasing -fno-common \ | |
| 399 | + -fno-strict-aliasing -fno-common -fshort-wchar \ | |
| 400 | 400 | -Werror-implicit-function-declaration \ |
| 401 | 401 | -Wno-format-security \ |
| 402 | 402 | -std=gnu89 $(call cc-option,-fno-PIE) |
| @@ -442,7 +442,7 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ · 39 unmodified lines | ||
| 442 | 442 | # =========================================================================== |
| 443 | 443 | # Rules shared between *config targets and build targets |
| 444 | 444 | |
| 445 | −# Basic helpers built in scripts/ | |
| 445 | +# Basic helpers built in scripts/basic/ | |
| 446 | 446 | PHONY += scripts_basic |
| 447 | 447 | scripts_basic: |
| 448 | 448 | $(Q)$(MAKE) $(build)=scripts/basic |
| @@ -505,7 +505,7 @@ ifeq ($(KBUILD_EXTMOD),) · 56 unmodified lines | ||
| 505 | 505 | endif |
| 506 | 506 | endif |
| 507 | 507 | endif |
| 508 | −# install and module_install need also be processed one by one | |
| 508 | +# install and modules_install need also be processed one by one | |
| 509 | 509 | ifneq ($(filter install,$(MAKECMDGOALS)),) |
| 510 | 510 | ifneq ($(filter modules_install,$(MAKECMDGOALS)),) |
| 511 | 511 | mixed-targets := 1 |
| @@ -964,7 +964,7 @@ export KBUILD_VMLINUX_MAIN := $(core-y) $(libs-y2) $(drivers-y) $(net-y) $(virt- · 452 unmodified lines | ||
| 964 | 964 | export KBUILD_VMLINUX_LIBS := $(libs-y1) |
| 965 | 965 | export KBUILD_LDS := arch/$(SRCARCH)/kernel/vmlinux.lds |
| 966 | 966 | export LDFLAGS_vmlinux |
| 967 | −# used by scripts/pacmage/Makefile | |
| 967 | +# used by scripts/package/Makefile | |
| 968 | 968 | export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) arch Documentation include samples scripts tools) |
| 969 | 969 | |
| 970 | 970 | vmlinux-deps := $(KBUILD_LDS) $(KBUILD_VMLINUX_INIT) $(KBUILD_VMLINUX_MAIN) $(KBUILD_VMLINUX_LIBS) |
| @@ -992,8 +992,8 @@ include/generated/autoksyms.h: FORCE · 21 unmodified lines | ||
| 992 | 992 | ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(SRCARCH)/Makefile.postlink) |
| 993 | 993 | |
| 994 | 994 | # Final link of vmlinux with optional arch pass after final link |
| 995 | − cmd_link-vmlinux = \ | |
| 996 | − $(CONFIG_SHELL) $< $(LD) $(LDFLAGS) $(LDFLAGS_vmlinux) ; \ | |
| 995 | +cmd_link-vmlinux = \ | |
| 996 | + $(CONFIG_SHELL) $< $(LD) $(LDFLAGS) $(LDFLAGS_vmlinux) ; \ | |
| 997 | 997 | $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true) |
| 998 | 998 | |
| 999 | 999 | vmlinux: scripts/link-vmlinux.sh vmlinux_prereq $(vmlinux-deps) FORCE |
| @@ -1184,6 +1184,7 @@ PHONY += kselftest · 184 unmodified lines | ||
| 1184 | 1184 | kselftest: |
| 1185 | 1185 | $(Q)$(MAKE) -C tools/testing/selftests run_tests |
| 1186 | 1186 | |
| 1187 | +PHONY += kselftest-clean | |
| 1187 | 1188 | kselftest-clean: |
| 1188 | 1189 | $(Q)$(MAKE) -C tools/testing/selftests clean |
| 1189 | 1190 | |
| @@ -96,7 +96,6 @@ menu "ARC Architecture Configuration" · 95 unmodified lines | ||
| 96 | 96 | |
| 97 | 97 | menu "ARC Platform/SoC/Board" |
| 98 | 98 | |
| 99 | −source "arch/arc/plat-sim/Kconfig" | |
| 100 | 99 | source "arch/arc/plat-tb10x/Kconfig" |
| 101 | 100 | source "arch/arc/plat-axs10x/Kconfig" |
| 102 | 101 | #New platform adds here |
| @@ -107,7 +107,7 @@ core-y += arch/arc/ · 106 unmodified lines | ||
| 107 | 107 | # w/o this dtb won't embed into kernel binary |
| 108 | 108 | core-y += arch/arc/boot/dts/ |
| 109 | 109 | |
| 110 | −core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/ | |
| 110 | +core-y += arch/arc/plat-sim/ | |
| 111 | 111 | core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ |
| 112 | 112 | core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ |
| 113 | 113 | core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/ |
| @@ -15,15 +15,15 @@ · 14 unmodified lines | ||
| 15 | 15 | |
| 16 | 16 | / { |
| 17 | 17 | compatible = "snps,arc"; |
| 18 | − #address-cells = <1>; | |
| 19 | − #size-cells = <1>; | |
| 18 | + #address-cells = <2>; | |
| 19 | + #size-cells = <2>; | |
| 20 | 20 | |
| 21 | 21 | cpu_card { |
| 22 | 22 | compatible = "simple-bus"; |
| 23 | 23 | #address-cells = <1>; |
| 24 | 24 | #size-cells = <1>; |
| 25 | 25 | |
| 26 | − ranges = <0x00000000 0xf0000000 0x10000000>; | |
| 26 | + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; | |
| 27 | 27 | |
| 28 | 28 | core_clk: core_clk { |
| 29 | 29 | #clock-cells = <0>; |
| @@ -91,23 +91,21 @@ · 61 unmodified lines | ||
| 91 | 91 | mb_intc: dw-apb-ictl@0xe0012000 { |
| 92 | 92 | #interrupt-cells = <1>; |
| 93 | 93 | compatible = "snps,dw-apb-ictl"; |
| 94 | − reg = < 0xe0012000 0x200 >; | |
| 94 | + reg = < 0x0 0xe0012000 0x0 0x200 >; | |
| 95 | 95 | interrupt-controller; |
| 96 | 96 | interrupt-parent = <&core_intc>; |
| 97 | 97 | interrupts = < 7 >; |
| 98 | 98 | }; |
| 99 | 99 | |
| 100 | 100 | memory { |
| 101 | − #address-cells = <1>; | |
| 102 | − #size-cells = <1>; | |
| 103 | − ranges = <0x00000000 0x80000000 0x20000000>; | |
| 104 | 101 | device_type = "memory"; |
| 105 | − reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */ | |
| 102 | + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ | |
| 103 | + reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ | |
| 106 | 104 | }; |
| 107 | 105 | |
| 108 | 106 | reserved-memory { |
| 109 | − #address-cells = <1>; | |
| 110 | − #size-cells = <1>; | |
| 107 | + #address-cells = <2>; | |
| 108 | + #size-cells = <2>; | |
| 111 | 109 | ranges; |
| 112 | 110 | /* |
| 113 | 111 | * We just move frame buffer area to the very end of |
| @@ -118,7 +116,7 @@ · 4 unmodified lines | ||
| 118 | 116 | */ |
| 119 | 117 | frame_buffer: frame_buffer@9e000000 { |
| 120 | 118 | compatible = "shared-dma-pool"; |
| 121 | − reg = <0x9e000000 0x2000000>; | |
| 119 | + reg = <0x0 0x9e000000 0x0 0x2000000>; | |
| 122 | 120 | no-map; |
| 123 | 121 | }; |
| 124 | 122 | }; |
| @@ -14,15 +14,15 @@ · 13 unmodified lines | ||
| 14 | 14 | |
| 15 | 15 | / { |
| 16 | 16 | compatible = "snps,arc"; |
| 17 | − #address-cells = <1>; | |
| 18 | − #size-cells = <1>; | |
| 17 | + #address-cells = <2>; | |
| 18 | + #size-cells = <2>; | |
| 19 | 19 | |
| 20 | 20 | cpu_card { |
| 21 | 21 | compatible = "simple-bus"; |
| 22 | 22 | #address-cells = <1>; |
| 23 | 23 | #size-cells = <1>; |
| 24 | 24 | |
| 25 | − ranges = <0x00000000 0xf0000000 0x10000000>; | |
| 25 | + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; | |
| 26 | 26 | |
| 27 | 27 | core_clk: core_clk { |
| 28 | 28 | #clock-cells = <0>; |
| @@ -94,30 +94,29 @@ · 65 unmodified lines | ||
| 94 | 94 | mb_intc: dw-apb-ictl@0xe0012000 { |
| 95 | 95 | #interrupt-cells = <1>; |
| 96 | 96 | compatible = "snps,dw-apb-ictl"; |
| 97 | − reg = < 0xe0012000 0x200 >; | |
| 97 | + reg = < 0x0 0xe0012000 0x0 0x200 >; | |
| 98 | 98 | interrupt-controller; |
| 99 | 99 | interrupt-parent = <&core_intc>; |
| 100 | 100 | interrupts = < 24 >; |
| 101 | 101 | }; |
| 102 | 102 | |
| 103 | 103 | memory { |
| 104 | − #address-cells = <1>; | |
| 105 | − #size-cells = <1>; | |
| 106 | − ranges = <0x00000000 0x80000000 0x40000000>; | |
| 107 | 104 | device_type = "memory"; |
| 108 | − reg = <0x80000000 0x20000000>; /* 512MiB */ | |
| 105 | + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ | |
| 106 | + reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ | |
| 107 | + 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ | |
| 109 | 108 | }; |
| 110 | 109 | |
| 111 | 110 | reserved-memory { |
| 112 | − #address-cells = <1>; | |
| 113 | − #size-cells = <1>; | |
| 111 | + #address-cells = <2>; | |
| 112 | + #size-cells = <2>; | |
| 114 | 113 | ranges; |
| 115 | 114 | /* |
| 116 | 115 | * Move frame buffer out of IOC aperture (0x8z-0xAz). |
| 117 | 116 | */ |
| 118 | 117 | frame_buffer: frame_buffer@be000000 { |
| 119 | 118 | compatible = "shared-dma-pool"; |
| 120 | − reg = <0xbe000000 0x2000000>; | |
| 119 | + reg = <0x0 0xbe000000 0x0 0x2000000>; | |
| 121 | 120 | no-map; |
| 122 | 121 | }; |
| 123 | 122 | }; |
| @@ -14,15 +14,15 @@ · 13 unmodified lines | ||
| 14 | 14 | |
| 15 | 15 | / { |
| 16 | 16 | compatible = "snps,arc"; |
| 17 | − #address-cells = <1>; | |
| 18 | − #size-cells = <1>; | |
| 17 | + #address-cells = <2>; | |
| 18 | + #size-cells = <2>; | |
| 19 | 19 | |
| 20 | 20 | cpu_card { |
| 21 | 21 | compatible = "simple-bus"; |
| 22 | 22 | #address-cells = <1>; |
| 23 | 23 | #size-cells = <1>; |
| 24 | 24 | |
| 25 | − ranges = <0x00000000 0xf0000000 0x10000000>; | |
| 25 | + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; | |
| 26 | 26 | |
| 27 | 27 | core_clk: core_clk { |
| 28 | 28 | #clock-cells = <0>; |
| @@ -100,30 +100,29 @@ · 71 unmodified lines | ||
| 100 | 100 | mb_intc: dw-apb-ictl@0xe0012000 { |
| 101 | 101 | #interrupt-cells = <1>; |
| 102 | 102 | compatible = "snps,dw-apb-ictl"; |
| 103 | − reg = < 0xe0012000 0x200 >; | |
| 103 | + reg = < 0x0 0xe0012000 0x0 0x200 >; | |
| 104 | 104 | interrupt-controller; |
| 105 | 105 | interrupt-parent = <&idu_intc>; |
| 106 | 106 | interrupts = <0>; |
| 107 | 107 | }; |
| 108 | 108 | |
| 109 | 109 | memory { |
| 110 | − #address-cells = <1>; | |
| 111 | − #size-cells = <1>; | |
| 112 | − ranges = <0x00000000 0x80000000 0x40000000>; | |
| 113 | 110 | device_type = "memory"; |
| 114 | − reg = <0x80000000 0x20000000>; /* 512MiB */ | |
| 111 | + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ | |
| 112 | + reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ | |
| 113 | + 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ | |
| 115 | 114 | }; |
| 116 | 115 | |
| 117 | 116 | reserved-memory { |
| 118 | − #address-cells = <1>; | |
| 119 | − #size-cells = <1>; | |
| 117 | + #address-cells = <2>; | |
| 118 | + #size-cells = <2>; | |
| 120 | 119 | ranges; |
| 121 | 120 | /* |
| 122 | 121 | * Move frame buffer out of IOC aperture (0x8z-0xAz). |
| 123 | 122 | */ |
| 124 | 123 | frame_buffer: frame_buffer@be000000 { |
| 125 | 124 | compatible = "shared-dma-pool"; |
| 126 | − reg = <0xbe000000 0x2000000>; | |
| 125 | + reg = <0x0 0xbe000000 0x0 0x2000000>; | |
| 127 | 126 | no-map; |
| 128 | 127 | }; |
| 129 | 128 | }; |
| @@ -13,7 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | compatible = "simple-bus"; |
| 14 | 14 | #address-cells = <1>; |
| 15 | 15 | #size-cells = <1>; |
| 16 | − ranges = <0x00000000 0xe0000000 0x10000000>; | |
| 16 | + ranges = <0x00000000 0x0 0xe0000000 0x10000000>; | |
| 17 | 17 | interrupt-parent = <&mb_intc>; |
| 18 | 18 | |
| 19 | 19 | i2sclk: i2sclk@100a0 { |
| @@ -21,7 +21,6 @@ CONFIG_MODULES=y · 20 unmodified lines | ||
| 21 | 21 | # CONFIG_BLK_DEV_BSG is not set |
| 22 | 22 | # CONFIG_IOSCHED_DEADLINE is not set |
| 23 | 23 | # CONFIG_IOSCHED_CFQ is not set |
| 24 | −CONFIG_ARC_PLAT_SIM=y | |
| 25 | 24 | CONFIG_ISA_ARCV2=y |
| 26 | 25 | CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs" |
| 27 | 26 | CONFIG_PREEMPT=y |
| @@ -23,7 +23,6 @@ CONFIG_MODULES=y · 22 unmodified lines | ||
| 23 | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | 24 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | 25 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | −CONFIG_ARC_PLAT_SIM=y | |
| 27 | 26 | CONFIG_ISA_ARCV2=y |
| 28 | 27 | CONFIG_SMP=y |
| 29 | 28 | CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu" |
| @@ -39,7 +39,6 @@ CONFIG_IP_PNP=y · 38 unmodified lines | ||
| 39 | 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 40 | 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 41 | 41 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 42 | −# CONFIG_INET_LRO is not set | |
| 43 | 42 | # CONFIG_INET_DIAG is not set |
| 44 | 43 | # CONFIG_IPV6 is not set |
| 45 | 44 | # CONFIG_WIRELESS is not set |
| @@ -23,7 +23,6 @@ CONFIG_MODULES=y · 22 unmodified lines | ||
| 23 | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | 24 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | 25 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | −CONFIG_ARC_PLAT_SIM=y | |
| 27 | 26 | CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700" |
| 28 | 27 | CONFIG_PREEMPT=y |
| 29 | 28 | # CONFIG_COMPACTION is not set |
| @@ -26,7 +26,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y · 25 unmodified lines | ||
| 26 | 26 | # CONFIG_BLK_DEV_BSG is not set |
| 27 | 27 | # CONFIG_IOSCHED_DEADLINE is not set |
| 28 | 28 | # CONFIG_IOSCHED_CFQ is not set |
| 29 | −CONFIG_ARC_PLAT_SIM=y | |
| 30 | 29 | CONFIG_ISA_ARCV2=y |
| 31 | 30 | CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs" |
| 32 | 31 | CONFIG_PREEMPT=y |
| @@ -24,7 +24,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y · 23 unmodified lines | ||
| 24 | 24 | # CONFIG_BLK_DEV_BSG is not set |
| 25 | 25 | # CONFIG_IOSCHED_DEADLINE is not set |
| 26 | 26 | # CONFIG_IOSCHED_CFQ is not set |
| 27 | −CONFIG_ARC_PLAT_SIM=y | |
| 28 | 27 | CONFIG_ISA_ARCV2=y |
| 29 | 28 | CONFIG_SMP=y |
| 30 | 29 | CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu" |
| @@ -23,7 +23,6 @@ CONFIG_MODULES=y · 22 unmodified lines | ||
| 23 | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | 24 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | 25 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | −CONFIG_ARC_PLAT_SIM=y | |
| 27 | 26 | CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci" |
| 28 | 27 | # CONFIG_COMPACTION is not set |
| 29 | 28 | CONFIG_NET=y |
| @@ -23,7 +23,6 @@ CONFIG_MODULES=y · 22 unmodified lines | ||
| 23 | 23 | # CONFIG_BLK_DEV_BSG is not set |
| 24 | 24 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | 25 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | −CONFIG_ARC_PLAT_SIM=y | |
| 27 | 26 | CONFIG_ISA_ARCV2=y |
| 28 | 27 | CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs" |
| 29 | 28 | # CONFIG_COMPACTION is not set |
| @@ -18,7 +18,6 @@ CONFIG_MODULES=y · 17 unmodified lines | ||
| 18 | 18 | # CONFIG_BLK_DEV_BSG is not set |
| 19 | 19 | # CONFIG_IOSCHED_DEADLINE is not set |
| 20 | 20 | # CONFIG_IOSCHED_CFQ is not set |
| 21 | −CONFIG_ARC_PLAT_SIM=y | |
| 22 | 21 | CONFIG_ISA_ARCV2=y |
| 23 | 22 | CONFIG_SMP=y |
| 24 | 23 | # CONFIG_ARC_TIMERS_64BIT is not set |
| @@ -38,7 +38,6 @@ CONFIG_IP_MULTICAST=y · 37 unmodified lines | ||
| 38 | 38 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 39 | 39 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 40 | 40 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 41 | −# CONFIG_INET_LRO is not set | |
| 42 | 41 | # CONFIG_INET_DIAG is not set |
| 43 | 42 | # CONFIG_IPV6 is not set |
| 44 | 43 | # CONFIG_WIRELESS is not set |
| @@ -96,7 +96,9 @@ extern unsigned long perip_base, perip_end; · 95 unmodified lines | ||
| 96 | 96 | #define ARC_REG_SLC_FLUSH 0x904 |
| 97 | 97 | #define ARC_REG_SLC_INVALIDATE 0x905 |
| 98 | 98 | #define ARC_REG_SLC_RGN_START 0x914 |
| 99 | +#define ARC_REG_SLC_RGN_START1 0x915 | |
| 99 | 100 | #define ARC_REG_SLC_RGN_END 0x916 |
| 101 | +#define ARC_REG_SLC_RGN_END1 0x917 | |
| 100 | 102 | |
| 101 | 103 | /* Bit val in SLC_CONTROL */ |
| 102 | 104 | #define SLC_CTRL_DIS 0x001 |
| @@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void) · 93 unmodified lines | ||
| 94 | 94 | return IS_ENABLED(CONFIG_ARC_HAS_PAE40); |
| 95 | 95 | } |
| 96 | 96 | |
| 97 | +extern int pae40_exist_but_not_enab(void); | |
| 98 | + | |
| 97 | 99 | #endif /* !__ASSEMBLY__ */ |
| 98 | 100 | |
| 99 | 101 | #endif |
| @@ -75,10 +75,13 @@ void arc_init_IRQ(void) · 74 unmodified lines | ||
| 75 | 75 | * Set a default priority for all available interrupts to prevent |
| 76 | 76 | * switching of register banks if Fast IRQ and multiple register banks |
| 77 | 77 | * are supported by CPU. |
| 78 | + * Also disable all IRQ lines so faulty external hardware won't | |
| 79 | + * trigger interrupt that kernel is not ready to handle. | |
| 78 | 80 | */ |
| 79 | 81 | for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { |
| 80 | 82 | write_aux_reg(AUX_IRQ_SELECT, i); |
| 81 | 83 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); |
| 84 | + write_aux_reg(AUX_IRQ_ENABLE, 0); | |
| 82 | 85 | } |
| 83 | 86 | |
| 84 | 87 | /* setup status32, don't enable intr yet as kernel doesn't want */ |
| @@ -27,7 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | */ |
| 28 | 28 | void arc_init_IRQ(void) |
| 29 | 29 | { |
| 30 | − int level_mask = 0; | |
| 30 | + int level_mask = 0, i; | |
| 31 | 31 | |
| 32 | 32 | /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */ |
| 33 | 33 | level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ; |
| @@ -40,6 +40,18 @@ void arc_init_IRQ(void) · 6 unmodified lines | ||
| 40 | 40 | |
| 41 | 41 | if (level_mask) |
| 42 | 42 | pr_info("Level-2 interrupts bitset %x\n", level_mask); |
| 43 | + | |
| 44 | + /* | |
| 45 | + * Disable all IRQ lines so faulty external hardware won't | |
| 46 | + * trigger interrupt that kernel is not ready to handle. | |
| 47 | + */ | |
| 48 | + for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) { | |
| 49 | + unsigned int ienb; | |
| 50 | + | |
| 51 | + ienb = read_aux_reg(AUX_IENABLE); | |
| 52 | + ienb &= ~(1 << i); | |
| 53 | + write_aux_reg(AUX_IENABLE, ienb); | |
| 54 | + } | |
| 43 | 55 | } |
| 44 | 56 | |
| 45 | 57 | /* |
| @@ -665,6 +665,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · 664 unmodified lines | ||
| 665 | 665 | static DEFINE_SPINLOCK(lock); |
| 666 | 666 | unsigned long flags; |
| 667 | 667 | unsigned int ctrl; |
| 668 | + phys_addr_t end; | |
| 668 | 669 | |
| 669 | 670 | spin_lock_irqsave(&lock, flags); |
| 670 | 671 | |
| @@ -694,8 +695,19 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · 23 unmodified lines | ||
| 694 | 695 | * END needs to be setup before START (latter triggers the operation) |
| 695 | 696 | * END can't be same as START, so add (l2_line_sz - 1) to sz |
| 696 | 697 | */ |
| 697 | − write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); | |
| 698 | − write_aux_reg(ARC_REG_SLC_RGN_START, paddr); | |
| 698 | + end = paddr + sz + l2_line_sz - 1; | |
| 699 | + if (is_pae40_enabled()) | |
| 700 | + write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end)); | |
| 701 | + | |
| 702 | + write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end)); | |
| 703 | + | |
| 704 | + if (is_pae40_enabled()) | |
| 705 | + write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr)); | |
| 706 | + | |
| 707 | + write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr)); | |
| 708 | + | |
| 709 | + /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ | |
| 710 | + read_aux_reg(ARC_REG_SLC_CTRL); | |
| 699 | 711 | |
| 700 | 712 | while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); |
| 701 | 713 | |
| @@ -1111,6 +1123,13 @@ noinline void __init arc_ioc_setup(void) · 409 unmodified lines | ||
| 1111 | 1123 | __dc_enable(); |
| 1112 | 1124 | } |
| 1113 | 1125 | |
| 1126 | +/* | |
| 1127 | + * Cache related boot time checks/setups only needed on master CPU: | |
| 1128 | + * - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES) | |
| 1129 | + * Assume SMP only, so all cores will have same cache config. A check on | |
| 1130 | + * one core suffices for all | |
| 1131 | + * - IOC setup / dma callbacks only need to be done once | |
| 1132 | + */ | |
| 1114 | 1133 | void __init arc_cache_init_master(void) |
| 1115 | 1134 | { |
| 1116 | 1135 | unsigned int __maybe_unused cpu = smp_processor_id(); |
| @@ -1190,12 +1209,27 @@ void __ref arc_cache_init(void) · 73 unmodified lines | ||
| 1190 | 1209 | |
| 1191 | 1210 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); |
| 1192 | 1211 | |
| 1193 | − /* | |
| 1194 | − * Only master CPU needs to execute rest of function: | |
| 1195 | − * - Assume SMP so all cores will have same cache config so | |
| 1196 | − * any geomtry checks will be same for all | |
| 1197 | − * - IOC setup / dma callbacks only need to be setup once | |
| 1198 | − */ | |
| 1199 | 1212 | if (!cpu) |
| 1200 | 1213 | arc_cache_init_master(); |
| 1214 | + | |
| 1215 | + /* | |
| 1216 | + * In PAE regime, TLB and cache maintenance ops take wider addresses | |
| 1217 | + * And even if PAE is not enabled in kernel, the upper 32-bits still need | |
| 1218 | + * to be zeroed to keep the ops sane. | |
| 1219 | + * As an optimization for more common !PAE enabled case, zero them out | |
| 1220 | + * once at init, rather than checking/setting to 0 for every runtime op | |
| 1221 | + */ | |
| 1222 | + if (is_isa_arcv2() && pae40_exist_but_not_enab()) { | |
| 1223 | + | |
| 1224 | + if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) | |
| 1225 | + write_aux_reg(ARC_REG_IC_PTAG_HI, 0); | |
| 1226 | + | |
| 1227 | + if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) | |
| 1228 | + write_aux_reg(ARC_REG_DC_PTAG_HI, 0); | |
| 1229 | + | |
| 1230 | + if (l2_line_sz) { | |
| 1231 | + write_aux_reg(ARC_REG_SLC_RGN_END1, 0); | |
| 1232 | + write_aux_reg(ARC_REG_SLC_RGN_START1, 0); | |
| 1233 | + } | |
| 1234 | + } | |
| 1201 | 1235 | } |
| @@ -153,6 +153,19 @@ static void _dma_cache_sync(phys_addr_t paddr, size_t size, · 152 unmodified lines | ||
| 153 | 153 | } |
| 154 | 154 | } |
| 155 | 155 | |
| 156 | +/* | |
| 157 | + * arc_dma_map_page - map a portion of a page for streaming DMA | |
| 158 | + * | |
| 159 | + * Ensure that any data held in the cache is appropriately discarded | |
| 160 | + * or written back. | |
| 161 | + * | |
| 162 | + * The device owns this memory once this call has completed. The CPU | |
| 163 | + * can regain ownership by calling dma_unmap_page(). | |
| 164 | + * | |
| 165 | + * Note: while it takes struct page as arg, caller can "abuse" it to pass | |
| 166 | + * a region larger than PAGE_SIZE, provided it is physically contiguous | |
| 167 | + * and this still works correctly | |
| 168 | + */ | |
| 156 | 169 | static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, |
| 157 | 170 | unsigned long offset, size_t size, enum dma_data_direction dir, |
| 158 | 171 | unsigned long attrs) |
| @@ -165,6 +178,24 @@ static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, · 6 unmodified lines | ||
| 165 | 178 | return plat_phys_to_dma(dev, paddr); |
| 166 | 179 | } |
| 167 | 180 | |
| 181 | +/* | |
| 182 | + * arc_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
| 183 | + * | |
| 184 | + * After this call, reads by the CPU to the buffer are guaranteed to see | |
| 185 | + * whatever the device wrote there. | |
| 186 | + * | |
| 187 | + * Note: historically this routine was not implemented for ARC | |
| 188 | + */ | |
| 189 | +static void arc_dma_unmap_page(struct device *dev, dma_addr_t handle, | |
| 190 | + size_t size, enum dma_data_direction dir, | |
| 191 | + unsigned long attrs) | |
| 192 | +{ | |
| 193 | + phys_addr_t paddr = plat_dma_to_phys(dev, handle); | |
| 194 | + | |
| 195 | + if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) | |
| 196 | + _dma_cache_sync(paddr, size, dir); | |
| 197 | +} | |
| 198 | + | |
| 168 | 199 | static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, |
| 169 | 200 | int nents, enum dma_data_direction dir, unsigned long attrs) |
| 170 | 201 | { |
| @@ -178,6 +209,18 @@ static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, · 7 unmodified lines | ||
| 178 | 209 | return nents; |
| 179 | 210 | } |
| 180 | 211 | |
| 212 | +static void arc_dma_unmap_sg(struct device *dev, struct scatterlist *sg, | |
| 213 | + int nents, enum dma_data_direction dir, | |
| 214 | + unsigned long attrs) | |
| 215 | +{ | |
| 216 | + struct scatterlist *s; | |
| 217 | + int i; | |
| 218 | + | |
| 219 | + for_each_sg(sg, s, nents, i) | |
| 220 | + arc_dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, | |
| 221 | + attrs); | |
| 222 | +} | |
| 223 | + | |
| 181 | 224 | static void arc_dma_sync_single_for_cpu(struct device *dev, |
| 182 | 225 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) |
| 183 | 226 | { |
| @@ -223,7 +266,9 @@ const struct dma_map_ops arc_dma_ops = { · 39 unmodified lines | ||
| 223 | 266 | .free = arc_dma_free, |
| 224 | 267 | .mmap = arc_dma_mmap, |
| 225 | 268 | .map_page = arc_dma_map_page, |
| 269 | + .unmap_page = arc_dma_unmap_page, | |
| 226 | 270 | .map_sg = arc_dma_map_sg, |
| 271 | + .unmap_sg = arc_dma_unmap_sg, | |
| 227 | 272 | .sync_single_for_device = arc_dma_sync_single_for_device, |
| 228 | 273 | .sync_single_for_cpu = arc_dma_sync_single_for_cpu, |
| 229 | 274 | .sync_sg_for_cpu = arc_dma_sync_sg_for_cpu, |
| @@ -104,6 +104,8 @@ · 103 unmodified lines | ||
| 104 | 104 | /* A copy of the ASID from the PID reg is kept in asid_cache */ |
| 105 | 105 | DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE; |
| 106 | 106 | |
| 107 | +static int __read_mostly pae_exists; | |
| 108 | + | |
| 107 | 109 | /* |
| 108 | 110 | * Utility Routine to erase a J-TLB entry |
| 109 | 111 | * Caller needs to setup Index Reg (manually or via getIndex) |
| @@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void) · 674 unmodified lines | ||
| 784 | 786 | mmu->u_dtlb = mmu4->u_dtlb * 4; |
| 785 | 787 | mmu->u_itlb = mmu4->u_itlb * 4; |
| 786 | 788 | mmu->sasid = mmu4->sasid; |
| 787 | − mmu->pae = mmu4->pae; | |
| 789 | + pae_exists = mmu->pae = mmu4->pae; | |
| 788 | 790 | } |
| 789 | 791 | } |
| 790 | 792 | |
| @@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) · 18 unmodified lines | ||
| 809 | 811 | return buf; |
| 810 | 812 | } |
| 811 | 813 | |
| 814 | +int pae40_exist_but_not_enab(void) | |
| 815 | +{ | |
| 816 | + return pae_exists && !is_pae40_enabled(); | |
| 817 | +} | |
| 818 | + | |
| 812 | 819 | void arc_mmu_init(void) |
| 813 | 820 | { |
| 814 | 821 | char str[256]; |
| @@ -859,6 +866,9 @@ void arc_mmu_init(void) · 44 unmodified lines | ||
| 859 | 866 | /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */ |
| 860 | 867 | write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir); |
| 861 | 868 | #endif |
| 869 | + | |
| 870 | + if (pae40_exist_but_not_enab()) | |
| 871 | + write_aux_reg(ARC_REG_TLBPD1HI, 0); | |
| 862 | 872 | } |
| 863 | 873 | |
| 864 | 874 | /* |
| @@ -1,13 +0,0 @@ | ||
| 1 | −# | |
| 2 | −# Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
| 3 | −# | |
| 4 | −# This program is free software; you can redistribute it and/or modify | |
| 5 | −# it under the terms of the GNU General Public License version 2 as | |
| 6 | −# published by the Free Software Foundation. | |
| 7 | −# | |
| 8 | − | |
| 9 | −menuconfig ARC_PLAT_SIM | |
| 10 | − bool "ARC nSIM based simulation virtual platforms" | |
| 11 | − help | |
| 12 | − Support for nSIM based ARC simulation platforms | |
| 13 | − This includes the standalone nSIM (uart only) vs. System C OSCI VP | |
| @@ -20,11 +20,14 @@ · 19 unmodified lines | ||
| 20 | 20 | */ |
| 21 | 21 | |
| 22 | 22 | static const char *simulation_compat[] __initconst = { |
| 23 | +#ifdef CONFIG_ISA_ARCOMPACT | |
| 23 | 24 | "snps,nsim", |
| 24 | − "snps,nsim_hs", | |
| 25 | 25 | "snps,nsimosci", |
| 26 | +#else | |
| 27 | + "snps,nsim_hs", | |
| 26 | 28 | "snps,nsimosci_hs", |
| 27 | 29 | "snps,zebu_hs", |
| 30 | +#endif | |
| 28 | 31 | NULL, |
| 29 | 32 | }; |
| 30 | 33 | |
| @@ -380,7 +380,7 @@ config ARCH_EP93XX · 379 unmodified lines | ||
| 380 | 380 | bool "EP93xx-based" |
| 381 | 381 | select ARCH_HAS_HOLES_MEMORYMODEL |
| 382 | 382 | select ARM_AMBA |
| 383 | − select ARM_PATCH_PHYS_VIRT | |
| 383 | + imply ARM_PATCH_PHYS_VIRT | |
| 384 | 384 | select ARM_VIC |
| 385 | 385 | select AUTO_ZRELADDR |
| 386 | 386 | select CLKDEV_LOOKUP |
| @@ -75,7 +75,7 @@ · 74 unmodified lines | ||
| 75 | 75 | pinctrl-names = "default"; |
| 76 | 76 | pinctrl-0 = <&pca0_pins>; |
| 77 | 77 | interrupt-parent = <&gpio0>; |
| 78 | − interrupts = <18 IRQ_TYPE_EDGE_FALLING>; | |
| 78 | + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; | |
| 79 | 79 | gpio-controller; |
| 80 | 80 | #gpio-cells = <2>; |
| 81 | 81 | interrupt-controller; |
| @@ -87,7 +87,7 @@ · 5 unmodified lines | ||
| 87 | 87 | compatible = "nxp,pca9555"; |
| 88 | 88 | pinctrl-names = "default"; |
| 89 | 89 | interrupt-parent = <&gpio0>; |
| 90 | − interrupts = <18 IRQ_TYPE_EDGE_FALLING>; | |
| 90 | + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; | |
| 91 | 91 | gpio-controller; |
| 92 | 92 | #gpio-cells = <2>; |
| 93 | 93 | interrupt-controller; |
| @@ -301,25 +301,4 @@ · 300 unmodified lines | ||
| 301 | 301 | pinctrl-names = "default"; |
| 302 | 302 | pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; |
| 303 | 303 | status = "okay"; |
| 304 | − | |
| 305 | − /* VPIF capture port */ | |
| 306 | − port@0 { | |
| 307 | − vpif_input_ch0: endpoint@0 { | |
| 308 | − reg = <0>; | |
| 309 | − bus-width = <8>; | |
| 310 | − }; | |
| 311 | − | |
| 312 | − vpif_input_ch1: endpoint@1 { | |
| 313 | − reg = <1>; | |
| 314 | − bus-width = <8>; | |
| 315 | − data-shift = <8>; | |
| 316 | − }; | |
| 317 | − }; | |
| 318 | − | |
| 319 | − /* VPIF display port */ | |
| 320 | − port@1 { | |
| 321 | − vpif_output_ch0: endpoint { | |
| 322 | − bus-width = <8>; | |
| 323 | − }; | |
| 324 | − }; | |
| 325 | 304 | }; |
| @@ -318,11 +318,4 @@ · 317 unmodified lines | ||
| 318 | 318 | pinctrl-names = "default"; |
| 319 | 319 | pinctrl-0 = <&vpif_capture_pins>; |
| 320 | 320 | status = "okay"; |
| 321 | − | |
| 322 | − /* VPIF capture port */ | |
| 323 | − port { | |
| 324 | − vpif_ch0: endpoint { | |
| 325 | − bus-width = <8>; | |
| 326 | − }; | |
| 327 | − }; | |
| 328 | 321 | }; |
| @@ -68,6 +68,34 @@ · 67 unmodified lines | ||
| 68 | 68 | DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ |
| 69 | 69 | >; |
| 70 | 70 | }; |
| 71 | + | |
| 72 | + nandflash_pins: nandflash_pins { | |
| 73 | + pinctrl-single,pins = < | |
| 74 | + DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ | |
| 75 | + DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ | |
| 76 | + DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ | |
| 77 | + DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ | |
| 78 | + DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ | |
| 79 | + DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ | |
| 80 | + DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ | |
| 81 | + DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ | |
| 82 | + DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ | |
| 83 | + DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ | |
| 84 | + DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ | |
| 85 | + DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ | |
| 86 | + DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ | |
| 87 | + DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ | |
| 88 | + DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ | |
| 89 | + DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ | |
| 90 | + DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ | |
| 91 | + DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ | |
| 92 | + DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ | |
| 93 | + DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ | |
| 94 | + DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ | |
| 95 | + DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ | |
| 96 | + DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ | |
| 97 | + >; | |
| 98 | + }; | |
| 71 | 99 | }; |
| 72 | 100 | |
| 73 | 101 | &i2c1 { |
| @@ -90,6 +118,8 @@ · 16 unmodified lines | ||
| 90 | 118 | |
| 91 | 119 | &gpmc { |
| 92 | 120 | ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ |
| 121 | + pinctrl-names = "default"; | |
| 122 | + pinctrl-0 = <&nandflash_pins>; | |
| 93 | 123 | |
| 94 | 124 | nand@0,0 { |
| 95 | 125 | compatible = "ti,omap2-nand"; |
| @@ -98,9 +128,11 @@ · 2 unmodified lines | ||
| 98 | 128 | interrupt-parent = <&gpmc>; |
| 99 | 129 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| 100 | 130 | <1 IRQ_TYPE_NONE>; /* termcount */ |
| 131 | + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ | |
| 101 | 132 | #address-cells = <1>; |
| 102 | 133 | #size-cells = <1>; |
| 103 | 134 | ti,nand-ecc-opt = "bch8"; |
| 135 | + ti,elm-id = <&elm>; | |
| 104 | 136 | nand-bus-width = <16>; |
| 105 | 137 | gpmc,device-width = <2>; |
| 106 | 138 | gpmc,sync-clk-ps = <0>; |
| @@ -164,7 +196,7 @@ · 57 unmodified lines | ||
| 164 | 196 | vmmc-supply = <&vmmcsd_fixed>; |
| 165 | 197 | bus-width = <4>; |
| 166 | 198 | cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; |
| 167 | − wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; | |
| 199 | + wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; | |
| 168 | 200 | }; |
| 169 | 201 | |
| 170 | 202 | /* At least dm8168-evm rev c won't support multipoint, later may */ |
| @@ -145,7 +145,7 @@ · 144 unmodified lines | ||
| 145 | 145 | }; |
| 146 | 146 | |
| 147 | 147 | elm: elm@48080000 { |
| 148 | − compatible = "ti,816-elm"; | |
| 148 | + compatible = "ti,am3352-elm"; | |
| 149 | 149 | ti,hwmods = "elm"; |
| 150 | 150 | reg = <0x48080000 0x2000>; |
| 151 | 151 | interrupts = <4>; |
| @@ -190,7 +190,7 @@ · 189 unmodified lines | ||
| 190 | 190 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| 191 | 191 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; |
| 192 | 192 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; |
| 193 | − ti,impedance-control = <0x1f>; | |
| 193 | + ti,min-output-impedance; | |
| 194 | 194 | }; |
| 195 | 195 | |
| 196 | 196 | dp83867_1: ethernet-phy@3 { |
| @@ -198,7 +198,7 @@ · 1 unmodified line | ||
| 198 | 198 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| 199 | 199 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; |
| 200 | 200 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; |
| 201 | − ti,impedance-control = <0x1f>; | |
| 201 | + ti,min-output-impedance; | |
| 202 | 202 | }; |
| 203 | 203 | }; |
| 204 | 204 | |
| @@ -59,6 +59,9 @@ · 58 unmodified lines | ||
| 59 | 59 | compatible = "samsung,exynos4210-audss-clock"; |
| 60 | 60 | reg = <0x03810000 0x0C>; |
| 61 | 61 | #clock-cells = <1>; |
| 62 | + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, | |
| 63 | + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>; | |
| 64 | + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; | |
| 62 | 65 | }; |
| 63 | 66 | |
| 64 | 67 | i2s0: i2s@03830000 { |
| @@ -266,6 +266,7 @@ · 265 unmodified lines | ||
| 266 | 266 | |
| 267 | 267 | &hdmicec { |
| 268 | 268 | status = "okay"; |
| 269 | + needs-hpd; | |
| 269 | 270 | }; |
| 270 | 271 | |
| 271 | 272 | &hsi2c_4 { |
| @@ -297,6 +297,7 @@ · 296 unmodified lines | ||
| 297 | 297 | #address-cells = <1>; |
| 298 | 298 | #size-cells = <1>; |
| 299 | 299 | status = "disabled"; |
| 300 | + ranges; | |
| 300 | 301 | |
| 301 | 302 | adc: adc@50030800 { |
| 302 | 303 | compatible = "fsl,imx25-gcq"; |
| @@ -507,7 +507,7 @@ · 506 unmodified lines | ||
| 507 | 507 | pinctrl_pcie: pciegrp { |
| 508 | 508 | fsl,pins = < |
| 509 | 509 | /* PCIe reset */ |
| 510 | − MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 | |
| 510 | + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 | |
| 511 | 511 | MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 |
| 512 | 512 | >; |
| 513 | 513 | }; |
| @@ -668,7 +668,7 @@ · 154 unmodified lines | ||
| 668 | 668 | &pcie { |
| 669 | 669 | pinctrl-names = "default"; |
| 670 | 670 | pinctrl-0 = <&pinctrl_pcie>; |
| 671 | − reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; | |
| 671 | + reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; | |
| 672 | 672 | status = "okay"; |
| 673 | 673 | }; |
| 674 | 674 | |
| @@ -557,6 +557,14 @@ · 556 unmodified lines | ||
| 557 | 557 | >; |
| 558 | 558 | }; |
| 559 | 559 | |
| 560 | + pinctrl_spi4: spi4grp { | |
| 561 | + fsl,pins = < | |
| 562 | + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 | |
| 563 | + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 | |
| 564 | + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 | |
| 565 | + >; | |
| 566 | + }; | |
| 567 | + | |
| 560 | 568 | pinctrl_tsc2046_pendown: tsc2046_pendown { |
| 561 | 569 | fsl,pins = < |
| 562 | 570 | MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 |
| @@ -697,13 +705,5 @@ · 134 unmodified lines | ||
| 697 | 705 | fsl,pins = < |
| 698 | 706 | MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0 |
| 699 | 707 | >; |
| 700 | − | |
| 701 | − pinctrl_spi4: spi4grp { | |
| 702 | − fsl,pins = < | |
| 703 | − MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 | |
| 704 | − MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 | |
| 705 | − MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 | |
| 706 | − >; | |
| 707 | − }; | |
| 708 | 708 | }; |
| 709 | 709 | }; |
| @@ -1126,8 +1126,8 @@ · 1125 unmodified lines | ||
| 1126 | 1126 | }; |
| 1127 | 1127 | }; |
| 1128 | 1128 | |
| 1129 | − gpu: mali@ffa30000 { | |
| 1130 | − compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; | |
| 1129 | + gpu: gpu@ffa30000 { | |
| 1130 | + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; | |
| 1131 | 1131 | reg = <0xffa30000 0x10000>; |
| 1132 | 1132 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 1133 | 1133 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -303,7 +303,7 @@ · 302 unmodified lines | ||
| 303 | 303 | #size-cells = <1>; |
| 304 | 304 | atmel,smc = <&hsmc>; |
| 305 | 305 | reg = <0x10000000 0x10000000 |
| 306 | − 0x40000000 0x30000000>; | |
| 306 | + 0x60000000 0x30000000>; | |
| 307 | 307 | ranges = <0x0 0x0 0x10000000 0x10000000 |
| 308 | 308 | 0x1 0x0 0x60000000 0x10000000 |
| 309 | 309 | 0x2 0x0 0x70000000 0x10000000 |
| @@ -1048,18 +1048,18 @@ · 738 unmodified lines | ||
| 1048 | 1048 | }; |
| 1049 | 1049 | |
| 1050 | 1050 | hsmc: hsmc@f8014000 { |
| 1051 | − compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; | |
| 1051 | + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; | |
| 1052 | 1052 | reg = <0xf8014000 0x1000>; |
| 1053 | − interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; | |
| 1053 | + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; | |
| 1054 | 1054 | clocks = <&hsmc_clk>; |
| 1055 | 1055 | #address-cells = <1>; |
| 1056 | 1056 | #size-cells = <1>; |
| 1057 | 1057 | ranges; |
| 1058 | 1058 | |
| 1059 | − pmecc: ecc-engine@ffffc070 { | |
| 1059 | + pmecc: ecc-engine@f8014070 { | |
| 1060 | 1060 | compatible = "atmel,sama5d2-pmecc"; |
| 1061 | − reg = <0xffffc070 0x490>, | |
| 1062 | − <0xffffc500 0x100>; | |
| 1061 | + reg = <0xf8014070 0x490>, | |
| 1062 | + <0xf8014500 0x100>; | |
| 1063 | 1063 | }; |
| 1064 | 1064 | }; |
| 1065 | 1065 | |
| @@ -44,7 +44,9 @@ · 43 unmodified lines | ||
| 44 | 44 | |
| 45 | 45 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 46 | 46 | |
| 47 | +#include <dt-bindings/clock/sun8i-a83t-ccu.h> | |
| 47 | 48 | #include <dt-bindings/clock/sun8i-r-ccu.h> |
| 49 | +#include <dt-bindings/reset/sun8i-a83t-ccu.h> | |
| 48 | 50 | |
| 49 | 51 | / { |
| 50 | 52 | interrupt-parent = <&gic>; |
| @@ -175,8 +177,8 @@ · 124 unmodified lines | ||
| 175 | 177 | compatible = "allwinner,sun8i-a83t-dma"; |
| 176 | 178 | reg = <0x01c02000 0x1000>; |
| 177 | 179 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | − clocks = <&ccu 21>; | |
| 179 | − resets = <&ccu 7>; | |
| 180 | + clocks = <&ccu CLK_BUS_DMA>; | |
| 181 | + resets = <&ccu RST_BUS_DMA>; | |
| 180 | 182 | #dma-cells = <1>; |
| 181 | 183 | }; |
| 182 | 184 | |
| @@ -195,7 +197,7 @@ · 12 unmodified lines | ||
| 195 | 197 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| 196 | 198 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 197 | 199 | reg = <0x01c20800 0x400>; |
| 198 | − clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>; | |
| 200 | + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; | |
| 199 | 201 | clock-names = "apb", "hosc", "losc"; |
| 200 | 202 | gpio-controller; |
| 201 | 203 | interrupt-controller; |
| @@ -247,8 +249,8 @@ · 45 unmodified lines | ||
| 247 | 249 | "allwinner,sun8i-h3-spdif"; |
| 248 | 250 | reg = <0x01c21000 0x400>; |
| 249 | 251 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 250 | − clocks = <&ccu 44>, <&ccu 76>; | |
| 251 | − resets = <&ccu 32>; | |
| 252 | + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; | |
| 253 | + resets = <&ccu RST_BUS_SPDIF>; | |
| 252 | 254 | clock-names = "apb", "spdif"; |
| 253 | 255 | dmas = <&dma 2>; |
| 254 | 256 | dma-names = "tx"; |
| @@ -263,8 +265,8 @@ · 8 unmodified lines | ||
| 263 | 265 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| 264 | 266 | reg-shift = <2>; |
| 265 | 267 | reg-io-width = <4>; |
| 266 | − clocks = <&ccu 53>; | |
| 267 | − resets = <&ccu 40>; | |
| 268 | + clocks = <&ccu CLK_BUS_UART0>; | |
| 269 | + resets = <&ccu RST_BUS_UART0>; | |
| 268 | 270 | status = "disabled"; |
| 269 | 271 | }; |
| 270 | 272 | |
| @@ -394,7 +394,7 @@ · 393 unmodified lines | ||
| 394 | 394 | emac: ethernet@1c30000 { |
| 395 | 395 | compatible = "allwinner,sun8i-h3-emac"; |
| 396 | 396 | syscon = <&syscon>; |
| 397 | − reg = <0x01c30000 0x104>; | |
| 397 | + reg = <0x01c30000 0x10000>; | |
| 398 | 398 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 399 | 399 | interrupt-names = "macirq"; |
| 400 | 400 | resets = <&ccu RST_BUS_EMAC>; |
| @@ -22,7 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | }; |
| 23 | 23 | |
| 24 | 24 | ð0 { |
| 25 | − phy-connection-type = "rgmii"; | |
| 25 | + phy-connection-type = "rgmii-id"; | |
| 26 | 26 | phy-handle = <ð0_phy>; |
| 27 | 27 | #address-cells = <1>; |
| 28 | 28 | #size-cells = <0>; |
| @@ -148,7 +148,8 @@ static inline void tlb_flush_mmu(struct mmu_gather *tlb) · 147 unmodified lines | ||
| 148 | 148 | } |
| 149 | 149 | |
| 150 | 150 | static inline void |
| 151 | −tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end) | |
| 151 | +arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, | |
| 152 | + unsigned long start, unsigned long end) | |
| 152 | 153 | { |
| 153 | 154 | tlb->mm = mm; |
| 154 | 155 | tlb->fullmm = !(start | (end+1)); |
| @@ -166,8 +167,14 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start · 11 unmodified lines | ||
| 166 | 167 | } |
| 167 | 168 | |
| 168 | 169 | static inline void |
| 169 | −tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) | |
| 170 | +arch_tlb_finish_mmu(struct mmu_gather *tlb, | |
| 171 | + unsigned long start, unsigned long end, bool force) | |
| 170 | 172 | { |
| 173 | + if (force) { | |
| 174 | + tlb->range_start = start; | |
| 175 | + tlb->range_end = end; | |
| 176 | + } | |
| 177 | + | |
| 171 | 178 | tlb_flush_mmu(tlb); |
| 172 | 179 | |
| 173 | 180 | /* keep the page table cache within bounds */ |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | menuconfig ARCH_AT91 |
| 2 | 2 | bool "Atmel SoCs" |
| 3 | 3 | depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M |
| 4 | − select ARM_CPU_SUSPEND if PM | |
| 4 | + select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7 | |
| 5 | 5 | select COMMON_CLK_AT91 |
| 6 | 6 | select GPIOLIB |
| 7 | 7 | select PINCTRL |
| @@ -608,6 +608,9 @@ static void __init at91_pm_init(void (*pm_idle)(void)) · 607 unmodified lines | ||
| 608 | 608 | |
| 609 | 609 | void __init at91rm9200_pm_init(void) |
| 610 | 610 | { |
| 611 | + if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) | |
| 612 | + return; | |
| 613 | + | |
| 611 | 614 | at91_dt_ramc(); |
| 612 | 615 | |
| 613 | 616 | /* |
| @@ -620,18 +623,27 @@ void __init at91rm9200_pm_init(void) · 6 unmodified lines | ||
| 620 | 623 | |
| 621 | 624 | void __init at91sam9_pm_init(void) |
| 622 | 625 | { |
| 626 | + if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) | |
| 627 | + return; | |
| 628 | + | |
| 623 | 629 | at91_dt_ramc(); |
| 624 | 630 | at91_pm_init(at91sam9_idle); |
| 625 | 631 | } |
| 626 | 632 | |
| 627 | 633 | void __init sama5_pm_init(void) |
| 628 | 634 | { |
| 635 | + if (!IS_ENABLED(CONFIG_SOC_SAMA5)) | |
| 636 | + return; | |
| 637 | + | |
| 629 | 638 | at91_dt_ramc(); |
| 630 | 639 | at91_pm_init(NULL); |
| 631 | 640 | } |
| 632 | 641 | |
| 633 | 642 | void __init sama5d2_pm_init(void) |
| 634 | 643 | { |
| 644 | + if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) | |
| 645 | + return; | |
| 646 | + | |
| 635 | 647 | at91_pm_backup_init(); |
| 636 | 648 | sama5_pm_init(); |
| 637 | 649 | } |
| @@ -1166,7 +1166,7 @@ static struct tvp514x_platform_data tvp5146_pdata = { · 1165 unmodified lines | ||
| 1166 | 1166 | |
| 1167 | 1167 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) |
| 1168 | 1168 | |
| 1169 | −static const struct vpif_input da850_ch0_inputs[] = { | |
| 1169 | +static struct vpif_input da850_ch0_inputs[] = { | |
| 1170 | 1170 | { |
| 1171 | 1171 | .input = { |
| 1172 | 1172 | .index = 0, |
| @@ -1181,7 +1181,7 @@ static const struct vpif_input da850_ch0_inputs[] = { · 8 unmodified lines | ||
| 1181 | 1181 | }, |
| 1182 | 1182 | }; |
| 1183 | 1183 | |
| 1184 | −static const struct vpif_input da850_ch1_inputs[] = { | |
| 1184 | +static struct vpif_input da850_ch1_inputs[] = { | |
| 1185 | 1185 | { |
| 1186 | 1186 | .input = { |
| 1187 | 1187 | .index = 0, |
| @@ -218,6 +218,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent) · 217 unmodified lines | ||
| 218 | 218 | } |
| 219 | 219 | EXPORT_SYMBOL(clk_set_parent); |
| 220 | 220 | |
| 221 | +struct clk *clk_get_parent(struct clk *clk) | |
| 222 | +{ | |
| 223 | + if (!clk) | |
| 224 | + return NULL; | |
| 225 | + | |
| 226 | + return clk->parent; | |
| 227 | +} | |
| 228 | +EXPORT_SYMBOL(clk_get_parent); | |
| 229 | + | |
| 221 | 230 | int clk_register(struct clk *clk) |
| 222 | 231 | { |
| 223 | 232 | if (clk == NULL || IS_ERR(clk)) |
| @@ -475,6 +475,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate) · 474 unmodified lines | ||
| 475 | 475 | } |
| 476 | 476 | EXPORT_SYMBOL(clk_set_rate); |
| 477 | 477 | |
| 478 | +long clk_round_rate(struct clk *clk, unsigned long rate) | |
| 479 | +{ | |
| 480 | + WARN_ON(clk); | |
| 481 | + return 0; | |
| 482 | +} | |
| 483 | +EXPORT_SYMBOL(clk_round_rate); | |
| 484 | + | |
| 485 | +int clk_set_parent(struct clk *clk, struct clk *parent) | |
| 486 | +{ | |
| 487 | + WARN_ON(clk); | |
| 488 | + return 0; | |
| 489 | +} | |
| 490 | +EXPORT_SYMBOL(clk_set_parent); | |
| 491 | + | |
| 492 | +struct clk *clk_get_parent(struct clk *clk) | |
| 493 | +{ | |
| 494 | + return clk->parent; | |
| 495 | +} | |
| 496 | +EXPORT_SYMBOL(clk_get_parent); | |
| 497 | + | |
| 478 | 498 | |
| 479 | 499 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; |
| 480 | 500 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; |
| @@ -95,8 +95,10 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p) · 94 unmodified lines | ||
| 95 | 95 | } |
| 96 | 96 | |
| 97 | 97 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
| 98 | − const u8 *vaddr, int count) | |
| 98 | + const void *p, int count) | |
| 99 | 99 | { |
| 100 | + const u8 *vaddr = p; | |
| 101 | + | |
| 100 | 102 | while (count--) |
| 101 | 103 | writeb(*vaddr++, bus_addr); |
| 102 | 104 | } |
| @@ -118,8 +120,10 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p) · 15 unmodified lines | ||
| 118 | 120 | } |
| 119 | 121 | |
| 120 | 122 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
| 121 | − const u16 *vaddr, int count) | |
| 123 | + const void *p, int count) | |
| 122 | 124 | { |
| 125 | + const u16 *vaddr = p; | |
| 126 | + | |
| 123 | 127 | while (count--) |
| 124 | 128 | writew(*vaddr++, bus_addr); |
| 125 | 129 | } |
| @@ -137,8 +141,9 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p) · 11 unmodified lines | ||
| 137 | 141 | } |
| 138 | 142 | |
| 139 | 143 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
| 140 | − const u32 *vaddr, int count) | |
| 144 | + const void *p, int count) | |
| 141 | 145 | { |
| 146 | + const u32 *vaddr = p; | |
| 142 | 147 | while (count--) |
| 143 | 148 | writel(*vaddr++, bus_addr); |
| 144 | 149 | } |
| @@ -160,8 +165,10 @@ static inline u8 __indirect_readb(const volatile void __iomem *p) · 15 unmodified lines | ||
| 160 | 165 | } |
| 161 | 166 | |
| 162 | 167 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
| 163 | − u8 *vaddr, u32 count) | |
| 168 | + void *p, u32 count) | |
| 164 | 169 | { |
| 170 | + u8 *vaddr = p; | |
| 171 | + | |
| 165 | 172 | while (count--) |
| 166 | 173 | *vaddr++ = readb(bus_addr); |
| 167 | 174 | } |
| @@ -183,8 +190,10 @@ static inline u16 __indirect_readw(const volatile void __iomem *p) · 15 unmodified lines | ||
| 183 | 190 | } |
| 184 | 191 | |
| 185 | 192 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
| 186 | − u16 *vaddr, u32 count) | |
| 193 | + void *p, u32 count) | |
| 187 | 194 | { |
| 195 | + u16 *vaddr = p; | |
| 196 | + | |
| 188 | 197 | while (count--) |
| 189 | 198 | *vaddr++ = readw(bus_addr); |
| 190 | 199 | } |
| @@ -204,8 +213,10 @@ static inline u32 __indirect_readl(const volatile void __iomem *p) · 13 unmodified lines | ||
| 204 | 213 | } |
| 205 | 214 | |
| 206 | 215 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
| 207 | − u32 *vaddr, u32 count) | |
| 216 | + void *p, u32 count) | |
| 208 | 217 | { |
| 218 | + u32 *vaddr = p; | |
| 219 | + | |
| 209 | 220 | while (count--) |
| 210 | 221 | *vaddr++ = readl(bus_addr); |
| 211 | 222 | } |
| @@ -523,8 +534,15 @@ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, · 311 unmodified lines | ||
| 523 | 534 | #endif |
| 524 | 535 | } |
| 525 | 536 | |
| 526 | −#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) | |
| 527 | −#define ioport_unmap(addr) | |
| 537 | +#define ioport_map(port, nr) ioport_map(port, nr) | |
| 538 | +static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) | |
| 539 | +{ | |
| 540 | + return ((void __iomem*)((port) + PIO_OFFSET)); | |
| 541 | +} | |
| 542 | +#define ioport_unmap(addr) ioport_unmap(addr) | |
| 543 | +static inline void ioport_unmap(void __iomem *addr) | |
| 544 | +{ | |
| 545 | +} | |
| 528 | 546 | #endif /* CONFIG_PCI */ |
| 529 | 547 | |
| 530 | 548 | #endif /* __ASM_ARM_ARCH_IO_H */ |
| @@ -238,7 +238,7 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg) · 237 unmodified lines | ||
| 238 | 238 | #endif |
| 239 | 239 | |
| 240 | 240 | #if IS_ENABLED(CONFIG_USB_SUPPORT) |
| 241 | −static u64 usb_dma_mask = ~(u32)0; | |
| 241 | +static u64 __maybe_unused usb_dma_mask = ~(u32)0; | |
| 242 | 242 | |
| 243 | 243 | #if IS_ENABLED(CONFIG_USB_MV_UDC) |
| 244 | 244 | struct resource pxa168_u2o_resources[] = { |
| @@ -211,7 +211,7 @@ static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr) · 210 unmodified lines | ||
| 211 | 211 | return PTR_ERR(base); |
| 212 | 212 | |
| 213 | 213 | writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG); |
| 214 | − writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG); | |
| 214 | + writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG); | |
| 215 | 215 | |
| 216 | 216 | iounmap(base); |
| 217 | 217 | |
| @@ -510,6 +510,7 @@ static void __init ams_delta_init(void) · 509 unmodified lines | ||
| 510 | 510 | static void modem_pm(struct uart_port *port, unsigned int state, unsigned old) |
| 511 | 511 | { |
| 512 | 512 | struct modem_private_data *priv = port->private_data; |
| 513 | + int ret; | |
| 513 | 514 | |
| 514 | 515 | if (IS_ERR(priv->regulator)) |
| 515 | 516 | return; |
| @@ -518,9 +519,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old) · 2 unmodified lines | ||
| 518 | 519 | return; |
| 519 | 520 | |
| 520 | 521 | if (state == 0) |
| 521 | − regulator_enable(priv->regulator); | |
| 522 | + ret = regulator_enable(priv->regulator); | |
| 522 | 523 | else if (old == 0) |
| 523 | − regulator_disable(priv->regulator); | |
| 524 | + ret = regulator_disable(priv->regulator); | |
| 525 | + else | |
| 526 | + ret = 0; | |
| 527 | + | |
| 528 | + if (ret) | |
| 529 | + dev_warn(port->dev, | |
| 530 | + "ams_delta modem_pm: failed to %sable regulator: %d\n", | |
| 531 | + state ? "dis" : "en", ret); | |
| 524 | 532 | } |
| 525 | 533 | |
| 526 | 534 | static struct plat_serial8250_port ams_delta_modem_ports[] = { |
| @@ -441,13 +441,11 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { { · 440 unmodified lines | ||
| 441 | 441 | .chip_select = 0, |
| 442 | 442 | } }; |
| 443 | 443 | |
| 444 | −#ifdef CONFIG_PM | |
| 445 | 444 | static irqreturn_t |
| 446 | 445 | osk_mistral_wake_interrupt(int irq, void *ignored) |
| 447 | 446 | { |
| 448 | 447 | return IRQ_HANDLED; |
| 449 | 448 | } |
| 450 | −#endif | |
| 451 | 449 | |
| 452 | 450 | static void __init osk_mistral_init(void) |
| 453 | 451 | { |
| @@ -515,7 +513,6 @@ static void __init osk_mistral_init(void) · 61 unmodified lines | ||
| 515 | 513 | |
| 516 | 514 | gpio_direction_input(OMAP_MPUIO(2)); |
| 517 | 515 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
| 518 | −#ifdef CONFIG_PM | |
| 519 | 516 | /* share the IRQ in case someone wants to use the |
| 520 | 517 | * button for more than wakeup from system sleep. |
| 521 | 518 | */ |
| @@ -529,7 +526,6 @@ static void __init osk_mistral_init(void) · 7 unmodified lines | ||
| 529 | 526 | ret); |
| 530 | 527 | } else |
| 531 | 528 | enable_irq_wake(irq); |
| 532 | −#endif | |
| 533 | 529 | } else |
| 534 | 530 | printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); |
| 535 | 531 | |
| @@ -28,7 +28,7 @@ static const struct of_device_id omap_dt_match_table[] __initconst = { · 27 unmodified lines | ||
| 28 | 28 | { } |
| 29 | 29 | }; |
| 30 | 30 | |
| 31 | −static void __init omap_generic_init(void) | |
| 31 | +static void __init __maybe_unused omap_generic_init(void) | |
| 32 | 32 | { |
| 33 | 33 | pdata_quirks_init(omap_dt_match_table); |
| 34 | 34 | |
| @@ -410,7 +410,7 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) · 409 unmodified lines | ||
| 410 | 410 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); |
| 411 | 411 | } |
| 412 | 412 | |
| 413 | −static void __init omap_hwmod_init_postsetup(void) | |
| 413 | +static void __init __maybe_unused omap_hwmod_init_postsetup(void) | |
| 414 | 414 | { |
| 415 | 415 | u8 postsetup_state; |
| 416 | 416 | |
| @@ -486,7 +486,6 @@ int __init omap3_pm_init(void) · 485 unmodified lines | ||
| 486 | 486 | ret = request_irq(omap_prcm_event_to_irq("io"), |
| 487 | 487 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", |
| 488 | 488 | omap3_pm_init); |
| 489 | − enable_irq(omap_prcm_event_to_irq("io")); | |
| 490 | 489 | |
| 491 | 490 | if (ret) { |
| 492 | 491 | pr_err("pm: Failed to request pm_io irq\n"); |
| @@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void) · 691 unmodified lines | ||
| 692 | 692 | { |
| 693 | 693 | struct device_node *np; |
| 694 | 694 | int irq_num; |
| 695 | − int ret; | |
| 696 | 695 | |
| 697 | 696 | if (!(prm_features & PRM_HAS_IO_WAKEUP)) |
| 698 | 697 | return 0; |
| @@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void) · 13 unmodified lines | ||
| 712 | 711 | } |
| 713 | 712 | |
| 714 | 713 | omap3xxx_prm_enable_io_wakeup(); |
| 715 | − ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); | |
| 716 | − if (!ret) | |
| 717 | − irq_set_status_flags(omap_prcm_event_to_irq("io"), | |
| 718 | − IRQ_NOAUTOEN); | |
| 719 | 714 | |
| 720 | − return ret; | |
| 715 | + return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); | |
| 721 | 716 | } |
| 722 | 717 | |
| 723 | 718 | static void __exit omap3xxx_prm_exit(void) |
| @@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void) · 335 unmodified lines | ||
| 336 | 336 | return; |
| 337 | 337 | } |
| 338 | 338 | |
| 339 | +/** | |
| 340 | + * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches | |
| 341 | + * | |
| 342 | + * Activates the I/O wakeup event latches and allows events logged by | |
| 343 | + * those latches to signal a wakeup event to the PRCM. For I/O wakeups | |
| 344 | + * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and | |
| 345 | + * omap44xx_prm_reconfigure_io_chain() must be called. No return value. | |
| 346 | + */ | |
| 347 | +static void __init omap44xx_prm_enable_io_wakeup(void) | |
| 348 | +{ | |
| 349 | + s32 inst = omap4_prmst_get_prm_dev_inst(); | |
| 350 | + | |
| 351 | + if (inst == PRM_INSTANCE_UNKNOWN) | |
| 352 | + return; | |
| 353 | + | |
| 354 | + omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, | |
| 355 | + OMAP4430_GLOBAL_WUEN_MASK, | |
| 356 | + inst, | |
| 357 | + omap4_prcm_irq_setup.pm_ctrl); | |
| 358 | +} | |
| 359 | + | |
| 339 | 360 | /** |
| 340 | 361 | * omap44xx_prm_read_reset_sources - return the last SoC reset source |
| 341 | 362 | * |
| @@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = { · 326 unmodified lines | ||
| 668 | 689 | .pwrdm_has_voltdm = omap4_check_vcvp, |
| 669 | 690 | }; |
| 670 | 691 | |
| 692 | +static int omap44xx_prm_late_init(void); | |
| 693 | + | |
| 671 | 694 | /* |
| 672 | 695 | * XXX document |
| 673 | 696 | */ |
| @@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { · 1 unmodified line | ||
| 675 | 698 | .read_reset_sources = &omap44xx_prm_read_reset_sources, |
| 676 | 699 | .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, |
| 677 | 700 | .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, |
| 701 | + .late_init = &omap44xx_prm_late_init, | |
| 678 | 702 | .assert_hardreset = omap4_prminst_assert_hardreset, |
| 679 | 703 | .deassert_hardreset = omap4_prminst_deassert_hardreset, |
| 680 | 704 | .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, |
| @@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data) · 30 unmodified lines | ||
| 711 | 735 | return prm_register(&omap44xx_prm_ll_data); |
| 712 | 736 | } |
| 713 | 737 | |
| 738 | +static int omap44xx_prm_late_init(void) | |
| 739 | +{ | |
| 740 | + int irq_num; | |
| 741 | + | |
| 742 | + if (!(prm_features & PRM_HAS_IO_WAKEUP)) | |
| 743 | + return 0; | |
| 744 | + | |
| 745 | + irq_num = of_irq_get(prm_init_data->np, 0); | |
| 746 | + /* | |
| 747 | + * Already have OMAP4 IRQ num. For all other platforms, we need | |
| 748 | + * IRQ numbers from DT | |
| 749 | + */ | |
| 750 | + if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) { | |
| 751 | + if (irq_num == -EPROBE_DEFER) | |
| 752 | + return irq_num; | |
| 753 | + | |
| 754 | + /* Have nothing to do */ | |
| 755 | + return 0; | |
| 756 | + } | |
| 757 | + | |
| 758 | + /* Once OMAP4 DT is filled as well */ | |
| 759 | + if (irq_num >= 0) { | |
| 760 | + omap4_prcm_irq_setup.irq = irq_num; | |
| 761 | + omap4_prcm_irq_setup.xlate_irq = NULL; | |
| 762 | + } | |
| 763 | + | |
| 764 | + omap44xx_prm_enable_io_wakeup(); | |
| 765 | + | |
| 766 | + return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); | |
| 767 | +} | |
| 768 | + | |
| 714 | 769 | static void __exit omap44xx_prm_exit(void) |
| 715 | 770 | { |
| 716 | 771 | prm_unregister(&omap44xx_prm_ll_data); |
| @@ -15,7 +15,7 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <linux/of_platform.h> |
| 16 | 16 | #include "common.h" |
| 17 | 17 | |
| 18 | −static void __init sirfsoc_init_late(void) | |
| 18 | +static void __init __maybe_unused sirfsoc_init_late(void) | |
| 19 | 19 | { |
| 20 | 20 | sirfsoc_pm_init(); |
| 21 | 21 | } |
| @@ -566,6 +566,7 @@ config MACH_ICONTROL · 565 unmodified lines | ||
| 566 | 566 | config ARCH_PXA_ESERIES |
| 567 | 567 | bool "PXA based Toshiba e-series PDAs" |
| 568 | 568 | select FB_W100 |
| 569 | + select FB | |
| 569 | 570 | select PXA25x |
| 570 | 571 | |
| 571 | 572 | config MACH_E330 |
| @@ -17,11 +17,15 @@ · 16 unmodified lines | ||
| 17 | 17 | |
| 18 | 18 | #include <mach/regs-ost.h> |
| 19 | 19 | |
| 20 | −#define xip_irqpending() (ICIP & ICMR) | |
| 20 | +/* restored July 2017, this did not build since 2011! */ | |
| 21 | + | |
| 22 | +#define ICIP io_p2v(0x40d00000) | |
| 23 | +#define ICMR io_p2v(0x40d00004) | |
| 24 | +#define xip_irqpending() (readl(ICIP) & readl(ICMR)) | |
| 21 | 25 | |
| 22 | 26 | /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ |
| 23 | −#define xip_currtime() (OSCR) | |
| 24 | −#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) | |
| 27 | +#define xip_currtime() readl(OSCR) | |
| 28 | +#define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4) | |
| 25 | 29 | |
| 26 | 30 | /* |
| 27 | 31 | * xip_cpu_idle() is used when waiting for a delay equal or larger than |
| @@ -25,8 +25,8 @@ · 24 unmodified lines | ||
| 25 | 25 | * *_SIZE is the size of the region |
| 26 | 26 | * *_BASE is the virtual address |
| 27 | 27 | */ |
| 28 | −#define RAM_SIZE 0x10000000 | |
| 29 | −#define RAM_START 0x10000000 | |
| 28 | +#define RPC_RAM_SIZE 0x10000000 | |
| 29 | +#define RPC_RAM_START 0x10000000 | |
| 30 | 30 | |
| 31 | 31 | #define EASI_SIZE 0x08000000 /* EASI I/O */ |
| 32 | 32 | #define EASI_START 0x08000000 |
| @@ -35,6 +35,31 @@ struct clk clk_##_name = { \ · 34 unmodified lines | ||
| 35 | 35 | |
| 36 | 36 | static DEFINE_SPINLOCK(clocks_lock); |
| 37 | 37 | |
| 38 | +/* Dummy clk routine to build generic kernel parts that may be using them */ | |
| 39 | +long clk_round_rate(struct clk *clk, unsigned long rate) | |
| 40 | +{ | |
| 41 | + return clk_get_rate(clk); | |
| 42 | +} | |
| 43 | +EXPORT_SYMBOL(clk_round_rate); | |
| 44 | + | |
| 45 | +int clk_set_rate(struct clk *clk, unsigned long rate) | |
| 46 | +{ | |
| 47 | + return 0; | |
| 48 | +} | |
| 49 | +EXPORT_SYMBOL(clk_set_rate); | |
| 50 | + | |
| 51 | +int clk_set_parent(struct clk *clk, struct clk *parent) | |
| 52 | +{ | |
| 53 | + return 0; | |
| 54 | +} | |
| 55 | +EXPORT_SYMBOL(clk_set_parent); | |
| 56 | + | |
| 57 | +struct clk *clk_get_parent(struct clk *clk) | |
| 58 | +{ | |
| 59 | + return NULL; | |
| 60 | +} | |
| 61 | +EXPORT_SYMBOL(clk_get_parent); | |
| 62 | + | |
| 38 | 63 | static void clk_gpio27_enable(struct clk *clk) |
| 39 | 64 | { |
| 40 | 65 | /* |
| @@ -20,7 +20,7 @@ · 19 unmodified lines | ||
| 20 | 20 | #define xip_irqpending() (ICIP & ICMR) |
| 21 | 21 | |
| 22 | 22 | /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ |
| 23 | −#define xip_currtime() (OSCR) | |
| 24 | −#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) | |
| 23 | +#define xip_currtime() readl_relaxed(OSCR) | |
| 24 | +#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4) | |
| 25 | 25 | |
| 26 | 26 | #endif /* __ARCH_SA1100_MTD_XIP_H__ */ |
| @@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb, · 66 unmodified lines | ||
| 67 | 67 | { |
| 68 | 68 | struct device *dev = data; |
| 69 | 69 | struct i2c_client *client; |
| 70 | + static bool done; | |
| 70 | 71 | u32 mon; |
| 71 | 72 | |
| 73 | + if (done) | |
| 74 | + return 0; | |
| 75 | + | |
| 72 | 76 | mon = ioread32(irqc + IRQC_MONITOR); |
| 73 | 77 | dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon); |
| 74 | 78 | if (mon & REGULATOR_IRQ_MASK) |
| @@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb, · 24 unmodified lines | ||
| 99 | 103 | remove: |
| 100 | 104 | dev_info(dev, "IRQ2 is not asserted, removing quirk\n"); |
| 101 | 105 | |
| 102 | − bus_unregister_notifier(&i2c_bus_type, nb); | |
| 106 | + done = true; | |
| 103 | 107 | iounmap(irqc); |
| 104 | 108 | return 0; |
| 105 | 109 | } |
| @@ -93,3 +93,32 @@ void nuc900_subclk_enable(struct clk *clk, int enable) · 92 unmodified lines | ||
| 93 | 93 | |
| 94 | 94 | __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK); |
| 95 | 95 | } |
| 96 | + | |
| 97 | +/* dummy functions, should not be called */ | |
| 98 | +long clk_round_rate(struct clk *clk, unsigned long rate) | |
| 99 | +{ | |
| 100 | + WARN_ON(clk); | |
| 101 | + return 0; | |
| 102 | +} | |
| 103 | +EXPORT_SYMBOL(clk_round_rate); | |
| 104 | + | |
| 105 | +int clk_set_rate(struct clk *clk, unsigned long rate) | |
| 106 | +{ | |
| 107 | + WARN_ON(clk); | |
| 108 | + return 0; | |
| 109 | +} | |
| 110 | +EXPORT_SYMBOL(clk_set_rate); | |
| 111 | + | |
| 112 | +int clk_set_parent(struct clk *clk, struct clk *parent) | |
| 113 | +{ | |
| 114 | + WARN_ON(clk); | |
| 115 | + return 0; | |
| 116 | +} | |
| 117 | +EXPORT_SYMBOL(clk_set_parent); | |
| 118 | + | |
| 119 | +struct clk *clk_get_parent(struct clk *clk) | |
| 120 | +{ | |
| 121 | + WARN_ON(clk); | |
| 122 | + return NULL; | |
| 123 | +} | |
| 124 | +EXPORT_SYMBOL(clk_get_parent); | |
| @@ -51,6 +51,7 @@ · 50 unmodified lines | ||
| 51 | 51 | compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; |
| 52 | 52 | |
| 53 | 53 | aliases { |
| 54 | + ethernet0 = &emac; | |
| 54 | 55 | serial0 = &uart0; |
| 55 | 56 | serial1 = &uart1; |
| 56 | 57 | }; |
| @@ -51,6 +51,7 @@ · 50 unmodified lines | ||
| 51 | 51 | compatible = "pine64,pine64", "allwinner,sun50i-a64"; |
| 52 | 52 | |
| 53 | 53 | aliases { |
| 54 | + ethernet0 = &emac; | |
| 54 | 55 | serial0 = &uart0; |
| 55 | 56 | serial1 = &uart1; |
| 56 | 57 | serial2 = &uart2; |
| @@ -53,6 +53,7 @@ · 52 unmodified lines | ||
| 53 | 53 | "allwinner,sun50i-a64"; |
| 54 | 54 | |
| 55 | 55 | aliases { |
| 56 | + ethernet0 = &emac; | |
| 56 | 57 | serial0 = &uart0; |
| 57 | 58 | }; |
| 58 | 59 | |
| @@ -452,7 +452,7 @@ · 451 unmodified lines | ||
| 452 | 452 | emac: ethernet@1c30000 { |
| 453 | 453 | compatible = "allwinner,sun50i-a64-emac"; |
| 454 | 454 | syscon = <&syscon>; |
| 455 | − reg = <0x01c30000 0x100>; | |
| 455 | + reg = <0x01c30000 0x10000>; | |
| 456 | 456 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 457 | 457 | interrupt-names = "macirq"; |
| 458 | 458 | resets = <&ccu RST_BUS_EMAC>; |
| @@ -120,5 +120,8 @@ · 119 unmodified lines | ||
| 120 | 120 | }; |
| 121 | 121 | |
| 122 | 122 | &pio { |
| 123 | + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
| 124 | + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, | |
| 125 | + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 123 | 126 | compatible = "allwinner,sun50i-h5-pinctrl"; |
| 124 | 127 | }; |
| @@ -400,7 +400,7 @@ · 399 unmodified lines | ||
| 400 | 400 | }; |
| 401 | 401 | |
| 402 | 402 | pwm_AO_ab: pwm@550 { |
| 403 | − compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; | |
| 403 | + compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; | |
| 404 | 404 | reg = <0x0 0x00550 0x0 0x10>; |
| 405 | 405 | #pwm-cells = <3>; |
| 406 | 406 | status = "disabled"; |
| @@ -109,8 +109,8 @@ · 108 unmodified lines | ||
| 109 | 109 | status = "okay"; |
| 110 | 110 | pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; |
| 111 | 111 | pinctrl-names = "default"; |
| 112 | − clocks = <&clkc CLKID_FCLK_DIV4>; | |
| 113 | − clock-names = "clkin0"; | |
| 112 | + clocks = <&xtal> , <&xtal>; | |
| 113 | + clock-names = "clkin0", "clkin1" ; | |
| 114 | 114 | }; |
| 115 | 115 | |
| 116 | 116 | &pwm_ef { |
| @@ -10,12 +10,20 @@ · 9 unmodified lines | ||
| 10 | 10 | |
| 11 | 11 | #include <dt-bindings/input/input.h> |
| 12 | 12 | |
| 13 | −#include "meson-gxl-s905x-p212.dtsi" | |
| 13 | +#include "meson-gxl-s905x.dtsi" | |
| 14 | 14 | |
| 15 | 15 | / { |
| 16 | 16 | compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; |
| 17 | 17 | model = "Libre Technology CC"; |
| 18 | 18 | |
| 19 | + aliases { | |
| 20 | + serial0 = &uart_AO; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + chosen { | |
| 24 | + stdout-path = "serial0:115200n8"; | |
| 25 | + }; | |
| 26 | + | |
| 19 | 27 | cvbs-connector { |
| 20 | 28 | compatible = "composite-video-connector"; |
| 21 | 29 | |
| @@ -26,6 +34,11 @@ · 4 unmodified lines | ||
| 26 | 34 | }; |
| 27 | 35 | }; |
| 28 | 36 | |
| 37 | + emmc_pwrseq: emmc-pwrseq { | |
| 38 | + compatible = "mmc-pwrseq-emmc"; | |
| 39 | + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; | |
| 40 | + }; | |
| 41 | + | |
| 29 | 42 | hdmi-connector { |
| 30 | 43 | compatible = "hdmi-connector"; |
| 31 | 44 | type = "a"; |
| @@ -53,6 +66,39 @@ · 21 unmodified lines | ||
| 53 | 66 | linux,default-trigger = "heartbeat"; |
| 54 | 67 | }; |
| 55 | 68 | }; |
| 69 | + | |
| 70 | + memory@0 { | |
| 71 | + device_type = "memory"; | |
| 72 | + reg = <0x0 0x0 0x0 0x80000000>; | |
| 73 | + }; | |
| 74 | + | |
| 75 | + vcc_3v3: regulator-vcc_3v3 { | |
| 76 | + compatible = "regulator-fixed"; | |
| 77 | + regulator-name = "VCC_3V3"; | |
| 78 | + regulator-min-microvolt = <3300000>; | |
| 79 | + regulator-max-microvolt = <3300000>; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + vcc_card: regulator-vcc-card { | |
| 83 | + compatible = "regulator-gpio"; | |
| 84 | + | |
| 85 | + regulator-name = "VCC_CARD"; | |
| 86 | + regulator-min-microvolt = <1800000>; | |
| 87 | + regulator-max-microvolt = <3300000>; | |
| 88 | + | |
| 89 | + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; | |
| 90 | + gpios-states = <0>; | |
| 91 | + | |
| 92 | + states = <3300000 0>, | |
| 93 | + <1800000 1>; | |
| 94 | + }; | |
| 95 | + | |
| 96 | + vddio_boot: regulator-vddio_boot { | |
| 97 | + compatible = "regulator-fixed"; | |
| 98 | + regulator-name = "VDDIO_BOOT"; | |
| 99 | + regulator-min-microvolt = <3300000>; | |
| 100 | + regulator-max-microvolt = <3300000>; | |
| 101 | + }; | |
| 56 | 102 | }; |
| 57 | 103 | |
| 58 | 104 | &cvbs_vdac_port { |
| @@ -61,6 +107,16 @@ · 2 unmodified lines | ||
| 61 | 107 | }; |
| 62 | 108 | }; |
| 63 | 109 | |
| 110 | +ðmac { | |
| 111 | + status = "okay"; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&ir { | |
| 115 | + status = "okay"; | |
| 116 | + pinctrl-0 = <&remote_input_ao_pins>; | |
| 117 | + pinctrl-names = "default"; | |
| 118 | +}; | |
| 119 | + | |
| 64 | 120 | &hdmi_tx { |
| 65 | 121 | status = "okay"; |
| 66 | 122 | pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; |
| @@ -73,20 +129,43 @@ · 6 unmodified lines | ||
| 73 | 129 | }; |
| 74 | 130 | }; |
| 75 | 131 | |
| 76 | −/* | |
| 77 | − * The following devices exists but are exposed on the general | |
| 78 | − * purpose GPIO header. End user may well decide to use those pins | |
| 79 | − * for another purpose | |
| 80 | − */ | |
| 132 | +/* SD card */ | |
| 133 | +&sd_emmc_b { | |
| 134 | + status = "okay"; | |
| 135 | + pinctrl-0 = <&sdcard_pins>; | |
| 136 | + pinctrl-names = "default"; | |
| 137 | + | |
| 138 | + bus-width = <4>; | |
| 139 | + cap-sd-highspeed; | |
| 140 | + max-frequency = <100000000>; | |
| 141 | + disable-wp; | |
| 142 | + | |
| 143 | + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; | |
| 144 | + cd-inverted; | |
| 81 | 145 | |
| 82 | −&sd_emmc_a { | |
| 83 | − status = "disabled"; | |
| 146 | + vmmc-supply = <&vcc_3v3>; | |
| 147 | + vqmmc-supply = <&vcc_card>; | |
| 84 | 148 | }; |
| 85 | 149 | |
| 86 | −&uart_A { | |
| 87 | − status = "disabled"; | |
| 150 | +/* eMMC */ | |
| 151 | +&sd_emmc_c { | |
| 152 | + status = "okay"; | |
| 153 | + pinctrl-0 = <&emmc_pins>; | |
| 154 | + pinctrl-names = "default"; | |
| 155 | + | |
| 156 | + bus-width = <8>; | |
| 157 | + cap-mmc-highspeed; | |
| 158 | + max-frequency = <50000000>; | |
| 159 | + non-removable; | |
| 160 | + disable-wp; | |
| 161 | + | |
| 162 | + mmc-pwrseq = <&emmc_pwrseq>; | |
| 163 | + vmmc-supply = <&vcc_3v3>; | |
| 164 | + vqmmc-supply = <&vddio_boot>; | |
| 88 | 165 | }; |
| 89 | 166 | |
| 90 | −&wifi32k { | |
| 91 | − status = "disabled"; | |
| 167 | +&uart_AO { | |
| 168 | + status = "okay"; | |
| 169 | + pinctrl-0 = <&uart_ao_a_pins>; | |
| 170 | + pinctrl-names = "default"; | |
| 92 | 171 | }; |
| @@ -219,7 +219,7 @@ · 218 unmodified lines | ||
| 219 | 219 | reg = <0x18800 0x100>, <0x18C00 0x20>; |
| 220 | 220 | gpiosb: gpio { |
| 221 | 221 | #gpio-cells = <2>; |
| 222 | − gpio-ranges = <&pinctrl_sb 0 0 29>; | |
| 222 | + gpio-ranges = <&pinctrl_sb 0 0 30>; | |
| 223 | 223 | gpio-controller; |
| 224 | 224 | interrupts = |
| 225 | 225 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
| @@ -270,6 +270,7 @@ · 269 unmodified lines | ||
| 270 | 270 | interrupt-names = "mem", "ring0", "ring1", |
| 271 | 271 | "ring2", "ring3", "eip"; |
| 272 | 272 | clocks = <&cpm_clk 1 26>; |
| 273 | + dma-coherent; | |
| 273 | 274 | }; |
| 274 | 275 | }; |
| 275 | 276 | |
| @@ -64,7 +64,7 @@ · 63 unmodified lines | ||
| 64 | 64 | compatible = "marvell,armada-8k-rtc"; |
| 65 | 65 | reg = <0x284000 0x20>, <0x284080 0x24>; |
| 66 | 66 | reg-names = "rtc", "rtc-soc"; |
| 67 | − interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 67 | + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 68 | 68 | }; |
| 69 | 69 | |
| 70 | 70 | cps_ethernet: ethernet@0 { |
| @@ -261,6 +261,7 @@ · 190 unmodified lines | ||
| 261 | 261 | interrupt-names = "mem", "ring0", "ring1", |
| 262 | 262 | "ring2", "ring3", "eip"; |
| 263 | 263 | clocks = <&cps_clk 1 26>; |
| 264 | + dma-coherent; | |
| 264 | 265 | /* |
| 265 | 266 | * The cryptographic engine found on the cp110 |
| 266 | 267 | * master is enabled by default at the SoC |
| @@ -45,7 +45,7 @@ · 44 unmodified lines | ||
| 45 | 45 | stdout-path = "serial0:115200n8"; |
| 46 | 46 | }; |
| 47 | 47 | |
| 48 | − audio_clkout: audio_clkout { | |
| 48 | + audio_clkout: audio-clkout { | |
| 49 | 49 | /* |
| 50 | 50 | * This is same as <&rcar_sound 0> |
| 51 | 51 | * but needed to avoid cs2000/rcar_sound probe dead-lock |
| @@ -508,7 +508,7 @@ · 456 unmodified lines | ||
| 508 | 508 | |
| 509 | 509 | /* audio_clkout0/1/2/3 */ |
| 510 | 510 | #clock-cells = <1>; |
| 511 | − clock-frequency = <11289600 12288000>; | |
| 511 | + clock-frequency = <12288000 11289600>; | |
| 512 | 512 | |
| 513 | 513 | status = "okay"; |
| 514 | 514 | |
| @@ -281,7 +281,7 @@ · 280 unmodified lines | ||
| 281 | 281 | |
| 282 | 282 | /* audio_clkout0/1/2/3 */ |
| 283 | 283 | #clock-cells = <1>; |
| 284 | − clock-frequency = <11289600 12288000>; | |
| 284 | + clock-frequency = <12288000 11289600>; | |
| 285 | 285 | |
| 286 | 286 | status = "okay"; |
| 287 | 287 | |
| @@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y · 475 unmodified lines | ||
| 476 | 476 | CONFIG_MSM_GCC_8916=y |
| 477 | 477 | CONFIG_MSM_GCC_8994=y |
| 478 | 478 | CONFIG_MSM_MMCC_8996=y |
| 479 | +CONFIG_HWSPINLOCK=y | |
| 479 | 480 | CONFIG_HWSPINLOCK_QCOM=y |
| 480 | 481 | CONFIG_ARM_MHU=y |
| 481 | 482 | CONFIG_PLATFORM_MHU=y |
| @@ -65,13 +65,13 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, · 64 unmodified lines | ||
| 65 | 65 | u64 _val; \ |
| 66 | 66 | if (needs_unstable_timer_counter_workaround()) { \ |
| 67 | 67 | const struct arch_timer_erratum_workaround *wa; \ |
| 68 | − preempt_disable(); \ | |
| 68 | + preempt_disable_notrace(); \ | |
| 69 | 69 | wa = __this_cpu_read(timer_unstable_counter_workaround); \ |
| 70 | 70 | if (wa && wa->read_##reg) \ |
| 71 | 71 | _val = wa->read_##reg(); \ |
| 72 | 72 | else \ |
| 73 | 73 | _val = read_sysreg(reg); \ |
| 74 | − preempt_enable(); \ | |
| 74 | + preempt_enable_notrace(); \ | |
| 75 | 75 | } else { \ |
| 76 | 76 | _val = read_sysreg(reg); \ |
| 77 | 77 | } \ |
| @@ -114,10 +114,10 @@ · 113 unmodified lines | ||
| 114 | 114 | |
| 115 | 115 | /* |
| 116 | 116 | * This is the base location for PIE (ET_DYN with INTERP) loads. On |
| 117 | − * 64-bit, this is raised to 4GB to leave the entire 32-bit address | |
| 117 | + * 64-bit, this is above 4GB to leave the entire 32-bit address | |
| 118 | 118 | * space open for things that want to use the area for 32-bit pointers. |
| 119 | 119 | */ |
| 120 | −#define ELF_ET_DYN_BASE 0x100000000UL | |
| 120 | +#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) | |
| 121 | 121 | |
| 122 | 122 | #ifndef __ASSEMBLY__ |
| 123 | 123 | |
| @@ -64,8 +64,10 @@ · 63 unmodified lines | ||
| 64 | 64 | * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. |
| 65 | 65 | */ |
| 66 | 66 | #define VA_BITS (CONFIG_ARM64_VA_BITS) |
| 67 | −#define VA_START (UL(0xffffffffffffffff) << VA_BITS) | |
| 68 | −#define PAGE_OFFSET (UL(0xffffffffffffffff) << (VA_BITS - 1)) | |
| 67 | +#define VA_START (UL(0xffffffffffffffff) - \ | |
| 68 | + (UL(1) << VA_BITS) + 1) | |
| 69 | +#define PAGE_OFFSET (UL(0xffffffffffffffff) - \ | |
| 70 | + (UL(1) << (VA_BITS - 1)) + 1) | |
| 69 | 71 | #define KIMAGE_VADDR (MODULES_END) |
| 70 | 72 | #define MODULES_END (MODULES_VADDR + MODULES_VSIZE) |
| 71 | 73 | #define MODULES_VADDR (VA_START + KASAN_SHADOW_SIZE) |
| @@ -161,9 +161,11 @@ void fpsimd_flush_thread(void) · 160 unmodified lines | ||
| 161 | 161 | { |
| 162 | 162 | if (!system_supports_fpsimd()) |
| 163 | 163 | return; |
| 164 | + preempt_disable(); | |
| 164 | 165 | memset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state)); |
| 165 | 166 | fpsimd_flush_task_state(current); |
| 166 | 167 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
| 168 | + preempt_enable(); | |
| 167 | 169 | } |
| 168 | 170 | |
| 169 | 171 | /* |
| @@ -354,7 +354,6 @@ __primary_switched: · 353 unmodified lines | ||
| 354 | 354 | tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? |
| 355 | 355 | b.ne 0f |
| 356 | 356 | mov x0, x21 // pass FDT address in x0 |
| 357 | − mov x1, x23 // pass modulo offset in x1 | |
| 358 | 357 | bl kaslr_early_init // parse FDT for KASLR options |
| 359 | 358 | cbz x0, 0f // KASLR disabled? just proceed |
| 360 | 359 | orr x23, x23, x0 // record KASLR offset |
| @@ -75,7 +75,7 @@ extern void *__init __fixmap_remap_fdt(phys_addr_t dt_phys, int *size, · 74 unmodified lines | ||
| 75 | 75 | * containing function pointers) to be reinitialized, and zero-initialized |
| 76 | 76 | * .bss variables will be reset to 0. |
| 77 | 77 | */ |
| 78 | −u64 __init kaslr_early_init(u64 dt_phys, u64 modulo_offset) | |
| 78 | +u64 __init kaslr_early_init(u64 dt_phys) | |
| 79 | 79 | { |
| 80 | 80 | void *fdt; |
| 81 | 81 | u64 seed, offset, mask, module_range; |
| @@ -131,15 +131,17 @@ u64 __init kaslr_early_init(u64 dt_phys, u64 modulo_offset) · 49 unmodified lines | ||
| 131 | 131 | /* |
| 132 | 132 | * The kernel Image should not extend across a 1GB/32MB/512MB alignment |
| 133 | 133 | * boundary (for 4KB/16KB/64KB granule kernels, respectively). If this |
| 134 | − * happens, increase the KASLR offset by the size of the kernel image | |
| 135 | − * rounded up by SWAPPER_BLOCK_SIZE. | |
| 134 | + * happens, round down the KASLR offset by (1 << SWAPPER_TABLE_SHIFT). | |
| 135 | + * | |
| 136 | + * NOTE: The references to _text and _end below will already take the | |
| 137 | + * modulo offset (the physical displacement modulo 2 MB) into | |
| 138 | + * account, given that the physical placement is controlled by | |
| 139 | + * the loader, and will not change as a result of the virtual | |
| 140 | + * mapping we choose. | |
| 136 | 141 | */ |
| 137 | − if ((((u64)_text + offset + modulo_offset) >> SWAPPER_TABLE_SHIFT) != | |
| 138 | − (((u64)_end + offset + modulo_offset) >> SWAPPER_TABLE_SHIFT)) { | |
| 139 | − u64 kimg_sz = _end - _text; | |
| 140 | − offset = (offset + round_up(kimg_sz, SWAPPER_BLOCK_SIZE)) | |
| 141 | − & mask; | |
| 142 | − } | |
| 142 | + if ((((u64)_text + offset) >> SWAPPER_TABLE_SHIFT) != | |
| 143 | + (((u64)_end + offset) >> SWAPPER_TABLE_SHIFT)) | |
| 144 | + offset = round_down(offset, 1 << SWAPPER_TABLE_SHIFT); | |
| 143 | 145 | |
| 144 | 146 | if (IS_ENABLED(CONFIG_KASAN)) |
| 145 | 147 | /* |
| @@ -523,7 +523,7 @@ static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) · 522 unmodified lines | ||
| 523 | 523 | { |
| 524 | 524 | int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; |
| 525 | 525 | |
| 526 | − pt_regs_write_reg(regs, rt, read_sysreg(cntfrq_el0)); | |
| 526 | + pt_regs_write_reg(regs, rt, arch_timer_get_rate()); | |
| 527 | 527 | regs->pc += 4; |
| 528 | 528 | } |
| 529 | 529 | |
| @@ -764,7 +764,7 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, · 763 unmodified lines | ||
| 764 | 764 | if (p->is_write) { |
| 765 | 765 | if (r->CRm & 0x2) |
| 766 | 766 | /* accessing PMOVSSET_EL0 */ |
| 767 | − kvm_pmu_overflow_set(vcpu, p->regval & mask); | |
| 767 | + vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); | |
| 768 | 768 | else |
| 769 | 769 | /* accessing PMOVSCLR_EL0 */ |
| 770 | 770 | vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); |
| @@ -163,26 +163,27 @@ int ptep_set_access_flags(struct vm_area_struct *vma, · 162 unmodified lines | ||
| 163 | 163 | /* only preserve the access flags and write permission */ |
| 164 | 164 | pte_val(entry) &= PTE_AF | PTE_WRITE | PTE_DIRTY; |
| 165 | 165 | |
| 166 | − /* | |
| 167 | − * PTE_RDONLY is cleared by default in the asm below, so set it in | |
| 168 | − * back if necessary (read-only or clean PTE). | |
| 169 | − */ | |
| 166 | + /* set PTE_RDONLY if actual read-only or clean PTE */ | |
| 170 | 167 | if (!pte_write(entry) || !pte_sw_dirty(entry)) |
| 171 | 168 | pte_val(entry) |= PTE_RDONLY; |
| 172 | 169 | |
| 173 | 170 | /* |
| 174 | 171 | * Setting the flags must be done atomically to avoid racing with the |
| 175 | − * hardware update of the access/dirty state. | |
| 172 | + * hardware update of the access/dirty state. The PTE_RDONLY bit must | |
| 173 | + * be set to the most permissive (lowest value) of *ptep and entry | |
| 174 | + * (calculated as: a & b == ~(~a | ~b)). | |
| 176 | 175 | */ |
| 176 | + pte_val(entry) ^= PTE_RDONLY; | |
| 177 | 177 | asm volatile("// ptep_set_access_flags\n" |
| 178 | 178 | " prfm pstl1strm, %2\n" |
| 179 | 179 | "1: ldxr %0, %2\n" |
| 180 | − " and %0, %0, %3 // clear PTE_RDONLY\n" | |
| 180 | + " eor %0, %0, %3 // negate PTE_RDONLY in *ptep\n" | |
| 181 | 181 | " orr %0, %0, %4 // set flags\n" |
| 182 | + " eor %0, %0, %3 // negate final PTE_RDONLY\n" | |
| 182 | 183 | " stxr %w1, %0, %2\n" |
| 183 | 184 | " cbnz %w1, 1b\n" |
| 184 | 185 | : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) |
| 185 | − : "L" (~PTE_RDONLY), "r" (pte_val(entry))); | |
| 186 | + : "L" (PTE_RDONLY), "r" (pte_val(entry))); | |
| 186 | 187 | |
| 187 | 188 | flush_tlb_fix_spurious_fault(vma, address); |
| 188 | 189 | return 1; |
| @@ -434,8 +435,11 @@ retry: · 245 unmodified lines | ||
| 434 | 435 | * the mmap_sem because it would already be released |
| 435 | 436 | * in __lock_page_or_retry in mm/filemap.c. |
| 436 | 437 | */ |
| 437 | − if (fatal_signal_pending(current)) | |
| 438 | + if (fatal_signal_pending(current)) { | |
| 439 | + if (!user_mode(regs)) | |
| 440 | + goto no_context; | |
| 438 | 441 | return 0; |
| 442 | + } | |
| 439 | 443 | |
| 440 | 444 | /* |
| 441 | 445 | * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of |
| @@ -168,7 +168,8 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb) · 167 unmodified lines | ||
| 168 | 168 | |
| 169 | 169 | |
| 170 | 170 | static inline void |
| 171 | −tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end) | |
| 171 | +arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, | |
| 172 | + unsigned long start, unsigned long end) | |
| 172 | 173 | { |
| 173 | 174 | tlb->mm = mm; |
| 174 | 175 | tlb->max = ARRAY_SIZE(tlb->local); |
| @@ -185,8 +186,11 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start · 10 unmodified lines | ||
| 185 | 186 | * collected. |
| 186 | 187 | */ |
| 187 | 188 | static inline void |
| 188 | −tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) | |
| 189 | +arch_tlb_finish_mmu(struct mmu_gather *tlb, | |
| 190 | + unsigned long start, unsigned long end, bool force) | |
| 189 | 191 | { |
| 192 | + if (force) | |
| 193 | + tlb->need_flush = 1; | |
| 190 | 194 | /* |
| 191 | 195 | * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and |
| 192 | 196 | * tlb->end_addr. |
| @@ -2260,7 +2260,7 @@ config CPU_R4K_CACHE_TLB · 2259 unmodified lines | ||
| 2260 | 2260 | |
| 2261 | 2261 | config MIPS_MT_SMP |
| 2262 | 2262 | bool "MIPS MT SMP support (1 TC on each available VPE)" |
| 2263 | − depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 | |
| 2263 | + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS | |
| 2264 | 2264 | select CPU_MIPSR2_IRQ_VI |
| 2265 | 2265 | select CPU_MIPSR2_IRQ_EI |
| 2266 | 2266 | select SYNC_R4K |
| @@ -243,8 +243,21 @@ include arch/mips/Kbuild.platforms · 242 unmodified lines | ||
| 243 | 243 | ifdef CONFIG_PHYSICAL_START |
| 244 | 244 | load-y = $(CONFIG_PHYSICAL_START) |
| 245 | 245 | endif |
| 246 | −entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ | |
| 246 | + | |
| 247 | +entry-noisa-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ | |
| 247 | 248 | | grep "\bkernel_entry\b" | cut -f1 -d \ ) |
| 249 | +ifdef CONFIG_CPU_MICROMIPS | |
| 250 | + # | |
| 251 | + # Set the ISA bit, since the kernel_entry symbol in the ELF will have it | |
| 252 | + # clear which would lead to images containing addresses which bootloaders may | |
| 253 | + # jump to as MIPS32 code. | |
| 254 | + # | |
| 255 | + entry-y = $(patsubst %0,%1,$(patsubst %2,%3,$(patsubst %4,%5, \ | |
| 256 | + $(patsubst %6,%7,$(patsubst %8,%9,$(patsubst %a,%b, \ | |
| 257 | + $(patsubst %c,%d,$(patsubst %e,%f,$(entry-noisa-y))))))))) | |
| 258 | +else | |
| 259 | + entry-y = $(entry-noisa-y) | |
| 260 | +endif | |
| 248 | 261 | |
| 249 | 262 | cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic |
| 250 | 263 | drivers-$(CONFIG_PCI) += arch/mips/pci/ |
| @@ -0,0 +1,2 @@ | ||
| 1 | +ashldi3.c | |
| 2 | +bswapsi.c | |
| @@ -13,9 +13,9 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <linux/mutex.h> |
| 14 | 14 | #include <linux/delay.h> |
| 15 | 15 | #include <linux/of_platform.h> |
| 16 | +#include <linux/io.h> | |
| 16 | 17 | |
| 17 | 18 | #include <asm/octeon/octeon.h> |
| 18 | −#include <asm/octeon/cvmx-gpio-defs.h> | |
| 19 | 19 | |
| 20 | 20 | /* USB Control Register */ |
| 21 | 21 | union cvm_usbdrd_uctl_ctl { |
| @@ -147,23 +147,12 @@ · 146 unmodified lines | ||
| 147 | 147 | * Find irq with highest priority |
| 148 | 148 | */ |
| 149 | 149 | # open coded PTR_LA t1, cpu_mask_nr_tbl |
| 150 | −#if (_MIPS_SZPTR == 32) | |
| 150 | +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) | |
| 151 | 151 | # open coded la t1, cpu_mask_nr_tbl |
| 152 | 152 | lui t1, %hi(cpu_mask_nr_tbl) |
| 153 | 153 | addiu t1, %lo(cpu_mask_nr_tbl) |
| 154 | − | |
| 155 | −#endif | |
| 156 | −#if (_MIPS_SZPTR == 64) | |
| 157 | − # open coded dla t1, cpu_mask_nr_tbl | |
| 158 | − .set push | |
| 159 | − .set noat | |
| 160 | − lui t1, %highest(cpu_mask_nr_tbl) | |
| 161 | − lui AT, %hi(cpu_mask_nr_tbl) | |
| 162 | − daddiu t1, t1, %higher(cpu_mask_nr_tbl) | |
| 163 | − daddiu AT, AT, %lo(cpu_mask_nr_tbl) | |
| 164 | − dsll t1, 32 | |
| 165 | − daddu t1, t1, AT | |
| 166 | − .set pop | |
| 154 | +#else | |
| 155 | +#error GCC `-msym32' option required for 64-bit DECstation builds | |
| 167 | 156 | #endif |
| 168 | 157 | 1: lw t2,(t1) |
| 169 | 158 | nop |
| @@ -214,23 +203,12 @@ · 44 unmodified lines | ||
| 214 | 203 | * Find irq with highest priority |
| 215 | 204 | */ |
| 216 | 205 | # open coded PTR_LA t1,asic_mask_nr_tbl |
| 217 | −#if (_MIPS_SZPTR == 32) | |
| 206 | +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) | |
| 218 | 207 | # open coded la t1, asic_mask_nr_tbl |
| 219 | 208 | lui t1, %hi(asic_mask_nr_tbl) |
| 220 | 209 | addiu t1, %lo(asic_mask_nr_tbl) |
| 221 | − | |
| 222 | −#endif | |
| 223 | −#if (_MIPS_SZPTR == 64) | |
| 224 | − # open coded dla t1, asic_mask_nr_tbl | |
| 225 | − .set push | |
| 226 | − .set noat | |
| 227 | − lui t1, %highest(asic_mask_nr_tbl) | |
| 228 | − lui AT, %hi(asic_mask_nr_tbl) | |
| 229 | − daddiu t1, t1, %higher(asic_mask_nr_tbl) | |
| 230 | − daddiu AT, AT, %lo(asic_mask_nr_tbl) | |
| 231 | − dsll t1, 32 | |
| 232 | − daddu t1, t1, AT | |
| 233 | − .set pop | |
| 210 | +#else | |
| 211 | +#error GCC `-msym32' option required for 64-bit DECstation builds | |
| 234 | 212 | #endif |
| 235 | 213 | 2: lw t2,(t1) |
| 236 | 214 | nop |
| @@ -9,6 +9,8 @@ · 8 unmodified lines | ||
| 9 | 9 | #ifndef _ASM_CACHE_H |
| 10 | 10 | #define _ASM_CACHE_H |
| 11 | 11 | |
| 12 | +#include <kmalloc.h> | |
| 13 | + | |
| 12 | 14 | #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT |
| 13 | 15 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 14 | 16 | |
| @@ -428,6 +428,9 @@ · 427 unmodified lines | ||
| 428 | 428 | #ifndef cpu_scache_line_size |
| 429 | 429 | #define cpu_scache_line_size() cpu_data[0].scache.linesz |
| 430 | 430 | #endif |
| 431 | +#ifndef cpu_tcache_line_size | |
| 432 | +#define cpu_tcache_line_size() cpu_data[0].tcache.linesz | |
| 433 | +#endif | |
| 431 | 434 | |
| 432 | 435 | #ifndef cpu_hwrena_impl_bits |
| 433 | 436 | #define cpu_hwrena_impl_bits 0 |
| @@ -13,6 +13,8 @@ · 12 unmodified lines | ||
| 13 | 13 | #ifndef _RALINK_REGS_H_ |
| 14 | 14 | #define _RALINK_REGS_H_ |
| 15 | 15 | |
| 16 | +#include <linux/io.h> | |
| 17 | + | |
| 16 | 18 | enum ralink_soc_type { |
| 17 | 19 | RALINK_UNKNOWN = 0, |
| 18 | 20 | RT2880_SOC, |
| @@ -33,6 +33,10 @@ · 32 unmodified lines | ||
| 33 | 33 | #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) |
| 34 | 34 | #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) |
| 35 | 35 | #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) |
| 36 | +#define CVMX_L2C_ERR_TDTX(block_id) \ | |
| 37 | + (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) | |
| 38 | +#define CVMX_L2C_ERR_TTGX(block_id) \ | |
| 39 | + (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) | |
| 36 | 40 | #define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) |
| 37 | 41 | #define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) |
| 38 | 42 | #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) |
| @@ -66,9 +70,40 @@ · 27 unmodified lines | ||
| 66 | 70 | ((offset) & 1) * 8) |
| 67 | 71 | #define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \ |
| 68 | 72 | ((offset) & 31) * 8) |
| 69 | −#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) | |
| 70 | 73 | |
| 71 | 74 | |
| 75 | +union cvmx_l2c_err_tdtx { | |
| 76 | + uint64_t u64; | |
| 77 | + struct cvmx_l2c_err_tdtx_s { | |
| 78 | + __BITFIELD_FIELD(uint64_t dbe:1, | |
| 79 | + __BITFIELD_FIELD(uint64_t sbe:1, | |
| 80 | + __BITFIELD_FIELD(uint64_t vdbe:1, | |
| 81 | + __BITFIELD_FIELD(uint64_t vsbe:1, | |
| 82 | + __BITFIELD_FIELD(uint64_t syn:10, | |
| 83 | + __BITFIELD_FIELD(uint64_t reserved_22_49:28, | |
| 84 | + __BITFIELD_FIELD(uint64_t wayidx:18, | |
| 85 | + __BITFIELD_FIELD(uint64_t reserved_2_3:2, | |
| 86 | + __BITFIELD_FIELD(uint64_t type:2, | |
| 87 | + ;))))))))) | |
| 88 | + } s; | |
| 89 | +}; | |
| 90 | + | |
| 91 | +union cvmx_l2c_err_ttgx { | |
| 92 | + uint64_t u64; | |
| 93 | + struct cvmx_l2c_err_ttgx_s { | |
| 94 | + __BITFIELD_FIELD(uint64_t dbe:1, | |
| 95 | + __BITFIELD_FIELD(uint64_t sbe:1, | |
| 96 | + __BITFIELD_FIELD(uint64_t noway:1, | |
| 97 | + __BITFIELD_FIELD(uint64_t reserved_56_60:5, | |
| 98 | + __BITFIELD_FIELD(uint64_t syn:6, | |
| 99 | + __BITFIELD_FIELD(uint64_t reserved_22_49:28, | |
| 100 | + __BITFIELD_FIELD(uint64_t wayidx:15, | |
| 101 | + __BITFIELD_FIELD(uint64_t reserved_2_6:5, | |
| 102 | + __BITFIELD_FIELD(uint64_t type:2, | |
| 103 | + ;))))))))) | |
| 104 | + } s; | |
| 105 | +}; | |
| 106 | + | |
| 72 | 107 | union cvmx_l2c_cfg { |
| 73 | 108 | uint64_t u64; |
| 74 | 109 | struct cvmx_l2c_cfg_s { |
| @@ -0,0 +1,60 @@ | ||
| 1 | +/***********************license start*************** | |
| 2 | + * Author: Cavium Networks | |
| 3 | + * | |
| 4 | + * Contact: support@caviumnetworks.com | |
| 5 | + * This file is part of the OCTEON SDK | |
| 6 | + * | |
| 7 | + * Copyright (c) 2003-2017 Cavium, Inc. | |
| 8 | + * | |
| 9 | + * This file is free software; you can redistribute it and/or modify | |
| 10 | + * it under the terms of the GNU General Public License, Version 2, as | |
| 11 | + * published by the Free Software Foundation. | |
| 12 | + * | |
| 13 | + * This file is distributed in the hope that it will be useful, but | |
| 14 | + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
| 15 | + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
| 16 | + * NONINFRINGEMENT. See the GNU General Public License for more | |
| 17 | + * details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public License | |
| 20 | + * along with this file; if not, write to the Free Software | |
| 21 | + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 22 | + * or visit http://www.gnu.org/licenses/. | |
| 23 | + * | |
| 24 | + * This file may also be available under a different license from Cavium. | |
| 25 | + * Contact Cavium Networks for more information | |
| 26 | + ***********************license end**************************************/ | |
| 27 | + | |
| 28 | +#ifndef __CVMX_L2D_DEFS_H__ | |
| 29 | +#define __CVMX_L2D_DEFS_H__ | |
| 30 | + | |
| 31 | +#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) | |
| 32 | +#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) | |
| 33 | + | |
| 34 | + | |
| 35 | +union cvmx_l2d_err { | |
| 36 | + uint64_t u64; | |
| 37 | + struct cvmx_l2d_err_s { | |
| 38 | + __BITFIELD_FIELD(uint64_t reserved_6_63:58, | |
| 39 | + __BITFIELD_FIELD(uint64_t bmhclsel:1, | |
| 40 | + __BITFIELD_FIELD(uint64_t ded_err:1, | |
| 41 | + __BITFIELD_FIELD(uint64_t sec_err:1, | |
| 42 | + __BITFIELD_FIELD(uint64_t ded_intena:1, | |
| 43 | + __BITFIELD_FIELD(uint64_t sec_intena:1, | |
| 44 | + __BITFIELD_FIELD(uint64_t ecc_ena:1, | |
| 45 | + ;))))))) | |
| 46 | + } s; | |
| 47 | +}; | |
| 48 | + | |
| 49 | +union cvmx_l2d_fus3 { | |
| 50 | + uint64_t u64; | |
| 51 | + struct cvmx_l2d_fus3_s { | |
| 52 | + __BITFIELD_FIELD(uint64_t reserved_40_63:24, | |
| 53 | + __BITFIELD_FIELD(uint64_t ema_ctl:3, | |
| 54 | + __BITFIELD_FIELD(uint64_t reserved_34_36:3, | |
| 55 | + __BITFIELD_FIELD(uint64_t q3fus:34, | |
| 56 | + ;)))) | |
| 57 | + } s; | |
| 58 | +}; | |
| 59 | + | |
| 60 | +#endif | |
| @@ -62,6 +62,7 @@ enum cvmx_mips_space { · 61 unmodified lines | ||
| 62 | 62 | #include <asm/octeon/cvmx-iob-defs.h> |
| 63 | 63 | #include <asm/octeon/cvmx-ipd-defs.h> |
| 64 | 64 | #include <asm/octeon/cvmx-l2c-defs.h> |
| 65 | +#include <asm/octeon/cvmx-l2d-defs.h> | |
| 65 | 66 | #include <asm/octeon/cvmx-l2t-defs.h> |
| 66 | 67 | #include <asm/octeon/cvmx-led-defs.h> |
| 67 | 68 | #include <asm/octeon/cvmx-mio-defs.h> |
| @@ -376,9 +376,6 @@ asmlinkage void start_secondary(void) · 375 unmodified lines | ||
| 376 | 376 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
| 377 | 377 | notify_cpu_starting(cpu); |
| 378 | 378 | |
| 379 | − complete(&cpu_running); | |
| 380 | − synchronise_count_slave(cpu); | |
| 381 | − | |
| 382 | 379 | set_cpu_online(cpu, true); |
| 383 | 380 | |
| 384 | 381 | set_cpu_sibling_map(cpu); |
| @@ -386,6 +383,9 @@ asmlinkage void start_secondary(void) · 1 unmodified line | ||
| 386 | 383 | |
| 387 | 384 | calculate_cpu_foreign_map(); |
| 388 | 385 | |
| 386 | + complete(&cpu_running); | |
| 387 | + synchronise_count_slave(cpu); | |
| 388 | + | |
| 389 | 389 | /* |
| 390 | 390 | * irq will be enabled in ->smp_finish(), enabling it too early |
| 391 | 391 | * is dangerous. |
| @@ -48,7 +48,7 @@ · 47 unmodified lines | ||
| 48 | 48 | |
| 49 | 49 | #include "uasm.c" |
| 50 | 50 | |
| 51 | −static const struct insn const insn_table[insn_invalid] = { | |
| 51 | +static const struct insn insn_table[insn_invalid] = { | |
| 52 | 52 | [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
| 53 | 53 | [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, |
| 54 | 54 | [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, |
| @@ -0,0 +1,1950 @@ | ||
| 1 | +/* | |
| 2 | + * Just-In-Time compiler for eBPF filters on MIPS | |
| 3 | + * | |
| 4 | + * Copyright (c) 2017 Cavium, Inc. | |
| 5 | + * | |
| 6 | + * Based on code from: | |
| 7 | + * | |
| 8 | + * Copyright (c) 2014 Imagination Technologies Ltd. | |
| 9 | + * Author: Markos Chandras <markos.chandras@imgtec.com> | |
| 10 | + * | |
| 11 | + * This program is free software; you can redistribute it and/or modify it | |
| 12 | + * under the terms of the GNU General Public License as published by the | |
| 13 | + * Free Software Foundation; version 2 of the License. | |
| 14 | + */ | |
| 15 | + | |
| 16 | +#include <linux/bitops.h> | |
| 17 | +#include <linux/errno.h> | |
| 18 | +#include <linux/filter.h> | |
| 19 | +#include <linux/bpf.h> | |
| 20 | +#include <linux/slab.h> | |
| 21 | +#include <asm/bitops.h> | |
| 22 | +#include <asm/byteorder.h> | |
| 23 | +#include <asm/cacheflush.h> | |
| 24 | +#include <asm/cpu-features.h> | |
| 25 | +#include <asm/uasm.h> | |
| 26 | + | |
| 27 | +/* Registers used by JIT */ | |
| 28 | +#define MIPS_R_ZERO 0 | |
| 29 | +#define MIPS_R_AT 1 | |
| 30 | +#define MIPS_R_V0 2 /* BPF_R0 */ | |
| 31 | +#define MIPS_R_V1 3 | |
| 32 | +#define MIPS_R_A0 4 /* BPF_R1 */ | |
| 33 | +#define MIPS_R_A1 5 /* BPF_R2 */ | |
| 34 | +#define MIPS_R_A2 6 /* BPF_R3 */ | |
| 35 | +#define MIPS_R_A3 7 /* BPF_R4 */ | |
| 36 | +#define MIPS_R_A4 8 /* BPF_R5 */ | |
| 37 | +#define MIPS_R_T4 12 /* BPF_AX */ | |
| 38 | +#define MIPS_R_T5 13 | |
| 39 | +#define MIPS_R_T6 14 | |
| 40 | +#define MIPS_R_T7 15 | |
| 41 | +#define MIPS_R_S0 16 /* BPF_R6 */ | |
| 42 | +#define MIPS_R_S1 17 /* BPF_R7 */ | |
| 43 | +#define MIPS_R_S2 18 /* BPF_R8 */ | |
| 44 | +#define MIPS_R_S3 19 /* BPF_R9 */ | |
| 45 | +#define MIPS_R_S4 20 /* BPF_TCC */ | |
| 46 | +#define MIPS_R_S5 21 | |
| 47 | +#define MIPS_R_S6 22 | |
| 48 | +#define MIPS_R_S7 23 | |
| 49 | +#define MIPS_R_T8 24 | |
| 50 | +#define MIPS_R_T9 25 | |
| 51 | +#define MIPS_R_SP 29 | |
| 52 | +#define MIPS_R_RA 31 | |
| 53 | + | |
| 54 | +/* eBPF flags */ | |
| 55 | +#define EBPF_SAVE_S0 BIT(0) | |
| 56 | +#define EBPF_SAVE_S1 BIT(1) | |
| 57 | +#define EBPF_SAVE_S2 BIT(2) | |
| 58 | +#define EBPF_SAVE_S3 BIT(3) | |
| 59 | +#define EBPF_SAVE_S4 BIT(4) | |
| 60 | +#define EBPF_SAVE_RA BIT(5) | |
| 61 | +#define EBPF_SEEN_FP BIT(6) | |
| 62 | +#define EBPF_SEEN_TC BIT(7) | |
| 63 | +#define EBPF_TCC_IN_V1 BIT(8) | |
| 64 | + | |
| 65 | +/* | |
| 66 | + * For the mips64 ISA, we need to track the value range or type for | |
| 67 | + * each JIT register. The BPF machine requires zero extended 32-bit | |
| 68 | + * values, but the mips64 ISA requires sign extended 32-bit values. | |
| 69 | + * At each point in the BPF program we track the state of every | |
| 70 | + * register so that we can zero extend or sign extend as the BPF | |
| 71 | + * semantics require. | |
| 72 | + */ | |
| 73 | +enum reg_val_type { | |
| 74 | + /* uninitialized */ | |
| 75 | + REG_UNKNOWN, | |
| 76 | + /* not known to be 32-bit compatible. */ | |
| 77 | + REG_64BIT, | |
| 78 | + /* 32-bit compatible, no truncation needed for 64-bit ops. */ | |
| 79 | + REG_64BIT_32BIT, | |
| 80 | + /* 32-bit compatible, need truncation for 64-bit ops. */ | |
| 81 | + REG_32BIT, | |
| 82 | + /* 32-bit zero extended. */ | |
| 83 | + REG_32BIT_ZERO_EX, | |
| 84 | + /* 32-bit no sign/zero extension needed. */ | |
| 85 | + REG_32BIT_POS | |
| 86 | +}; | |
| 87 | + | |
| 88 | +/* | |
| 89 | + * high bit of offsets indicates if long branch conversion done at | |
| 90 | + * this insn. | |
| 91 | + */ | |
| 92 | +#define OFFSETS_B_CONV BIT(31) | |
| 93 | + | |
| 94 | +/** | |
| 95 | + * struct jit_ctx - JIT context | |
| 96 | + * @skf: The sk_filter | |
| 97 | + * @stack_size: eBPF stack size | |
| 98 | + * @tmp_offset: eBPF $sp offset to 8-byte temporary memory | |
| 99 | + * @idx: Instruction index | |
| 100 | + * @flags: JIT flags | |
| 101 | + * @offsets: Instruction offsets | |
| 102 | + * @target: Memory location for the compiled filter | |
| 103 | + * @reg_val_types Packed enum reg_val_type for each register. | |
| 104 | + */ | |
| 105 | +struct jit_ctx { | |
| 106 | + const struct bpf_prog *skf; | |
| 107 | + int stack_size; | |
| 108 | + int tmp_offset; | |
| 109 | + u32 idx; | |
| 110 | + u32 flags; | |
| 111 | + u32 *offsets; | |
| 112 | + u32 *target; | |
| 113 | + u64 *reg_val_types; | |
| 114 | + unsigned int long_b_conversion:1; | |
| 115 | + unsigned int gen_b_offsets:1; | |
| 116 | +}; | |
| 117 | + | |
| 118 | +static void set_reg_val_type(u64 *rvt, int reg, enum reg_val_type type) | |
| 119 | +{ | |
| 120 | + *rvt &= ~(7ull << (reg * 3)); | |
| 121 | + *rvt |= ((u64)type << (reg * 3)); | |
| 122 | +} | |
| 123 | + | |
| 124 | +static enum reg_val_type get_reg_val_type(const struct jit_ctx *ctx, | |
| 125 | + int index, int reg) | |
| 126 | +{ | |
| 127 | + return (ctx->reg_val_types[index] >> (reg * 3)) & 7; | |
| 128 | +} | |
| 129 | + | |
| 130 | +/* Simply emit the instruction if the JIT memory space has been allocated */ | |
| 131 | +#define emit_instr(ctx, func, ...) \ | |
| 132 | +do { \ | |
| 133 | + if ((ctx)->target != NULL) { \ | |
| 134 | + u32 *p = &(ctx)->target[ctx->idx]; \ | |
| 135 | + uasm_i_##func(&p, ##__VA_ARGS__); \ | |
| 136 | + } \ | |
| 137 | + (ctx)->idx++; \ | |
| 138 | +} while (0) | |
| 139 | + | |
| 140 | +static unsigned int j_target(struct jit_ctx *ctx, int target_idx) | |
| 141 | +{ | |
| 142 | + unsigned long target_va, base_va; | |
| 143 | + unsigned int r; | |
| 144 | + | |
| 145 | + if (!ctx->target) | |
| 146 | + return 0; | |
| 147 | + | |
| 148 | + base_va = (unsigned long)ctx->target; | |
| 149 | + target_va = base_va + (ctx->offsets[target_idx] & ~OFFSETS_B_CONV); | |
| 150 | + | |
| 151 | + if ((base_va & ~0x0ffffffful) != (target_va & ~0x0ffffffful)) | |
| 152 | + return (unsigned int)-1; | |
| 153 | + r = target_va & 0x0ffffffful; | |
| 154 | + return r; | |
| 155 | +} | |
| 156 | + | |
| 157 | +/* Compute the immediate value for PC-relative branches. */ | |
| 158 | +static u32 b_imm(unsigned int tgt, struct jit_ctx *ctx) | |
| 159 | +{ | |
| 160 | + if (!ctx->gen_b_offsets) | |
| 161 | + return 0; | |
| 162 | + | |
| 163 | + /* | |
| 164 | + * We want a pc-relative branch. tgt is the instruction offset | |
| 165 | + * we want to jump to. | |
| 166 | + | |
| 167 | + * Branch on MIPS: | |
| 168 | + * I: target_offset <- sign_extend(offset) | |
| 169 | + * I+1: PC += target_offset (delay slot) | |
| 170 | + * | |
| 171 | + * ctx->idx currently points to the branch instruction | |
| 172 | + * but the offset is added to the delay slot so we need | |
| 173 | + * to subtract 4. | |
| 174 | + */ | |
| 175 | + return (ctx->offsets[tgt] & ~OFFSETS_B_CONV) - | |
| 176 | + (ctx->idx * 4) - 4; | |
| 177 | +} | |
| 178 | + | |
| 179 | +int bpf_jit_enable __read_mostly; | |
| 180 | + | |
| 181 | +enum which_ebpf_reg { | |
| 182 | + src_reg, | |
| 183 | + src_reg_no_fp, | |
| 184 | + dst_reg, | |
| 185 | + dst_reg_fp_ok | |
| 186 | +}; | |
| 187 | + | |
| 188 | +/* | |
| 189 | + * For eBPF, the register mapping naturally falls out of the | |
| 190 | + * requirements of eBPF and the MIPS n64 ABI. We don't maintain a | |
| 191 | + * separate frame pointer, so BPF_REG_10 relative accesses are | |
| 192 | + * adjusted to be $sp relative. | |
| 193 | + */ | |
| 194 | +int ebpf_to_mips_reg(struct jit_ctx *ctx, const struct bpf_insn *insn, | |
| 195 | + enum which_ebpf_reg w) | |
| 196 | +{ | |
| 197 | + int ebpf_reg = (w == src_reg || w == src_reg_no_fp) ? | |
| 198 | + insn->src_reg : insn->dst_reg; | |
| 199 | + | |
| 200 | + switch (ebpf_reg) { | |
| 201 | + case BPF_REG_0: | |
| 202 | + return MIPS_R_V0; | |
| 203 | + case BPF_REG_1: | |
| 204 | + return MIPS_R_A0; | |
| 205 | + case BPF_REG_2: | |
| 206 | + return MIPS_R_A1; | |
| 207 | + case BPF_REG_3: | |
| 208 | + return MIPS_R_A2; | |
| 209 | + case BPF_REG_4: | |
| 210 | + return MIPS_R_A3; | |
| 211 | + case BPF_REG_5: | |
| 212 | + return MIPS_R_A4; | |
| 213 | + case BPF_REG_6: | |
| 214 | + ctx->flags |= EBPF_SAVE_S0; | |
| 215 | + return MIPS_R_S0; | |
| 216 | + case BPF_REG_7: | |
| 217 | + ctx->flags |= EBPF_SAVE_S1; | |
| 218 | + return MIPS_R_S1; | |
| 219 | + case BPF_REG_8: | |
| 220 | + ctx->flags |= EBPF_SAVE_S2; | |
| 221 | + return MIPS_R_S2; | |
| 222 | + case BPF_REG_9: | |
| 223 | + ctx->flags |= EBPF_SAVE_S3; | |
| 224 | + return MIPS_R_S3; | |
| 225 | + case BPF_REG_10: | |
| 226 | + if (w == dst_reg || w == src_reg_no_fp) | |
| 227 | + goto bad_reg; | |
| 228 | + ctx->flags |= EBPF_SEEN_FP; | |
| 229 | + /* | |
| 230 | + * Needs special handling, return something that | |
| 231 | + * cannot be clobbered just in case. | |
| 232 | + */ | |
| 233 | + return MIPS_R_ZERO; | |
| 234 | + case BPF_REG_AX: | |
| 235 | + return MIPS_R_T4; | |
| 236 | + default: | |
| 237 | +bad_reg: | |
| 238 | + WARN(1, "Illegal bpf reg: %d\n", ebpf_reg); | |
| 239 | + return -EINVAL; | |
| 240 | + } | |
| 241 | +} | |
| 242 | +/* | |
| 243 | + * eBPF stack frame will be something like: | |
| 244 | + * | |
| 245 | + * Entry $sp ------> +--------------------------------+ | |
| 246 | + * | $ra (optional) | | |
| 247 | + * +--------------------------------+ | |
| 248 | + * | $s0 (optional) | | |
| 249 | + * +--------------------------------+ | |
| 250 | + * | $s1 (optional) | | |
| 251 | + * +--------------------------------+ | |
| 252 | + * | $s2 (optional) | | |
| 253 | + * +--------------------------------+ | |
| 254 | + * | $s3 (optional) | | |
| 255 | + * +--------------------------------+ | |
| 256 | + * | $s4 (optional) | | |
| 257 | + * +--------------------------------+ | |
| 258 | + * | tmp-storage (if $ra saved) | | |
| 259 | + * $sp + tmp_offset --> +--------------------------------+ <--BPF_REG_10 | |
| 260 | + * | BPF_REG_10 relative storage | | |
| 261 | + * | MAX_BPF_STACK (optional) | | |
| 262 | + * | . | | |
| 263 | + * | . | | |
| 264 | + * | . | | |
| 265 | + * $sp --------> +--------------------------------+ | |
| 266 | + * | |
| 267 | + * If BPF_REG_10 is never referenced, then the MAX_BPF_STACK sized | |
| 268 | + * area is not allocated. | |
| 269 | + */ | |
| 270 | +static int gen_int_prologue(struct jit_ctx *ctx) | |
| 271 | +{ | |
| 272 | + int stack_adjust = 0; | |
| 273 | + int store_offset; | |
| 274 | + int locals_size; | |
| 275 | + | |
| 276 | + if (ctx->flags & EBPF_SAVE_RA) | |
| 277 | + /* | |
| 278 | + * If RA we are doing a function call and may need | |
| 279 | + * extra 8-byte tmp area. | |
| 280 | + */ | |
| 281 | + stack_adjust += 16; | |
| 282 | + if (ctx->flags & EBPF_SAVE_S0) | |
| 283 | + stack_adjust += 8; | |
| 284 | + if (ctx->flags & EBPF_SAVE_S1) | |
| 285 | + stack_adjust += 8; | |
| 286 | + if (ctx->flags & EBPF_SAVE_S2) | |
| 287 | + stack_adjust += 8; | |
| 288 | + if (ctx->flags & EBPF_SAVE_S3) | |
| 289 | + stack_adjust += 8; | |
| 290 | + if (ctx->flags & EBPF_SAVE_S4) | |
| 291 | + stack_adjust += 8; | |
| 292 | + | |
| 293 | + BUILD_BUG_ON(MAX_BPF_STACK & 7); | |
| 294 | + locals_size = (ctx->flags & EBPF_SEEN_FP) ? MAX_BPF_STACK : 0; | |
| 295 | + | |
| 296 | + stack_adjust += locals_size; | |
| 297 | + ctx->tmp_offset = locals_size; | |
| 298 | + | |
| 299 | + ctx->stack_size = stack_adjust; | |
| 300 | + | |
| 301 | + /* | |
| 302 | + * First instruction initializes the tail call count (TCC). | |
| 303 | + * On tail call we skip this instruction, and the TCC is | |
| 304 | + * passed in $v1 from the caller. | |
| 305 | + */ | |
| 306 | + emit_instr(ctx, daddiu, MIPS_R_V1, MIPS_R_ZERO, MAX_TAIL_CALL_CNT); | |
| 307 | + if (stack_adjust) | |
| 308 | + emit_instr(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack_adjust); | |
| 309 | + else | |
| 310 | + return 0; | |
| 311 | + | |
| 312 | + store_offset = stack_adjust - 8; | |
| 313 | + | |
| 314 | + if (ctx->flags & EBPF_SAVE_RA) { | |
| 315 | + emit_instr(ctx, sd, MIPS_R_RA, store_offset, MIPS_R_SP); | |
| 316 | + store_offset -= 8; | |
| 317 | + } | |
| 318 | + if (ctx->flags & EBPF_SAVE_S0) { | |
| 319 | + emit_instr(ctx, sd, MIPS_R_S0, store_offset, MIPS_R_SP); | |
| 320 | + store_offset -= 8; | |
| 321 | + } | |
| 322 | + if (ctx->flags & EBPF_SAVE_S1) { | |
| 323 | + emit_instr(ctx, sd, MIPS_R_S1, store_offset, MIPS_R_SP); | |
| 324 | + store_offset -= 8; | |
| 325 | + } | |
| 326 | + if (ctx->flags & EBPF_SAVE_S2) { | |
| 327 | + emit_instr(ctx, sd, MIPS_R_S2, store_offset, MIPS_R_SP); | |
| 328 | + store_offset -= 8; | |
| 329 | + } | |
| 330 | + if (ctx->flags & EBPF_SAVE_S3) { | |
| 331 | + emit_instr(ctx, sd, MIPS_R_S3, store_offset, MIPS_R_SP); | |
| 332 | + store_offset -= 8; | |
| 333 | + } | |
| 334 | + if (ctx->flags & EBPF_SAVE_S4) { | |
| 335 | + emit_instr(ctx, sd, MIPS_R_S4, store_offset, MIPS_R_SP); | |
| 336 | + store_offset -= 8; | |
| 337 | + } | |
| 338 | + | |
| 339 | + if ((ctx->flags & EBPF_SEEN_TC) && !(ctx->flags & EBPF_TCC_IN_V1)) | |
| 340 | + emit_instr(ctx, daddu, MIPS_R_S4, MIPS_R_V1, MIPS_R_ZERO); | |
| 341 | + | |
| 342 | + return 0; | |
| 343 | +} | |
| 344 | + | |
| 345 | +static int build_int_epilogue(struct jit_ctx *ctx, int dest_reg) | |
| 346 | +{ | |
| 347 | + const struct bpf_prog *prog = ctx->skf; | |
| 348 | + int stack_adjust = ctx->stack_size; | |
| 349 | + int store_offset = stack_adjust - 8; | |
| 350 | + int r0 = MIPS_R_V0; | |
| 351 | + | |
| 352 | + if (dest_reg == MIPS_R_RA && | |
| 353 | + get_reg_val_type(ctx, prog->len, BPF_REG_0) == REG_32BIT_ZERO_EX) | |
| 354 | + /* Don't let zero extended value escape. */ | |
| 355 | + emit_instr(ctx, sll, r0, r0, 0); | |
| 356 | + | |
| 357 | + if (ctx->flags & EBPF_SAVE_RA) { | |
| 358 | + emit_instr(ctx, ld, MIPS_R_RA, store_offset, MIPS_R_SP); | |
| 359 | + store_offset -= 8; | |
| 360 | + } | |
| 361 | + if (ctx->flags & EBPF_SAVE_S0) { | |
| 362 | + emit_instr(ctx, ld, MIPS_R_S0, store_offset, MIPS_R_SP); | |
| 363 | + store_offset -= 8; | |
| 364 | + } | |
| 365 | + if (ctx->flags & EBPF_SAVE_S1) { | |
| 366 | + emit_instr(ctx, ld, MIPS_R_S1, store_offset, MIPS_R_SP); | |
| 367 | + store_offset -= 8; | |
| 368 | + } | |
| 369 | + if (ctx->flags & EBPF_SAVE_S2) { | |
| 370 | + emit_instr(ctx, ld, MIPS_R_S2, store_offset, MIPS_R_SP); | |
| 371 | + store_offset -= 8; | |
| 372 | + } | |
| 373 | + if (ctx->flags & EBPF_SAVE_S3) { | |
| 374 | + emit_instr(ctx, ld, MIPS_R_S3, store_offset, MIPS_R_SP); | |
| 375 | + store_offset -= 8; | |
| 376 | + } | |
| 377 | + if (ctx->flags & EBPF_SAVE_S4) { | |
| 378 | + emit_instr(ctx, ld, MIPS_R_S4, store_offset, MIPS_R_SP); | |
| 379 | + store_offset -= 8; | |
| 380 | + } | |
| 381 | + emit_instr(ctx, jr, dest_reg); | |
| 382 | + | |
| 383 | + if (stack_adjust) | |
| 384 | + emit_instr(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, stack_adjust); | |
| 385 | + else | |
| 386 | + emit_instr(ctx, nop); | |
| 387 | + | |
| 388 | + return 0; | |
| 389 | +} | |
| 390 | + | |
| 391 | +static void gen_imm_to_reg(const struct bpf_insn *insn, int reg, | |
| 392 | + struct jit_ctx *ctx) | |
| 393 | +{ | |
| 394 | + if (insn->imm >= S16_MIN && insn->imm <= S16_MAX) { | |
| 395 | + emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm); | |
| 396 | + } else { | |
| 397 | + int lower = (s16)(insn->imm & 0xffff); | |
| 398 | + int upper = insn->imm - lower; | |
| 399 | + | |
| 400 | + emit_instr(ctx, lui, reg, upper >> 16); | |
| 401 | + emit_instr(ctx, addiu, reg, reg, lower); | |
| 402 | + } | |
| 403 | + | |
| 404 | +} | |
| 405 | + | |
| 406 | +static int gen_imm_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, | |
| 407 | + int idx) | |
| 408 | +{ | |
| 409 | + int upper_bound, lower_bound; | |
| 410 | + int dst = ebpf_to_mips_reg(ctx, insn, dst_reg); | |
| 411 | + | |
| 412 | + if (dst < 0) | |
| 413 | + return dst; | |
| 414 | + | |
| 415 | + switch (BPF_OP(insn->code)) { | |
| 416 | + case BPF_MOV: | |
| 417 | + case BPF_ADD: | |
| 418 | + upper_bound = S16_MAX; | |
| 419 | + lower_bound = S16_MIN; | |
| 420 | + break; | |
| 421 | + case BPF_SUB: | |
| 422 | + upper_bound = -(int)S16_MIN; | |
| 423 | + lower_bound = -(int)S16_MAX; | |
| 424 | + break; | |
| 425 | + case BPF_AND: | |
| 426 | + case BPF_OR: | |
| 427 | + case BPF_XOR: | |
| 428 | + upper_bound = 0xffff; | |
| 429 | + lower_bound = 0; | |
| 430 | + break; | |
| 431 | + case BPF_RSH: | |
| 432 | + case BPF_LSH: | |
| 433 | + case BPF_ARSH: | |
| 434 | + /* Shift amounts are truncated, no need for bounds */ | |
| 435 | + upper_bound = S32_MAX; | |
| 436 | + lower_bound = S32_MIN; | |
| 437 | + break; | |
| 438 | + default: | |
| 439 | + return -EINVAL; | |
| 440 | + } | |
| 441 | + | |
| 442 | + /* | |
| 443 | + * Immediate move clobbers the register, so no sign/zero | |
| 444 | + * extension needed. | |
| 445 | + */ | |
| 446 | + if (BPF_CLASS(insn->code) == BPF_ALU64 && | |
| 447 | + BPF_OP(insn->code) != BPF_MOV && | |
| 448 | + get_reg_val_type(ctx, idx, insn->dst_reg) == REG_32BIT) | |
| 449 | + emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); | |
| 450 | + /* BPF_ALU | BPF_LSH doesn't need separate sign extension */ | |
| 451 | + if (BPF_CLASS(insn->code) == BPF_ALU && | |
| 452 | + BPF_OP(insn->code) != BPF_LSH && | |
| 453 | + BPF_OP(insn->code) != BPF_MOV && | |
| 454 | + get_reg_val_type(ctx, idx, insn->dst_reg) != REG_32BIT) | |
| 455 | + emit_instr(ctx, sll, dst, dst, 0); | |
| 456 | + | |
| 457 | + if (insn->imm >= lower_bound && insn->imm <= upper_bound) { | |
| 458 | + /* single insn immediate case */ | |
| 459 | + switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { | |
| 460 | + case BPF_ALU64 | BPF_MOV: | |
| 461 | + emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, insn->imm); | |
| 462 | + break; | |
| 463 | + case BPF_ALU64 | BPF_AND: | |
| 464 | + case BPF_ALU | BPF_AND: | |
| 465 | + emit_instr(ctx, andi, dst, dst, insn->imm); | |
| 466 | + break; | |
| 467 | + case BPF_ALU64 | BPF_OR: | |
| 468 | + case BPF_ALU | BPF_OR: | |
| 469 | + emit_instr(ctx, ori, dst, dst, insn->imm); | |
| 470 | + break; | |
| 471 | + case BPF_ALU64 | BPF_XOR: | |
| 472 | + case BPF_ALU | BPF_XOR: | |
| 473 | + emit_instr(ctx, xori, dst, dst, insn->imm); | |
| 474 | + break; | |
| 475 | + case BPF_ALU64 | BPF_ADD: | |
| 476 | + emit_instr(ctx, daddiu, dst, dst, insn->imm); | |
| 477 | + break; | |
| 478 | + case BPF_ALU64 | BPF_SUB: | |
| 479 | + emit_instr(ctx, daddiu, dst, dst, -insn->imm); | |
| 480 | + break; | |
| 481 | + case BPF_ALU64 | BPF_RSH: | |
| 482 | + emit_instr(ctx, dsrl_safe, dst, dst, insn->imm & 0x3f); | |
| 483 | + break; | |
| 484 | + case BPF_ALU | BPF_RSH: | |
| 485 | + emit_instr(ctx, srl, dst, dst, insn->imm & 0x1f); | |
| 486 | + break; | |
| 487 | + case BPF_ALU64 | BPF_LSH: | |
| 488 | + emit_instr(ctx, dsll_safe, dst, dst, insn->imm & 0x3f); | |
| 489 | + break; | |
| 490 | + case BPF_ALU | BPF_LSH: | |
| 491 | + emit_instr(ctx, sll, dst, dst, insn->imm & 0x1f); | |
| 492 | + break; | |
| 493 | + case BPF_ALU64 | BPF_ARSH: | |
| 494 | + emit_instr(ctx, dsra_safe, dst, dst, insn->imm & 0x3f); | |
| 495 | + break; | |
| 496 | + case BPF_ALU | BPF_ARSH: | |
| 497 | + emit_instr(ctx, sra, dst, dst, insn->imm & 0x1f); | |
| 498 | + break; | |
| 499 | + case BPF_ALU | BPF_MOV: | |
| 500 | + emit_instr(ctx, addiu, dst, MIPS_R_ZERO, insn->imm); | |
| 501 | + break; | |
| 502 | + case BPF_ALU | BPF_ADD: | |
| 503 | + emit_instr(ctx, addiu, dst, dst, insn->imm); | |
| 504 | + break; | |
| 505 | + case BPF_ALU | BPF_SUB: | |
| 506 | + emit_instr(ctx, addiu, dst, dst, -insn->imm); | |
| 507 | + break; | |
| 508 | + default: | |
| 509 | + return -EINVAL; | |
| 510 | + } | |
| 511 | + } else { | |
| 512 | + /* multi insn immediate case */ | |
| 513 | + if (BPF_OP(insn->code) == BPF_MOV) { | |
| 514 | + gen_imm_to_reg(insn, dst, ctx); | |
| 515 | + } else { | |
| 516 | + gen_imm_to_reg(insn, MIPS_R_AT, ctx); | |
| 517 | + switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { | |
| 518 | + case BPF_ALU64 | BPF_AND: | |
| 519 | + case BPF_ALU | BPF_AND: | |
| 520 | + emit_instr(ctx, and, dst, dst, MIPS_R_AT); | |
| 521 | + break; | |
| 522 | + case BPF_ALU64 | BPF_OR: | |
| 523 | + case BPF_ALU | BPF_OR: | |
| 524 | + emit_instr(ctx, or, dst, dst, MIPS_R_AT); | |
| 525 | + break; | |
| 526 | + case BPF_ALU64 | BPF_XOR: | |
| 527 | + case BPF_ALU | BPF_XOR: | |
| 528 | + emit_instr(ctx, xor, dst, dst, MIPS_R_AT); | |
| 529 | + break; | |
| 530 | + case BPF_ALU64 | BPF_ADD: | |
| 531 | + emit_instr(ctx, daddu, dst, dst, MIPS_R_AT); | |
| 532 | + break; | |
| 533 | + case BPF_ALU64 | BPF_SUB: | |
| 534 | + emit_instr(ctx, dsubu, dst, dst, MIPS_R_AT); | |
| 535 | + break; | |
| 536 | + case BPF_ALU | BPF_ADD: | |
| 537 | + emit_instr(ctx, addu, dst, dst, MIPS_R_AT); | |
| 538 | + break; | |
| 539 | + case BPF_ALU | BPF_SUB: | |
| 540 | + emit_instr(ctx, subu, dst, dst, MIPS_R_AT); | |
| 541 | + break; | |
| 542 | + default: | |
| 543 | + return -EINVAL; | |
| 544 | + } | |
| 545 | + } | |
| 546 | + } | |
| 547 | + | |
| 548 | + return 0; | |
| 549 | +} | |
| 550 | + | |
| 551 | +static void * __must_check | |
| 552 | +ool_skb_header_pointer(const struct sk_buff *skb, int offset, | |
| 553 | + int len, void *buffer) | |
| 554 | +{ | |
| 555 | + return skb_header_pointer(skb, offset, len, buffer); | |
| 556 | +} | |
| 557 | + | |
| 558 | +static int size_to_len(const struct bpf_insn *insn) | |
| 559 | +{ | |
| 560 | + switch (BPF_SIZE(insn->code)) { | |
| 561 | + case BPF_B: | |
| 562 | + return 1; | |
| 563 | + case BPF_H: | |
| 564 | + return 2; | |
| 565 | + case BPF_W: | |
| 566 | + return 4; | |
| 567 | + case BPF_DW: | |
| 568 | + return 8; | |
| 569 | + } | |
| 570 | + return 0; | |
| 571 | +} | |
| 572 | + | |
| 573 | +static void emit_const_to_reg(struct jit_ctx *ctx, int dst, u64 value) | |
| 574 | +{ | |
| 575 | + if (value >= 0xffffffffffff8000ull || value < 0x8000ull) { | |
| 576 | + emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, (int)value); | |
| 577 | + } else if (value >= 0xffffffff80000000ull || | |
| 578 | + (value < 0x80000000 && value > 0xffff)) { | |
| 579 | + emit_instr(ctx, lui, dst, (s32)(s16)(value >> 16)); | |
| 580 | + emit_instr(ctx, ori, dst, dst, (unsigned int)(value & 0xffff)); | |
| 581 | + } else { | |
| 582 | + int i; | |
| 583 | + bool seen_part = false; | |
| 584 | + int needed_shift = 0; | |
| 585 | + | |
| 586 | + for (i = 0; i < 4; i++) { | |
| 587 | + u64 part = (value >> (16 * (3 - i))) & 0xffff; | |
| 588 | + | |
| 589 | + if (seen_part && needed_shift > 0 && (part || i == 3)) { | |
| 590 | + emit_instr(ctx, dsll_safe, dst, dst, needed_shift); | |
| 591 | + needed_shift = 0; | |
| 592 | + } | |
| 593 | + if (part) { | |
| 594 | + if (i == 0 || (!seen_part && i < 3 && part < 0x8000)) { | |
| 595 | + emit_instr(ctx, lui, dst, (s32)(s16)part); | |
| 596 | + needed_shift = -16; | |
| 597 | + } else { | |
| 598 | + emit_instr(ctx, ori, dst, | |
| 599 | + seen_part ? dst : MIPS_R_ZERO, | |
| 600 | + (unsigned int)part); | |
| 601 | + } | |
| 602 | + seen_part = true; | |
| 603 | + } | |
| 604 | + if (seen_part) | |
| 605 | + needed_shift += 16; | |
| 606 | + } | |
| 607 | + } | |
| 608 | +} | |
| 609 | + | |
| 610 | +static int emit_bpf_tail_call(struct jit_ctx *ctx, int this_idx) | |
| 611 | +{ | |
| 612 | + int off, b_off; | |
| 613 | + | |
| 614 | + ctx->flags |= EBPF_SEEN_TC; | |
| 615 | + /* | |
| 616 | + * if (index >= array->map.max_entries) | |
| 617 | + * goto out; | |
| 618 | + */ | |
| 619 | + off = offsetof(struct bpf_array, map.max_entries); | |
| 620 | + emit_instr(ctx, lwu, MIPS_R_T5, off, MIPS_R_A1); | |
| 621 | + emit_instr(ctx, sltu, MIPS_R_AT, MIPS_R_T5, MIPS_R_A2); | |
| 622 | + b_off = b_imm(this_idx + 1, ctx); | |
| 623 | + emit_instr(ctx, bne, MIPS_R_AT, MIPS_R_ZERO, b_off); | |
| 624 | + /* | |
| 625 | + * if (--TCC < 0) | |
| 626 | + * goto out; | |
| 627 | + */ | |
| 628 | + /* Delay slot */ | |
| 629 | + emit_instr(ctx, daddiu, MIPS_R_T5, | |
| 630 | + (ctx->flags & EBPF_TCC_IN_V1) ? MIPS_R_V1 : MIPS_R_S4, -1); | |
| 631 | + b_off = b_imm(this_idx + 1, ctx); | |
| 632 | + emit_instr(ctx, bltz, MIPS_R_T5, b_off); | |
| 633 | + /* | |
| 634 | + * prog = array->ptrs[index]; | |
| 635 | + * if (prog == NULL) | |
| 636 | + * goto out; | |
| 637 | + */ | |
| 638 | + /* Delay slot */ | |
| 639 | + emit_instr(ctx, dsll, MIPS_R_T8, MIPS_R_A2, 3); | |
| 640 | + emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, MIPS_R_A1); | |
| 641 | + off = offsetof(struct bpf_array, ptrs); | |
| 642 | + emit_instr(ctx, ld, MIPS_R_AT, off, MIPS_R_T8); | |
| 643 | + b_off = b_imm(this_idx + 1, ctx); | |
| 644 | + emit_instr(ctx, beq, MIPS_R_AT, MIPS_R_ZERO, b_off); | |
| 645 | + /* Delay slot */ | |
| 646 | + emit_instr(ctx, nop); | |
| 647 | + | |
| 648 | + /* goto *(prog->bpf_func + 4); */ | |
| 649 | + off = offsetof(struct bpf_prog, bpf_func); | |
| 650 | + emit_instr(ctx, ld, MIPS_R_T9, off, MIPS_R_AT); | |
| 651 | + /* All systems are go... propagate TCC */ | |
| 652 | + emit_instr(ctx, daddu, MIPS_R_V1, MIPS_R_T5, MIPS_R_ZERO); | |
| 653 | + /* Skip first instruction (TCC initialization) */ | |
| 654 | + emit_instr(ctx, daddiu, MIPS_R_T9, MIPS_R_T9, 4); | |
| 655 | + return build_int_epilogue(ctx, MIPS_R_T9); | |
| 656 | +} | |
| 657 | + | |
| 658 | +static bool use_bbit_insns(void) | |
| 659 | +{ | |
| 660 | + switch (current_cpu_type()) { | |
| 661 | + case CPU_CAVIUM_OCTEON: | |
| 662 | + case CPU_CAVIUM_OCTEON_PLUS: | |
| 663 | + case CPU_CAVIUM_OCTEON2: | |
| 664 | + case CPU_CAVIUM_OCTEON3: | |
| 665 | + return true; | |
| 666 | + default: | |
| 667 | + return false; | |
| 668 | + } | |
| 669 | +} | |
| 670 | + | |
| 671 | +static bool is_bad_offset(int b_off) | |
| 672 | +{ | |
| 673 | + return b_off > 0x1ffff || b_off < -0x20000; | |
| 674 | +} | |
| 675 | + | |
| 676 | +/* Returns the number of insn slots consumed. */ | |
| 677 | +static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, | |
| 678 | + int this_idx, int exit_idx) | |
| 679 | +{ | |
| 680 | + int src, dst, r, td, ts, mem_off, b_off; | |
| 681 | + bool need_swap, did_move, cmp_eq; | |
| 682 | + unsigned int target; | |
| 683 | + u64 t64; | |
| 684 | + s64 t64s; | |
| 685 | + | |
| 686 | + switch (insn->code) { | |
| 687 | + case BPF_ALU64 | BPF_ADD | BPF_K: /* ALU64_IMM */ | |
| 688 | + case BPF_ALU64 | BPF_SUB | BPF_K: /* ALU64_IMM */ | |
| 689 | + case BPF_ALU64 | BPF_OR | BPF_K: /* ALU64_IMM */ | |
| 690 | + case BPF_ALU64 | BPF_AND | BPF_K: /* ALU64_IMM */ | |
| 691 | + case BPF_ALU64 | BPF_LSH | BPF_K: /* ALU64_IMM */ | |
| 692 | + case BPF_ALU64 | BPF_RSH | BPF_K: /* ALU64_IMM */ | |
| 693 | + case BPF_ALU64 | BPF_XOR | BPF_K: /* ALU64_IMM */ | |
| 694 | + case BPF_ALU64 | BPF_ARSH | BPF_K: /* ALU64_IMM */ | |
| 695 | + case BPF_ALU64 | BPF_MOV | BPF_K: /* ALU64_IMM */ | |
| 696 | + case BPF_ALU | BPF_MOV | BPF_K: /* ALU32_IMM */ | |
| 697 | + case BPF_ALU | BPF_ADD | BPF_K: /* ALU32_IMM */ | |
| 698 | + case BPF_ALU | BPF_SUB | BPF_K: /* ALU32_IMM */ | |
| 699 | + case BPF_ALU | BPF_OR | BPF_K: /* ALU64_IMM */ | |
| 700 | + case BPF_ALU | BPF_AND | BPF_K: /* ALU64_IMM */ | |
| 701 | + case BPF_ALU | BPF_LSH | BPF_K: /* ALU64_IMM */ | |
| 702 | + case BPF_ALU | BPF_RSH | BPF_K: /* ALU64_IMM */ | |
| 703 | + case BPF_ALU | BPF_XOR | BPF_K: /* ALU64_IMM */ | |
| 704 | + case BPF_ALU | BPF_ARSH | BPF_K: /* ALU64_IMM */ | |
| 705 | + r = gen_imm_insn(insn, ctx, this_idx); | |
| 706 | + if (r < 0) | |
| 707 | + return r; | |
| 708 | + break; | |
| 709 | + case BPF_ALU64 | BPF_MUL | BPF_K: /* ALU64_IMM */ | |
| 710 | + dst = ebpf_to_mips_reg(ctx, insn, dst_reg); | |
| 711 | + if (dst < 0) | |
| 712 | + return dst; | |
| 713 | + if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) | |
| 714 | + emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); | |
| 715 | + if (insn->imm == 1) /* Mult by 1 is a nop */ | |
| 716 | + break; | |
| 717 | + gen_imm_to_reg(insn, MIPS_R_AT, ctx); | |
| 718 | + emit_instr(ctx, dmultu, MIPS_R_AT, dst); | |
| 719 | + emit_instr(ctx, mflo, dst); | |
| 720 | + break; | |
| 721 | + case BPF_ALU64 | BPF_NEG | BPF_K: /* ALU64_IMM */ | |
| 722 | + dst = ebpf_to_mips_reg(ctx, insn, dst_reg); | |
| 723 | + if (dst < 0) | |
| 724 | + return dst; | |
| 725 | + if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) | |
| 726 | + emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); | |
| 727 | + emit_instr(ctx, dsubu, dst, MIPS_R_ZERO, dst); | |
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