PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register: Immediate Readiness – This optional bit, when Set, indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration Requests to this Function. When this bit is Set, for accesses to this Function, software is exempt from all requirements to delay configuration accesses following any type of reset, including but not limited to the timing requirements defined in Section 6.6. This means that all delays after a Conventional or Function Reset can be skipped. This patch reads such bit and caches its value in a flag inside struct pci_dev to be checked later if we should delay or can skip delays after a reset. While at that, also move the explicit msleep(100) call from pcie_flr() and pci_af_flr() to pci_dev_wait().
Unified · Split
| @@ -999,7 +999,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) · 998 unmodified lines | ||
| 999 | 999 | * because have already delayed for the bridge. |
| 1000 | 1000 | */ |
| 1001 | 1001 | if (dev->runtime_d3cold) { |
| 1002 | − if (dev->d3cold_delay) | |
| 1002 | + if (dev->d3cold_delay && !dev->imm_ready) | |
| 1003 | 1003 | msleep(dev->d3cold_delay); |
| 1004 | 1004 | /* |
| 1005 | 1005 | * When powering on a bridge from D3cold, the |
| @@ -2644,6 +2644,7 @@ EXPORT_SYMBOL_GPL(pci_d3cold_disable); · 1638 unmodified lines | ||
| 2644 | 2644 | void pci_pm_init(struct pci_dev *dev) |
| 2645 | 2645 | { |
| 2646 | 2646 | int pm; |
| 2647 | + u16 status; | |
| 2647 | 2648 | u16 pmc; |
| 2648 | 2649 | |
| 2649 | 2650 | pm_runtime_forbid(&dev->dev); |
| @@ -2706,6 +2707,10 @@ void pci_pm_init(struct pci_dev *dev) · 56 unmodified lines | ||
| 2706 | 2707 | /* Disable the PME# generation functionality */ |
| 2707 | 2708 | pci_pme_active(dev, false); |
| 2708 | 2709 | } |
| 2710 | + | |
| 2711 | + pci_read_config_word(dev, PCI_STATUS, &status); | |
| 2712 | + if (status & PCI_STATUS_IMM_READY) | |
| 2713 | + dev->imm_ready = 1; | |
| 2709 | 2714 | } |
| 2710 | 2715 | |
| 2711 | 2716 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
| @@ -4376,6 +4381,9 @@ int pcie_flr(struct pci_dev *dev) · 1664 unmodified lines | ||
| 4376 | 4381 | |
| 4377 | 4382 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
| 4378 | 4383 | |
| 4384 | + if (dev->imm_ready) | |
| 4385 | + return 0; | |
| 4386 | + | |
| 4379 | 4387 | /* |
| 4380 | 4388 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within |
| 4381 | 4389 | * 100ms, but may silently discard requests while the FLR is in |
| @@ -4417,6 +4425,9 @@ static int pci_af_flr(struct pci_dev *dev, int probe) · 35 unmodified lines | ||
| 4417 | 4425 | |
| 4418 | 4426 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
| 4419 | 4427 | |
| 4428 | + if (dev->imm_ready) | |
| 4429 | + return 0; | |
| 4430 | + | |
| 4420 | 4431 | /* |
| 4421 | 4432 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, |
| 4422 | 4433 | * updated 27 July 2006; a device must complete an FLR within |
| @@ -325,6 +325,7 @@ struct pci_dev { · 324 unmodified lines | ||
| 325 | 325 | pci_power_t current_state; /* Current operating state. In ACPI, |
| 326 | 326 | this is D0-D3, D0 being fully |
| 327 | 327 | functional, and D3 being off. */ |
| 328 | + unsigned int imm_ready:1; /* Supports Immediate Readiness */ | |
| 328 | 329 | u8 pm_cap; /* PM capability offset */ |
| 329 | 330 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
| 330 | 331 | can be generated */ |
| @@ -52,6 +52,7 @@ · 51 unmodified lines | ||
| 52 | 52 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
| 53 | 53 | |
| 54 | 54 | #define PCI_STATUS 0x06 /* 16 bits */ |
| 55 | +#define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ | |
| 55 | 56 | #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ |
| 56 | 57 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
| 57 | 58 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ |