Merge branch 'lpc32xx/multiplatform' into arm/soc

I revisited some older patches here, getting two of the remaining ARM platforms to build with ARCH_MULTIPLATFORM like most others do. In case of lpc32xx, I created a new set of patches, which seemed easier than digging out what I did for an older release many years ago. * lpc32xx/multiplatform: ARM: lpc32xx: allow multiplatform build ARM: lpc32xx: clean up header files serial: lpc32xx: allow compile testing net: lpc-enet: allow compile testing net: lpc-enet: fix printk format strings net: lpc-enet: fix badzero.cocci warnings net: lpc-enet: move phy setup into platform code net: lpc-enet: factor out iram access gpio: lpc32xx: allow building on non-lpc32xx targets serial: lpc32xx_hs: allow compile-testing watchdog: pnx4008_wdt: allow compile-testing usb: udc: lpc32xx: allow compile-testing usb: ohci-nxp: enable compile-testing

Arnd Bergmann committed 7 years ago

Commit d64a1fd2 parents 3584be9 75bf1bd27 files · +242 −272Browse files

Unified · Split

27 files

arch/arm/Kconfig +2 −15
arch/arm/configs/lpc32xx_defconfig +2 −0
arch/arm/mach-lpc32xx/Kconfig +11 −0
arch/arm/mach-lpc32xx/common.c +20 −4
arch/arm/mach-lpc32xx/common.h +0 −1
arch/arm/mach-lpc32xx/include/mach/board.h +0 −15
arch/arm/mach-lpc32xx/include/mach/entry-macro.S +0 −28
arch/arm/mach-lpc32xx/include/mach/hardware.h +0 −25
arch/arm/mach-lpc32xx/include/mach/uncompress.h +0 −50
arch/arm/mach-lpc32xx/lpc32xx.h +16 −2
arch/arm/mach-lpc32xx/pm.c +1 −2
arch/arm/mach-lpc32xx/serial.c +31 −2
arch/arm/mach-lpc32xx/suspend.S +1 −2
drivers/gpio/Kconfig +7 −0
drivers/gpio/Makefile +1 −1
drivers/gpio/gpio-lpc32xx.c +68 −50
drivers/net/ethernet/nxp/Kconfig +1 −1
drivers/net/ethernet/nxp/lpc_eth.c +18 −27
drivers/tty/serial/Kconfig +2 −1
drivers/tty/serial/lpc32xx_hs.c +4 −33
drivers/usb/gadget/udc/Kconfig +2 −1
drivers/usb/gadget/udc/lpc32xx_udc.c +1 −2
drivers/usb/host/Kconfig +2 −1
drivers/usb/host/ohci-nxp.c +18 −7
drivers/watchdog/Kconfig +1 −1
drivers/watchdog/pnx4008_wdt.c +0 −1
include/linux/soc/nxp/lpc32xx-misc.h +33 −0

arch/arm/Kconfig+2−15

@@ -424,21 +424,6 @@ config ARCH_DOVE · 423 unmodified lines
424	424	help
425	425	Support for the Marvell Dove SoC 88AP510
426	426
427		−config ARCH_LPC32XX
428		− bool "NXP LPC32XX"
429		− select ARM_AMBA
430		− select CLKDEV_LOOKUP
431		− select CLKSRC_LPC32XX
432		− select COMMON_CLK
433		− select CPU_ARM926T
434		− select GENERIC_CLOCKEVENTS
435		− select GENERIC_IRQ_MULTI_HANDLER
436		− select GPIOLIB
437		− select SPARSE_IRQ
438		− select USE_OF
439		− help
440		− Support for the NXP LPC32XX family of processors
441		−
442	427	config ARCH_PXA
443	428	bool "PXA2xx/PXA3xx-based"
444	429	depends on MMU
@@ -686,6 +671,8 @@ source "arch/arm/mach-ixp4xx/Kconfig" · 241 unmodified lines
686	671
687	672	source "arch/arm/mach-keystone/Kconfig"
688	673
	674	+source "arch/arm/mach-lpc32xx/Kconfig"
	675	+
689	676	source "arch/arm/mach-mediatek/Kconfig"
690	677
691	678	source "arch/arm/mach-meson/Kconfig"

arch/arm/configs/lpc32xx_defconfig+2−0

@@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y · 11 unmodified lines
12	12	CONFIG_SYSCTL_SYSCALL=y
13	13	CONFIG_EMBEDDED=y
14	14	CONFIG_SLAB=y
	15	+# CONFIG_ARCH_MULTI_V7 is not set
15	16	CONFIG_ARCH_LPC32XX=y
16	17	CONFIG_AEABI=y
17	18	CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -93,6 +94,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y · 75 unmodified lines
93	94	# CONFIG_HW_RANDOM is not set
94	95	CONFIG_I2C_CHARDEV=y
95	96	CONFIG_I2C_PNX=y
	97	+CONFIG_GPIO_LPC32XX=y
96	98	CONFIG_SPI=y
97	99	CONFIG_SPI_PL022=y
98	100	CONFIG_GPIO_SYSFS=y

arch/arm/mach-lpc32xx/Kconfig+11−0

@@ -0,0 +1,11 @@
	1	+# SPDX-License-Identifier: GPL-2.0-only
	2	+
	3	+config ARCH_LPC32XX
	4	+ bool "NXP LPC32XX"
	5	+ depends on ARCH_MULTI_V5
	6	+ select ARM_AMBA
	7	+ select CLKSRC_LPC32XX
	8	+ select CPU_ARM926T
	9	+ select GPIOLIB
	10	+ help
	11	+ Support for the NXP LPC32XX family of processors

arch/arm/mach-lpc32xx/common.c+20−4

@@ -8,12 +8,12 @@ · 7 unmodified lines
8	8	*/
9	9
10	10	#include <linux/init.h>
	11	+#include <linux/soc/nxp/lpc32xx-misc.h>
11	12
12	13	#include <asm/mach/map.h>
13	14	#include <asm/system_info.h>
14	15
15		−#include <mach/hardware.h>
16		−#include <mach/platform.h>
	16	+#include "lpc32xx.h"
17	17	#include "common.h"
18	18
19	19	/*
@@ -32,7 +32,7 @@ void lpc32xx_get_uid(u32 devid[4]) · 12 unmodified lines
32	32	*/
33	33	#define LPC32XX_IRAM_BANK_SIZE SZ_128K
34	34	static u32 iram_size;
35		−u32 lpc32xx_return_iram_size(void)
	35	+u32 lpc32xx_return_iram(void __iomem *mapbase, dma_addr_t dmaaddr)
36	36	{
37	37	if (iram_size == 0) {
38	38	u32 savedval1, savedval2;
@@ -53,10 +53,26 @@ u32 lpc32xx_return_iram_size(void) · 14 unmodified lines
53	53	} else
54	54	iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
55	55	}
	56	+ if (dmaaddr)
	57	+ *dmaaddr = LPC32XX_IRAM_BASE;
	58	+ if (mapbase)
	59	+ *mapbase = io_p2v(LPC32XX_IRAM_BASE);
56	60
57	61	return iram_size;
58	62	}
59		−EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
	63	+EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
	64	+
	65	+void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
	66	+{
	67	+ u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
	68	+ tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
	69	+ if (mode == PHY_INTERFACE_MODE_MII)
	70	+ tmp \|= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
	71	+ else
	72	+ tmp \|= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
	73	+ __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
	74	+}
	75	+EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
60	76
61	77	static struct map_desc lpc32xx_io_desc[] __initdata = {
62	78	{

arch/arm/mach-lpc32xx/common.h+0−1

@@ -23,7 +23,6 @@ extern void __init lpc32xx_serial_init(void); · 22 unmodified lines
23	23	*/
24	24	extern void lpc32xx_get_uid(u32 devid[4]);
25	25
26		−extern u32 lpc32xx_return_iram_size(void);
27	26	/*
28	27	* Pointers used for sizing and copying suspend function data
29	28	*/

arch/arm/mach-lpc32xx/include/mach/board.h+0−15

@@ -1,15 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-or-later */
2		−/*
3		− * arm/arch/mach-lpc32xx/include/mach/board.h
4		− *
5		− * Author: Kevin Wells <kevin.wells@nxp.com>
6		− *
7		− * Copyright (C) 2010 NXP Semiconductors
8		− */
9		−
10		−#ifndef __ASM_ARCH_BOARD_H
11		−#define __ASM_ARCH_BOARD_H
12		−
13		−extern u32 lpc32xx_return_iram_size(void);
14		−
15		−#endif /* __ASM_ARCH_BOARD_H */

arch/arm/mach-lpc32xx/include/mach/entry-macro.S+0−28

@@ -1,28 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-or-later */
2		−/*
3		− * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
4		− *
5		− * Author: Kevin Wells <kevin.wells@nxp.com>
6		− *
7		− * Copyright (C) 2010 NXP Semiconductors
8		− */
9		−
10		−#include <mach/hardware.h>
11		−#include <mach/platform.h>
12		−
13		−#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
14		−
15		− .macro get_irqnr_preamble, base, tmp
16		− ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
17		− .endm
18		−
19		−/*
20		− * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
21		− * as set if an interrupt is pending.
22		− */
23		− .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24		− ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
25		− clz \irqnr, \irqstat
26		− rsb \irqnr, \irqnr, #31
27		− teq \irqstat, #0
28		− .endm

arch/arm/mach-lpc32xx/include/mach/hardware.h+0−25

@@ -1,25 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-or-later */
2		−/*
3		− * arch/arm/mach-lpc32xx/include/mach/hardware.h
4		− *
5		− * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
6		− */
7		−
8		−#ifndef __ASM_ARCH_HARDWARE_H
9		−#define __ASM_ARCH_HARDWARE_H
10		−
11		−/*
12		− * Start of virtual addresses for IO devices
13		− */
14		−#define IO_BASE 0xF0000000
15		−
16		−/*
17		− * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
18		− */
19		−#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) \| ((x) & 0xfffff)) \|\
20		− IO_BASE)
21		−
22		−#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
23		−#define io_v2p(x) ((((x) & 0x0ff00000) << 4) \| ((x) & 0x000fffff))
24		−
25		−#endif

arch/arm/mach-lpc32xx/include/mach/uncompress.h+0−50

@@ -1,50 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-or-later */
2		−/*
3		− * arch/arm/mach-lpc32xx/include/mach/uncompress.h
4		− *
5		− * Author: Kevin Wells <kevin.wells@nxp.com>
6		− *
7		− * Copyright (C) 2010 NXP Semiconductors
8		− */
9		−
10		−#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
11		−#define __ASM_ARM_ARCH_UNCOMPRESS_H
12		−
13		−#include <linux/io.h>
14		−
15		−#include <mach/hardware.h>
16		−#include <mach/platform.h>
17		−
18		−/*
19		− * Uncompress output is hardcoded to standard UART 5
20		− */
21		−
22		−#define UART_FIFO_CTL_TX_RESET (1 << 2)
23		−#define UART_STATUS_TX_MT (1 << 6)
24		−
25		−#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
26		−
27		−#define LPC32XX_UART_DLLFIFO_O 0x00
28		−#define LPC32XX_UART_IIRFCR_O 0x08
29		−#define LPC32XX_UART_LSR_O 0x14
30		−
31		−static inline void putc(int ch)
32		−{
33		− /* Wait for transmit FIFO to empty */
34		− while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
35		− UART_STATUS_TX_MT) == 0)
36		− ;
37		−
38		− __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
39		−}
40		−
41		−static inline void flush(void)
42		−{
43		− __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) \|
44		− UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
45		−}
46		−
47		−/* NULL functions; we don't presently need them */
48		−#define arch_decomp_setup()
49		−
50		−#endif

arch/arm/mach-lpc32xx/lpc32xx.hrenamed from arch/arm/mach-lpc32xx/include/mach/platform.h+16−2

@@ -7,8 +7,8 @@ · 6 unmodified lines
7	7	* Copyright (C) 2010 NXP Semiconductors
8	8	*/
9	9
10		−#ifndef __ASM_ARCH_PLATFORM_H
11		−#define __ASM_ARCH_PLATFORM_H
	10	+#ifndef __ARM_LPC32XX_H
	11	+#define __ARM_LPC32XX_H
12	12
13	13	#define _SBF(f, v) ((v) << (f))
14	14	#define _BIT(n) _SBF(n, 1)
@@ -700,4 +700,18 @@ · 685 unmodified lines
700	700	#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
701	701	#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
702	702
	703	+/*
	704	+ * Start of virtual addresses for IO devices
	705	+ */
	706	+#define IO_BASE 0xF0000000
	707	+
	708	+/*
	709	+ * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
	710	+ */
	711	+#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) \| ((x) & 0xfffff)) \|\
	712	+ IO_BASE)
	713	+
	714	+#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
	715	+#define io_v2p(x) ((((x) & 0x0ff00000) << 4) \| ((x) & 0x000fffff))
	716	+
703	717	#endif

arch/arm/mach-lpc32xx/pm.c+1−2

@@ -70,8 +70,7 @@ · 69 unmodified lines
70	70
71	71	#include <asm/cacheflush.h>
72	72
73		−#include <mach/hardware.h>
74		−#include <mach/platform.h>
	73	+#include "lpc32xx.h"
75	74	#include "common.h"
76	75
77	76	#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)

arch/arm/mach-lpc32xx/serial.c+31−2

@@ -16,8 +16,7 @@ · 15 unmodified lines
16	16	#include <linux/clk.h>
17	17	#include <linux/io.h>
18	18
19		−#include <mach/hardware.h>
20		−#include <mach/platform.h>
	19	+#include "lpc32xx.h"
21	20	#include "common.h"
22	21
23	22	#define LPC32XX_SUART_FIFO_SIZE 64
@@ -60,6 +59,36 @@ static struct uartinit uartinit_data[] __initdata = { · 36 unmodified lines
60	59	},
61	60	};
62	61
	62	+/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
	63	+void lpc32xx_loopback_set(resource_size_t mapbase, int state)
	64	+{
	65	+ int bit;
	66	+ u32 tmp;
	67	+
	68	+ switch (mapbase) {
	69	+ case LPC32XX_HS_UART1_BASE:
	70	+ bit = 0;
	71	+ break;
	72	+ case LPC32XX_HS_UART2_BASE:
	73	+ bit = 1;
	74	+ break;
	75	+ case LPC32XX_HS_UART7_BASE:
	76	+ bit = 6;
	77	+ break;
	78	+ default:
	79	+ WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
	80	+ return;
	81	+ }
	82	+
	83	+ tmp = readl(LPC32XX_UARTCTL_CLOOP);
	84	+ if (state)
	85	+ tmp \|= (1 << bit);
	86	+ else
	87	+ tmp &= ~(1 << bit);
	88	+ writel(tmp, LPC32XX_UARTCTL_CLOOP);
	89	+}
	90	+EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
	91	+
63	92	void __init lpc32xx_serial_init(void)
64	93	{
65	94	u32 tmp, clkmodes = 0;

arch/arm/mach-lpc32xx/suspend.S+1−2

@@ -11,8 +11,7 @@ · 10 unmodified lines
11	11	*/
12	12	#include <linux/linkage.h>
13	13	#include <asm/assembler.h>
14		−#include <mach/platform.h>
15		−#include <mach/hardware.h>
	14	+#include "lpc32xx.h"
16	15
17	16	/* Using named register defines makes the code easier to follow */
18	17	#define WORK1_REG r0

drivers/gpio/Kconfig+7−0

@@ -311,6 +311,13 @@ config GPIO_LPC18XX · 310 unmodified lines
311	311	Select this option to enable GPIO driver for
312	312	NXP LPC18XX/43XX devices.
313	313
	314	+config GPIO_LPC32XX
	315	+ tristate "NXP LPC32XX GPIO support"
	316	+ depends on OF_GPIO && (ARCH_LPC32XX \|\| COMPILE_TEST)
	317	+ help
	318	+ Select this option to enable GPIO driver for
	319	+ NXP LPC32XX devices.
	320	+
314	321	config GPIO_LYNXPOINT
315	322	tristate "Intel Lynxpoint GPIO support"
316	323	depends on ACPI && X86

drivers/gpio/Makefile+1−1

@@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o · 73 unmodified lines
74	74	obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
75	75	obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
76	76	obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
77		−obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
	77	+obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
78	78	obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
79	79	obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
80	80	obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o

drivers/gpio/gpio-lpc32xx.c+68−50

@@ -16,36 +16,33 @@ · 15 unmodified lines
16	16	#include <linux/platform_device.h>
17	17	#include <linux/module.h>
18	18
19		−#include <mach/hardware.h>
20		−#include <mach/platform.h>
21		−
22		−#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
23		−#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
24		−#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
25		−#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
26		−#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
27		−#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
28		−#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
29		−#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
30		−#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
31		−#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
32		−#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
33		−#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
34		−#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
35		−#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
36		−#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
37		−#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
38		−#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
39		−#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
40		−#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
41		−#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
42		−#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
43		−#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
44		−#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
45		−#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
46		−#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
47		−#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
48		−#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
	19	+#define LPC32XX_GPIO_P3_INP_STATE (0x000)
	20	+#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
	21	+#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
	22	+#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
	23	+#define LPC32XX_GPIO_P2_DIR_SET (0x010)
	24	+#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
	25	+#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
	26	+#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
	27	+#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
	28	+#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
	29	+#define LPC32XX_GPIO_P2_MUX_SET (0x028)
	30	+#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
	31	+#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
	32	+#define LPC32XX_GPIO_P0_INP_STATE (0x040)
	33	+#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
	34	+#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
	35	+#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
	36	+#define LPC32XX_GPIO_P0_DIR_SET (0x050)
	37	+#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
	38	+#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
	39	+#define LPC32XX_GPIO_P1_INP_STATE (0x060)
	40	+#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
	41	+#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
	42	+#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
	43	+#define LPC32XX_GPIO_P1_DIR_SET (0x070)
	44	+#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
	45	+#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
49	46
50	47	#define GPIO012_PIN_TO_BIT(x) (1 << (x))
51	48	#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
@@ -72,12 +69,12 @@ · 20 unmodified lines
72	69	#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
73	70
74	71	struct gpio_regs {
75		− void __iomem *inp_state;
76		− void __iomem *outp_state;
77		− void __iomem *outp_set;
78		− void __iomem *outp_clr;
79		− void __iomem *dir_set;
80		− void __iomem *dir_clr;
	72	+ unsigned long inp_state;
	73	+ unsigned long outp_state;
	74	+ unsigned long outp_set;
	75	+ unsigned long outp_clr;
	76	+ unsigned long dir_set;
	77	+ unsigned long dir_clr;
81	78	};
82	79
83	80	/*
@@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = { · 81 unmodified lines
165	162	struct lpc32xx_gpio_chip {
166	163	struct gpio_chip chip;
167	164	struct gpio_regs *gpio_grp;
	165	+ void __iomem *reg_base;
168	166	};
169	167
	168	+static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
	169	+{
	170	+ return __raw_readl(group->reg_base + offset);
	171	+}
	172	+
	173	+static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
	174	+{
	175	+ __raw_writel(val, group->reg_base + offset);
	176	+}
	177	+
170	178	static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
171	179	unsigned pin, int input)
172	180	{
173	181	if (input)
174		− __raw_writel(GPIO012_PIN_TO_BIT(pin),
	182	+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
175	183	group->gpio_grp->dir_clr);
176	184	else
177		− __raw_writel(GPIO012_PIN_TO_BIT(pin),
	185	+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
178	186	group->gpio_grp->dir_set);
179	187	}
180	188
@@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, · 3 unmodified lines
184	192	u32 u = GPIO3_PIN_TO_BIT(pin);
185	193
186	194	if (input)
187		− __raw_writel(u, group->gpio_grp->dir_clr);
	195	+ gpreg_write(group, u, group->gpio_grp->dir_clr);
188	196	else
189		− __raw_writel(u, group->gpio_grp->dir_set);
	197	+ gpreg_write(group, u, group->gpio_grp->dir_set);
190	198	}
191	199
192	200	static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
193	201	unsigned pin, int high)
194	202	{
195	203	if (high)
196		− __raw_writel(GPIO012_PIN_TO_BIT(pin),
	204	+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
197	205	group->gpio_grp->outp_set);
198	206	else
199		− __raw_writel(GPIO012_PIN_TO_BIT(pin),
	207	+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
200	208	group->gpio_grp->outp_clr);
201	209	}
202	210
@@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, · 3 unmodified lines
206	214	u32 u = GPIO3_PIN_TO_BIT(pin);
207	215
208	216	if (high)
209		− __raw_writel(u, group->gpio_grp->outp_set);
	217	+ gpreg_write(group, u, group->gpio_grp->outp_set);
210	218	else
211		− __raw_writel(u, group->gpio_grp->outp_clr);
	219	+ gpreg_write(group, u, group->gpio_grp->outp_clr);
212	220	}
213	221
214	222	static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
215	223	unsigned pin, int high)
216	224	{
217	225	if (high)
218		− __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
	226	+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
219	227	else
220		− __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
	228	+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
221	229	}
222	230
223	231	static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
224	232	unsigned pin)
225	233	{
226		− return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
	234	+ return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
227	235	pin);
228	236	}
229	237
230	238	static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
231	239	unsigned pin)
232	240	{
233		− int state = __raw_readl(group->gpio_grp->inp_state);
	241	+ int state = gpreg_read(group, group->gpio_grp->inp_state);
234	242
235	243	/*
236	244	* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
@@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, · 5 unmodified lines
242	250	static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
243	251	unsigned pin)
244	252	{
245		− return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
	253	+ return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
246	254	}
247	255
248	256	static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
249	257	unsigned pin)
250	258	{
251		− return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
	259	+ return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
252	260	}
253	261
254	262	/*
@@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc, · 242 unmodified lines
497	505	static int lpc32xx_gpio_probe(struct platform_device *pdev)
498	506	{
499	507	int i;
	508	+ void __iomem *reg_base;
	509	+
	510	+ reg_base = devm_platform_ioremap_resource(pdev, 0);
	511	+ if (IS_ERR(reg_base))
	512	+ return PTR_ERR(reg_base);
500	513
501	514	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
502	515	if (pdev->dev.of_node) {
503	516	lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
504	517	lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
505	518	lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
	519	+ lpc32xx_gpiochip[i].reg_base = reg_base;
506	520	}
507	521	devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
508	522	&lpc32xx_gpiochip[i]);
@@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = { · 18 unmodified lines
527	541	};
528	542
529	543	module_platform_driver(lpc32xx_gpio_driver);
	544	+
	545	+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
	546	+MODULE_LICENSE("GPL");
	547	+MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");

drivers/net/ethernet/nxp/Kconfig+1−1

@@ -1,7 +1,7 @@
1	1	# SPDX-License-Identifier: GPL-2.0-only
2	2	config LPC_ENET
3	3	tristate "NXP ethernet MAC on LPC devices"
4		− depends on ARCH_LPC32XX
	4	+ depends on ARCH_LPC32XX \|\| COMPILE_TEST
5	5	select PHYLIB
6	6	help
7	7	Say Y or M here if you want to use the NXP ethernet MAC included on

drivers/net/ethernet/nxp/lpc_eth.c+18−27

@@ -14,14 +14,12 @@ · 13 unmodified lines
14	14	#include <linux/crc32.h>
15	15	#include <linux/etherdevice.h>
16	16	#include <linux/module.h>
	17	+#include <linux/of.h>
17	18	#include <linux/of_net.h>
18	19	#include <linux/phy.h>
19	20	#include <linux/platform_device.h>
20	21	#include <linux/spinlock.h>
21		−
22		−#include <mach/board.h>
23		−#include <mach/hardware.h>
24		−#include <mach/platform.h>
	22	+#include <linux/soc/nxp/lpc32xx-misc.h>
25	23
26	24	#define MODNAME "lpc-eth"
27	25	#define DRV_VERSION "1.00"
@@ -1237,16 +1235,9 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) · 1209 unmodified lines
1237	1235	dma_addr_t dma_handle;
1238	1236	struct resource *res;
1239	1237	int irq, ret;
1240		− u32 tmp;
1241	1238
1242	1239	/* Setup network interface for RMII or MII mode */
1243		− tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
1244		− tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
1245		− if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII)
1246		− tmp \|= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
1247		− else
1248		− tmp \|= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
1249		− __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
	1240	+ lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev));
1250	1241
1251	1242	/* Get platform resources */
1252	1243	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1311,19 +1302,18 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) · 58 unmodified lines
1311	1302	/* Get size of DMA buffers/descriptors region */
1312	1303	pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
1313	1304	sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
1314		− pldat->dma_buff_base_v = 0;
1315	1305
1316	1306	if (use_iram_for_net(dev)) {
1317		− dma_handle = LPC32XX_IRAM_BASE;
1318		− if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
1319		− pldat->dma_buff_base_v =
1320		− io_p2v(LPC32XX_IRAM_BASE);
1321		− else
	1307	+ if (pldat->dma_buff_size >
	1308	+ lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) {
	1309	+ pldat->dma_buff_base_v = NULL;
	1310	+ pldat->dma_buff_size = 0;
1322	1311	netdev_err(ndev,
1323	1312	"IRAM not big enough for net buffers, using SDRAM instead.\n");
	1313	+ }
1324	1314	}
1325	1315
1326		− if (pldat->dma_buff_base_v == 0) {
	1316	+ if (pldat->dma_buff_base_v == NULL) {
1327	1317	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1328	1318	if (ret)
1329	1319	goto err_out_free_irq;
@@ -1344,13 +1334,14 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) · 14 unmodified lines
1344	1334	pldat->dma_buff_base_p = dma_handle;
1345	1335
1346	1336	netdev_dbg(ndev, "IO address space :%pR\n", res);
1347		− netdev_dbg(ndev, "IO address size :%d\n", resource_size(res));
	1337	+ netdev_dbg(ndev, "IO address size :%zd\n",
	1338	+ (size_t)resource_size(res));
1348	1339	netdev_dbg(ndev, "IO address (mapped) :0x%p\n",
1349	1340	pldat->net_base);
1350	1341	netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);
1351		− netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size);
1352		− netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
1353		− pldat->dma_buff_base_p);
	1342	+ netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size);
	1343	+ netdev_dbg(ndev, "DMA buffer P address :%pad\n",
	1344	+ &pldat->dma_buff_base_p);
1354	1345	netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
1355	1346	pldat->dma_buff_base_v);
1356	1347
@@ -1397,8 +1388,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) · 40 unmodified lines
1397	1388	if (ret)
1398	1389	goto err_out_unregister_netdev;
1399	1390
1400		− netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
1401		− res->start, ndev->irq);
	1391	+ netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n",
	1392	+ (unsigned long)res->start, ndev->irq);
1402	1393
1403	1394	device_init_wakeup(dev, 1);
1404	1395	device_set_wakeup_enable(dev, 0);
@@ -1409,7 +1400,7 @@ err_out_unregister_netdev: · 4 unmodified lines
1409	1400	unregister_netdev(ndev);
1410	1401	err_out_dma_unmap:
1411	1402	if (!use_iram_for_net(dev) \|\|
1412		− pldat->dma_buff_size > lpc32xx_return_iram_size())
	1403	+ pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
1413	1404	dma_free_coherent(dev, pldat->dma_buff_size,
1414	1405	pldat->dma_buff_base_v,
1415	1406	pldat->dma_buff_base_p);
@@ -1436,7 +1427,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) · 20 unmodified lines
1436	1427	unregister_netdev(ndev);
1437	1428
1438	1429	if (!use_iram_for_net(&pldat->pdev->dev) \|\|
1439		− pldat->dma_buff_size > lpc32xx_return_iram_size())
	1430	+ pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
1440	1431	dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1441	1432	pldat->dma_buff_base_v,
1442	1433	pldat->dma_buff_base_p);

drivers/tty/serial/Kconfig+2−1

@@ -739,7 +739,8 @@ config SERIAL_PNX8XXX_CONSOLE · 738 unmodified lines
739	739
740	740	config SERIAL_HS_LPC32XX
741	741	tristate "LPC32XX high speed serial port support"
742		− depends on ARCH_LPC32XX && OF
	742	+ depends on ARCH_LPC32XX \|\| COMPILE_TEST
	743	+ depends on OF
743	744	select SERIAL_CORE
744	745	help
745	746	Support for the LPC32XX high speed serial ports (up to 900kbps).

drivers/tty/serial/lpc32xx_hs.c+4−33

@@ -25,8 +25,8 @@ · 24 unmodified lines
25	25	#include <linux/irq.h>
26	26	#include <linux/gpio.h>
27	27	#include <linux/of.h>
28		−#include <mach/platform.h>
29		−#include <mach/hardware.h>
	28	+#include <linux/sizes.h>
	29	+#include <linux/soc/nxp/lpc32xx-misc.h>
30	30
31	31	/*
32	32	* High Speed UART register offsets
@@ -81,6 +81,8 @@ · 48 unmodified lines
81	81	#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
82	82	#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
83	83
	84	+#define LPC32XX_MAIN_OSC_FREQ 13000000
	85	+
84	86	#define MODNAME "lpc32xx_hsuart"
85	87
86	88	struct lpc32xx_hsuart_port {
@@ -151,8 +153,6 @@ static void lpc32xx_hsuart_console_write(struct console co, const char s, · 64 unmodified lines
151	153	local_irq_restore(flags);
152	154	}
153	155
154		−static void lpc32xx_loopback_set(resource_size_t mapbase, int state);
155		−
156	156	static int __init lpc32xx_hsuart_console_setup(struct console *co,
157	157	char *options)
158	158	{
@@ -439,35 +439,6 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port, · 280 unmodified lines
439	439	spin_unlock_irqrestore(&port->lock, flags);
440	440	}
441	441
442		−/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
443		−static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
444		−{
445		− int bit;
446		− u32 tmp;
447		−
448		− switch (mapbase) {
449		− case LPC32XX_HS_UART1_BASE:
450		− bit = 0;
451		− break;
452		− case LPC32XX_HS_UART2_BASE:
453		− bit = 1;
454		− break;
455		− case LPC32XX_HS_UART7_BASE:
456		− bit = 6;
457		− break;
458		− default:
459		− WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
460		− return;
461		− }
462		−
463		− tmp = readl(LPC32XX_UARTCTL_CLOOP);
464		− if (state)
465		− tmp \|= (1 << bit);
466		− else
467		− tmp &= ~(1 << bit);
468		− writel(tmp, LPC32XX_UARTCTL_CLOOP);
469		−}
470		−
471	442	/* port->lock is not held. */
472	443	static int serial_lpc32xx_startup(struct uart_port *port)
473	444	{

drivers/usb/gadget/udc/Kconfig+2−1

@@ -45,7 +45,8 @@ config USB_AT91 · 44 unmodified lines
45	45
46	46	config USB_LPC32XX
47	47	tristate "LPC32XX USB Peripheral Controller"
48		− depends on ARCH_LPC32XX && I2C
	48	+ depends on ARCH_LPC32XX \|\| COMPILE_TEST
	49	+ depends on I2C
49	50	select USB_ISP1301
50	51	help
51	52	This option selects the USB device controller in the LPC32xx SoC.

drivers/usb/gadget/udc/lpc32xx_udc.c+1−2

@@ -24,6 +24,7 @@ · 23 unmodified lines
24	24	#include <linux/module.h>
25	25	#include <linux/of.h>
26	26	#include <linux/platform_device.h>
	27	+#include <linux/prefetch.h>
27	28	#include <linux/proc_fs.h>
28	29	#include <linux/slab.h>
29	30	#include <linux/usb/ch9.h>
@@ -35,8 +36,6 @@ · 5 unmodified lines
35	36	#include <linux/seq_file.h>
36	37	#endif
37	38
38		−#include <mach/hardware.h>
39		−
40	39	/*
41	40	* USB device configuration structure
42	41	*/

drivers/usb/host/Kconfig+2−1

@@ -441,7 +441,8 @@ config USB_OHCI_HCD_S3C2410 · 440 unmodified lines
441	441
442	442	config USB_OHCI_HCD_LPC32XX
443	443	tristate "Support for LPC on-chip OHCI USB controller"
444		− depends on USB_OHCI_HCD && ARCH_LPC32XX
	444	+ depends on USB_OHCI_HCD
	445	+ depends on ARCH_LPC32XX \|\| COMPILE_TEST
445	446	depends on USB_ISP1301
446	447	default y
447	448	---help---

drivers/usb/host/ohci-nxp.c+18−7

@@ -29,10 +29,7 @@ · 28 unmodified lines
29	29
30	30	#include "ohci.h"
31	31
32		−#include <mach/hardware.h>
33		−
34	32	#define USB_CONFIG_BASE 0x31020000
35		−#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110)
36	33
37	34	/* USB_OTG_STAT_CONTROL bit defines */
38	35	#define TRANSPARENT_I2C_EN (1 << 7)
@@ -122,19 +119,33 @@ static inline void isp1301_vbus_off(void) · 83 unmodified lines
122	119
123	120	static void ohci_nxp_start_hc(void)
124	121	{
125		− unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) \| HOST_EN;
	122	+ void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
	123	+ unsigned long tmp;
	124	+
	125	+ if (WARN_ON(!usb_otg_stat_control))
	126	+ return;
	127	+
	128	+ tmp = __raw_readl(usb_otg_stat_control) \| HOST_EN;
126	129
127		− __raw_writel(tmp, USB_OTG_STAT_CONTROL);
	130	+ __raw_writel(tmp, usb_otg_stat_control);
128	131	isp1301_vbus_on();
	132	+
	133	+ iounmap(usb_otg_stat_control);
129	134	}
130	135
131	136	static void ohci_nxp_stop_hc(void)
132	137	{
	138	+ void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
133	139	unsigned long tmp;
134	140
	141	+ if (WARN_ON(!usb_otg_stat_control))
	142	+ return;
	143	+
135	144	isp1301_vbus_off();
136		− tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
137		− __raw_writel(tmp, USB_OTG_STAT_CONTROL);
	145	+ tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN;
	146	+ __raw_writel(tmp, usb_otg_stat_control);
	147	+
	148	+ iounmap(usb_otg_stat_control);
138	149	}
139	150
140	151	static int ohci_hcd_nxp_probe(struct platform_device *pdev)

drivers/watchdog/Kconfig+1−1

@@ -551,7 +551,7 @@ config OMAP_WATCHDOG · 550 unmodified lines
551	551
552	552	config PNX4008_WATCHDOG
553	553	tristate "LPC32XX Watchdog"
554		− depends on ARCH_LPC32XX
	554	+ depends on ARCH_LPC32XX \|\| COMPILE_TEST
555	555	select WATCHDOG_CORE
556	556	help
557	557	Say Y here if to include support for the watchdog timer

drivers/watchdog/pnx4008_wdt.c+0−1

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	30	#include <linux/of.h>
31	31	#include <linux/delay.h>
32	32	#include <linux/reboot.h>
33		−#include <mach/hardware.h>
34	33
35	34	/* WatchDog Timer - Chapter 23 Page 207 */
36	35

include/linux/soc/nxp/lpc32xx-misc.h+33−0

@@ -0,0 +1,33 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	+/*
	3	+ * Author: Kevin Wells <kevin.wells@nxp.com>
	4	+ *
	5	+ * Copyright (C) 2010 NXP Semiconductors
	6	+ */
	7	+
	8	+#ifndef __SOC_LPC32XX_MISC_H
	9	+#define __SOC_LPC32XX_MISC_H
	10	+
	11	+#include <linux/types.h>
	12	+#include <linux/phy.h>
	13	+
	14	+#ifdef CONFIG_ARCH_LPC32XX
	15	+extern u32 lpc32xx_return_iram(void __iomem *mapbase, dma_addr_t dmaaddr);
	16	+extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode);
	17	+extern void lpc32xx_loopback_set(resource_size_t mapbase, int state);
	18	+#else
	19	+static inline u32 lpc32xx_return_iram(void __iomem *mapbase, dma_addr_t dmaaddr)
	20	+{
	21	+ *mapbase = NULL;
	22	+ *dmaaddr = 0;
	23	+ return 0;
	24	+}
	25	+static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
	26	+{
	27	+}
	28	+static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state)
	29	+{
	30	+}
	31	+#endif
	32	+
	33	+#endif /* __SOC_LPC32XX_MISC_H */

Merge branch 'lpc32xx/multiplatform' into arm/soc

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