Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits) soc: aspeed: fix Kconfig soc: add aspeed folder and misc drivers spi: zynqmp: Fix build break soc: imx: Add generic i.MX8 SoC driver MAINTAINERS: Update email for Qualcomm SoC maintainer memory: tegra: Fix a typos for "fdcdwr2" mc client Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" memory: tegra: Replace readl-writel with mc_readl-mc_writel memory: tegra: Fix integer overflow on tick value calculation memory: tegra: Fix missed registers values latching ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 optee: allow to work without static shared memory soc/tegra: pmc: Move powergate initialisation to probe soc/tegra: pmc: Remove reset sysfs entries on error soc/tegra: pmc: Fix reset sources and levels soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask fpga manager: Adding FPGA Manager support for Xilinx zynqmp dt-bindings: fpga: Add bindings for ZynqMP fpga driver firmware: xilinx: Add fpga API's ...
Showing the changes to include/linux (6 of 71 files). Show all
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| @@ -15,4 +15,9 @@ · 14 unmodified lines | ||
| 15 | 15 | |
| 16 | 16 | #include <linux/firmware/imx/svc/misc.h> |
| 17 | 17 | #include <linux/firmware/imx/svc/pm.h> |
| 18 | + | |
| 19 | +int imx_scu_enable_general_irq_channel(struct device *dev); | |
| 20 | +int imx_scu_irq_register_notifier(struct notifier_block *nb); | |
| 21 | +int imx_scu_irq_unregister_notifier(struct notifier_block *nb); | |
| 22 | +int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable); | |
| 18 | 23 | #endif /* _SC_SCI_H */ |
| @@ -48,6 +48,14 @@ · 47 unmodified lines | ||
| 48 | 48 | #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U |
| 49 | 49 | #define ZYNQMP_PM_CAPABILITY_POWER 0x8U |
| 50 | 50 | |
| 51 | +/* | |
| 52 | + * Firmware FPGA Manager flags | |
| 53 | + * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration | |
| 54 | + * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration | |
| 55 | + */ | |
| 56 | +#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U | |
| 57 | +#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) | |
| 58 | + | |
| 51 | 59 | enum pm_api_id { |
| 52 | 60 | PM_GET_API_VERSION = 1, |
| 53 | 61 | PM_REQUEST_NODE = 13, |
| @@ -56,6 +64,8 @@ enum pm_api_id { · 2 unmodified lines | ||
| 56 | 64 | PM_RESET_ASSERT = 17, |
| 57 | 65 | PM_RESET_GET_STATUS, |
| 58 | 66 | PM_PM_INIT_FINALIZE = 21, |
| 67 | + PM_FPGA_LOAD, | |
| 68 | + PM_FPGA_GET_STATUS, | |
| 59 | 69 | PM_GET_CHIPID = 24, |
| 60 | 70 | PM_IOCTL = 34, |
| 61 | 71 | PM_QUERY_DATA, |
| @@ -258,6 +268,8 @@ struct zynqmp_pm_query_data { · 196 unmodified lines | ||
| 258 | 268 | struct zynqmp_eemi_ops { |
| 259 | 269 | int (*get_api_version)(u32 *version); |
| 260 | 270 | int (*get_chipid)(u32 *idcode, u32 *version); |
| 271 | + int (*fpga_load)(const u64 address, const u32 size, const u32 flags); | |
| 272 | + int (*fpga_get_status)(u32 *value); | |
| 261 | 273 | int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); |
| 262 | 274 | int (*clock_enable)(u32 clock_id); |
| 263 | 275 | int (*clock_disable)(u32 clock_id); |
| @@ -293,7 +305,7 @@ const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); · 29 unmodified lines | ||
| 293 | 305 | #else |
| 294 | 306 | static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) |
| 295 | 307 | { |
| 296 | − return NULL; | |
| 308 | + return ERR_PTR(-ENODEV); | |
| 297 | 309 | } |
| 298 | 310 | #endif |
| 299 | 311 | |
| @@ -51,6 +51,11 @@ struct am33xx_pm_platform_data { · 50 unmodified lines | ||
| 51 | 51 | unsigned long args); |
| 52 | 52 | struct am33xx_pm_sram_addr *(*get_sram_addrs)(void); |
| 53 | 53 | void __iomem *(*get_rtc_base_addr)(void); |
| 54 | + void (*save_context)(void); | |
| 55 | + void (*restore_context)(void); | |
| 56 | + void (*prepare_rtc_suspend)(void); | |
| 57 | + void (*prepare_rtc_resume)(void); | |
| 58 | + int (*check_off_mode_enable)(void); | |
| 54 | 59 | }; |
| 55 | 60 | |
| 56 | 61 | struct am33xx_pm_sram_data { |
| @@ -2,6 +2,8 @@ · 1 unmodified line | ||
| 2 | 2 | #ifndef _LINUX_RESET_H_ |
| 3 | 3 | #define _LINUX_RESET_H_ |
| 4 | 4 | |
| 5 | +#include <linux/err.h> | |
| 6 | +#include <linux/errno.h> | |
| 5 | 7 | #include <linux/types.h> |
| 6 | 8 | |
| 7 | 9 | struct device; |
| @@ -0,0 +1,7 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | + | |
| 3 | +#ifndef _LINUX_RTCOMAP_H_ | |
| 4 | +#define _LINUX_RTCOMAP_H_ | |
| 5 | + | |
| 6 | +int omap_rtc_power_off_program(struct device *dev); | |
| 7 | +#endif /* _LINUX_RTCOMAP_H_ */ | |
| @@ -55,6 +55,7 @@ struct ti_emif_pm_data { · 54 unmodified lines | ||
| 55 | 55 | struct ti_emif_pm_functions { |
| 56 | 56 | u32 save_context; |
| 57 | 57 | u32 restore_context; |
| 58 | + u32 run_hw_leveling; | |
| 58 | 59 | u32 enter_sr; |
| 59 | 60 | u32 exit_sr; |
| 60 | 61 | u32 abort_sr; |
| @@ -126,6 +127,8 @@ static inline void ti_emif_asm_offsets(void) · 65 unmodified lines | ||
| 126 | 127 | offsetof(struct ti_emif_pm_functions, save_context)); |
| 127 | 128 | DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET, |
| 128 | 129 | offsetof(struct ti_emif_pm_functions, restore_context)); |
| 130 | + DEFINE(EMIF_PM_RUN_HW_LEVELING, | |
| 131 | + offsetof(struct ti_emif_pm_functions, run_hw_leveling)); | |
| 129 | 132 | DEFINE(EMIF_PM_ENTER_SR_OFFSET, |
| 130 | 133 | offsetof(struct ti_emif_pm_functions, enter_sr)); |
| 131 | 134 | DEFINE(EMIF_PM_EXIT_SR_OFFSET, |