History

Merge drm/drm-next into drm-intel-next

Sync the drm-intel-gt-next changes back to drm-intel-next via drm-next.

Jani Nikula committed 3 years ago

Commit e2a9f0a2 parents 3e36c49 85d712f497 files · +11303 −4747Browse files

Unified · Split

497 files
  1. Documentation/block/index.rst +0 −1
  2. Documentation/block/request.rst +0 −99
  3. Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +4 −1
  4. Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +23 −0
  5. Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml +11 −3
  6. Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml +11 −5
  7. Documentation/devicetree/bindings/display/panel/panel-simple.yaml +4 −0
  8. Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml +2 −0
  9. Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml +70 −0
  10. Documentation/devicetree/bindings/media/i2c/ovti,ov2685.yaml +1 −0
  11. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +2 −11
  12. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +38 −0
  13. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +77 −0
  14. Documentation/gpu/rfc/index.rst +4 −0
  15. Documentation/gpu/rfc/xe.rst +235 −0
  16. Documentation/gpu/todo.rst +2 −5
  17. Documentation/gpu/vkms.rst +1 −6
  18. Documentation/networking/bonding.rst +5 −4
  19. Documentation/networking/index.rst +1 −1
  20. Documentation/networking/x25-iface.rst +1 −2
  21. MAINTAINERS +1156 −1148
  22. Makefile +1 −1
  23. arch/arc/include/asm/fb.h +2 −14
  24. arch/arm/include/asm/fb.h +1 −14
  25. arch/arm/kernel/unwind.c +24 −1
  26. arch/arm/mach-sa1100/jornada720_ssp.c +4 −1
  27. arch/arm/vfp/entry.S +5 −2
  28. arch/arm/vfp/vfphw.S +4 −2
  29. arch/arm64/include/asm/fb.h +1 −14
  30. arch/ia64/include/asm/fb.h +23 −4
  31. arch/loongarch/include/asm/fb.h +16 −8
  32. arch/m68k/include/asm/fb.h +7 −15
  33. arch/mips/include/asm/fb.h +24 −4
  34. arch/parisc/Makefile +3 −1
  35. arch/parisc/include/asm/fb.h +5 −15
  36. arch/parisc/include/asm/pgtable.h +4 −4
  37. arch/parisc/kernel/kexec.c +2 −0
  38. arch/parisc/video/Makefile +3 −0
  39. arch/parisc/video/fbdev.c +26 −0
  40. arch/powerpc/include/asm/fb.h +3 −5
  41. arch/riscv/kernel/pi/Makefile +1 −1
  42. arch/riscv/kernel/vmlinux.lds.S +2 −5
  43. arch/sh/include/asm/fb.h +1 −14
  44. arch/sparc/Makefile +1 −0
  45. arch/sparc/include/asm/fb.h +27 −20
  46. arch/sparc/video/Makefile +3 −0
  47. arch/sparc/video/fbdev.c +23 −0
  48. arch/x86/events/core.c +2 −4
  49. arch/x86/events/intel/ds.c +32 −24
  50. arch/x86/include/asm/fb.h +8 −13
  51. arch/x86/include/asm/perf_event.h +3 −0
  52. arch/x86/kernel/amd_nb.c +2 −0
  53. arch/x86/lib/retpoline.S +2 −2
  54. arch/x86/video/fbdev.c +15 −13
  55. drivers/auxdisplay/cfag12864bfb.c +1 −1
  56. drivers/auxdisplay/ht16k33.c +1 −1
  57. drivers/block/nbd.c +2 −2
  58. drivers/block/rnbd/rnbd-proto.h +1 −1
  59. drivers/block/ublk_drv.c +1 −1
  60. drivers/cxl/core/pci.c +1 −0
  61. drivers/dma-buf/dma-resv.c +1 −1
  62. drivers/dma-buf/sw_sync.c +1 −1
  63. drivers/firewire/net.c +11 −10
  64. drivers/firmware/sysfb.c +1 −1
  65. drivers/firmware/sysfb_simplefb.c +3 −1
  66. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +11 −1
  67. drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +5 −3
  68. drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +0 −46
  69. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +2 −1
  70. drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +1 −0
  71. drivers/gpu/drm/amd/amdgpu/nv.c +16 −6
  72. drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +5 −3
  73. drivers/gpu/drm/amd/amdgpu/soc21.c +1 −1
  74. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c +65 −0
  75. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h +2 −0
  76. drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c +1 −1
  77. drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +3 −2
  78. drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h +1 −0
  79. drivers/gpu/drm/amd/pm/amdgpu_dpm.c +18 −7
  80. drivers/gpu/drm/arm/hdlcd_drv.c +1 −1
  81. drivers/gpu/drm/armada/Makefile +2 −1
  82. drivers/gpu/drm/armada/armada_drm.h +6 −4
  83. drivers/gpu/drm/armada/armada_drv.c +4 −10
  84. drivers/gpu/drm/armada/armada_fb.c +0 −1
  85. drivers/gpu/drm/armada/armada_fbdev.c +87 −32
  86. drivers/gpu/drm/ast/ast_main.c +5 −4
  87. drivers/gpu/drm/bridge/analogix/anx7625.c +88 −41
  88. drivers/gpu/drm/bridge/fsl-ldb.c +13 −1
  89. drivers/gpu/drm/bridge/ite-it6505.c +2 −1
  90. drivers/gpu/drm/bridge/lontium-lt9211.c +3 −1
  91. drivers/gpu/drm/bridge/lontium-lt9611.c +3 −1
  92. drivers/gpu/drm/bridge/samsung-dsim.c +26 −2
  93. drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +1 −1
  94. drivers/gpu/drm/bridge/tc358767.c +2 −2
  95. drivers/gpu/drm/bridge/tc358768.c +74 −23
  96. drivers/gpu/drm/bridge/ti-sn65dsi83.c +1 −0
  97. drivers/gpu/drm/bridge/ti-sn65dsi86.c +19 −0
  98. drivers/gpu/drm/drm_aperture.c +3 −8
  99. drivers/gpu/drm/drm_atomic_helper.c +11 −2
  100. drivers/gpu/drm/drm_drv.c +3 −1
  101. drivers/gpu/drm/drm_fb_helper.c +16 −174
  102. drivers/gpu/drm/drm_gem_framebuffer_helper.c +9 −0
  103. drivers/gpu/drm/drm_gem_vram_helper.c +3 −3
  104. drivers/gpu/drm/drm_mipi_dsi.c +1 −1
  105. drivers/gpu/drm/drm_sysfs.c +51 −0
  106. drivers/gpu/drm/gma500/fbdev.c +1 −1
  107. drivers/gpu/drm/gma500/psb_drv.c +34 −9
  108. drivers/gpu/drm/hyperv/hyperv_drm_drv.c +0 −1
  109. drivers/gpu/drm/i915/Makefile +4 −2
  110. drivers/gpu/drm/i915/display/intel_dpt.c +7 −7
  111. drivers/gpu/drm/i915/display/intel_fb.c +6 −3
  112. drivers/gpu/drm/i915/display/intel_fbdev.c +24 −14
  113. drivers/gpu/drm/i915/display/intel_plane_initial.c +3 −1
  114. drivers/gpu/drm/i915/gem/i915_gem_domain.c +43 −18
  115. drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +12 −3
  116. drivers/gpu/drm/i915/gem/i915_gem_mman.c +102 −46
  117. drivers/gpu/drm/i915/gem/i915_gem_mman.h +1 −1
  118. drivers/gpu/drm/i915/gem/i915_gem_object.c +59 −1
  119. drivers/gpu/drm/i915/gem/i915_gem_object.h +9 −1
  120. drivers/gpu/drm/i915/gem/i915_gem_object_types.h +60 −8
  121. drivers/gpu/drm/i915/gem/i915_gem_pages.c +4 −1
  122. drivers/gpu/drm/i915/gem/i915_gem_region.h +1 −3
  123. drivers/gpu/drm/i915/gem/i915_gem_shmem.c +8 −1
  124. drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +0 −2
  125. drivers/gpu/drm/i915/gem/i915_gem_stolen.c +11 −1
  126. drivers/gpu/drm/i915/gem/i915_gem_ttm.h +2 −1
  127. drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +8 −5
  128. drivers/gpu/drm/i915/gem/selftests/huge_pages.c +82 −26
  129. drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +10 −8
  130. drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c +1 −1
  131. drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +1 −1
  132. drivers/gpu/drm/i915/gt/gen6_ppgtt.c +6 −4
  133. drivers/gpu/drm/i915/gt/gen8_ppgtt.c +61 −23
  134. drivers/gpu/drm/i915/gt/gen8_ppgtt.h +1 −2
  135. drivers/gpu/drm/i915/gt/intel_context.c +4 −1
  136. drivers/gpu/drm/i915/gt/intel_context.h +4 −4
  137. drivers/gpu/drm/i915/gt/intel_context_types.h +2 −0
  138. drivers/gpu/drm/i915/gt/intel_engine_cs.c +1 −1
  139. drivers/gpu/drm/i915/gt/intel_engine_types.h +1 −0
  140. drivers/gpu/drm/i915/gt/intel_engine_user.c +1 −1
  141. drivers/gpu/drm/i915/gt/intel_ggtt.c +59 −25
  142. drivers/gpu/drm/i915/gt/intel_gt_irq.c +21 −4
  143. drivers/gpu/drm/i915/gt/intel_gt_pm.c +2 −2
  144. drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +4 −1
  145. drivers/gpu/drm/i915/gt/intel_gt_regs.h +13 −1
  146. drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +35 −0
  147. drivers/gpu/drm/i915/gt/intel_gtt.c +46 −1
  148. drivers/gpu/drm/i915/gt/intel_gtt.h +25 −11
  149. drivers/gpu/drm/i915/gt/intel_lrc.c +3 −1
  150. drivers/gpu/drm/i915/gt/intel_migrate.c +28 −23
  151. drivers/gpu/drm/i915/gt/intel_migrate.h +6 −7
  152. drivers/gpu/drm/i915/gt/intel_mocs.c +69 −1
  153. drivers/gpu/drm/i915/gt/intel_ppgtt.c +2 −2
  154. drivers/gpu/drm/i915/gt/intel_rc6.c +84 −83
  155. drivers/gpu/drm/i915/gt/intel_workarounds.c +41 −15
  156. drivers/gpu/drm/i915/gt/selftest_engine_pm.c +2 −1
  157. drivers/gpu/drm/i915/gt/selftest_migrate.c +25 −22
  158. drivers/gpu/drm/i915/gt/selftest_mocs.c +2 −1
  159. drivers/gpu/drm/i915/gt/selftest_reset.c +6 −2
  160. drivers/gpu/drm/i915/gt/selftest_slpc.c +37 −5
  161. drivers/gpu/drm/i915/gt/selftest_timeline.c +1 −1
  162. drivers/gpu/drm/i915/gt/selftest_tlb.c +3 −1
  163. drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h +1 −0
  164. drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h +14 −6
  165. drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c +23 −0
  166. drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h +1 −0
  167. drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c +424 −0
  168. drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h +18 −0
  169. drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c +72 −4
  170. drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h +16 −1
  171. drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c +102 −0
  172. drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h +26 −1
  173. drivers/gpu/drm/i915/gt/uc/intel_guc.c +7 −0
  174. drivers/gpu/drm/i915/gt/uc/intel_guc.h +1 −0
  175. drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +35 −1
  176. drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +121 −148
  177. drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h +3 −0
  178. drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +59 −0
  179. drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +6 −0
  180. drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c +10 −2
  181. drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +10 −1
  182. drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +29 −11
  183. drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +1 −0
  184. drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h +1 −0
  185. drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +65 −10
  186. drivers/gpu/drm/i915/gt/uc/intel_uc.c +14 −2
  187. drivers/gpu/drm/i915/gt/uc/intel_uc.h +1 −0
  188. drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +154 −84
  189. drivers/gpu/drm/i915/gvt/aperture_gm.c +1 −1
  190. drivers/gpu/drm/i915/i915_active.h +7 −7
  191. drivers/gpu/drm/i915/i915_debugfs.c +43 −10
  192. drivers/gpu/drm/i915/i915_drm_client.c +1 −5
  193. drivers/gpu/drm/i915/i915_drv.h +195 −196
  194. drivers/gpu/drm/i915/i915_gem.c +23 −4
  195. drivers/gpu/drm/i915/i915_getparam.c +7 −0
  196. drivers/gpu/drm/i915/i915_gpu_error.c +147 −6
  197. drivers/gpu/drm/i915/i915_gpu_error.h +10 −0
  198. drivers/gpu/drm/i915/i915_hwmon.c +75 −12
  199. drivers/gpu/drm/i915/i915_hwmon.h +7 −0
  200. drivers/gpu/drm/i915/i915_irq.c +11 −6
  201. drivers/gpu/drm/i915/i915_pci.c +71 −9
  202. drivers/gpu/drm/i915/i915_perf.c +1 −0
  203. drivers/gpu/drm/i915/i915_perf_oa_regs.h +0 −4
  204. drivers/gpu/drm/i915/i915_pmu.c +205 −85
  205. drivers/gpu/drm/i915/i915_pmu.h +18 −10
  206. drivers/gpu/drm/i915/i915_request.h +26 −26
  207. drivers/gpu/drm/i915/i915_scatterlist.h +4 −5
  208. drivers/gpu/drm/i915/i915_utils.h +1 −1
  209. drivers/gpu/drm/i915/i915_vma.c +8 −8
  210. drivers/gpu/drm/i915/i915_vma.h +2 −2
  211. drivers/gpu/drm/i915/i915_vma_resource.h +28 −18
  212. drivers/gpu/drm/i915/i915_vma_types.h +0 −2
  213. drivers/gpu/drm/i915/intel_device_info.h +5 −0
  214. drivers/gpu/drm/i915/pxp/intel_pxp.c +78 −24
  215. drivers/gpu/drm/i915/pxp/intel_pxp.h +2 −0
  216. drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +24 −0
  217. drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +5 −1
  218. drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +444 −0
  219. drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h +43 −0
  220. drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +2 −1
  221. drivers/gpu/drm/i915/pxp/intel_pxp_regs.h +27 −0
  222. drivers/gpu/drm/i915/pxp/intel_pxp_session.c +14 −11
  223. drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +0 −2
  224. drivers/gpu/drm/i915/pxp/intel_pxp_types.h +23 −1
  225. drivers/gpu/drm/i915/selftests/i915_gem.c +4 −1
  226. drivers/gpu/drm/i915/selftests/i915_gem_evict.c +5 −3
  227. drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +10 −5
  228. drivers/gpu/drm/i915/selftests/igt_live_test.c +28 −19
  229. drivers/gpu/drm/i915/selftests/intel_memory_region.c +3 −1
  230. drivers/gpu/drm/i915/selftests/mock_gem_device.c +9 −0
  231. drivers/gpu/drm/i915/selftests/mock_gtt.c +4 −4
  232. drivers/gpu/drm/imx/lcdc/imx-lcdc.c +2 −2
  233. drivers/gpu/drm/meson/meson_drv.c +1 −1
  234. drivers/gpu/drm/meson/meson_venc.c +16 −16
  235. drivers/gpu/drm/msm/msm_drv.c +1 −1
  236. drivers/gpu/drm/msm/msm_fbdev.c +3 −3
  237. drivers/gpu/drm/nouveau/dispnv50/disp.c +1 −0
  238. drivers/gpu/drm/nouveau/include/nvif/if0012.h +3 −1
  239. drivers/gpu/drm/nouveau/nouveau_debugfs.c +10 −9
  240. drivers/gpu/drm/nouveau/nouveau_hwmon.c +1 −1
  241. drivers/gpu/drm/nouveau/nv50_display.h +1 −3
  242. drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h +2 −1
  243. drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c +1 −1
  244. drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c +1 −2
  245. drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +1 −1
  246. drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c +1 −1
  247. drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c +3 −4
  248. drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c +1 −1
  249. drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c +1 −1
  250. drivers/gpu/drm/panel/Kconfig +7 −0
  251. drivers/gpu/drm/panel/Makefile +1 −0
  252. drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +241 −163
  253. drivers/gpu/drm/panel/panel-novatek-nt36523.c +566 −3
  254. drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c +585 −0
  255. drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c +6 −37
  256. drivers/gpu/drm/panel/panel-simple.c +69 −0
  257. drivers/gpu/drm/panel/panel-sitronix-st7703.c +99 −3
  258. drivers/gpu/drm/rockchip/cdn-dp-core.c +2 −3
  259. drivers/gpu/drm/rockchip/rockchip_drm_drv.c +1 −1
  260. drivers/gpu/drm/rockchip/rockchip_drm_vop.c +4 −4
  261. drivers/gpu/drm/scheduler/sched_entity.c +40 −13
  262. drivers/gpu/drm/scheduler/sched_fence.c +3 −1
  263. drivers/gpu/drm/scheduler/sched_main.c +20 −19
  264. drivers/gpu/drm/shmobile/Kconfig +2 −2
  265. drivers/gpu/drm/shmobile/shmob_drm_crtc.c +31 −4
  266. drivers/gpu/drm/shmobile/shmob_drm_drv.c +3 −0
  267. drivers/gpu/drm/shmobile/shmob_drm_kms.c +7 −2
  268. drivers/gpu/drm/shmobile/shmob_drm_plane.c +5 −0
  269. drivers/gpu/drm/solomon/ssd130x.h +3 −3
  270. drivers/gpu/drm/sti/sti_dvo.c +1 −1
  271. drivers/gpu/drm/sti/sti_hdmi.c +6 −5
  272. drivers/gpu/drm/sti/sti_hdmi.h +0 −2
  273. drivers/gpu/drm/stm/drv.c +1 −1
  274. drivers/gpu/drm/sun4i/Makefile +1 −1
  275. drivers/gpu/drm/sun4i/sun4i_drv.c +1 −1
  276. drivers/gpu/drm/sun4i/sun4i_tcon.c +30 −35
  277. drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c +1 −1
  278. drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h +0 −0
  279. drivers/gpu/drm/tegra/drm.c +1 −1
  280. drivers/gpu/drm/tests/drm_rect_test.c +315 −0
  281. drivers/gpu/drm/ttm/ttm_device.c +1 −1
  282. drivers/gpu/drm/tve200/tve200_drv.c +1 −3
  283. drivers/gpu/drm/udl/udl_main.c +1 −1
  284. drivers/gpu/drm/vc4/tests/vc4_mock.h +3 −0
  285. drivers/gpu/drm/vc4/tests/vc4_mock_output.c +2 −2
  286. drivers/gpu/drm/vc4/vc4_dpi.c +2 −5
  287. drivers/gpu/drm/vc4/vc4_drv.c +1 −1
  288. drivers/gpu/drm/vc4/vc4_drv.h +19 −46
  289. drivers/gpu/drm/vc4/vc4_dsi.c +6 −11
  290. drivers/gpu/drm/vc4/vc4_hdmi.c +281 −55
  291. drivers/gpu/drm/vc4/vc4_hdmi.h +14 −11
  292. drivers/gpu/drm/vc4/vc4_kms.c +5 −11
  293. drivers/gpu/drm/vc4/vc4_plane.c +1 −2
  294. drivers/gpu/drm/vc4/vc4_txp.c +4 −8
  295. drivers/gpu/drm/vc4/vc4_vec.c +4 −10
  296. drivers/gpu/drm/vkms/vkms_composer.c +31 −7
  297. drivers/gpu/drm/vkms/vkms_crtc.c +2 −3
  298. drivers/gpu/drm/vkms/vkms_drv.c +5 −1
  299. drivers/gpu/drm/vkms/vkms_drv.h +4 −2
  300. drivers/gpu/drm/vkms/vkms_formats.c +68 −77
  301. drivers/gpu/drm/vkms/vkms_formats.h +1 −1
  302. drivers/gpu/drm/vkms/vkms_plane.c +18 −32
  303. drivers/gpu/ipu-v3/ipu-prv.h +1 −0
  304. drivers/hid/hid-picolcd_fb.c +2 −2
  305. drivers/hwmon/k10temp.c +1 −0
  306. drivers/media/pci/ivtv/ivtvfb.c +2 −2
  307. drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +1 −2
  308. drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c +3 −3
  309. drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c +21 −20
  310. drivers/media/platform/renesas/rcar-vin/rcar-dma.c +15 −6
  311. drivers/misc/mei/Kconfig +1 −1
  312. drivers/misc/mei/Makefile +1 −0
  313. drivers/misc/mei/gsc_proxy/Kconfig +14 −0
  314. drivers/misc/mei/gsc_proxy/Makefile +7 −0
  315. drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c +208 −0
  316. drivers/net/bonding/bond_netlink.c +6 −1
  317. drivers/net/bonding/bond_options.c +7 −1
  318. drivers/net/ethernet/google/gve/gve_main.c +0 −13
  319. drivers/net/ethernet/mediatek/mtk_wed.c +1 −1
  320. drivers/net/ethernet/mscc/vsc7514_regs.c +9 −9
  321. drivers/net/ethernet/stmicro/stmmac/dwmac4.h +1 −0
  322. drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +5 −0
  323. drivers/net/ipvlan/ipvlan_core.c +6 −0
  324. drivers/net/mdio/mdio-mvusb.c +10 −1
  325. drivers/net/pcs/pcs-xpcs.c +1 −1
  326. drivers/net/phy/bcm-phy-lib.h +5 −0
  327. drivers/net/phy/bcm7xxx.c +1 −1
  328. drivers/net/tap.c +2 −2
  329. drivers/platform/mellanox/mlxbf-tmfifo.c +9 −2
  330. drivers/platform/x86/hp/hp-wmi.c +1 −0
  331. drivers/platform/x86/intel/uncore-frequency/uncore-frequency-common.c +5 −1
  332. drivers/platform/x86/intel_scu_pcidrv.c +1 −0
  333. drivers/platform/x86/thinkpad_acpi.c +19 −5
  334. drivers/platform/x86/touchscreen_dmi.c +41 −0
  335. drivers/staging/sm750fb/sm750.c +1 −1
  336. drivers/ufs/core/ufshcd.c +9 −1
  337. drivers/video/Kconfig +7 −0
  338. drivers/video/Makefile +1 −0
  339. drivers/video/aperture.c +46 −24
  340. drivers/video/console/Kconfig +1 −0
  341. drivers/video/console/Makefile +1 −3
  342. drivers/video/console/sticon.c +3 −3
  343. drivers/video/fbdev/68328fb.c +6 −6
  344. drivers/video/fbdev/Kconfig +1 −2
  345. drivers/video/fbdev/arcfb.c +17 −10
  346. drivers/video/fbdev/atmel_lcdfb.c +1 −1
  347. drivers/video/fbdev/aty/atyfb.h +2 −0
  348. drivers/video/fbdev/aty/mach64_cursor.c +1 −1
  349. drivers/video/fbdev/au1200fb.c +1 −1
  350. drivers/video/fbdev/broadsheetfb.c +8 −8
  351. drivers/video/fbdev/cg14.c +1 −1
  352. drivers/video/fbdev/chipsfb.c +1 −1
  353. drivers/video/fbdev/cobalt_lcdfb.c +6 −0
  354. drivers/video/fbdev/controlfb.c +17 −17
  355. drivers/video/fbdev/core/Makefile +1 −1
  356. drivers/video/fbdev/core/fb_io_fops.c +133 −0
  357. drivers/video/fbdev/core/fb_sys_fops.c +20 −16
  358. drivers/video/fbdev/core/fbcon.c +0 −1
  359. drivers/video/fbdev/core/fbmem.c +4 −109
  360. drivers/video/fbdev/core/modedb.c +5 −0
  361. drivers/video/fbdev/g364fb.c +3 −3
  362. drivers/video/fbdev/hecubafb.c +6 −6
  363. drivers/video/fbdev/hgafb.c +18 −18
  364. drivers/video/fbdev/hitfb.c +69 −53
  365. drivers/video/fbdev/hpfb.c +4 −4
  366. drivers/video/fbdev/hyperv_fb.c +1 −1
  367. drivers/video/fbdev/imsttfb.c +8 −7
  368. drivers/video/fbdev/kyro/fbdev.c +1 −1
  369. drivers/video/fbdev/macfb.c +5 −5
  370. drivers/video/fbdev/matrox/matroxfb_accel.c +3 −3
  371. drivers/video/fbdev/matrox/matroxfb_base.h +2 −2
  372. drivers/video/fbdev/maxinefb.c +1 −1
  373. drivers/video/fbdev/metronomefb.c +8 −8
  374. drivers/video/fbdev/p9100.c +2 −2
  375. drivers/video/fbdev/platinumfb.c +15 −15
  376. drivers/video/fbdev/ps3fb.c +2 −2
  377. drivers/video/fbdev/pvr2fb.c +4 −1
  378. drivers/video/fbdev/sa1100fb.c +16 −16
  379. drivers/video/fbdev/sm712fb.c +2 −8
  380. drivers/video/fbdev/smscufx.c +7 −7
  381. drivers/video/fbdev/ssd1307fb.c +3 −0
  382. drivers/video/fbdev/sstfb.c +1 −1
  383. drivers/video/fbdev/stifb.c +82 −81
  384. drivers/video/fbdev/tdfxfb.c +1 −1
  385. drivers/video/fbdev/udlfb.c +6 −6
  386. drivers/video/fbdev/valkyriefb.c +7 −7
  387. drivers/video/fbdev/vfb.c +6 −6
  388. drivers/video/fbdev/wmt_ge_rops.c +2 −0
  389. drivers/video/fbdev/xen-fbfront.c +1 −1
  390. drivers/video/sticore.c +52 −71
  391. fs/btrfs/backref.c +10 −9
  392. fs/btrfs/backref.h +6 −0
  393. fs/btrfs/block-rsv.c +2 −1
  394. fs/btrfs/ctree.c +37 −1
  395. fs/btrfs/disk-io.c +18 −7
  396. fs/btrfs/file-item.c +3 −2
  397. fs/btrfs/free-space-cache.c +4 −3
  398. fs/btrfs/free-space-tree.c +49 −1
  399. fs/btrfs/free-space-tree.h +2 −1
  400. fs/btrfs/inode.c +3 −0
  401. fs/btrfs/ioctl.c +3 −1
  402. fs/btrfs/print-tree.c +3 −3
  403. fs/btrfs/relocation.c +1 −1
  404. fs/btrfs/super.c +5 −1
  405. fs/btrfs/volumes.c +1 −0
  406. fs/btrfs/zoned.c +8 −9
  407. fs/cifs/cifsfs.c +17 −1
  408. fs/cifs/connect.c +7 −0
  409. fs/cifs/smb2ops.c +1 −1
  410. fs/cifs/smb2pdu.c +3 −0
  411. fs/ext4/balloc.c +42 −1
  412. fs/ext4/ext4.h +26 −13
  413. fs/ext4/extents_status.c +13 −17
  414. fs/ext4/hash.c +5 −1
  415. fs/ext4/ialloc.c +8 −4
  416. fs/ext4/inline.c +14 −3
  417. fs/ext4/inode.c +11 −9
  418. fs/ext4/mballoc.c +58 −12
  419. fs/ext4/migrate.c +6 −5
  420. fs/ext4/mmp.c +21 −9
  421. fs/ext4/namei.c +37 −16
  422. fs/ext4/super.c +25 −12
  423. fs/ext4/xattr.c +3 −2
  424. fs/gfs2/super.c +8 −0
  425. fs/nfs/dir.c +1 −1
  426. fs/notify/inotify/inotify_fsnotify.c +9 −2
  427. fs/pipe.c +4 −2
  428. fs/xfs/libxfs/xfs_ag.c +9 −10
  429. fs/xfs/libxfs/xfs_bmap.c +3 −2
  430. fs/xfs/scrub/bmap.c +2 −2
  431. fs/xfs/scrub/common.c +0 −26
  432. fs/xfs/scrub/common.h +0 −2
  433. fs/xfs/scrub/fscounters.c +6 −7
  434. fs/xfs/scrub/scrub.c +0 −2
  435. fs/xfs/scrub/scrub.h +0 −1
  436. fs/xfs/scrub/trace.h +0 −1
  437. fs/xfs/xfs_bmap_util.c +3 −1
  438. fs/xfs/xfs_icache.c +33 −7
  439. fs/xfs/xfs_iomap.c +3 −2
  440. fs/xfs/xfs_mount.h +3 −0
  441. fs/xfs/xfs_super.c +3 −0
  442. include/asm-generic/fb.h +124 −2
  443. include/drm/bridge/samsung-dsim.h +2 −0
  444. include/drm/display/drm_dp.h +5 −3
  445. include/drm/display/drm_dp_helper.h +2 −3
  446. include/drm/drm_aperture.h +3 −4
  447. include/drm/drm_connector.h +5 −0
  448. include/drm/drm_fixed.h +6 −0
  449. include/drm/gpu_scheduler.h +4 −3
  450. include/drm/i915_component.h +2 −1
  451. include/drm/i915_gsc_proxy_mei_interface.h +53 −0
  452. include/drm/ttm/ttm_device.h +2 −2
  453. include/linux/aperture.h +11 −5
  454. include/linux/dim.h +2 −1
  455. include/linux/fb.h +12 −53
  456. include/linux/if_vlan.h +17 −0
  457. include/linux/io_uring.h +5 −5
  458. include/linux/pci_ids.h +1 −0
  459. include/net/bonding.h +1 −1
  460. include/net/sock.h +1 −1
  461. include/uapi/drm/drm_mode.h +5 −0
  462. include/uapi/drm/i915_drm.h +50 −1
  463. include/video/sticore.h +9 −7
  464. kernel/events/core.c +13 −1
  465. kernel/locking/rwsem.c +4 −4
  466. kernel/sched/core.c +2 −2
  467. kernel/time/tick-broadcast.c +88 −32
  468. lib/dim/dim.c +3 −2
  469. lib/dim/net_dim.c +2 −1
  470. lib/dim/rdma_dim.c +2 −1
  471. net/bridge/br_forward.c +1 −1
  472. net/core/datagram.c +10 −5
  473. net/core/dev.c +1 −1
  474. net/core/skbuff.c +2 −2
  475. net/core/stream.c +6 −6
  476. net/ipv4/af_inet.c +1 −1
  477. net/ipv4/tcp.c +8 −6
  478. net/ipv4/tcp_bpf.c +1 −1
  479. net/ipv4/tcp_input.c +2 −2
  480. net/llc/af_llc.c +5 −3
  481. net/netfilter/core.c +4 −2
  482. net/netfilter/nf_conntrack_standalone.c +2 −1
  483. net/netfilter/nft_chain_filter.c +6 −3
  484. net/netlink/af_netlink.c +4 −4
  485. net/packet/af_packet.c +2 −4
  486. net/smc/smc_close.c +2 −2
  487. net/smc/smc_rx.c +2 −2
  488. net/smc/smc_tx.c +2 −2
  489. net/socket.c +1 −1
  490. net/tipc/socket.c +2 −2
  491. net/tls/tls_main.c +2 −1
  492. net/unix/af_unix.c +13 −9
  493. tools/testing/cxl/test/mock.c +1 −1
  494. tools/testing/selftests/drivers/net/bonding/bond_options.sh +50 −0
  495. tools/testing/selftests/drivers/net/bonding/bond_topo_3d1c.sh +2 −0
  496. tools/testing/selftests/net/forwarding/lib.sh +2 −1
  497. tools/testing/selftests/netfilter/nft_flowtable.sh +139 −6
Documentation/block/index.rst+0−1
@@ -18,7 +18,6 @@ Block · 17 unmodified lines
1818 kyber-iosched
1919 null_blk
2020 pr
21− request
2221 stat
2322 switching-sched
2423 writeback_cache_control
Documentation/block/request.rst+0−99
@@ -1,99 +0,0 @@
1−============================
2−struct request documentation
3−============================
4−
5−Jens Axboe <jens.axboe@oracle.com> 27/05/02
6−
7−
8−.. FIXME:
9− No idea about what does mean - seems just some noise, so comment it
10−
11− 1.0
12− Index
13−
14− 2.0 Struct request members classification
15−
16− 2.1 struct request members explanation
17−
18− 3.0
19−
20−
21− 2.0
22−
23−
24−
25−Short explanation of request members
26−====================================
27−
28−Classification flags:
29−
30− = ====================
31− D driver member
32− B block layer member
33− I I/O scheduler member
34− = ====================
35−
36−Unless an entry contains a D classification, a device driver must not access
37−this member. Some members may contain D classifications, but should only be
38−access through certain macros or functions (eg ->flags).
39−
40−<linux/blkdev.h>
41−
42−=============================== ======= =======================================
43−Member Flag Comment
44−=============================== ======= =======================================
45−struct list_head queuelist BI Organization on various internal
46− queues
47−
48−``void *elevator_private`` I I/O scheduler private data
49−
50−unsigned char cmd[16] D Driver can use this for setting up
51− a cdb before execution, see
52− blk_queue_prep_rq
53−
54−unsigned long flags DBI Contains info about data direction,
55− request type, etc.
56−
57−int rq_status D Request status bits
58−
59−kdev_t rq_dev DBI Target device
60−
61−int errors DB Error counts
62−
63−sector_t sector DBI Target location
64−
65−unsigned long hard_nr_sectors B Used to keep sector sane
66−
67−unsigned long nr_sectors DBI Total number of sectors in request
68−
69−unsigned long hard_nr_sectors B Used to keep nr_sectors sane
70−
71−unsigned short nr_phys_segments DB Number of physical scatter gather
72− segments in a request
73−
74−unsigned short nr_hw_segments DB Number of hardware scatter gather
75− segments in a request
76−
77−unsigned int current_nr_sectors DB Number of sectors in first segment
78− of request
79−
80−unsigned int hard_cur_sectors B Used to keep current_nr_sectors sane
81−
82−int tag DB TCQ tag, if assigned
83−
84−``void *special`` D Free to be used by driver
85−
86−``char *buffer`` D Map of first segment, also see
87− section on bouncing SECTION
88−
89−``struct completion *waiting`` D Can be used by driver to get signalled
90− on request completion
91−
92−``struct bio *bio`` DBI First bio in request
93−
94−``struct bio *biotail`` DBI Last bio in request
95−
96−``struct request_queue *q`` DB Request queue this request belongs to
97−
98−``struct request_list *rl`` B Request list this request came from
99−=============================== ======= =======================================
Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml+4−1
@@ -17,6 +17,7 @@ description: | · 16 unmodified lines
1717 properties:
1818 compatible:
1919 enum:
20+ - fsl,imx6sx-ldb
2021 - fsl,imx8mp-ldb
2122 - fsl,imx93-ldb
2223
@@ -64,7 +65,9 @@ allOf: · 41 unmodified lines
6465 properties:
6566 compatible:
6667 contains:
67− const: fsl,imx93-ldb
68+ enum:
69+ - fsl,imx6sx-ldb
70+ - fsl,imx93-ldb
6871 then:
6972 properties:
7073 ports:
Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml+23−0
@@ -105,6 +105,29 @@ properties: · 104 unmodified lines
105105 DSI output port node to the panel or the next bridge
106106 in the chain.
107107
108+ properties:
109+ endpoint:
110+ $ref: /schemas/media/video-interfaces.yaml#
111+ unevaluatedProperties: false
112+
113+ properties:
114+ data-lanes:
115+ minItems: 1
116+ maxItems: 4
117+ uniqueItems: true
118+ items:
119+ enum: [ 1, 2, 3, 4 ]
120+
121+ lane-polarities:
122+ minItems: 1
123+ maxItems: 5
124+ description:
125+ The Samsung MIPI DSI IP requires that all the data lanes have
126+ the same polarity.
127+
128+ dependencies:
129+ lane-polarities: [data-lanes]
130+
108131 required:
109132 - clock-names
110133 - clocks
Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml+11−3
@@ -4,16 +4,24 @@ · 3 unmodified lines
44 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
55 $schema: http://devicetree.org/meta-schemas/core.yaml#
66
7−title: Toshiba TC358767 eDP bridge
7+title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
88
99 maintainers:
1010 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
1111
12−description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP
12+description: |
13+ The TC358767/TC358867/TC9595 is bridge device which
14+ converts DSI/DPI to eDP/DP .
1315
1416 properties:
1517 compatible:
16− const: toshiba,tc358767
18+ oneOf:
19+ - items:
20+ - enum:
21+ - toshiba,tc358867
22+ - toshiba,tc9595
23+ - const: toshiba,tc358767
24+ - const: toshiba,tc358767
1725
1826 reg:
1927 enum:
Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml+11−5
@@ -19,11 +19,16 @@ allOf: · 18 unmodified lines
1919
2020 properties:
2121 compatible:
22− items:
23− - enum:
24− - xiaomi,elish-boe-nt36523
25− - xiaomi,elish-csot-nt36523
26− - const: novatek,nt36523
22+ oneOf:
23+ - items:
24+ - enum:
25+ - xiaomi,elish-boe-nt36523
26+ - xiaomi,elish-csot-nt36523
27+ - const: novatek,nt36523
28+ - items:
29+ - enum:
30+ - lenovo,j606f-boe-nt36523w
31+ - const: novatek,nt36523w
2732
2833 reset-gpios:
2934 maxItems: 1
@@ -34,6 +39,7 @@ properties: · 4 unmodified lines
3439
3540 reg: true
3641 ports: true
42+ rotation: true
3743 backlight: true
3844
3945 required:
Documentation/devicetree/bindings/display/panel/panel-simple.yaml+4−0
@@ -77,6 +77,8 @@ properties: · 76 unmodified lines
7777 - auo,t215hvn01
7878 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
7979 - avic,tm070ddh03
80+ # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
81+ - boe,ev121wxm-n10-1850
8082 # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
8183 - boe,hv070wsa-100
8284 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
@@ -174,6 +176,8 @@ properties: · 91 unmodified lines
174176 - innolux,at043tn24
175177 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel
176178 - innolux,at070tn92
179+ # Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel
180+ - innolux,g070ace-l01
177181 # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
178182 - innolux,g070y2-l01
179183 # Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel
Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml+2−0
@@ -20,6 +20,8 @@ allOf: · 19 unmodified lines
2020 properties:
2121 compatible:
2222 enum:
23+ # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel
24+ - anbernic,rg353v-panel-v2
2325 # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
2426 - rocktech,jh057n00900
2527 # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel
Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml+70−0
@@ -0,0 +1,70 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/panel/samsung,s6d7aa0.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Samsung S6D7AA0 MIPI-DSI LCD panel controller
8+
9+maintainers:
10+ - Artur Weber <aweber.kernel@gmail.com>
11+
12+allOf:
13+ - $ref: panel-common.yaml#
14+
15+properties:
16+ compatible:
17+ items:
18+ - enum:
19+ # 1280x800 LSL080AL02 panel
20+ - samsung,lsl080al02
21+ # 1024x768 LSL080AL03 panel
22+ - samsung,lsl080al03
23+ # 1024x768 LTL101AT01 panel
24+ - samsung,ltl101at01
25+ - const: samsung,s6d7aa0
26+
27+ reg: true
28+
29+ backlight:
30+ description:
31+ Backlight to use for the panel. If this property is set on panels
32+ that have DSI-based backlight control (LSL080AL03 and LTL101AT01),
33+ it overrides the DSI-based backlight.
34+
35+ reset-gpios:
36+ description: Reset GPIO pin, usually GPIO_ACTIVE_LOW.
37+
38+ power-supply:
39+ description:
40+ Main power supply for the panel; the exact voltage differs between
41+ panels, and is usually somewhere around 3.3-5v.
42+
43+ vmipi-supply:
44+ description: VMIPI supply, usually 1.8v.
45+
46+required:
47+ - compatible
48+ - reg
49+ - reset-gpios
50+
51+additionalProperties: false
52+
53+examples:
54+ - |
55+ #include <dt-bindings/gpio/gpio.h>
56+
57+ dsi {
58+ #address-cells = <1>;
59+ #size-cells = <0>;
60+
61+ panel@0 {
62+ compatible = "samsung,lsl080al02", "samsung,s6d7aa0";
63+ reg = <0>;
64+ power-supply = <&display_3v3_supply>;
65+ reset-gpios = <&gpf0 4 GPIO_ACTIVE_LOW>;
66+ backlight = <&backlight>;
67+ };
68+ };
69+
70+...
Documentation/devicetree/bindings/media/i2c/ovti,ov2685.yaml+1−0
@@ -49,6 +49,7 @@ properties: · 48 unmodified lines
4949
5050 properties:
5151 data-lanes:
52+ minItems: 1
5253 maxItems: 2
5354
5455 required:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml+2−11
@@ -17,20 +17,11 @@ description: · 16 unmodified lines
1717 properties:
1818 clocks:
1919 minItems: 3
20− items:
21− - description: PCIe bridge clock.
22− - description: PCIe bus clock.
23− - description: PCIe PHY clock.
24− - description: Additional required clock entry for imx6sx-pcie,
25− imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
20+ maxItems: 4
2621
2722 clock-names:
2823 minItems: 3
29− items:
30− - const: pcie
31− - const: pcie_bus
32− - enum: [ pcie_phy, pcie_aux ]
33− - enum: [ pcie_inbound_axi, pcie_aux ]
24+ maxItems: 4
3425
3526 num-lanes:
3627 const: 1
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml+38−0
@@ -31,6 +31,19 @@ properties: · 30 unmodified lines
3131 - const: dbi
3232 - const: addr_space
3333
34+ clocks:
35+ minItems: 3
36+ items:
37+ - description: PCIe bridge clock.
38+ - description: PCIe bus clock.
39+ - description: PCIe PHY clock.
40+ - description: Additional required clock entry for imx6sx-pcie,
41+ imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
42+
43+ clock-names:
44+ minItems: 3
45+ maxItems: 4
46+
3447 interrupts:
3548 items:
3649 - description: builtin eDMA interrupter.
@@ -49,6 +62,31 @@ required: · 12 unmodified lines
4962 allOf:
5063 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
5164 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
65+ - if:
66+ properties:
67+ compatible:
68+ enum:
69+ - fsl,imx8mq-pcie-ep
70+ then:
71+ properties:
72+ clocks:
73+ minItems: 4
74+ clock-names:
75+ items:
76+ - const: pcie
77+ - const: pcie_bus
78+ - const: pcie_phy
79+ - const: pcie_aux
80+ else:
81+ properties:
82+ clocks:
83+ maxItems: 3
84+ clock-names:
85+ items:
86+ - const: pcie
87+ - const: pcie_bus
88+ - const: pcie_aux
89+
5290
5391 unevaluatedProperties: false
5492
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml+77−0
@@ -40,6 +40,19 @@ properties: · 39 unmodified lines
4040 - const: dbi
4141 - const: config
4242
43+ clocks:
44+ minItems: 3
45+ items:
46+ - description: PCIe bridge clock.
47+ - description: PCIe bus clock.
48+ - description: PCIe PHY clock.
49+ - description: Additional required clock entry for imx6sx-pcie,
50+ imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
51+
52+ clock-names:
53+ minItems: 3
54+ maxItems: 4
55+
4356 interrupts:
4457 items:
4558 - description: builtin MSI controller.
@@ -77,6 +90,70 @@ required: · 31 unmodified lines
7790 allOf:
7891 - $ref: /schemas/pci/snps,dw-pcie.yaml#
7992 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
93+ - if:
94+ properties:
95+ compatible:
96+ enum:
97+ - fsl,imx6sx-pcie
98+ then:
99+ properties:
100+ clocks:
101+ minItems: 4
102+ clock-names:
103+ items:
104+ - const: pcie
105+ - const: pcie_bus
106+ - const: pcie_phy
107+ - const: pcie_inbound_axi
108+
109+ - if:
110+ properties:
111+ compatible:
112+ enum:
113+ - fsl,imx8mq-pcie
114+ then:
115+ properties:
116+ clocks:
117+ minItems: 4
118+ clock-names:
119+ items:
120+ - const: pcie
121+ - const: pcie_bus
122+ - const: pcie_phy
123+ - const: pcie_aux
124+
125+ - if:
126+ properties:
127+ compatible:
128+ enum:
129+ - fsl,imx6q-pcie
130+ - fsl,imx6qp-pcie
131+ - fsl,imx7d-pcie
132+ then:
133+ properties:
134+ clocks:
135+ maxItems: 3
136+ clock-names:
137+ items:
138+ - const: pcie
139+ - const: pcie_bus
140+ - const: pcie_phy
141+
142+ - if:
143+ properties:
144+ compatible:
145+ enum:
146+ - fsl,imx8mm-pcie
147+ - fsl,imx8mp-pcie
148+ then:
149+ properties:
150+ clocks:
151+ maxItems: 3
152+ clock-names:
153+ items:
154+ - const: pcie
155+ - const: pcie_bus
156+ - const: pcie_aux
80157
81158 unevaluatedProperties: false
82159
Documentation/gpu/rfc/index.rst+4−0
@@ -31,3 +31,7 @@ host such documentation: · 30 unmodified lines
3131 .. toctree::
3232
3333 i915_vm_bind.rst
34+
35+.. toctree::
36+
37+ xe.rst
Documentation/gpu/rfc/xe.rst+235−0
@@ -0,0 +1,235 @@
1+==========================
2+Xe – Merge Acceptance Plan
3+==========================
4+Xe is a new driver for Intel GPUs that supports both integrated and
5+discrete platforms starting with Tiger Lake (first Intel Xe Architecture).
6+
7+This document aims to establish a merge plan for the Xe, by writing down clear
8+pre-merge goals, in order to avoid unnecessary delays.
9+
10+Xe – Overview
11+=============
12+The main motivation of Xe is to have a fresh base to work from that is
13+unencumbered by older platforms, whilst also taking the opportunity to
14+rearchitect our driver to increase sharing across the drm subsystem, both
15+leveraging and allowing us to contribute more towards other shared components
16+like TTM and drm/scheduler.
17+
18+This is also an opportunity to start from the beginning with a clean uAPI that is
19+extensible by design and already aligned with the modern userspace needs. For
20+this reason, the memory model is solely based on GPU Virtual Address space
21+bind/unbind (‘VM_BIND’) of GEM buffer objects (BOs) and execution only supporting
22+explicit synchronization. With persistent mapping across the execution, the
23+userspace does not need to provide a list of all required mappings during each
24+submission.
25+
26+The new driver leverages a lot from i915. As for display, the intent is to share
27+the display code with the i915 driver so that there is maximum reuse there.
28+
29+As for the power management area, the goal is to have a much-simplified support
30+for the system suspend states (S-states), PCI device suspend states (D-states),
31+GPU/Render suspend states (R-states) and frequency management. It should leverage
32+as much as possible all the existent PCI-subsystem infrastructure (pm and
33+runtime_pm) and underlying firmware components such PCODE and GuC for the power
34+states and frequency decisions.
35+
36+Repository:
37+
38+https://gitlab.freedesktop.org/drm/xe/kernel (branch drm-xe-next)
39+
40+Xe – Platforms
41+==============
42+Currently, Xe is already functional and has experimental support for multiple
43+platforms starting from Tiger Lake, with initial support in userspace implemented
44+in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO
45+(for OpenCL and Level0).
46+
47+During a transition period, platforms will be supported by both Xe and i915.
48+However, the force_probe mechanism existent in both drivers will allow only one
49+official and by-default probe at a given time.
50+
51+For instance, in order to probe a DG2 which PCI ID is 0x5690 by Xe instead of
52+i915, the following set of parameters need to be used:
53+
54+```
55+i915.force_probe=!5690 xe.force_probe=5690
56+```
57+
58+In both drivers, the ‘.require_force_probe’ protection forces the user to use the
59+force_probe parameter while the driver is under development. This protection is
60+only removed when the support for the platform and the uAPI are stable. Stability
61+which needs to be demonstrated by CI results.
62+
63+In order to avoid user space regressions, i915 will continue to support all the
64+current platforms that are already out of this protection. Xe support will be
65+forever experimental and dependent on the usage of force_probe for these
66+platforms.
67+
68+When the time comes for Xe, the protection will be lifted on Xe and kept in i915.
69+
70+Xe driver will be protected with both STAGING Kconfig and force_probe. Changes in
71+the uAPI are expected while the driver is behind these protections. STAGING will
72+be removed when the driver uAPI gets to a mature state where we can guarantee the
73+‘no regression’ rule. Then force_probe will be lifted only for future platforms
74+that will be productized with Xe driver, but not with i915.
75+
76+Xe – Pre-Merge Goals
77+====================
78+
79+Drm_scheduler
80+-------------
81+Xe primarily uses Firmware based scheduling (GuC FW). However, it will use
82+drm_scheduler as the scheduler ‘frontend’ for userspace submission in order to
83+resolve syncobj and dma-buf implicit sync dependencies. However, drm_scheduler is
84+not yet prepared to handle the 1-to-1 relationship between drm_gpu_scheduler and
85+drm_sched_entity.
86+
87+Deeper changes to drm_scheduler should *not* be required to get Xe accepted, but
88+some consensus needs to be reached between Xe and other community drivers that
89+could also benefit from this work, for coupling FW based/assisted submission such
90+as the ARM’s new Mali GPU driver, and others.
91+
92+As a key measurable result, the patch series introducing Xe itself shall not
93+depend on any other patch touching drm_scheduler itself that was not yet merged
94+through drm-misc. This, by itself, already includes the reach of an agreement for
95+uniform 1 to 1 relationship implementation / usage across drivers.
96+
97+GPU VA
98+------
99+Two main goals of Xe are meeting together here:
100+
101+1) Have an uAPI that aligns with modern UMD needs.
102+
103+2) Early upstream engagement.
104+
105+RedHat engineers working on Nouveau proposed a new DRM feature to handle keeping
106+track of GPU virtual address mappings. This is still not merged upstream, but
107+this aligns very well with our goals and with our VM_BIND. The engagement with
108+upstream and the port of Xe towards GPUVA is already ongoing.
109+
110+As a key measurable result, Xe needs to be aligned with the GPU VA and working in
111+our tree. Missing Nouveau patches should *not* block Xe and any needed GPUVA
112+related patch should be independent and present on dri-devel or acked by
113+maintainers to go along with the first Xe pull request towards drm-next.
114+
115+DRM_VM_BIND
116+-----------
117+Nouveau, and Xe are all implementing ‘VM_BIND’ and new ‘Exec’ uAPIs in order to
118+fulfill the needs of the modern uAPI. Xe merge should *not* be blocked on the
119+development of a common new drm_infrastructure. However, the Xe team needs to
120+engage with the community to explore the options of a common API.
121+
122+As a key measurable result, the DRM_VM_BIND needs to be documented in this file
123+below, or this entire block deleted if the consensus is for independent drivers
124+vm_bind ioctls.
125+
126+Although having a common DRM level IOCTL for VM_BIND is not a requirement to get
127+Xe merged, it is mandatory to enforce the overall locking scheme for all major
128+structs and list (so vm and vma). So, a consensus is needed, and possibly some
129+common helpers. If helpers are needed, they should be also documented in this
130+document.
131+
132+ASYNC VM_BIND
133+-------------
134+Although having a common DRM level IOCTL for VM_BIND is not a requirement to get
135+Xe merged, it is mandatory to have a consensus with other drivers and Mesa.
136+It needs to be clear how to handle async VM_BIND and interactions with userspace
137+memory fences. Ideally with helper support so people don't get it wrong in all
138+possible ways.
139+
140+As a key measurable result, the benefits of ASYNC VM_BIND and a discussion of
141+various flavors, error handling and a sample API should be documented here or in
142+a separate document pointed to by this document.
143+
144+Userptr integration and vm_bind
145+-------------------------------
146+Different drivers implement different ways of dealing with execution of userptr.
147+With multiple drivers currently introducing support to VM_BIND, the goal is to
148+aim for a DRM consensus on what’s the best way to have that support. To some
149+extent this is already getting addressed itself with the GPUVA where likely the
150+userptr will be a GPUVA with a NULL GEM call VM bind directly on the userptr.
151+However, there are more aspects around the rules for that and the usage of
152+mmu_notifiers, locking and other aspects.
153+
154+This task here has the goal of introducing a documentation of the basic rules.
155+
156+The documentation *needs* to first live in this document (API session below) and
157+then moved to another more specific document or at Xe level or at DRM level.
158+
159+Documentation should include:
160+
161+ * The userptr part of the VM_BIND api.
162+
163+ * Locking, including the page-faulting case.
164+
165+ * O(1) complexity under VM_BIND.
166+
167+Some parts of userptr like mmu_notifiers should become GPUVA or DRM helpers when
168+the second driver supporting VM_BIND+userptr appears. Details to be defined when
169+the time comes.
170+
171+Long running compute: minimal data structure/scaffolding
172+--------------------------------------------------------
173+The generic scheduler code needs to include the handling of endless compute
174+contexts, with the minimal scaffolding for preempt-ctx fences (probably on the
175+drm_sched_entity) and making sure drm_scheduler can cope with the lack of job
176+completion fence.
177+
178+The goal is to achieve a consensus ahead of Xe initial pull-request, ideally with
179+this minimal drm/scheduler work, if needed, merged to drm-misc in a way that any
180+drm driver, including Xe, could re-use and add their own individual needs on top
181+in a next stage. However, this should not block the initial merge.
182+
183+This is a non-blocker item since the driver without the support for the long
184+running compute enabled is not a showstopper.
185+
186+Display integration with i915
187+-----------------------------
188+In order to share the display code with the i915 driver so that there is maximum
189+reuse, the i915/display/ code is built twice, once for i915.ko and then for
190+xe.ko. Currently, the i915/display code in Xe tree is polluted with many 'ifdefs'
191+depending on the build target. The goal is to refactor both Xe and i915/display
192+code simultaneously in order to get a clean result before they land upstream, so
193+that display can already be part of the initial pull request towards drm-next.
194+
195+However, display code should not gate the acceptance of Xe in upstream. Xe
196+patches will be refactored in a way that display code can be removed, if needed,
197+from the first pull request of Xe towards drm-next. The expectation is that when
198+both drivers are part of the drm-tip, the introduction of cleaner patches will be
199+easier and speed up.
200+
201+Drm_exec
202+--------
203+Helper to make dma_resv locking for a big number of buffers is getting removed in
204+the drm_exec series proposed in https://patchwork.freedesktop.org/patch/524376/
205+If that happens, Xe needs to change and incorporate the changes in the driver.
206+The goal is to engage with the Community to understand if the best approach is to
207+move that to the drivers that are using it or if we should keep the helpers in
208+place waiting for Xe to get merged.
209+
210+This item ties into the GPUVA, VM_BIND, and even long-running compute support.
211+
212+As a key measurable result, we need to have a community consensus documented in
213+this document and the Xe driver prepared for the changes, if necessary.
214+
215+Dev_coredump
216+------------
217+
218+Xe needs to align with other drivers on the way that the error states are
219+dumped, avoiding a Xe only error_state solution. The goal is to use devcoredump
220+infrastructure to report error states, since it produces a standardized way
221+by exposing a virtual and temporary /sys/class/devcoredump device.
222+
223+As the key measurable result, Xe driver needs to provide GPU snapshots captured
224+at hang time through devcoredump, but without depending on any core modification
225+of devcoredump infrastructure itself.
226+
227+Later, when we are in-tree, the goal is to collaborate with devcoredump
228+infrastructure with overall possible improvements, like multiple file support
229+for better organization of the dumps, snapshot support, dmesg extra print,
230+and whatever may make sense and help the overall infrastructure.
231+
232+Xe – uAPI high level overview
233+=============================
234+
235+...Warning: To be done in follow up patches after/when/where the main consensus in various items are individually reached.
Documentation/gpu/todo.rst+2−5
@@ -276,11 +276,8 @@ Various hold-ups: · 275 unmodified lines
276276 - Need to switch to drm_fbdev_generic_setup(), otherwise a lot of the custom fb
277277 setup code can't be deleted.
278278
279−- Many drivers wrap drm_gem_fb_create() only to check for valid formats. For
280− atomic drivers we could check for valid formats by calling
281− drm_plane_check_pixel_format() against all planes, and pass if any plane
282− supports the format. For non-atomic that's not possible since like the format
283− list for the primary plane is fake and we'd therefor reject valid formats.
279+- Need to switch to drm_gem_fb_create(), as now drm_gem_fb_create() checks for
280+ valid formats for atomic drivers.
284281
285282 - Many drivers subclass drm_framebuffer, we'd need a embedding compatible
286283 version of the varios drm_gem_fb_create functions. Maybe called
Documentation/gpu/vkms.rst+1−6
@@ -118,14 +118,9 @@ Add Plane Features · 117 unmodified lines
118118
119119 There's lots of plane features we could add support for:
120120
121−- ARGB format on primary plane: blend the primary plane into background with
122− translucent alpha.
123−
124121 - Add background color KMS property[Good to get started].
125122
126−- Full alpha blending on all planes.
127−
128−- Rotation, scaling.
123+- Scaling.
129124
130125 - Additional buffer formats, especially YUV formats for video like NV12.
131126 Low/high bpp RGB formats would also be interesting.
Documentation/networking/bonding.rst+5−4
@@ -776,10 +776,11 @@ peer_notif_delay · 775 unmodified lines
776776 Specify the delay, in milliseconds, between each peer
777777 notification (gratuitous ARP and unsolicited IPv6 Neighbor
778778 Advertisement) when they are issued after a failover event.
779− This delay should be a multiple of the link monitor interval
780− (arp_interval or miimon, whichever is active). The default
781− value is 0 which means to match the value of the link monitor
782− interval.
779+ This delay should be a multiple of the MII link monitor interval
780+ (miimon).
781+
782+ The valid range is 0 - 300000. The default value is 0, which means
783+ to match the value of the MII link monitor interval.
783784
784785 prio
785786 Slave priority. A higher number means higher priority.
Documentation/networking/index.rst+1−1
@@ -116,8 +116,8 @@ Contents: · 115 unmodified lines
116116 udplite
117117 vrf
118118 vxlan
119− x25-iface
120119 x25
120+ x25-iface
121121 xfrm_device
122122 xfrm_proc
123123 xfrm_sync
Documentation/networking/x25-iface.rst+1−2
@@ -1,8 +1,7 @@
11 .. SPDX-License-Identifier: GPL-2.0
22
3−============================-
43 X.25 Device Driver Interface
5−============================-
4+============================
65
76 Version 1.1
87
MAINTAINERS+1156−1148
@@ -273,8 +273,8 @@ ABI/API · 272 unmodified lines
273273 L: linux-api@vger.kernel.org
274274 F: include/linux/syscalls.h
275275 F: kernel/sys_ni.c
276−X: include/uapi/
277276 X: arch/*/include/uapi/
277+X: include/uapi/
278278
279279 ABIT UGURU 1,2 HARDWARE MONITOR DRIVER
280280 M: Hans de Goede <hdegoede@redhat.com>
@@ -406,12 +406,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 125 unmodified lines
406406 S: Maintained
407407 F: drivers/acpi/arm64
408408
409−ACPI SERIAL MULTI INSTANTIATE DRIVER
410−M: Hans de Goede <hdegoede@redhat.com>
411−L: platform-driver-x86@vger.kernel.org
412−S: Maintained
413−F: drivers/platform/x86/serial-multi-instantiate.c
414−
415409 ACPI PCC(Platform Communication Channel) MAILBOX DRIVER
416410 M: Sudeep Holla <sudeep.holla@arm.com>
417411 L: linux-acpi@vger.kernel.org
@@ -430,6 +424,12 @@ B: https://bugzilla.kernel.org · 12 unmodified lines
430424 T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
431425 F: drivers/acpi/pmic/
432426
427+ACPI SERIAL MULTI INSTANTIATE DRIVER
428+M: Hans de Goede <hdegoede@redhat.com>
429+L: platform-driver-x86@vger.kernel.org
430+S: Maintained
431+F: drivers/platform/x86/serial-multi-instantiate.c
432+
433433 ACPI THERMAL DRIVER
434434 M: Rafael J. Wysocki <rafael@kernel.org>
435435 R: Zhang Rui <rui.zhang@intel.com>
@@ -823,6 +823,13 @@ L: linux-crypto@vger.kernel.org · 387 unmodified lines
823823 S: Maintained
824824 F: drivers/crypto/allwinner/
825825
826+ALLWINNER DMIC DRIVERS
827+M: Ban Tao <fengzheng923@gmail.com>
828+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
829+S: Maintained
830+F: Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
831+F: sound/soc/sunxi/sun50i-dmic.c
832+
826833 ALLWINNER HARDWARE SPINLOCK SUPPORT
827834 M: Wilken Gottwalt <wilken.gottwalt@posteo.net>
828835 S: Maintained
@@ -844,13 +851,6 @@ L: linux-media@vger.kernel.org · 15 unmodified lines
844851 S: Maintained
845852 F: drivers/staging/media/sunxi/cedrus/
846853
847−ALLWINNER DMIC DRIVERS
848−M: Ban Tao <fengzheng923@gmail.com>
849−L: alsa-devel@alsa-project.org (moderated for non-subscribers)
850−S: Maintained
851−F: Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
852−F: sound/soc/sunxi/sun50i-dmic.c
853−
854854 ALPHA PORT
855855 M: Richard Henderson <richard.henderson@linaro.org>
856856 M: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
@@ -1026,6 +1026,16 @@ F: drivers/char/hw_random/geode-rng.c · 169 unmodified lines
10261026 F: drivers/crypto/geode*
10271027 F: drivers/video/fbdev/geode/
10281028
1029+AMD HSMP DRIVER
1030+M: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
1031+R: Carlos Bilbao <carlos.bilbao@amd.com>
1032+L: platform-driver-x86@vger.kernel.org
1033+S: Maintained
1034+F: Documentation/arch/x86/amd_hsmp.rst
1035+F: arch/x86/include/asm/amd_hsmp.h
1036+F: arch/x86/include/uapi/asm/amd_hsmp.h
1037+F: drivers/platform/x86/amd/hsmp.c
1038+
10291039 AMD IOMMU (AMD-VI)
10301040 M: Joerg Roedel <joro@8bytes.org>
10311041 R: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
@@ -1049,6 +1059,13 @@ F: drivers/gpu/drm/amd/include/vi_structs.h · 17 unmodified lines
10491059 F: include/uapi/linux/kfd_ioctl.h
10501060 F: include/uapi/linux/kfd_sysfs.h
10511061
1062+AMD MP2 I2C DRIVER
1063+M: Elie Morisse <syniurge@gmail.com>
1064+M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
1065+L: linux-i2c@vger.kernel.org
1066+S: Maintained
1067+F: drivers/i2c/busses/i2c-amd-mp2*
1068+
10521069 AMD PDS CORE DRIVER
10531070 M: Shannon Nelson <shannon.nelson@amd.com>
10541071 M: Brett Creeley <brett.creeley@amd.com>
@@ -1058,18 +1075,6 @@ F: Documentation/networking/device_drivers/ethernet/amd/pds_core.rst · 3 unmodified lines
10581075 F: drivers/net/ethernet/amd/pds_core/
10591076 F: include/linux/pds/
10601077
1061−AMD SPI DRIVER
1062−M: Sanjay R Mehta <sanju.mehta@amd.com>
1063−S: Maintained
1064−F: drivers/spi/spi-amd.c
1065−
1066−AMD MP2 I2C DRIVER
1067−M: Elie Morisse <syniurge@gmail.com>
1068−M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
1069−L: linux-i2c@vger.kernel.org
1070−S: Maintained
1071−F: drivers/i2c/busses/i2c-amd-mp2*
1072−
10731078 AMD PMC DRIVER
10741079 M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
10751080 L: platform-driver-x86@vger.kernel.org
@@ -1083,16 +1088,6 @@ S: Maintained · 7 unmodified lines
10831088 F: Documentation/ABI/testing/sysfs-amd-pmf
10841089 F: drivers/platform/x86/amd/pmf/
10851090
1086−AMD HSMP DRIVER
1087−M: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
1088−R: Carlos Bilbao <carlos.bilbao@amd.com>
1089−L: platform-driver-x86@vger.kernel.org
1090−S: Maintained
1091−F: Documentation/arch/x86/amd_hsmp.rst
1092−F: arch/x86/include/asm/amd_hsmp.h
1093−F: arch/x86/include/uapi/asm/amd_hsmp.h
1094−F: drivers/platform/x86/amd/hsmp.c
1095−
10961091 AMD POWERPLAY AND SWSMU
10971092 M: Evan Quan <evan.quan@amd.com>
10981093 L: amd-gfx@lists.freedesktop.org
@@ -1121,13 +1116,6 @@ M: Tom Lendacky <thomas.lendacky@amd.com> · 22 unmodified lines
11211116 S: Supported
11221117 F: arch/arm64/boot/dts/amd/
11231118
1124−AMD XGBE DRIVER
1125−M: "Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
1126−L: netdev@vger.kernel.org
1127−S: Supported
1128−F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
1129−F: drivers/net/ethernet/amd/xgbe/
1130−
11311119 AMD SENSOR FUSION HUB DRIVER
11321120 M: Basavaraj Natikar <basavaraj.natikar@amd.com>
11331121 L: linux-input@vger.kernel.org
@@ -1135,6 +1123,18 @@ S: Maintained · 1 unmodified line
11351123 F: Documentation/hid/amd-sfh*
11361124 F: drivers/hid/amd-sfh-hid/
11371125
1126+AMD SPI DRIVER
1127+M: Sanjay R Mehta <sanju.mehta@amd.com>
1128+S: Maintained
1129+F: drivers/spi/spi-amd.c
1130+
1131+AMD XGBE DRIVER
1132+M: "Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
1133+L: netdev@vger.kernel.org
1134+S: Supported
1135+F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
1136+F: drivers/net/ethernet/amd/xgbe/
1137+
11381138 AMLOGIC DDR PMU DRIVER
11391139 M: Jiucheng Xu <jiucheng.xu@amlogic.com>
11401140 L: linux-amlogic@lists.infradead.org
@@ -1169,6 +1169,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git · 28 unmodified lines
11691169 T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
11701170 F: drivers/net/amt.c
11711171
1172+ANALOG DEVICES INC AD3552R DRIVER
1173+M: Nuno Sá <nuno.sa@analog.com>
1174+L: linux-iio@vger.kernel.org
1175+S: Supported
1176+W: https://ez.analog.com/linux-software-drivers
1177+F: Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
1178+F: drivers/iio/dac/ad3552r.c
1179+
11721180 ANALOG DEVICES INC AD4130 DRIVER
11731181 M: Cosmin Tanislav <cosmin.tanislav@analog.com>
11741182 L: linux-iio@vger.kernel.org
@@ -1194,14 +1202,6 @@ W: https://ez.analog.com/linux-software-drivers · 19 unmodified lines
11941202 F: Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml
11951203 F: drivers/iio/adc/ad7292.c
11961204
1197−ANALOG DEVICES INC AD3552R DRIVER
1198−M: Nuno Sá <nuno.sa@analog.com>
1199−L: linux-iio@vger.kernel.org
1200−S: Supported
1201−W: https://ez.analog.com/linux-software-drivers
1202−F: Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
1203−F: drivers/iio/dac/ad3552r.c
1204−
12051205 ANALOG DEVICES INC AD7293 DRIVER
12061206 M: Antoniu Miclaus <antoniu.miclaus@analog.com>
12071207 L: linux-iio@vger.kernel.org
@@ -1210,23 +1210,6 @@ W: https://ez.analog.com/linux-software-drivers · 2 unmodified lines
12101210 F: Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml
12111211 F: drivers/iio/dac/ad7293.c
12121212
1213−ANALOG DEVICES INC AD7768-1 DRIVER
1214−M: Michael Hennerich <Michael.Hennerich@analog.com>
1215−L: linux-iio@vger.kernel.org
1216−S: Supported
1217−W: https://ez.analog.com/linux-software-drivers
1218−F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
1219−F: drivers/iio/adc/ad7768-1.c
1220−
1221−ANALOG DEVICES INC AD7780 DRIVER
1222−M: Michael Hennerich <Michael.Hennerich@analog.com>
1223−M: Renato Lui Geh <renatogeh@gmail.com>
1224−L: linux-iio@vger.kernel.org
1225−S: Supported
1226−W: https://ez.analog.com/linux-software-drivers
1227−F: Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
1228−F: drivers/iio/adc/ad7780.c
1229−
12301213 ANALOG DEVICES INC AD74115 DRIVER
12311214 M: Cosmin Tanislav <cosmin.tanislav@analog.com>
12321215 L: linux-iio@vger.kernel.org
@@ -1244,6 +1227,23 @@ F: Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml · 11 unmodified lines
12441227 F: drivers/iio/addac/ad74413r.c
12451228 F: include/dt-bindings/iio/addac/adi,ad74413r.h
12461229
1230+ANALOG DEVICES INC AD7768-1 DRIVER
1231+M: Michael Hennerich <Michael.Hennerich@analog.com>
1232+L: linux-iio@vger.kernel.org
1233+S: Supported
1234+W: https://ez.analog.com/linux-software-drivers
1235+F: Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
1236+F: drivers/iio/adc/ad7768-1.c
1237+
1238+ANALOG DEVICES INC AD7780 DRIVER
1239+M: Michael Hennerich <Michael.Hennerich@analog.com>
1240+M: Renato Lui Geh <renatogeh@gmail.com>
1241+L: linux-iio@vger.kernel.org
1242+S: Supported
1243+W: https://ez.analog.com/linux-software-drivers
1244+F: Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
1245+F: drivers/iio/adc/ad7780.c
1246+
12471247 ANALOG DEVICES INC ADA4250 DRIVER
12481248 M: Antoniu Miclaus <antoniu.miclaus@analog.com>
12491249 L: linux-iio@vger.kernel.org
@@ -1294,10 +1294,10 @@ F: drivers/iio/imu/adis16460.c · 44 unmodified lines
12941294 ANALOG DEVICES INC ADIS16475 DRIVER
12951295 M: Nuno Sa <nuno.sa@analog.com>
12961296 L: linux-iio@vger.kernel.org
1297−W: https://ez.analog.com/linux-software-drivers
12981297 S: Supported
1299−F: drivers/iio/imu/adis16475.c
1298+W: https://ez.analog.com/linux-software-drivers
13001299 F: Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml
1300+F: drivers/iio/imu/adis16475.c
13011301
13021302 ANALOG DEVICES INC ADM1177 DRIVER
13031303 M: Michael Hennerich <Michael.Hennerich@analog.com>
@@ -1315,21 +1315,21 @@ W: https://ez.analog.com/linux-software-drivers · 11 unmodified lines
13151315 F: Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml
13161316 F: drivers/iio/frequency/admv1013.c
13171317
1318−ANALOG DEVICES INC ADMV8818 DRIVER
1318+ANALOG DEVICES INC ADMV1014 DRIVER
13191319 M: Antoniu Miclaus <antoniu.miclaus@analog.com>
13201320 L: linux-iio@vger.kernel.org
13211321 S: Supported
13221322 W: https://ez.analog.com/linux-software-drivers
1323−F: Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml
1324−F: drivers/iio/filter/admv8818.c
1323+F: Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
1324+F: drivers/iio/frequency/admv1014.c
13251325
1326−ANALOG DEVICES INC ADMV1014 DRIVER
1326+ANALOG DEVICES INC ADMV8818 DRIVER
13271327 M: Antoniu Miclaus <antoniu.miclaus@analog.com>
13281328 L: linux-iio@vger.kernel.org
13291329 S: Supported
13301330 W: https://ez.analog.com/linux-software-drivers
1331−F: Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
1332−F: drivers/iio/frequency/admv1014.c
1331+F: Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml
1332+F: drivers/iio/filter/admv8818.c
13331333
13341334 ANALOG DEVICES INC ADP5061 DRIVER
13351335 M: Michael Hennerich <Michael.Hennerich@analog.com>
@@ -1351,8 +1351,8 @@ M: Lars-Peter Clausen <lars@metafoo.de> · 15 unmodified lines
13511351 L: linux-media@vger.kernel.org
13521352 S: Supported
13531353 W: https://ez.analog.com/linux-software-drivers
1354−F: drivers/media/i2c/adv7180.c
13551354 F: Documentation/devicetree/bindings/media/i2c/adv7180.yaml
1355+F: drivers/media/i2c/adv7180.c
13561356
13571357 ANALOG DEVICES INC ADV748X DRIVER
13581358 M: Kieran Bingham <kieran.bingham@ideasonboard.com>
@@ -1371,8 +1371,8 @@ ANALOG DEVICES INC ADV7604 DRIVER · 12 unmodified lines
13711371 M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
13721372 L: linux-media@vger.kernel.org
13731373 S: Maintained
1374−F: drivers/media/i2c/adv7604*
13751374 F: Documentation/devicetree/bindings/media/i2c/adv7604.yaml
1375+F: drivers/media/i2c/adv7604*
13761376
13771377 ANALOG DEVICES INC ADV7842 DRIVER
13781378 M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
@@ -1384,8 +1384,8 @@ ANALOG DEVICES INC ADXRS290 DRIVER · 5 unmodified lines
13841384 M: Nishant Malpani <nish.malpani25@gmail.com>
13851385 L: linux-iio@vger.kernel.org
13861386 S: Supported
1387−F: drivers/iio/gyro/adxrs290.c
13881387 F: Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml
1388+F: drivers/iio/gyro/adxrs290.c
13891389
13901390 ANALOG DEVICES INC ASOC CODEC DRIVERS
13911391 M: Lars-Peter Clausen <lars@metafoo.de>
@@ -1625,6 +1625,17 @@ S: Maintained · 233 unmodified lines
16251625 F: drivers/net/arcnet/
16261626 F: include/uapi/linux/if_arcnet.h
16271627
1628+ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
1629+M: Arnd Bergmann <arnd@arndb.de>
1630+M: Olof Johansson <olof@lixom.net>
1631+M: soc@kernel.org
1632+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1633+S: Maintained
1634+C: irc://irc.libera.chat/armlinux
1635+T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
1636+F: arch/arm/boot/dts/Makefile
1637+F: arch/arm64/boot/dts/Makefile
1638+
16281639 ARM ARCHITECTED TIMER DRIVER
16291640 M: Mark Rutland <mark.rutland@arm.com>
16301641 M: Marc Zyngier <maz@kernel.org>
@@ -1738,22 +1749,6 @@ S: Odd Fixes · 107 unmodified lines
17381749 F: drivers/amba/
17391750 F: include/linux/amba/bus.h
17401751
1741−ARM PRIMECELL PL35X NAND CONTROLLER DRIVER
1742−M: Miquel Raynal <miquel.raynal@bootlin.com>
1743−M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1744−L: linux-mtd@lists.infradead.org
1745−S: Maintained
1746−F: Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
1747−F: drivers/mtd/nand/raw/pl35x-nand-controller.c
1748−
1749−ARM PRIMECELL PL35X SMC DRIVER
1750−M: Miquel Raynal <miquel.raynal@bootlin.com>
1751−M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1752−L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1753−S: Maintained
1754−F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
1755−F: drivers/memory/pl353-smc.c
1756−
17571752 ARM PRIMECELL CLCD PL110 DRIVER
17581753 M: Russell King <linux@armlinux.org.uk>
17591754 S: Odd Fixes
@@ -1771,6 +1766,22 @@ S: Odd Fixes · 11 unmodified lines
17711766 F: drivers/mmc/host/mmci.*
17721767 F: include/linux/amba/mmci.h
17731768
1769+ARM PRIMECELL PL35X NAND CONTROLLER DRIVER
1770+M: Miquel Raynal <miquel.raynal@bootlin.com>
1771+M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1772+L: linux-mtd@lists.infradead.org
1773+S: Maintained
1774+F: Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
1775+F: drivers/mtd/nand/raw/pl35x-nand-controller.c
1776+
1777+ARM PRIMECELL PL35X SMC DRIVER
1778+M: Miquel Raynal <miquel.raynal@bootlin.com>
1779+M: Naga Sureshkumar Relli <nagasure@xilinx.com>
1780+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1781+S: Maintained
1782+F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
1783+F: drivers/memory/pl353-smc.c
1784+
17741785 ARM PRIMECELL SSP PL022 SPI DRIVER
17751786 M: Linus Walleij <linus.walleij@linaro.org>
17761787 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1807,17 +1818,6 @@ F: Documentation/devicetree/bindings/iommu/arm,smmu* · 30 unmodified lines
18071818 F: drivers/iommu/arm/
18081819 F: drivers/iommu/io-pgtable-arm*
18091820
1810−ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
1811−M: Arnd Bergmann <arnd@arndb.de>
1812−M: Olof Johansson <olof@lixom.net>
1813−M: soc@kernel.org
1814−L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1815−S: Maintained
1816−C: irc://irc.libera.chat/armlinux
1817−T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
1818−F: arch/arm/boot/dts/Makefile
1819−F: arch/arm64/boot/dts/Makefile
1820−
18211821 ARM SUB-ARCHITECTURES
18221822 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
18231823 S: Maintained
@@ -1869,9 +1869,9 @@ M: Chen-Yu Tsai <wens@csie.org> · 45 unmodified lines
18691869 M: Jernej Skrabec <jernej.skrabec@gmail.com>
18701870 M: Samuel Holland <samuel@sholland.org>
18711871 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1872+L: linux-sunxi@lists.linux.dev
18721873 S: Maintained
18731874 T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
1874−L: linux-sunxi@lists.linux.dev
18751875 F: arch/arm/mach-sunxi/
18761876 F: arch/arm64/boot/dts/allwinner/
18771877 F: drivers/clk/sunxi-ng/
@@ -1934,6 +1934,15 @@ F: arch/arm/mach-alpine/ · 56 unmodified lines
19341934 F: arch/arm64/boot/dts/amazon/
19351935 F: drivers/*/*alpine*
19361936
1937+ARM/APPLE MACHINE SOUND DRIVERS
1938+M: Martin Povišer <povik+lin@cutebit.org>
1939+L: asahi@lists.linux.dev
1940+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
1941+S: Maintained
1942+F: Documentation/devicetree/bindings/sound/apple,*
1943+F: sound/soc/apple/*
1944+F: sound/soc/codecs/cs42l83-i2c.c
1945+
19371946 ARM/APPLE MACHINE SUPPORT
19381947 M: Hector Martin <marcan@marcan.st>
19391948 M: Sven Peter <sven@svenpeter.dev>
@@ -1961,7 +1970,7 @@ F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml · 21 unmodified lines
19611970 F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
19621971 F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
19631972 F: Documentation/devicetree/bindings/power/apple*
1964−F: Documentation/devicetree/bindings/pwm/pwm-apple.yaml
1973+F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
19651974 F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
19661975 F: arch/arm64/boot/dts/apple/
19671976 F: drivers/bluetooth/hci_bcm4377.c
@@ -1985,15 +1994,6 @@ F: include/dt-bindings/pinctrl/apple.h · 17 unmodified lines
19851994 F: include/linux/apple-mailbox.h
19861995 F: include/linux/soc/apple/*
19871996
1988−ARM/APPLE MACHINE SOUND DRIVERS
1989−M: Martin Povišer <povik+lin@cutebit.org>
1990−L: asahi@lists.linux.dev
1991−L: alsa-devel@alsa-project.org (moderated for non-subscribers)
1992−S: Maintained
1993−F: Documentation/devicetree/bindings/sound/apple,*
1994−F: sound/soc/apple/*
1995−F: sound/soc/codecs/cs42l83-i2c.c
1996−
19971997 ARM/ARTPEC MACHINE SUPPORT
19981998 M: Jesper Nilsson <jesper.nilsson@axis.com>
19991999 M: Lars Persson <lars.persson@axis.com>
@@ -2109,19 +2109,19 @@ S: Maintained · 109 unmodified lines
21092109 T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
21102110 F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
21112111 F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
2112−F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml
21132112 F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
21142113 F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
2114+F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml
21152115 F: Documentation/trace/coresight/*
21162116 F: drivers/hwtracing/coresight/*
21172117 F: include/dt-bindings/arm/coresight-cti-dt.h
21182118 F: include/linux/coresight*
21192119 F: samples/coresight/*
2120−F: tools/perf/tests/shell/coresight/*
21212120 F: tools/perf/arch/arm/util/auxtrace.c
21222121 F: tools/perf/arch/arm/util/cs-etm.c
21232122 F: tools/perf/arch/arm/util/cs-etm.h
21242123 F: tools/perf/arch/arm/util/pmu.c
2124+F: tools/perf/tests/shell/coresight/*
21252125 F: tools/perf/util/cs-etm-decoder/*
21262126 F: tools/perf/util/cs-etm.*
21272127
@@ -2156,9 +2156,9 @@ F: Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml · 28 unmodified lines
21562156 F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt
21572157 F: drivers/bus/moxtet.c
21582158 F: drivers/firmware/turris-mox-rwtm.c
2159+F: drivers/gpio/gpio-moxtet.c
21592160 F: drivers/leds/leds-turris-omnia.c
21602161 F: drivers/mailbox/armada-37xx-rwtm-mailbox.c
2161−F: drivers/gpio/gpio-moxtet.c
21622162 F: drivers/watchdog/armada_37xx_wdt.c
21632163 F: include/dt-bindings/bus/moxtet.h
21642164 F: include/linux/armada-37xx-rwtm-mailbox.h
@@ -2188,10 +2188,10 @@ R: NXP Linux Team <linux-imx@nxp.com> · 23 unmodified lines
21882188 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
21892189 S: Maintained
21902190 T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
2191−X: drivers/media/i2c/
21922191 F: arch/arm64/boot/dts/freescale/
21932192 X: arch/arm64/boot/dts/freescale/fsl-*
21942193 X: arch/arm64/boot/dts/freescale/qoriq-*
2194+X: drivers/media/i2c/
21952195 N: imx
21962196 N: mxs
21972197
@@ -2245,12 +2245,12 @@ ARM/HPE GXP ARCHITECTURE · 47 unmodified lines
22452245 M: Jean-Marie Verdun <verdun@hpe.com>
22462246 M: Nick Hawkins <nick.hawkins@hpe.com>
22472247 S: Maintained
2248−F: Documentation/hwmon/gxp-fan-ctrl.rst
22492248 F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
22502249 F: Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml
22512250 F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml
22522251 F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
22532252 F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
2253+F: Documentation/hwmon/gxp-fan-ctrl.rst
22542254 F: arch/arm/boot/dts/hpe-bmc*
22552255 F: arch/arm/boot/dts/hpe-gxp*
22562256 F: arch/arm/mach-hpe/
@@ -2275,9 +2275,9 @@ M: Krzysztof Halasa <khalasa@piap.pl> · 18 unmodified lines
22752275 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
22762276 S: Maintained
22772277 F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
2278−F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
22792278 F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
22802279 F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
2280+F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
22812281 F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
22822282 F: arch/arm/boot/dts/intel-ixp*
22832283 F: arch/arm/mach-ixp4xx/
@@ -2447,13 +2447,6 @@ F: drivers/net/ethernet/microchip/vcap/ · 163 unmodified lines
24472447 F: drivers/pinctrl/pinctrl-microchip-sgpio.c
24482448 N: sparx5
24492449
2450−Microchip Timer Counter Block (TCB) Capture Driver
2451−M: Kamel Bouhara <kamel.bouhara@bootlin.com>
2452−L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2453−L: linux-iio@vger.kernel.org
2454−S: Maintained
2455−F: drivers/counter/microchip-tcb-capture.c
2456−
24572450 ARM/MILBEAUT ARCHITECTURE
24582451 M: Taichi Sugaya <sugaya.taichi@socionext.com>
24592452 M: Takao Orito <orito.takao@socionext.com>
@@ -2525,8 +2518,8 @@ F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml · 65 unmodified lines
25252518 F: arch/arm/boot/dts/nuvoton-npcm*
25262519 F: arch/arm/mach-npcm/
25272520 F: arch/arm64/boot/dts/nuvoton/
2528−F: drivers/*/*npcm*
25292521 F: drivers/*/*/*npcm*
2522+F: drivers/*/*npcm*
25302523 F: drivers/rtc/rtc-nct3018y.c
25312524 F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
25322525 F: include/dt-bindings/clock/nuvoton,npcm845-clk.h
@@ -2569,9 +2562,15 @@ F: arch/arm/mach-oxnas/ · 36 unmodified lines
25692562 F: drivers/power/reset/oxnas-restart.c
25702563 N: oxnas
25712564
2572−ARM/QUALCOMM SUPPORT
2573−M: Andy Gross <agross@kernel.org>
2574−M: Bjorn Andersson <andersson@kernel.org>
2565+ARM/QUALCOMM CHROMEBOOK SUPPORT
2566+R: cros-qcom-dts-watchers@chromium.org
2567+F: arch/arm64/boot/dts/qcom/sc7180*
2568+F: arch/arm64/boot/dts/qcom/sc7280*
2569+F: arch/arm64/boot/dts/qcom/sdm845-cheza*
2570+
2571+ARM/QUALCOMM SUPPORT
2572+M: Andy Gross <agross@kernel.org>
2573+M: Bjorn Andersson <andersson@kernel.org>
25752574 R: Konrad Dybcio <konrad.dybcio@linaro.org>
25762575 L: linux-arm-msm@vger.kernel.org
25772576 S: Maintained
@@ -2602,22 +2601,16 @@ F: drivers/pci/controller/dwc/pcie-qcom.c · 24 unmodified lines
26022601 F: drivers/phy/qualcomm/
26032602 F: drivers/power/*/msm*
26042603 F: drivers/reset/reset-qcom-*
2605−F: drivers/ufs/host/ufs-qcom*
26062604 F: drivers/spi/spi-geni-qcom.c
26072605 F: drivers/spi/spi-qcom-qspi.c
26082606 F: drivers/spi/spi-qup.c
26092607 F: drivers/tty/serial/msm_serial.c
2608+F: drivers/ufs/host/ufs-qcom*
26102609 F: drivers/usb/dwc3/dwc3-qcom.c
26112610 F: include/dt-bindings/*/qcom*
26122611 F: include/linux/*/qcom*
26132612 F: include/linux/soc/qcom/
26142613
2615−ARM/QUALCOMM CHROMEBOOK SUPPORT
2616−R: cros-qcom-dts-watchers@chromium.org
2617−F: arch/arm64/boot/dts/qcom/sc7180*
2618−F: arch/arm64/boot/dts/qcom/sc7280*
2619−F: arch/arm64/boot/dts/qcom/sdm845-cheza*
2620−
26212614 ARM/RDA MICRO ARCHITECTURE
26222615 M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
26232616 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -2709,9 +2702,9 @@ R: Alim Akhtar <alim.akhtar@samsung.com> · 85 unmodified lines
27092702 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
27102703 L: linux-samsung-soc@vger.kernel.org
27112704 S: Maintained
2712−C: irc://irc.libera.chat/linux-exynos
27132705 Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
27142706 B: mailto:linux-samsung-soc@vger.kernel.org
2707+C: irc://irc.libera.chat/linux-exynos
27152708 T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
27162709 F: Documentation/arm/samsung/
27172710 F: Documentation/devicetree/bindings/arm/samsung/
@@ -2811,8 +2804,8 @@ M: Patrice Chotard <patrice.chotard@foss.st.com> · 93 unmodified lines
28112804 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
28122805 S: Maintained
28132806 W: http://www.stlinux.com
2814−F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml
28152807 F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml
2808+F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml
28162809 F: arch/arm/boot/dts/sti*
28172810 F: arch/arm/mach-sti/
28182811 F: drivers/ata/ahci_st.c
@@ -2959,15 +2952,15 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git · 140 unmodified lines
29592952 F: Documentation/devicetree/bindings/arm/toshiba.yaml
29602953 F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
29612954 F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
2962−F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
29632955 F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
2956+F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
29642957 F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
29652958 F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
29662959 F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
29672960 F: arch/arm64/boot/dts/toshiba/
29682961 F: drivers/clk/visconti/
2969−F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
29702962 F: drivers/gpio/gpio-visconti.c
2963+F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
29712964 F: drivers/pci/controller/dwc/pcie-visconti.c
29722965 F: drivers/pinctrl/visconti/
29732966 F: drivers/watchdog/visconti_wdt.c
@@ -3112,6 +3105,13 @@ S: Maintained · 138 unmodified lines
31123105 F: Documentation/devicetree/bindings/net/asix,ax88796c.yaml
31133106 F: drivers/net/ethernet/asix/ax88796c_*
31143107
3108+ASPEED CRYPTO DRIVER
3109+M: Neal Liu <neal_liu@aspeedtech.com>
3110+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3111+S: Maintained
3112+F: Documentation/devicetree/bindings/crypto/aspeed,*
3113+F: drivers/crypto/aspeed/
3114+
31153115 ASPEED PECI CONTROLLER
31163116 M: Iwona Winiarska <iwona.winiarska@intel.com>
31173117 L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
@@ -3156,6 +3156,13 @@ S: Maintained · 38 unmodified lines
31563156 F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
31573157 F: drivers/spi/spi-aspeed-smc.c
31583158
3159+ASPEED USB UDC DRIVER
3160+M: Neal Liu <neal_liu@aspeedtech.com>
3161+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3162+S: Maintained
3163+F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
3164+F: drivers/usb/gadget/udc/aspeed_udc.c
3165+
31593166 ASPEED VIDEO ENGINE DRIVER
31603167 M: Eddie James <eajames@linux.ibm.com>
31613168 L: linux-media@vger.kernel.org
@@ -3164,19 +3171,11 @@ S: Maintained · 2 unmodified lines
31643171 F: Documentation/devicetree/bindings/media/aspeed-video.txt
31653172 F: drivers/media/platform/aspeed/
31663173
3167−ASPEED USB UDC DRIVER
3168−M: Neal Liu <neal_liu@aspeedtech.com>
3169−L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3170−S: Maintained
3171−F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
3172−F: drivers/usb/gadget/udc/aspeed_udc.c
3173−
3174−ASPEED CRYPTO DRIVER
3175−M: Neal Liu <neal_liu@aspeedtech.com>
3176−L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3174+ASUS EC HARDWARE MONITOR DRIVER
3175+M: Eugene Shalygin <eugene.shalygin@gmail.com>
3176+L: linux-hwmon@vger.kernel.org
31773177 S: Maintained
3178−F: Documentation/devicetree/bindings/crypto/aspeed,*
3179−F: drivers/crypto/aspeed/
3178+F: drivers/hwmon/asus-ec-sensors.c
31803179
31813180 ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
31823181 M: Corentin Chary <corentin.chary@gmail.com>
@@ -3194,6 +3193,12 @@ S: Maintained · 11 unmodified lines
31943193 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
31953194 F: drivers/platform/x86/asus-tf103c-dock.c
31963195
3196+ASUS WIRELESS RADIO CONTROL DRIVER
3197+M: João Paulo Rechi Vita <jprvita@gmail.com>
3198+L: platform-driver-x86@vger.kernel.org
3199+S: Maintained
3200+F: drivers/platform/x86/asus-wireless.c
3201+
31973202 ASUS WMI HARDWARE MONITOR DRIVER
31983203 M: Ed Brindley <kernel@maidavale.org>
31993204 M: Denis Pauk <pauk.denis@gmail.com>
@@ -3201,18 +3206,6 @@ L: linux-hwmon@vger.kernel.org · 1 unmodified line
32013206 S: Maintained
32023207 F: drivers/hwmon/asus_wmi_sensors.c
32033208
3204−ASUS EC HARDWARE MONITOR DRIVER
3205−M: Eugene Shalygin <eugene.shalygin@gmail.com>
3206−L: linux-hwmon@vger.kernel.org
3207−S: Maintained
3208−F: drivers/hwmon/asus-ec-sensors.c
3209−
3210−ASUS WIRELESS RADIO CONTROL DRIVER
3211−M: João Paulo Rechi Vita <jprvita@gmail.com>
3212−L: platform-driver-x86@vger.kernel.org
3213−S: Maintained
3214−F: drivers/platform/x86/asus-wireless.c
3215−
32163209 ASYMMETRIC KEYS
32173210 M: David Howells <dhowells@redhat.com>
32183211 L: keyrings@vger.kernel.org
@@ -3352,10 +3345,10 @@ R: Boqun Feng <boqun.feng@gmail.com> · 133 unmodified lines
33523345 R: Mark Rutland <mark.rutland@arm.com>
33533346 L: linux-kernel@vger.kernel.org
33543347 S: Maintained
3348+F: Documentation/atomic_*.txt
33553349 F: arch/*/include/asm/atomic*.h
33563350 F: include/*/atomic*.h
33573351 F: include/linux/refcount.h
3358−F: Documentation/atomic_*.txt
33593352 F: scripts/atomic/
33603353
33613354 ATTO EXPRESSSAS SAS/SATA RAID SCSI DRIVER
@@ -3649,50 +3642,6 @@ S: Maintained · 287 unmodified lines
36493642 F: Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
36503643 F: drivers/iio/accel/bma400*
36513644
3652−BPF [GENERAL] (Safe Dynamic Programs and Tools)
3653−M: Alexei Starovoitov <ast@kernel.org>
3654−M: Daniel Borkmann <daniel@iogearbox.net>
3655−M: Andrii Nakryiko <andrii@kernel.org>
3656−R: Martin KaFai Lau <martin.lau@linux.dev>
3657−R: Song Liu <song@kernel.org>
3658−R: Yonghong Song <yhs@fb.com>
3659−R: John Fastabend <john.fastabend@gmail.com>
3660−R: KP Singh <kpsingh@kernel.org>
3661−R: Stanislav Fomichev <sdf@google.com>
3662−R: Hao Luo <haoluo@google.com>
3663−R: Jiri Olsa <jolsa@kernel.org>
3664−L: bpf@vger.kernel.org
3665−S: Supported
3666−W: https://bpf.io/
3667−Q: https://patchwork.kernel.org/project/netdevbpf/list/?delegate=121173
3668−T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
3669−T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git
3670−F: Documentation/bpf/
3671−F: Documentation/networking/filter.rst
3672−F: Documentation/userspace-api/ebpf/
3673−F: arch/*/net/*
3674−F: include/linux/bpf*
3675−F: include/linux/btf*
3676−F: include/linux/filter.h
3677−F: include/trace/events/xdp.h
3678−F: include/uapi/linux/bpf*
3679−F: include/uapi/linux/btf*
3680−F: include/uapi/linux/filter.h
3681−F: kernel/bpf/
3682−F: kernel/trace/bpf_trace.c
3683−F: lib/test_bpf.c
3684−F: net/bpf/
3685−F: net/core/filter.c
3686−F: net/sched/act_bpf.c
3687−F: net/sched/cls_bpf.c
3688−F: samples/bpf/
3689−F: scripts/bpf_doc.py
3690−F: scripts/pahole-flags.sh
3691−F: scripts/pahole-version.sh
3692−F: tools/bpf/
3693−F: tools/lib/bpf/
3694−F: tools/testing/selftests/bpf/
3695−
36963645 BPF JIT for ARM
36973646 M: Shubham Bansal <illusionist.neo@gmail.com>
36983647 L: bpf@vger.kernel.org
@@ -3771,79 +3720,79 @@ S: Supported · 72 unmodified lines
37713720 F: arch/x86/net/
37723721 X: arch/x86/net/bpf_jit_comp32.c
37733722
3723+BPF [BTF]
3724+M: Martin KaFai Lau <martin.lau@linux.dev>
3725+L: bpf@vger.kernel.org
3726+S: Maintained
3727+F: include/linux/btf*
3728+F: kernel/bpf/btf.c
3729+
37743730 BPF [CORE]
37753731 M: Alexei Starovoitov <ast@kernel.org>
37763732 M: Daniel Borkmann <daniel@iogearbox.net>
37773733 R: John Fastabend <john.fastabend@gmail.com>
37783734 L: bpf@vger.kernel.org
37793735 S: Maintained
3780−F: kernel/bpf/verifier.c
3781−F: kernel/bpf/tnum.c
3782−F: kernel/bpf/core.c
3783−F: kernel/bpf/syscall.c
3784−F: kernel/bpf/dispatcher.c
3785−F: kernel/bpf/trampoline.c
37863736 F: include/linux/bpf*
37873737 F: include/linux/filter.h
37883738 F: include/linux/tnum.h
3739+F: kernel/bpf/core.c
3740+F: kernel/bpf/dispatcher.c
3741+F: kernel/bpf/syscall.c
3742+F: kernel/bpf/tnum.c
3743+F: kernel/bpf/trampoline.c
3744+F: kernel/bpf/verifier.c
37893745
3790−BPF [BTF]
3791−M: Martin KaFai Lau <martin.lau@linux.dev>
3792−L: bpf@vger.kernel.org
3793−S: Maintained
3794−F: kernel/bpf/btf.c
3795−F: include/linux/btf*
3796−
3797−BPF [TRACING]
3798−M: Song Liu <song@kernel.org>
3799−R: Jiri Olsa <jolsa@kernel.org>
3746+BPF [DOCUMENTATION] (Related to Standardization)
3747+R: David Vernet <void@manifault.com>
38003748 L: bpf@vger.kernel.org
3749+L: bpf@ietf.org
38013750 S: Maintained
3802−F: kernel/trace/bpf_trace.c
3803−F: kernel/bpf/stackmap.c
3751+F: Documentation/bpf/instruction-set.rst
38043752
3805−BPF [NETWORKING] (tc BPF, sock_addr)
3806−M: Martin KaFai Lau <martin.lau@linux.dev>
3753+BPF [GENERAL] (Safe Dynamic Programs and Tools)
3754+M: Alexei Starovoitov <ast@kernel.org>
38073755 M: Daniel Borkmann <daniel@iogearbox.net>
3756+M: Andrii Nakryiko <andrii@kernel.org>
3757+R: Martin KaFai Lau <martin.lau@linux.dev>
3758+R: Song Liu <song@kernel.org>
3759+R: Yonghong Song <yhs@fb.com>
38083760 R: John Fastabend <john.fastabend@gmail.com>
3761+R: KP Singh <kpsingh@kernel.org>
3762+R: Stanislav Fomichev <sdf@google.com>
3763+R: Hao Luo <haoluo@google.com>
3764+R: Jiri Olsa <jolsa@kernel.org>
38093765 L: bpf@vger.kernel.org
3810−L: netdev@vger.kernel.org
3811−S: Maintained
3766+S: Supported
3767+W: https://bpf.io/
3768+Q: https://patchwork.kernel.org/project/netdevbpf/list/?delegate=121173
3769+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
3770+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git
3771+F: Documentation/bpf/
3772+F: Documentation/networking/filter.rst
3773+F: Documentation/userspace-api/ebpf/
3774+F: arch/*/net/*
3775+F: include/linux/bpf*
3776+F: include/linux/btf*
3777+F: include/linux/filter.h
3778+F: include/trace/events/xdp.h
3779+F: include/uapi/linux/bpf*
3780+F: include/uapi/linux/btf*
3781+F: include/uapi/linux/filter.h
3782+F: kernel/bpf/
3783+F: kernel/trace/bpf_trace.c
3784+F: lib/test_bpf.c
3785+F: net/bpf/
38123786 F: net/core/filter.c
38133787 F: net/sched/act_bpf.c
38143788 F: net/sched/cls_bpf.c
3815−
3816−BPF [NETWORKING] (struct_ops, reuseport)
3817−M: Martin KaFai Lau <martin.lau@linux.dev>
3818−L: bpf@vger.kernel.org
3819−L: netdev@vger.kernel.org
3820−S: Maintained
3821−F: kernel/bpf/bpf_struct*
3822−
3823−BPF [SECURITY & LSM] (Security Audit and Enforcement using BPF)
3824−M: KP Singh <kpsingh@kernel.org>
3825−R: Florent Revest <revest@chromium.org>
3826−R: Brendan Jackman <jackmanb@chromium.org>
3827−L: bpf@vger.kernel.org
3828−S: Maintained
3829−F: Documentation/bpf/prog_lsm.rst
3830−F: include/linux/bpf_lsm.h
3831−F: kernel/bpf/bpf_lsm.c
3832−F: security/bpf/
3833−
3834−BPF [STORAGE & CGROUPS]
3835−M: Martin KaFai Lau <martin.lau@linux.dev>
3836−L: bpf@vger.kernel.org
3837−S: Maintained
3838−F: kernel/bpf/cgroup.c
3839−F: kernel/bpf/*storage.c
3840−F: kernel/bpf/bpf_lru*
3841−
3842−BPF [RINGBUF]
3843−M: Andrii Nakryiko <andrii@kernel.org>
3844−L: bpf@vger.kernel.org
3845−S: Maintained
3846−F: kernel/bpf/ringbuf.c
3789+F: samples/bpf/
3790+F: scripts/bpf_doc.py
3791+F: scripts/pahole-flags.sh
3792+F: scripts/pahole-version.sh
3793+F: tools/bpf/
3794+F: tools/lib/bpf/
3795+F: tools/testing/selftests/bpf/
38473796
38483797 BPF [ITERATOR]
38493798 M: Yonghong Song <yhs@fb.com>
@@ -3870,12 +3819,45 @@ L: bpf@vger.kernel.org · 20 unmodified lines
38703819 S: Maintained
38713820 F: tools/lib/bpf/
38723821
3873−BPF [TOOLING] (bpftool)
3874−M: Quentin Monnet <quentin@isovalent.com>
3822+BPF [MISC]
3823+L: bpf@vger.kernel.org
3824+S: Odd Fixes
3825+K: (?:\b|_)bpf(?:\b|_)
3826+
3827+BPF [NETWORKING] (struct_ops, reuseport)
3828+M: Martin KaFai Lau <martin.lau@linux.dev>
38753829 L: bpf@vger.kernel.org
3830+L: netdev@vger.kernel.org
38763831 S: Maintained
3877−F: kernel/bpf/disasm.*
3878−F: tools/bpf/bpftool/
3832+F: kernel/bpf/bpf_struct*
3833+
3834+BPF [NETWORKING] (tc BPF, sock_addr)
3835+M: Martin KaFai Lau <martin.lau@linux.dev>
3836+M: Daniel Borkmann <daniel@iogearbox.net>
3837+R: John Fastabend <john.fastabend@gmail.com>
3838+L: bpf@vger.kernel.org
3839+L: netdev@vger.kernel.org
3840+S: Maintained
3841+F: net/core/filter.c
3842+F: net/sched/act_bpf.c
3843+F: net/sched/cls_bpf.c
3844+
3845+BPF [RINGBUF]
3846+M: Andrii Nakryiko <andrii@kernel.org>
3847+L: bpf@vger.kernel.org
3848+S: Maintained
3849+F: kernel/bpf/ringbuf.c
3850+
3851+BPF [SECURITY & LSM] (Security Audit and Enforcement using BPF)
3852+M: KP Singh <kpsingh@kernel.org>
3853+R: Florent Revest <revest@chromium.org>
3854+R: Brendan Jackman <jackmanb@chromium.org>
3855+L: bpf@vger.kernel.org
3856+S: Maintained
3857+F: Documentation/bpf/prog_lsm.rst
3858+F: include/linux/bpf_lsm.h
3859+F: kernel/bpf/bpf_lsm.c
3860+F: security/bpf/
38793861
38803862 BPF [SELFTESTS] (Test Runners & Infrastructure)
38813863 M: Andrii Nakryiko <andrii@kernel.org>
@@ -3884,17 +3866,28 @@ L: bpf@vger.kernel.org · 2 unmodified lines
38843866 S: Maintained
38853867 F: tools/testing/selftests/bpf/
38863868
3887−BPF [DOCUMENTATION] (Related to Standardization)
3888−R: David Vernet <void@manifault.com>
3869+BPF [STORAGE & CGROUPS]
3870+M: Martin KaFai Lau <martin.lau@linux.dev>
38893871 L: bpf@vger.kernel.org
3890−L: bpf@ietf.org
38913872 S: Maintained
3892−F: Documentation/bpf/instruction-set.rst
3873+F: kernel/bpf/*storage.c
3874+F: kernel/bpf/bpf_lru*
3875+F: kernel/bpf/cgroup.c
38933876
3894−BPF [MISC]
3877+BPF [TOOLING] (bpftool)
3878+M: Quentin Monnet <quentin@isovalent.com>
38953879 L: bpf@vger.kernel.org
3896−S: Odd Fixes
3897−K: (?:\b|_)bpf(?:\b|_)
3880+S: Maintained
3881+F: kernel/bpf/disasm.*
3882+F: tools/bpf/bpftool/
3883+
3884+BPF [TRACING]
3885+M: Song Liu <song@kernel.org>
3886+R: Jiri Olsa <jolsa@kernel.org>
3887+L: bpf@vger.kernel.org
3888+S: Maintained
3889+F: kernel/bpf/stackmap.c
3890+F: kernel/trace/bpf_trace.c
38983891
38993892 BROADCOM B44 10/100 ETHERNET DRIVER
39003893 M: Michael Chan <michael.chan@broadcom.com>
@@ -3913,34 +3906,6 @@ F: drivers/net/dsa/bcm_sf2* · 12 unmodified lines
39133906 F: include/linux/dsa/brcm.h
39143907 F: include/linux/platform_data/b53.h
39153908
3916−BROADCOM BCMBCA ARM ARCHITECTURE
3917−M: William Zhang <william.zhang@broadcom.com>
3918−M: Anand Gore <anand.gore@broadcom.com>
3919−M: Kursad Oney <kursad.oney@broadcom.com>
3920−M: Florian Fainelli <f.fainelli@gmail.com>
3921−M: Rafał Miłecki <rafal@milecki.pl>
3922−R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
3923−L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
3924−S: Maintained
3925−T: git https://github.com/broadcom/stblinux.git
3926−F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
3927−F: arch/arm64/boot/dts/broadcom/bcmbca/*
3928−N: bcmbca
3929−N: bcm[9]?47622
3930−N: bcm[9]?4912
3931−N: bcm[9]?63138
3932−N: bcm[9]?63146
3933−N: bcm[9]?63148
3934−N: bcm[9]?63158
3935−N: bcm[9]?63178
3936−N: bcm[9]?6756
3937−N: bcm[9]?6813
3938−N: bcm[9]?6846
3939−N: bcm[9]?6855
3940−N: bcm[9]?6856
3941−N: bcm[9]?6858
3942−N: bcm[9]?6878
3943−
39443909 BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
39453910 M: Florian Fainelli <f.fainelli@gmail.com>
39463911 R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
@@ -4038,11 +4003,39 @@ N: brcmstb · 91 unmodified lines
40384003 N: bcm7038
40394004 N: bcm7120
40404005
4006+BROADCOM BCMBCA ARM ARCHITECTURE
4007+M: William Zhang <william.zhang@broadcom.com>
4008+M: Anand Gore <anand.gore@broadcom.com>
4009+M: Kursad Oney <kursad.oney@broadcom.com>
4010+M: Florian Fainelli <f.fainelli@gmail.com>
4011+M: Rafał Miłecki <rafal@milecki.pl>
4012+R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
4013+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
4014+S: Maintained
4015+T: git https://github.com/broadcom/stblinux.git
4016+F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
4017+F: arch/arm64/boot/dts/broadcom/bcmbca/*
4018+N: bcmbca
4019+N: bcm[9]?47622
4020+N: bcm[9]?4912
4021+N: bcm[9]?63138
4022+N: bcm[9]?63146
4023+N: bcm[9]?63148
4024+N: bcm[9]?63158
4025+N: bcm[9]?63178
4026+N: bcm[9]?6756
4027+N: bcm[9]?6813
4028+N: bcm[9]?6846
4029+N: bcm[9]?6855
4030+N: bcm[9]?6856
4031+N: bcm[9]?6858
4032+N: bcm[9]?6878
4033+
40414034 BROADCOM BDC DRIVER
40424035 M: Justin Chen <justinpopo6@gmail.com>
40434036 M: Al Cooper <alcooperx@gmail.com>
4044−L: linux-usb@vger.kernel.org
40454037 R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
4038+L: linux-usb@vger.kernel.org
40464039 S: Maintained
40474040 F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml
40484041 F: drivers/usb/gadget/udc/bdc/
@@ -4064,10 +4057,10 @@ F: arch/mips/bmips/* · 15 unmodified lines
40644057 F: arch/mips/boot/dts/brcm/bcm*.dts*
40654058 F: arch/mips/include/asm/mach-bmips/*
40664059 F: arch/mips/kernel/*bmips*
4067−F: drivers/soc/bcm/bcm63xx
40684060 F: drivers/irqchip/irq-bcm63*
40694061 F: drivers/irqchip/irq-bcm7*
40704062 F: drivers/irqchip/irq-brcmstb*
4063+F: drivers/soc/bcm/bcm63xx
40714064 F: include/linux/bcm963xx_nvram.h
40724065 F: include/linux/bcm963xx_tag.h
40734066
@@ -4349,9 +4342,9 @@ M: Florian Fainelli <f.fainelli@gmail.com> · 275 unmodified lines
43494342 R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
43504343 L: netdev@vger.kernel.org
43514344 S: Supported
4345+F: Documentation/devicetree/bindings/net/brcm,systemport.yaml
43524346 F: drivers/net/ethernet/broadcom/bcmsysport.*
43534347 F: drivers/net/ethernet/broadcom/unimac.h
4354−F: Documentation/devicetree/bindings/net/brcm,systemport.yaml
43554348
43564349 BROADCOM TG3 GIGABIT ETHERNET DRIVER
43574350 M: Siva Reddy Kallam <siva.kallam@broadcom.com>
@@ -4483,29 +4476,6 @@ W: https://github.com/Cascoda/ca8210-linux.git · 125 unmodified lines
44834476 F: Documentation/devicetree/bindings/net/ieee802154/ca8210.txt
44844477 F: drivers/net/ieee802154/ca8210.c
44854478
4486−CANAAN/KENDRYTE K210 SOC FPIOA DRIVER
4487−M: Damien Le Moal <dlemoal@kernel.org>
4488−L: linux-riscv@lists.infradead.org
4489−L: linux-gpio@vger.kernel.org (pinctrl driver)
4490−F: Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
4491−F: drivers/pinctrl/pinctrl-k210.c
4492−
4493−CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER
4494−M: Damien Le Moal <dlemoal@kernel.org>
4495−L: linux-kernel@vger.kernel.org
4496−L: linux-riscv@lists.infradead.org
4497−S: Maintained
4498−F: Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
4499−F: drivers/reset/reset-k210.c
4500−
4501−CANAAN/KENDRYTE K210 SOC SYSTEM CONTROLLER DRIVER
4502−M: Damien Le Moal <dlemoal@kernel.org>
4503−L: linux-riscv@lists.infradead.org
4504−S: Maintained
4505−F: Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
4506−F: drivers/soc/canaan/
4507−F: include/soc/canaan/
4508−
45094479 CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
45104480 M: David Howells <dhowells@redhat.com>
45114481 L: linux-cachefs@redhat.com (moderated for non-subscribers)
@@ -4627,6 +4597,29 @@ F: Documentation/networking/j1939.rst · 115 unmodified lines
46274597 F: include/uapi/linux/can/j1939.h
46284598 F: net/can/j1939/
46294599
4600+CANAAN/KENDRYTE K210 SOC FPIOA DRIVER
4601+M: Damien Le Moal <dlemoal@kernel.org>
4602+L: linux-riscv@lists.infradead.org
4603+L: linux-gpio@vger.kernel.org (pinctrl driver)
4604+F: Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
4605+F: drivers/pinctrl/pinctrl-k210.c
4606+
4607+CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER
4608+M: Damien Le Moal <dlemoal@kernel.org>
4609+L: linux-kernel@vger.kernel.org
4610+L: linux-riscv@lists.infradead.org
4611+S: Maintained
4612+F: Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
4613+F: drivers/reset/reset-k210.c
4614+
4615+CANAAN/KENDRYTE K210 SOC SYSTEM CONTROLLER DRIVER
4616+M: Damien Le Moal <dlemoal@kernel.org>
4617+L: linux-riscv@lists.infradead.org
4618+S: Maintained
4619+F: Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
4620+F: drivers/soc/canaan/
4621+F: include/soc/canaan/
4622+
46304623 CAPABILITIES
46314624 M: Serge Hallyn <serge@hallyn.com>
46324625 L: linux-security-module@vger.kernel.org
@@ -4686,8 +4679,8 @@ F: arch/arm64/boot/dts/cavium/thunder2-99xx* · 53 unmodified lines
46864679
46874680 CBS/ETF/TAPRIO QDISCS
46884681 M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
4689−S: Maintained
46904682 L: netdev@vger.kernel.org
4683+S: Maintained
46914684 F: net/sched/sch_cbs.c
46924685 F: net/sched/sch_etf.c
46934686 F: net/sched/sch_taprio.c
@@ -4710,10 +4703,10 @@ CCTRNG ARM TRUSTZONE CRYPTOCELL TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER · 16 unmodified lines
47104703 M: Hadar Gat <hadar.gat@arm.com>
47114704 L: linux-crypto@vger.kernel.org
47124705 S: Supported
4706+W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
4707+F: Documentation/devicetree/bindings/rng/arm-cctrng.yaml
47134708 F: drivers/char/hw_random/cctrng.c
47144709 F: drivers/char/hw_random/cctrng.h
4715−F: Documentation/devicetree/bindings/rng/arm-cctrng.yaml
4716−W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
47174710
47184711 CEC FRAMEWORK
47194712 M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
@@ -4873,13 +4866,6 @@ S: Maintained · 153 unmodified lines
48734866 F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml
48744867 F: sound/soc/codecs/cros_ec_codec.*
48754868
4876−CHROMEOS EC UART DRIVER
4877−M: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
4878−R: Benson Leung <bleung@chromium.org>
4879−R: Tzung-Bi Shih <tzungbi@kernel.org>
4880−S: Maintained
4881−F: drivers/platform/chrome/cros_ec_uart.c
4882−
48834869 CHROMEOS EC SUBDRIVERS
48844870 M: Benson Leung <bleung@chromium.org>
48854871 R: Guenter Roeck <groeck@chromium.org>
@@ -4889,13 +4875,12 @@ F: drivers/power/supply/cros_usbpd-charger.c · 3 unmodified lines
48894875 N: cros_ec
48904876 N: cros-ec
48914877
4892−CHROMEOS EC USB TYPE-C DRIVER
4893−M: Prashant Malani <pmalani@chromium.org>
4894−L: chrome-platform@lists.linux.dev
4878+CHROMEOS EC UART DRIVER
4879+M: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
4880+R: Benson Leung <bleung@chromium.org>
4881+R: Tzung-Bi Shih <tzungbi@kernel.org>
48954882 S: Maintained
4896−F: drivers/platform/chrome/cros_ec_typec.*
4897−F: drivers/platform/chrome/cros_typec_switch.c
4898−F: drivers/platform/chrome/cros_typec_vdm.*
4883+F: drivers/platform/chrome/cros_ec_uart.c
48994884
49004885 CHROMEOS EC USB PD NOTIFY DRIVER
49014886 M: Prashant Malani <pmalani@chromium.org>
@@ -4904,6 +4889,14 @@ S: Maintained · 2 unmodified lines
49044889 F: drivers/platform/chrome/cros_usbpd_notify.c
49054890 F: include/linux/platform_data/cros_usbpd_notify.h
49064891
4892+CHROMEOS EC USB TYPE-C DRIVER
4893+M: Prashant Malani <pmalani@chromium.org>
4894+L: chrome-platform@lists.linux.dev
4895+S: Maintained
4896+F: drivers/platform/chrome/cros_ec_typec.*
4897+F: drivers/platform/chrome/cros_typec_switch.c
4898+F: drivers/platform/chrome/cros_typec_vdm.*
4899+
49074900 CHROMEOS HPS DRIVER
49084901 M: Dan Callaghan <dcallagh@chromium.org>
49094902 R: Sami Kyöstilä <skyostil@chromium.org>
@@ -5021,6 +5014,18 @@ M: Nelson Escobar <neescoba@cisco.com> · 111 unmodified lines
50215014 S: Supported
50225015 F: drivers/infiniband/hw/usnic/
50235016
5017+CLANG CONTROL FLOW INTEGRITY SUPPORT
5018+M: Sami Tolvanen <samitolvanen@google.com>
5019+M: Kees Cook <keescook@chromium.org>
5020+R: Nathan Chancellor <nathan@kernel.org>
5021+R: Nick Desaulniers <ndesaulniers@google.com>
5022+L: llvm@lists.linux.dev
5023+S: Supported
5024+B: https://github.com/ClangBuiltLinux/linux/issues
5025+T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/hardening
5026+F: include/linux/cfi.h
5027+F: kernel/cfi.c
5028+
50245029 CLANG-FORMAT FILE
50255030 M: Miguel Ojeda <ojeda@kernel.org>
50265031 S: Maintained
@@ -5041,18 +5046,6 @@ F: scripts/Makefile.clang · 14 unmodified lines
50415046 F: scripts/clang-tools/
50425047 K: \b(?i:clang|llvm)\b
50435048
5044−CLANG CONTROL FLOW INTEGRITY SUPPORT
5045−M: Sami Tolvanen <samitolvanen@google.com>
5046−M: Kees Cook <keescook@chromium.org>
5047−R: Nathan Chancellor <nathan@kernel.org>
5048−R: Nick Desaulniers <ndesaulniers@google.com>
5049−L: llvm@lists.linux.dev
5050−S: Supported
5051−B: https://github.com/ClangBuiltLinux/linux/issues
5052−T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/hardening
5053−F: include/linux/cfi.h
5054−F: kernel/cfi.c
5055−
50565049 CLK API
50575050 M: Russell King <linux@armlinux.org.uk>
50585051 L: linux-clk@vger.kernel.org
@@ -5223,8 +5216,8 @@ CONTEXT TRACKING · 164 unmodified lines
52235216 M: Frederic Weisbecker <frederic@kernel.org>
52245217 M: "Paul E. McKenney" <paulmck@kernel.org>
52255218 S: Maintained
5226−F: kernel/context_tracking.c
52275219 F: include/linux/context_tracking*
5220+F: kernel/context_tracking.c
52285221
52295222 CONTROL GROUP (CGROUP)
52305223 M: Tejun Heo <tj@kernel.org>
@@ -5385,8 +5378,8 @@ F: drivers/cpuidle/cpuidle-big_little.c · 154 unmodified lines
53855378
53865379 CPUIDLE DRIVER - ARM EXYNOS
53875380 M: Daniel Lezcano <daniel.lezcano@linaro.org>
5388−R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
53895381 M: Kukjin Kim <kgene@kernel.org>
5382+R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
53905383 L: linux-pm@vger.kernel.org
53915384 L: linux-samsung-soc@vger.kernel.org
53925385 S: Supported
@@ -5407,8 +5400,8 @@ M: Ulf Hansson <ulf.hansson@linaro.org> · 14 unmodified lines
54075400 L: linux-pm@vger.kernel.org
54085401 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
54095402 S: Supported
5410−F: drivers/cpuidle/cpuidle-psci.h
54115403 F: drivers/cpuidle/cpuidle-psci-domain.c
5404+F: drivers/cpuidle/cpuidle-psci.h
54125405
54135406 CPUIDLE DRIVER - DT IDLE PM DOMAIN
54145407 M: Ulf Hansson <ulf.hansson@linaro.org>
@@ -5552,19 +5545,19 @@ S: Supported · 137 unmodified lines
55525545 W: http://www.chelsio.com
55535546 F: drivers/crypto/chelsio
55545547
5555−CXGB4 INLINE CRYPTO DRIVER
5556−M: Ayush Sawal <ayush.sawal@chelsio.com>
5548+CXGB4 ETHERNET DRIVER (CXGB4)
5549+M: Raju Rangoju <rajur@chelsio.com>
55575550 L: netdev@vger.kernel.org
55585551 S: Supported
55595552 W: http://www.chelsio.com
5560−F: drivers/net/ethernet/chelsio/inline_crypto/
5553+F: drivers/net/ethernet/chelsio/cxgb4/
55615554
5562−CXGB4 ETHERNET DRIVER (CXGB4)
5563−M: Raju Rangoju <rajur@chelsio.com>
5555+CXGB4 INLINE CRYPTO DRIVER
5556+M: Ayush Sawal <ayush.sawal@chelsio.com>
55645557 L: netdev@vger.kernel.org
55655558 S: Supported
55665559 W: http://www.chelsio.com
5567−F: drivers/net/ethernet/chelsio/cxgb4/
5560+F: drivers/net/ethernet/chelsio/inline_crypto/
55685561
55695562 CXGB4 ISCSI DRIVER (CXGB4I)
55705563 M: Varun Prakash <varun@chelsio.com>
@@ -5621,16 +5614,6 @@ CYCLADES PC300 DRIVER · 50 unmodified lines
56215614 S: Orphan
56225615 F: drivers/net/wan/pc300*
56235616
5624−CYPRESS_FIRMWARE MEDIA DRIVER
5625−M: Antti Palosaari <crope@iki.fi>
5626−L: linux-media@vger.kernel.org
5627−S: Maintained
5628−W: https://linuxtv.org
5629−W: http://palosaari.fi/linux/
5630−Q: http://patchwork.linuxtv.org/project/linux-media/list/
5631−T: git git://linuxtv.org/anttip/media_tree.git
5632−F: drivers/media/common/cypress_firmware*
5633−
56345617 CYPRESS CY8C95X0 PINCTRL DRIVER
56355618 M: Patrick Rudolph <patrick.rudolph@9elements.com>
56365619 L: linux-gpio@vger.kernel.org
@@ -5650,6 +5633,16 @@ S: Maintained · 13 unmodified lines
56505633 F: Documentation/devicetree/bindings/input/cypress-sf.yaml
56515634 F: drivers/input/keyboard/cypress-sf.c
56525635
5636+CYPRESS_FIRMWARE MEDIA DRIVER
5637+M: Antti Palosaari <crope@iki.fi>
5638+L: linux-media@vger.kernel.org
5639+S: Maintained
5640+W: https://linuxtv.org
5641+W: http://palosaari.fi/linux/
5642+Q: http://patchwork.linuxtv.org/project/linux-media/list/
5643+T: git git://linuxtv.org/anttip/media_tree.git
5644+F: drivers/media/common/cypress_firmware*
5645+
56535646 CYTTSP TOUCHSCREEN DRIVER
56545647 M: Linus Walleij <linus.walleij@linaro.org>
56555648 L: linux-input@vger.kernel.org
@@ -5816,11 +5809,6 @@ S: Maintained · 160 unmodified lines
58165809 F: Documentation/driver-api/dcdbas.rst
58175810 F: drivers/platform/x86/dell/dcdbas.*
58185811
5819−DELL WMI DESCRIPTOR DRIVER
5820−L: Dell.Client.Kernel@dell.com
5821−S: Maintained
5822−F: drivers/platform/x86/dell/dell-wmi-descriptor.c
5823−
58245812 DELL WMI DDV DRIVER
58255813 M: Armin Wolf <W_Armin@gmx.de>
58265814 S: Maintained
@@ -5828,13 +5816,17 @@ F: Documentation/ABI/testing/debugfs-dell-wmi-ddv · 1 unmodified line
58285816 F: Documentation/ABI/testing/sysfs-platform-dell-wmi-ddv
58295817 F: drivers/platform/x86/dell/dell-wmi-ddv.c
58305818
5831−DELL WMI SYSMAN DRIVER
5832−M: Prasanth Ksr <prasanth.ksr@dell.com>
5819+DELL WMI DESCRIPTOR DRIVER
5820+L: Dell.Client.Kernel@dell.com
5821+S: Maintained
5822+F: drivers/platform/x86/dell/dell-wmi-descriptor.c
5823+
5824+DELL WMI HARDWARE PRIVACY SUPPORT
5825+M: Perry Yuan <Perry.Yuan@dell.com>
58335826 L: Dell.Client.Kernel@dell.com
58345827 L: platform-driver-x86@vger.kernel.org
58355828 S: Maintained
5836−F: Documentation/ABI/testing/sysfs-class-firmware-attributes
5837−F: drivers/platform/x86/dell/dell-wmi-sysman/
5829+F: drivers/platform/x86/dell/dell-wmi-privacy.c
58385830
58395831 DELL WMI NOTIFICATIONS DRIVER
58405832 M: Matthew Garrett <mjg59@srcf.ucam.org>
@@ -5842,20 +5834,13 @@ M: Pali Rohár <pali@kernel.org> · 1 unmodified line
58425834 S: Maintained
58435835 F: drivers/platform/x86/dell/dell-wmi-base.c
58445836
5845−DELL WMI HARDWARE PRIVACY SUPPORT
5846−M: Perry Yuan <Perry.Yuan@dell.com>
5837+DELL WMI SYSMAN DRIVER
5838+M: Prasanth Ksr <prasanth.ksr@dell.com>
58475839 L: Dell.Client.Kernel@dell.com
58485840 L: platform-driver-x86@vger.kernel.org
58495841 S: Maintained
5850−F: drivers/platform/x86/dell/dell-wmi-privacy.c
5851−
5852−DELTA ST MEDIA DRIVER
5853−M: Hugues Fruchet <hugues.fruchet@foss.st.com>
5854−L: linux-media@vger.kernel.org
5855−S: Supported
5856−W: https://linuxtv.org
5857−T: git git://linuxtv.org/media_tree.git
5858−F: drivers/media/platform/st/sti/delta
5842+F: Documentation/ABI/testing/sysfs-class-firmware-attributes
5843+F: drivers/platform/x86/dell/dell-wmi-sysman/
58595844
58605845 DELTA AHE-50DC FAN CONTROL MODULE DRIVER
58615846 M: Zev Weiss <zev@bewilderbeest.net>
@@ -5879,6 +5864,14 @@ F: Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml · 17 unmodified lines
58795864 F: drivers/gpio/gpio-tn48m.c
58805865 F: include/dt-bindings/reset/delta,tn48m-reset.h
58815866
5867+DELTA ST MEDIA DRIVER
5868+M: Hugues Fruchet <hugues.fruchet@foss.st.com>
5869+L: linux-media@vger.kernel.org
5870+S: Supported
5871+W: https://linuxtv.org
5872+T: git git://linuxtv.org/media_tree.git
5873+F: drivers/media/platform/st/sti/delta
5874+
58825875 DENALI NAND DRIVER
58835876 L: linux-mtd@lists.infradead.org
58845877 S: Orphan
@@ -5891,13 +5884,6 @@ S: Maintained · 6 unmodified lines
58915884 F: drivers/dma/dw-edma/
58925885 F: include/linux/dma/edma.h
58935886
5894−DESIGNWARE XDATA IP DRIVER
5895−M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
5896−L: linux-pci@vger.kernel.org
5897−S: Maintained
5898−F: Documentation/misc-devices/dw-xdata-pcie.rst
5899−F: drivers/misc/dw-xdata-pcie.c
5900−
59015887 DESIGNWARE USB2 DRD IP DRIVER
59025888 M: Minas Harutyunyan <hminas@synopsys.com>
59035889 L: linux-usb@vger.kernel.org
@@ -5911,6 +5897,13 @@ L: linux-usb@vger.kernel.org · 7 unmodified lines
59115897 S: Maintained
59125898 F: drivers/usb/dwc3/
59135899
5900+DESIGNWARE XDATA IP DRIVER
5901+M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
5902+L: linux-pci@vger.kernel.org
5903+S: Maintained
5904+F: Documentation/misc-devices/dw-xdata-pcie.rst
5905+F: drivers/misc/dw-xdata-pcie.c
5906+
59145907 DEVANTECH SRF ULTRASONIC RANGER IIO DRIVER
59155908 M: Andreas Klinger <ak@it-klinger.de>
59165909 L: linux-iio@vger.kernel.org
@@ -6020,8 +6013,8 @@ F: Documentation/devicetree/bindings/input/da90??-onkey.txt · 103 unmodified lines
60206013 F: Documentation/devicetree/bindings/input/dlg,da72??.txt
60216014 F: Documentation/devicetree/bindings/mfd/da90*.txt
60226015 F: Documentation/devicetree/bindings/mfd/da90*.yaml
6023−F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
60246016 F: Documentation/devicetree/bindings/regulator/da92*.txt
6017+F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
60256018 F: Documentation/devicetree/bindings/regulator/slg51000.txt
60266019 F: Documentation/devicetree/bindings/sound/da[79]*.txt
60276020 F: Documentation/devicetree/bindings/thermal/da90??-thermal.txt
@@ -6140,6 +6133,12 @@ F: include/linux/dma/ · 112 unmodified lines
61406133 F: include/linux/dmaengine.h
61416134 F: include/linux/of_dma.h
61426135
6136+DMA MAPPING BENCHMARK
6137+M: Xiang Chen <chenxiang66@hisilicon.com>
6138+L: iommu@lists.linux.dev
6139+F: kernel/dma/map_benchmark.c
6140+F: tools/testing/selftests/dma/
6141+
61436142 DMA MAPPING HELPERS
61446143 M: Christoph Hellwig <hch@lst.de>
61456144 M: Marek Szyprowski <m.szyprowski@samsung.com>
@@ -6150,17 +6149,11 @@ W: http://git.infradead.org/users/hch/dma-mapping.git · 4 unmodified lines
61506149 T: git git://git.infradead.org/users/hch/dma-mapping.git
61516150 F: include/asm-generic/dma-mapping.h
61526151 F: include/linux/dma-direct.h
6153−F: include/linux/dma-mapping.h
61546152 F: include/linux/dma-map-ops.h
6153+F: include/linux/dma-mapping.h
61556154 F: include/linux/swiotlb.h
61566155 F: kernel/dma/
61576156
6158−DMA MAPPING BENCHMARK
6159−M: Xiang Chen <chenxiang66@hisilicon.com>
6160−L: iommu@lists.linux.dev
6161−F: kernel/dma/map_benchmark.c
6162−F: tools/testing/selftests/dma/
6163−
61646157 DMA-BUF HEAPS FRAMEWORK
61656158 M: Sumit Semwal <sumit.semwal@linaro.org>
61666159 R: Benjamin Gaignard <benjamin.gaignard@collabora.com>
@@ -6350,6 +6343,25 @@ S: Maintained · 183 unmodified lines
63506343 F: drivers/soc/ti/smartreflex.c
63516344 F: include/linux/power/smartreflex.h
63526345
6346+DRM ACCEL DRIVERS FOR INTEL VPU
6347+M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
6348+M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
6349+L: dri-devel@lists.freedesktop.org
6350+S: Supported
6351+T: git git://anongit.freedesktop.org/drm/drm-misc
6352+F: drivers/accel/ivpu/
6353+F: include/uapi/drm/ivpu_accel.h
6354+
6355+DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
6356+M: Oded Gabbay <ogabbay@kernel.org>
6357+L: dri-devel@lists.freedesktop.org
6358+S: Maintained
6359+C: irc://irc.oftc.net/dri-devel
6360+T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
6361+F: Documentation/accel/
6362+F: drivers/accel/
6363+F: include/drm/drm_accel.h
6364+
63536365 DRM DRIVER FOR ALLWINNER DE2 AND DE3 ENGINE
63546366 M: Maxime Ripard <mripard@kernel.org>
63556367 M: Chen-Yu Tsai <wens@csie.org>
@@ -6432,6 +6444,21 @@ S: Maintained · 76 unmodified lines
64326444 F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
64336445 F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
64346446
6447+DRM DRIVER FOR FIRMWARE FRAMEBUFFERS
6448+M: Thomas Zimmermann <tzimmermann@suse.de>
6449+M: Javier Martinez Canillas <javierm@redhat.com>
6450+L: dri-devel@lists.freedesktop.org
6451+S: Maintained
6452+T: git git://anongit.freedesktop.org/drm/drm-misc
6453+F: drivers/gpu/drm/drm_aperture.c
6454+F: drivers/gpu/drm/tiny/ofdrm.c
6455+F: drivers/gpu/drm/tiny/simpledrm.c
6456+F: drivers/video/aperture.c
6457+F: drivers/video/nomodeset.c
6458+F: include/drm/drm_aperture.h
6459+F: include/linux/aperture.h
6460+F: include/video/nomodeset.h
6461+
64356462 DRM DRIVER FOR GENERIC EDP PANELS
64366463 R: Douglas Anderson <dianders@chromium.org>
64376464 F: Documentation/devicetree/bindings/display/panel/panel-edp.yaml
@@ -6466,6 +6493,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 28 unmodified lines
64666493 F: Documentation/devicetree/bindings/display/himax,hx8357d.txt
64676494 F: drivers/gpu/drm/tiny/hx8357d.c
64686495
6496+DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
6497+M: Deepak Rawat <drawat.floss@gmail.com>
6498+L: linux-hyperv@vger.kernel.org
6499+L: dri-devel@lists.freedesktop.org
6500+S: Maintained
6501+T: git git://anongit.freedesktop.org/drm/drm-misc
6502+F: drivers/gpu/drm/hyperv
6503+
64696504 DRM DRIVER FOR ILITEK ILI9225 PANELS
64706505 M: David Lechner <david@lechnology.com>
64716506 S: Maintained
@@ -6495,11 +6530,11 @@ F: drivers/gpu/drm/logicvc/ · 23 unmodified lines
64956530 DRM DRIVER FOR LVDS PANELS
64966531 M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
64976532 L: dri-devel@lists.freedesktop.org
6498−T: git git://anongit.freedesktop.org/drm/drm-misc
64996533 S: Maintained
6500−F: drivers/gpu/drm/panel/panel-lvds.c
6534+T: git git://anongit.freedesktop.org/drm/drm-misc
65016535 F: Documentation/devicetree/bindings/display/lvds.yaml
65026536 F: Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
6537+F: drivers/gpu/drm/panel/panel-lvds.c
65036538
65046539 DRM DRIVER FOR MANTIX MLAF057WE51 PANELS
65056540 M: Guido Günther <agx@sigxcpu.org>
@@ -6608,13 +6643,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 102 unmodified lines
66086643 F: Documentation/devicetree/bindings/display/repaper.txt
66096644 F: drivers/gpu/drm/tiny/repaper.c
66106645
6611−DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
6612−M: Javier Martinez Canillas <javierm@redhat.com>
6613−S: Maintained
6614−T: git git://anongit.freedesktop.org/drm/drm-misc
6615−F: Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
6616−F: drivers/gpu/drm/solomon/ssd130x*
6617−
66186646 DRM DRIVER FOR QEMU'S CIRRUS DEVICE
66196647 M: Dave Airlie <airlied@redhat.com>
66206648 M: Gerd Hoffmann <kraxel@redhat.com>
@@ -6663,28 +6691,11 @@ S: Maintained · 42 unmodified lines
66636691 F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
66646692 F: drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
66656693
6666−DRM DRIVER FOR SITRONIX ST7703 PANELS
6667−M: Guido Günther <agx@sigxcpu.org>
6668−R: Purism Kernel Team <kernel@puri.sm>
6669−R: Ondrej Jirman <megous@megous.com>
6670−S: Maintained
6671−F: Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
6672−F: drivers/gpu/drm/panel/panel-sitronix-st7703.c
6673−
6674−DRM DRIVER FOR FIRMWARE FRAMEBUFFERS
6675−M: Thomas Zimmermann <tzimmermann@suse.de>
6676−M: Javier Martinez Canillas <javierm@redhat.com>
6677−L: dri-devel@lists.freedesktop.org
6694+DRM DRIVER FOR SAMSUNG S6D7AA0 PANELS
6695+M: Artur Weber <aweber.kernel@gmail.com>
66786696 S: Maintained
6679−T: git git://anongit.freedesktop.org/drm/drm-misc
6680−F: drivers/gpu/drm/drm_aperture.c
6681−F: drivers/gpu/drm/tiny/ofdrm.c
6682−F: drivers/gpu/drm/tiny/simpledrm.c
6683−F: drivers/video/aperture.c
6684−F: drivers/video/nomodeset.c
6685−F: include/drm/drm_aperture.h
6686−F: include/linux/aperture.h
6687−F: include/video/nomodeset.h
6697+F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
6698+F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
66886699
66896700 DRM DRIVER FOR SITRONIX ST7586 PANELS
66906701 M: David Lechner <david@lechnology.com>
@@ -6699,6 +6710,14 @@ S: Maintained · 8 unmodified lines
66996710 F: Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
67006711 F: drivers/gpu/drm/panel/panel-sitronix-st7701.c
67016712
6713+DRM DRIVER FOR SITRONIX ST7703 PANELS
6714+M: Guido Günther <agx@sigxcpu.org>
6715+R: Purism Kernel Team <kernel@puri.sm>
6716+R: Ondrej Jirman <megous@megous.com>
6717+S: Maintained
6718+F: Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
6719+F: drivers/gpu/drm/panel/panel-sitronix-st7703.c
6720+
67026721 DRM DRIVER FOR SITRONIX ST7735R PANELS
67036722 M: David Lechner <david@lechnology.com>
67046723 S: Maintained
@@ -6706,6 +6725,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 1 unmodified line
67066725 F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml
67076726 F: drivers/gpu/drm/tiny/st7735r.c
67086727
6728+DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
6729+M: Javier Martinez Canillas <javierm@redhat.com>
6730+S: Maintained
6731+T: git git://anongit.freedesktop.org/drm/drm-misc
6732+F: Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
6733+F: drivers/gpu/drm/solomon/ssd130x*
6734+
67096735 DRM DRIVER FOR ST-ERICSSON MCDE
67106736 M: Linus Walleij <linus.walleij@linaro.org>
67116737 S: Maintained
@@ -6743,6 +6769,7 @@ F: drivers/gpu/drm/udl/ · 31 unmodified lines
67436769 DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)
67446770 M: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
67456771 M: Melissa Wen <melissa.srw@gmail.com>
6772+M: Maíra Canal <mairacanal@riseup.net>
67466773 R: Haneen Mohammed <hamohammed.sa@gmail.com>
67476774 R: Daniel Vetter <daniel@ffwll.ch>
67486775 L: dri-devel@lists.freedesktop.org
@@ -6804,25 +6831,6 @@ F: include/drm/drm* · 55 unmodified lines
68046831 F: include/linux/vga*
68056832 F: include/uapi/drm/drm*
68066833
6807−DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
6808−M: Oded Gabbay <ogabbay@kernel.org>
6809−L: dri-devel@lists.freedesktop.org
6810−S: Maintained
6811−C: irc://irc.oftc.net/dri-devel
6812−T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
6813−F: Documentation/accel/
6814−F: drivers/accel/
6815−F: include/drm/drm_accel.h
6816−
6817−DRM ACCEL DRIVERS FOR INTEL VPU
6818−M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
6819−M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
6820−L: dri-devel@lists.freedesktop.org
6821−S: Supported
6822−T: git git://anongit.freedesktop.org/drm/drm-misc
6823−F: drivers/accel/ivpu/
6824−F: include/uapi/drm/ivpu_accel.h
6825−
68266834 DRM DRIVERS FOR ALLWINNER A10
68276835 M: Maxime Ripard <mripard@kernel.org>
68286836 M: Chen-Yu Tsai <wens@csie.org>
@@ -6864,6 +6872,7 @@ S: Maintained · 35 unmodified lines
68646872 T: git git://anongit.freedesktop.org/drm/drm-misc
68656873 F: Documentation/devicetree/bindings/display/bridge/
68666874 F: drivers/gpu/drm/bridge/
6875+F: drivers/gpu/drm/drm_bridge.c
68676876 F: include/drm/drm_bridge.h
68686877
68696878 DRM DRIVERS FOR EXYNOS
@@ -6926,14 +6935,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 56 unmodified lines
69266935 F: Documentation/devicetree/bindings/display/hisilicon/
69276936 F: drivers/gpu/drm/hisilicon/
69286937
6929−DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
6930−M: Deepak Rawat <drawat.floss@gmail.com>
6931−L: linux-hyperv@vger.kernel.org
6932−L: dri-devel@lists.freedesktop.org
6933−S: Maintained
6934−T: git git://anongit.freedesktop.org/drm/drm-misc
6935−F: drivers/gpu/drm/hyperv
6936−
69376938 DRM DRIVERS FOR LIMA
69386939 M: Qiang Yu <yuq825@gmail.com>
69396940 L: dri-devel@lists.freedesktop.org
@@ -7085,6 +7086,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 145 unmodified lines
70857086 F: Documentation/devicetree/bindings/display/xlnx/
70867087 F: drivers/gpu/drm/xlnx/
70877088
7089+DRM GPU SCHEDULER
7090+M: Luben Tuikov <luben.tuikov@amd.com>
7091+L: dri-devel@lists.freedesktop.org
7092+S: Maintained
7093+T: git git://anongit.freedesktop.org/drm/drm-misc
7094+F: drivers/gpu/drm/scheduler/
7095+F: include/drm/gpu_scheduler.h
7096+
70887097 DRM PANEL DRIVERS
70897098 M: Neil Armstrong <neil.armstrong@linaro.org>
70907099 R: Sam Ravnborg <sam@ravnborg.org>
@@ -7113,14 +7122,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 22 unmodified lines
71137122 F: drivers/gpu/drm/ttm/
71147123 F: include/drm/ttm/
71157124
7116−DRM GPU SCHEDULER
7117−M: Luben Tuikov <luben.tuikov@amd.com>
7118−L: dri-devel@lists.freedesktop.org
7119−S: Maintained
7120−T: git git://anongit.freedesktop.org/drm/drm-misc
7121−F: drivers/gpu/drm/scheduler/
7122−F: include/drm/gpu_scheduler.h
7123−
71247125 DSBR100 USB FM RADIO DRIVER
71257126 M: Alexey Klimov <klimov.linux@gmail.com>
71267127 L: linux-media@vger.kernel.org
@@ -7248,10 +7249,10 @@ F: drivers/media/usb/dvb-usb-v2/usb_urb.c · 121 unmodified lines
72487249
72497250 DYNAMIC DEBUG
72507251 M: Jason Baron <jbaron@akamai.com>
7252+M: Jim Cromie <jim.cromie@gmail.com>
72517253 S: Maintained
72527254 F: include/linux/dynamic_debug.h
72537255 F: lib/dynamic_debug.c
7254−M: Jim Cromie <jim.cromie@gmail.com>
72557256 F: lib/test_dynamic_debug.c
72567257
72577258 DYNAMIC INTERRUPT MODERATION
@@ -7261,6 +7262,15 @@ F: Documentation/networking/net_dim.rst · 3 unmodified lines
72617262 F: include/linux/dim.h
72627263 F: lib/dim/
72637264
7265+DYNAMIC THERMAL POWER MANAGEMENT (DTPM)
7266+M: Daniel Lezcano <daniel.lezcano@kernel.org>
7267+L: linux-pm@vger.kernel.org
7268+S: Supported
7269+B: https://bugzilla.kernel.org
7270+T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
7271+F: drivers/powercap/dtpm*
7272+F: include/linux/dtpm.h
7273+
72647274 DZ DECSTATION DZ11 SERIAL DRIVER
72657275 M: "Maciej W. Rozycki" <macro@orcam.me.uk>
72667276 S: Maintained
@@ -7599,22 +7609,22 @@ W: http://www.broadcom.com · 332 unmodified lines
75997609 F: drivers/infiniband/hw/ocrdma/
76007610 F: include/uapi/rdma/ocrdma-abi.h
76017611
7602−EMULEX/BROADCOM LPFC FC/FCOE SCSI DRIVER
7612+EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER
76037613 M: James Smart <james.smart@broadcom.com>
7604−M: Dick Kennedy <dick.kennedy@broadcom.com>
7614+M: Ram Vegesna <ram.vegesna@broadcom.com>
76057615 L: linux-scsi@vger.kernel.org
7616+L: target-devel@vger.kernel.org
76067617 S: Supported
76077618 W: http://www.broadcom.com
7608−F: drivers/scsi/lpfc/
7619+F: drivers/scsi/elx/
76097620
7610−EMULEX/BROADCOM EFCT FC/FCOE SCSI TARGET DRIVER
7621+EMULEX/BROADCOM LPFC FC/FCOE SCSI DRIVER
76117622 M: James Smart <james.smart@broadcom.com>
7612−M: Ram Vegesna <ram.vegesna@broadcom.com>
7623+M: Dick Kennedy <dick.kennedy@broadcom.com>
76137624 L: linux-scsi@vger.kernel.org
7614−L: target-devel@vger.kernel.org
76157625 S: Supported
76167626 W: http://www.broadcom.com
7617−F: drivers/scsi/elx/
7627+F: drivers/scsi/lpfc/
76187628
76197629 ENE CB710 FLASH CARD READER DRIVER
76207630 M: Michał Mirosław <mirq-linux@rere.qmqm.pl>
@@ -7707,8 +7717,8 @@ F: drivers/net/mdio/of_mdio.c · 86 unmodified lines
77077717 F: drivers/net/pcs/
77087718 F: drivers/net/phy/
77097719 F: include/dt-bindings/net/qca-ar803x.h
7710−F: include/linux/linkmode.h
77117720 F: include/linux/*mdio*.h
7721+F: include/linux/linkmode.h
77127722 F: include/linux/mdio/*.h
77137723 F: include/linux/mii.h
77147724 F: include/linux/of_net.h
@@ -7771,8 +7781,8 @@ M: Mimi Zohar <zohar@linux.ibm.com> · 56 unmodified lines
77717781 L: linux-integrity@vger.kernel.org
77727782 S: Supported
77737783 T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
7774−F: security/integrity/evm/
77757784 F: security/integrity/
7785+F: security/integrity/evm/
77767786
77777787 EXTENSIBLE FIRMWARE INTERFACE (EFI)
77787788 M: Ard Biesheuvel <ardb@kernel.org>
@@ -7803,8 +7813,8 @@ EXTRA BOOT CONFIG · 24 unmodified lines
78037813 M: Masami Hiramatsu <mhiramat@kernel.org>
78047814 L: linux-kernel@vger.kernel.org
78057815 L: linux-trace-kernel@vger.kernel.org
7806−Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
78077816 S: Maintained
7817+Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
78087818 T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
78097819 F: Documentation/admin-guide/bootconfig.rst
78107820 F: fs/proc/bootconfig.c
@@ -8091,21 +8101,6 @@ F: Documentation/fpga/ · 280 unmodified lines
80918101 F: drivers/fpga/
80928102 F: include/linux/fpga/
80938103
8094−INTEL MAX10 BMC SECURE UPDATES
8095−M: Russ Weight <russell.h.weight@intel.com>
8096−L: linux-fpga@vger.kernel.org
8097−S: Maintained
8098−F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
8099−F: drivers/fpga/intel-m10-bmc-sec-update.c
8100−
8101−MICROCHIP POLARFIRE FPGA DRIVERS
8102−M: Conor Dooley <conor.dooley@microchip.com>
8103−R: Ivan Bornyakov <i.bornyakov@metrotek.ru>
8104−L: linux-fpga@vger.kernel.org
8105−S: Supported
8106−F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
8107−F: drivers/fpga/microchip-spi.c
8108−
81098104 FPU EMULATOR
81108105 M: Bill Metzenthen <billm@melbpc.org.au>
81118106 S: Maintained
@@ -8114,9 +8109,9 @@ F: arch/x86/math-emu/ · 2 unmodified lines
81148109
81158110 FRAMEBUFFER CORE
81168111 M: Daniel Vetter <daniel@ffwll.ch>
8117−F: drivers/video/fbdev/core/
81188112 S: Odd Fixes
81198113 T: git git://anongit.freedesktop.org/drm/drm-misc
8114+F: drivers/video/fbdev/core/
81208115
81218116 FRAMEBUFFER LAYER
81228117 M: Helge Deller <deller@gmx.de>
@@ -8493,15 +8488,15 @@ M: Masami Hiramatsu <mhiramat@kernel.org> · 370 unmodified lines
84938488 R: Mark Rutland <mark.rutland@arm.com>
84948489 L: linux-kernel@vger.kernel.org
84958490 L: linux-trace-kernel@vger.kernel.org
8496−Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
84978491 S: Maintained
8492+Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
84988493 T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
84998494 F: Documentation/trace/ftrace*
8500−F: kernel/trace/ftrace*
8501−F: kernel/trace/fgraph.c
85028495 F: arch/*/*/*/*ftrace*
85038496 F: arch/*/*/*ftrace*
85048497 F: include/*/ftrace.h
8498+F: kernel/trace/fgraph.c
8499+F: kernel/trace/ftrace*
85058500 F: samples/ftrace
85068501
85078502 FUNGIBLE ETHERNET DRIVERS
@@ -8542,10 +8537,10 @@ GATEWORKS SYSTEM CONTROLLER (GSC) DRIVER · 34 unmodified lines
85428537 M: Tim Harvey <tharvey@gateworks.com>
85438538 S: Maintained
85448539 F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml
8545−F: drivers/mfd/gateworks-gsc.c
8546−F: include/linux/mfd/gsc.h
85478540 F: Documentation/hwmon/gsc-hwmon.rst
85488541 F: drivers/hwmon/gsc-hwmon.c
8542+F: drivers/mfd/gateworks-gsc.c
8543+F: include/linux/mfd/gsc.h
85498544 F: include/linux/platform_data/gsc_hwmon.h
85508545
85518546 GCC PLUGINS
@@ -8673,8 +8668,8 @@ R: Andy Shevchenko <andy@kernel.org> · 121 unmodified lines
86738668 S: Maintained
86748669 F: lib/string.c
86758670 F: lib/string_helpers.c
8676−F: lib/test_string.c
86778671 F: lib/test-string_helpers.c
8672+F: lib/test_string.c
86788673
86798674 GENERIC UIO DRIVER FOR PCI DEVICES
86808675 M: "Michael S. Tsirkin" <mst@redhat.com>
@@ -9157,12 +9152,11 @@ L: linux-input@vger.kernel.org · 476 unmodified lines
91579152 S: Maintained
91589153 F: drivers/hid/hid-logitech-*
91599154
9160−HID++ LOGITECH DRIVERS
9161−R: Filipe Laíns <lains@riseup.net>
9162−R: Bastien Nocera <hadess@hadess.net>
9155+HID PHOENIX RC FLIGHT CONTROLLER
9156+M: Marcus Folkesson <marcus.folkesson@gmail.com>
91639157 L: linux-input@vger.kernel.org
91649158 S: Maintained
9165−F: drivers/hid/hid-logitech-hidpp.c
9159+F: drivers/hid/hid-pxrc.c
91669160
91679161 HID PLAYSTATION DRIVER
91689162 M: Roderick Colenbrander <roderick.colenbrander@sony.com>
@@ -9170,12 +9164,6 @@ L: linux-input@vger.kernel.org · 1 unmodified line
91709164 S: Supported
91719165 F: drivers/hid/hid-playstation.c
91729166
9173−HID PHOENIX RC FLIGHT CONTROLLER
9174−M: Marcus Folkesson <marcus.folkesson@gmail.com>
9175−L: linux-input@vger.kernel.org
9176−S: Maintained
9177−F: drivers/hid/hid-pxrc.c
9178−
91799167 HID SENSOR HUB DRIVERS
91809168 M: Jiri Kosina <jikos@kernel.org>
91819169 M: Jonathan Cameron <jic23@kernel.org>
@@ -9202,6 +9190,13 @@ S: Maintained · 20 unmodified lines
92029190 F: drivers/hid/wacom.h
92039191 F: drivers/hid/wacom_*
92049192
9193+HID++ LOGITECH DRIVERS
9194+R: Filipe Laíns <lains@riseup.net>
9195+R: Bastien Nocera <hadess@hadess.net>
9196+L: linux-input@vger.kernel.org
9197+S: Maintained
9198+F: drivers/hid/hid-logitech-hidpp.c
9199+
92059200 HIGH-RESOLUTION TIMERS, CLOCKEVENTS
92069201 M: Thomas Gleixner <tglx@linutronix.de>
92079202 L: linux-kernel@vger.kernel.org
@@ -9226,6 +9221,12 @@ W: http://www.highpoint-tech.com · 18 unmodified lines
92269221 F: Documentation/scsi/hptiop.rst
92279222 F: drivers/scsi/hptiop.c
92289223
9224+HIKEY960 ONBOARD USB GPIO HUB DRIVER
9225+M: John Stultz <jstultz@google.com>
9226+L: linux-kernel@vger.kernel.org
9227+S: Maintained
9228+F: drivers/misc/hisi_hikey_usb.c
9229+
92299230 HIMAX HX83112B TOUCHSCREEN SUPPORT
92309231 M: Job Noorman <job@noorman.info>
92319232 L: linux-input@vger.kernel.org
@@ -9274,6 +9275,12 @@ F: drivers/crypto/hisilicon/hpre/hpre.h · 42 unmodified lines
92749275 F: drivers/crypto/hisilicon/hpre/hpre_crypto.c
92759276 F: drivers/crypto/hisilicon/hpre/hpre_main.c
92769277
9278+HISILICON HNS3 PMU DRIVER
9279+M: Guangbin Huang <huangguangbin2@huawei.com>
9280+S: Supported
9281+F: Documentation/admin-guide/perf/hns3-pmu.rst
9282+F: drivers/perf/hisilicon/hns3_pmu.c
9283+
92779284 HISILICON I2C CONTROLLER DRIVER
92789285 M: Yicong Yang <yangyicong@hisilicon.com>
92799286 L: linux-i2c@vger.kernel.org
@@ -9306,12 +9313,6 @@ W: http://www.hisilicon.com · 26 unmodified lines
93069313 F: Documentation/devicetree/bindings/net/hisilicon*.txt
93079314 F: drivers/net/ethernet/hisilicon/
93089315
9309−HIKEY960 ONBOARD USB GPIO HUB DRIVER
9310−M: John Stultz <jstultz@google.com>
9311−L: linux-kernel@vger.kernel.org
9312−S: Maintained
9313−F: drivers/misc/hisi_hikey_usb.c
9314−
93159316 HISILICON PMU DRIVER
93169317 M: Shaokun Zhang <zhangshaokun@hisilicon.com>
93179318 M: Jonathan Cameron <jonathan.cameron@huawei.com>
@@ -9321,12 +9322,6 @@ F: Documentation/admin-guide/perf/hisi-pcie-pmu.rst · 3 unmodified lines
93219322 F: Documentation/admin-guide/perf/hisi-pmu.rst
93229323 F: drivers/perf/hisilicon
93239324
9324−HISILICON HNS3 PMU DRIVER
9325−M: Guangbin Huang <huangguangbin2@huawei.com>
9326−S: Supported
9327−F: Documentation/admin-guide/perf/hns3-pmu.rst
9328−F: drivers/perf/hisilicon/hns3_pmu.c
9329−
93309325 HISILICON PTT DRIVER
93319326 M: Yicong Yang <yangyicong@hisilicon.com>
93329327 M: Jonathan Cameron <jonathan.cameron@huawei.com>
@@ -9350,14 +9345,6 @@ F: drivers/crypto/hisilicon/qm.c · 17 unmodified lines
93509345 F: drivers/crypto/hisilicon/sgl.c
93519346 F: include/linux/hisi_acc_qm.h
93529347
9353−HISILICON ZIP Controller DRIVER
9354−M: Yang Shen <shenyang39@huawei.com>
9355−M: Zhou Wang <wangzhou1@hisilicon.com>
9356−L: linux-crypto@vger.kernel.org
9357−S: Maintained
9358−F: Documentation/ABI/testing/debugfs-hisi-zip
9359−F: drivers/crypto/hisilicon/zip/
9360−
93619348 HISILICON ROCE DRIVER
93629349 M: Haoyue Xu <xuhaoyue1@hisilicon.com>
93639350 M: Wenpeng Liang <liangwenpeng@huawei.com>
@@ -9416,6 +9403,14 @@ S: Maintained · 52 unmodified lines
94169403 W: http://www.hisilicon.com
94179404 F: drivers/spi/spi-hisi-sfc-v3xx.c
94189405
9406+HISILICON ZIP Controller DRIVER
9407+M: Yang Shen <shenyang39@huawei.com>
9408+M: Zhou Wang <wangzhou1@hisilicon.com>
9409+L: linux-crypto@vger.kernel.org
9410+S: Maintained
9411+F: Documentation/ABI/testing/debugfs-hisi-zip
9412+F: drivers/crypto/hisilicon/zip/
9413+
94199414 HMM - Heterogeneous Memory Management
94209415 M: Jérôme Glisse <jglisse@redhat.com>
94219416 L: linux-mm@kvack.org
@@ -9492,9 +9487,9 @@ F: drivers/input/touchscreen/htcpen.c · 70 unmodified lines
94929487 HTE SUBSYSTEM
94939488 M: Dipen Patel <dipenp@nvidia.com>
94949489 L: timestamp@lists.linux.dev
9495−T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
9496−Q: https://patchwork.kernel.org/project/timestamp/list/
94979490 S: Maintained
9491+Q: https://patchwork.kernel.org/project/timestamp/list/
9492+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
94989493 F: Documentation/devicetree/bindings/timestamp/
94999494 F: Documentation/driver-api/hte/
95009495 F: drivers/hte/
@@ -9589,8 +9584,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git · 88 unmodified lines
95899584 F: Documentation/ABI/stable/sysfs-bus-vmbus
95909585 F: Documentation/ABI/testing/debugfs-hyperv
95919586 F: Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
9592−F: Documentation/virt/hyperv
95939587 F: Documentation/networking/device_drivers/ethernet/microsoft/netvsc.rst
9588+F: Documentation/virt/hyperv
95949589 F: arch/arm64/hyperv
95959590 F: arch/arm64/include/asm/hyperv-tlfs.h
95969591 F: arch/arm64/include/asm/mshyperv.h
@@ -9772,6 +9767,12 @@ L: linux-i2c@vger.kernel.org · 175 unmodified lines
97729767 S: Maintained
97739768 F: drivers/i2c/i2c-stub.c
97749769
9770+I3C DRIVER FOR ASPEED AST2600
9771+M: Jeremy Kerr <jk@codeconstruct.com.au>
9772+S: Maintained
9773+F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
9774+F: drivers/i3c/master/ast2600-i3c-master.c
9775+
97759776 I3C DRIVER FOR CADENCE I3C MASTER IP
97769777 M: Przemysław Gaj <pgaj@cadence.com>
97779778 S: Maintained
@@ -9783,12 +9784,6 @@ S: Orphan · 5 unmodified lines
97839784 F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
97849785 F: drivers/i3c/master/dw*
97859786
9786−I3C DRIVER FOR ASPEED AST2600
9787−M: Jeremy Kerr <jk@codeconstruct.com.au>
9788−S: Maintained
9789−F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
9790−F: drivers/i3c/master/ast2600-i3c-master.c
9791−
97929787 I3C SUBSYSTEM
97939788 M: Alexandre Belloni <alexandre.belloni@bootlin.com>
97949789 L: linux-i3c@lists.infradead.org (moderated for non-subscribers)
@@ -9867,6 +9862,11 @@ L: netdev@vger.kernel.org · 72 unmodified lines
98679862 S: Supported
98689863 F: drivers/net/ethernet/ibm/ibmvnic.*
98699864
9865+IBM Power VFIO Support
9866+M: Timothy Pearson <tpearson@raptorengineering.com>
9867+S: Supported
9868+F: drivers/vfio/vfio_iommu_spapr_tce.c
9869+
98709870 IBM Power Virtual Ethernet Device Driver
98719871 M: Nick Child <nnac123@linux.ibm.com>
98729872 L: netdev@vger.kernel.org
@@ -9912,11 +9912,6 @@ F: drivers/crypto/vmx/ghash* · 39 unmodified lines
99129912 F: drivers/crypto/vmx/ppc-xlate.pl
99139913 F: drivers/crypto/vmx/vmx.c
99149914
9915−IBM Power VFIO Support
9916−M: Timothy Pearson <tpearson@raptorengineering.com>
9917−S: Supported
9918−F: drivers/vfio/vfio_iommu_spapr_tce.c
9919−
99209915 IBM ServeRAID RAID DRIVER
99219916 S: Orphan
99229917 F: drivers/scsi/ips.*
@@ -9984,6 +9979,10 @@ F: include/net/nl802154.h · 61 unmodified lines
99849979 F: net/ieee802154/
99859980 F: net/mac802154/
99869981
9982+IFCVF VIRTIO DATA PATH ACCELERATOR
9983+R: Zhu Lingshan <lingshan.zhu@intel.com>
9984+F: drivers/vdpa/ifcvf/
9985+
99879986 IFE PROTOCOL
99889987 M: Yotam Gigi <yotam.gi@gmail.com>
99899988 M: Jamal Hadi Salim <jhs@mojatatu.com>
@@ -10248,8 +10247,8 @@ M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com> · 258 unmodified lines
1024810247 L: linux-integrity@vger.kernel.org
1024910248 S: Supported
1025010249 T: git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
10251−F: security/integrity/ima/
1025210250 F: security/integrity/
10251+F: security/integrity/ima/
1025310252
1025410253 INTEL 810/815 FRAMEBUFFER DRIVER
1025510254 M: Antonino Daplas <adaplas@gmail.com>
@@ -10403,14 +10402,6 @@ S: Supported · 147 unmodified lines
1040310402 Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
1040410403 F: drivers/dma/ioat*
1040510404
10406−INTEL IDXD DRIVER
10407−M: Fenghua Yu <fenghua.yu@intel.com>
10408−M: Dave Jiang <dave.jiang@intel.com>
10409−L: dmaengine@vger.kernel.org
10410−S: Supported
10411−F: drivers/dma/idxd/*
10412−F: include/uapi/linux/idxd.h
10413−
1041410405 INTEL IDLE DRIVER
1041510406 M: Jacob Pan <jacob.jun.pan@linux.intel.com>
1041610407 M: Len Brown <lenb@kernel.org>
@@ -10420,6 +10411,14 @@ B: https://bugzilla.kernel.org · 3 unmodified lines
1042010411 T: git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git
1042110412 F: drivers/idle/intel_idle.c
1042210413
10414+INTEL IDXD DRIVER
10415+M: Fenghua Yu <fenghua.yu@intel.com>
10416+M: Dave Jiang <dave.jiang@intel.com>
10417+L: dmaengine@vger.kernel.org
10418+S: Supported
10419+F: drivers/dma/idxd/*
10420+F: include/uapi/linux/idxd.h
10421+
1042310422 INTEL IN FIELD SCAN (IFS) DEVICE
1042410423 M: Jithu Joseph <jithu.joseph@intel.com>
1042510424 R: Ashok Raj <ashok.raj@intel.com>
@@ -10466,18 +10465,18 @@ F: Documentation/admin-guide/media/ipu3_rcb.svg · 40 unmodified lines
1046610465 F: Documentation/userspace-api/media/v4l/pixfmt-meta-intel-ipu3.rst
1046710466 F: drivers/staging/media/ipu3/
1046810467
10469−INTEL IXP4XX CRYPTO SUPPORT
10470−M: Corentin Labbe <clabbe@baylibre.com>
10471−L: linux-crypto@vger.kernel.org
10472−S: Maintained
10473−F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
10474−
1047510468 INTEL ISHTP ECLITE DRIVER
1047610469 M: Sumesh K Naduvalath <sumesh.k.naduvalath@intel.com>
1047710470 L: platform-driver-x86@vger.kernel.org
1047810471 S: Supported
1047910472 F: drivers/platform/x86/intel/ishtp_eclite.c
1048010473
10474+INTEL IXP4XX CRYPTO SUPPORT
10475+M: Corentin Labbe <clabbe@baylibre.com>
10476+L: linux-crypto@vger.kernel.org
10477+S: Maintained
10478+F: drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
10479+
1048110480 INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
1048210481 M: Krzysztof Halasa <khalasa@piap.pl>
1048310482 S: Maintained
@@ -10556,6 +10555,13 @@ F: drivers/hwmon/intel-m10-bmc-hwmon.c · 72 unmodified lines
1055610555 F: drivers/mfd/intel-m10-bmc*
1055710556 F: include/linux/mfd/intel-m10-bmc.h
1055810557
10558+INTEL MAX10 BMC SECURE UPDATES
10559+M: Russ Weight <russell.h.weight@intel.com>
10560+L: linux-fpga@vger.kernel.org
10561+S: Maintained
10562+F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
10563+F: drivers/fpga/intel-m10-bmc-sec-update.c
10564+
1055910565 INTEL P-Unit IPC DRIVER
1056010566 M: Zha Qipeng <qipeng.zha@intel.com>
1056110567 L: platform-driver-x86@vger.kernel.org
@@ -10603,6 +10609,13 @@ L: linux-pm@vger.kernel.org · 41 unmodified lines
1060310609 S: Supported
1060410610 F: drivers/cpufreq/intel_pstate.c
1060510611
10612+INTEL PTP DFL ToD DRIVER
10613+M: Tianfei Zhang <tianfei.zhang@intel.com>
10614+L: linux-fpga@vger.kernel.org
10615+L: netdev@vger.kernel.org
10616+S: Maintained
10617+F: drivers/ptp/ptp_dfl_tod.c
10618+
1060610619 INTEL QUADRATURE ENCODER PERIPHERAL DRIVER
1060710620 M: Jarkko Nikula <jarkko.nikula@linux.intel.com>
1060810621 L: linux-iio@vger.kernel.org
@@ -10621,6 +10634,21 @@ F: drivers/platform/x86/intel/sdsi.c · 12 unmodified lines
1062110634 F: tools/arch/x86/intel_sdsi/
1062210635 F: tools/testing/selftests/drivers/sdsi/
1062310636
10637+INTEL SGX
10638+M: Jarkko Sakkinen <jarkko@kernel.org>
10639+R: Dave Hansen <dave.hansen@linux.intel.com>
10640+L: linux-sgx@vger.kernel.org
10641+S: Supported
10642+Q: https://patchwork.kernel.org/project/intel-sgx/list/
10643+T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/sgx
10644+F: Documentation/arch/x86/sgx.rst
10645+F: arch/x86/entry/vdso/vsgx.S
10646+F: arch/x86/include/asm/sgx.h
10647+F: arch/x86/include/uapi/asm/sgx.h
10648+F: arch/x86/kernel/cpu/sgx/*
10649+F: tools/testing/selftests/sgx/*
10650+K: \bSGX_
10651+
1062410652 INTEL SKYLAKE INT3472 ACPI DEVICE DRIVER
1062510653 M: Daniel Scally <djrscally@gmail.com>
1062610654 S: Maintained
@@ -10638,13 +10666,13 @@ INTEL STRATIX10 FIRMWARE DRIVERS · 11 unmodified lines
1063810666 M: Dinh Nguyen <dinguyen@kernel.org>
1063910667 L: linux-kernel@vger.kernel.org
1064010668 S: Maintained
10669+T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
1064110670 F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
1064210671 F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
1064310672 F: drivers/firmware/stratix10-rsu.c
1064410673 F: drivers/firmware/stratix10-svc.c
1064510674 F: include/linux/firmware/intel/stratix10-smc.h
1064610675 F: include/linux/firmware/intel/stratix10-svc-client.h
10647−T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
1064810676
1064910677 INTEL TELEMETRY DRIVER
1065010678 M: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
@@ -10729,21 +10757,6 @@ F: Documentation/arch/x86/intel_txt.rst · 78 unmodified lines
1072910757 F: arch/x86/kernel/tboot.c
1073010758 F: include/linux/tboot.h
1073110759
10732−INTEL SGX
10733−M: Jarkko Sakkinen <jarkko@kernel.org>
10734−R: Dave Hansen <dave.hansen@linux.intel.com>
10735−L: linux-sgx@vger.kernel.org
10736−S: Supported
10737−Q: https://patchwork.kernel.org/project/intel-sgx/list/
10738−T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/sgx
10739−F: Documentation/arch/x86/sgx.rst
10740−F: arch/x86/entry/vdso/vsgx.S
10741−F: arch/x86/include/asm/sgx.h
10742−F: arch/x86/include/uapi/asm/sgx.h
10743−F: arch/x86/kernel/cpu/sgx/*
10744−F: tools/testing/selftests/sgx/*
10745−K: \bSGX_
10746−
1074710760 INTERCONNECT API
1074810761 M: Georgi Djakov <djakov@kernel.org>
1074910762 L: linux-pm@vger.kernel.org
@@ -10812,18 +10825,6 @@ F: drivers/iommu/dma-iommu.h · 62 unmodified lines
1081210825 F: drivers/iommu/iova.c
1081310826 F: include/linux/iova.h
1081410827
10815−IOMMUFD
10816−M: Jason Gunthorpe <jgg@nvidia.com>
10817−M: Kevin Tian <kevin.tian@intel.com>
10818−L: iommu@lists.linux.dev
10819−S: Maintained
10820−T: git git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git
10821−F: Documentation/userspace-api/iommufd.rst
10822−F: drivers/iommu/iommufd/
10823−F: include/linux/iommufd.h
10824−F: include/uapi/linux/iommufd.h
10825−F: tools/testing/selftests/iommu/
10826−
1082710828 IOMMU SUBSYSTEM
1082810829 M: Joerg Roedel <joro@8bytes.org>
1082910830 M: Will Deacon <will@kernel.org>
@@ -10839,6 +10840,18 @@ F: include/linux/iova.h · 9 unmodified lines
1083910840 F: include/linux/of_iommu.h
1084010841 F: include/uapi/linux/iommu.h
1084110842
10843+IOMMUFD
10844+M: Jason Gunthorpe <jgg@nvidia.com>
10845+M: Kevin Tian <kevin.tian@intel.com>
10846+L: iommu@lists.linux.dev
10847+S: Maintained
10848+T: git git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git
10849+F: Documentation/userspace-api/iommufd.rst
10850+F: drivers/iommu/iommufd/
10851+F: include/linux/iommufd.h
10852+F: include/uapi/linux/iommufd.h
10853+F: tools/testing/selftests/iommu/
10854+
1084210855 IOSYS-MAP HELPERS
1084310856 M: Thomas Zimmermann <tzimmermann@suse.de>
1084410857 L: dri-devel@lists.freedesktop.org
@@ -10853,11 +10866,11 @@ L: io-uring@vger.kernel.org · 8 unmodified lines
1085310866 S: Maintained
1085410867 T: git git://git.kernel.dk/linux-block
1085510868 T: git git://git.kernel.dk/liburing
10856−F: io_uring/
1085710869 F: include/linux/io_uring.h
1085810870 F: include/linux/io_uring_types.h
1085910871 F: include/trace/events/io_uring.h
1086010872 F: include/uapi/linux/io_uring.h
10873+F: io_uring/
1086110874 F: tools/io_uring/
1086210875
1086310876 IPMI SUBSYSTEM
@@ -10866,8 +10879,8 @@ L: openipmi-developer@lists.sourceforge.net (moderated for non-subscribers) · 2 unmodified lines
1086610879 S: Supported
1086710880 W: http://openipmi.sourceforge.net/
1086810881 T: git https://github.com/cminyard/linux-ipmi.git for-next
10869−F: Documentation/driver-api/ipmi.rst
1087010882 F: Documentation/devicetree/bindings/ipmi/
10883+F: Documentation/driver-api/ipmi.rst
1087110884 F: drivers/char/ipmi/
1087210885 F: include/linux/ipmi*
1087310886 F: include/uapi/linux/ipmi*
@@ -10919,8 +10932,8 @@ M: Thomas Gleixner <tglx@linutronix.de> · 45 unmodified lines
1091910932 L: linux-kernel@vger.kernel.org
1092010933 S: Maintained
1092110934 T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
10922−F: kernel/irq/
1092310935 F: include/linux/group_cpus.h
10936+F: kernel/irq/
1092410937 F: lib/group_cpus.c
1092510938
1092610939 IRQCHIP DRIVERS
@@ -11258,6 +11271,7 @@ L: linux-nfs@vger.kernel.org · 331 unmodified lines
1125811271 S: Supported
1125911272 W: http://nfs.sourceforge.net/
1126011273 T: git git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux.git
11274+F: Documentation/filesystems/nfs/
1126111275 F: fs/exportfs/
1126211276 F: fs/lockd/
1126311277 F: fs/nfs_common/
@@ -11273,7 +11287,6 @@ F: include/trace/misc/sunrpc.h · 9 unmodified lines
1127311287 F: include/uapi/linux/nfsd/
1127411288 F: include/uapi/linux/sunrpc/
1127511289 F: net/sunrpc/
11276−F: Documentation/filesystems/nfs/
1127711290
1127811291 KERNEL REGRESSIONS
1127911292 M: Thorsten Leemhuis <linux@leemhuis.info>
@@ -11388,83 +11401,42 @@ F: arch/riscv/include/asm/kvm* · 108 unmodified lines
1138811401 F: arch/riscv/include/uapi/asm/kvm*
1138911402 F: arch/riscv/kvm/
1139011403 F: tools/testing/selftests/kvm/*/riscv/
11391−
11392−KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
11393−M: Christian Borntraeger <borntraeger@linux.ibm.com>
11394−M: Janosch Frank <frankja@linux.ibm.com>
11395−M: Claudio Imbrenda <imbrenda@linux.ibm.com>
11396−R: David Hildenbrand <david@redhat.com>
11397−L: kvm@vger.kernel.org
11398−S: Supported
11399−T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
11400−F: Documentation/virt/kvm/s390*
11401−F: arch/s390/include/asm/gmap.h
11402−F: arch/s390/include/asm/kvm*
11403−F: arch/s390/include/uapi/asm/kvm*
11404−F: arch/s390/include/uapi/asm/uvdevice.h
11405−F: arch/s390/kernel/uv.c
11406−F: arch/s390/kvm/
11407−F: arch/s390/mm/gmap.c
11408−F: drivers/s390/char/uvdevice.c
11409−F: tools/testing/selftests/drivers/s390x/uvdevice/
11410−F: tools/testing/selftests/kvm/*/s390x/
11411−F: tools/testing/selftests/kvm/s390x/
11412−
11413−KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
11414−M: Sean Christopherson <seanjc@google.com>
11415−M: Paolo Bonzini <pbonzini@redhat.com>
11416−L: kvm@vger.kernel.org
11417−S: Supported
11418−T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11419−F: arch/x86/include/asm/kvm*
11420−F: arch/x86/include/asm/svm.h
11421−F: arch/x86/include/asm/vmx*.h
11422−F: arch/x86/include/uapi/asm/kvm*
11423−F: arch/x86/include/uapi/asm/svm.h
11424−F: arch/x86/include/uapi/asm/vmx.h
11425−F: arch/x86/kvm/
11426−F: arch/x86/kvm/*/
11427−
11428−KVM PARAVIRT (KVM/paravirt)
11429−M: Paolo Bonzini <pbonzini@redhat.com>
11430−R: Wanpeng Li <wanpengli@tencent.com>
11431−R: Vitaly Kuznetsov <vkuznets@redhat.com>
11432−L: kvm@vger.kernel.org
11433−S: Supported
11434−T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11435−F: arch/x86/kernel/kvm.c
11436−F: arch/x86/kernel/kvmclock.c
11437−F: arch/x86/include/asm/pvclock-abi.h
11438−F: include/linux/kvm_para.h
11439−F: include/uapi/linux/kvm_para.h
11440−F: include/uapi/asm-generic/kvm_para.h
11441−F: include/asm-generic/kvm_para.h
11442−F: arch/um/include/asm/kvm_para.h
11443−F: arch/x86/include/asm/kvm_para.h
11444−F: arch/x86/include/uapi/asm/kvm_para.h
11445−
11446−KVM X86 HYPER-V (KVM/hyper-v)
11447−M: Vitaly Kuznetsov <vkuznets@redhat.com>
11448−M: Sean Christopherson <seanjc@google.com>
11449−M: Paolo Bonzini <pbonzini@redhat.com>
11404+
11405+KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
11406+M: Christian Borntraeger <borntraeger@linux.ibm.com>
11407+M: Janosch Frank <frankja@linux.ibm.com>
11408+M: Claudio Imbrenda <imbrenda@linux.ibm.com>
11409+R: David Hildenbrand <david@redhat.com>
1145011410 L: kvm@vger.kernel.org
1145111411 S: Supported
11452−T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11453−F: arch/x86/kvm/hyperv.*
11454−F: arch/x86/kvm/kvm_onhyperv.*
11455−F: arch/x86/kvm/svm/hyperv.*
11456−F: arch/x86/kvm/svm/svm_onhyperv.*
11457−F: arch/x86/kvm/vmx/hyperv.*
11412+T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
11413+F: Documentation/virt/kvm/s390*
11414+F: arch/s390/include/asm/gmap.h
11415+F: arch/s390/include/asm/kvm*
11416+F: arch/s390/include/uapi/asm/kvm*
11417+F: arch/s390/include/uapi/asm/uvdevice.h
11418+F: arch/s390/kernel/uv.c
11419+F: arch/s390/kvm/
11420+F: arch/s390/mm/gmap.c
11421+F: drivers/s390/char/uvdevice.c
11422+F: tools/testing/selftests/drivers/s390x/uvdevice/
11423+F: tools/testing/selftests/kvm/*/s390x/
11424+F: tools/testing/selftests/kvm/s390x/
1145811425
11459−KVM X86 Xen (KVM/Xen)
11460−M: David Woodhouse <dwmw2@infradead.org>
11461−M: Paul Durrant <paul@xen.org>
11426+KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
1146211427 M: Sean Christopherson <seanjc@google.com>
1146311428 M: Paolo Bonzini <pbonzini@redhat.com>
1146411429 L: kvm@vger.kernel.org
1146511430 S: Supported
1146611431 T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11467−F: arch/x86/kvm/xen.*
11432+F: arch/x86/include/asm/kvm*
11433+F: arch/x86/include/asm/svm.h
11434+F: arch/x86/include/asm/vmx*.h
11435+F: arch/x86/include/uapi/asm/kvm*
11436+F: arch/x86/include/uapi/asm/svm.h
11437+F: arch/x86/include/uapi/asm/vmx.h
11438+F: arch/x86/kvm/
11439+F: arch/x86/kvm/*/
1146811440
1146911441 KERNFS
1147011442 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@@ -11504,14 +11476,6 @@ F: include/keys/trusted-type.h · 33 unmodified lines
1150411476 F: include/keys/trusted_tpm.h
1150511477 F: security/keys/trusted-keys/
1150611478
11507−KEYS-TRUSTED-TEE
11508−M: Sumit Garg <sumit.garg@linaro.org>
11509−L: linux-integrity@vger.kernel.org
11510−L: keyrings@vger.kernel.org
11511−S: Supported
11512−F: include/keys/trusted_tee.h
11513−F: security/keys/trusted-keys/trusted_tee.c
11514−
1151511479 KEYS-TRUSTED-CAAM
1151611480 M: Ahmad Fatoum <a.fatoum@pengutronix.de>
1151711481 R: Pengutronix Kernel Team <kernel@pengutronix.de>
@@ -11521,6 +11485,14 @@ S: Maintained · 3 unmodified lines
1152111485 F: include/keys/trusted_caam.h
1152211486 F: security/keys/trusted-keys/trusted_caam.c
1152311487
11488+KEYS-TRUSTED-TEE
11489+M: Sumit Garg <sumit.garg@linaro.org>
11490+L: linux-integrity@vger.kernel.org
11491+L: keyrings@vger.kernel.org
11492+S: Supported
11493+F: include/keys/trusted_tee.h
11494+F: security/keys/trusted-keys/trusted_tee.c
11495+
1152411496 KEYS/KEYRINGS
1152511497 M: David Howells <dhowells@redhat.com>
1152611498 M: Jarkko Sakkinen <jarkko@kernel.org>
@@ -11583,8 +11555,8 @@ L: linux-amlogic@lists.infradead.org · 56 unmodified lines
1158311555 S: Maintained
1158411556 F: Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
1158511557 F: drivers/mfd/khadas-mcu.c
11586−F: include/linux/mfd/khadas-mcu.h
1158711558 F: drivers/thermal/khadas_mcu_fan.c
11559+F: include/linux/mfd/khadas-mcu.h
1158811560
1158911561 KIONIX/ROHM KX022A ACCELEROMETER
1159011562 M: Matti Vaittinen <mazziesaccount@gmail.com>
@@ -11621,8 +11593,8 @@ M: "David S. Miller" <davem@davemloft.net> · 30 unmodified lines
1162111593 M: Masami Hiramatsu <mhiramat@kernel.org>
1162211594 L: linux-kernel@vger.kernel.org
1162311595 L: linux-trace-kernel@vger.kernel.org
11624−Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
1162511596 S: Maintained
11597+Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
1162611598 T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
1162711599 F: Documentation/trace/kprobes.rst
1162811600 F: include/asm-generic/kprobes.h
@@ -11656,6 +11628,47 @@ S: Maintained · 27 unmodified lines
1165611628 F: Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml
1165711629 F: drivers/video/backlight/ktz8866.c
1165811630
11631+KVM PARAVIRT (KVM/paravirt)
11632+M: Paolo Bonzini <pbonzini@redhat.com>
11633+R: Wanpeng Li <wanpengli@tencent.com>
11634+R: Vitaly Kuznetsov <vkuznets@redhat.com>
11635+L: kvm@vger.kernel.org
11636+S: Supported
11637+T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11638+F: arch/um/include/asm/kvm_para.h
11639+F: arch/x86/include/asm/kvm_para.h
11640+F: arch/x86/include/asm/pvclock-abi.h
11641+F: arch/x86/include/uapi/asm/kvm_para.h
11642+F: arch/x86/kernel/kvm.c
11643+F: arch/x86/kernel/kvmclock.c
11644+F: include/asm-generic/kvm_para.h
11645+F: include/linux/kvm_para.h
11646+F: include/uapi/asm-generic/kvm_para.h
11647+F: include/uapi/linux/kvm_para.h
11648+
11649+KVM X86 HYPER-V (KVM/hyper-v)
11650+M: Vitaly Kuznetsov <vkuznets@redhat.com>
11651+M: Sean Christopherson <seanjc@google.com>
11652+M: Paolo Bonzini <pbonzini@redhat.com>
11653+L: kvm@vger.kernel.org
11654+S: Supported
11655+T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11656+F: arch/x86/kvm/hyperv.*
11657+F: arch/x86/kvm/kvm_onhyperv.*
11658+F: arch/x86/kvm/svm/hyperv.*
11659+F: arch/x86/kvm/svm/svm_onhyperv.*
11660+F: arch/x86/kvm/vmx/hyperv.*
11661+
11662+KVM X86 Xen (KVM/Xen)
11663+M: David Woodhouse <dwmw2@infradead.org>
11664+M: Paul Durrant <paul@xen.org>
11665+M: Sean Christopherson <seanjc@google.com>
11666+M: Paolo Bonzini <pbonzini@redhat.com>
11667+L: kvm@vger.kernel.org
11668+S: Supported
11669+T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
11670+F: arch/x86/kvm/xen.*
11671+
1165911672 L3MDEV
1166011673 M: David Ahern <dsahern@kernel.org>
1166111674 L: netdev@vger.kernel.org
@@ -11897,9 +11910,9 @@ F: scripts/spdxexclude · 235 unmodified lines
1189711910 LINEAR RANGES HELPERS
1189811911 M: Mark Brown <broonie@kernel.org>
1189911912 R: Matti Vaittinen <mazziesaccount@gmail.com>
11913+F: include/linux/linear_range.h
1190011914 F: lib/linear_ranges.c
1190111915 F: lib/test_linear_ranges.c
11902−F: include/linux/linear_range.h
1190311916
1190411917 LINUX FOR POWER MACINTOSH
1190511918 M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
@@ -12026,11 +12039,11 @@ M: Joel Stanley <joel@jms.id.au> · 120 unmodified lines
1202612039 S: Maintained
1202712040 F: Documentation/devicetree/bindings/*/litex,*.yaml
1202812041 F: arch/openrisc/boot/dts/or1klitex.dts
12029−F: include/linux/litex.h
12030−F: drivers/tty/serial/liteuart.c
12031−F: drivers/soc/litex/*
12032−F: drivers/net/ethernet/litex/*
1203312042 F: drivers/mmc/host/litex_mmc.c
12043+F: drivers/net/ethernet/litex/*
12044+F: drivers/soc/litex/*
12045+F: drivers/tty/serial/liteuart.c
12046+F: include/linux/litex.h
1203412047 N: litex
1203512048
1203612049 LIVE PATCHING
@@ -12159,10 +12172,17 @@ R: WANG Xuerui <kernel@xen0n.name> · 122 unmodified lines
1215912172 L: loongarch@lists.linux.dev
1216012173 S: Maintained
1216112174 T: git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
12162−F: arch/loongarch/
12163−F: drivers/*/*loongarch*
1216412175 F: Documentation/loongarch/
1216512176 F: Documentation/translations/zh_CN/loongarch/
12177+F: arch/loongarch/
12178+F: drivers/*/*loongarch*
12179+
12180+LOONGSON GPIO DRIVER
12181+M: Yinbo Zhu <zhuyinbo@loongson.cn>
12182+L: linux-gpio@vger.kernel.org
12183+S: Maintained
12184+F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
12185+F: drivers/gpio/gpio-loongson-64bit.c
1216612186
1216712187 LOONGSON LS2X I2C DRIVER
1216812188 M: Binbin Zhou <zhoubinbin@loongson.cn>
@@ -12171,6 +12191,14 @@ S: Maintained · 2 unmodified lines
1217112191 F: Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml
1217212192 F: drivers/i2c/busses/i2c-ls2x.c
1217312193
12194+LOONGSON-2 SOC SERIES CLOCK DRIVER
12195+M: Yinbo Zhu <zhuyinbo@loongson.cn>
12196+L: linux-clk@vger.kernel.org
12197+S: Maintained
12198+F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
12199+F: drivers/clk/clk-loongson2.c
12200+F: include/dt-bindings/clock/loongson,ls2k-clk.h
12201+
1217412202 LOONGSON-2 SOC SERIES GUTS DRIVER
1217512203 M: Yinbo Zhu <zhuyinbo@loongson.cn>
1217612204 L: loongarch@lists.linux.dev
@@ -12186,21 +12214,6 @@ S: Maintained · 9 unmodified lines
1218612214 F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml
1218712215 F: drivers/pinctrl/pinctrl-loongson2.c
1218812216
12189−LOONGSON GPIO DRIVER
12190−M: Yinbo Zhu <zhuyinbo@loongson.cn>
12191−L: linux-gpio@vger.kernel.org
12192−S: Maintained
12193−F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
12194−F: drivers/gpio/gpio-loongson-64bit.c
12195−
12196−LOONGSON-2 SOC SERIES CLOCK DRIVER
12197−M: Yinbo Zhu <zhuyinbo@loongson.cn>
12198−L: linux-clk@vger.kernel.org
12199−S: Maintained
12200−F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
12201−F: drivers/clk/clk-loongson2.c
12202−F: include/dt-bindings/clock/loongson,ls2k-clk.h
12203−
1220412217 LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
1220512218 M: Sathya Prakash <sathya.prakash@broadcom.com>
1220612219 M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
@@ -12361,20 +12374,26 @@ MAILBOX API · 154 unmodified lines
1236112374 M: Jassi Brar <jassisinghbrar@gmail.com>
1236212375 L: linux-kernel@vger.kernel.org
1236312376 S: Maintained
12377+F: Documentation/devicetree/bindings/mailbox/
1236412378 F: drivers/mailbox/
12379+F: include/dt-bindings/mailbox/
1236512380 F: include/linux/mailbox_client.h
1236612381 F: include/linux/mailbox_controller.h
12367−F: include/dt-bindings/mailbox/
12368−F: Documentation/devicetree/bindings/mailbox/
1236912382
1237012383 MAILBOX ARM MHUv2
1237112384 M: Viresh Kumar <viresh.kumar@linaro.org>
1237212385 M: Tushar Khandelwal <Tushar.Khandelwal@arm.com>
1237312386 L: linux-kernel@vger.kernel.org
1237412387 S: Maintained
12388+F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
1237512389 F: drivers/mailbox/arm_mhuv2.c
1237612390 F: include/linux/mailbox/arm_mhuv2_message.h
12377−F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
12391+
12392+MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
12393+M: Michael Kerrisk <mtk.manpages@gmail.com>
12394+L: linux-man@vger.kernel.org
12395+S: Maintained
12396+W: http://www.kernel.org/doc/man-pages
1237812397
1237912398 MANAGEMENT COMPONENT TRANSPORT PROTOCOL (MCTP)
1238012399 M: Jeremy Kerr <jk@codeconstruct.com.au>
@@ -12388,12 +12407,6 @@ F: include/net/mctpdevice.h · 7 unmodified lines
1238812407 F: include/net/netns/mctp.h
1238912408 F: net/mctp/
1239012409
12391−MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
12392−M: Michael Kerrisk <mtk.manpages@gmail.com>
12393−L: linux-man@vger.kernel.org
12394−S: Maintained
12395−W: http://www.kernel.org/doc/man-pages
12396−
1239712410 MAPLE TREE
1239812411 M: Liam R. Howlett <Liam.Howlett@oracle.com>
1239912412 L: linux-mm@kvack.org
@@ -12425,8 +12438,8 @@ F: include/linux/platform_data/mv88e6xxx.h · 25 unmodified lines
1242512438 MARVELL ARMADA 3700 PHY DRIVERS
1242612439 M: Miquel Raynal <miquel.raynal@bootlin.com>
1242712440 S: Maintained
12428−F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
1242912441 F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
12442+F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
1243012443 F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
1243112444 F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c
1243212445
@@ -12528,6 +12541,13 @@ S: Maintained · 95 unmodified lines
1252812541 F: Documentation/devicetree/bindings/mtd/marvell-nand.txt
1252912542 F: drivers/mtd/nand/raw/marvell_nand.c
1253012543
12544+MARVELL OCTEON ENDPOINT DRIVER
12545+M: Veerasenareddy Burru <vburru@marvell.com>
12546+M: Abhijit Ayarekar <aayarekar@marvell.com>
12547+L: netdev@vger.kernel.org
12548+S: Supported
12549+F: drivers/net/ethernet/marvell/octeon_ep
12550+
1253112551 MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
1253212552 M: Sunil Goutham <sgoutham@marvell.com>
1253312553 M: Geetha sowjanya <gakula@marvell.com>
@@ -12575,13 +12595,6 @@ S: Supported · 41 unmodified lines
1257512595 F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
1257612596 F: drivers/mmc/host/sdhci-xenon*
1257712597
12578−MARVELL OCTEON ENDPOINT DRIVER
12579−M: Veerasenareddy Burru <vburru@marvell.com>
12580−M: Abhijit Ayarekar <aayarekar@marvell.com>
12581−L: netdev@vger.kernel.org
12582−S: Supported
12583−F: drivers/net/ethernet/marvell/octeon_ep
12584−
1258512598 MATROX FRAMEBUFFER DRIVER
1258612599 L: linux-fbdev@vger.kernel.org
1258712600 S: Orphan
@@ -12781,12 +12794,6 @@ L: netdev@vger.kernel.org · 193 unmodified lines
1278112794 S: Supported
1278212795 F: drivers/net/phy/mxl-gpy.c
1278312796
12784−MCBA MICROCHIP CAN BUS ANALYZER TOOL DRIVER
12785−R: Yasushi SHOJI <yashi@spacecubics.com>
12786−L: linux-can@vger.kernel.org
12787−S: Maintained
12788−F: drivers/net/can/usb/mcba_usb.c
12789−
1279012797 MCAN MMIO DEVICE DRIVER
1279112798 M: Chandrasekar Ramakrishnan <rcsekar@samsung.com>
1279212799 L: linux-can@vger.kernel.org
@@ -12796,6 +12803,12 @@ F: drivers/net/can/m_can/m_can.c · 3 unmodified lines
1279612803 F: drivers/net/can/m_can/m_can.h
1279712804 F: drivers/net/can/m_can/m_can_platform.c
1279812805
12806+MCBA MICROCHIP CAN BUS ANALYZER TOOL DRIVER
12807+R: Yasushi SHOJI <yashi@spacecubics.com>
12808+L: linux-can@vger.kernel.org
12809+S: Maintained
12810+F: drivers/net/can/usb/mcba_usb.c
12811+
1279912812 MCP2221A MICROCHIP USB-HID TO I2C BRIDGE DRIVER
1280012813 M: Rishi Gupta <gupt21@gmail.com>
1280112814 L: linux-i2c@vger.kernel.org
@@ -13204,13 +13217,6 @@ S: Maintained · 402 unmodified lines
1320413217 F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
1320513218 F: drivers/clk/ralink/clk-mt7621.c
1320613219
13207−MEDIATEK MT7621/28/88 I2C DRIVER
13208−M: Stefan Roese <sr@denx.de>
13209−L: linux-i2c@vger.kernel.org
13210−S: Maintained
13211−F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
13212−F: drivers/i2c/busses/i2c-mt7621.c
13213−
1321413220 MEDIATEK MT7621 PCIE CONTROLLER DRIVER
1321513221 M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
1321613222 S: Maintained
@@ -13223,6 +13229,13 @@ S: Maintained · 6 unmodified lines
1322313229 F: Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
1322413230 F: drivers/phy/ralink/phy-mt7621-pci.c
1322513231
13232+MEDIATEK MT7621/28/88 I2C DRIVER
13233+M: Stefan Roese <sr@denx.de>
13234+L: linux-i2c@vger.kernel.org
13235+S: Maintained
13236+F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
13237+F: drivers/i2c/busses/i2c-mt7621.c
13238+
1322613239 MEDIATEK NAND CONTROLLER DRIVER
1322713240 L: linux-mtd@lists.infradead.org
1322813241 S: Orphan
@@ -13482,10 +13495,22 @@ MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA · 253 unmodified lines
1348213495 M: Dmitry Osipenko <digetx@gmail.com>
1348313496 L: linux-pm@vger.kernel.org
1348413497 L: linux-tegra@vger.kernel.org
13485−T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
1348613498 S: Maintained
13499+T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
1348713500 F: drivers/devfreq/tegra30-devfreq.c
1348813501
13502+MEMORY HOT(UN)PLUG
13503+M: David Hildenbrand <david@redhat.com>
13504+M: Oscar Salvador <osalvador@suse.de>
13505+L: linux-mm@kvack.org
13506+S: Maintained
13507+F: Documentation/admin-guide/mm/memory-hotplug.rst
13508+F: Documentation/core-api/memory-hotplug.rst
13509+F: drivers/base/memory.c
13510+F: include/linux/memory_hotplug.h
13511+F: mm/memory_hotplug.c
13512+F: tools/testing/selftests/memory-hotplug/
13513+
1348913514 MEMORY MANAGEMENT
1349013515 M: Andrew Morton <akpm@linux-foundation.org>
1349113516 L: linux-mm@kvack.org
@@ -13504,30 +13529,6 @@ F: mm/ · 12 unmodified lines
1350413529 F: tools/mm/
1350513530 F: tools/testing/selftests/mm/
1350613531
13507−VMALLOC
13508−M: Andrew Morton <akpm@linux-foundation.org>
13509−R: Uladzislau Rezki <urezki@gmail.com>
13510−R: Christoph Hellwig <hch@infradead.org>
13511−R: Lorenzo Stoakes <lstoakes@gmail.com>
13512−L: linux-mm@kvack.org
13513−S: Maintained
13514−W: http://www.linux-mm.org
13515−T: git git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
13516−F: include/linux/vmalloc.h
13517−F: mm/vmalloc.c
13518−
13519−MEMORY HOT(UN)PLUG
13520−M: David Hildenbrand <david@redhat.com>
13521−M: Oscar Salvador <osalvador@suse.de>
13522−L: linux-mm@kvack.org
13523−S: Maintained
13524−F: Documentation/admin-guide/mm/memory-hotplug.rst
13525−F: Documentation/core-api/memory-hotplug.rst
13526−F: drivers/base/memory.c
13527−F: include/linux/memory_hotplug.h
13528−F: mm/memory_hotplug.c
13529−F: tools/testing/selftests/memory-hotplug/
13530−
1353113532 MEMORY TECHNOLOGY DEVICES (MTD)
1353213533 M: Miquel Raynal <miquel.raynal@bootlin.com>
1353313534 M: Richard Weinberger <richard@nod.at>
@@ -13638,6 +13639,12 @@ W: http://www.monstr.eu/fdt/ · 104 unmodified lines
1363813639 T: git git://git.monstr.eu/linux-2.6-microblaze.git
1363913640 F: arch/microblaze/
1364013641
13642+MICROBLAZE TMR INJECT
13643+M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13644+S: Supported
13645+F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
13646+F: drivers/misc/xilinx_tmr_inject.c
13647+
1364113648 MICROBLAZE TMR MANAGER
1364213649 M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
1364313650 S: Supported
@@ -13645,12 +13652,6 @@ F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager · 1 unmodified line
1364513652 F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
1364613653 F: drivers/misc/xilinx_tmr_manager.c
1364713654
13648−MICROBLAZE TMR INJECT
13649−M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13650−S: Supported
13651−F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
13652−F: drivers/misc/xilinx_tmr_inject.c
13653−
1365413655 MICROCHIP AT91 DMA DRIVERS
1365513656 M: Ludovic Desroches <ludovic.desroches@microchip.com>
1365613657 M: Tudor Ambarus <tudor.ambarus@linaro.org>
@@ -13725,11 +13726,11 @@ M: Eugen Hristev <eugen.hristev@microchip.com> · 68 unmodified lines
1372513726 L: linux-media@vger.kernel.org
1372613727 S: Supported
1372713728 F: Documentation/devicetree/bindings/media/atmel,isc.yaml
13728−F: Documentation/devicetree/bindings/media/microchip,xisc.yaml
13729−F: drivers/staging/media/deprecated/atmel/atmel-isc*
13730−F: drivers/staging/media/deprecated/atmel/atmel-sama*-isc*
13729+F: Documentation/devicetree/bindings/media/microchip,xisc.yaml
1373113730 F: drivers/media/platform/microchip/microchip-isc*
1373213731 F: drivers/media/platform/microchip/microchip-sama*-isc*
13732+F: drivers/staging/media/deprecated/atmel/atmel-isc*
13733+F: drivers/staging/media/deprecated/atmel/atmel-sama*-isc*
1373313734 F: include/linux/atmel-isc-media.h
1373413735
1373513736 MICROCHIP ISI DRIVER
@@ -13751,13 +13752,6 @@ F: include/linux/dsa/ksz_common.h · 15 unmodified lines
1375113752 F: include/linux/platform_data/microchip-ksz.h
1375213753 F: net/dsa/tag_ksz.c
1375313754
13754−MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER
13755−M: Arun Ramadoss <arun.ramadoss@microchip.com>
13756−R: UNGLinuxDriver@microchip.com
13757−L: netdev@vger.kernel.org
13758−S: Maintained
13759−F: drivers/net/phy/microchip_t1.c
13760−
1376113755 MICROCHIP LAN743X ETHERNET DRIVER
1376213756 M: Bryan Whitehead <bryan.whitehead@microchip.com>
1376313757 M: UNGLinuxDriver@microchip.com
@@ -13765,6 +13759,13 @@ L: netdev@vger.kernel.org · 1 unmodified line
1376513759 S: Maintained
1376613760 F: drivers/net/ethernet/microchip/lan743x_*
1376713761
13762+MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER
13763+M: Arun Ramadoss <arun.ramadoss@microchip.com>
13764+R: UNGLinuxDriver@microchip.com
13765+L: netdev@vger.kernel.org
13766+S: Maintained
13767+F: drivers/net/phy/microchip_t1.c
13768+
1376813769 MICROCHIP LAN966X ETHERNET DRIVER
1376913770 M: Horatiu Vultur <horatiu.vultur@microchip.com>
1377013771 M: UNGLinuxDriver@microchip.com
@@ -13806,14 +13807,6 @@ S: Supported · 35 unmodified lines
1380613807 F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
1380713808 F: drivers/mtd/nand/raw/atmel/*
1380813809
13809−MICROCHIP PCI1XXXX GP DRIVER
13810−M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
13811−L: linux-gpio@vger.kernel.org
13812−S: Supported
13813−F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
13814−F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
13815−F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
13816−
1381713810 MICROCHIP OTPC DRIVER
1381813811 M: Claudiu Beznea <claudiu.beznea@microchip.com>
1381913812 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -13822,6 +13815,14 @@ F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml · 2 unmodified lines
1382213815 F: drivers/nvmem/microchip-otpc.c
1382313816 F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
1382413817
13818+MICROCHIP PCI1XXXX GP DRIVER
13819+M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
13820+L: linux-gpio@vger.kernel.org
13821+S: Supported
13822+F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
13823+F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
13824+F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
13825+
1382513826 MICROCHIP PCI1XXXX I2C DRIVER
1382613827 M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
1382713828 M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
@@ -13837,6 +13838,14 @@ L: linux-serial@vger.kernel.org · 9 unmodified lines
1383713838 S: Maintained
1383813839 F: drivers/tty/serial/8250/8250_pci1xxxx.c
1383913840
13841+MICROCHIP POLARFIRE FPGA DRIVERS
13842+M: Conor Dooley <conor.dooley@microchip.com>
13843+R: Ivan Bornyakov <i.bornyakov@metrotek.ru>
13844+L: linux-fpga@vger.kernel.org
13845+S: Supported
13846+F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
13847+F: drivers/fpga/microchip-spi.c
13848+
1384013849 MICROCHIP PWM DRIVER
1384113850 M: Claudiu Beznea <claudiu.beznea@microchip.com>
1384213851 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -13858,6 +13867,12 @@ M: Claudiu Beznea <claudiu.beznea@microchip.com> · 15 unmodified lines
1385813867 S: Supported
1385913868 F: drivers/power/reset/at91-sama5d2_shdwc.c
1386013869
13870+MICROCHIP SOC DRIVERS
13871+M: Conor Dooley <conor@kernel.org>
13872+S: Supported
13873+T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
13874+F: drivers/soc/microchip/
13875+
1386113876 MICROCHIP SPI DRIVER
1386213877 M: Tudor Ambarus <tudor.ambarus@linaro.org>
1386313878 S: Supported
@@ -13871,11 +13886,12 @@ F: Documentation/devicetree/bindings/misc/atmel-ssc.txt · 7 unmodified lines
1387113886 F: drivers/misc/atmel-ssc.c
1387213887 F: include/linux/atmel-ssc.h
1387313888
13874−MICROCHIP SOC DRIVERS
13875−M: Conor Dooley <conor@kernel.org>
13876−S: Supported
13877−T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
13878−F: drivers/soc/microchip/
13889+Microchip Timer Counter Block (TCB) Capture Driver
13890+M: Kamel Bouhara <kamel.bouhara@bootlin.com>
13891+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
13892+L: linux-iio@vger.kernel.org
13893+S: Maintained
13894+F: drivers/counter/microchip-tcb-capture.c
1387913895
1388013896 MICROCHIP USB251XB DRIVER
1388113897 M: Richard Leitner <richard.leitner@skidata.com>
@@ -13992,6 +14008,12 @@ L: platform-driver-x86@vger.kernel.org · 110 unmodified lines
1399214008 S: Supported
1399314009 F: drivers/platform/surface/surfacepro3_button.c
1399414010
14011+MICROSOFT SURFACE SYSTEM AGGREGATOR HUB DRIVER
14012+M: Maximilian Luz <luzmaximilian@gmail.com>
14013+L: platform-driver-x86@vger.kernel.org
14014+S: Maintained
14015+F: drivers/platform/surface/surface_aggregator_hub.c
14016+
1399514017 MICROSOFT SURFACE SYSTEM AGGREGATOR SUBSYSTEM
1399614018 M: Maximilian Luz <luzmaximilian@gmail.com>
1399714019 L: platform-driver-x86@vger.kernel.org
@@ -14007,12 +14029,6 @@ F: include/linux/surface_acpi_notify.h · 9 unmodified lines
1400714029 F: include/linux/surface_aggregator/
1400814030 F: include/uapi/linux/surface_aggregator/
1400914031
14010−MICROSOFT SURFACE SYSTEM AGGREGATOR HUB DRIVER
14011−M: Maximilian Luz <luzmaximilian@gmail.com>
14012−L: platform-driver-x86@vger.kernel.org
14013−S: Maintained
14014−F: drivers/platform/surface/surface_aggregator_hub.c
14015−
1401614032 MICROTEK X6 SCANNER
1401714033 M: Oliver Neukum <oliver@neukum.org>
1401814034 S: Maintained
@@ -14178,11 +14194,11 @@ L: linux-modules@vger.kernel.org · 159 unmodified lines
1417814194 L: linux-kernel@vger.kernel.org
1417914195 S: Maintained
1418014196 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git modules-next
14181−F: include/linux/module.h
1418214197 F: include/linux/kmod.h
14198+F: include/linux/module.h
1418314199 F: kernel/module/
14184−F: scripts/module*
1418514200 F: lib/test_kmod.c
14201+F: scripts/module*
1418614202 F: tools/testing/selftests/kmod/
1418714203
1418814204 MONOLITHIC POWER SYSTEM PMIC DRIVER
@@ -14771,6 +14787,7 @@ L: linux-nfs@vger.kernel.org · 582 unmodified lines
1477114787 S: Maintained
1477214788 W: http://client.linux-nfs.org
1477314789 T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
14790+F: Documentation/filesystems/nfs/
1477414791 F: fs/lockd/
1477514792 F: fs/nfs/
1477614793 F: fs/nfs_common/
@@ -14780,7 +14797,6 @@ F: include/linux/sunrpc/ · 3 unmodified lines
1478014797 F: include/uapi/linux/nfs*
1478114798 F: include/uapi/linux/sunrpc/
1478214799 F: net/sunrpc/
14783−F: Documentation/filesystems/nfs/
1478414800
1478514801 NILFS2 FILESYSTEM
1478614802 M: Ryusuke Konishi <konishi.ryusuke@gmail.com>
@@ -14984,12 +15000,6 @@ F: drivers/nvme/target/auth.c · 197 unmodified lines
1498415000 F: drivers/nvme/target/fabrics-cmd-auth.c
1498515001 F: include/linux/nvme-auth.h
1498615002
14987−NVM EXPRESS HARDWARE MONITORING SUPPORT
14988−M: Guenter Roeck <linux@roeck-us.net>
14989−L: linux-nvme@lists.infradead.org
14990−S: Supported
14991−F: drivers/nvme/host/hwmon.c
14992−
1499315003 NVM EXPRESS FC TRANSPORT DRIVERS
1499415004 M: James Smart <james.smart@broadcom.com>
1499515005 L: linux-nvme@lists.infradead.org
@@ -15000,6 +15010,12 @@ F: drivers/nvme/target/fcloop.c · 4 unmodified lines
1500015010 F: include/linux/nvme-fc-driver.h
1500115011 F: include/linux/nvme-fc.h
1500215012
15013+NVM EXPRESS HARDWARE MONITORING SUPPORT
15014+M: Guenter Roeck <linux@roeck-us.net>
15015+L: linux-nvme@lists.infradead.org
15016+S: Supported
15017+F: drivers/nvme/host/hwmon.c
15018+
1500315019 NVM EXPRESS TARGET DRIVER
1500415020 M: Christoph Hellwig <hch@lst.de>
1500515021 M: Sagi Grimberg <sagi@grimberg.me>
@@ -15020,6 +15036,13 @@ F: drivers/nvmem/ · 14 unmodified lines
1502015036 F: include/linux/nvmem-consumer.h
1502115037 F: include/linux/nvmem-provider.h
1502215038
15039+NXP BLUETOOTH WIRELESS DRIVERS
15040+M: Amitkumar Karwar <amitkumar.karwar@nxp.com>
15041+M: Neeraj Kale <neeraj.sanjaykale@nxp.com>
15042+S: Maintained
15043+F: Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml
15044+F: drivers/bluetooth/btnxpuart.c
15045+
1502315046 NXP C45 TJA11XX PHY DRIVER
1502415047 M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
1502515048 L: netdev@vger.kernel.org
@@ -15045,16 +15068,17 @@ F: drivers/iio/gyro/fxas21002c_core.c · 19 unmodified lines
1504515068 F: drivers/iio/gyro/fxas21002c_i2c.c
1504615069 F: drivers/iio/gyro/fxas21002c_spi.c
1504715070
15048−NXP i.MX CLOCK DRIVERS
15049−M: Abel Vesa <abelvesa@kernel.org>
15050−R: Peng Fan <peng.fan@nxp.com>
15051−L: linux-clk@vger.kernel.org
15071+NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER
15072+M: Haibo Chen <haibo.chen@nxp.com>
15073+L: linux-iio@vger.kernel.org
1505215074 L: linux-imx@nxp.com
1505315075 S: Maintained
15054−T: git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx
15055−F: Documentation/devicetree/bindings/clock/imx*
15056−F: drivers/clk/imx/
15057−F: include/dt-bindings/clock/imx*
15076+F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml
15077+F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
15078+F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
15079+F: drivers/iio/adc/imx7d_adc.c
15080+F: drivers/iio/adc/imx93_adc.c
15081+F: drivers/iio/adc/vf610_adc.c
1505815082
1505915083 NXP i.MX 8M ISI DRIVER
1506015084 M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
@@ -15063,6 +15087,15 @@ S: Maintained · 2 unmodified lines
1506315087 F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
1506415088 F: drivers/media/platform/nxp/imx8-isi/
1506515089
15090+NXP i.MX 8MP DW100 V4L2 DRIVER
15091+M: Xavier Roumegue <xavier.roumegue@oss.nxp.com>
15092+L: linux-media@vger.kernel.org
15093+S: Maintained
15094+F: Documentation/devicetree/bindings/media/nxp,dw100.yaml
15095+F: Documentation/userspace-api/media/drivers/dw100.rst
15096+F: drivers/media/platform/nxp/dw100/
15097+F: include/uapi/linux/dw100.h
15098+
1506615099 NXP i.MX 8MQ DCSS DRIVER
1506715100 M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
1506815101 R: Lucas Stach <l.stach@pengutronix.de>
@@ -15080,17 +15113,24 @@ S: Maintained · 11 unmodified lines
1508015113 F: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml
1508115114 F: drivers/iio/adc/imx8qxp-adc.c
1508215115
15083−NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER
15084−M: Haibo Chen <haibo.chen@nxp.com>
15085−L: linux-iio@vger.kernel.org
15116+NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER
15117+M: Mirela Rabulea <mirela.rabulea@nxp.com>
15118+R: NXP Linux Team <linux-imx@nxp.com>
15119+L: linux-media@vger.kernel.org
15120+S: Maintained
15121+F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
15122+F: drivers/media/platform/nxp/imx-jpeg
15123+
15124+NXP i.MX CLOCK DRIVERS
15125+M: Abel Vesa <abelvesa@kernel.org>
15126+R: Peng Fan <peng.fan@nxp.com>
15127+L: linux-clk@vger.kernel.org
1508615128 L: linux-imx@nxp.com
1508715129 S: Maintained
15088−F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml
15089−F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
15090−F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
15091−F: drivers/iio/adc/imx7d_adc.c
15092−F: drivers/iio/adc/imx93_adc.c
15093−F: drivers/iio/adc/vf610_adc.c
15130+T: git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx
15131+F: Documentation/devicetree/bindings/clock/imx*
15132+F: drivers/clk/imx/
15133+F: include/dt-bindings/clock/imx*
1509415134
1509515135 NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
1509615136 M: Jagan Teki <jagan@amarulasolutions.com>
@@ -15136,34 +15176,17 @@ S: Maintained · 39 unmodified lines
1513615176 F: Documentation/devicetree/bindings/sound/tfa9879.txt
1513715177 F: sound/soc/codecs/tfa9879*
1513815178
15139−NXP/Goodix TFA989X (TFA1) DRIVER
15140−M: Stephan Gerhold <stephan@gerhold.net>
15141−L: alsa-devel@alsa-project.org (moderated for non-subscribers)
15142−S: Maintained
15143−F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
15144−F: sound/soc/codecs/tfa989x.c
15145−
1514615179 NXP-NCI NFC DRIVER
1514715180 S: Orphan
1514815181 F: Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
1514915182 F: drivers/nfc/nxp-nci
1515015183
15151−NXP i.MX 8MP DW100 V4L2 DRIVER
15152−M: Xavier Roumegue <xavier.roumegue@oss.nxp.com>
15153−L: linux-media@vger.kernel.org
15154−S: Maintained
15155−F: Documentation/devicetree/bindings/media/nxp,dw100.yaml
15156−F: Documentation/userspace-api/media/drivers/dw100.rst
15157−F: drivers/media/platform/nxp/dw100/
15158−F: include/uapi/linux/dw100.h
15159−
15160−NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER
15161−M: Mirela Rabulea <mirela.rabulea@nxp.com>
15162−R: NXP Linux Team <linux-imx@nxp.com>
15163−L: linux-media@vger.kernel.org
15184+NXP/Goodix TFA989X (TFA1) DRIVER
15185+M: Stephan Gerhold <stephan@gerhold.net>
15186+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
1516415187 S: Maintained
15165−F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
15166−F: drivers/media/platform/nxp/imx-jpeg
15188+F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
15189+F: sound/soc/codecs/tfa989x.c
1516715190
1516815191 NZXT-KRAKEN2 HARDWARE MONITORING DRIVER
1516915192 M: Jonas Malaco <jonas@protocubo.io>
@@ -15689,8 +15712,8 @@ M: Rob Herring <robh+dt@kernel.org> · 519 unmodified lines
1568915712 M: Frank Rowand <frowand.list@gmail.com>
1569015713 L: devicetree@vger.kernel.org
1569115714 S: Maintained
15692−C: irc://irc.libera.chat/devicetree
1569315715 W: http://www.devicetree.org/
15716+C: irc://irc.libera.chat/devicetree
1569415717 T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
1569515718 F: Documentation/ABI/testing/sysfs-firmware-ofw
1569615719 F: drivers/of/
@@ -15706,8 +15729,8 @@ M: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> · 9 unmodified lines
1570615729 M: Conor Dooley <conor+dt@kernel.org>
1570715730 L: devicetree@vger.kernel.org
1570815731 S: Maintained
15709−C: irc://irc.libera.chat/devicetree
1571015732 Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/
15733+C: irc://irc.libera.chat/devicetree
1571115734 T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
1571215735 F: Documentation/devicetree/
1571315736 F: arch/*/boot/dts/
@@ -15720,13 +15743,6 @@ L: netdev@vger.kernel.org · 6 unmodified lines
1572015743 S: Maintained
1572115744 F: drivers/ptp/ptp_ocp.c
1572215745
15723−INTEL PTP DFL ToD DRIVER
15724−M: Tianfei Zhang <tianfei.zhang@intel.com>
15725−L: linux-fpga@vger.kernel.org
15726−L: netdev@vger.kernel.org
15727−S: Maintained
15728−F: drivers/ptp/ptp_dfl_tod.c
15729−
1573015746 OPENCORES I2C BUS DRIVER
1573115747 M: Peter Korsgaard <peter@korsgaard.com>
1573215748 M: Andrew Lunn <andrew@lunn.ch>
@@ -15745,8 +15761,8 @@ L: linux-openrisc@vger.kernel.org · 12 unmodified lines
1574515761 S: Maintained
1574615762 W: http://openrisc.io
1574715763 T: git https://github.com/openrisc/linux.git
15748−F: Documentation/devicetree/bindings/openrisc/
1574915764 F: Documentation/arch/openrisc/
15765+F: Documentation/devicetree/bindings/openrisc/
1575015766 F: arch/openrisc/
1575115767 F: drivers/irqchip/irq-ompic.c
1575215768 F: drivers/irqchip/irq-or1k-*
@@ -16062,6 +16078,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 309 unmodified lines
1606216078 S: Maintained
1606316079 F: drivers/pci/controller/dwc/*layerscape*
1606416080
16081+PCI DRIVER FOR FU740
16082+M: Paul Walmsley <paul.walmsley@sifive.com>
16083+M: Greentime Hu <greentime.hu@sifive.com>
16084+L: linux-pci@vger.kernel.org
16085+S: Maintained
16086+F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
16087+F: drivers/pci/controller/dwc/pcie-fu740.c
16088+
1606516089 PCI DRIVER FOR GENERIC OF HOSTS
1606616090 M: Will Deacon <will@kernel.org>
1606716091 L: linux-pci@vger.kernel.org
@@ -16082,14 +16106,6 @@ F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml · 14 unmodified lines
1608216106 F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
1608316107 F: drivers/pci/controller/dwc/*imx6*
1608416108
16085−PCI DRIVER FOR FU740
16086−M: Paul Walmsley <paul.walmsley@sifive.com>
16087−M: Greentime Hu <greentime.hu@sifive.com>
16088−L: linux-pci@vger.kernel.org
16089−S: Maintained
16090−F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
16091−F: drivers/pci/controller/dwc/pcie-fu740.c
16092−
1609316109 PCI DRIVER FOR INTEL IXP4XX
1609416110 M: Linus Walleij <linus.walleij@linaro.org>
1609516111 S: Maintained
@@ -16169,8 +16185,8 @@ M: Jingoo Han <jingoohan1@gmail.com> · 73 unmodified lines
1616916185 M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
1617016186 L: linux-pci@vger.kernel.org
1617116187 S: Maintained
16172−F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
1617316188 F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
16189+F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
1617416190 F: drivers/pci/controller/dwc/*designware*
1617516191
1617616192 PCI DRIVER FOR TI DRA7XX/J721E
@@ -16190,6 +16206,14 @@ S: Maintained · 13 unmodified lines
1619016206 F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
1619116207 F: drivers/pci/controller/pci-v3-semi.c
1619216208
16209+PCI DRIVER FOR XILINX VERSAL CPM
16210+M: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
16211+M: Michal Simek <michal.simek@amd.com>
16212+L: linux-pci@vger.kernel.org
16213+S: Maintained
16214+F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
16215+F: drivers/pci/controller/pcie-xilinx-cpm.c
16216+
1619316217 PCI ENDPOINT SUBSYSTEM
1619416218 M: Lorenzo Pieralisi <lpieralisi@kernel.org>
1619516219 M: Krzysztof Wilczyński <kw@linux.com>
@@ -16227,19 +16251,6 @@ L: linux-pci@vger.kernel.org · 31 unmodified lines
1622716251 S: Supported
1622816252 F: Documentation/PCI/pci-error-recovery.rst
1622916253
16230−PCI PEER-TO-PEER DMA (P2PDMA)
16231−M: Bjorn Helgaas <bhelgaas@google.com>
16232−M: Logan Gunthorpe <logang@deltatee.com>
16233−L: linux-pci@vger.kernel.org
16234−S: Supported
16235−Q: https://patchwork.kernel.org/project/linux-pci/list/
16236−B: https://bugzilla.kernel.org
16237−C: irc://irc.oftc.net/linux-pci
16238−T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16239−F: Documentation/driver-api/pci/p2pdma.rst
16240−F: drivers/pci/p2pdma.c
16241−F: include/linux/pci-p2pdma.h
16242−
1624316254 PCI MSI DRIVER FOR ALTERA MSI IP
1624416255 M: Joyce Ooi <joyce.ooi@intel.com>
1624516256 L: linux-pci@vger.kernel.org
@@ -16270,6 +16281,19 @@ F: drivers/pci/controller/ · 24 unmodified lines
1627016281 F: drivers/pci/pci-bridge-emul.c
1627116282 F: drivers/pci/pci-bridge-emul.h
1627216283
16284+PCI PEER-TO-PEER DMA (P2PDMA)
16285+M: Bjorn Helgaas <bhelgaas@google.com>
16286+M: Logan Gunthorpe <logang@deltatee.com>
16287+L: linux-pci@vger.kernel.org
16288+S: Supported
16289+Q: https://patchwork.kernel.org/project/linux-pci/list/
16290+B: https://bugzilla.kernel.org
16291+C: irc://irc.oftc.net/linux-pci
16292+T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
16293+F: Documentation/driver-api/pci/p2pdma.rst
16294+F: drivers/pci/p2pdma.c
16295+F: include/linux/pci-p2pdma.h
16296+
1627316297 PCI SUBSYSTEM
1627416298 M: Bjorn Helgaas <bhelgaas@google.com>
1627516299 L: linux-pci@vger.kernel.org
@@ -16378,14 +16402,6 @@ L: linux-arm-msm@vger.kernel.org · 102 unmodified lines
1637816402 S: Maintained
1637916403 F: drivers/pci/controller/dwc/pcie-qcom.c
1638016404
16381−PCIE ENDPOINT DRIVER FOR QUALCOMM
16382−M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16383−L: linux-pci@vger.kernel.org
16384−L: linux-arm-msm@vger.kernel.org
16385−S: Maintained
16386−F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
16387−F: drivers/pci/controller/dwc/pcie-qcom-ep.c
16388−
1638916405 PCIE DRIVER FOR ROCKCHIP
1639016406 M: Shawn Lin <shawn.lin@rock-chips.com>
1639116407 L: linux-pci@vger.kernel.org
@@ -16407,13 +16423,13 @@ L: linux-pci@vger.kernel.org · 15 unmodified lines
1640716423 S: Maintained
1640816424 F: drivers/pci/controller/dwc/*spear*
1640916425
16410−PCI DRIVER FOR XILINX VERSAL CPM
16411−M: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
16412−M: Michal Simek <michal.simek@amd.com>
16426+PCIE ENDPOINT DRIVER FOR QUALCOMM
16427+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1641316428 L: linux-pci@vger.kernel.org
16429+L: linux-arm-msm@vger.kernel.org
1641416430 S: Maintained
16415−F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
16416−F: drivers/pci/controller/pcie-xilinx-cpm.c
16431+F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
16432+F: drivers/pci/controller/dwc/pcie-qcom-ep.c
1641716433
1641816434 PCMCIA SUBSYSTEM
1641916435 M: Dominik Brodowski <linux@dominikbrodowski.net>
@@ -16683,9 +16699,9 @@ R: Alim Akhtar <alim.akhtar@samsung.com> · 263 unmodified lines
1668316699 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1668416700 L: linux-samsung-soc@vger.kernel.org
1668516701 S: Maintained
16686−C: irc://irc.libera.chat/linux-exynos
1668716702 Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
1668816703 B: mailto:linux-samsung-soc@vger.kernel.org
16704+C: irc://irc.libera.chat/linux-exynos
1668916705 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
1669016706 F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml
1669116707 F: drivers/pinctrl/samsung/
@@ -16747,13 +16763,6 @@ M: Logan Gunthorpe <logang@deltatee.com> · 55 unmodified lines
1674716763 S: Maintained
1674816764 F: drivers/dma/plx_dma.c
1674916765
16750−PM6764TR DRIVER
16751−M: Charles Hsu <hsu.yungteng@gmail.com>
16752−L: linux-hwmon@vger.kernel.org
16753−S: Maintained
16754−F: Documentation/hwmon/pm6764tr.rst
16755−F: drivers/hwmon/pmbus/pm6764tr.c
16756−
1675716766 PM-GRAPH UTILITY
1675816767 M: "Todd E Brandt" <todd.e.brandt@linux.intel.com>
1675916768 L: linux-pm@vger.kernel.org
@@ -16763,6 +16772,13 @@ B: https://bugzilla.kernel.org/buglist.cgi?component=pm-graph&product=Tools · 3 unmodified lines
1676316772 T: git git://github.com/intel/pm-graph
1676416773 F: tools/power/pm-graph
1676516774
16775+PM6764TR DRIVER
16776+M: Charles Hsu <hsu.yungteng@gmail.com>
16777+L: linux-hwmon@vger.kernel.org
16778+S: Maintained
16779+F: Documentation/hwmon/pm6764tr.rst
16780+F: drivers/hwmon/pmbus/pm6764tr.c
16781+
1676616782 PMBUS HARDWARE MONITORING DRIVERS
1676716783 M: Guenter Roeck <linux@roeck-us.net>
1676816784 L: linux-hwmon@vger.kernel.org
@@ -16843,15 +16859,6 @@ F: include/linux/pm_* · 74 unmodified lines
1684316859 F: include/linux/powercap.h
1684416860 F: kernel/configs/nopm.config
1684516861
16846−DYNAMIC THERMAL POWER MANAGEMENT (DTPM)
16847−M: Daniel Lezcano <daniel.lezcano@kernel.org>
16848−L: linux-pm@vger.kernel.org
16849−S: Supported
16850−B: https://bugzilla.kernel.org
16851−T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
16852−F: drivers/powercap/dtpm*
16853−F: include/linux/dtpm.h
16854−
1685516862 POWER STATE COORDINATION INTERFACE (PSCI)
1685616863 M: Mark Rutland <mark.rutland@arm.com>
1685716864 M: Lorenzo Pieralisi <lpieralisi@kernel.org>
@@ -17010,8 +17017,8 @@ R: Guilherme G. Piccoli <gpiccoli@igalia.com> · 152 unmodified lines
1701017017 L: linux-hardening@vger.kernel.org
1701117018 S: Supported
1701217019 T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/pstore
17013−F: Documentation/admin-guide/ramoops.rst
1701417020 F: Documentation/admin-guide/pstore-blk.rst
17021+F: Documentation/admin-guide/ramoops.rst
1701517022 F: Documentation/devicetree/bindings/reserved-memory/ramoops.yaml
1701617023 F: drivers/acpi/apei/erst.c
1701717024 F: drivers/firmware/efi/efi-pstore.c
@@ -17160,10 +17167,10 @@ F: sound/soc/codecs/lpass-va-macro.c · 142 unmodified lines
1716017167 F: sound/soc/codecs/lpass-wsa-macro.*
1716117168 F: sound/soc/codecs/msm8916-wcd-analog.c
1716217169 F: sound/soc/codecs/msm8916-wcd-digital.c
17163−F: sound/soc/codecs/wcd9335.*
17164−F: sound/soc/codecs/wcd934x.c
1716517170 F: sound/soc/codecs/wcd-clsh-v2.*
1716617171 F: sound/soc/codecs/wcd-mbhc-v2.*
17172+F: sound/soc/codecs/wcd9335.*
17173+F: sound/soc/codecs/wcd934x.c
1716717174 F: sound/soc/codecs/wsa881x.c
1716817175 F: sound/soc/codecs/wsa883x.c
1716917176 F: sound/soc/qcom/
@@ -17320,14 +17327,21 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ · 150 unmodified lines
1732017327 T: git git://linuxtv.org/anttip/media_tree.git
1732117328 F: drivers/media/tuners/qt1010*
1732217329
17330+QUALCOMM ATH12K WIRELESS DRIVER
17331+M: Kalle Valo <kvalo@kernel.org>
17332+L: ath12k@lists.infradead.org
17333+S: Supported
17334+T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
17335+F: drivers/net/wireless/ath/ath12k/
17336+
1732317337 QUALCOMM ATHEROS ATH10K WIRELESS DRIVER
1732417338 M: Kalle Valo <kvalo@kernel.org>
1732517339 L: ath10k@lists.infradead.org
1732617340 S: Supported
1732717341 W: https://wireless.wiki.kernel.org/en/users/Drivers/ath10k
1732817342 T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
17329−F: drivers/net/wireless/ath/ath10k/
1733017343 F: Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml
17344+F: drivers/net/wireless/ath/ath10k/
1733117345
1733217346 QUALCOMM ATHEROS ATH11K WIRELESS DRIVER
1733317347 M: Kalle Valo <kvalo@kernel.org>
@@ -17337,13 +17351,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git · 3 unmodified lines
1733717351 F: Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
1733817352 F: drivers/net/wireless/ath/ath11k/
1733917353
17340−QUALCOMM ATH12K WIRELESS DRIVER
17341−M: Kalle Valo <kvalo@kernel.org>
17342−L: ath12k@lists.infradead.org
17343−S: Supported
17344−T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
17345−F: drivers/net/wireless/ath/ath12k/
17346−
1734717354 QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
1734817355 M: Toke Høiland-Jørgensen <toke@toke.dk>
1734917356 L: linux-wireless@vger.kernel.org
@@ -17440,8 +17447,8 @@ F: include/uapi/misc/fastrpc.h · 90 unmodified lines
1744017447 QUALCOMM HEXAGON ARCHITECTURE
1744117448 M: Brian Cain <bcain@quicinc.com>
1744217449 L: linux-hexagon@vger.kernel.org
17443−T: git git://git.kernel.org/pub/scm/linux/kernel/git/bcain/linux.git
1744417450 S: Supported
17451+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bcain/linux.git
1744517452 F: arch/hexagon/
1744617453
1744717454 QUALCOMM HIDMA DRIVER
@@ -17563,9 +17570,9 @@ M: Christian König <christian.koenig@amd.com> · 115 unmodified lines
1756317570 M: Pan, Xinhui <Xinhui.Pan@amd.com>
1756417571 L: amd-gfx@lists.freedesktop.org
1756517572 S: Supported
17566−T: git https://gitlab.freedesktop.org/agd5f/linux.git
1756717573 B: https://gitlab.freedesktop.org/drm/amd/-/issues
1756817574 C: irc://irc.oftc.net/radeon
17575+T: git https://gitlab.freedesktop.org/agd5f/linux.git
1756917576 F: Documentation/gpu/amdgpu/
1757017577 F: drivers/gpu/drm/amd/
1757117578 F: drivers/gpu/drm/radeon/
@@ -17653,8 +17660,8 @@ F: arch/mips/generic/board-ranchu.c · 81 unmodified lines
1765317660 RANDOM NUMBER DRIVER
1765417661 M: "Theodore Ts'o" <tytso@mit.edu>
1765517662 M: Jason A. Donenfeld <Jason@zx2c4.com>
17656−T: git https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git
1765717663 S: Maintained
17664+T: git https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git
1765817665 F: drivers/char/random.c
1765917666 F: drivers/virt/vmgenid.c
1766017667
@@ -17688,8 +17695,8 @@ T: git git://linuxtv.org/media_tree.git · 27 unmodified lines
1768817695 F: Documentation/driver-api/media/rc-core.rst
1768917696 F: Documentation/userspace-api/media/rc/
1769017697 F: drivers/media/rc/
17691−F: include/media/rc-map.h
1769217698 F: include/media/rc-core.h
17699+F: include/media/rc-map.h
1769317700 F: include/uapi/linux/lirc.h
1769417701
1769517702 RCMM REMOTE CONTROLS DECODER
@@ -17806,6 +17813,14 @@ F: include/linux/rtc/ · 110 unmodified lines
1780617813 F: include/uapi/linux/rtc.h
1780717814 F: tools/testing/selftests/rtc/
1780817815
17816+Real-time Linux Analysis (RTLA) tools
17817+M: Daniel Bristot de Oliveira <bristot@kernel.org>
17818+M: Steven Rostedt <rostedt@goodmis.org>
17819+L: linux-trace-devel@vger.kernel.org
17820+S: Maintained
17821+F: Documentation/tools/rtla/
17822+F: tools/tracing/rtla/
17823+
1780917824 REALTEK AUDIO CODECS
1781017825 M: Oder Chiou <oder_chiou@realtek.com>
1781117826 S: Maintained
@@ -17929,6 +17944,14 @@ S: Maintained · 117 unmodified lines
1792917944 F: Documentation/devicetree/bindings/sound/renesas,idt821034.yaml
1793017945 F: sound/soc/codecs/idt821034.c
1793117946
17947+RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER
17948+M: Miquel Raynal <miquel.raynal@bootlin.com>
17949+L: linux-mtd@lists.infradead.org
17950+L: linux-renesas-soc@vger.kernel.org
17951+S: Maintained
17952+F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
17953+F: drivers/mtd/nand/raw/renesas-nand-controller.c
17954+
1793217955 RENESAS R-CAR GYROADC DRIVER
1793317956 M: Marek Vasut <marek.vasut@gmail.com>
1793417957 L: linux-iio@vger.kernel.org
@@ -17947,9 +17970,9 @@ F: drivers/i2c/busses/i2c-sh_mobile.c · 12 unmodified lines
1794717970
1794817971 RENESAS R-CAR SATA DRIVER
1794917972 R: Sergey Shtylyov <s.shtylyov@omp.ru>
17950−S: Supported
1795117973 L: linux-ide@vger.kernel.org
1795217974 L: linux-renesas-soc@vger.kernel.org
17975+S: Supported
1795317976 F: Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
1795417977 F: drivers/ata/sata_rcar.c
1795517978
@@ -17969,12 +17992,6 @@ S: Supported · 13 unmodified lines
1796917992 F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml
1797017993 F: drivers/i2c/busses/i2c-riic.c
1797117994
17972−RENESAS USB PHY DRIVER
17973−M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17974−L: linux-renesas-soc@vger.kernel.org
17975−S: Maintained
17976−F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
17977−
1797817995 RENESAS RZ/G2L A/D DRIVER
1797917996 M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
1798017997 L: linux-iio@vger.kernel.org
@@ -18020,13 +18037,11 @@ S: Maintained · 39 unmodified lines
1802018037 F: Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml
1802118038 F: drivers/usb/gadget/udc/renesas_usbf.c
1802218039
18023−RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER
18024−M: Miquel Raynal <miquel.raynal@bootlin.com>
18025−L: linux-mtd@lists.infradead.org
18040+RENESAS USB PHY DRIVER
18041+M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
1802618042 L: linux-renesas-soc@vger.kernel.org
1802718043 S: Maintained
18028−F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
18029−F: drivers/mtd/nand/raw/renesas-nand-controller.c
18044+F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
1803018045
1803118046 RENESAS VERSACLOCK 7 CLOCK DRIVER
1803218047 M: Alex Helms <alexander.helms.jy@renesas.com>
@@ -18094,15 +18109,6 @@ S: Maintained · 61 unmodified lines
1809418109 F: drivers/mtd/nand/raw/r852.c
1809518110 F: drivers/mtd/nand/raw/r852.h
1809618111
18097−RISC-V PMU DRIVERS
18098−M: Atish Patra <atishp@atishpatra.org>
18099−R: Anup Patel <anup@brainfault.org>
18100−L: linux-riscv@lists.infradead.org
18101−S: Supported
18102−F: drivers/perf/riscv_pmu.c
18103−F: drivers/perf/riscv_pmu_legacy.c
18104−F: drivers/perf/riscv_pmu_sbi.c
18105−
1810618112 RISC-V ARCHITECTURE
1810718113 M: Paul Walmsley <paul.walmsley@sifive.com>
1810818114 M: Palmer Dabbelt <palmer@dabbelt.com>
@@ -18155,6 +18161,15 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ · 46 unmodified lines
1815518161 F: Documentation/devicetree/bindings/riscv/
1815618162 F: arch/riscv/boot/dts/
1815718163
18164+RISC-V PMU DRIVERS
18165+M: Atish Patra <atishp@atishpatra.org>
18166+R: Anup Patel <anup@brainfault.org>
18167+L: linux-riscv@lists.infradead.org
18168+S: Supported
18169+F: drivers/perf/riscv_pmu.c
18170+F: drivers/perf/riscv_pmu_legacy.c
18171+F: drivers/perf/riscv_pmu_sbi.c
18172+
1815818173 RNBD BLOCK DRIVERS
1815918174 M: Md. Haris Iqbal <haris.iqbal@ionos.com>
1816018175 M: Jack Wang <jinpu.wang@ionos.com>
@@ -18459,14 +18474,6 @@ F: drivers/s390/net/*iucv* · 298 unmodified lines
1845918474 F: include/net/iucv/
1846018475 F: net/iucv/
1846118476
18462−S390 NETWORK DRIVERS
18463−M: Alexandra Winter <wintera@linux.ibm.com>
18464−M: Wenjia Zhang <wenjia@linux.ibm.com>
18465−L: linux-s390@vger.kernel.org
18466−L: netdev@vger.kernel.org
18467−S: Supported
18468−F: drivers/s390/net/
18469−
1847018477 S390 MM
1847118478 M: Alexander Gordeev <agordeev@linux.ibm.com>
1847218479 M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
@@ -18476,14 +18483,22 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git · 3 unmodified lines
1847618483 F: arch/s390/include/asm/pgtable.h
1847718484 F: arch/s390/mm
1847818485
18486+S390 NETWORK DRIVERS
18487+M: Alexandra Winter <wintera@linux.ibm.com>
18488+M: Wenjia Zhang <wenjia@linux.ibm.com>
18489+L: linux-s390@vger.kernel.org
18490+L: netdev@vger.kernel.org
18491+S: Supported
18492+F: drivers/s390/net/
18493+
1847918494 S390 PCI SUBSYSTEM
1848018495 M: Niklas Schnelle <schnelle@linux.ibm.com>
1848118496 M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
1848218497 L: linux-s390@vger.kernel.org
1848318498 S: Supported
18499+F: Documentation/s390/pci.rst
1848418500 F: arch/s390/pci/
1848518501 F: drivers/pci/hotplug/s390_pci_hpc.c
18486−F: Documentation/s390/pci.rst
1848718502
1848818503 S390 SCM DRIVER
1848918504 M: Vineeth Vijayan <vneethv@linux.ibm.com>
@@ -18916,6 +18931,13 @@ L: linux-mmc@vger.kernel.org · 426 unmodified lines
1891618931 S: Supported
1891718932 F: drivers/mmc/host/sdhci-of-at91.c
1891818933
18934+SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) NXP i.MX DRIVER
18935+M: Haibo Chen <haibo.chen@nxp.com>
18936+L: linux-imx@nxp.com
18937+L: linux-mmc@vger.kernel.org
18938+S: Maintained
18939+F: drivers/mmc/host/sdhci-esdhc-imx.c
18940+
1891918941 SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER
1892018942 M: Ben Dooks <ben-linux@fluff.org>
1892118943 M: Jaehoon Chung <jh80.chung@samsung.com>
@@ -18935,13 +18957,6 @@ L: linux-mmc@vger.kernel.org · 13 unmodified lines
1893518957 S: Maintained
1893618958 F: drivers/mmc/host/sdhci-omap.c
1893718959
18938−SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) NXP i.MX DRIVER
18939−M: Haibo Chen <haibo.chen@nxp.com>
18940−L: linux-imx@nxp.com
18941−L: linux-mmc@vger.kernel.org
18942−S: Maintained
18943−F: drivers/mmc/host/sdhci-esdhc-imx.c
18944−
1894518960 SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER
1894618961 M: Jonathan Derrick <jonathan.derrick@linux.dev>
1894718962 L: linux-block@vger.kernel.org
@@ -18951,6 +18966,15 @@ F: block/sed* · 3 unmodified lines
1895118966 F: include/linux/sed*
1895218967 F: include/uapi/linux/sed*
1895318968
18969+SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)
18970+M: Mark Rutland <mark.rutland@arm.com>
18971+M: Lorenzo Pieralisi <lpieralisi@kernel.org>
18972+M: Sudeep Holla <sudeep.holla@arm.com>
18973+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
18974+S: Maintained
18975+F: drivers/firmware/smccc/
18976+F: include/linux/arm-smccc.h
18977+
1895418978 SECURITY CONTACT
1895518979 M: Security Officers <security@kernel.org>
1895618980 S: Supported
@@ -19400,15 +19424,6 @@ M: Nicolas Pitre <nico@fluxnic.net> · 443 unmodified lines
1940019424 S: Odd Fixes
1940119425 F: drivers/net/ethernet/smsc/smc91x.*
1940219426
19403−SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)
19404−M: Mark Rutland <mark.rutland@arm.com>
19405−M: Lorenzo Pieralisi <lpieralisi@kernel.org>
19406−M: Sudeep Holla <sudeep.holla@arm.com>
19407−L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
19408−S: Maintained
19409−F: drivers/firmware/smccc/
19410−F: include/linux/arm-smccc.h
19411−
1941219427 SMM665 HARDWARE MONITOR DRIVER
1941319428 M: Guenter Roeck <linux@roeck-us.net>
1941419429 L: linux-hwmon@vger.kernel.org
@@ -19456,6 +19471,10 @@ L: netdev@vger.kernel.org · 41 unmodified lines
1945619471 S: Maintained
1945719472 F: drivers/net/ethernet/smsc/smsc9420.*
1945819473
19474+SNET DPU VIRTIO DATA PATH ACCELERATOR
19475+R: Alvaro Karsz <alvaro.karsz@solid-run.com>
19476+F: drivers/vdpa/solidrun/
19477+
1945919478 SOCIONEXT (SNI) AVE NETWORK DRIVER
1946019479 M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
1946119480 L: netdev@vger.kernel.org
@@ -19725,6 +19744,13 @@ F: include/uapi/sound/ · 263 unmodified lines
1972519744 F: sound/
1972619745 F: tools/testing/selftests/alsa
1972719746
19747+SOUND - ALSA SELFTESTS
19748+M: Mark Brown <broonie@kernel.org>
19749+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
19750+L: linux-kselftest@vger.kernel.org
19751+S: Supported
19752+F: tools/testing/selftests/alsa
19753+
1972819754 SOUND - COMPRESSED AUDIO
1972919755 M: Vinod Koul <vkoul@kernel.org>
1973019756 L: alsa-devel@alsa-project.org (moderated for non-subscribers)
@@ -19743,13 +19769,6 @@ F: include/sound/dmaengine_pcm.h · 12 unmodified lines
1974319769 F: sound/core/pcm_dmaengine.c
1974419770 F: sound/soc/soc-generic-dmaengine-pcm.c
1974519771
19746−SOUND - ALSA SELFTESTS
19747−M: Mark Brown <broonie@kernel.org>
19748−L: alsa-devel@alsa-project.org (moderated for non-subscribers)
19749−L: linux-kselftest@vger.kernel.org
19750−S: Supported
19751−F: tools/testing/selftests/alsa
19752−
1975319772 SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
1975419773 M: Liam Girdwood <lgirdwood@gmail.com>
1975519774 M: Mark Brown <broonie@kernel.org>
@@ -19769,8 +19788,8 @@ M: Liam Girdwood <lgirdwood@gmail.com> · 13 unmodified lines
1976919788 M: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
1977019789 M: Bard Liao <yung-chuan.liao@linux.intel.com>
1977119790 M: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
19772−R: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1977319791 M: Daniel Baluta <daniel.baluta@nxp.com>
19792+R: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1977419793 L: sound-open-firmware@alsa-project.org (moderated for non-subscribers)
1977519794 S: Supported
1977619795 W: https://github.com/thesofproject/linux/
@@ -19832,9 +19851,9 @@ M: "Luc Van Oostenryck" <luc.vanoostenryck@gmail.com> · 55 unmodified lines
1983219851 L: linux-sparse@vger.kernel.org
1983319852 S: Maintained
1983419853 W: https://sparse.docs.kernel.org/
19835−T: git git://git.kernel.org/pub/scm/devel/sparse/sparse.git
1983619854 Q: https://patchwork.kernel.org/project/linux-sparse/list/
1983719855 B: https://bugzilla.kernel.org/enter_bug.cgi?component=Sparse&product=Tools
19856+T: git git://git.kernel.org/pub/scm/devel/sparse/sparse.git
1983819857 F: include/linux/compiler.h
1983919858
1984019859 SPEAKUP CONSOLE SPEECH DRIVER
@@ -20203,6 +20222,11 @@ W: http://www.stlinux.com · 362 unmodified lines
2020320222 F: Documentation/networking/device_drivers/ethernet/stmicro/
2020420223 F: drivers/net/ethernet/stmicro/stmmac/
2020520224
20225+SUN HAPPY MEAL ETHERNET DRIVER
20226+M: Sean Anderson <seanga2@gmail.com>
20227+S: Maintained
20228+F: drivers/net/ethernet/sun/sunhme.*
20229+
2020620230 SUN3/3X
2020720231 M: Sam Creasey <sammy@sammy.net>
2020820232 S: Maintained
@@ -20225,11 +20249,6 @@ L: netdev@vger.kernel.org · 16 unmodified lines
2022520249 S: Maintained
2022620250 F: drivers/net/ethernet/dlink/sundance.c
2022720251
20228−SUN HAPPY MEAL ETHERNET DRIVER
20229−M: Sean Anderson <seanga2@gmail.com>
20230−S: Maintained
20231−F: drivers/net/ethernet/sun/sunhme.*
20232−
2023320252 SUNPLUS ETHERNET DRIVER
2023420253 M: Wells Lu <wellslutw@gmail.com>
2023520254 L: netdev@vger.kernel.org
@@ -20251,15 +20270,6 @@ S: Maintained · 15 unmodified lines
2025120270 F: Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
2025220271 F: drivers/nvmem/sunplus-ocotp.c
2025320272
20254−SUNPLUS USB2 PHY DRIVER
20255−M: Vincent Shih <vincent.sunplus@gmail.com>
20256−L: linux-usb@vger.kernel.org
20257−S: Maintained
20258−F: Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
20259−F: drivers/phy/sunplus/Kconfig
20260−F: drivers/phy/sunplus/Makefile
20261−F: drivers/phy/sunplus/phy-sunplus-usb2.c
20262−
2026320273 SUNPLUS PWM DRIVER
2026420274 M: Hammer Hsieh <hammerh0314@gmail.com>
2026520275 S: Maintained
@@ -20286,6 +20296,15 @@ S: Maintained · 20 unmodified lines
2028620296 F: Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
2028720297 F: drivers/tty/serial/sunplus-uart.c
2028820298
20299+SUNPLUS USB2 PHY DRIVER
20300+M: Vincent Shih <vincent.sunplus@gmail.com>
20301+L: linux-usb@vger.kernel.org
20302+S: Maintained
20303+F: Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
20304+F: drivers/phy/sunplus/Kconfig
20305+F: drivers/phy/sunplus/Makefile
20306+F: drivers/phy/sunplus/phy-sunplus-usb2.c
20307+
2028920308 SUNPLUS WATCHDOG DRIVER
2029020309 M: Xiantao Hu <xt.hu@cqplus1.com>
2029120310 L: linux-watchdog@vger.kernel.org
@@ -20697,6 +20716,14 @@ F: include/linux/if_team.h · 405 unmodified lines
2069720716 F: include/uapi/linux/if_team.h
2069820717 F: tools/testing/selftests/drivers/net/team/
2069920718
20719+TECHNICAL ADVISORY BOARD PROCESS DOCS
20720+M: "Theodore Ts'o" <tytso@mit.edu>
20721+M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
20722+L: tech-board-discuss@lists.linux-foundation.org
20723+S: Maintained
20724+F: Documentation/process/contribution-maturity-model.rst
20725+F: Documentation/process/researcher-guidelines.rst
20726+
2070020727 TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT
2070120728 M: "Savoir-faire Linux Inc." <kernel@savoirfairelinux.com>
2070220729 S: Maintained
@@ -20776,6 +20803,14 @@ M: Thierry Reding <thierry.reding@gmail.com> · 73 unmodified lines
2077620803 S: Supported
2077720804 F: drivers/pwm/pwm-tegra.c
2077820805
20806+TEGRA QUAD SPI DRIVER
20807+M: Thierry Reding <thierry.reding@gmail.com>
20808+M: Jonathan Hunter <jonathanh@nvidia.com>
20809+M: Sowjanya Komatineni <skomatineni@nvidia.com>
20810+L: linux-tegra@vger.kernel.org
20811+S: Maintained
20812+F: drivers/spi/spi-tegra210-quad.c
20813+
2077920814 TEGRA SERIAL DRIVER
2078020815 M: Laxman Dewangan <ldewangan@nvidia.com>
2078120816 S: Supported
@@ -20786,14 +20821,6 @@ M: Laxman Dewangan <ldewangan@nvidia.com> · 4 unmodified lines
2078620821 S: Supported
2078720822 F: drivers/spi/spi-tegra*
2078820823
20789−TEGRA QUAD SPI DRIVER
20790−M: Thierry Reding <thierry.reding@gmail.com>
20791−M: Jonathan Hunter <jonathanh@nvidia.com>
20792−M: Sowjanya Komatineni <skomatineni@nvidia.com>
20793−L: linux-tegra@vger.kernel.org
20794−S: Maintained
20795−F: drivers/spi/spi-tegra210-quad.c
20796−
2079720824 TEGRA VIDEO DRIVER
2079820825 M: Thierry Reding <thierry.reding@gmail.com>
2079920826 M: Jonathan Hunter <jonathanh@nvidia.com>
@@ -20842,13 +20869,6 @@ S: Maintained · 42 unmodified lines
2084220869 F: Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
2084320870 F: sound/soc/ti/
2084420871
20845−TEXAS INSTRUMENTS' DAC7612 DAC DRIVER
20846−M: Ricardo Ribalda <ribalda@kernel.org>
20847−L: linux-iio@vger.kernel.org
20848−S: Supported
20849−F: Documentation/devicetree/bindings/iio/dac/ti,dac7612.yaml
20850−F: drivers/iio/dac/ti-dac7612.c
20851−
2085220872 TEXAS INSTRUMENTS DMA DRIVERS
2085320873 M: Peter Ujfalusi <peter.ujfalusi@gmail.com>
2085420874 L: dmaengine@vger.kernel.org
@@ -20857,10 +20877,26 @@ F: Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt · 2 unmodified lines
2085720877 F: Documentation/devicetree/bindings/dma/ti-edma.txt
2085820878 F: Documentation/devicetree/bindings/dma/ti/
2085920879 F: drivers/dma/ti/
20860−X: drivers/dma/ti/cppi41.c
20880+F: include/linux/dma/k3-psil.h
2086120881 F: include/linux/dma/k3-udma-glue.h
2086220882 F: include/linux/dma/ti-cppi5.h
20863−F: include/linux/dma/k3-psil.h
20883+X: drivers/dma/ti/cppi41.c
20884+
20885+TEXAS INSTRUMENTS TPS23861 PoE PSE DRIVER
20886+M: Robert Marko <robert.marko@sartura.hr>
20887+M: Luka Perkov <luka.perkov@sartura.hr>
20888+L: linux-hwmon@vger.kernel.org
20889+S: Maintained
20890+F: Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml
20891+F: Documentation/hwmon/tps23861.rst
20892+F: drivers/hwmon/tps23861.c
20893+
20894+TEXAS INSTRUMENTS' DAC7612 DAC DRIVER
20895+M: Ricardo Ribalda <ribalda@kernel.org>
20896+L: linux-iio@vger.kernel.org
20897+S: Supported
20898+F: Documentation/devicetree/bindings/iio/dac/ti,dac7612.yaml
20899+F: drivers/iio/dac/ti-dac7612.c
2086420900
2086520901 TEXAS INSTRUMENTS' SYSTEM CONTROL INTERFACE (TISCI) PROTOCOL DRIVER
2086620902 M: Nishanth Menon <nm@ti.com>
@@ -20886,15 +20922,6 @@ F: include/dt-bindings/soc/ti,sci_pm_domain.h · 19 unmodified lines
2088620922 F: include/linux/soc/ti/ti_sci_inta_msi.h
2088720923 F: include/linux/soc/ti/ti_sci_protocol.h
2088820924
20889−TEXAS INSTRUMENTS TPS23861 PoE PSE DRIVER
20890−M: Robert Marko <robert.marko@sartura.hr>
20891−M: Luka Perkov <luka.perkov@sartura.hr>
20892−L: linux-hwmon@vger.kernel.org
20893−S: Maintained
20894−F: Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml
20895−F: Documentation/hwmon/tps23861.rst
20896−F: drivers/hwmon/tps23861.c
20897−
2089820925 TEXAS INSTRUMENTS' TMP117 TEMPERATURE SENSOR DRIVER
2089920926 M: Puranjay Mohan <puranjay12@gmail.com>
2090020927 L: linux-iio@vger.kernel.org
@@ -21371,8 +21398,8 @@ M: Steven Rostedt <rostedt@goodmis.org> · 470 unmodified lines
2137121398 M: Masami Hiramatsu <mhiramat@kernel.org>
2137221399 L: linux-kernel@vger.kernel.org
2137321400 L: linux-trace-kernel@vger.kernel.org
21374−Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
2137521401 S: Maintained
21402+Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/
2137621403 T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git
2137721404 F: Documentation/trace/*
2137821405 F: fs/tracefs/
@@ -21400,31 +21427,15 @@ TRACING OS NOISE / LATENCY TRACERS · 21 unmodified lines
2140021427 M: Steven Rostedt <rostedt@goodmis.org>
2140121428 M: Daniel Bristot de Oliveira <bristot@kernel.org>
2140221429 S: Maintained
21403−F: kernel/trace/trace_osnoise.c
21430+F: Documentation/trace/hwlat_detector.rst
21431+F: Documentation/trace/osnoise-tracer.rst
21432+F: Documentation/trace/timerlat-tracer.rst
21433+F: arch/*/kernel/trace.c
2140421434 F: include/trace/events/osnoise.h
2140521435 F: kernel/trace/trace_hwlat.c
2140621436 F: kernel/trace/trace_irqsoff.c
21437+F: kernel/trace/trace_osnoise.c
2140721438 F: kernel/trace/trace_sched_wakeup.c
21408−F: Documentation/trace/osnoise-tracer.rst
21409−F: Documentation/trace/timerlat-tracer.rst
21410−F: Documentation/trace/hwlat_detector.rst
21411−F: arch/*/kernel/trace.c
21412−
21413−Real-time Linux Analysis (RTLA) tools
21414−M: Daniel Bristot de Oliveira <bristot@kernel.org>
21415−M: Steven Rostedt <rostedt@goodmis.org>
21416−L: linux-trace-devel@vger.kernel.org
21417−S: Maintained
21418−F: Documentation/tools/rtla/
21419−F: tools/tracing/rtla/
21420−
21421−TECHNICAL ADVISORY BOARD PROCESS DOCS
21422−M: "Theodore Ts'o" <tytso@mit.edu>
21423−M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21424−L: tech-board-discuss@lists.linux-foundation.org
21425−S: Maintained
21426−F: Documentation/process/researcher-guidelines.rst
21427−F: Documentation/process/contribution-maturity-model.rst
2142821439
2142921440 TRADITIONAL CHINESE DOCUMENTATION
2143021441 M: Hu Haowen <src.res@email.cn>
@@ -21782,8 +21793,8 @@ USB ISP1760 DRIVER · 351 unmodified lines
2178221793 M: Rui Miguel Silva <rui.silva@linaro.org>
2178321794 L: linux-usb@vger.kernel.org
2178421795 S: Maintained
21785−F: drivers/usb/isp1760/*
2178621796 F: Documentation/devicetree/bindings/usb/nxp,isp1760.yaml
21797+F: drivers/usb/isp1760/*
2178721798
2178821799 USB LAN78XX ETHERNET DRIVER
2178921800 M: Woojung Huh <woojung.huh@microchip.com>
@@ -21854,6 +21865,13 @@ L: linux-usb@vger.kernel.org · 64 unmodified lines
2185421865 S: Supported
2185521866 F: drivers/usb/class/usblp.c
2185621867
21868+USB QMI WWAN NETWORK DRIVER
21869+M: Bjørn Mork <bjorn@mork.no>
21870+L: netdev@vger.kernel.org
21871+S: Maintained
21872+F: Documentation/ABI/testing/sysfs-class-net-qmi
21873+F: drivers/net/usb/qmi_wwan.c
21874+
2185721875 USB RAW GADGET DRIVER
2185821876 R: Andrey Konovalov <andreyknvl@gmail.com>
2185921877 L: linux-usb@vger.kernel.org
@@ -21862,13 +21880,6 @@ F: Documentation/usb/raw-gadget.rst · 2 unmodified lines
2186221880 F: drivers/usb/gadget/legacy/raw_gadget.c
2186321881 F: include/uapi/linux/usb/raw_gadget.h
2186421882
21865−USB QMI WWAN NETWORK DRIVER
21866−M: Bjørn Mork <bjorn@mork.no>
21867−L: netdev@vger.kernel.org
21868−S: Maintained
21869−F: Documentation/ABI/testing/sysfs-class-net-qmi
21870−F: drivers/net/usb/qmi_wwan.c
21871−
2187221883 USB RTL8150 DRIVER
2187321884 M: Petko Manolov <petkan@nucleusys.com>
2187421885 L: linux-usb@vger.kernel.org
@@ -22120,6 +22131,12 @@ F: drivers/vfio/mdev/ · 245 unmodified lines
2212022131 F: include/linux/mdev.h
2212122132 F: samples/vfio-mdev/
2212222133
22134+VFIO MLX5 PCI DRIVER
22135+M: Yishai Hadas <yishaih@nvidia.com>
22136+L: kvm@vger.kernel.org
22137+S: Maintained
22138+F: drivers/vfio/pci/mlx5/
22139+
2212322140 VFIO PCI DEVICE SPECIFIC DRIVERS
2212422141 R: Jason Gunthorpe <jgg@nvidia.com>
2212522142 R: Yishai Hadas <yishaih@nvidia.com>
@@ -22136,12 +22153,6 @@ L: kvm@vger.kernel.org · 10 unmodified lines
2213622153 S: Maintained
2213722154 F: drivers/vfio/platform/
2213822155
22139−VFIO MLX5 PCI DRIVER
22140−M: Yishai Hadas <yishaih@nvidia.com>
22141−L: kvm@vger.kernel.org
22142−S: Maintained
22143−F: drivers/vfio/pci/mlx5/
22144−
2214522156 VGA_SWITCHEROO
2214622157 R: Lukas Wunner <lukas@wunner.de>
2214722158 S: Maintained
@@ -22151,8 +22162,8 @@ F: drivers/gpu/vga/vga_switcheroo.c · 3 unmodified lines
2215122162 F: include/linux/vga_switcheroo.h
2215222163
2215322164 VIA RHINE NETWORK DRIVER
22154−S: Maintained
2215522165 M: Kevin Brace <kevinbrace@bracecomputerlab.com>
22166+S: Maintained
2215622167 F: drivers/net/ethernet/via/via-rhine.c
2215722168
2215822169 VIA SD/MMC CARD CONTROLLER DRIVER
@@ -22204,6 +22215,14 @@ S: Maintained · 45 unmodified lines
2220422215 F: drivers/media/common/videobuf2/*
2220522216 F: include/media/videobuf2-*
2220622217
22218+VIDTV VIRTUAL DIGITAL TV DRIVER
22219+M: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
22220+L: linux-media@vger.kernel.org
22221+S: Maintained
22222+W: https://linuxtv.org
22223+T: git git://linuxtv.org/media_tree.git
22224+F: drivers/media/test-drivers/vidtv/*
22225+
2220722226 VIMC VIRTUAL MEDIA CONTROLLER DRIVER
2220822227 M: Shuah Khan <skhan@linuxfoundation.org>
2220922228 R: Kieran Bingham <kieran.bingham@ideasonboard.com>
@@ -22233,6 +22252,16 @@ F: include/uapi/linux/virtio_vsock.h · 23 unmodified lines
2223322252 F: net/vmw_vsock/virtio_transport.c
2223422253 F: net/vmw_vsock/virtio_transport_common.c
2223522254
22255+VIRTIO BALLOON
22256+M: "Michael S. Tsirkin" <mst@redhat.com>
22257+M: David Hildenbrand <david@redhat.com>
22258+L: virtualization@lists.linux-foundation.org
22259+S: Maintained
22260+F: drivers/virtio/virtio_balloon.c
22261+F: include/linux/balloon_compaction.h
22262+F: include/uapi/linux/virtio_balloon.h
22263+F: mm/balloon_compaction.c
22264+
2223622265 VIRTIO BLOCK AND SCSI DRIVERS
2223722266 M: "Michael S. Tsirkin" <mst@redhat.com>
2223822267 M: Jason Wang <jasowang@redhat.com>
@@ -22275,30 +22304,6 @@ F: include/linux/vringh.h · 36 unmodified lines
2227522304 F: include/uapi/linux/virtio_*.h
2227622305 F: tools/virtio/
2227722306
22278−VISL VIRTUAL STATELESS DECODER DRIVER
22279−M: Daniel Almeida <daniel.almeida@collabora.com>
22280−L: linux-media@vger.kernel.org
22281−S: Supported
22282−F: drivers/media/test-drivers/visl
22283−
22284−IFCVF VIRTIO DATA PATH ACCELERATOR
22285−R: Zhu Lingshan <lingshan.zhu@intel.com>
22286−F: drivers/vdpa/ifcvf/
22287−
22288−SNET DPU VIRTIO DATA PATH ACCELERATOR
22289−R: Alvaro Karsz <alvaro.karsz@solid-run.com>
22290−F: drivers/vdpa/solidrun/
22291−
22292−VIRTIO BALLOON
22293−M: "Michael S. Tsirkin" <mst@redhat.com>
22294−M: David Hildenbrand <david@redhat.com>
22295−L: virtualization@lists.linux-foundation.org
22296−S: Maintained
22297−F: drivers/virtio/virtio_balloon.c
22298−F: include/uapi/linux/virtio_balloon.h
22299−F: include/linux/balloon_compaction.h
22300−F: mm/balloon_compaction.c
22301−
2230222307 VIRTIO CRYPTO DRIVER
2230322308 M: Gonglei <arei.gonglei@huawei.com>
2230422309 L: virtualization@lists.linux-foundation.org
@@ -22359,11 +22364,20 @@ L: virtualization@lists.linux-foundation.org · 54 unmodified lines
2235922364 L: netdev@vger.kernel.org
2236022365 S: Maintained
2236122366 T: git git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git
22362−F: kernel/vhost_task.c
2236322367 F: drivers/vhost/
2236422368 F: include/linux/sched/vhost_task.h
2236522369 F: include/linux/vhost_iotlb.h
2236622370 F: include/uapi/linux/vhost.h
22371+F: kernel/vhost_task.c
22372+
22373+VIRTIO I2C DRIVER
22374+M: Conghui Chen <conghui.chen@intel.com>
22375+M: Viresh Kumar <viresh.kumar@linaro.org>
22376+L: linux-i2c@vger.kernel.org
22377+L: virtualization@lists.linux-foundation.org
22378+S: Maintained
22379+F: drivers/i2c/busses/i2c-virtio.c
22380+F: include/uapi/linux/virtio_i2c.h
2236722381
2236822382 VIRTIO INPUT DRIVER
2236922383 M: Gerd Hoffmann <kraxel@redhat.com>
@@ -22386,6 +22400,13 @@ W: https://virtio-mem.gitlab.io/ · 16 unmodified lines
2238622400 F: drivers/virtio/virtio_mem.c
2238722401 F: include/uapi/linux/virtio_mem.h
2238822402
22403+VIRTIO PMEM DRIVER
22404+M: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
22405+L: virtualization@lists.linux-foundation.org
22406+S: Maintained
22407+F: drivers/nvdimm/nd_virtio.c
22408+F: drivers/nvdimm/virtio_pmem.c
22409+
2238922410 VIRTIO SOUND DRIVER
2239022411 M: Anton Yakovlev <anton.yakovlev@opensynergy.com>
2239122412 M: "Michael S. Tsirkin" <mst@redhat.com>
@@ -22395,22 +22416,6 @@ S: Maintained · 3 unmodified lines
2239522416 F: include/uapi/linux/virtio_snd.h
2239622417 F: sound/virtio/*
2239722418
22398−VIRTIO I2C DRIVER
22399−M: Conghui Chen <conghui.chen@intel.com>
22400−M: Viresh Kumar <viresh.kumar@linaro.org>
22401−L: linux-i2c@vger.kernel.org
22402−L: virtualization@lists.linux-foundation.org
22403−S: Maintained
22404−F: drivers/i2c/busses/i2c-virtio.c
22405−F: include/uapi/linux/virtio_i2c.h
22406−
22407−VIRTIO PMEM DRIVER
22408−M: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
22409−L: virtualization@lists.linux-foundation.org
22410−S: Maintained
22411−F: drivers/nvdimm/virtio_pmem.c
22412−F: drivers/nvdimm/nd_virtio.c
22413−
2241422419 VIRTUAL BOX GUEST DEVICE DRIVER
2241522420 M: Hans de Goede <hdegoede@redhat.com>
2241622421 M: Arnd Bergmann <arnd@arndb.de>
@@ -22432,6 +22437,12 @@ S: Maintained · 15 unmodified lines
2243222437 F: drivers/input/serio/userio.c
2243322438 F: include/uapi/linux/userio.h
2243422439
22440+VISL VIRTUAL STATELESS DECODER DRIVER
22441+M: Daniel Almeida <daniel.almeida@collabora.com>
22442+L: linux-media@vger.kernel.org
22443+S: Supported
22444+F: drivers/media/test-drivers/visl
22445+
2243522446 VIVID VIRTUAL VIDEO DRIVER
2243622447 M: Hans Verkuil <hverkuil@xs4all.nl>
2243722448 L: linux-media@vger.kernel.org
@@ -22440,14 +22451,6 @@ W: https://linuxtv.org · 2 unmodified lines
2244022451 T: git git://linuxtv.org/media_tree.git
2244122452 F: drivers/media/test-drivers/vivid/*
2244222453
22443−VIDTV VIRTUAL DIGITAL TV DRIVER
22444−M: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
22445−L: linux-media@vger.kernel.org
22446−S: Maintained
22447−W: https://linuxtv.org
22448−T: git git://linuxtv.org/media_tree.git
22449−F: drivers/media/test-drivers/vidtv/*
22450−
2245122454 VLYNQ BUS
2245222455 M: Florian Fainelli <f.fainelli@gmail.com>
2245322456 L: openwrt-devel@lists.openwrt.org (subscribers-only)
@@ -22455,16 +22458,6 @@ S: Maintained · 1 unmodified line
2245522458 F: drivers/vlynq/vlynq.c
2245622459 F: include/linux/vlynq.h
2245722460
22458−VME SUBSYSTEM
22459−M: Martyn Welch <martyn@welchs.me.uk>
22460−M: Manohar Vanga <manohar.vanga@gmail.com>
22461−M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22462−L: linux-kernel@vger.kernel.org
22463−S: Odd fixes
22464−T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
22465−F: Documentation/driver-api/vme.rst
22466−F: drivers/staging/vme_user/
22467−
2246822461 VM SOCKETS (AF_VSOCK)
2246922462 M: Stefano Garzarella <sgarzare@redhat.com>
2247022463 L: virtualization@lists.linux-foundation.org
@@ -22478,6 +22471,28 @@ F: include/uapi/linux/vsockmon.h · 7 unmodified lines
2247822471 F: net/vmw_vsock/
2247922472 F: tools/testing/vsock/
2248022473
22474+VMALLOC
22475+M: Andrew Morton <akpm@linux-foundation.org>
22476+R: Uladzislau Rezki <urezki@gmail.com>
22477+R: Christoph Hellwig <hch@infradead.org>
22478+R: Lorenzo Stoakes <lstoakes@gmail.com>
22479+L: linux-mm@kvack.org
22480+S: Maintained
22481+W: http://www.linux-mm.org
22482+T: git git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
22483+F: include/linux/vmalloc.h
22484+F: mm/vmalloc.c
22485+
22486+VME SUBSYSTEM
22487+M: Martyn Welch <martyn@welchs.me.uk>
22488+M: Manohar Vanga <manohar.vanga@gmail.com>
22489+M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22490+L: linux-kernel@vger.kernel.org
22491+S: Odd fixes
22492+T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
22493+F: Documentation/driver-api/vme.rst
22494+F: drivers/staging/vme_user/
22495+
2248122496 VMWARE BALLOON DRIVER
2248222497 M: Nadav Amit <namit@vmware.com>
2248322498 R: VMware PV-Drivers Reviewers <pv-drivers@vmware.com>
@@ -22659,9 +22674,9 @@ F: drivers/input/tablet/wacom_serial4.c · 175 unmodified lines
2265922674 WANGXUN ETHERNET DRIVER
2266022675 M: Jiawen Wu <jiawenwu@trustnetic.com>
2266122676 M: Mengyuan Lou <mengyuanlou@net-swift.com>
22662−W: https://www.net-swift.com
2266322677 L: netdev@vger.kernel.org
2266422678 S: Maintained
22679+W: https://www.net-swift.com
2266522680 F: Documentation/networking/device_drivers/ethernet/wangxun/*
2266622681 F: drivers/net/ethernet/wangxun/
2266722682
@@ -22676,8 +22691,8 @@ F: Documentation/devicetree/bindings/watchdog/ · 8 unmodified lines
2267622691 F: Documentation/watchdog/
2267722692 F: drivers/watchdog/
2267822693 F: include/linux/watchdog.h
22679−F: include/uapi/linux/watchdog.h
2268022694 F: include/trace/events/watchdog.h
22695+F: include/uapi/linux/watchdog.h
2268122696
2268222697 WHISKEYCOVE PMIC GPIO DRIVER
2268322698 M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
@@ -22834,8 +22849,8 @@ R: "H. Peter Anvin" <hpa@zytor.com> · 150 unmodified lines
2283422849 L: linux-kernel@vger.kernel.org
2283522850 S: Maintained
2283622851 T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
22837−F: Documentation/devicetree/bindings/x86/
2283822852 F: Documentation/arch/x86/
22853+F: Documentation/devicetree/bindings/x86/
2283922854 F: arch/x86/
2284022855
2284122856 X86 ENTRY CODE
@@ -22966,6 +22981,8 @@ M: John Fastabend <john.fastabend@gmail.com> · 124 unmodified lines
2296622981 L: netdev@vger.kernel.org
2296722982 L: bpf@vger.kernel.org
2296822983 S: Supported
22984+F: drivers/net/ethernet/*/*/*/*/*xdp*
22985+F: drivers/net/ethernet/*/*/*xdp*
2296922986 F: include/net/xdp.h
2297022987 F: include/net/xdp_priv.h
2297122988 F: include/trace/events/xdp.h
@@ -22973,10 +22990,8 @@ F: kernel/bpf/cpumap.c · 1 unmodified line
2297322990 F: kernel/bpf/devmap.c
2297422991 F: net/core/xdp.c
2297522992 F: samples/bpf/xdp*
22976−F: tools/testing/selftests/bpf/*xdp*
2297722993 F: tools/testing/selftests/bpf/*/*xdp*
22978−F: drivers/net/ethernet/*/*/*/*/*xdp*
22979−F: drivers/net/ethernet/*/*/*xdp*
22994+F: tools/testing/selftests/bpf/*xdp*
2298022995 K: (?:\b|_)xdp(?:\b|_)
2298122996
2298222997 XDP SOCKETS (AF_XDP)
@@ -22988,11 +23003,11 @@ L: netdev@vger.kernel.org · 5 unmodified lines
2298823003 L: bpf@vger.kernel.org
2298923004 S: Maintained
2299023005 F: Documentation/networking/af_xdp.rst
23006+F: include/net/netns/xdp.h
2299123007 F: include/net/xdp_sock*
2299223008 F: include/net/xsk_buff_pool.h
2299323009 F: include/uapi/linux/if_xdp.h
2299423010 F: include/uapi/linux/xdp_diag.h
22995−F: include/net/netns/xdp.h
2299623011 F: net/xdp/
2299723012 F: tools/testing/selftests/bpf/*xsk*
2299823013
@@ -23094,11 +23109,11 @@ F: include/xen/arm/swiotlb-xen.h · 95 unmodified lines
2309423109 F: include/xen/swiotlb-xen.h
2309523110
2309623111 XFS FILESYSTEM
23097−C: irc://irc.oftc.net/xfs
2309823112 M: Darrick J. Wong <djwong@kernel.org>
2309923113 L: linux-xfs@vger.kernel.org
2310023114 S: Supported
2310123115 W: http://xfs.org/
23116+C: irc://irc.oftc.net/xfs
2310223117 T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git
2310323118 F: Documentation/ABI/testing/sysfs-fs-xfs
2310423119 F: Documentation/admin-guide/xfs.rst
@@ -23128,16 +23143,28 @@ S: Maintained · 23 unmodified lines
2312823143 F: Documentation/devicetree/bindings/net/can/xilinx,can.yaml
2312923144 F: drivers/net/can/xilinx_can.c
2313023145
23146+XILINX EVENT MANAGEMENT DRIVER
23147+M: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
23148+S: Maintained
23149+F: drivers/soc/xilinx/xlnx_event_manager.c
23150+F: include/linux/firmware/xlnx-event-manager.h
23151+
2313123152 XILINX GPIO DRIVER
2313223153 M: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
2313323154 R: Srinivas Neeli <srinivas.neeli@xilinx.com>
2313423155 R: Michal Simek <michal.simek@amd.com>
2313523156 S: Maintained
23136−F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
2313723157 F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
23158+F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
2313823159 F: drivers/gpio/gpio-xilinx.c
2313923160 F: drivers/gpio/gpio-zynq.c
2314023161
23162+XILINX PWM DRIVER
23163+M: Sean Anderson <sean.anderson@seco.com>
23164+S: Maintained
23165+F: drivers/pwm/pwm-xilinx.c
23166+F: include/clocksource/timer-xilinx.h
23167+
2314123168 XILINX SD-FEC IP CORES
2314223169 M: Derek Kiernan <derek.kiernan@xilinx.com>
2314323170 M: Dragan Cvetic <dragan.cvetic@xilinx.com>
@@ -23149,12 +23176,6 @@ F: drivers/misc/Makefile · 5 unmodified lines
2314923176 F: drivers/misc/xilinx_sdfec.c
2315023177 F: include/uapi/misc/xilinx_sdfec.h
2315123178
23152−XILINX PWM DRIVER
23153−M: Sean Anderson <sean.anderson@seco.com>
23154−S: Maintained
23155−F: drivers/pwm/pwm-xilinx.c
23156−F: include/clocksource/timer-xilinx.h
23157−
2315823179 XILINX UARTLITE SERIAL DRIVER
2315923180 M: Peter Korsgaard <jacmet@sunsite.dk>
2316023181 L: linux-serial@vger.kernel.org
@@ -23220,12 +23241,6 @@ M: Harsha <harsha.harsha@xilinx.com> · 59 unmodified lines
2322023241 S: Maintained
2322123242 F: drivers/crypto/xilinx/zynqmp-sha.c
2322223243
23223−XILINX EVENT MANAGEMENT DRIVER
23224−M: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
23225−S: Maintained
23226−F: drivers/soc/xilinx/xlnx_event_manager.c
23227−F: include/linux/firmware/xlnx-event-manager.h
23228−
2322923244 XILLYBUS DRIVER
2323023245 M: Eli Billauer <eli.billauer@gmail.com>
2323123246 L: linux-kernel@vger.kernel.org
@@ -23273,6 +23288,13 @@ S: Maintained · 41 unmodified lines
2327323288 F: Documentation/input/devices/yealink.rst
2327423289 F: drivers/input/misc/yealink.*
2327523290
23291+Z3FOLD COMPRESSED PAGE ALLOCATOR
23292+M: Vitaly Wool <vitaly.wool@konsulko.com>
23293+R: Miaohe Lin <linmiaohe@huawei.com>
23294+L: linux-mm@kvack.org
23295+S: Maintained
23296+F: mm/z3fold.c
23297+
2327623298 Z8530 DRIVER FOR AX.25
2327723299 M: Joerg Reuter <jreuter@yaina.de>
2327823300 L: linux-hams@vger.kernel.org
@@ -23290,13 +23312,6 @@ L: linux-mm@kvack.org · 11 unmodified lines
2329023312 S: Maintained
2329123313 F: mm/zbud.c
2329223314
23293−Z3FOLD COMPRESSED PAGE ALLOCATOR
23294−M: Vitaly Wool <vitaly.wool@konsulko.com>
23295−R: Miaohe Lin <linmiaohe@huawei.com>
23296−L: linux-mm@kvack.org
23297−S: Maintained
23298−F: mm/z3fold.c
23299−
2330023315 ZD1211RW WIRELESS DRIVER
2330123316 M: Ulrich Kunitz <kune@deine-taler.de>
2330223317 L: linux-wireless@vger.kernel.org
@@ -23383,10 +23398,10 @@ M: Nick Terrell <terrelln@fb.com> · 80 unmodified lines
2338323398 S: Maintained
2338423399 B: https://github.com/facebook/zstd/issues
2338523400 T: git https://github.com/terrelln/linux.git
23401+F: crypto/zstd.c
2338623402 F: include/linux/zstd*
23387−F: lib/zstd/
2338823403 F: lib/decompress_unzstd.c
23389−F: crypto/zstd.c
23404+F: lib/zstd/
2339023405 N: zstd
2339123406 K: zstd
2339223407
@@ -23398,13 +23413,6 @@ L: linux-mm@kvack.org · 5 unmodified lines
2339823413 S: Maintained
2339923414 F: mm/zswap.c
2340023415
23401−NXP BLUETOOTH WIRELESS DRIVERS
23402−M: Amitkumar Karwar <amitkumar.karwar@nxp.com>
23403−M: Neeraj Kale <neeraj.sanjaykale@nxp.com>
23404−S: Maintained
23405−F: Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml
23406−F: drivers/bluetooth/btnxpuart.c
23407−
2340823416 THE REST
2340923417 M: Linus Torvalds <torvalds@linux-foundation.org>
2341023418 L: linux-kernel@vger.kernel.org
Makefile+1−1
@@ -2,7 +2,7 @@ · 1 unmodified line
22 VERSION = 6
33 PATCHLEVEL = 4
44 SUBLEVEL = 0
5−EXTRAVERSION = -rc1
5+EXTRAVERSION = -rc2
66 NAME = Hurr durr I'ma ninja sloth
77
88 # *DOCUMENTATION*
arch/arc/include/asm/fb.h+2−14
@@ -1,20 +1,8 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
2+
23 #ifndef _ASM_FB_H_
34 #define _ASM_FB_H_
45
5−#include <linux/fb.h>
6−#include <linux/fs.h>
7−#include <asm/page.h>
8−
9−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10− unsigned long off)
11−{
12− vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
13−}
14−
15−static inline int fb_is_primary_device(struct fb_info *info)
16−{
17− return 0;
18−}
6+#include <asm-generic/fb.h>
197
208 #endif /* _ASM_FB_H_ */
arch/arm/include/asm/fb.h+1−14
@@ -1,19 +1,6 @@
11 #ifndef _ASM_FB_H_
22 #define _ASM_FB_H_
33
4−#include <linux/fb.h>
5−#include <linux/fs.h>
6−#include <asm/page.h>
7−
8−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
9− unsigned long off)
10−{
11− vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
12−}
13−
14−static inline int fb_is_primary_device(struct fb_info *info)
15−{
16− return 0;
17−}
4+#include <asm-generic/fb.h>
185
196 #endif /* _ASM_FB_H_ */
arch/arm/kernel/unwind.c+24−1
@@ -308,6 +308,29 @@ static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, · 307 unmodified lines
308308 return URC_OK;
309309 }
310310
311+static unsigned long unwind_decode_uleb128(struct unwind_ctrl_block *ctrl)
312+{
313+ unsigned long bytes = 0;
314+ unsigned long insn;
315+ unsigned long result = 0;
316+
317+ /*
318+ * unwind_get_byte() will advance `ctrl` one instruction at a time, so
319+ * loop until we get an instruction byte where bit 7 is not set.
320+ *
321+ * Note: This decodes a maximum of 4 bytes to output 28 bits data where
322+ * max is 0xfffffff: that will cover a vsp increment of 1073742336, hence
323+ * it is sufficient for unwinding the stack.
324+ */
325+ do {
326+ insn = unwind_get_byte(ctrl);
327+ result |= (insn & 0x7f) << (bytes * 7);
328+ bytes++;
329+ } while (!!(insn & 0x80) && (bytes != sizeof(result)));
330+
331+ return result;
332+}
333+
311334 /*
312335 * Execute the current unwind instruction.
313336 */
@@ -361,7 +384,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) · 47 unmodified lines
361384 if (ret)
362385 goto error;
363386 } else if (insn == 0xb2) {
364− unsigned long uleb128 = unwind_get_byte(ctrl);
387+ unsigned long uleb128 = unwind_decode_uleb128(ctrl);
365388
366389 ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
367390 } else {
arch/arm/mach-sa1100/jornada720_ssp.c+4−1
@@ -1,5 +1,5 @@
11 // SPDX-License-Identifier: GPL-2.0-only
2−/**
2+/*
33 * arch/arm/mac-sa1100/jornada720_ssp.c
44 *
55 * Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
@@ -26,6 +26,7 @@ static unsigned long jornada_ssp_flags; · 20 unmodified lines
2626
2727 /**
2828 * jornada_ssp_reverse - reverses input byte
29+ * @byte: input byte to reverse
2930 *
3031 * we need to reverse all data we receive from the mcu due to its physical location
3132 * returns : 01110111 -> 11101110
@@ -46,6 +47,7 @@ EXPORT_SYMBOL(jornada_ssp_reverse); · 14 unmodified lines
4647
4748 /**
4849 * jornada_ssp_byte - waits for ready ssp bus and sends byte
50+ * @byte: input byte to transmit
4951 *
5052 * waits for fifo buffer to clear and then transmits, if it doesn't then we will
5153 * timeout after <timeout> rounds. Needs mcu running before its called.
@@ -77,6 +79,7 @@ EXPORT_SYMBOL(jornada_ssp_byte); · 25 unmodified lines
7779
7880 /**
7981 * jornada_ssp_inout - decide if input is command or trading byte
82+ * @byte: input byte to send (may be %TXDUMMY)
8083 *
8184 * returns : (jornada_ssp_byte(byte)) on success
8285 * : %-ETIMEDOUT on timeout failure
arch/arm/vfp/entry.S+5−2
@@ -23,6 +23,9 @@ · 22 unmodified lines
2323 @
2424 ENTRY(do_vfp)
2525 mov r1, r10
26− mov r3, r9
27− b vfp_entry
26+ str lr, [sp, #-8]!
27+ add r3, sp, #4
28+ str r9, [r3]
29+ bl vfp_entry
30+ ldr pc, [sp], #8
2831 ENDPROC(do_vfp)
arch/arm/vfp/vfphw.S+4−2
@@ -172,13 +172,14 @@ vfp_hw_state_valid: · 171 unmodified lines
172172 @ out before setting an FPEXC that
173173 @ stops us reading stuff
174174 VFPFMXR FPEXC, r1 @ Restore FPEXC last
175+ mov sp, r3 @ we think we have handled things
176+ pop {lr}
175177 sub r2, r2, #4 @ Retry current instruction - if Thumb
176178 str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
177179 @ else it's one 32-bit instruction, so
178180 @ always subtract 4 from the following
179181 @ instruction address.
180182
181− mov lr, r3 @ we think we have handled things
182183 local_bh_enable_and_ret:
183184 adr r0, .
184185 mov r1, #SOFTIRQ_DISABLE_OFFSET
@@ -209,8 +210,9 @@ skip: · 24 unmodified lines
209210
210211 process_exception:
211212 DBGSTR "bounce"
213+ mov sp, r3 @ setup for a return to the user code.
214+ pop {lr}
212215 mov r2, sp @ nothing stacked - regdump is at TOS
213− mov lr, r3 @ setup for a return to the user code.
214216
215217 @ Now call the C code to package up the bounce to the support code
216218 @ r0 holds the trigger instruction
arch/arm64/include/asm/fb.h+1−14
@@ -5,19 +5,6 @@ · 4 unmodified lines
55 #ifndef __ASM_FB_H_
66 #define __ASM_FB_H_
77
8−#include <linux/fb.h>
9−#include <linux/fs.h>
10−#include <asm/page.h>
11−
12−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
13− unsigned long off)
14−{
15− vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
16−}
17−
18−static inline int fb_is_primary_device(struct fb_info *info)
19−{
20− return 0;
21−}
8+#include <asm-generic/fb.h>
229
2310 #endif /* __ASM_FB_H_ */
arch/ia64/include/asm/fb.h+23−4
@@ -2,11 +2,14 @@ · 1 unmodified line
22 #ifndef _ASM_FB_H_
33 #define _ASM_FB_H_
44
5−#include <linux/fb.h>
6−#include <linux/fs.h>
5+#include <linux/compiler.h>
76 #include <linux/efi.h>
7+#include <linux/string.h>
8+
89 #include <asm/page.h>
910
11+struct file;
12+
1013 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
1114 unsigned long off)
1215 {
@@ -15,10 +18,26 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, · 2 unmodified lines
1518 else
1619 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1720 }
21+#define fb_pgprotect fb_pgprotect
22+
23+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
24+{
25+ memcpy(to, (void __force *)from, n);
26+}
27+#define fb_memcpy_fromio fb_memcpy_fromio
1828
19−static inline int fb_is_primary_device(struct fb_info *info)
29+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
2030 {
21− return 0;
31+ memcpy((void __force *)to, from, n);
2232 }
33+#define fb_memcpy_toio fb_memcpy_toio
34+
35+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
36+{
37+ memset((void __force *)addr, c, n);
38+}
39+#define fb_memset fb_memset_io
40+
41+#include <asm-generic/fb.h>
2342
2443 #endif /* _ASM_FB_H_ */
arch/loongarch/include/asm/fb.h+16−8
@@ -5,19 +5,27 @@ · 4 unmodified lines
55 #ifndef _ASM_FB_H_
66 #define _ASM_FB_H_
77
8−#include <linux/fb.h>
9−#include <linux/fs.h>
10−#include <asm/page.h>
8+#include <linux/compiler.h>
9+#include <linux/string.h>
1110
12−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
13− unsigned long off)
11+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
1412 {
15− vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
13+ memcpy(to, (void __force *)from, n);
1614 }
15+#define fb_memcpy_fromio fb_memcpy_fromio
1716
18−static inline int fb_is_primary_device(struct fb_info *info)
17+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
1918 {
20− return 0;
19+ memcpy((void __force *)to, from, n);
2120 }
21+#define fb_memcpy_toio fb_memcpy_toio
22+
23+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
24+{
25+ memset((void __force *)addr, c, n);
26+}
27+#define fb_memset fb_memset_io
28+
29+#include <asm-generic/fb.h>
2230
2331 #endif /* _ASM_FB_H_ */
arch/m68k/include/asm/fb.h+7−15
@@ -2,22 +2,18 @@ · 1 unmodified line
22 #ifndef _ASM_FB_H_
33 #define _ASM_FB_H_
44
5−#include <linux/fb.h>
6−#include <linux/fs.h>
75 #include <asm/page.h>
86 #include <asm/setup.h>
97
10−#ifdef CONFIG_MMU
11−#ifdef CONFIG_SUN3
8+struct file;
9+
1210 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
1311 unsigned long off)
1412 {
13+#ifdef CONFIG_MMU
14+#ifdef CONFIG_SUN3
1515 pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
16−}
1716 #else
18−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
19− unsigned long off)
20−{
2117 if (CPU_IS_020_OR_030)
2218 pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
2319 if (CPU_IS_040_OR_060) {
@@ -25,15 +21,11 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, · 1 unmodified line
2521 /* Use no-cache mode, serialized */
2622 pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
2723 }
28−}
2924 #endif /* CONFIG_SUN3 */
30−#else
31−#define fb_pgprotect(...) do {} while (0)
3225 #endif /* CONFIG_MMU */
33−
34−static inline int fb_is_primary_device(struct fb_info *info)
35−{
36− return 0;
3726 }
27+#define fb_pgprotect fb_pgprotect
28+
29+#include <asm-generic/fb.h>
3830
3931 #endif /* _ASM_FB_H_ */
arch/mips/include/asm/fb.h+24−4
@@ -1,19 +1,39 @@
11 #ifndef _ASM_FB_H_
22 #define _ASM_FB_H_
33
4−#include <linux/fb.h>
5−#include <linux/fs.h>
64 #include <asm/page.h>
75
6+struct file;
7+
88 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
99 unsigned long off)
1010 {
1111 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1212 }
13+#define fb_pgprotect fb_pgprotect
1314
14−static inline int fb_is_primary_device(struct fb_info *info)
15+/*
16+ * MIPS doesn't define __raw_ I/O macros, so the helpers
17+ * in <asm-generic/fb.h> don't generate fb_readq() and
18+ * fb_write(). We have to provide them here.
19+ *
20+ * TODO: Convert MIPS to generic I/O. The helpers below can
21+ * then be removed.
22+ */
23+#ifdef CONFIG_64BIT
24+static inline u64 fb_readq(const volatile void __iomem *addr)
1525 {
16− return 0;
26+ return __raw_readq(addr);
1727 }
28+#define fb_readq fb_readq
29+
30+static inline void fb_writeq(u64 b, volatile void __iomem *addr)
31+{
32+ __raw_writeq(b, addr);
33+}
34+#define fb_writeq fb_writeq
35+#endif
36+
37+#include <asm-generic/fb.h>
1838
1939 #endif /* _ASM_FB_H_ */
arch/parisc/Makefile+3−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111 # Copyright (C) 1994 by Linus Torvalds
1212 # Portions Copyright (C) 1999 The Puffin Group
1313 #
14−# Modified for PA-RISC Linux by Paul Lahaie, Alex deVries,
14+# Modified for PA-RISC Linux by Paul Lahaie, Alex deVries,
1515 # Mike Shaver, Helge Deller and Martin K. Petersen
1616 #
1717
@@ -119,6 +119,8 @@ export LIBGCC · 101 unmodified lines
119119
120120 libs-y += arch/parisc/lib/ $(LIBGCC)
121121
122+drivers-y += arch/parisc/video/
123+
122124 boot := arch/parisc/boot
123125
124126 PALO := $(shell if (which palo 2>&1); then : ; \
arch/parisc/include/asm/fb.h+5−15
@@ -2,23 +2,13 @@ · 1 unmodified line
22 #ifndef _ASM_FB_H_
33 #define _ASM_FB_H_
44
5−#include <linux/fb.h>
6−#include <linux/fs.h>
7−#include <asm/page.h>
5+struct fb_info;
86
9−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10− unsigned long off)
11−{
12− pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
13−}
14−
15−#if defined(CONFIG_FB_STI)
7+#if defined(CONFIG_STI_CORE)
168 int fb_is_primary_device(struct fb_info *info);
17−#else
18−static inline int fb_is_primary_device(struct fb_info *info)
19−{
20− return 0;
21−}
9+#define fb_is_primary_device fb_is_primary_device
2210 #endif
2311
12+#include <asm-generic/fb.h>
13+
2414 #endif /* _ASM_FB_H_ */
arch/parisc/include/asm/pgtable.h+4−4
@@ -413,12 +413,12 @@ extern void paging_init (void); · 412 unmodified lines
413413 * For the 64bit version, the offset is extended by 32bit.
414414 */
415415 #define __swp_type(x) ((x).val & 0x1f)
416−#define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
417− (((x).val >> 8) & ~0x7) )
416+#define __swp_offset(x) ( (((x).val >> 5) & 0x7) | \
417+ (((x).val >> 10) << 3) )
418418 #define __swp_entry(type, offset) ((swp_entry_t) { \
419419 ((type) & 0x1f) | \
420− ((offset & 0x7) << 6) | \
421− ((offset & ~0x7) << 8) })
420+ ((offset & 0x7) << 5) | \
421+ ((offset >> 3) << 10) })
422422 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
423423 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
424424
arch/parisc/kernel/kexec.c+2−0
@@ -4,6 +4,8 @@ · 3 unmodified lines
44 #include <linux/console.h>
55 #include <linux/kexec.h>
66 #include <linux/delay.h>
7+#include <linux/reboot.h>
8+
79 #include <asm/cacheflush.h>
810 #include <asm/sections.h>
911
arch/parisc/video/Makefile+3−0
@@ -0,0 +1,3 @@
1+# SPDX-License-Identifier: GPL-2.0-only
2+
3+obj-$(CONFIG_STI_CORE) += fbdev.o
arch/parisc/video/fbdev.c+26−0
@@ -0,0 +1,26 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
4+ * Copyright (C) 2001-2020 Helge Deller <deller@gmx.de>
5+ * Copyright (C) 2001-2002 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
6+ */
7+
8+#include <linux/fb.h>
9+#include <linux/module.h>
10+
11+#include <video/sticore.h>
12+
13+int fb_is_primary_device(struct fb_info *info)
14+{
15+ struct sti_struct *sti;
16+
17+ sti = sti_get_rom(0);
18+
19+ /* if no built-in graphics card found, allow any fb driver as default */
20+ if (!sti)
21+ return true;
22+
23+ /* return true if it's the default built-in framebuffer driver */
24+ return (sti->info == info);
25+}
26+EXPORT_SYMBOL(fb_is_primary_device);
arch/powerpc/include/asm/fb.h+3−5
@@ -2,8 +2,8 @@ · 1 unmodified line
22 #ifndef _ASM_FB_H_
33 #define _ASM_FB_H_
44
5−#include <linux/fb.h>
65 #include <linux/fs.h>
6+
77 #include <asm/page.h>
88
99 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
@@ -13,10 +13,8 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, · 3 unmodified lines
1313 vma->vm_end - vma->vm_start,
1414 vma->vm_page_prot);
1515 }
16+#define fb_pgprotect fb_pgprotect
1617
17−static inline int fb_is_primary_device(struct fb_info *info)
18−{
19− return 0;
20−}
18+#include <asm-generic/fb.h>
2119
2220 #endif /* _ASM_FB_H_ */
arch/riscv/kernel/pi/Makefile+1−1
@@ -22,7 +22,7 @@ KCOV_INSTRUMENT := n · 21 unmodified lines
2222
2323 $(obj)/%.pi.o: OBJCOPYFLAGS := --prefix-symbols=__pi_ \
2424 --remove-section=.note.gnu.property \
25− --prefix-alloc-sections=.init
25+ --prefix-alloc-sections=.init.pi
2626 $(obj)/%.pi.o: $(obj)/%.o FORCE
2727 $(call if_changed,objcopy)
2828
arch/riscv/kernel/vmlinux.lds.S+2−5
@@ -84,11 +84,8 @@ SECTIONS · 83 unmodified lines
8484 __init_data_begin = .;
8585 INIT_DATA_SECTION(16)
8686
87− /* Those sections result from the compilation of kernel/pi/string.c */
88− .init.pidata : {
89− *(.init.srodata.cst8*)
90− *(.init__bug_table*)
91− *(.init.sdata*)
87+ .init.pi : {
88+ *(.init.pi*)
9289 }
9390
9491 .init.bss : {
arch/sh/include/asm/fb.h+1−14
@@ -2,19 +2,6 @@ · 1 unmodified line
22 #ifndef _ASM_FB_H_
33 #define _ASM_FB_H_
44
5−#include <linux/fb.h>
6−#include <linux/fs.h>
7−#include <asm/page.h>
8−
9−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10− unsigned long off)
11−{
12− vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
13−}
14−
15−static inline int fb_is_primary_device(struct fb_info *info)
16−{
17− return 0;
18−}
5+#include <asm-generic/fb.h>
196
207 #endif /* _ASM_FB_H_ */
arch/sparc/Makefile+1−0
@@ -60,6 +60,7 @@ libs-y += arch/sparc/prom/ · 59 unmodified lines
6060 libs-y += arch/sparc/lib/
6161
6262 drivers-$(CONFIG_PM) += arch/sparc/power/
63+drivers-$(CONFIG_FB) += arch/sparc/video/
6364
6465 boot := arch/sparc/boot
6566
arch/sparc/include/asm/fb.h+27−20
@@ -1,34 +1,41 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
22 #ifndef _SPARC_FB_H_
33 #define _SPARC_FB_H_
4−#include <linux/console.h>
5−#include <linux/fb.h>
6−#include <linux/fs.h>
7−#include <asm/page.h>
8−#include <asm/prom.h>
94
5+#include <linux/io.h>
6+
7+struct fb_info;
8+struct file;
9+struct vm_area_struct;
10+
11+#ifdef CONFIG_SPARC32
1012 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
1113 unsigned long off)
12−{
13−#ifdef CONFIG_SPARC64
14− vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
14+{ }
15+#define fb_pgprotect fb_pgprotect
1516 #endif
16−}
1717
18−static inline int fb_is_primary_device(struct fb_info *info)
19−{
20− struct device *dev = info->device;
21− struct device_node *node;
18+int fb_is_primary_device(struct fb_info *info);
19+#define fb_is_primary_device fb_is_primary_device
2220
23− if (console_set_on_cmdline)
24− return 0;
21+static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
22+{
23+ sbus_memcpy_fromio(to, from, n);
24+}
25+#define fb_memcpy_fromio fb_memcpy_fromio
2526
26− node = dev->of_node;
27− if (node &&
28− node == of_console_device)
29− return 1;
27+static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n)
28+{
29+ sbus_memcpy_toio(to, from, n);
30+}
31+#define fb_memcpy_toio fb_memcpy_toio
3032
31− return 0;
33+static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
34+{
35+ sbus_memset_io(addr, c, n);
3236 }
37+#define fb_memset fb_memset_io
38+
39+#include <asm-generic/fb.h>
3340
3441 #endif /* _SPARC_FB_H_ */
arch/sparc/video/Makefile+3−0
@@ -0,0 +1,3 @@
1+# SPDX-License-Identifier: GPL-2.0-only
2+
3+obj-$(CONFIG_FB) += fbdev.o
arch/sparc/video/fbdev.c+23−0
@@ -0,0 +1,23 @@
1+// SPDX-License-Identifier: GPL-2.0
2+
3+#include <linux/console.h>
4+#include <linux/fb.h>
5+#include <linux/module.h>
6+
7+#include <asm/prom.h>
8+
9+int fb_is_primary_device(struct fb_info *info)
10+{
11+ struct device *dev = info->device;
12+ struct device_node *node;
13+
14+ if (console_set_on_cmdline)
15+ return 0;
16+
17+ node = dev->of_node;
18+ if (node && node == of_console_device)
19+ return 1;
20+
21+ return 0;
22+}
23+EXPORT_SYMBOL(fb_is_primary_device);
arch/x86/events/core.c+2−4
@@ -1703,10 +1703,8 @@ int x86_pmu_handle_irq(struct pt_regs *regs) · 1702 unmodified lines
17031703
17041704 perf_sample_data_init(&data, 0, event->hw.last_period);
17051705
1706− if (has_branch_stack(event)) {
1707− data.br_stack = &cpuc->lbr_stack;
1708− data.sample_flags |= PERF_SAMPLE_BRANCH_STACK;
1709− }
1706+ if (has_branch_stack(event))
1707+ perf_sample_save_brstack(&data, event, &cpuc->lbr_stack);
17101708
17111709 if (perf_event_overflow(event, &data, regs))
17121710 x86_pmu_stop(event, 0);
arch/x86/events/intel/ds.c+32−24
@@ -1229,12 +1229,14 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 1228 unmodified lines
12291229 struct perf_event *event, bool add)
12301230 {
12311231 struct pmu *pmu = event->pmu;
1232+
12321233 /*
12331234 * Make sure we get updated with the first PEBS
12341235 * event. It will trigger also during removal, but
12351236 * that does not hurt:
12361237 */
1237− bool update = cpuc->n_pebs == 1;
1238+ if (cpuc->n_pebs == 1)
1239+ cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW;
12381240
12391241 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
12401242 if (!needed_cb)
@@ -1242,7 +1244,7 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 1 unmodified line
12421244 else
12431245 perf_sched_cb_dec(pmu);
12441246
1245− update = true;
1247+ cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW;
12461248 }
12471249
12481250 /*
@@ -1252,24 +1254,13 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, · 3 unmodified lines
12521254 if (x86_pmu.intel_cap.pebs_baseline && add) {
12531255 u64 pebs_data_cfg;
12541256
1255− /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1256− if (cpuc->n_pebs == 1) {
1257− cpuc->pebs_data_cfg = 0;
1258− cpuc->pebs_record_size = sizeof(struct pebs_basic);
1259− }
1260−
12611257 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1262−
1263− /* Update pebs_record_size if new event requires more data. */
1264− if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1265− cpuc->pebs_data_cfg |= pebs_data_cfg;
1266− adaptive_pebs_record_size_update();
1267− update = true;
1268− }
1258+ /*
1259+ * Be sure to update the thresholds when we change the record.
1260+ */
1261+ if (pebs_data_cfg & ~cpuc->pebs_data_cfg)
1262+ cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW;
12691263 }
1270−
1271− if (update)
1272− pebs_update_threshold(cpuc);
12731264 }
12741265
12751266 void intel_pmu_pebs_add(struct perf_event *event)
@@ -1326,9 +1317,17 @@ static void intel_pmu_pebs_via_pt_enable(struct perf_event *event) · 50 unmodified lines
13261317 wrmsrl(base + idx, value);
13271318 }
13281319
1320+static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
1321+{
1322+ if (cpuc->n_pebs == cpuc->n_large_pebs &&
1323+ cpuc->n_pebs != cpuc->n_pebs_via_pt)
1324+ intel_pmu_drain_pebs_buffer();
1325+}
1326+
13291327 void intel_pmu_pebs_enable(struct perf_event *event)
13301328 {
13311329 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1330+ u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW;
13321331 struct hw_perf_event *hwc = &event->hw;
13331332 struct debug_store *ds = cpuc->ds;
13341333 unsigned int idx = hwc->idx;
@@ -1344,11 +1343,22 @@ void intel_pmu_pebs_enable(struct perf_event *event) · 9 unmodified lines
13441343
13451344 if (x86_pmu.intel_cap.pebs_baseline) {
13461345 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1347− if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1348− wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1349− cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1346+ if (pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1347+ /*
1348+ * drain_pebs() assumes uniform record size;
1349+ * hence we need to drain when changing said
1350+ * size.
1351+ */
1352+ intel_pmu_drain_large_pebs(cpuc);
1353+ adaptive_pebs_record_size_update();
1354+ wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg);
1355+ cpuc->active_pebs_data_cfg = pebs_data_cfg;
13501356 }
13511357 }
1358+ if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) {
1359+ cpuc->pebs_data_cfg = pebs_data_cfg;
1360+ pebs_update_threshold(cpuc);
1361+ }
13521362
13531363 if (idx >= INTEL_PMC_IDX_FIXED) {
13541364 if (x86_pmu.intel_cap.pebs_format < 5)
@@ -1391,9 +1401,7 @@ void intel_pmu_pebs_disable(struct perf_event *event) · 36 unmodified lines
13911401 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
13921402 struct hw_perf_event *hwc = &event->hw;
13931403
1394− if (cpuc->n_pebs == cpuc->n_large_pebs &&
1395− cpuc->n_pebs != cpuc->n_pebs_via_pt)
1396− intel_pmu_drain_pebs_buffer();
1404+ intel_pmu_drain_large_pebs(cpuc);
13971405
13981406 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
13991407
arch/x86/include/asm/fb.h+8−13
@@ -2,21 +2,16 @@ · 1 unmodified line
22 #ifndef _ASM_X86_FB_H
33 #define _ASM_X86_FB_H
44
5−#include <linux/fb.h>
6−#include <linux/fs.h>
7−#include <asm/page.h>
5+struct fb_info;
6+struct file;
7+struct vm_area_struct;
88
9−static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10− unsigned long off)
11−{
12− unsigned long prot;
9+void fb_pgprotect(struct file *file, struct vm_area_struct *vma, unsigned long off);
10+#define fb_pgprotect fb_pgprotect
1311
14− prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
15− if (boot_cpu_data.x86 > 3)
16− pgprot_val(vma->vm_page_prot) =
17− prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
18−}
12+int fb_is_primary_device(struct fb_info *info);
13+#define fb_is_primary_device fb_is_primary_device
1914
20−extern int fb_is_primary_device(struct fb_info *info);
15+#include <asm-generic/fb.h>
2116
2217 #endif /* _ASM_X86_FB_H */
arch/x86/include/asm/perf_event.h+3−0
@@ -121,6 +121,9 @@ · 120 unmodified lines
121121 #define PEBS_DATACFG_LBRS BIT_ULL(3)
122122 #define PEBS_DATACFG_LBR_SHIFT 24
123123
124+/* Steal the highest bit of pebs_data_cfg for SW usage */
125+#define PEBS_UPDATE_DS_SW BIT_ULL(63)
126+
124127 /*
125128 * Intel "Architectural Performance Monitoring" CPUID
126129 * detection/enumeration details:
arch/x86/kernel/amd_nb.c+2−0
@@ -36,6 +36,7 @@ · 35 unmodified lines
3636 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
3737 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
3838 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
39+#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
3940
4041 /* Protect the PCI config register pairs used for SMN. */
4142 static DEFINE_MUTEX(smn_mutex);
@@ -79,6 +80,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = { · 37 unmodified lines
7980 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
8081 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
8182 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
83+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
8284 {}
8385 };
8486
arch/x86/lib/retpoline.S+2−2
@@ -144,8 +144,8 @@ SYM_CODE_END(__x86_indirect_jump_thunk_array) · 143 unmodified lines
144144 */
145145 .align 64
146146 .skip 63, 0xcc
147−SYM_FUNC_START_NOALIGN(zen_untrain_ret);
148−
147+SYM_START(zen_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
148+ ANNOTATE_NOENDBR
149149 /*
150150 * As executed from zen_untrain_ret, this is:
151151 *
arch/x86/video/fbdev.c+15−13
@@ -6,35 +6,37 @@ · 5 unmodified lines
66 * for more details.
77 *
88 */
9+
910 #include <linux/fb.h>
10−#include <linux/pci.h>
1111 #include <linux/module.h>
12+#include <linux/pci.h>
1213 #include <linux/vgaarb.h>
1314
15+void fb_pgprotect(struct file *file, struct vm_area_struct *vma, unsigned long off)
16+{
17+ unsigned long prot;
18+
19+ prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
20+ if (boot_cpu_data.x86 > 3)
21+ pgprot_val(vma->vm_page_prot) =
22+ prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
23+}
24+EXPORT_SYMBOL(fb_pgprotect);
25+
1426 int fb_is_primary_device(struct fb_info *info)
1527 {
1628 struct device *device = info->device;
17− struct pci_dev *default_device = vga_default_device();
1829 struct pci_dev *pci_dev;
19− struct resource *res;
2030
2131 if (!device || !dev_is_pci(device))
2232 return 0;
2333
2434 pci_dev = to_pci_dev(device);
2535
26− if (default_device) {
27− if (pci_dev == default_device)
28− return 1;
29− return 0;
30− }
31−
32− res = pci_dev->resource + PCI_ROM_RESOURCE;
33−
34− if (res->flags & IORESOURCE_ROM_SHADOW)
36+ if (pci_dev == vga_default_device())
3537 return 1;
36−
3738 return 0;
3839 }
3940 EXPORT_SYMBOL(fb_is_primary_device);
41+
4042 MODULE_LICENSE("GPL");
drivers/auxdisplay/cfag12864bfb.c+1−1
@@ -72,7 +72,7 @@ static int cfag12864bfb_probe(struct platform_device *device) · 71 unmodified lines
7272 if (!info)
7373 goto none;
7474
75− info->screen_base = (char __iomem *) cfag12864b_buffer;
75+ info->screen_buffer = cfag12864b_buffer;
7676 info->screen_size = CFAG12864B_SIZE;
7777 info->fbops = &cfag12864bfb_ops;
7878 info->fix = cfag12864bfb_fix;
drivers/auxdisplay/ht16k33.c+1−1
@@ -640,7 +640,7 @@ static int ht16k33_fbdev_probe(struct device *dev, struct ht16k33_priv *priv, · 639 unmodified lines
640640
641641 INIT_DELAYED_WORK(&priv->work, ht16k33_fb_update);
642642 fbdev->info->fbops = &ht16k33_fb_ops;
643− fbdev->info->screen_base = (char __iomem *) fbdev->buffer;
643+ fbdev->info->screen_buffer = fbdev->buffer;
644644 fbdev->info->screen_size = HT16K33_FB_SIZE;
645645 fbdev->info->fix = ht16k33_fb_fix;
646646 fbdev->info->var = ht16k33_fb_var;
drivers/block/nbd.c+2−2
@@ -1666,7 +1666,7 @@ static int nbd_dev_dbg_init(struct nbd_device *nbd) · 1665 unmodified lines
16661666 return -EIO;
16671667
16681668 dir = debugfs_create_dir(nbd_name(nbd), nbd_dbg_dir);
1669− if (!dir) {
1669+ if (IS_ERR(dir)) {
16701670 dev_err(nbd_to_dev(nbd), "Failed to create debugfs dir for '%s'\n",
16711671 nbd_name(nbd));
16721672 return -EIO;
@@ -1692,7 +1692,7 @@ static int nbd_dbg_init(void) · 19 unmodified lines
16921692 struct dentry *dbg_dir;
16931693
16941694 dbg_dir = debugfs_create_dir("nbd", NULL);
1695− if (!dbg_dir)
1695+ if (IS_ERR(dbg_dir))
16961696 return -EIO;
16971697
16981698 nbd_dbg_dir = dbg_dir;
drivers/block/rnbd/rnbd-proto.h+1−1
@@ -241,7 +241,7 @@ static inline blk_opf_t rnbd_to_bio_flags(u32 rnbd_opf) · 240 unmodified lines
241241 bio_opf = REQ_OP_WRITE;
242242 break;
243243 case RNBD_OP_FLUSH:
244− bio_opf = REQ_OP_FLUSH | REQ_PREFLUSH;
244+ bio_opf = REQ_OP_WRITE | REQ_PREFLUSH;
245245 break;
246246 case RNBD_OP_DISCARD:
247247 bio_opf = REQ_OP_DISCARD;
drivers/block/ublk_drv.c+1−1
@@ -1281,7 +1281,7 @@ static inline int ublk_check_cmd_op(u32 cmd_op) · 1280 unmodified lines
12811281 {
12821282 u32 ioc_type = _IOC_TYPE(cmd_op);
12831283
1284− if (IS_ENABLED(CONFIG_BLKDEV_UBLK_LEGACY_OPCODES) && ioc_type != 'u')
1284+ if (!IS_ENABLED(CONFIG_BLKDEV_UBLK_LEGACY_OPCODES) && ioc_type != 'u')
12851285 return -EOPNOTSUPP;
12861286
12871287 if (ioc_type != 'u' && ioc_type != 0)
drivers/cxl/core/pci.c+1−0
@@ -571,6 +571,7 @@ void read_cdat_data(struct cxl_port *port) · 570 unmodified lines
571571 /* Don't leave table data allocated on error */
572572 devm_kfree(dev, cdat_table);
573573 dev_err(dev, "CDAT data read error\n");
574+ return;
574575 }
575576
576577 port->cdat.table = cdat_table + sizeof(__le32);
drivers/dma-buf/dma-resv.c+1−1
@@ -660,7 +660,7 @@ EXPORT_SYMBOL_GPL(dma_resv_get_singleton); · 659 unmodified lines
660660 * dma_resv_lock() already
661661 * RETURNS
662662 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or
663− * greater than zer on success.
663+ * greater than zero on success.
664664 */
665665 long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage,
666666 bool intr, unsigned long timeout)
drivers/dma-buf/sw_sync.c+1−1
@@ -85,7 +85,7 @@ static struct sync_timeline *sync_timeline_create(const char *name) · 84 unmodified lines
8585
8686 kref_init(&obj->kref);
8787 obj->context = dma_fence_context_alloc(1);
88− strlcpy(obj->name, name, sizeof(obj->name));
88+ strscpy(obj->name, name, sizeof(obj->name));
8989
9090 obj->pt_tree = RB_ROOT;
9191 INIT_LIST_HEAD(&obj->pt_list);
drivers/firewire/net.c+11−10
@@ -706,21 +706,22 @@ static void fwnet_receive_packet(struct fw_card *card, struct fw_request *r, · 705 unmodified lines
706706 int rcode;
707707
708708 if (destination == IEEE1394_ALL_NODES) {
709− kfree(r);
710−
711− return;
712− }
713−
714− if (offset != dev->handler.offset)
709+ // Although the response to the broadcast packet is not necessarily required, the
710+ // fw_send_response() function should still be called to maintain the reference
711+ // counting of the object. In the case, the call of function just releases the
712+ // object as a result to decrease the reference counting.
713+ rcode = RCODE_COMPLETE;
714+ } else if (offset != dev->handler.offset) {
715715 rcode = RCODE_ADDRESS_ERROR;
716− else if (tcode != TCODE_WRITE_BLOCK_REQUEST)
716+ } else if (tcode != TCODE_WRITE_BLOCK_REQUEST) {
717717 rcode = RCODE_TYPE_ERROR;
718− else if (fwnet_incoming_packet(dev, payload, length,
719− source, generation, false) != 0) {
718+ } else if (fwnet_incoming_packet(dev, payload, length,
719+ source, generation, false) != 0) {
720720 dev_err(&dev->netdev->dev, "incoming packet failure\n");
721721 rcode = RCODE_CONFLICT_ERROR;
722− } else
722+ } else {
723723 rcode = RCODE_COMPLETE;
724+ }
724725
725726 fw_send_response(card, r, rcode);
726727 }
drivers/firmware/sysfb.c+1−1
@@ -128,4 +128,4 @@ unlock_mutex: · 127 unmodified lines
128128 }
129129
130130 /* must execute after PCI subsystem for EFI quirks */
131−device_initcall(sysfb_init);
131+subsys_initcall_sync(sysfb_init);
drivers/firmware/sysfb_simplefb.c+3−1
@@ -51,7 +51,8 @@ __init bool sysfb_parse_mode(const struct screen_info *si, · 50 unmodified lines
5151 *
5252 * It's not easily possible to fix this in struct screen_info,
5353 * as this could break UAPI. The best solution is to compute
54− * bits_per_pixel here and ignore lfb_depth. In the loop below,
54+ * bits_per_pixel from the color bits, reserved bits and
55+ * reported lfb_depth, whichever is highest. In the loop below,
5556 * ignore simplefb formats with alpha bits, as EFI and VESA
5657 * don't specify alpha channels.
5758 */
@@ -60,6 +61,7 @@ __init bool sysfb_parse_mode(const struct screen_info *si, · 2 unmodified lines
6061 si->green_size + si->green_pos,
6162 si->blue_size + si->blue_pos),
6263 si->rsvd_size + si->rsvd_pos);
64+ bits_per_pixel = max_t(u32, bits_per_pixel, si->lfb_depth);
6365 } else {
6466 bits_per_pixel = si->lfb_depth;
6567 }
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+11−1
@@ -3757,6 +3757,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 3756 unmodified lines
37573757 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
37583758 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
37593759 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3760+ /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
3761+ * internal path natively support atomics, set have_atomics_support to true.
3762+ */
3763+ else if ((adev->flags & AMD_IS_APU) &&
3764+ (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)))
3765+ adev->have_atomics_support = true;
37603766 else
37613767 adev->have_atomics_support =
37623768 !pci_enable_atomic_ops_to_root(adev->pdev,
@@ -4506,7 +4512,11 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) · 743 unmodified lines
45064512 dev_info(adev->dev, "recover vram bo from shadow start\n");
45074513 mutex_lock(&adev->shadow_list_lock);
45084514 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4509− shadow = &vmbo->bo;
4515+ /* If vm is compute context or adev is APU, shadow will be NULL */
4516+ if (!vmbo->shadow)
4517+ continue;
4518+ shadow = vmbo->shadow;
4519+
45104520 /* No need to recover an evicted BO */
45114521 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
45124522 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+5−3
@@ -687,9 +687,11 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r · 686 unmodified lines
687687 if (r)
688688 return r;
689689
690− r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
691− if (r)
692− goto late_fini;
690+ if (adev->gfx.cp_ecc_error_irq.funcs) {
691+ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
692+ if (r)
693+ goto late_fini;
694+ }
693695 } else {
694696 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
695697 }
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+0−46
@@ -1315,13 +1315,6 @@ static int gfx_v11_0_sw_init(void *handle) · 1314 unmodified lines
13151315 if (r)
13161316 return r;
13171317
1318− /* ECC error */
1319− r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1320− GFX_11_0_0__SRCID__CP_ECC_ERROR,
1321− &adev->gfx.cp_ecc_error_irq);
1322− if (r)
1323− return r;
1324−
13251318 /* FED error */
13261319 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
13271320 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
@@ -4444,7 +4437,6 @@ static int gfx_v11_0_hw_fini(void *handle) · 3116 unmodified lines
44444437 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
44454438 int r;
44464439
4447− amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
44484440 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
44494441 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
44504442
@@ -5897,36 +5889,6 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev · 1446 unmodified lines
58975889 }
58985890 }
58995891
5900−#define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1
5901−#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \
5902− do { \
5903− uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \
5904− tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \
5905− WREG32_SOC15_IP(GC, reg_addr, tmp); \
5906− } while (0)
5907−
5908−static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5909− struct amdgpu_irq_src *source,
5910− unsigned type,
5911− enum amdgpu_interrupt_state state)
5912−{
5913− uint32_t ecc_irq_state = 0;
5914− uint32_t pipe0_int_cntl_addr = 0;
5915− int i = 0;
5916−
5917− ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;
5918−
5919− pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5920−
5921− WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);
5922−
5923− for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)
5924− SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,
5925− ecc_irq_state);
5926−
5927− return 0;
5928−}
5929−
59305892 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
59315893 struct amdgpu_irq_src *src,
59325894 unsigned type,
@@ -6341,11 +6303,6 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { · 408 unmodified lines
63416303 .process = gfx_v11_0_priv_inst_irq,
63426304 };
63436305
6344−static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {
6345− .set = gfx_v11_0_set_cp_ecc_error_state,
6346− .process = amdgpu_gfx_cp_ecc_error_irq,
6347−};
6348−
63496306 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
63506307 .process = gfx_v11_0_rlc_gc_fed_irq,
63516308 };
@@ -6361,9 +6318,6 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) · 9 unmodified lines
63616318 adev->gfx.priv_inst_irq.num_types = 1;
63626319 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
63636320
6364− adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */
6365− adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;
6366−
63676321 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
63686322 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
63696323
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+2−1
@@ -3764,7 +3764,8 @@ static int gfx_v9_0_hw_fini(void *handle) · 3763 unmodified lines
37643764 {
37653765 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
37663766
3767− amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3767+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
3768+ amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
37683769 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
37693770 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
37703771
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c+1−0
@@ -54,6 +54,7 @@ static int jpeg_v3_0_early_init(void *handle) · 53 unmodified lines
5454
5555 switch (adev->ip_versions[UVD_HWIP][0]) {
5656 case IP_VERSION(3, 1, 1):
57+ case IP_VERSION(3, 1, 2):
5758 break;
5859 default:
5960 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
drivers/gpu/drm/amd/amdgpu/nv.c+16−6
@@ -98,6 +98,16 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = · 97 unmodified lines
9898 };
9999
100100 /* Sienna Cichlid */
101+static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
102+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
103+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
104+};
105+
106+static const struct amdgpu_video_codecs sc_video_codecs_encode = {
107+ .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
108+ .codec_array = sc_video_codecs_encode_array,
109+};
110+
101111 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
102112 {
103113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
@@ -136,8 +146,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = · 32 unmodified lines
136146 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
137147 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
138148 {
139− {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
140− {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
149+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
150+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
141151 };
142152
143153 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
@@ -237,12 +247,12 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, · 93 unmodified lines
237247 } else {
238248 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
239249 if (encode)
240− *codecs = &nv_video_codecs_encode;
250+ *codecs = &sc_video_codecs_encode;
241251 else
242252 *codecs = &sc_video_codecs_decode_vcn1;
243253 } else {
244254 if (encode)
245− *codecs = &nv_video_codecs_encode;
255+ *codecs = &sc_video_codecs_encode;
246256 else
247257 *codecs = &sc_video_codecs_decode_vcn0;
248258 }
@@ -251,14 +261,14 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, · 2 unmodified lines
251261 case IP_VERSION(3, 0, 16):
252262 case IP_VERSION(3, 0, 2):
253263 if (encode)
254− *codecs = &nv_video_codecs_encode;
264+ *codecs = &sc_video_codecs_encode;
255265 else
256266 *codecs = &sc_video_codecs_decode_vcn0;
257267 return 0;
258268 case IP_VERSION(3, 1, 1):
259269 case IP_VERSION(3, 1, 2):
260270 if (encode)
261− *codecs = &nv_video_codecs_encode;
271+ *codecs = &sc_video_codecs_encode;
262272 else
263273 *codecs = &yc_video_codecs_decode;
264274 return 0;
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+5−3
@@ -1917,9 +1917,11 @@ static int sdma_v4_0_hw_fini(void *handle) · 1916 unmodified lines
19171917 return 0;
19181918 }
19191919
1920− for (i = 0; i < adev->sdma.num_instances; i++) {
1921− amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1922− AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1920+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1921+ for (i = 0; i < adev->sdma.num_instances; i++) {
1922+ amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1923+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1924+ }
19231925 }
19241926
19251927 sdma_v4_0_ctx_switch_enable(adev, false);
drivers/gpu/drm/amd/amdgpu/soc21.c+1−1
@@ -711,7 +711,7 @@ static int soc21_common_early_init(void *handle) · 710 unmodified lines
711711 AMD_PG_SUPPORT_VCN_DPG |
712712 AMD_PG_SUPPORT_GFX_PG |
713713 AMD_PG_SUPPORT_JPEG;
714− adev->external_rev_id = adev->rev_id + 0x1;
714+ adev->external_rev_id = adev->rev_id + 0x80;
715715 break;
716716
717717 default:
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c+65−0
@@ -423,3 +423,68 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool · 422 unmodified lines
423423
424424 PERF_TRACE();
425425 }
426+static void apply_symclk_on_tx_off_wa(struct dc_link *link)
427+{
428+ /* There are use cases where SYMCLK is referenced by OTG. For instance
429+ * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
430+ * However current link interface will power off PHY when disabling link
431+ * output. This will turn off SYMCLK generated by PHY. The workaround is
432+ * to identify such case where SYMCLK is still in use by OTG when we
433+ * power off PHY. When this is detected, we will temporarily power PHY
434+ * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
435+ * program_pix_clk interface. When OTG is disabled, we will then power
436+ * off PHY by calling disable link output again.
437+ *
438+ * In future dcn generations, we plan to rework transmitter control
439+ * interface so that we could have an option to set SYMCLK ON TX OFF
440+ * state in one step without this workaround
441+ */
442+
443+ struct dc *dc = link->ctx->dc;
444+ struct pipe_ctx *pipe_ctx = NULL;
445+ uint8_t i;
446+
447+ if (link->phy_state.symclk_ref_cnts.otg > 0) {
448+ for (i = 0; i < MAX_PIPES; i++) {
449+ pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
450+ if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
451+ pipe_ctx->clock_source->funcs->program_pix_clk(
452+ pipe_ctx->clock_source,
453+ &pipe_ctx->stream_res.pix_clk_params,
454+ dc->link_srv->dp_get_encoding_format(
455+ &pipe_ctx->link_config.dp_link_settings),
456+ &pipe_ctx->pll_settings);
457+ link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
458+ break;
459+ }
460+ }
461+ }
462+}
463+
464+void dcn314_disable_link_output(struct dc_link *link,
465+ const struct link_resource *link_res,
466+ enum signal_type signal)
467+{
468+ struct dc *dc = link->ctx->dc;
469+ const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
470+ struct dmcu *dmcu = dc->res_pool->dmcu;
471+
472+ if (signal == SIGNAL_TYPE_EDP &&
473+ link->dc->hwss.edp_backlight_control)
474+ link->dc->hwss.edp_backlight_control(link, false);
475+ else if (dmcu != NULL && dmcu->funcs->lock_phy)
476+ dmcu->funcs->lock_phy(dmcu);
477+
478+ link_hwss->disable_link_output(link, link_res, signal);
479+ link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
480+ /*
481+ * Add the logic to extract BOTH power up and power down sequences
482+ * from enable/disable link output and only call edp panel control
483+ * in enable_link_dp and disable_link_dp once.
484+ */
485+ if (dmcu != NULL && dmcu->funcs->lock_phy)
486+ dmcu->funcs->unlock_phy(dmcu);
487+ dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
488+
489+ apply_symclk_on_tx_off_wa(link);
490+}
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h+2−0
@@ -45,4 +45,6 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool · 44 unmodified lines
4545
4646 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
4747
48+void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal);
49+
4850 #endif /* __DC_HWSS_DCN314_H__ */
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c+1−1
@@ -105,7 +105,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { · 104 unmodified lines
105105 .enable_lvds_link_output = dce110_enable_lvds_link_output,
106106 .enable_tmds_link_output = dce110_enable_tmds_link_output,
107107 .enable_dp_link_output = dce110_enable_dp_link_output,
108− .disable_link_output = dce110_disable_link_output,
108+ .disable_link_output = dcn314_disable_link_output,
109109 .z10_restore = dcn31_z10_restore,
110110 .z10_save_init = dcn31_z10_save_init,
111111 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c+3−2
@@ -810,7 +810,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman · 809 unmodified lines
810810 v->SwathHeightY[k],
811811 v->SwathHeightC[k],
812812 TWait,
813− v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
813+ (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
814+ v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?
814815 mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
815816 /* Output */
816817 &v->DSTXAfterScaler[k],
@@ -3310,7 +3311,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 2493 unmodified lines
33103311 v->swath_width_chroma_ub_this_state[k],
33113312 v->SwathHeightYThisState[k],
33123313 v->SwathHeightCThisState[k], v->TWait,
3313− v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
3314+ (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?
33143315 mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
33153316
33163317 /* Output */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h+1−0
@@ -53,6 +53,7 @@ · 52 unmodified lines
5353 #define BPP_BLENDED_PIPE 0xffffffff
5454
5555 #define MEM_STROBE_FREQ_MHZ 1600
56+#define MIN_DCFCLK_FREQ_MHZ 200
5657 #define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
5758
5859 struct display_mode_lib;
drivers/gpu/drm/amd/pm/amdgpu_dpm.c+18−7
@@ -36,6 +36,8 @@ · 35 unmodified lines
3636 #define amdgpu_dpm_enable_bapm(adev, e) \
3737 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
3838
39+#define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev))
40+
3941 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
4042 {
4143 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
@@ -1460,15 +1462,24 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, · 1418 unmodified lines
14601462
14611463 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
14621464 {
1463− struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1464− struct smu_context *smu = adev->powerplay.pp_handle;
1465+ if (is_support_sw_smu(adev)) {
1466+ struct smu_context *smu = adev->powerplay.pp_handle;
14651467
1466− if ((is_support_sw_smu(adev) && smu->od_enabled) ||
1467− (is_support_sw_smu(adev) && smu->is_apu) ||
1468− (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1469− return true;
1468+ return (smu->od_enabled || smu->is_apu);
1469+ } else {
1470+ struct pp_hwmgr *hwmgr;
14701471
1471− return false;
1472+ /*
1473+ * dpm on some legacy asics don't carry od_enabled member
1474+ * as its pp_handle is casted directly from adev.
1475+ */
1476+ if (amdgpu_dpm_is_legacy_dpm(adev))
1477+ return false;
1478+
1479+ hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
1480+
1481+ return hwmgr->od_enabled;
1482+ }
14721483 }
14731484
14741485 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
drivers/gpu/drm/arm/hdlcd_drv.c+1−1
@@ -285,7 +285,7 @@ static int hdlcd_drm_bind(struct device *dev) · 284 unmodified lines
285285 */
286286 if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
287287 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
288− drm_aperture_remove_framebuffers(false, &hdlcd_driver);
288+ drm_aperture_remove_framebuffers(&hdlcd_driver);
289289 }
290290
291291 drm_mode_config_reset(drm);
drivers/gpu/drm/armada/Makefile+2−1
@@ -1,7 +1,8 @@
11 # SPDX-License-Identifier: GPL-2.0
2−armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \
2+armada-y := armada_crtc.o armada_drv.o armada_fb.o \
33 armada_gem.o armada_overlay.o armada_plane.o armada_trace.o
44 armada-y += armada_510.o
55 armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
6+armada-$(CONFIG_DRM_FBDEV_EMULATION) += armada_fbdev.o
67
78 obj-$(CONFIG_DRM_ARMADA) := armada.o
drivers/gpu/drm/armada/armada_drm.h+6−4
@@ -16,7 +16,6 @@ struct armada_crtc; · 15 unmodified lines
1616 struct armada_gem_object;
1717 struct clk;
1818 struct drm_display_mode;
19−struct drm_fb_helper;
2019
2120 static inline void
2221 armada_updatel(uint32_t val, uint32_t mask, void __iomem *ptr)
@@ -55,7 +54,6 @@ extern const struct armada_variant armada510_ops; · 32 unmodified lines
5554
5655 struct armada_private {
5756 struct drm_device drm;
58− struct drm_fb_helper *fbdev;
5957 struct armada_crtc *dcrtc[2];
6058 struct drm_mm linear; /* protected by linear_lock */
6159 struct mutex linear_lock;
@@ -75,8 +73,12 @@ struct armada_private { · 13 unmodified lines
7573
7674 #define drm_to_armada_dev(dev) container_of(dev, struct armada_private, drm)
7775
78−int armada_fbdev_init(struct drm_device *);
79−void armada_fbdev_fini(struct drm_device *);
76+#if defined(CONFIG_DRM_FBDEV_EMULATION)
77+void armada_fbdev_setup(struct drm_device *dev);
78+#else
79+static inline void armada_fbdev_setup(struct drm_device *dev)
80+{ }
81+#endif
8082
8183 int armada_overlay_plane_create(struct drm_device *, unsigned long);
8284
drivers/gpu/drm/armada/armada_drv.c+4−10
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #include <linux/clk.h>
77 #include <linux/component.h>
88 #include <linux/module.h>
9+#include <linux/of.h>
910 #include <linux/of_graph.h>
1011 #include <linux/platform_device.h>
1112
@@ -16,7 +17,6 @@ · 4 unmodified lines
1617 #include <drm/drm_managed.h>
1718 #include <drm/drm_prime.h>
1819 #include <drm/drm_probe_helper.h>
19−#include <drm/drm_fb_helper.h>
2020 #include <drm/drm_of.h>
2121 #include <drm/drm_vblank.h>
2222
@@ -37,7 +37,6 @@ static const struct drm_ioctl_desc armada_ioctls[] = { · 14 unmodified lines
3737 DEFINE_DRM_GEM_FOPS(armada_drm_fops);
3838
3939 static const struct drm_driver armada_drm_driver = {
40− .lastclose = drm_fb_helper_lastclose,
4140 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
4241 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
4342 .gem_prime_import = armada_gem_prime_import,
@@ -55,7 +54,6 @@ static const struct drm_driver armada_drm_driver = { · 11 unmodified lines
5554
5655 static const struct drm_mode_config_funcs armada_drm_mode_config_funcs = {
5756 .fb_create = armada_fb_create,
58− .output_poll_changed = drm_fb_helper_output_poll_changed,
5957 .atomic_check = drm_atomic_helper_check,
6058 .atomic_commit = drm_atomic_helper_commit,
6159 };
@@ -95,7 +93,7 @@ static int armada_drm_bind(struct device *dev) · 33 unmodified lines
9593 }
9694
9795 /* Remove early framebuffers */
98− ret = drm_aperture_remove_framebuffers(false, &armada_drm_driver);
96+ ret = drm_aperture_remove_framebuffers(&armada_drm_driver);
9997 if (ret) {
10098 dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n",
10199 __func__, ret);
@@ -131,10 +129,6 @@ static int armada_drm_bind(struct device *dev) · 29 unmodified lines
131129
132130 drm_mode_config_reset(&priv->drm);
133131
134− ret = armada_fbdev_init(&priv->drm);
135− if (ret)
136− goto err_comp;
137−
138132 drm_kms_helper_poll_init(&priv->drm);
139133
140134 ret = drm_dev_register(&priv->drm, 0);
@@ -145,11 +139,12 @@ static int armada_drm_bind(struct device *dev) · 4 unmodified lines
145139 armada_drm_debugfs_init(priv->drm.primary);
146140 #endif
147141
142+ armada_fbdev_setup(&priv->drm);
143+
148144 return 0;
149145
150146 err_poll:
151147 drm_kms_helper_poll_fini(&priv->drm);
152− armada_fbdev_fini(&priv->drm);
153148 err_comp:
154149 component_unbind_all(dev, &priv->drm);
155150 err_kms:
@@ -164,7 +159,6 @@ static void armada_drm_unbind(struct device *dev) · 8 unmodified lines
164159 struct armada_private *priv = drm_to_armada_dev(drm);
165160
166161 drm_kms_helper_poll_fini(&priv->drm);
167− armada_fbdev_fini(&priv->drm);
168162
169163 drm_dev_unregister(&priv->drm);
170164
drivers/gpu/drm/armada/armada_fb.c+0−1
@@ -4,7 +4,6 @@ · 3 unmodified lines
44 */
55
66 #include <drm/drm_modeset_helper.h>
7−#include <drm/drm_fb_helper.h>
87 #include <drm/drm_fourcc.h>
98 #include <drm/drm_gem_framebuffer_helper.h>
109
drivers/gpu/drm/armada/armada_fbdev.c+87−32
@@ -8,6 +8,8 @@ · 7 unmodified lines
88 #include <linux/kernel.h>
99 #include <linux/module.h>
1010
11+#include <drm/drm_crtc_helper.h>
12+#include <drm/drm_drv.h>
1113 #include <drm/drm_fb_helper.h>
1214 #include <drm/drm_fourcc.h>
1315
@@ -16,6 +18,19 @@ · 2 unmodified lines
1618 #include "armada_fb.h"
1719 #include "armada_gem.h"
1820
21+static void armada_fbdev_fb_destroy(struct fb_info *info)
22+{
23+ struct drm_fb_helper *fbh = info->par;
24+
25+ drm_fb_helper_fini(fbh);
26+
27+ fbh->fb->funcs->destroy(fbh->fb);
28+
29+ drm_client_release(&fbh->client);
30+ drm_fb_helper_unprepare(fbh);
31+ kfree(fbh);
32+}
33+
1934 static const struct fb_ops armada_fb_ops = {
2035 .owner = THIS_MODULE,
2136 DRM_FB_HELPER_DEFAULT_OPS,
@@ -24,6 +39,7 @@ static const struct fb_ops armada_fb_ops = { · 2 unmodified lines
2439 .fb_fillrect = drm_fb_helper_cfb_fillrect,
2540 .fb_copyarea = drm_fb_helper_cfb_copyarea,
2641 .fb_imageblit = drm_fb_helper_cfb_imageblit,
42+ .fb_destroy = armada_fbdev_fb_destroy,
2743 };
2844
2945 static int armada_fbdev_create(struct drm_fb_helper *fbh,
@@ -117,56 +133,95 @@ static const struct drm_fb_helper_funcs armada_fb_helper_funcs = { · 87 unmodified lines
117133 .fb_probe = armada_fb_probe,
118134 };
119135
120−int armada_fbdev_init(struct drm_device *dev)
136+/*
137+ * Fbdev client and struct drm_client_funcs
138+ */
139+
140+static void armada_fbdev_client_unregister(struct drm_client_dev *client)
121141 {
122− struct armada_private *priv = drm_to_armada_dev(dev);
123− struct drm_fb_helper *fbh;
124− int ret;
142+ struct drm_fb_helper *fbh = drm_fb_helper_from_client(client);
125143
126− fbh = devm_kzalloc(dev->dev, sizeof(*fbh), GFP_KERNEL);
127− if (!fbh)
128− return -ENOMEM;
144+ if (fbh->info) {
145+ drm_fb_helper_unregister_info(fbh);
146+ } else {
147+ drm_client_release(&fbh->client);
148+ drm_fb_helper_unprepare(fbh);
149+ kfree(fbh);
150+ }
151+}
129152
130− priv->fbdev = fbh;
153+static int armada_fbdev_client_restore(struct drm_client_dev *client)
154+{
155+ drm_fb_helper_lastclose(client->dev);
131156
132− drm_fb_helper_prepare(dev, fbh, 32, &armada_fb_helper_funcs);
157+ return 0;
158+}
159+
160+static int armada_fbdev_client_hotplug(struct drm_client_dev *client)
161+{
162+ struct drm_fb_helper *fbh = drm_fb_helper_from_client(client);
163+ struct drm_device *dev = client->dev;
164+ int ret;
165+
166+ if (dev->fb_helper)
167+ return drm_fb_helper_hotplug_event(dev->fb_helper);
133168
134169 ret = drm_fb_helper_init(dev, fbh);
135− if (ret) {
136− DRM_ERROR("failed to initialize drm fb helper\n");
137− goto err_fb_helper;
138− }
170+ if (ret)
171+ goto err_drm_err;
172+
173+ if (!drm_drv_uses_atomic_modeset(dev))
174+ drm_helper_disable_unused_functions(dev);
139175
140176 ret = drm_fb_helper_initial_config(fbh);
141− if (ret) {
142− DRM_ERROR("failed to set initial config\n");
143− goto err_fb_setup;
144− }
177+ if (ret)
178+ goto err_drm_fb_helper_fini;
145179
146180 return 0;
147− err_fb_setup:
181+
182+err_drm_fb_helper_fini:
148183 drm_fb_helper_fini(fbh);
149− err_fb_helper:
150− drm_fb_helper_unprepare(fbh);
151− priv->fbdev = NULL;
184+err_drm_err:
185+ drm_err(dev, "armada: Failed to setup fbdev emulation (ret=%d)\n", ret);
152186 return ret;
153187 }
154188
155−void armada_fbdev_fini(struct drm_device *dev)
189+static const struct drm_client_funcs armada_fbdev_client_funcs = {
190+ .owner = THIS_MODULE,
191+ .unregister = armada_fbdev_client_unregister,
192+ .restore = armada_fbdev_client_restore,
193+ .hotplug = armada_fbdev_client_hotplug,
194+};
195+
196+void armada_fbdev_setup(struct drm_device *dev)
156197 {
157− struct armada_private *priv = drm_to_armada_dev(dev);
158− struct drm_fb_helper *fbh = priv->fbdev;
198+ struct drm_fb_helper *fbh;
199+ int ret;
159200
160− if (fbh) {
161− drm_fb_helper_unregister_info(fbh);
201+ drm_WARN(dev, !dev->registered, "Device has not been registered.\n");
202+ drm_WARN(dev, dev->fb_helper, "fb_helper is already set!\n");
203+
204+ fbh = kzalloc(sizeof(*fbh), GFP_KERNEL);
205+ if (!fbh)
206+ return;
207+ drm_fb_helper_prepare(dev, fbh, 32, &armada_fb_helper_funcs);
162208
163− drm_fb_helper_fini(fbh);
209+ ret = drm_client_init(dev, &fbh->client, "fbdev", &armada_fbdev_client_funcs);
210+ if (ret) {
211+ drm_err(dev, "Failed to register client: %d\n", ret);
212+ goto err_drm_client_init;
213+ }
164214
165− if (fbh->fb)
166− fbh->fb->funcs->destroy(fbh->fb);
215+ ret = armada_fbdev_client_hotplug(&fbh->client);
216+ if (ret)
217+ drm_dbg_kms(dev, "client hotplug ret=%d\n", ret);
167218
168− drm_fb_helper_unprepare(fbh);
219+ drm_client_register(&fbh->client);
169220
170− priv->fbdev = NULL;
171− }
221+ return;
222+
223+err_drm_client_init:
224+ drm_fb_helper_unprepare(fbh);
225+ kfree(fbh);
226+ return;
172227 }
drivers/gpu/drm/ast/ast_main.c+5−4
@@ -425,11 +425,12 @@ struct ast_device *ast_device_create(const struct drm_driver *drv, · 424 unmodified lines
425425 return ERR_PTR(-EIO);
426426
427427 /*
428− * If we don't have IO space at all, use MMIO now and
429− * assume the chip has MMIO enabled by default (rev 0x20
430− * and higher).
428+ * After AST2500, MMIO is enabled by default, and it should be adopted
429+ * to be compatible with Arm.
431430 */
432− if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
431+ if (pdev->revision >= 0x40) {
432+ ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
433+ } else if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
433434 drm_info(dev, "platform has no IO space, trying MMIO\n");
434435 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
435436 }
drivers/gpu/drm/bridge/analogix/anx7625.c+88−41
@@ -17,7 +17,6 @@ · 16 unmodified lines
1717 #include <linux/types.h>
1818 #include <linux/workqueue.h>
1919
20−#include <linux/of_gpio.h>
2120 #include <linux/of_graph.h>
2221 #include <linux/of_platform.h>
2322
@@ -1687,6 +1686,14 @@ static int anx7625_parse_dt(struct device *dev, · 1663 unmodified lines
16871686 if (of_property_read_bool(np, "analogix,audio-enable"))
16881687 pdata->audio_en = 1;
16891688
1689+ return 0;
1690+}
1691+
1692+static int anx7625_parse_dt_panel(struct device *dev,
1693+ struct anx7625_platform_data *pdata)
1694+{
1695+ struct device_node *np = dev->of_node;
1696+
16901697 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
16911698 if (IS_ERR(pdata->panel_bridge)) {
16921699 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
@@ -2032,7 +2039,7 @@ static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) · 339 unmodified lines
20322039 return 0;
20332040 }
20342041
2035−static int anx7625_attach_dsi(struct anx7625_data *ctx)
2042+static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
20362043 {
20372044 struct mipi_dsi_device *dsi;
20382045 struct device *dev = &ctx->client->dev;
@@ -2042,9 +2049,6 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) · 3 unmodified lines
20422049 .channel = 0,
20432050 .node = NULL,
20442051 };
2045− int ret;
2046−
2047− DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
20482052
20492053 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
20502054 if (!host) {
@@ -2065,14 +2069,24 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) · 14 unmodified lines
20652069 MIPI_DSI_MODE_VIDEO_HSE |
20662070 MIPI_DSI_HS_PKT_END_ALIGNED;
20672071
2068− ret = devm_mipi_dsi_attach(dev, dsi);
2072+ ctx->dsi = dsi;
2073+
2074+ return 0;
2075+}
2076+
2077+static int anx7625_attach_dsi(struct anx7625_data *ctx)
2078+{
2079+ struct device *dev = &ctx->client->dev;
2080+ int ret;
2081+
2082+ DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2083+
2084+ ret = devm_mipi_dsi_attach(dev, ctx->dsi);
20692085 if (ret) {
20702086 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
20712087 return ret;
20722088 }
20732089
2074− ctx->dsi = dsi;
2075−
20762090 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
20772091
20782092 return 0;
@@ -2560,6 +2574,40 @@ static void anx7625_runtime_disable(void *data) · 481 unmodified lines
25602574 pm_runtime_disable(data);
25612575 }
25622576
2577+static int anx7625_link_bridge(struct drm_dp_aux *aux)
2578+{
2579+ struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux);
2580+ struct device *dev = aux->dev;
2581+ int ret;
2582+
2583+ ret = anx7625_parse_dt_panel(dev, &platform->pdata);
2584+ if (ret) {
2585+ DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret);
2586+ return ret;
2587+ }
2588+
2589+ platform->bridge.funcs = &anx7625_bridge_funcs;
2590+ platform->bridge.of_node = dev->of_node;
2591+ if (!anx7625_of_panel_on_aux_bus(dev))
2592+ platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2593+ if (!platform->pdata.panel_bridge)
2594+ platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2595+ DRM_BRIDGE_OP_DETECT;
2596+ platform->bridge.type = platform->pdata.panel_bridge ?
2597+ DRM_MODE_CONNECTOR_eDP :
2598+ DRM_MODE_CONNECTOR_DisplayPort;
2599+
2600+ drm_bridge_add(&platform->bridge);
2601+
2602+ if (!platform->pdata.is_dpi) {
2603+ ret = anx7625_attach_dsi(platform);
2604+ if (ret)
2605+ drm_bridge_remove(&platform->bridge);
2606+ }
2607+
2608+ return ret;
2609+}
2610+
25632611 static int anx7625_i2c_probe(struct i2c_client *client)
25642612 {
25652613 struct anx7625_data *platform;
@@ -2634,6 +2682,24 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 68 unmodified lines
26342682 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
26352683 drm_dp_aux_init(&platform->aux);
26362684
2685+ ret = anx7625_parse_dt(dev, pdata);
2686+ if (ret) {
2687+ if (ret != -EPROBE_DEFER)
2688+ DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2689+ goto free_wq;
2690+ }
2691+
2692+ if (!platform->pdata.is_dpi) {
2693+ ret = anx7625_setup_dsi_device(platform);
2694+ if (ret < 0)
2695+ goto free_wq;
2696+ }
2697+
2698+ /*
2699+ * Registering the i2c devices will retrigger deferred probe, so it
2700+ * needs to be done after calls that might return EPROBE_DEFER,
2701+ * otherwise we can get an infinite loop.
2702+ */
26372703 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
26382704 ret = -ENOMEM;
26392705 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
@@ -2648,13 +2714,21 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 8 unmodified lines
26482714 if (ret)
26492715 goto free_wq;
26502716
2651− devm_of_dp_aux_populate_ep_devices(&platform->aux);
2652−
2653− ret = anx7625_parse_dt(dev, pdata);
2717+ /*
2718+ * Populating the aux bus will retrigger deferred probe, so it needs to
2719+ * be done after calls that might return EPROBE_DEFER, otherwise we can
2720+ * get an infinite loop.
2721+ */
2722+ ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge);
26542723 if (ret) {
2655− if (ret != -EPROBE_DEFER)
2656− DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2657− goto free_wq;
2724+ if (ret != -ENODEV) {
2725+ DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret);
2726+ goto free_wq;
2727+ }
2728+
2729+ ret = anx7625_link_bridge(&platform->aux);
2730+ if (ret)
2731+ goto free_wq;
26582732 }
26592733
26602734 if (!platform->pdata.low_power_mode) {
@@ -2667,27 +2741,6 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 6 unmodified lines
26672741 if (platform->pdata.intp_irq)
26682742 queue_work(platform->workqueue, &platform->work);
26692743
2670− platform->bridge.funcs = &anx7625_bridge_funcs;
2671− platform->bridge.of_node = client->dev.of_node;
2672− if (!anx7625_of_panel_on_aux_bus(&client->dev))
2673− platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2674− if (!platform->pdata.panel_bridge)
2675− platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2676− DRM_BRIDGE_OP_DETECT;
2677− platform->bridge.type = platform->pdata.panel_bridge ?
2678− DRM_MODE_CONNECTOR_eDP :
2679− DRM_MODE_CONNECTOR_DisplayPort;
2680−
2681− drm_bridge_add(&platform->bridge);
2682−
2683− if (!platform->pdata.is_dpi) {
2684− ret = anx7625_attach_dsi(platform);
2685− if (ret) {
2686− DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret);
2687− goto unregister_bridge;
2688− }
2689− }
2690−
26912744 if (platform->pdata.audio_en)
26922745 anx7625_register_audio(dev, platform);
26932746
@@ -2695,12 +2748,6 @@ static int anx7625_i2c_probe(struct i2c_client *client) · 1 unmodified line
26952748
26962749 return 0;
26972750
2698−unregister_bridge:
2699− drm_bridge_remove(&platform->bridge);
2700−
2701− if (!platform->pdata.low_power_mode)
2702− pm_runtime_put_sync_suspend(&client->dev);
2703−
27042751 free_wq:
27052752 if (platform->workqueue)
27062753 destroy_workqueue(platform->workqueue);
drivers/gpu/drm/bridge/fsl-ldb.c+13−1
@@ -56,6 +56,7 @@ · 55 unmodified lines
5656 #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
5757
5858 enum fsl_ldb_devtype {
59+ IMX6SX_LDB,
5960 IMX8MP_LDB,
6061 IMX93_LDB,
6162 };
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata { · 2 unmodified lines
6465 u32 ldb_ctrl;
6566 u32 lvds_ctrl;
6667 bool lvds_en_bit;
68+ bool single_ctrl_reg;
6769 };
6870
6971 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
72+ [IMX6SX_LDB] = {
73+ .ldb_ctrl = 0x18,
74+ .single_ctrl_reg = true,
75+ },
7076 [IMX8MP_LDB] = {
7177 .ldb_ctrl = 0x5c,
7278 .lvds_ctrl = 0x128,
@@ -201,6 +207,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, · 128 unmodified lines
201207
202208 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
203209
210+ if (fsl_ldb->devdata->single_ctrl_reg)
211+ return;
212+
204213 /* Program LVDS_CTRL */
205214 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
206215 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -226,7 +235,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, · 19 unmodified lines
226235 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
227236 LVDS_CTRL_LVDS_EN);
228237 else
229− regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
238+ if (!fsl_ldb->devdata->single_ctrl_reg)
239+ regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
230240 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
231241
232242 clk_disable_unprepare(fsl_ldb->clk);
@@ -372,6 +382,8 @@ static void fsl_ldb_remove(struct platform_device *pdev) · 139 unmodified lines
372382 }
373383
374384 static const struct of_device_id fsl_ldb_match[] = {
385+ { .compatible = "fsl,imx6sx-ldb",
386+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
375387 { .compatible = "fsl,imx8mp-ldb",
376388 .data = &fsl_ldb_devdata[IMX8MP_LDB], },
377389 { .compatible = "fsl,imx93-ldb",
drivers/gpu/drm/bridge/ite-it6505.c+2−1
@@ -3207,7 +3207,7 @@ static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf, · 3206 unmodified lines
32073207 size_t len, loff_t *ppos)
32083208 {
32093209 struct it6505 *it6505 = file->private_data;
3210− struct drm_display_mode *vid = &it6505->video_info;
3210+ struct drm_display_mode *vid;
32113211 u8 read_buf[READ_BUFFER_SIZE];
32123212 u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
32133213 ssize_t ret, count;
@@ -3216,6 +3216,7 @@ static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf, · 2 unmodified lines
32163216 return -ENODEV;
32173217
32183218 it6505_calc_video_info(it6505);
3219+ vid = &it6505->video_info;
32193220 str += scnprintf(str, end - str, "---video timing---\n");
32203221 str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
32213222 vid->clock / 1000, vid->clock % 1000);
drivers/gpu/drm/bridge/lontium-lt9211.c+3−1
@@ -709,7 +709,9 @@ static int lt9211_host_attach(struct lt9211 *ctx) · 708 unmodified lines
709709 dsi->lanes = dsi_lanes;
710710 dsi->format = MIPI_DSI_FMT_RGB888;
711711 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
712− MIPI_DSI_MODE_VIDEO_HSE;
712+ MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA |
713+ MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
714+ MIPI_DSI_MODE_NO_EOT_PACKET;
713715
714716 ret = devm_mipi_dsi_attach(dev, dsi);
715717 if (ret < 0) {
drivers/gpu/drm/bridge/lontium-lt9611.c+3−1
@@ -774,7 +774,9 @@ static struct mipi_dsi_device *lt9611_attach_dsi(struct lt9611 *lt9611, · 773 unmodified lines
774774 dsi->lanes = 4;
775775 dsi->format = MIPI_DSI_FMT_RGB888;
776776 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
777− MIPI_DSI_MODE_VIDEO_HSE;
777+ MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO_NO_HSA |
778+ MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
779+ MIPI_DSI_MODE_NO_EOT_PACKET;
778780
779781 ret = devm_mipi_dsi_attach(dev, dsi);
780782 if (ret < 0) {
drivers/gpu/drm/bridge/samsung-dsim.c+26−2
@@ -183,6 +183,8 @@ · 182 unmodified lines
183183 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
184184
185185 /* DSIM_PLLCTRL */
186+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
187+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
186188 #define DSIM_FREQ_BAND(x) ((x) << 24)
187189 #define DSIM_PLL_EN BIT(23)
188190 #define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, · 433 unmodified lines
622624 reg |= DSIM_FREQ_BAND(band);
623625 }
624626
627+ if (dsi->swap_dn_dp_clk)
628+ reg |= DSIM_PLL_DPDNSWAP_CLK;
629+ if (dsi->swap_dn_dp_data)
630+ reg |= DSIM_PLL_DPDNSWAP_DAT;
631+
625632 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
626633
627634 timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) · 1068 unmodified lines
16961703 {
16971704 struct device *dev = dsi->dev;
16981705 struct device_node *node = dev->of_node;
1699− int ret;
1706+ u32 lane_polarities[5] = { 0 };
1707+ struct device_node *endpoint;
1708+ int i, nr_lanes, ret;
17001709
17011710 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
17021711 &dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) · 10 unmodified lines
17131722 if (ret < 0)
17141723 return ret;
17151724
1725+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1726+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1727+ if (nr_lanes > 0 && nr_lanes <= 4) {
1728+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
1729+ of_property_read_u32_array(endpoint, "lane-polarities",
1730+ lane_polarities, nr_lanes + 1);
1731+ for (i = 1; i <= nr_lanes; i++) {
1732+ if (lane_polarities[1] != lane_polarities[i])
1733+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1734+ }
1735+ if (lane_polarities[0])
1736+ dsi->swap_dn_dp_clk = true;
1737+ if (lane_polarities[1])
1738+ dsi->swap_dn_dp_data = true;
1739+ }
1740+
17161741 return 0;
17171742 }
17181743
@@ -1954,7 +1979,6 @@ static struct platform_driver samsung_dsim_driver = { · 235 unmodified lines
19541979 .remove = samsung_dsim_remove,
19551980 .driver = {
19561981 .name = "samsung-dsim",
1957− .owner = THIS_MODULE,
19581982 .pm = &samsung_dsim_pm_ops,
19591983 .of_match_table = samsung_dsim_of_match,
19601984 },
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c+1−1
@@ -533,7 +533,7 @@ static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) · 532 unmodified lines
533533 adap->owner = THIS_MODULE;
534534 adap->dev.parent = hdmi->dev;
535535 adap->algo = &dw_hdmi_algorithm;
536− strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
536+ strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
537537 i2c_set_adapdata(adap, hdmi);
538538
539539 ret = i2c_add_adapter(adap);
drivers/gpu/drm/bridge/tc358767.c+2−2
@@ -1890,7 +1890,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc) · 1889 unmodified lines
18901890 if (dsi_lanes < 0)
18911891 return dsi_lanes;
18921892
1893− dsi = mipi_dsi_device_register_full(host, &info);
1893+ dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
18941894 if (IS_ERR(dsi))
18951895 return dev_err_probe(dev, PTR_ERR(dsi),
18961896 "failed to create dsi device\n");
@@ -1901,7 +1901,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc) · 4 unmodified lines
19011901 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
19021902 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
19031903
1904− ret = mipi_dsi_attach(dsi);
1904+ ret = devm_mipi_dsi_attach(dev, dsi);
19051905 if (ret < 0) {
19061906 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
19071907 return ret;
drivers/gpu/drm/bridge/tc358768.c+74−23
@@ -9,6 +9,8 @@ · 8 unmodified lines
99 #include <linux/gpio/consumer.h>
1010 #include <linux/i2c.h>
1111 #include <linux/kernel.h>
12+#include <linux/media-bus-format.h>
13+#include <linux/minmax.h>
1214 #include <linux/module.h>
1315 #include <linux/regmap.h>
1416 #include <linux/regulator/consumer.h>
@@ -146,6 +148,7 @@ struct tc358768_priv { · 131 unmodified lines
146148
147149 u32 pd_lines; /* number of Parallel Port Input Data Lines */
148150 u32 dsi_lanes; /* number of DSI Lanes */
151+ u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
149152
150153 /* Parameters for PLL programming */
151154 u32 fbd; /* PLL feedback divider */
@@ -284,12 +287,12 @@ static void tc358768_hw_disable(struct tc358768_priv *priv) · 132 unmodified lines
284287
285288 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
286289 {
287− return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
290+ return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
288291 }
289292
290293 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
291294 {
292− return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
295+ return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
293296 }
294297
295298 static int tc358768_calc_pll(struct tc358768_priv *priv,
@@ -334,13 +337,17 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, · 38 unmodified lines
334337 u32 fbd;
335338
336339 for (fbd = 0; fbd < 512; ++fbd) {
337− u32 pll, diff;
340+ u32 pll, diff, pll_in;
338341
339342 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
340343
341344 if (pll >= max_pll || pll < min_pll)
342345 continue;
343346
347+ pll_in = (u32)div_u64((u64)refclk, prd + 1);
348+ if (pll_in < 4000000)
349+ continue;
350+
344351 diff = max(pll, target_pll) - min(pll, target_pll);
345352
346353 if (diff < best_diff) {
@@ -422,6 +429,7 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, · 75 unmodified lines
422429 priv->output.panel = panel;
423430
424431 priv->dsi_lanes = dev->lanes;
432+ priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
425433
426434 /* get input ep (port0/endpoint0) */
427435 ret = -EINVAL;
@@ -433,7 +441,7 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, · 5 unmodified lines
433441 }
434442
435443 if (ret)
436− priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
444+ priv->pd_lines = priv->dsi_bpp;
437445
438446 drm_bridge_add(&priv->bridge);
439447
@@ -632,8 +640,9 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 192 unmodified lines
632640 struct mipi_dsi_device *dsi_dev = priv->output.dev;
633641 unsigned long mode_flags = dsi_dev->mode_flags;
634642 u32 val, val2, lptxcnt, hact, data_type;
643+ s32 raw_val;
635644 const struct drm_display_mode *mode;
636− u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
645+ u32 dsibclk_nsk, dsiclk_nsk, ui_nsk;
637646 u32 dsiclk, dsibclk, video_start;
638647 const u32 internal_delay = 40;
639648 int ret, i;
@@ -717,11 +726,9 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 77 unmodified lines
717726 dsibclk);
718727 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
719728 ui_nsk = dsiclk_nsk / 2;
720− phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
721729 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
722730 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
723731 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
724− dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
725732
726733 /* LP11 > 100us for D-PHY Rx Init */
727734 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
@@ -736,25 +743,26 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 8 unmodified lines
736743
737744 /* 38ns < TCLK_PREPARE < 95ns */
738745 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
739− /* TCLK_PREPARE > 300ns */
740− val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
741− dsibclk_nsk);
742− val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
746+ /* TCLK_PREPARE + TCLK_ZERO > 300ns */
747+ val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
748+ dsibclk_nsk) - 2;
749+ val |= val2 << 8;
743750 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
744751 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
745752
746− /* TCLK_TRAIL > 60ns + 3*UI */
747− val = 60 + tc358768_to_ns(3 * ui_nsk);
748− val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
753+ /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
754+ raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
755+ val = clamp(raw_val, 0, 127);
749756 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
750757 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
751758
752759 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
753760 val = 50 + tc358768_to_ns(4 * ui_nsk);
754761 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
755− /* THS_ZERO > 145ns + 10*UI */
756− val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
757− val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
762+ /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
763+ raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
764+ val2 = clamp(raw_val, 0, 127);
765+ val |= val2 << 8;
758766 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
759767 tc358768_write(priv, TC358768_THS_HEADERCNT, val);
760768
@@ -770,9 +778,10 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 9 unmodified lines
770778 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
771779 tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
772780
773− /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
774− val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
775− dsibclk_nsk) - 5;
781+ /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
782+ raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
783+ dsibclk_nsk) - 4;
784+ val = clamp(raw_val, 0, 15);
776785 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
777786 tc358768_write(priv, TC358768_THS_TRAILCNT, val);
778787
@@ -786,7 +795,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 7 unmodified lines
786795
787796 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
788797 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
789− val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
798+ val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
790799 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
791800 dsibclk_nsk) - 2;
792801 val = val << 16 | val2;
@@ -866,8 +875,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) · 73 unmodified lines
866875 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
867876 val |= (dsi_dev->lanes - 1) << 1;
868877
869− if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
870− val |= TC358768_DSI_CONTROL_TXMD;
878+ val |= TC358768_DSI_CONTROL_TXMD;
871879
872880 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
873881 val |= TC358768_DSI_CONTROL_HSCKMD;
@@ -913,6 +921,44 @@ static void tc358768_bridge_enable(struct drm_bridge *bridge) · 39 unmodified lines
913921 }
914922 }
915923
924+#define MAX_INPUT_SEL_FORMATS 1
925+
926+static u32 *
927+tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
928+ struct drm_bridge_state *bridge_state,
929+ struct drm_crtc_state *crtc_state,
930+ struct drm_connector_state *conn_state,
931+ u32 output_fmt,
932+ unsigned int *num_input_fmts)
933+{
934+ struct tc358768_priv *priv = bridge_to_tc358768(bridge);
935+ u32 *input_fmts;
936+
937+ *num_input_fmts = 0;
938+
939+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
940+ GFP_KERNEL);
941+ if (!input_fmts)
942+ return NULL;
943+
944+ switch (priv->pd_lines) {
945+ case 16:
946+ input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
947+ break;
948+ case 18:
949+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
950+ break;
951+ default:
952+ case 24:
953+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
954+ break;
955+ }
956+
957+ *num_input_fmts = MAX_INPUT_SEL_FORMATS;
958+
959+ return input_fmts;
960+}
961+
916962 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
917963 .attach = tc358768_bridge_attach,
918964 .mode_valid = tc358768_bridge_mode_valid,
@@ -920,6 +966,11 @@ static const struct drm_bridge_funcs tc358768_bridge_funcs = { · 1 unmodified line
920966 .enable = tc358768_bridge_enable,
921967 .disable = tc358768_bridge_disable,
922968 .post_disable = tc358768_bridge_post_disable,
969+
970+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
971+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
972+ .atomic_reset = drm_atomic_helper_bridge_reset,
973+ .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
923974 };
924975
925976 static const struct drm_bridge_timings default_tc358768_timings = {
drivers/gpu/drm/bridge/ti-sn65dsi83.c+1−0
@@ -478,6 +478,7 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, · 477 unmodified lines
478478 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
479479 /* On failure, disable PLL again and exit. */
480480 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
481+ regulator_disable(ctx->vcc);
481482 return;
482483 }
483484
drivers/gpu/drm/bridge/ti-sn65dsi86.c+19−0
@@ -618,6 +618,24 @@ exit: · 617 unmodified lines
618618 return len;
619619 }
620620
621+static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
622+{
623+ /*
624+ * The HPD in this chip is a bit useless (See comment in
625+ * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
626+ * for HPD, we just assume it's asserted after the wait_us delay.
627+ *
628+ * In case we are asked to wait forever (wait_us=0) take conservative
629+ * 500ms delay.
630+ */
631+ if (wait_us == 0)
632+ wait_us = 500000;
633+
634+ usleep_range(wait_us, wait_us + 1000);
635+
636+ return 0;
637+}
638+
621639 static int ti_sn_aux_probe(struct auxiliary_device *adev,
622640 const struct auxiliary_device_id *id)
623641 {
@@ -627,6 +645,7 @@ static int ti_sn_aux_probe(struct auxiliary_device *adev, · 3 unmodified lines
627645 pdata->aux.name = "ti-sn65dsi86-aux";
628646 pdata->aux.dev = &adev->dev;
629647 pdata->aux.transfer = ti_sn_aux_transfer;
648+ pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
630649 drm_dp_aux_init(&pdata->aux);
631650
632651 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
drivers/gpu/drm/drm_aperture.c+3−8
@@ -32,17 +32,13 @@ · 31 unmodified lines
3232 *
3333 * static int remove_conflicting_framebuffers(struct pci_dev *pdev)
3434 * {
35− * bool primary = false;
3635 * resource_size_t base, size;
3736 * int ret;
3837 *
3938 * base = pci_resource_start(pdev, 0);
4039 * size = pci_resource_len(pdev, 0);
41− * #ifdef CONFIG_X86
42− * primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
43− * #endif
4440 *
45− * return drm_aperture_remove_conflicting_framebuffers(base, size, primary,
41+ * return drm_aperture_remove_conflicting_framebuffers(base, size,
4642 * &example_driver);
4743 * }
4844 *
@@ -161,7 +157,6 @@ EXPORT_SYMBOL(devm_aperture_acquire_from_firmware); · 112 unmodified lines
161157 * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range
162158 * @base: the aperture's base address in physical memory
163159 * @size: aperture size in bytes
164− * @primary: also kick vga16fb if present
165160 * @req_driver: requesting DRM driver
166161 *
167162 * This function removes graphics device drivers which use the memory range described by
@@ -171,9 +166,9 @@ EXPORT_SYMBOL(devm_aperture_acquire_from_firmware); · 3 unmodified lines
171166 * 0 on success, or a negative errno code otherwise
172167 */
173168 int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
174− bool primary, const struct drm_driver *req_driver)
169+ const struct drm_driver *req_driver)
175170 {
176− return aperture_remove_conflicting_devices(base, size, primary, req_driver->name);
171+ return aperture_remove_conflicting_devices(base, size, req_driver->name);
177172 }
178173 EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers);
179174
drivers/gpu/drm/drm_atomic_helper.c+11−2
@@ -1209,7 +1209,16 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) · 1208 unmodified lines
12091209 continue;
12101210
12111211 ret = drm_crtc_vblank_get(crtc);
1212− WARN_ONCE(ret != -EINVAL, "driver forgot to call drm_crtc_vblank_off()\n");
1212+ /*
1213+ * Self-refresh is not a true "disable"; ensure vblank remains
1214+ * enabled.
1215+ */
1216+ if (new_crtc_state->self_refresh_active)
1217+ WARN_ONCE(ret != 0,
1218+ "driver disabled vblank in self-refresh\n");
1219+ else
1220+ WARN_ONCE(ret != -EINVAL,
1221+ "driver forgot to call drm_crtc_vblank_off()\n");
12131222 if (ret == 0)
12141223 drm_crtc_vblank_put(crtc);
12151224 }
@@ -3145,7 +3154,7 @@ fail: · 1929 unmodified lines
31453154 EXPORT_SYMBOL(drm_atomic_helper_update_plane);
31463155
31473156 /**
3148− * drm_atomic_helper_disable_plane - Helper for primary plane disable using * atomic
3157+ * drm_atomic_helper_disable_plane - Helper for primary plane disable using atomic
31493158 * @plane: plane to disable
31503159 * @ctx: lock acquire context
31513160 *
drivers/gpu/drm/drm_drv.c+3−1
@@ -969,7 +969,9 @@ EXPORT_SYMBOL(drm_dev_register); · 968 unmodified lines
969969 *
970970 * Unregister the DRM device from the system. This does the reverse of
971971 * drm_dev_register() but does not deallocate the device. The caller must call
972− * drm_dev_put() to drop their final reference.
972+ * drm_dev_put() to drop their final reference, unless it is managed with devres
973+ * (as devices allocated with devm_drm_dev_alloc() are), in which case there is
974+ * already an unwind action registered.
973975 *
974976 * A special form of unregistering for hotpluggable devices is drm_dev_unplug(),
975977 * which can be called while there are still open users of @dev.
drivers/gpu/drm/drm_fb_helper.c+16−174
@@ -641,19 +641,27 @@ static void drm_fb_helper_damage(struct drm_fb_helper *helper, u32 x, u32 y, · 640 unmodified lines
641641 static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, size_t len,
642642 struct drm_rect *clip)
643643 {
644+ u32 line_length = info->fix.line_length;
645+ u32 fb_height = info->var.yres;
644646 off_t end = off + len;
645647 u32 x1 = 0;
646− u32 y1 = off / info->fix.line_length;
648+ u32 y1 = off / line_length;
647649 u32 x2 = info->var.xres;
648− u32 y2 = DIV_ROUND_UP(end, info->fix.line_length);
650+ u32 y2 = DIV_ROUND_UP(end, line_length);
651+
652+ /* Don't allow any of them beyond the bottom bound of display area */
653+ if (y1 > fb_height)
654+ y1 = fb_height;
655+ if (y2 > fb_height)
656+ y2 = fb_height;
649657
650658 if ((y2 - y1) == 1) {
651659 /*
652660 * We've only written to a single scanline. Try to reduce
653661 * the number of horizontal pixels that need an update.
654662 */
655− off_t bit_off = (off % info->fix.line_length) * 8;
656− off_t bit_end = (end % info->fix.line_length) * 8;
663+ off_t bit_off = (off % line_length) * 8;
664+ off_t bit_end = (end % line_length) * 8;
657665
658666 x1 = bit_off / info->var.bits_per_pixel;
659667 x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);
@@ -706,95 +714,6 @@ void drm_fb_helper_deferred_io(struct fb_info *info, struct list_head *pagerefli · 46 unmodified lines
706714 }
707715 EXPORT_SYMBOL(drm_fb_helper_deferred_io);
708716
709−typedef ssize_t (*drm_fb_helper_read_screen)(struct fb_info *info, char __user *buf,
710− size_t count, loff_t pos);
711−
712−static ssize_t __drm_fb_helper_read(struct fb_info *info, char __user *buf, size_t count,
713− loff_t *ppos, drm_fb_helper_read_screen read_screen)
714−{
715− loff_t pos = *ppos;
716− size_t total_size;
717− ssize_t ret;
718−
719− if (info->screen_size)
720− total_size = info->screen_size;
721− else
722− total_size = info->fix.smem_len;
723−
724− if (pos >= total_size)
725− return 0;
726− if (count >= total_size)
727− count = total_size;
728− if (total_size - count < pos)
729− count = total_size - pos;
730−
731− if (info->fbops->fb_sync)
732− info->fbops->fb_sync(info);
733−
734− ret = read_screen(info, buf, count, pos);
735− if (ret > 0)
736− *ppos += ret;
737−
738− return ret;
739−}
740−
741−typedef ssize_t (*drm_fb_helper_write_screen)(struct fb_info *info, const char __user *buf,
742− size_t count, loff_t pos);
743−
744−static ssize_t __drm_fb_helper_write(struct fb_info *info, const char __user *buf, size_t count,
745− loff_t *ppos, drm_fb_helper_write_screen write_screen)
746−{
747− loff_t pos = *ppos;
748− size_t total_size;
749− ssize_t ret;
750− int err = 0;
751−
752− if (info->screen_size)
753− total_size = info->screen_size;
754− else
755− total_size = info->fix.smem_len;
756−
757− if (pos > total_size)
758− return -EFBIG;
759− if (count > total_size) {
760− err = -EFBIG;
761− count = total_size;
762− }
763− if (total_size - count < pos) {
764− if (!err)
765− err = -ENOSPC;
766− count = total_size - pos;
767− }
768−
769− if (info->fbops->fb_sync)
770− info->fbops->fb_sync(info);
771−
772− /*
773− * Copy to framebuffer even if we already logged an error. Emulates
774− * the behavior of the original fbdev implementation.
775− */
776− ret = write_screen(info, buf, count, pos);
777− if (ret < 0)
778− return ret; /* return last error, if any */
779− else if (!ret)
780− return err; /* return previous error, if any */
781−
782− *ppos += ret;
783−
784− return ret;
785−}
786−
787−static ssize_t drm_fb_helper_read_screen_buffer(struct fb_info *info, char __user *buf,
788− size_t count, loff_t pos)
789−{
790− const char *src = info->screen_buffer + pos;
791−
792− if (copy_to_user(buf, src, count))
793− return -EFAULT;
794−
795− return count;
796−}
797−
798717 /**
799718 * drm_fb_helper_sys_read - Implements struct &fb_ops.fb_read for system memory
800719 * @info: fb_info struct pointer
@@ -808,21 +727,10 @@ static ssize_t drm_fb_helper_read_screen_buffer(struct fb_info *info, char __use · 7 unmodified lines
808727 ssize_t drm_fb_helper_sys_read(struct fb_info *info, char __user *buf,
809728 size_t count, loff_t *ppos)
810729 {
811− return __drm_fb_helper_read(info, buf, count, ppos, drm_fb_helper_read_screen_buffer);
730+ return fb_sys_read(info, buf, count, ppos);
812731 }
813732 EXPORT_SYMBOL(drm_fb_helper_sys_read);
814733
815−static ssize_t drm_fb_helper_write_screen_buffer(struct fb_info *info, const char __user *buf,
816− size_t count, loff_t pos)
817−{
818− char *dst = info->screen_buffer + pos;
819−
820− if (copy_from_user(dst, buf, count))
821− return -EFAULT;
822−
823− return count;
824−}
825−
826734 /**
827735 * drm_fb_helper_sys_write - Implements struct &fb_ops.fb_write for system memory
828736 * @info: fb_info struct pointer
@@ -841,7 +749,7 @@ ssize_t drm_fb_helper_sys_write(struct fb_info *info, const char __user *buf, · 12 unmodified lines
841749 ssize_t ret;
842750 struct drm_rect damage_area;
843751
844− ret = __drm_fb_helper_write(info, buf, count, ppos, drm_fb_helper_write_screen_buffer);
752+ ret = fb_sys_write(info, buf, count, ppos);
845753 if (ret <= 0)
846754 return ret;
847755
@@ -913,39 +821,6 @@ void drm_fb_helper_sys_imageblit(struct fb_info *info, · 65 unmodified lines
913821 }
914822 EXPORT_SYMBOL(drm_fb_helper_sys_imageblit);
915823
916−static ssize_t fb_read_screen_base(struct fb_info *info, char __user *buf, size_t count,
917− loff_t pos)
918−{
919− const char __iomem *src = info->screen_base + pos;
920− size_t alloc_size = min_t(size_t, count, PAGE_SIZE);
921− ssize_t ret = 0;
922− int err = 0;
923− char *tmp;
924−
925− tmp = kmalloc(alloc_size, GFP_KERNEL);
926− if (!tmp)
927− return -ENOMEM;
928−
929− while (count) {
930− size_t c = min_t(size_t, count, alloc_size);
931−
932− memcpy_fromio(tmp, src, c);
933− if (copy_to_user(buf, tmp, c)) {
934− err = -EFAULT;
935− break;
936− }
937−
938− src += c;
939− buf += c;
940− ret += c;
941− count -= c;
942− }
943−
944− kfree(tmp);
945−
946− return ret ? ret : err;
947−}
948−
949824 /**
950825 * drm_fb_helper_cfb_read - Implements struct &fb_ops.fb_read for I/O memory
951826 * @info: fb_info struct pointer
@@ -959,43 +834,10 @@ static ssize_t fb_read_screen_base(struct fb_info *info, char __user *buf, size_ · 7 unmodified lines
959834 ssize_t drm_fb_helper_cfb_read(struct fb_info *info, char __user *buf,
960835 size_t count, loff_t *ppos)
961836 {
962− return __drm_fb_helper_read(info, buf, count, ppos, fb_read_screen_base);
837+ return fb_io_read(info, buf, count, ppos);
963838 }
964839 EXPORT_SYMBOL(drm_fb_helper_cfb_read);
965840
966−static ssize_t fb_write_screen_base(struct fb_info *info, const char __user *buf, size_t count,
967− loff_t pos)
968−{
969− char __iomem *dst = info->screen_base + pos;
970− size_t alloc_size = min_t(size_t, count, PAGE_SIZE);
971− ssize_t ret = 0;
972− int err = 0;
973− u8 *tmp;
974−
975− tmp = kmalloc(alloc_size, GFP_KERNEL);
976− if (!tmp)
977− return -ENOMEM;
978−
979− while (count) {
980− size_t c = min_t(size_t, count, alloc_size);
981−
982− if (copy_from_user(tmp, buf, c)) {
983− err = -EFAULT;
984− break;
985− }
986− memcpy_toio(dst, tmp, c);
987−
988− dst += c;
989− buf += c;
990− ret += c;
991− count -= c;
992− }
993−
994− kfree(tmp);
995−
996− return ret ? ret : err;
997−}
998−
999841 /**
1000842 * drm_fb_helper_cfb_write - Implements struct &fb_ops.fb_write for I/O memory
1001843 * @info: fb_info struct pointer
@@ -1014,7 +856,7 @@ ssize_t drm_fb_helper_cfb_write(struct fb_info *info, const char __user *buf, · 12 unmodified lines
1014856 ssize_t ret;
1015857 struct drm_rect damage_area;
1016858
1017− ret = __drm_fb_helper_write(info, buf, count, ppos, fb_write_screen_base);
859+ ret = fb_io_write(info, buf, count, ppos);
1018860 if (ret <= 0)
1019861 return ret;
1020862
drivers/gpu/drm/drm_gem_framebuffer_helper.c+9−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <linux/module.h>
1010
1111 #include <drm/drm_damage_helper.h>
12+#include <drm/drm_drv.h>
1213 #include <drm/drm_fourcc.h>
1314 #include <drm/drm_framebuffer.h>
1415 #include <drm/drm_gem.h>
@@ -164,6 +165,14 @@ int drm_gem_fb_init_with_funcs(struct drm_device *dev, · 149 unmodified lines
164165 return -EINVAL;
165166 }
166167
168+ if (drm_drv_uses_atomic_modeset(dev) &&
169+ !drm_any_plane_has_format(dev, mode_cmd->pixel_format,
170+ mode_cmd->modifier[0])) {
171+ drm_dbg(dev, "Unsupported pixel format %p4cc / modifier 0x%llx\n",
172+ &mode_cmd->pixel_format, mode_cmd->modifier[0]);
173+ return -EINVAL;
174+ }
175+
167176 for (i = 0; i < info->num_planes; i++) {
168177 unsigned int width = mode_cmd->width / (i ? info->hsub : 1);
169178 unsigned int height = mode_cmd->height / (i ? info->vsub : 1);
drivers/gpu/drm/drm_gem_vram_helper.c+3−3
@@ -45,7 +45,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 44 unmodified lines
4545 * the frame's scanout buffer or the cursor image. If there's no more space
4646 * left in VRAM, inactive GEM objects can be moved to system memory.
4747 *
48− * To initialize the VRAM helper library call drmm_vram_helper_alloc_mm().
48+ * To initialize the VRAM helper library call drmm_vram_helper_init().
4949 * The function allocates and initializes an instance of &struct drm_vram_mm
5050 * in &struct drm_device.vram_mm . Use &DRM_GEM_VRAM_DRIVER to initialize
5151 * &struct drm_driver and &DRM_VRAM_MM_FILE_OPERATIONS to initialize
@@ -73,7 +73,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 21 unmodified lines
7373 * // setup device, vram base and size
7474 * // ...
7575 *
76− * ret = drmm_vram_helper_alloc_mm(dev, vram_base, vram_size);
76+ * ret = drmm_vram_helper_init(dev, vram_base, vram_size);
7777 * if (ret)
7878 * return ret;
7979 * return 0;
@@ -86,7 +86,7 @@ static const struct drm_gem_object_funcs drm_gem_vram_object_funcs; · 6 unmodified lines
8686 * to userspace.
8787 *
8888 * You don't have to clean up the instance of VRAM MM.
89− * drmm_vram_helper_alloc_mm() is a managed interface that installs a
89+ * drmm_vram_helper_init() is a managed interface that installs a
9090 * clean-up handler to run during the DRM device's release.
9191 *
9292 * For drawing or scanout operations, rsp. buffer objects have to be pinned
drivers/gpu/drm/drm_mipi_dsi.c+1−1
@@ -221,7 +221,7 @@ mipi_dsi_device_register_full(struct mipi_dsi_host *host, · 220 unmodified lines
221221 return dsi;
222222 }
223223
224− dsi->dev.of_node = info->node;
224+ device_set_node(&dsi->dev, of_fwnode_handle(info->node));
225225 dsi->channel = info->channel;
226226 strlcpy(dsi->name, info->type, sizeof(dsi->name));
227227
drivers/gpu/drm/drm_sysfs.c+51−0
@@ -11,12 +11,14 @@ · 10 unmodified lines
1111 */
1212
1313 #include <linux/acpi.h>
14+#include <linux/component.h>
1415 #include <linux/device.h>
1516 #include <linux/err.h>
1617 #include <linux/export.h>
1718 #include <linux/gfp.h>
1819 #include <linux/i2c.h>
1920 #include <linux/kdev_t.h>
21+#include <linux/property.h>
2022 #include <linux/slab.h>
2123
2224 #include <drm/drm_accel.h>
@@ -96,6 +98,34 @@ static char *drm_devnode(const struct device *dev, umode_t *mode) · 73 unmodified lines
9698 return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev));
9799 }
98100
101+static int typec_connector_bind(struct device *dev,
102+ struct device *typec_connector, void *data)
103+{
104+ int ret;
105+
106+ ret = sysfs_create_link(&dev->kobj, &typec_connector->kobj, "typec_connector");
107+ if (ret)
108+ return ret;
109+
110+ ret = sysfs_create_link(&typec_connector->kobj, &dev->kobj, "drm_connector");
111+ if (ret)
112+ sysfs_remove_link(&dev->kobj, "typec_connector");
113+
114+ return ret;
115+}
116+
117+static void typec_connector_unbind(struct device *dev,
118+ struct device *typec_connector, void *data)
119+{
120+ sysfs_remove_link(&typec_connector->kobj, "drm_connector");
121+ sysfs_remove_link(&dev->kobj, "typec_connector");
122+}
123+
124+static const struct component_ops typec_connector_ops = {
125+ .bind = typec_connector_bind,
126+ .unbind = typec_connector_unbind,
127+};
128+
99129 static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810");
100130
101131 /**
@@ -282,16 +312,27 @@ static ssize_t modes_show(struct device *device, · 180 unmodified lines
282312 return written;
283313 }
284314
315+static ssize_t connector_id_show(struct device *device,
316+ struct device_attribute *attr,
317+ char *buf)
318+{
319+ struct drm_connector *connector = to_drm_connector(device);
320+
321+ return sysfs_emit(buf, "%d\n", connector->base.id);
322+}
323+
285324 static DEVICE_ATTR_RW(status);
286325 static DEVICE_ATTR_RO(enabled);
287326 static DEVICE_ATTR_RO(dpms);
288327 static DEVICE_ATTR_RO(modes);
328+static DEVICE_ATTR_RO(connector_id);
289329
290330 static struct attribute *connector_dev_attrs[] = {
291331 &dev_attr_status.attr,
292332 &dev_attr_enabled.attr,
293333 &dev_attr_dpms.attr,
294334 &dev_attr_modes.attr,
335+ &dev_attr_connector_id.attr,
295336 NULL
296337 };
297338
@@ -353,9 +394,16 @@ int drm_sysfs_connector_add(struct drm_connector *connector) · 55 unmodified lines
353394
354395 connector->kdev = kdev;
355396
397+ if (dev_fwnode(kdev)) {
398+ r = component_add(kdev, &typec_connector_ops);
399+ if (r)
400+ drm_err(dev, "failed to add component to create link to typec connector\n");
401+ }
402+
356403 if (connector->ddc)
357404 return sysfs_create_link(&connector->kdev->kobj,
358405 &connector->ddc->dev.kobj, "ddc");
406+
359407 return 0;
360408
361409 err_free:
@@ -371,6 +419,9 @@ void drm_sysfs_connector_remove(struct drm_connector *connector) · 9 unmodified lines
371419 if (connector->ddc)
372420 sysfs_remove_link(&connector->kdev->kobj, "ddc");
373421
422+ if (dev_fwnode(connector->kdev))
423+ component_del(connector->kdev, &typec_connector_ops);
424+
374425 DRM_DEBUG("removing \"%s\" from sysfs\n",
375426 connector->name);
376427
drivers/gpu/drm/gma500/fbdev.c+1−1
@@ -231,7 +231,7 @@ static int psb_fbdev_fb_probe(struct drm_fb_helper *fb_helper, · 230 unmodified lines
231231 info->fix.mmio_start = pci_resource_start(pdev, 0);
232232 info->fix.mmio_len = pci_resource_len(pdev, 0);
233233
234− memset(info->screen_base, 0, info->screen_size);
234+ fb_memset_io(info->screen_base, 0, info->screen_size);
235235
236236 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
237237
drivers/gpu/drm/gma500/psb_drv.c+34−9
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 *
88 **************************************************************************/
99
10+#include <linux/aperture.h>
1011 #include <linux/cpu.h>
1112 #include <linux/module.h>
1213 #include <linux/notifier.h>
@@ -19,7 +20,6 @@ · 6 unmodified lines
1920 #include <acpi/video.h>
2021
2122 #include <drm/drm.h>
22−#include <drm/drm_aperture.h>
2323 #include <drm/drm_drv.h>
2424 #include <drm/drm_file.h>
2525 #include <drm/drm_ioctl.h>
@@ -414,20 +414,45 @@ out_err: · 388 unmodified lines
414414 return ret;
415415 }
416416
417+/*
418+ * Hardware for gma500 is a hybrid device, which both acts as a PCI
419+ * device (for legacy vga functionality) but also more like an
420+ * integrated display on a SoC where the framebuffer simply
421+ * resides in main memory and not in a special PCI bar (that
422+ * internally redirects to a stolen range of main memory) like all
423+ * other integrated PCI display devices implement it.
424+ *
425+ * To catch all cases we need to remove conflicting firmware devices
426+ * for the stolen system memory and for the VGA functionality. As we
427+ * currently cannot easily find the framebuffer's location in stolen
428+ * memory, we remove all framebuffers here.
429+ *
430+ * TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then
431+ * we might be able to read the framebuffer range from the
432+ * device.
433+ */
434+static int gma_remove_conflicting_framebuffers(struct pci_dev *pdev,
435+ const struct drm_driver *req_driver)
436+{
437+ resource_size_t base = 0;
438+ resource_size_t size = U32_MAX; /* 4 GiB HW limit */
439+ const char *name = req_driver->name;
440+ int ret;
441+
442+ ret = aperture_remove_conflicting_devices(base, size, name);
443+ if (ret)
444+ return ret;
445+
446+ return __aperture_remove_legacy_vga_devices(pdev);
447+}
448+
417449 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
418450 {
419451 struct drm_psb_private *dev_priv;
420452 struct drm_device *dev;
421453 int ret;
422454
423− /*
424− * We cannot yet easily find the framebuffer's location in memory. So
425− * remove all framebuffers here.
426− *
427− * TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then we
428− * might be able to read the framebuffer range from the device.
429− */
430− ret = drm_aperture_remove_framebuffers(true, &driver);
455+ ret = gma_remove_conflicting_framebuffers(pdev, &driver);
431456 if (ret)
432457 return ret;
433458
drivers/gpu/drm/hyperv/hyperv_drm_drv.c+0−1
@@ -74,7 +74,6 @@ static int hyperv_setup_vram(struct hyperv_drm_device *hv, · 73 unmodified lines
7474
7575 drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,
7676 screen_info.lfb_size,
77− false,
7877 &hyperv_driver);
7978
8079 hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024;
drivers/gpu/drm/i915/Makefile+4−2
@@ -195,6 +195,7 @@ i915-y += \ · 194 unmodified lines
195195 # general-purpose microcontroller (GuC) support
196196 i915-y += \
197197 gt/uc/intel_gsc_fw.o \
198+ gt/uc/intel_gsc_proxy.o \
198199 gt/uc/intel_gsc_uc.o \
199200 gt/uc/intel_gsc_uc_heci_cmd_submit.o\
200201 gt/uc/intel_guc.o \
@@ -347,6 +348,7 @@ i915-y += \ · 146 unmodified lines
347348 i915-$(CONFIG_DRM_I915_PXP) += \
348349 pxp/intel_pxp_cmd.o \
349350 pxp/intel_pxp_debugfs.o \
351+ pxp/intel_pxp_gsccs.o \
350352 pxp/intel_pxp_irq.o \
351353 pxp/intel_pxp_pm.o \
352354 pxp/intel_pxp_session.o
@@ -382,7 +384,7 @@ obj-$(CONFIG_DRM_I915_GVT_KVMGT) += kvmgt.o · 29 unmodified lines
382384 #
383385 # Enable locally for CONFIG_DRM_I915_WERROR=y. See also scripts/Makefile.build
384386 ifdef CONFIG_DRM_I915_WERROR
385− cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $<
387+ cmd_checkdoc = $(srctree)/scripts/kernel-doc -none -Werror $<
386388 endif
387389
388390 # header test
@@ -397,7 +399,7 @@ always-$(CONFIG_DRM_I915_WERROR) += \ · 8 unmodified lines
397399
398400 quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
399401 cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; \
400− $(srctree)/scripts/kernel-doc -none $<; touch $@
402+ $(srctree)/scripts/kernel-doc -none -Werror $<; touch $@
401403
402404 $(obj)/%.hdrtest: $(src)/%.h FORCE
403405 $(call if_changed_dep,hdrtest)
drivers/gpu/drm/i915/display/intel_dpt.c+7−7
@@ -43,24 +43,24 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) · 42 unmodified lines
4343 static void dpt_insert_page(struct i915_address_space *vm,
4444 dma_addr_t addr,
4545 u64 offset,
46− enum i915_cache_level level,
46+ unsigned int pat_index,
4747 u32 flags)
4848 {
4949 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
5050 gen8_pte_t __iomem *base = dpt->iomem;
5151
5252 gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
53− vm->pte_encode(addr, level, flags));
53+ vm->pte_encode(addr, pat_index, flags));
5454 }
5555
5656 static void dpt_insert_entries(struct i915_address_space *vm,
5757 struct i915_vma_resource *vma_res,
58− enum i915_cache_level level,
58+ unsigned int pat_index,
5959 u32 flags)
6060 {
6161 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
6262 gen8_pte_t __iomem *base = dpt->iomem;
63− const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
63+ const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
6464 struct sgt_iter sgt_iter;
6565 dma_addr_t addr;
6666 int i;
@@ -83,7 +83,7 @@ static void dpt_clear_range(struct i915_address_space *vm, · 16 unmodified lines
8383 static void dpt_bind_vma(struct i915_address_space *vm,
8484 struct i915_vm_pt_stash *stash,
8585 struct i915_vma_resource *vma_res,
86− enum i915_cache_level cache_level,
86+ unsigned int pat_index,
8787 u32 flags)
8888 {
8989 u32 pte_flags;
@@ -98,7 +98,7 @@ static void dpt_bind_vma(struct i915_address_space *vm, · 8 unmodified lines
9898 if (vma_res->bi.lmem)
9999 pte_flags |= PTE_LM;
100100
101− vm->insert_entries(vm, vma_res, cache_level, pte_flags);
101+ vm->insert_entries(vm, vma_res, pat_index, pte_flags);
102102
103103 vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
104104
@@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb) · 195 unmodified lines
300300 vm->vma_ops.bind_vma = dpt_bind_vma;
301301 vm->vma_ops.unbind_vma = dpt_unbind_vma;
302302
303− vm->pte_encode = gen8_ggtt_pte_encode;
303+ vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
304304
305305 dpt->obj = dpt_obj;
306306 dpt->obj->is_dpt = true;
drivers/gpu/drm/i915/display/intel_fb.c+6−3
@@ -1230,7 +1230,8 @@ bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) · 1229 unmodified lines
12301230 {
12311231 struct drm_i915_private *i915 = to_i915(fb->base.dev);
12321232
1233− return IS_ALDERLAKE_P(i915) && intel_fb_uses_dpt(&fb->base);
1233+ return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1234+ intel_fb_uses_dpt(&fb->base);
12341235 }
12351236
12361237 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
@@ -1366,9 +1367,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, · 129 unmodified lines
13661367 unsigned int tile_width,
13671368 unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
13681369 {
1370+ struct drm_i915_private *i915 = to_i915(fb->base.dev);
13691371 unsigned int stride_tiles;
13701372
1371− if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
1373+ if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
13721374 stride_tiles = src_stride_tiles;
13731375 else
13741376 stride_tiles = dst_stride_tiles;
@@ -1562,7 +1564,8 @@ static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_vi · 187 unmodified lines
15621564 memset(view, 0, sizeof(*view));
15631565 view->gtt.type = view_type;
15641566
1565− if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
1567+ if (view_type == I915_GTT_VIEW_REMAPPED &&
1568+ (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
15661569 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
15671570 }
15681571
drivers/gpu/drm/i915/display/intel_fbdev.c+24−14
@@ -40,8 +40,10 @@ · 39 unmodified lines
4040 #include <drm/drm_crtc.h>
4141 #include <drm/drm_fb_helper.h>
4242 #include <drm/drm_fourcc.h>
43+#include <drm/drm_gem_framebuffer_helper.h>
4344
4445 #include "gem/i915_gem_lmem.h"
46+#include "gem/i915_gem_mman.h"
4547
4648 #include "i915_drv.h"
4749 #include "intel_display_types.h"
@@ -67,6 +69,11 @@ struct intel_fbdev { · 19 unmodified lines
6769 struct mutex hpd_lock;
6870 };
6971
72+static struct intel_fbdev *to_intel_fbdev(struct drm_fb_helper *fb_helper)
73+{
74+ return container_of(fb_helper, struct intel_fbdev, helper);
75+}
76+
7077 static struct intel_frontbuffer *to_frontbuffer(struct intel_fbdev *ifbdev)
7178 {
7279 return ifbdev->fb->frontbuffer;
@@ -79,9 +86,7 @@ static void intel_fbdev_invalidate(struct intel_fbdev *ifbdev) · 6 unmodified lines
7986
8087 static int intel_fbdev_set_par(struct fb_info *info)
8188 {
82− struct drm_fb_helper *fb_helper = info->par;
83− struct intel_fbdev *ifbdev =
84− container_of(fb_helper, struct intel_fbdev, helper);
89+ struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
8590 int ret;
8691
8792 ret = drm_fb_helper_set_par(info);
@@ -93,9 +98,7 @@ static int intel_fbdev_set_par(struct fb_info *info) · 5 unmodified lines
9398
9499 static int intel_fbdev_blank(int blank, struct fb_info *info)
95100 {
96− struct drm_fb_helper *fb_helper = info->par;
97− struct intel_fbdev *ifbdev =
98− container_of(fb_helper, struct intel_fbdev, helper);
101+ struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
99102 int ret;
100103
101104 ret = drm_fb_helper_blank(blank, info);
@@ -108,9 +111,7 @@ static int intel_fbdev_blank(int blank, struct fb_info *info) · 6 unmodified lines
108111 static int intel_fbdev_pan_display(struct fb_var_screeninfo *var,
109112 struct fb_info *info)
110113 {
111− struct drm_fb_helper *fb_helper = info->par;
112− struct intel_fbdev *ifbdev =
113− container_of(fb_helper, struct intel_fbdev, helper);
114+ struct intel_fbdev *ifbdev = to_intel_fbdev(info->par);
114115 int ret;
115116
116117 ret = drm_fb_helper_pan_display(var, info);
@@ -120,6 +121,15 @@ static int intel_fbdev_pan_display(struct fb_var_screeninfo *var, · 3 unmodified lines
120121 return ret;
121122 }
122123
124+static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma)
125+{
126+ struct intel_fbdev *fbdev = to_intel_fbdev(info->par);
127+ struct drm_gem_object *bo = drm_gem_fb_get_obj(&fbdev->fb->base, 0);
128+ struct drm_i915_gem_object *obj = to_intel_bo(bo);
129+
130+ return i915_gem_fb_mmap(obj, vma);
131+}
132+
123133 static const struct fb_ops intelfb_ops = {
124134 .owner = THIS_MODULE,
125135 DRM_FB_HELPER_DEFAULT_OPS,
@@ -131,13 +141,13 @@ static const struct fb_ops intelfb_ops = { · 5 unmodified lines
131141 .fb_imageblit = drm_fb_helper_cfb_imageblit,
132142 .fb_pan_display = intel_fbdev_pan_display,
133143 .fb_blank = intel_fbdev_blank,
144+ .fb_mmap = intel_fbdev_mmap,
134145 };
135146
136147 static int intelfb_alloc(struct drm_fb_helper *helper,
137148 struct drm_fb_helper_surface_size *sizes)
138149 {
139− struct intel_fbdev *ifbdev =
140− container_of(helper, struct intel_fbdev, helper);
150+ struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
141151 struct drm_framebuffer *fb;
142152 struct drm_device *dev = helper->dev;
143153 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -163,7 +173,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper, · 19 unmodified lines
163173 obj = ERR_PTR(-ENODEV);
164174 if (HAS_LMEM(dev_priv)) {
165175 obj = i915_gem_object_create_lmem(dev_priv, size,
166− I915_BO_ALLOC_CONTIGUOUS);
176+ I915_BO_ALLOC_CONTIGUOUS |
177+ I915_BO_ALLOC_USER);
167178 } else {
168179 /*
169180 * If the FB is too big, just don't use it since fbdev is not very
@@ -193,8 +204,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper, · 23 unmodified lines
193204 static int intelfb_create(struct drm_fb_helper *helper,
194205 struct drm_fb_helper_surface_size *sizes)
195206 {
196− struct intel_fbdev *ifbdev =
197− container_of(helper, struct intel_fbdev, helper);
207+ struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
198208 struct intel_framebuffer *intel_fb = ifbdev->fb;
199209 struct drm_device *dev = helper->dev;
200210 struct drm_i915_private *dev_priv = to_i915(dev);
drivers/gpu/drm/i915/display/intel_plane_initial.c+3−1
@@ -110,7 +110,9 @@ initial_plane_vma(struct drm_i915_private *i915, · 109 unmodified lines
110110 size * 2 > i915->dsm.usable_size)
111111 return NULL;
112112
113− obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
113+ obj = i915_gem_object_create_region_at(mem, phys_base, size,
114+ I915_BO_ALLOC_USER |
115+ I915_BO_PREALLOC);
114116 if (IS_ERR(obj))
115117 return NULL;
116118
drivers/gpu/drm/i915/gem/i915_gem_domain.c+43−18
@@ -27,8 +27,15 @@ static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) · 26 unmodified lines
2727 if (IS_DGFX(i915))
2828 return false;
2929
30− return !(obj->cache_level == I915_CACHE_NONE ||
31− obj->cache_level == I915_CACHE_WT);
30+ /*
31+ * For objects created by userspace through GEM_CREATE with pat_index
32+ * set by set_pat extension, i915_gem_object_has_cache_level() will
33+ * always return true, because the coherency of such object is managed
34+ * by userspace. Othereise the call here would fall back to checking
35+ * whether the object is un-cached or write-through.
36+ */
37+ return !(i915_gem_object_has_cache_level(obj, I915_CACHE_NONE) ||
38+ i915_gem_object_has_cache_level(obj, I915_CACHE_WT));
3239 }
3340
3441 bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
@@ -267,7 +274,13 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, · 232 unmodified lines
267274 {
268275 int ret;
269276
270− if (obj->cache_level == cache_level)
277+ /*
278+ * For objects created by userspace through GEM_CREATE with pat_index
279+ * set by set_pat extension, simply return 0 here without touching
280+ * the cache setting, because such objects should have an immutable
281+ * cache setting by desgin and always managed by userspace.
282+ */
283+ if (i915_gem_object_has_cache_level(obj, cache_level))
271284 return 0;
272285
273286 ret = i915_gem_object_wait(obj,
@@ -278,10 +291,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, · 4 unmodified lines
278291 return ret;
279292
280293 /* Always invalidate stale cachelines */
281− if (obj->cache_level != cache_level) {
282− i915_gem_object_set_cache_coherency(obj, cache_level);
283− obj->cache_dirty = true;
284− }
294+ i915_gem_object_set_cache_coherency(obj, cache_level);
295+ obj->cache_dirty = true;
285296
286297 /* The cache-level will be applied when each vma is rebound. */
287298 return i915_gem_object_unbind(obj,
@@ -306,20 +317,22 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, · 18 unmodified lines
306317 goto out;
307318 }
308319
309− switch (obj->cache_level) {
310− case I915_CACHE_LLC:
311− case I915_CACHE_L3_LLC:
312− args->caching = I915_CACHING_CACHED;
313− break;
320+ /*
321+ * This ioctl should be disabled for the objects with pat_index
322+ * set by user space.
323+ */
324+ if (obj->pat_set_by_user) {
325+ err = -EOPNOTSUPP;
326+ goto out;
327+ }
314328
315− case I915_CACHE_WT:
329+ if (i915_gem_object_has_cache_level(obj, I915_CACHE_LLC) ||
330+ i915_gem_object_has_cache_level(obj, I915_CACHE_L3_LLC))
331+ args->caching = I915_CACHING_CACHED;
332+ else if (i915_gem_object_has_cache_level(obj, I915_CACHE_WT))
316333 args->caching = I915_CACHING_DISPLAY;
317− break;
318−
319− default:
334+ else
320335 args->caching = I915_CACHING_NONE;
321− break;
322− }
323336 out:
324337 rcu_read_unlock();
325338 return err;
@@ -337,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, · 11 unmodified lines
337350 if (IS_DGFX(i915))
338351 return -ENODEV;
339352
353+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
354+ return -EOPNOTSUPP;
355+
340356 switch (args->caching) {
341357 case I915_CACHING_NONE:
342358 level = I915_CACHE_NONE;
@@ -364,6 +380,15 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, · 21 unmodified lines
364380 if (!obj)
365381 return -ENOENT;
366382
383+ /*
384+ * This ioctl should be disabled for the objects with pat_index
385+ * set by user space.
386+ */
387+ if (obj->pat_set_by_user) {
388+ ret = -EOPNOTSUPP;
389+ goto out;
390+ }
391+
367392 /*
368393 * The caching mode of proxy object is handled by its generator, and
369394 * not allowed to be changed by userspace.
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+12−3
@@ -640,9 +640,15 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, · 639 unmodified lines
640640 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
641641 return false;
642642
643+ /*
644+ * For objects created by userspace through GEM_CREATE with pat_index
645+ * set by set_pat extension, i915_gem_object_has_cache_level() always
646+ * return true, otherwise the call would fall back to checking whether
647+ * the object is un-cached.
648+ */
643649 return (cache->has_llc ||
644650 obj->cache_dirty ||
645− obj->cache_level != I915_CACHE_NONE);
651+ !i915_gem_object_has_cache_level(obj, I915_CACHE_NONE));
646652 }
647653
648654 static int eb_reserve_vma(struct i915_execbuffer *eb,
@@ -1324,7 +1330,10 @@ static void *reloc_iomap(struct i915_vma *batch, · 675 unmodified lines
13241330 if (drm_mm_node_allocated(&cache->node)) {
13251331 ggtt->vm.insert_page(&ggtt->vm,
13261332 i915_gem_object_get_dma_address(obj, page),
1327− offset, I915_CACHE_NONE, 0);
1333+ offset,
1334+ i915_gem_get_pat_index(ggtt->vm.i915,
1335+ I915_CACHE_NONE),
1336+ 0);
13281337 } else {
13291338 offset += page << PAGE_SHIFT;
13301339 }
@@ -1464,7 +1473,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, · 133 unmodified lines
14641473 reloc_cache_unmap(&eb->reloc_cache);
14651474 mutex_lock(&vma->vm->mutex);
14661475 err = i915_vma_bind(target->vma,
1467− target->vma->obj->cache_level,
1476+ target->vma->obj->pat_index,
14681477 PIN_GLOBAL, NULL, NULL);
14691478 mutex_unlock(&vma->vm->mutex);
14701479 reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
drivers/gpu/drm/i915/gem/i915_gem_mman.c+102−46
@@ -383,7 +383,16 @@ retry: · 382 unmodified lines
383383 }
384384
385385 /* Access to snoopable pages through the GTT is incoherent. */
386− if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(i915)) {
386+ /*
387+ * For objects created by userspace through GEM_CREATE with pat_index
388+ * set by set_pat extension, coherency is managed by userspace, make
389+ * sure we don't fail handling the vm fault by calling
390+ * i915_gem_object_has_cache_level() which always return true for such
391+ * objects. Otherwise this helper function would fall back to checking
392+ * whether the object is un-cached.
393+ */
394+ if (!(i915_gem_object_has_cache_level(obj, I915_CACHE_NONE) ||
395+ HAS_LLC(i915))) {
387396 ret = -EFAULT;
388397 goto err_unpin;
389398 }
@@ -927,53 +936,15 @@ static struct file *mmap_singleton(struct drm_i915_private *i915) · 537 unmodified lines
927936 return file;
928937 }
929938
930−/*
931− * This overcomes the limitation in drm_gem_mmap's assignment of a
932− * drm_gem_object as the vma->vm_private_data. Since we need to
933− * be able to resolve multiple mmap offsets which could be tied
934− * to a single gem object.
935− */
936−int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
939+static int
940+i915_gem_object_mmap(struct drm_i915_gem_object *obj,
941+ struct i915_mmap_offset *mmo,
942+ struct vm_area_struct *vma)
937943 {
938− struct drm_vma_offset_node *node;
939− struct drm_file *priv = filp->private_data;
940− struct drm_device *dev = priv->minor->dev;
941− struct drm_i915_gem_object *obj = NULL;
942− struct i915_mmap_offset *mmo = NULL;
944+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
945+ struct drm_device *dev = &i915->drm;
943946 struct file *anon;
944947
945− if (drm_dev_is_unplugged(dev))
946− return -ENODEV;
947−
948− rcu_read_lock();
949− drm_vma_offset_lock_lookup(dev->vma_offset_manager);
950− node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
951− vma->vm_pgoff,
952− vma_pages(vma));
953− if (node && drm_vma_node_is_allowed(node, priv)) {
954− /*
955− * Skip 0-refcnted objects as it is in the process of being
956− * destroyed and will be invalid when the vma manager lock
957− * is released.
958− */
959− if (!node->driver_private) {
960− mmo = container_of(node, struct i915_mmap_offset, vma_node);
961− obj = i915_gem_object_get_rcu(mmo->obj);
962−
963− GEM_BUG_ON(obj && obj->ops->mmap_ops);
964− } else {
965− obj = i915_gem_object_get_rcu
966− (container_of(node, struct drm_i915_gem_object,
967− base.vma_node));
968−
969− GEM_BUG_ON(obj && !obj->ops->mmap_ops);
970− }
971− }
972− drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
973− rcu_read_unlock();
974− if (!obj)
975− return node ? -EACCES : -EINVAL;
976−
977948 if (i915_gem_object_is_readonly(obj)) {
978949 if (vma->vm_flags & VM_WRITE) {
979950 i915_gem_object_put(obj);
@@ -1005,7 +976,7 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma) · 25 unmodified lines
1005976 if (obj->ops->mmap_ops) {
1006977 vma->vm_page_prot = pgprot_decrypted(vm_get_page_prot(vma->vm_flags));
1007978 vma->vm_ops = obj->ops->mmap_ops;
1008− vma->vm_private_data = node->driver_private;
979+ vma->vm_private_data = obj->base.vma_node.driver_private;
1009980 return 0;
1010981 }
1011982
@@ -1043,6 +1014,91 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma) · 31 unmodified lines
10431014 return 0;
10441015 }
10451016
1017+/*
1018+ * This overcomes the limitation in drm_gem_mmap's assignment of a
1019+ * drm_gem_object as the vma->vm_private_data. Since we need to
1020+ * be able to resolve multiple mmap offsets which could be tied
1021+ * to a single gem object.
1022+ */
1023+int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
1024+{
1025+ struct drm_vma_offset_node *node;
1026+ struct drm_file *priv = filp->private_data;
1027+ struct drm_device *dev = priv->minor->dev;
1028+ struct drm_i915_gem_object *obj = NULL;
1029+ struct i915_mmap_offset *mmo = NULL;
1030+
1031+ if (drm_dev_is_unplugged(dev))
1032+ return -ENODEV;
1033+
1034+ rcu_read_lock();
1035+ drm_vma_offset_lock_lookup(dev->vma_offset_manager);
1036+ node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
1037+ vma->vm_pgoff,
1038+ vma_pages(vma));
1039+ if (node && drm_vma_node_is_allowed(node, priv)) {
1040+ /*
1041+ * Skip 0-refcnted objects as it is in the process of being
1042+ * destroyed and will be invalid when the vma manager lock
1043+ * is released.
1044+ */
1045+ if (!node->driver_private) {
1046+ mmo = container_of(node, struct i915_mmap_offset, vma_node);
1047+ obj = i915_gem_object_get_rcu(mmo->obj);
1048+
1049+ GEM_BUG_ON(obj && obj->ops->mmap_ops);
1050+ } else {
1051+ obj = i915_gem_object_get_rcu
1052+ (container_of(node, struct drm_i915_gem_object,
1053+ base.vma_node));
1054+
1055+ GEM_BUG_ON(obj && !obj->ops->mmap_ops);
1056+ }
1057+ }
1058+ drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
1059+ rcu_read_unlock();
1060+ if (!obj)
1061+ return node ? -EACCES : -EINVAL;
1062+
1063+ return i915_gem_object_mmap(obj, mmo, vma);
1064+}
1065+
1066+int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma)
1067+{
1068+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
1069+ struct drm_device *dev = &i915->drm;
1070+ struct i915_mmap_offset *mmo = NULL;
1071+ enum i915_mmap_type mmap_type;
1072+ struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
1073+
1074+ if (drm_dev_is_unplugged(dev))
1075+ return -ENODEV;
1076+
1077+ /* handle ttm object */
1078+ if (obj->ops->mmap_ops) {
1079+ /*
1080+ * ttm fault handler, ttm_bo_vm_fault_reserved() uses fake offset
1081+ * to calculate page offset so set that up.
1082+ */
1083+ vma->vm_pgoff += drm_vma_node_start(&obj->base.vma_node);
1084+ } else {
1085+ /* handle stolen and smem objects */
1086+ mmap_type = i915_ggtt_has_aperture(ggtt) ? I915_MMAP_TYPE_GTT : I915_MMAP_TYPE_WC;
1087+ mmo = mmap_offset_attach(obj, mmap_type, NULL);
1088+ if (!mmo)
1089+ return -ENODEV;
1090+ }
1091+
1092+ /*
1093+ * When we install vm_ops for mmap we are too late for
1094+ * the vm_ops->open() which increases the ref_count of
1095+ * this obj and then it gets decreased by the vm_ops->close().
1096+ * To balance this increase the obj ref_count here.
1097+ */
1098+ obj = i915_gem_object_get(obj);
1099+ return i915_gem_object_mmap(obj, mmo, vma);
1100+}
1101+
10461102 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
10471103 #include "selftests/i915_gem_mman.c"
10481104 #endif
drivers/gpu/drm/i915/gem/i915_gem_mman.h+1−1
@@ -29,5 +29,5 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); · 28 unmodified lines
2929
3030 void i915_gem_object_runtime_pm_release_mmap_offset(struct drm_i915_gem_object *obj);
3131 void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
32−
32+int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma);
3333 #endif
drivers/gpu/drm/i915/gem/i915_gem_object.c+59−1
@@ -45,6 +45,33 @@ static struct kmem_cache *slab_objects; · 44 unmodified lines
4545
4646 static const struct drm_gem_object_funcs i915_gem_object_funcs;
4747
48+unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
49+ enum i915_cache_level level)
50+{
51+ if (drm_WARN_ON(&i915->drm, level >= I915_MAX_CACHE_LEVEL))
52+ return 0;
53+
54+ return INTEL_INFO(i915)->cachelevel_to_pat[level];
55+}
56+
57+bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
58+ enum i915_cache_level lvl)
59+{
60+ /*
61+ * In case the pat_index is set by user space, this kernel mode
62+ * driver should leave the coherency to be managed by user space,
63+ * simply return true here.
64+ */
65+ if (obj->pat_set_by_user)
66+ return true;
67+
68+ /*
69+ * Otherwise the pat_index should have been converted from cache_level
70+ * so that the following comparison is valid.
71+ */
72+ return obj->pat_index == i915_gem_get_pat_index(obj_to_i915(obj), lvl);
73+}
74+
4875 struct drm_i915_gem_object *i915_gem_object_alloc(void)
4976 {
5077 struct drm_i915_gem_object *obj;
@@ -124,7 +151,7 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, · 73 unmodified lines
124151 {
125152 struct drm_i915_private *i915 = to_i915(obj->base.dev);
126153
127− obj->cache_level = cache_level;
154+ obj->pat_index = i915_gem_get_pat_index(i915, cache_level);
128155
129156 if (cache_level != I915_CACHE_NONE)
130157 obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
@@ -139,6 +166,37 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, · 8 unmodified lines
139166 !IS_DGFX(i915);
140167 }
141168
169+/**
170+ * i915_gem_object_set_pat_index - set PAT index to be used in PTE encode
171+ * @obj: #drm_i915_gem_object
172+ * @pat_index: PAT index
173+ *
174+ * This is a clone of i915_gem_object_set_cache_coherency taking pat index
175+ * instead of cache_level as its second argument.
176+ */
177+void i915_gem_object_set_pat_index(struct drm_i915_gem_object *obj,
178+ unsigned int pat_index)
179+{
180+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
181+
182+ if (obj->pat_index == pat_index)
183+ return;
184+
185+ obj->pat_index = pat_index;
186+
187+ if (pat_index != i915_gem_get_pat_index(i915, I915_CACHE_NONE))
188+ obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
189+ I915_BO_CACHE_COHERENT_FOR_WRITE);
190+ else if (HAS_LLC(i915))
191+ obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ;
192+ else
193+ obj->cache_coherent = 0;
194+
195+ obj->cache_dirty =
196+ !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE) &&
197+ !IS_DGFX(i915);
198+}
199+
142200 bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
143201 {
144202 struct drm_i915_private *i915 = to_i915(obj->base.dev);
drivers/gpu/drm/i915/gem/i915_gem_object.h+9−1
@@ -20,6 +20,8 @@ · 19 unmodified lines
2020
2121 enum intel_region_id;
2222
23+#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
24+
2325 static inline bool i915_gem_object_size_2big(u64 size)
2426 {
2527 struct drm_i915_gem_object *obj;
@@ -30,6 +32,10 @@ static inline bool i915_gem_object_size_2big(u64 size) · 4 unmodified lines
3032 return false;
3133 }
3234
35+unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,
36+ enum i915_cache_level level);
37+bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
38+ enum i915_cache_level lvl);
3339 void i915_gem_init__objects(struct drm_i915_private *i915);
3440
3541 void i915_objects_module_exit(void);
@@ -80,7 +86,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj); · 44 unmodified lines
8086
8187 /**
8288 * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
83− * @filp: DRM file private date
89+ * @file: DRM file private date
8490 * @handle: userspace handle
8591 *
8692 * Returns:
@@ -760,6 +766,8 @@ bool i915_gem_object_has_unknown_state(struct drm_i915_gem_object *obj); · 673 unmodified lines
760766
761767 void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
762768 unsigned int cache_level);
769+void i915_gem_object_set_pat_index(struct drm_i915_gem_object *obj,
770+ unsigned int pat_index);
763771 bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj);
764772 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
765773 void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj);
drivers/gpu/drm/i915/gem/i915_gem_object_types.h+60−8
@@ -194,6 +194,13 @@ enum i915_cache_level { · 193 unmodified lines
194194 * engine.
195195 */
196196 I915_CACHE_WT,
197+ /**
198+ * @I915_MAX_CACHE_LEVEL:
199+ *
200+ * Mark the last entry in the enum. Used for defining cachelevel_to_pat
201+ * array for cache_level to pat translation table.
202+ */
203+ I915_MAX_CACHE_LEVEL,
197204 };
198205
199206 enum i915_map_type {
@@ -328,6 +335,12 @@ struct drm_i915_gem_object { · 128 unmodified lines
328335 */
329336 #define I915_BO_ALLOC_GPU_ONLY BIT(6)
330337 #define I915_BO_ALLOC_CCS_AUX BIT(7)
338+/*
339+ * Object is allowed to retain its initial data and will not be cleared on first
340+ * access if used along with I915_BO_ALLOC_USER. This is mainly to keep
341+ * preallocated framebuffer data intact while transitioning it to i915drmfb.
342+ */
343+#define I915_BO_PREALLOC BIT(8)
331344 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
332345 I915_BO_ALLOC_VOLATILE | \
333346 I915_BO_ALLOC_CPU_CLEAR | \
@@ -335,10 +348,11 @@ struct drm_i915_gem_object { · 1 unmodified line
335348 I915_BO_ALLOC_PM_VOLATILE | \
336349 I915_BO_ALLOC_PM_EARLY | \
337350 I915_BO_ALLOC_GPU_ONLY | \
338− I915_BO_ALLOC_CCS_AUX)
339−#define I915_BO_READONLY BIT(8)
340−#define I915_TILING_QUIRK_BIT 9 /* unknown swizzling; do not release! */
341−#define I915_BO_PROTECTED BIT(10)
351+ I915_BO_ALLOC_CCS_AUX | \
352+ I915_BO_PREALLOC)
353+#define I915_BO_READONLY BIT(9)
354+#define I915_TILING_QUIRK_BIT 10 /* unknown swizzling; do not release! */
355+#define I915_BO_PROTECTED BIT(11)
342356 /**
343357 * @mem_flags - Mutable placement-related flags
344358 *
@@ -350,15 +364,43 @@ struct drm_i915_gem_object { · 5 unmodified lines
350364 #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
351365 #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
352366 /**
353− * @cache_level: The desired GTT caching level.
367+ * @pat_index: The desired PAT index.
368+ *
369+ * See hardware specification for valid PAT indices for each platform.
370+ * This field replaces the @cache_level that contains a value of enum
371+ * i915_cache_level since PAT indices are being used by both userspace
372+ * and kernel mode driver for caching policy control after GEN12.
373+ * In the meantime platform specific tables are created to translate
374+ * i915_cache_level into pat index, for more details check the macros
375+ * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
376+ * For backward compatibility, this field contains values exactly match
377+ * the entries of enum i915_cache_level for pre-GEN12 platforms (See
378+ * LEGACY_CACHELEVEL), so that the PTE encode functions for these
379+ * legacy platforms can stay the same.
380+ */
381+ unsigned int pat_index:6;
382+ /**
383+ * @pat_set_by_user: Indicate whether pat_index is set by user space
354384 *
355− * See enum i915_cache_level for possible values, along with what
356− * each does.
385+ * This field is set to false by default, only set to true if the
386+ * pat_index is set by user space. By design, user space is capable of
387+ * managing caching behavior by setting pat_index, in which case this
388+ * kernel mode driver should never touch the pat_index.
357389 */
358− unsigned int cache_level:3;
390+ unsigned int pat_set_by_user:1;
359391 /**
360392 * @cache_coherent:
361393 *
394+ * Note: with the change above which replaced @cache_level with pat_index,
395+ * the use of @cache_coherent is limited to the objects created by kernel
396+ * or by userspace without pat index specified.
397+ * Check for @pat_set_by_user to find out if an object has pat index set
398+ * by userspace. The ioctl's to change cache settings have also been
399+ * disabled for the objects with pat index set by userspace. Please don't
400+ * assume @cache_coherent having the flags set as describe here. A helper
401+ * function i915_gem_object_has_cache_level() provides one way to bypass
402+ * the use of this field.
403+ *
362404 * Track whether the pages are coherent with the GPU if reading or
363405 * writing through the CPU caches. The largely depends on the
364406 * @cache_level setting.
@@ -432,6 +474,16 @@ struct drm_i915_gem_object { · 67 unmodified lines
432474 /**
433475 * @cache_dirty:
434476 *
477+ * Note: with the change above which replaced cache_level with pat_index,
478+ * the use of @cache_dirty is limited to the objects created by kernel
479+ * or by userspace without pat index specified.
480+ * Check for @pat_set_by_user to find out if an object has pat index set
481+ * by userspace. The ioctl's to change cache settings have also been
482+ * disabled for the objects with pat_index set by userspace. Please don't
483+ * assume @cache_dirty is set as describe here. Also see helper function
484+ * i915_gem_object_has_cache_level() for possible ways to bypass the use
485+ * of this field.
486+ *
435487 * Track if we are we dirty with writes through the CPU cache for this
436488 * object. As a result reading directly from main memory might yield
437489 * stale data.
drivers/gpu/drm/i915/gem/i915_gem_pages.c+4−1
@@ -469,7 +469,10 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915, · 468 unmodified lines
469469 struct drm_i915_gem_object *obj,
470470 bool always_coherent)
471471 {
472− if (i915_gem_object_is_lmem(obj))
472+ /*
473+ * Wa_22016122933: always return I915_MAP_WC for MTL
474+ */
475+ if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
473476 return I915_MAP_WC;
474477 if (HAS_LLC(i915) || always_coherent)
475478 return I915_MAP_WB;
drivers/gpu/drm/i915/gem/i915_gem_region.h+1−3
@@ -22,9 +22,7 @@ struct i915_gem_apply_to_region; · 21 unmodified lines
2222 */
2323 struct i915_gem_apply_to_region_ops {
2424 /**
25− * process_obj - Process the current object
26− * @apply: Embed this for private data.
27− * @obj: The current object.
25+ * @process_obj: Process the current object
2826 *
2927 * Note that if this function is part of a ww transaction, and
3028 * if returns -EDEADLK for one of the objects, it may be
drivers/gpu/drm/i915/gem/i915_gem_shmem.c+8−1
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, · 600 unmodified lines
601601 obj->write_domain = I915_GEM_DOMAIN_CPU;
602602 obj->read_domains = I915_GEM_DOMAIN_CPU;
603603
604− if (HAS_LLC(i915))
604+ /*
605+ * MTL doesn't snoop CPU cache by default for GPU access (namely
606+ * 1-way coherency). However some UMD's are currently depending on
607+ * that. Make 1-way coherent the default setting for MTL. A follow
608+ * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
609+ * caching mode at BO creation time
610+ */
611+ if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
605612 /* On some devices, we can have the GPU use the LLC (the CPU
606613 * cache) for about a 10% performance improvement
607614 * compared to uncached. Graphics requests other than
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c+0−2
@@ -460,8 +460,6 @@ void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915, · 459 unmodified lines
460460 fs_reclaim_release(GFP_KERNEL);
461461 }
462462
463−#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
464−
465463 /**
466464 * i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By
467465 * default all object types that support shrinking(see IS_SHRINKABLE), will also
drivers/gpu/drm/i915/gem/i915_gem_stolen.c+11−1
@@ -535,6 +535,14 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem) · 534 unmodified lines
535535 /* Basic memrange allocator for stolen space. */
536536 drm_mm_init(&i915->mm.stolen, 0, i915->dsm.usable_size);
537537
538+ /*
539+ * Access to stolen lmem beyond certain size for MTL A0 stepping
540+ * would crash the machine. Disable stolen lmem for userspace access
541+ * by setting usable_size to zero.
542+ */
543+ if (IS_METEORLAKE(i915) && INTEL_REVID(i915) == 0x0)
544+ i915->dsm.usable_size = 0;
545+
538546 return 0;
539547 }
540548
@@ -557,7 +565,9 @@ static void dbg_poison(struct i915_ggtt *ggtt, · 16 unmodified lines
557565
558566 ggtt->vm.insert_page(&ggtt->vm, addr,
559567 ggtt->error_capture.start,
560− I915_CACHE_NONE, 0);
568+ i915_gem_get_pat_index(ggtt->vm.i915,
569+ I915_CACHE_NONE),
570+ 0);
561571 mb();
562572
563573 s = io_mapping_map_wc(&ggtt->iomap,
drivers/gpu/drm/i915/gem/i915_gem_ttm.h+2−1
@@ -42,8 +42,9 @@ static inline bool i915_ttm_is_ghost_object(struct ttm_buffer_object *bo) · 41 unmodified lines
4242 /**
4343 * i915_ttm_to_gem - Convert a struct ttm_buffer_object to an embedding
4444 * struct drm_i915_gem_object.
45+ * @bo: Pointer to the ttm buffer object
4546 *
46− * Return: Pointer to the embedding struct ttm_buffer_object.
47+ * Return: Pointer to the embedding struct drm_i915_gem_object.
4748 */
4849 static inline struct drm_i915_gem_object *
4950 i915_ttm_to_gem(struct ttm_buffer_object *bo)
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c+8−5
@@ -214,7 +214,8 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo, · 213 unmodified lines
214214
215215 intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
216216 ret = intel_context_migrate_clear(to_gt(i915)->migrate.context, deps,
217− dst_st->sgl, dst_level,
217+ dst_st->sgl,
218+ i915_gem_get_pat_index(i915, dst_level),
218219 i915_ttm_gtt_binds_lmem(dst_mem),
219220 0, &rq);
220221 } else {
@@ -228,9 +229,10 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo, · 7 unmodified lines
228229 intel_engine_pm_get(to_gt(i915)->migrate.context->engine);
229230 ret = intel_context_migrate_copy(to_gt(i915)->migrate.context,
230231 deps, src_rsgt->table.sgl,
231− src_level,
232+ i915_gem_get_pat_index(i915, src_level),
232233 i915_ttm_gtt_binds_lmem(bo->resource),
233− dst_st->sgl, dst_level,
234+ dst_st->sgl,
235+ i915_gem_get_pat_index(i915, dst_level),
234236 i915_ttm_gtt_binds_lmem(dst_mem),
235237 &rq);
236238
@@ -576,7 +578,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict, · 339 unmodified lines
576578 struct dma_fence *migration_fence = NULL;
577579 struct ttm_tt *ttm = bo->ttm;
578580 struct i915_refct_sgt *dst_rsgt;
579− bool clear;
581+ bool clear, prealloc_bo;
580582 int ret;
581583
582584 if (GEM_WARN_ON(i915_ttm_is_ghost_object(bo))) {
@@ -632,7 +634,8 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict, · 49 unmodified lines
632634 return PTR_ERR(dst_rsgt);
633635
634636 clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
635− if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC))) {
637+ prealloc_bo = obj->flags & I915_BO_PREALLOC;
638+ if (!(clear && ttm && !((ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC) && !prealloc_bo))) {
636639 struct i915_deps deps;
637640
638641 i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
drivers/gpu/drm/i915/gem/selftests/huge_pages.c+82−26
@@ -354,7 +354,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single) · 353 unmodified lines
354354
355355 obj->write_domain = I915_GEM_DOMAIN_CPU;
356356 obj->read_domains = I915_GEM_DOMAIN_CPU;
357− obj->cache_level = I915_CACHE_NONE;
357+ obj->pat_index = i915_gem_get_pat_index(i915, I915_CACHE_NONE);
358358
359359 return obj;
360360 }
@@ -695,8 +695,7 @@ out_put: · 334 unmodified lines
695695 return err;
696696 }
697697
698−static void close_object_list(struct list_head *objects,
699− struct i915_ppgtt *ppgtt)
698+static void close_object_list(struct list_head *objects)
700699 {
701700 struct drm_i915_gem_object *obj, *on;
702701
@@ -710,17 +709,36 @@ static void close_object_list(struct list_head *objects, · 7 unmodified lines
710709 }
711710 }
712711
713−static int igt_mock_ppgtt_huge_fill(void *arg)
712+static int igt_ppgtt_huge_fill(void *arg)
714713 {
715− struct i915_ppgtt *ppgtt = arg;
716− struct drm_i915_private *i915 = ppgtt->vm.i915;
717− unsigned long max_pages = ppgtt->vm.total >> PAGE_SHIFT;
714+ struct drm_i915_private *i915 = arg;
715+ unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
716+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
717+ struct i915_address_space *vm;
718+ struct i915_gem_context *ctx;
719+ unsigned long max_pages;
718720 unsigned long page_num;
721+ struct file *file;
719722 bool single = false;
720723 LIST_HEAD(objects);
721724 IGT_TIMEOUT(end_time);
722725 int err = -ENODEV;
723726
727+ if (supported == I915_GTT_PAGE_SIZE_4K)
728+ return 0;
729+
730+ file = mock_file(i915);
731+ if (IS_ERR(file))
732+ return PTR_ERR(file);
733+
734+ ctx = hugepage_ctx(i915, file);
735+ if (IS_ERR(ctx)) {
736+ err = PTR_ERR(ctx);
737+ goto out;
738+ }
739+ vm = i915_gem_context_get_eb_vm(ctx);
740+ max_pages = vm->total >> PAGE_SHIFT;
741+
724742 for_each_prime_number_from(page_num, 1, max_pages) {
725743 struct drm_i915_gem_object *obj;
726744 u64 size = page_num << PAGE_SHIFT;
@@ -750,13 +768,14 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 23 unmodified lines
750768
751769 list_add(&obj->st_link, &objects);
752770
753− vma = i915_vma_instance(obj, &ppgtt->vm, NULL);
771+ vma = i915_vma_instance(obj, vm, NULL);
754772 if (IS_ERR(vma)) {
755773 err = PTR_ERR(vma);
756774 break;
757775 }
758776
759− err = i915_vma_pin(vma, 0, 0, PIN_USER);
777+ /* vma start must be aligned to BIT(21) to allow 2M PTEs */
778+ err = i915_vma_pin(vma, 0, BIT(21), PIN_USER);
760779 if (err)
761780 break;
762781
@@ -784,12 +803,13 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 21 unmodified lines
784803 GEM_BUG_ON(!expected_gtt);
785804 GEM_BUG_ON(size);
786805
787− if (expected_gtt & I915_GTT_PAGE_SIZE_4K)
806+ if (!has_pte64 && (obj->base.size < I915_GTT_PAGE_SIZE_2M ||
807+ expected_gtt & I915_GTT_PAGE_SIZE_2M))
788808 expected_gtt &= ~I915_GTT_PAGE_SIZE_64K;
789809
790810 i915_vma_unpin(vma);
791811
792− if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
812+ if (!has_pte64 && vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
793813 if (!IS_ALIGNED(vma->node.start,
794814 I915_GTT_PAGE_SIZE_2M)) {
795815 pr_err("node.start(%llx) not aligned to 2M\n",
@@ -808,7 +828,7 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 12 unmodified lines
808828 }
809829
810830 if (vma->resource->page_sizes_gtt != expected_gtt) {
811− pr_err("gtt=%u, expected=%u, size=%zd, single=%s\n",
831+ pr_err("gtt=%#x, expected=%#x, size=0x%zx, single=%s\n",
812832 vma->resource->page_sizes_gtt, expected_gtt,
813833 obj->base.size, str_yes_no(!!single));
814834 err = -EINVAL;
@@ -823,19 +843,25 @@ static int igt_mock_ppgtt_huge_fill(void *arg) · 8 unmodified lines
823843 single = !single;
824844 }
825845
826− close_object_list(&objects, ppgtt);
846+ close_object_list(&objects);
827847
828848 if (err == -ENOMEM || err == -ENOSPC)
829849 err = 0;
830850
851+ i915_vm_put(vm);
852+out:
853+ fput(file);
831854 return err;
832855 }
833856
834−static int igt_mock_ppgtt_64K(void *arg)
857+static int igt_ppgtt_64K(void *arg)
835858 {
836− struct i915_ppgtt *ppgtt = arg;
837− struct drm_i915_private *i915 = ppgtt->vm.i915;
859+ struct drm_i915_private *i915 = arg;
860+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
838861 struct drm_i915_gem_object *obj;
862+ struct i915_address_space *vm;
863+ struct i915_gem_context *ctx;
864+ struct file *file;
839865 const struct object_info {
840866 unsigned int size;
841867 unsigned int gtt;
@@ -907,16 +933,41 @@ static int igt_mock_ppgtt_64K(void *arg) · 65 unmodified lines
907933 if (!HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K))
908934 return 0;
909935
936+ file = mock_file(i915);
937+ if (IS_ERR(file))
938+ return PTR_ERR(file);
939+
940+ ctx = hugepage_ctx(i915, file);
941+ if (IS_ERR(ctx)) {
942+ err = PTR_ERR(ctx);
943+ goto out;
944+ }
945+ vm = i915_gem_context_get_eb_vm(ctx);
946+
910947 for (i = 0; i < ARRAY_SIZE(objects); ++i) {
911948 unsigned int size = objects[i].size;
912949 unsigned int expected_gtt = objects[i].gtt;
913950 unsigned int offset = objects[i].offset;
914951 unsigned int flags = PIN_USER;
915952
953+ /*
954+ * For modern GTT models, the requirements for marking a page-table
955+ * as 64K have been relaxed. Account for this.
956+ */
957+ if (has_pte64) {
958+ expected_gtt = 0;
959+ if (size >= SZ_64K)
960+ expected_gtt |= I915_GTT_PAGE_SIZE_64K;
961+ if (size & (SZ_64K - 1))
962+ expected_gtt |= I915_GTT_PAGE_SIZE_4K;
963+ }
964+
916965 for (single = 0; single <= 1; single++) {
917966 obj = fake_huge_pages_object(i915, size, !!single);
918− if (IS_ERR(obj))
919− return PTR_ERR(obj);
967+ if (IS_ERR(obj)) {
968+ err = PTR_ERR(obj);
969+ goto out_vm;
970+ }
920971
921972 err = i915_gem_object_pin_pages_unlocked(obj);
922973 if (err)
@@ -928,7 +979,7 @@ static int igt_mock_ppgtt_64K(void *arg) · 5 unmodified lines
928979 */
929980 obj->mm.page_sizes.sg &= ~I915_GTT_PAGE_SIZE_2M;
930981
931− vma = i915_vma_instance(obj, &ppgtt->vm, NULL);
982+ vma = i915_vma_instance(obj, vm, NULL);
932983 if (IS_ERR(vma)) {
933984 err = PTR_ERR(vma);
934985 goto out_object_unpin;
@@ -945,7 +996,8 @@ static int igt_mock_ppgtt_64K(void *arg) · 10 unmodified lines
945996 if (err)
946997 goto out_vma_unpin;
947998
948− if (!offset && vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
999+ if (!has_pte64 && !offset &&
1000+ vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
9491001 if (!IS_ALIGNED(vma->node.start,
9501002 I915_GTT_PAGE_SIZE_2M)) {
9511003 pr_err("node.start(%llx) not aligned to 2M\n",
@@ -964,9 +1016,10 @@ static int igt_mock_ppgtt_64K(void *arg) · 12 unmodified lines
9641016 }
9651017
9661018 if (vma->resource->page_sizes_gtt != expected_gtt) {
967− pr_err("gtt=%u, expected=%u, i=%d, single=%s\n",
1019+ pr_err("gtt=%#x, expected=%#x, i=%d, single=%s offset=%#x size=%#x\n",
9681020 vma->resource->page_sizes_gtt,
969− expected_gtt, i, str_yes_no(!!single));
1021+ expected_gtt, i, str_yes_no(!!single),
1022+ offset, size);
9701023 err = -EINVAL;
9711024 goto out_vma_unpin;
9721025 }
@@ -982,7 +1035,7 @@ static int igt_mock_ppgtt_64K(void *arg) · 9 unmodified lines
9821035 }
9831036 }
9841037
985− return 0;
1038+ goto out_vm;
9861039
9871040 out_vma_unpin:
9881041 i915_vma_unpin(vma);
@@ -992,7 +1045,10 @@ out_object_unpin: · 3 unmodified lines
9921045 i915_gem_object_unlock(obj);
9931046 out_object_put:
9941047 i915_gem_object_put(obj);
995−
1048+out_vm:
1049+ i915_vm_put(vm);
1050+out:
1051+ fput(file);
9961052 return err;
9971053 }
9981054
@@ -1910,8 +1966,6 @@ int i915_gem_huge_page_mock_selftests(void) · 911 unmodified lines
19101966 SUBTEST(igt_mock_exhaust_device_supported_pages),
19111967 SUBTEST(igt_mock_memory_region_huge_pages),
19121968 SUBTEST(igt_mock_ppgtt_misaligned_dma),
1913− SUBTEST(igt_mock_ppgtt_huge_fill),
1914− SUBTEST(igt_mock_ppgtt_64K),
19151969 };
19161970 struct drm_i915_private *dev_priv;
19171971 struct i915_ppgtt *ppgtt;
@@ -1962,6 +2016,8 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915) · 44 unmodified lines
19622016 SUBTEST(igt_ppgtt_sanity_check),
19632017 SUBTEST(igt_ppgtt_compact),
19642018 SUBTEST(igt_ppgtt_mixed),
2019+ SUBTEST(igt_ppgtt_huge_fill),
2020+ SUBTEST(igt_ppgtt_64K),
19652021 };
19662022
19672023 if (!HAS_PPGTT(i915)) {
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c+10−8
@@ -66,7 +66,7 @@ static int live_nop_switch(void *arg) · 65 unmodified lines
6666 ctx[n] = live_context(i915, file);
6767 if (IS_ERR(ctx[n])) {
6868 err = PTR_ERR(ctx[n]);
69− goto out_file;
69+ goto out_ctx;
7070 }
7171 }
7272
@@ -82,7 +82,7 @@ static int live_nop_switch(void *arg) · 9 unmodified lines
8282 this = igt_request_alloc(ctx[n], engine);
8383 if (IS_ERR(this)) {
8484 err = PTR_ERR(this);
85− goto out_file;
85+ goto out_ctx;
8686 }
8787 if (rq) {
8888 i915_request_await_dma_fence(this, &rq->fence);
@@ -93,10 +93,10 @@ static int live_nop_switch(void *arg) · 4 unmodified lines
9393 }
9494 if (i915_request_wait(rq, 0, 10 * HZ) < 0) {
9595 pr_err("Failed to populated %d contexts\n", nctx);
96− intel_gt_set_wedged(to_gt(i915));
96+ intel_gt_set_wedged(engine->gt);
9797 i915_request_put(rq);
9898 err = -EIO;
99− goto out_file;
99+ goto out_ctx;
100100 }
101101 i915_request_put(rq);
102102
@@ -107,7 +107,7 @@ static int live_nop_switch(void *arg) · 4 unmodified lines
107107
108108 err = igt_live_test_begin(&t, i915, __func__, engine->name);
109109 if (err)
110− goto out_file;
110+ goto out_ctx;
111111
112112 end_time = jiffies + i915_selftest.timeout_jiffies;
113113 for_each_prime_number_from(prime, 2, 8192) {
@@ -120,7 +120,7 @@ static int live_nop_switch(void *arg) · 6 unmodified lines
120120 this = igt_request_alloc(ctx[n % nctx], engine);
121121 if (IS_ERR(this)) {
122122 err = PTR_ERR(this);
123− goto out_file;
123+ goto out_ctx;
124124 }
125125
126126 if (rq) { /* Force submission order */
@@ -149,7 +149,7 @@ static int live_nop_switch(void *arg) · 22 unmodified lines
149149 if (i915_request_wait(rq, 0, HZ / 5) < 0) {
150150 pr_err("Switching between %ld contexts timed out\n",
151151 prime);
152− intel_gt_set_wedged(to_gt(i915));
152+ intel_gt_set_wedged(engine->gt);
153153 i915_request_put(rq);
154154 break;
155155 }
@@ -165,7 +165,7 @@ static int live_nop_switch(void *arg) · 9 unmodified lines
165165
166166 err = igt_live_test_end(&t);
167167 if (err)
168− goto out_file;
168+ goto out_ctx;
169169
170170 pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
171171 engine->name,
@@ -173,6 +173,8 @@ static int live_nop_switch(void *arg) · 1 unmodified line
173173 prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
174174 }
175175
176+out_ctx:
177+ kfree(ctx);
176178 out_file:
177179 fput(file);
178180 return err;
drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c+1−1
@@ -219,7 +219,7 @@ static int __igt_lmem_pages_migrate(struct intel_gt *gt, · 218 unmodified lines
219219 continue;
220220
221221 err = intel_migrate_clear(&gt->migrate, &ww, deps,
222− obj->mm.pages->sgl, obj->cache_level,
222+ obj->mm.pages->sgl, obj->pat_index,
223223 i915_gem_object_is_lmem(obj),
224224 0xdeadbeaf, &rq);
225225 if (rq) {
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c+1−1
@@ -1222,7 +1222,7 @@ static int __igt_mmap_migrate(struct intel_memory_region **placements, · 1221 unmodified lines
12221222 }
12231223
12241224 err = intel_context_migrate_clear(to_gt(i915)->migrate.context, NULL,
1225− obj->mm.pages->sgl, obj->cache_level,
1225+ obj->mm.pages->sgl, obj->pat_index,
12261226 i915_gem_object_is_lmem(obj),
12271227 expand32(POISON_INUSE), &rq);
12281228 i915_gem_object_unpin_pages(obj);
drivers/gpu/drm/i915/gt/gen6_ppgtt.c+6−4
@@ -109,7 +109,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm, · 108 unmodified lines
109109
110110 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
111111 struct i915_vma_resource *vma_res,
112− enum i915_cache_level cache_level,
112+ unsigned int pat_index,
113113 u32 flags)
114114 {
115115 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -117,7 +117,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, · 1 unmodified line
117117 unsigned int first_entry = vma_res->start / I915_GTT_PAGE_SIZE;
118118 unsigned int act_pt = first_entry / GEN6_PTES;
119119 unsigned int act_pte = first_entry % GEN6_PTES;
120− const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
120+ const u32 pte_encode = vm->pte_encode(0, pat_index, flags);
121121 struct sgt_dma iter = sgt_dma(vma_res);
122122 gen6_pte_t *vaddr;
123123
@@ -227,7 +227,9 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt) · 103 unmodified lines
227227
228228 vm->scratch[0]->encode =
229229 vm->pte_encode(px_dma(vm->scratch[0]),
230− I915_CACHE_NONE, PTE_READ_ONLY);
230+ i915_gem_get_pat_index(vm->i915,
231+ I915_CACHE_NONE),
232+ PTE_READ_ONLY);
231233
232234 vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
233235 if (IS_ERR(vm->scratch[1])) {
@@ -278,7 +280,7 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm) · 44 unmodified lines
278280 static void pd_vma_bind(struct i915_address_space *vm,
279281 struct i915_vm_pt_stash *stash,
280282 struct i915_vma_resource *vma_res,
281− enum i915_cache_level cache_level,
283+ unsigned int pat_index,
282284 u32 unused)
283285 {
284286 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
drivers/gpu/drm/i915/gt/gen8_ppgtt.c+61−23
@@ -29,7 +29,7 @@ static u64 gen8_pde_encode(const dma_addr_t addr, · 28 unmodified lines
2929 }
3030
3131 static u64 gen8_pte_encode(dma_addr_t addr,
32− enum i915_cache_level level,
32+ unsigned int pat_index,
3333 u32 flags)
3434 {
3535 gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
@@ -40,7 +40,12 @@ static u64 gen8_pte_encode(dma_addr_t addr, · 4 unmodified lines
4040 if (flags & PTE_LM)
4141 pte |= GEN12_PPGTT_PTE_LM;
4242
43− switch (level) {
43+ /*
44+ * For pre-gen12 platforms pat_index is the same as enum
45+ * i915_cache_level, so the switch-case here is still valid.
46+ * See translation table defined by LEGACY_CACHELEVEL.
47+ */
48+ switch (pat_index) {
4449 case I915_CACHE_NONE:
4550 pte |= PPAT_UNCACHED;
4651 break;
@@ -55,6 +60,33 @@ static u64 gen8_pte_encode(dma_addr_t addr, · 8 unmodified lines
5560 return pte;
5661 }
5762
63+static u64 gen12_pte_encode(dma_addr_t addr,
64+ unsigned int pat_index,
65+ u32 flags)
66+{
67+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
68+
69+ if (unlikely(flags & PTE_READ_ONLY))
70+ pte &= ~GEN8_PAGE_RW;
71+
72+ if (flags & PTE_LM)
73+ pte |= GEN12_PPGTT_PTE_LM;
74+
75+ if (pat_index & BIT(0))
76+ pte |= GEN12_PPGTT_PTE_PAT0;
77+
78+ if (pat_index & BIT(1))
79+ pte |= GEN12_PPGTT_PTE_PAT1;
80+
81+ if (pat_index & BIT(2))
82+ pte |= GEN12_PPGTT_PTE_PAT2;
83+
84+ if (pat_index & BIT(3))
85+ pte |= MTL_PPGTT_PTE_PAT3;
86+
87+ return pte;
88+}
89+
5890 static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
5991 {
6092 struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -423,11 +455,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, · 362 unmodified lines
423455 struct i915_page_directory *pdp,
424456 struct sgt_dma *iter,
425457 u64 idx,
426− enum i915_cache_level cache_level,
458+ unsigned int pat_index,
427459 u32 flags)
428460 {
429461 struct i915_page_directory *pd;
430− const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
462+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, pat_index, flags);
431463 gen8_pte_t *vaddr;
432464
433465 pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
@@ -470,10 +502,10 @@ static void · 36 unmodified lines
470502 xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
471503 struct i915_vma_resource *vma_res,
472504 struct sgt_dma *iter,
473− enum i915_cache_level cache_level,
505+ unsigned int pat_index,
474506 u32 flags)
475507 {
476− const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
508+ const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
477509 unsigned int rem = sg_dma_len(iter->sg);
478510 u64 start = vma_res->start;
479511 u64 end = start + vma_res->vma_size;
@@ -570,6 +602,7 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 90 unmodified lines
570602 }
571603 } while (rem >= page_size && index < max);
572604
605+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
573606 vma_res->page_sizes_gtt |= page_size;
574607 } while (iter->sg && sg_dma_len(iter->sg));
575608 }
@@ -577,10 +610,10 @@ xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm, · 1 unmodified line
577610 static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
578611 struct i915_vma_resource *vma_res,
579612 struct sgt_dma *iter,
580− enum i915_cache_level cache_level,
613+ unsigned int pat_index,
581614 u32 flags)
582615 {
583− const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
616+ const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
584617 unsigned int rem = sg_dma_len(iter->sg);
585618 u64 start = vma_res->start;
586619
@@ -700,17 +733,17 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, · 113 unmodified lines
700733
701734 static void gen8_ppgtt_insert(struct i915_address_space *vm,
702735 struct i915_vma_resource *vma_res,
703− enum i915_cache_level cache_level,
736+ unsigned int pat_index,
704737 u32 flags)
705738 {
706739 struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
707740 struct sgt_dma iter = sgt_dma(vma_res);
708741
709742 if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
710− if (HAS_64K_PAGES(vm->i915))
711− xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, cache_level, flags);
743+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
744+ xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
712745 else
713− gen8_ppgtt_insert_huge(vm, vma_res, &iter, cache_level, flags);
746+ gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
714747 } else {
715748 u64 idx = vma_res->start >> GEN8_PTE_SHIFT;
716749
@@ -719,7 +752,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm, · 2 unmodified lines
719752 gen8_pdp_for_page_index(vm, idx);
720753
721754 idx = gen8_ppgtt_insert_pte(ppgtt, pdp, &iter, idx,
722− cache_level, flags);
755+ pat_index, flags);
723756 } while (idx);
724757
725758 vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
@@ -729,7 +762,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm, · 3 unmodified lines
729762 static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
730763 dma_addr_t addr,
731764 u64 offset,
732− enum i915_cache_level level,
765+ unsigned int pat_index,
733766 u32 flags)
734767 {
735768 u64 idx = offset >> GEN8_PTE_SHIFT;
@@ -743,14 +776,14 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, · 7 unmodified lines
743776 GEM_BUG_ON(pt->is_compact);
744777
745778 vaddr = px_vaddr(pt);
746− vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
779+ vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, pat_index, flags);
747780 drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
748781 }
749782
750783 static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
751784 dma_addr_t addr,
752785 u64 offset,
753− enum i915_cache_level level,
786+ unsigned int pat_index,
754787 u32 flags)
755788 {
756789 u64 idx = offset >> GEN8_PTE_SHIFT;
@@ -773,20 +806,20 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, · 16 unmodified lines
773806 }
774807
775808 vaddr = px_vaddr(pt);
776− vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
809+ vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
777810 }
778811
779812 static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
780813 dma_addr_t addr,
781814 u64 offset,
782− enum i915_cache_level level,
815+ unsigned int pat_index,
783816 u32 flags)
784817 {
785818 if (flags & PTE_LM)
786819 return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
787− level, flags);
820+ pat_index, flags);
788821
789− return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
822+ return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
790823 }
791824
792825 static int gen8_init_scratch(struct i915_address_space *vm)
@@ -820,8 +853,10 @@ static int gen8_init_scratch(struct i915_address_space *vm) · 27 unmodified lines
820853 pte_flags |= PTE_LM;
821854
822855 vm->scratch[0]->encode =
823− gen8_pte_encode(px_dma(vm->scratch[0]),
824− I915_CACHE_NONE, pte_flags);
856+ vm->pte_encode(px_dma(vm->scratch[0]),
857+ i915_gem_get_pat_index(vm->i915,
858+ I915_CACHE_NONE),
859+ pte_flags);
825860
826861 for (i = 1; i <= vm->top; i++) {
827862 struct drm_i915_gem_object *obj;
@@ -963,7 +998,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, · 135 unmodified lines
963998 */
964999 ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
9651000
966− ppgtt->vm.pte_encode = gen8_pte_encode;
1001+ if (GRAPHICS_VER(gt->i915) >= 12)
1002+ ppgtt->vm.pte_encode = gen12_pte_encode;
1003+ else
1004+ ppgtt->vm.pte_encode = gen8_pte_encode;
9671005
9681006 ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
9691007 ppgtt->vm.insert_entries = gen8_ppgtt_insert;
drivers/gpu/drm/i915/gt/gen8_ppgtt.h+1−2
@@ -10,13 +10,12 @@ · 9 unmodified lines
1010
1111 struct i915_address_space;
1212 struct intel_gt;
13−enum i915_cache_level;
1413
1514 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
1615 unsigned long lmem_pt_obj_flags);
1716
1817 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
19− enum i915_cache_level level,
18+ unsigned int pat_index,
2019 u32 flags);
2120
2221 #endif
drivers/gpu/drm/i915/gt/intel_context.c+4−1
@@ -578,10 +578,13 @@ void intel_context_bind_parent_child(struct intel_context *parent, · 577 unmodified lines
578578 child->parallel.parent = parent;
579579 }
580580
581−u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
581+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
582582 {
583583 u64 total, active;
584584
585+ if (ce->ops->update_stats)
586+ ce->ops->update_stats(ce);
587+
585588 total = ce->stats.runtime.total;
586589 if (ce->ops->flags & COPS_RUNTIME_CYCLES)
587590 total *= ce->engine->gt->clock_period_ns;
drivers/gpu/drm/i915/gt/intel_context.h+4−4
@@ -97,7 +97,7 @@ void intel_context_bind_parent_child(struct intel_context *parent, · 96 unmodified lines
9797
9898 /**
9999 * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context
100− * @ce - the context
100+ * @ce: the context
101101 *
102102 * Acquire a lock on the pinned status of the HW context, such that the context
103103 * can neither be bound to the GPU or unbound whilst the lock is held, i.e.
@@ -111,7 +111,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce) · 7 unmodified lines
111111
112112 /**
113113 * intel_context_is_pinned - Reports the 'pinned' status
114− * @ce - the context
114+ * @ce: the context
115115 *
116116 * While in use by the GPU, the context, along with its ring and page
117117 * tables is pinned into memory and the GTT.
@@ -133,7 +133,7 @@ static inline void intel_context_cancel_request(struct intel_context *ce, · 15 unmodified lines
133133
134134 /**
135135 * intel_context_unlock_pinned - Releases the earlier locking of 'pinned' status
136− * @ce - the context
136+ * @ce: the context
137137 *
138138 * Releases the lock earlier acquired by intel_context_unlock_pinned().
139139 */
@@ -375,7 +375,7 @@ intel_context_clear_nopreempt(struct intel_context *ce) · 235 unmodified lines
375375 clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
376376 }
377377
378−u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
378+u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
379379 u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
380380
381381 static inline u64 intel_context_clock(void)
drivers/gpu/drm/i915/gt/intel_context_types.h+2−0
@@ -58,6 +58,8 @@ struct intel_context_ops { · 57 unmodified lines
5858
5959 void (*sched_disable)(struct intel_context *ce);
6060
61+ void (*update_stats)(struct intel_context *ce);
62+
6163 void (*reset)(struct intel_context *ce);
6264 void (*destroy)(struct kref *kref);
6365
drivers/gpu/drm/i915/gt/intel_engine_cs.c+1−1
@@ -1515,7 +1515,7 @@ int intel_engines_init(struct intel_gt *gt) · 1514 unmodified lines
15151515 }
15161516
15171517 /**
1518− * intel_engines_cleanup_common - cleans up the engine state created by
1518+ * intel_engine_cleanup_common - cleans up the engine state created by
15191519 * the common initiailizers.
15201520 * @engine: Engine to cleanup.
15211521 *
drivers/gpu/drm/i915/gt/intel_engine_types.h+1−0
@@ -289,6 +289,7 @@ struct intel_engine_execlists { · 288 unmodified lines
289289 */
290290 u8 csb_head;
291291
292+ /* private: selftest */
292293 I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
293294 };
294295
drivers/gpu/drm/i915/gt/intel_engine_user.c+1−1
@@ -117,7 +117,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) · 116 unmodified lines
117117 disabled |= (I915_SCHEDULER_CAP_ENABLED |
118118 I915_SCHEDULER_CAP_PRIORITY);
119119
120− if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))
120+ if (intel_uc_uses_guc_submission(&engine->gt->uc))
121121 enabled |= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
122122
123123 for (i = 0; i < ARRAY_SIZE(map); i++) {
drivers/gpu/drm/i915/gt/intel_ggtt.c+59−25
@@ -220,8 +220,28 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt) · 219 unmodified lines
220220 }
221221 }
222222
223+static u64 mtl_ggtt_pte_encode(dma_addr_t addr,
224+ unsigned int pat_index,
225+ u32 flags)
226+{
227+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
228+
229+ WARN_ON_ONCE(addr & ~GEN12_GGTT_PTE_ADDR_MASK);
230+
231+ if (flags & PTE_LM)
232+ pte |= GEN12_GGTT_PTE_LM;
233+
234+ if (pat_index & BIT(0))
235+ pte |= MTL_GGTT_PTE_PAT0;
236+
237+ if (pat_index & BIT(1))
238+ pte |= MTL_GGTT_PTE_PAT1;
239+
240+ return pte;
241+}
242+
223243 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
224− enum i915_cache_level level,
244+ unsigned int pat_index,
225245 u32 flags)
226246 {
227247 gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
@@ -240,25 +260,25 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) · 12 unmodified lines
240260 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
241261 dma_addr_t addr,
242262 u64 offset,
243− enum i915_cache_level level,
263+ unsigned int pat_index,
244264 u32 flags)
245265 {
246266 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
247267 gen8_pte_t __iomem *pte =
248268 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
249269
250− gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
270+ gen8_set_pte(pte, ggtt->vm.pte_encode(addr, pat_index, flags));
251271
252272 ggtt->invalidate(ggtt);
253273 }
254274
255275 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
256276 struct i915_vma_resource *vma_res,
257− enum i915_cache_level level,
277+ unsigned int pat_index,
258278 u32 flags)
259279 {
260− const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
261280 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
281+ const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, pat_index, flags);
262282 gen8_pte_t __iomem *gte;
263283 gen8_pte_t __iomem *end;
264284 struct sgt_iter iter;
@@ -315,14 +335,14 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, · 50 unmodified lines
315335 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
316336 dma_addr_t addr,
317337 u64 offset,
318− enum i915_cache_level level,
338+ unsigned int pat_index,
319339 u32 flags)
320340 {
321341 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
322342 gen6_pte_t __iomem *pte =
323343 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
324344
325− iowrite32(vm->pte_encode(addr, level, flags), pte);
345+ iowrite32(vm->pte_encode(addr, pat_index, flags), pte);
326346
327347 ggtt->invalidate(ggtt);
328348 }
@@ -335,7 +355,7 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm, · 6 unmodified lines
335355 */
336356 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
337357 struct i915_vma_resource *vma_res,
338− enum i915_cache_level level,
358+ unsigned int pat_index,
339359 u32 flags)
340360 {
341361 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
@@ -352,7 +372,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, · 10 unmodified lines
352372 iowrite32(vm->scratch[0]->encode, gte++);
353373 end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE;
354374 for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
355− iowrite32(vm->pte_encode(addr, level, flags), gte++);
375+ iowrite32(vm->pte_encode(addr, pat_index, flags), gte++);
356376 GEM_BUG_ON(gte > end);
357377
358378 /* Fill the allocated but "unused" space beyond the end of the buffer */
@@ -387,14 +407,15 @@ struct insert_page { · 28 unmodified lines
387407 struct i915_address_space *vm;
388408 dma_addr_t addr;
389409 u64 offset;
390− enum i915_cache_level level;
410+ unsigned int pat_index;
391411 };
392412
393413 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
394414 {
395415 struct insert_page *arg = _arg;
396416
397− gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
417+ gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset,
418+ arg->pat_index, 0);
398419 bxt_vtd_ggtt_wa(arg->vm);
399420
400421 return 0;
@@ -403,10 +424,10 @@ static int bxt_vtd_ggtt_insert_page__cb(void *_arg) · 2 unmodified lines
403424 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
404425 dma_addr_t addr,
405426 u64 offset,
406− enum i915_cache_level level,
427+ unsigned int pat_index,
407428 u32 unused)
408429 {
409− struct insert_page arg = { vm, addr, offset, level };
430+ struct insert_page arg = { vm, addr, offset, pat_index };
410431
411432 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
412433 }
@@ -414,7 +435,7 @@ static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm, · 1 unmodified line
414435 struct insert_entries {
415436 struct i915_address_space *vm;
416437 struct i915_vma_resource *vma_res;
417− enum i915_cache_level level;
438+ unsigned int pat_index;
418439 u32 flags;
419440 };
420441
@@ -422,7 +443,8 @@ static int bxt_vtd_ggtt_insert_entries__cb(void *_arg) · 1 unmodified line
422443 {
423444 struct insert_entries *arg = _arg;
424445
425− gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
446+ gen8_ggtt_insert_entries(arg->vm, arg->vma_res,
447+ arg->pat_index, arg->flags);
426448 bxt_vtd_ggtt_wa(arg->vm);
427449
428450 return 0;
@@ -430,10 +452,10 @@ static int bxt_vtd_ggtt_insert_entries__cb(void *_arg) · 1 unmodified line
430452
431453 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
432454 struct i915_vma_resource *vma_res,
433− enum i915_cache_level level,
455+ unsigned int pat_index,
434456 u32 flags)
435457 {
436− struct insert_entries arg = { vm, vma_res, level, flags };
458+ struct insert_entries arg = { vm, vma_res, pat_index, flags };
437459
438460 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
439461 }
@@ -462,7 +484,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm, · 22 unmodified lines
462484 void intel_ggtt_bind_vma(struct i915_address_space *vm,
463485 struct i915_vm_pt_stash *stash,
464486 struct i915_vma_resource *vma_res,
465− enum i915_cache_level cache_level,
487+ unsigned int pat_index,
466488 u32 flags)
467489 {
468490 u32 pte_flags;
@@ -479,7 +501,7 @@ void intel_ggtt_bind_vma(struct i915_address_space *vm, · 10 unmodified lines
479501 if (vma_res->bi.lmem)
480502 pte_flags |= PTE_LM;
481503
482− vm->insert_entries(vm, vma_res, cache_level, pte_flags);
504+ vm->insert_entries(vm, vma_res, pat_index, pte_flags);
483505 vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
484506 }
485507
@@ -628,7 +650,7 @@ err: · 142 unmodified lines
628650 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
629651 struct i915_vm_pt_stash *stash,
630652 struct i915_vma_resource *vma_res,
631− enum i915_cache_level cache_level,
653+ unsigned int pat_index,
632654 u32 flags)
633655 {
634656 u32 pte_flags;
@@ -640,10 +662,10 @@ static void aliasing_gtt_bind_vma(struct i915_address_space *vm, · 5 unmodified lines
640662
641663 if (flags & I915_VMA_LOCAL_BIND)
642664 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
643− stash, vma_res, cache_level, flags);
665+ stash, vma_res, pat_index, flags);
644666
645667 if (flags & I915_VMA_GLOBAL_BIND)
646− vm->insert_entries(vm, vma_res, cache_level, pte_flags);
668+ vm->insert_entries(vm, vma_res, pat_index, pte_flags);
647669
648670 vma_res->bound_flags |= flags;
649671 }
@@ -900,7 +922,9 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) · 250 unmodified lines
900922
901923 ggtt->vm.scratch[0]->encode =
902924 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
903− I915_CACHE_NONE, pte_flags);
925+ i915_gem_get_pat_index(i915,
926+ I915_CACHE_NONE),
927+ pte_flags);
904928
905929 return 0;
906930 }
@@ -981,11 +1005,19 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) · 74 unmodified lines
9811005 ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;
9821006 ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
9831007
984− ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
1008+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
1009+ ggtt->vm.pte_encode = mtl_ggtt_pte_encode;
1010+ else
1011+ ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
9851012
9861013 return ggtt_probe_common(ggtt, size);
9871014 }
9881015
1016+/*
1017+ * For pre-gen8 platforms pat_index is the same as enum i915_cache_level,
1018+ * so these PTE encode functions are left with using cache_level.
1019+ * See translation table LEGACY_CACHELEVEL.
1020+ */
9891021 static u64 snb_pte_encode(dma_addr_t addr,
9901022 enum i915_cache_level level,
9911023 u32 flags)
@@ -1266,7 +1298,9 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm) · 274 unmodified lines
12661298 */
12671299 vma->resource->bound_flags = 0;
12681300 vma->ops->bind_vma(vm, NULL, vma->resource,
1269− obj ? obj->cache_level : 0,
1301+ obj ? obj->pat_index :
1302+ i915_gem_get_pat_index(vm->i915,
1303+ I915_CACHE_NONE),
12701304 was_bound);
12711305
12721306 if (obj) { /* only used during resume => exclusive access */
drivers/gpu/drm/i915/gt/intel_gt_irq.c+21−4
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include "intel_uncore.h"
1717 #include "intel_rps.h"
1818 #include "pxp/intel_pxp_irq.h"
19+#include "uc/intel_gsc_proxy.h"
1920
2021 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
2122 {
@@ -82,6 +83,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, · 60 unmodified lines
8283 if (instance == OTHER_GSC_INSTANCE)
8384 return intel_gsc_irq_handler(gt, iir);
8485
86+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
87+ return intel_gsc_proxy_irq_handler(&gt->uc.gsc, iir);
88+
8589 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
8690 instance, iir);
8791 }
@@ -101,7 +105,10 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) · 13 unmodified lines
101105 case VIDEO_ENHANCEMENT_CLASS:
102106 return media_gt;
103107 case OTHER_CLASS:
104− if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
108+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
109+ return media_gt;
110+ if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) &&
111+ HAS_ENGINE(media_gt, GSC0))
105112 return media_gt;
106113 fallthrough;
107114 default:
@@ -257,6 +264,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) · 149 unmodified lines
257264 u32 irqs = GT_RENDER_USER_INTERRUPT;
258265 u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;
259266 u32 gsc_mask = 0;
267+ u32 heci_mask = 0;
260268 u32 dmask;
261269 u32 smask;
262270
@@ -268,10 +276,16 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) · 5 unmodified lines
268276 dmask = irqs << 16 | irqs;
269277 smask = irqs << 16;
270278
271− if (HAS_ENGINE(gt, GSC0))
279+ if (HAS_ENGINE(gt, GSC0)) {
280+ /*
281+ * the heci2 interrupt is enabled via the same register as the
282+ * GSC interrupt, but it has its own mask register.
283+ */
272284 gsc_mask = irqs;
273− else if (HAS_HECI_GSC(gt->i915))
285+ heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/
286+ } else if (HAS_HECI_GSC(gt->i915)) {
274287 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
288+ }
275289
276290 BUILD_BUG_ON(irqs & 0xffff0000);
277291
@@ -281,7 +295,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) · 3 unmodified lines
281295 if (CCS_MASK(gt))
282296 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
283297 if (gsc_mask)
284− intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
298+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask);
285299
286300 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
287301 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -309,6 +323,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) · 21 unmodified lines
309323 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
310324 if (gsc_mask)
311325 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
326+ if (heci_mask)
327+ intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK,
328+ ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask));
312329
313330 if (guc_mask) {
314331 /* the enable bit is common for both GTs but the masks are separate */
drivers/gpu/drm/i915/gt/intel_gt_pm.c+2−2
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf) · 86 unmodified lines
8787
8888 intel_rc6_unpark(&gt->rc6);
8989 intel_rps_unpark(&gt->rps);
90− i915_pmu_gt_unparked(i915);
90+ i915_pmu_gt_unparked(gt);
9191 intel_guc_busyness_unpark(gt);
9292
9393 intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf) · 15 unmodified lines
109109
110110 intel_guc_busyness_park(gt);
111111 i915_vma_parked(gt);
112− i915_pmu_gt_parked(i915);
112+ i915_pmu_gt_parked(gt);
113113 intel_rps_park(&gt->rps);
114114 intel_rc6_park(&gt->rc6);
115115
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c+4−1
@@ -539,7 +539,10 @@ static bool rps_eval(void *data) · 538 unmodified lines
539539 {
540540 struct intel_gt *gt = data;
541541
542− return HAS_RPS(gt->i915);
542+ if (intel_guc_slpc_is_used(&gt->uc.guc))
543+ return false;
544+ else
545+ return HAS_RPS(gt->i915);
543546 }
544547
545548 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
drivers/gpu/drm/i915/gt/intel_gt_regs.h+13−1
@@ -357,7 +357,11 @@ · 356 unmodified lines
357357 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
358358
359359 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
360−#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4)
360+#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
361+ 0x4800, 0x4804, \
362+ 0x4848, 0x484c)
363+#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
364+#define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index))
361365
362366 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
363367 #define XEHP_TILE_LMEM_RANGE_SHIFT 8
@@ -526,6 +530,11 @@ · 162 unmodified lines
526530
527531 #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
528532
533+#define GEN12_SQCNT1 _MMIO(0x8718)
534+#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
535+#define GEN12_SQCNT1_OABPC REG_BIT(29)
536+#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
537+
529538 #define XEHP_SQCM MCR_REG(0x8724)
530539 #define EN_32B_ACCESS REG_BIT(30)
531540
@@ -1588,6 +1597,7 @@ · 1056 unmodified lines
15881597
15891598 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
15901599 #define GEN11_CSME (31)
1600+#define GEN12_HECI_2 (30)
15911601 #define GEN11_GUNIT (28)
15921602 #define GEN11_GUC (25)
15931603 #define MTL_MGUC (24)
@@ -1629,6 +1639,7 @@ · 35 unmodified lines
16291639 /* irq instances for OTHER_CLASS */
16301640 #define OTHER_GUC_INSTANCE 0
16311641 #define OTHER_GTPM_INSTANCE 1
1642+#define OTHER_GSC_HECI_2_INSTANCE 3
16321643 #define OTHER_KCR_INSTANCE 4
16331644 #define OTHER_GSC_INSTANCE 6
16341645 #define OTHER_MEDIA_GUC_INSTANCE 16
@@ -1644,6 +1655,7 @@ · 9 unmodified lines
16441655 #define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
16451656 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
16461657 #define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
1658+#define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4)
16471659 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
16481660 #define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */
16491661 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c+35−0
@@ -451,6 +451,33 @@ static ssize_t punit_req_freq_mhz_show(struct kobject *kobj, · 450 unmodified lines
451451 return sysfs_emit(buff, "%u\n", preq);
452452 }
453453
454+static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
455+ struct kobj_attribute *attr,
456+ char *buff)
457+{
458+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
459+ struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
460+
461+ return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
462+}
463+
464+static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
465+ struct kobj_attribute *attr,
466+ const char *buff, size_t count)
467+{
468+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
469+ struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
470+ int err;
471+ u32 val;
472+
473+ err = kstrtou32(buff, 0, &val);
474+ if (err)
475+ return err;
476+
477+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
478+ return err ?: count;
479+}
480+
454481 struct intel_gt_bool_throttle_attr {
455482 struct attribute attr;
456483 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
@@ -663,6 +690,8 @@ static struct kobj_attribute attr_media_freq_factor_scale = · 206 unmodified lines
663690 INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
664691 INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
665692
693+INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
694+
666695 static const struct attribute *media_perf_power_attrs[] = {
667696 &attr_media_freq_factor.attr,
668697 &attr_media_freq_factor_scale.attr,
@@ -744,6 +773,12 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj) · 75 unmodified lines
744773 if (ret)
745774 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
746775
776+ if (intel_uc_uses_guc_slpc(&gt->uc)) {
777+ ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
778+ if (ret)
779+ gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
780+ }
781+
747782 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
748783 ret = sysfs_create_files(kobj, throttle_reason_attrs);
749784 if (ret)
drivers/gpu/drm/i915/gt/intel_gtt.c+46−1
@@ -468,6 +468,44 @@ void gtt_write_workarounds(struct intel_gt *gt) · 467 unmodified lines
468468 }
469469 }
470470
471+static void xelpmp_setup_private_ppat(struct intel_uncore *uncore)
472+{
473+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(0),
474+ MTL_PPAT_L4_0_WB);
475+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(1),
476+ MTL_PPAT_L4_1_WT);
477+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(2),
478+ MTL_PPAT_L4_3_UC);
479+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(3),
480+ MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
481+ intel_uncore_write(uncore, XELPMP_PAT_INDEX(4),
482+ MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
483+
484+ /*
485+ * Remaining PAT entries are left at the hardware-default
486+ * fully-cached setting
487+ */
488+}
489+
490+static void xelpg_setup_private_ppat(struct intel_gt *gt)
491+{
492+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
493+ MTL_PPAT_L4_0_WB);
494+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
495+ MTL_PPAT_L4_1_WT);
496+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
497+ MTL_PPAT_L4_3_UC);
498+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
499+ MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
500+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
501+ MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
502+
503+ /*
504+ * Remaining PAT entries are left at the hardware-default
505+ * fully-cached setting
506+ */
507+}
508+
471509 static void tgl_setup_private_ppat(struct intel_uncore *uncore)
472510 {
473511 /* TGL doesn't support LLC or AGE settings */
@@ -603,7 +641,14 @@ void setup_private_pat(struct intel_gt *gt) · 129 unmodified lines
603641
604642 GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
605643
606− if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
644+ if (gt->type == GT_MEDIA) {
645+ xelpmp_setup_private_ppat(gt->uncore);
646+ return;
647+ }
648+
649+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
650+ xelpg_setup_private_ppat(gt);
651+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
607652 xehp_setup_private_ppat(gt);
608653 else if (GRAPHICS_VER(i915) >= 12)
609654 tgl_setup_private_ppat(uncore);
drivers/gpu/drm/i915/gt/intel_gtt.h+25−11
@@ -88,9 +88,17 @@ typedef u64 gen8_pte_t; · 87 unmodified lines
8888 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
8989 #define BYT_PTE_WRITEABLE REG_BIT(1)
9090
91+#define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
9192 #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
93+#define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)
94+#define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)
95+#define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)
9296
93−#define GEN12_GGTT_PTE_LM BIT_ULL(1)
97+#define GEN12_GGTT_PTE_LM BIT_ULL(1)
98+#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
99+#define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
100+#define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12)
101+#define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52)
94102
95103 #define GEN12_PDE_64K BIT(6)
96104 #define GEN12_PTE_PS64 BIT(8)
@@ -147,7 +155,13 @@ typedef u64 gen8_pte_t; · 50 unmodified lines
147155 #define GEN8_PDE_IPS_64K BIT(11)
148156 #define GEN8_PDE_PS_2M BIT(7)
149157
150−enum i915_cache_level;
158+#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
159+#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
160+#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
161+#define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
162+#define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
163+#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
164+#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
151165
152166 struct drm_i915_gem_object;
153167 struct i915_fence_reg;
@@ -216,7 +230,7 @@ struct i915_vma_ops { · 62 unmodified lines
216230 void (*bind_vma)(struct i915_address_space *vm,
217231 struct i915_vm_pt_stash *stash,
218232 struct i915_vma_resource *vma_res,
219− enum i915_cache_level cache_level,
233+ unsigned int pat_index,
220234 u32 flags);
221235 /*
222236 * Unmap an object from an address space. This usually consists of
@@ -288,7 +302,7 @@ struct i915_address_space { · 65 unmodified lines
288302 (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
289303
290304 u64 (*pte_encode)(dma_addr_t addr,
291− enum i915_cache_level level,
305+ unsigned int pat_index,
292306 u32 flags); /* Create a valid PTE */
293307 #define PTE_READ_ONLY BIT(0)
294308 #define PTE_LM BIT(1)
@@ -303,20 +317,20 @@ struct i915_address_space { · 8 unmodified lines
303317 void (*insert_page)(struct i915_address_space *vm,
304318 dma_addr_t addr,
305319 u64 offset,
306− enum i915_cache_level cache_level,
320+ unsigned int pat_index,
307321 u32 flags);
308322 void (*insert_entries)(struct i915_address_space *vm,
309323 struct i915_vma_resource *vma_res,
310− enum i915_cache_level cache_level,
324+ unsigned int pat_index,
311325 u32 flags);
312326 void (*raw_insert_page)(struct i915_address_space *vm,
313327 dma_addr_t addr,
314328 u64 offset,
315− enum i915_cache_level cache_level,
329+ unsigned int pat_index,
316330 u32 flags);
317331 void (*raw_insert_entries)(struct i915_address_space *vm,
318332 struct i915_vma_resource *vma_res,
319− enum i915_cache_level cache_level,
333+ unsigned int pat_index,
320334 u32 flags);
321335 void (*cleanup)(struct i915_address_space *vm);
322336
@@ -493,7 +507,7 @@ static inline void i915_vm_put(struct i915_address_space *vm) · 170 unmodified lines
493507
494508 /**
495509 * i915_vm_resv_put - Release a reference on the vm's reservation lock
496− * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get()
510+ * @vm: The vm whose reservation lock reference we want to release
497511 */
498512 static inline void i915_vm_resv_put(struct i915_address_space *vm)
499513 {
@@ -563,7 +577,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, · 63 unmodified lines
563577 void intel_ggtt_bind_vma(struct i915_address_space *vm,
564578 struct i915_vm_pt_stash *stash,
565579 struct i915_vma_resource *vma_res,
566− enum i915_cache_level cache_level,
580+ unsigned int pat_index,
567581 u32 flags);
568582 void intel_ggtt_unbind_vma(struct i915_address_space *vm,
569583 struct i915_vma_resource *vma_res);
@@ -641,7 +655,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); · 71 unmodified lines
641655 void ppgtt_bind_vma(struct i915_address_space *vm,
642656 struct i915_vm_pt_stash *stash,
643657 struct i915_vma_resource *vma_res,
644− enum i915_cache_level cache_level,
658+ unsigned int pat_index,
645659 u32 flags);
646660 void ppgtt_unbind_vma(struct i915_address_space *vm,
647661 struct i915_vma_resource *vma_res);
drivers/gpu/drm/i915/gt/intel_lrc.c+3−1
@@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) · 1369 unmodified lines
13701370 cs, GEN12_GFX_CCS_AUX_NV);
13711371
13721372 /* Wa_16014892111 */
1373− if (IS_DG2(ce->engine->i915))
1373+ if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
1374+ IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
1375+ IS_DG2(ce->engine->i915))
13741376 cs = dg2_emit_draw_watermark_setting(cs);
13751377
13761378 return cs;
drivers/gpu/drm/i915/gt/intel_migrate.c+28−23
@@ -45,7 +45,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm, · 44 unmodified lines
4545 * Insert a dummy PTE into every PT that will map to LMEM to ensure
4646 * we have a correctly setup PDE structure for later use.
4747 */
48− vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
48+ vm->insert_page(vm, 0, d->offset,
49+ i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
50+ PTE_LM);
4951 GEM_BUG_ON(!pt->is_compact);
5052 d->offset += SZ_2M;
5153 }
@@ -63,7 +65,9 @@ static void xehpsdv_insert_pte(struct i915_address_space *vm, · 11 unmodified lines
6365 * alignment is 64K underneath for the pt, and we are careful
6466 * not to access the space in the void.
6567 */
66− vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
68+ vm->insert_page(vm, px_dma(pt), d->offset,
69+ i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
70+ PTE_LM);
6771 d->offset += SZ_64K;
6872 }
6973
@@ -73,7 +77,8 @@ static void insert_pte(struct i915_address_space *vm, · 3 unmodified lines
7377 {
7478 struct insert_pte_data *d = data;
7579
76− vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
80+ vm->insert_page(vm, px_dma(pt), d->offset,
81+ i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE),
7782 i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
7883 d->offset += PAGE_SIZE;
7984 }
@@ -356,13 +361,13 @@ static int max_pte_pkt_size(struct i915_request *rq, int pkt) · 276 unmodified lines
356361
357362 static int emit_pte(struct i915_request *rq,
358363 struct sgt_dma *it,
359− enum i915_cache_level cache_level,
364+ unsigned int pat_index,
360365 bool is_lmem,
361366 u64 offset,
362367 int length)
363368 {
364369 bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
365− const u64 encode = rq->context->vm->pte_encode(0, cache_level,
370+ const u64 encode = rq->context->vm->pte_encode(0, pat_index,
366371 is_lmem ? PTE_LM : 0);
367372 struct intel_ring *ring = rq->ring;
368373 int pkt, dword_length;
@@ -673,17 +678,17 @@ int · 304 unmodified lines
673678 intel_context_migrate_copy(struct intel_context *ce,
674679 const struct i915_deps *deps,
675680 struct scatterlist *src,
676− enum i915_cache_level src_cache_level,
681+ unsigned int src_pat_index,
677682 bool src_is_lmem,
678683 struct scatterlist *dst,
679− enum i915_cache_level dst_cache_level,
684+ unsigned int dst_pat_index,
680685 bool dst_is_lmem,
681686 struct i915_request **out)
682687 {
683688 struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst), it_ccs;
684689 struct drm_i915_private *i915 = ce->engine->i915;
685690 u64 ccs_bytes_to_cpy = 0, bytes_to_cpy;
686− enum i915_cache_level ccs_cache_level;
691+ unsigned int ccs_pat_index;
687692 u32 src_offset, dst_offset;
688693 u8 src_access, dst_access;
689694 struct i915_request *rq;
@@ -707,12 +712,12 @@ intel_context_migrate_copy(struct intel_context *ce, · 17 unmodified lines
707712 dst_sz = scatter_list_length(dst);
708713 if (src_is_lmem) {
709714 it_ccs = it_dst;
710− ccs_cache_level = dst_cache_level;
715+ ccs_pat_index = dst_pat_index;
711716 ccs_is_src = false;
712717 } else if (dst_is_lmem) {
713718 bytes_to_cpy = dst_sz;
714719 it_ccs = it_src;
715− ccs_cache_level = src_cache_level;
720+ ccs_pat_index = src_pat_index;
716721 ccs_is_src = true;
717722 }
718723
@@ -773,7 +778,7 @@ intel_context_migrate_copy(struct intel_context *ce, · 54 unmodified lines
773778 src_sz = calculate_chunk_sz(i915, src_is_lmem,
774779 bytes_to_cpy, ccs_bytes_to_cpy);
775780
776− len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem,
781+ len = emit_pte(rq, &it_src, src_pat_index, src_is_lmem,
777782 src_offset, src_sz);
778783 if (!len) {
779784 err = -EINVAL;
@@ -784,7 +789,7 @@ intel_context_migrate_copy(struct intel_context *ce, · 4 unmodified lines
784789 goto out_rq;
785790 }
786791
787− err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
792+ err = emit_pte(rq, &it_dst, dst_pat_index, dst_is_lmem,
788793 dst_offset, len);
789794 if (err < 0)
790795 goto out_rq;
@@ -811,7 +816,7 @@ intel_context_migrate_copy(struct intel_context *ce, · 20 unmodified lines
811816 goto out_rq;
812817
813818 ccs_sz = GET_CCS_BYTES(i915, len);
814− err = emit_pte(rq, &it_ccs, ccs_cache_level, false,
819+ err = emit_pte(rq, &it_ccs, ccs_pat_index, false,
815820 ccs_is_src ? src_offset : dst_offset,
816821 ccs_sz);
817822 if (err < 0)
@@ -920,7 +925,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size, · 102 unmodified lines
920925
921926 GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
922927
923− if (HAS_FLAT_CCS(i915) && ver >= 12)
928+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
924929 ring_sz = XY_FAST_COLOR_BLT_DW;
925930 else if (ver >= 8)
926931 ring_sz = 8;
@@ -931,7 +936,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size, · 4 unmodified lines
931936 if (IS_ERR(cs))
932937 return PTR_ERR(cs);
933938
934− if (HAS_FLAT_CCS(i915) && ver >= 12) {
939+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
935940 *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
936941 (XY_FAST_COLOR_BLT_DW - 2);
937942 *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
@@ -979,7 +984,7 @@ int · 41 unmodified lines
979984 intel_context_migrate_clear(struct intel_context *ce,
980985 const struct i915_deps *deps,
981986 struct scatterlist *sg,
982− enum i915_cache_level cache_level,
987+ unsigned int pat_index,
983988 bool is_lmem,
984989 u32 value,
985990 struct i915_request **out)
@@ -1027,7 +1032,7 @@ intel_context_migrate_clear(struct intel_context *ce, · 41 unmodified lines
10271032 if (err)
10281033 goto out_rq;
10291034
1030− len = emit_pte(rq, &it, cache_level, is_lmem, offset, CHUNK_SZ);
1035+ len = emit_pte(rq, &it, pat_index, is_lmem, offset, CHUNK_SZ);
10311036 if (len <= 0) {
10321037 err = len;
10331038 goto out_rq;
@@ -1074,10 +1079,10 @@ int intel_migrate_copy(struct intel_migrate *m, · 40 unmodified lines
10741079 struct i915_gem_ww_ctx *ww,
10751080 const struct i915_deps *deps,
10761081 struct scatterlist *src,
1077− enum i915_cache_level src_cache_level,
1082+ unsigned int src_pat_index,
10781083 bool src_is_lmem,
10791084 struct scatterlist *dst,
1080− enum i915_cache_level dst_cache_level,
1085+ unsigned int dst_pat_index,
10811086 bool dst_is_lmem,
10821087 struct i915_request **out)
10831088 {
@@ -1098,8 +1103,8 @@ int intel_migrate_copy(struct intel_migrate *m, · 14 unmodified lines
10981103 goto out;
10991104
11001105 err = intel_context_migrate_copy(ce, deps,
1101− src, src_cache_level, src_is_lmem,
1102− dst, dst_cache_level, dst_is_lmem,
1106+ src, src_pat_index, src_is_lmem,
1107+ dst, dst_pat_index, dst_is_lmem,
11031108 out);
11041109
11051110 intel_context_unpin(ce);
@@ -1113,7 +1118,7 @@ intel_migrate_clear(struct intel_migrate *m, · 7 unmodified lines
11131118 struct i915_gem_ww_ctx *ww,
11141119 const struct i915_deps *deps,
11151120 struct scatterlist *sg,
1116− enum i915_cache_level cache_level,
1121+ unsigned int pat_index,
11171122 bool is_lmem,
11181123 u32 value,
11191124 struct i915_request **out)
@@ -1134,7 +1139,7 @@ intel_migrate_clear(struct intel_migrate *m, · 14 unmodified lines
11341139 if (err)
11351140 goto out;
11361141
1137− err = intel_context_migrate_clear(ce, deps, sg, cache_level,
1142+ err = intel_context_migrate_clear(ce, deps, sg, pat_index,
11381143 is_lmem, value, out);
11391144
11401145 intel_context_unpin(ce);
drivers/gpu/drm/i915/gt/intel_migrate.h+6−7
@@ -16,7 +16,6 @@ struct i915_request; · 15 unmodified lines
1616 struct i915_gem_ww_ctx;
1717 struct intel_gt;
1818 struct scatterlist;
19−enum i915_cache_level;
2019
2120 int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt);
2221
@@ -26,20 +25,20 @@ int intel_migrate_copy(struct intel_migrate *m, · 3 unmodified lines
2625 struct i915_gem_ww_ctx *ww,
2726 const struct i915_deps *deps,
2827 struct scatterlist *src,
29− enum i915_cache_level src_cache_level,
28+ unsigned int src_pat_index,
3029 bool src_is_lmem,
3130 struct scatterlist *dst,
32− enum i915_cache_level dst_cache_level,
31+ unsigned int dst_pat_index,
3332 bool dst_is_lmem,
3433 struct i915_request **out);
3534
3635 int intel_context_migrate_copy(struct intel_context *ce,
3736 const struct i915_deps *deps,
3837 struct scatterlist *src,
39− enum i915_cache_level src_cache_level,
38+ unsigned int src_pat_index,
4039 bool src_is_lmem,
4140 struct scatterlist *dst,
42− enum i915_cache_level dst_cache_level,
41+ unsigned int dst_pat_index,
4342 bool dst_is_lmem,
4443 struct i915_request **out);
4544
@@ -48,7 +47,7 @@ intel_migrate_clear(struct intel_migrate *m, · 2 unmodified lines
4847 struct i915_gem_ww_ctx *ww,
4948 const struct i915_deps *deps,
5049 struct scatterlist *sg,
51− enum i915_cache_level cache_level,
50+ unsigned int pat_index,
5251 bool is_lmem,
5352 u32 value,
5453 struct i915_request **out);
@@ -56,7 +55,7 @@ int · 1 unmodified line
5655 intel_context_migrate_clear(struct intel_context *ce,
5756 const struct i915_deps *deps,
5857 struct scatterlist *sg,
59− enum i915_cache_level cache_level,
58+ unsigned int pat_index,
6059 bool is_lmem,
6160 u32 value,
6261 struct i915_request **out);
drivers/gpu/drm/i915/gt/intel_mocs.c+69−1
@@ -40,6 +40,10 @@ struct drm_i915_mocs_table { · 39 unmodified lines
4040 #define LE_COS(value) ((value) << 15)
4141 #define LE_SSE(value) ((value) << 17)
4242
43+/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
44+#define _L4_CACHEABILITY(value) ((value) << 2)
45+#define IG_PAT(value) ((value) << 8)
46+
4347 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
4448 #define L3_ESC(value) ((value) << 0)
4549 #define L3_SCC(value) ((value) << 1)
@@ -50,6 +54,7 @@ struct drm_i915_mocs_table { · 4 unmodified lines
5054 /* Helper defines */
5155 #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
5256 #define PVC_NUM_MOCS_ENTRIES 3
57+#define MTL_NUM_MOCS_ENTRIES 16
5358
5459 /* (e)LLC caching options */
5560 /*
@@ -73,6 +78,12 @@ struct drm_i915_mocs_table { · 17 unmodified lines
7378 #define L3_2_RESERVED _L3_CACHEABILITY(2)
7479 #define L3_3_WB _L3_CACHEABILITY(3)
7580
81+/* L4 caching options */
82+#define L4_0_WB _L4_CACHEABILITY(0)
83+#define L4_1_WT _L4_CACHEABILITY(1)
84+#define L4_2_RESERVED _L4_CACHEABILITY(2)
85+#define L4_3_UC _L4_CACHEABILITY(3)
86+
7687 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
7788 [__idx] = { \
7889 .control_value = __control_value, \
@@ -416,6 +427,57 @@ static const struct drm_i915_mocs_entry pvc_mocs_table[] = { · 337 unmodified lines
416427 MOCS_ENTRY(2, 0, L3_3_WB),
417428 };
418429
430+static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
431+ /* Error - Reserved for Non-Use */
432+ MOCS_ENTRY(0,
433+ IG_PAT(0),
434+ L3_LKUP(1) | L3_3_WB),
435+ /* Cached - L3 + L4 */
436+ MOCS_ENTRY(1,
437+ IG_PAT(1),
438+ L3_LKUP(1) | L3_3_WB),
439+ /* L4 - GO:L3 */
440+ MOCS_ENTRY(2,
441+ IG_PAT(1),
442+ L3_LKUP(1) | L3_1_UC),
443+ /* Uncached - GO:L3 */
444+ MOCS_ENTRY(3,
445+ IG_PAT(1) | L4_3_UC,
446+ L3_LKUP(1) | L3_1_UC),
447+ /* L4 - GO:Mem */
448+ MOCS_ENTRY(4,
449+ IG_PAT(1),
450+ L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
451+ /* Uncached - GO:Mem */
452+ MOCS_ENTRY(5,
453+ IG_PAT(1) | L4_3_UC,
454+ L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
455+ /* L4 - L3:NoLKUP; GO:L3 */
456+ MOCS_ENTRY(6,
457+ IG_PAT(1),
458+ L3_1_UC),
459+ /* Uncached - L3:NoLKUP; GO:L3 */
460+ MOCS_ENTRY(7,
461+ IG_PAT(1) | L4_3_UC,
462+ L3_1_UC),
463+ /* L4 - L3:NoLKUP; GO:Mem */
464+ MOCS_ENTRY(8,
465+ IG_PAT(1),
466+ L3_GLBGO(1) | L3_1_UC),
467+ /* Uncached - L3:NoLKUP; GO:Mem */
468+ MOCS_ENTRY(9,
469+ IG_PAT(1) | L4_3_UC,
470+ L3_GLBGO(1) | L3_1_UC),
471+ /* Display - L3; L4:WT */
472+ MOCS_ENTRY(14,
473+ IG_PAT(1) | L4_1_WT,
474+ L3_LKUP(1) | L3_3_WB),
475+ /* CCS - Non-Displayable */
476+ MOCS_ENTRY(15,
477+ IG_PAT(1),
478+ L3_GLBGO(1) | L3_1_UC),
479+};
480+
419481 enum {
420482 HAS_GLOBAL_MOCS = BIT(0),
421483 HAS_ENGINE_MOCS = BIT(1),
@@ -445,7 +507,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, · 23 unmodified lines
445507 memset(table, 0, sizeof(struct drm_i915_mocs_table));
446508
447509 table->unused_entries_index = I915_MOCS_PTE;
448− if (IS_PONTEVECCHIO(i915)) {
510+ if (IS_METEORLAKE(i915)) {
511+ table->size = ARRAY_SIZE(mtl_mocs_table);
512+ table->table = mtl_mocs_table;
513+ table->n_entries = MTL_NUM_MOCS_ENTRIES;
514+ table->uc_index = 9;
515+ table->unused_entries_index = 1;
516+ } else if (IS_PONTEVECCHIO(i915)) {
449517 table->size = ARRAY_SIZE(pvc_mocs_table);
450518 table->table = pvc_mocs_table;
451519 table->n_entries = PVC_NUM_MOCS_ENTRIES;
drivers/gpu/drm/i915/gt/intel_ppgtt.c+2−2
@@ -181,7 +181,7 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, · 180 unmodified lines
181181 void ppgtt_bind_vma(struct i915_address_space *vm,
182182 struct i915_vm_pt_stash *stash,
183183 struct i915_vma_resource *vma_res,
184− enum i915_cache_level cache_level,
184+ unsigned int pat_index,
185185 u32 flags)
186186 {
187187 u32 pte_flags;
@@ -199,7 +199,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm, · 11 unmodified lines
199199 if (vma_res->bi.lmem)
200200 pte_flags |= PTE_LM;
201201
202− vm->insert_entries(vm, vma_res, cache_level, pte_flags);
202+ vm->insert_entries(vm, vma_res, pat_index, pte_flags);
203203 wmb();
204204 }
205205
drivers/gpu/drm/i915/gt/intel_rc6.c+84−83
@@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) · 52 unmodified lines
5353 return rc6_to_gt(rc)->i915;
5454 }
5555
56−static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
57−{
58− intel_uncore_write_fw(uncore, reg, val);
59−}
60−
6156 static void gen11_rc6_enable(struct intel_rc6 *rc6)
6257 {
6358 struct intel_gt *gt = rc6_to_gt(rc6);
@@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 8 unmodified lines
7267 */
7368 if (!intel_uc_uses_guc_rc(&gt->uc)) {
7469 /* 2b: Program RC6 thresholds.*/
75− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
76− set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
70+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
71+ intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
7772
78− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
79− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
73+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
74+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
8075 for_each_engine(engine, rc6_to_gt(rc6), id)
81− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
76+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
8277
83− set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
78+ intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
8479
85− set(uncore, GEN6_RC_SLEEP, 0);
80+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
8681
87− set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
82+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
8883 }
8984
9085 /*
@@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 14 unmodified lines
105100 * Broadwell+, To be conservative, we want to factor in a context
106101 * switch on top (due to ksoftirqd).
107102 */
108− set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
109− set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
103+ intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
104+ intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
110105
111106 /* 3a: Enable RC6
112107 *
@@ -122,8 +117,14 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 9 unmodified lines
122117 GEN6_RC_CTL_RC6_ENABLE |
123118 GEN6_RC_CTL_EI_MODE(1);
124119
125− /* Wa_16011777198 - Render powergating must remain disabled */
126− if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
120+ /*
121+ * Wa_16011777198 and BSpec 52698 - Render powergating must be off.
122+ * FIXME BSpec is outdated, disabling powergating for MTL is just
123+ * temporary wa and should be removed after fixing real cause
124+ * of forcewake timeouts.
125+ */
126+ if (IS_METEORLAKE(gt->i915) ||
127+ IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
127128 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
128129 pg_enable =
129130 GEN9_MEDIA_PG_ENABLE |
@@ -141,7 +142,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) · 11 unmodified lines
141142 VDN_MFX_POWERGATE_ENABLE(i));
142143 }
143144
144− set(uncore, GEN9_PG_ENABLE, pg_enable);
145+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
145146 }
146147
147148 static void gen9_rc6_enable(struct intel_rc6 *rc6)
@@ -152,26 +153,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 4 unmodified lines
152153
153154 /* 2b: Program RC6 thresholds.*/
154155 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
155− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
156− set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
156+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
157+ intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
157158 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
158159 /*
159160 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
160161 * when CPG is enabled
161162 */
162− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
163+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
163164 } else {
164− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
165+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
165166 }
166167
167− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
168− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
168+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
169+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
169170 for_each_engine(engine, rc6_to_gt(rc6), id)
170− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
171+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
171172
172− set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
173+ intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
173174
174− set(uncore, GEN6_RC_SLEEP, 0);
175+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
175176
176177 /*
177178 * 2c: Program Coarse Power Gating Policies.
@@ -194,11 +195,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 16 unmodified lines
194195 * conservative, we have to factor in a context switch on top (due
195196 * to ksoftirqd).
196197 */
197− set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
198− set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
198+ intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
199+ intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
199200
200201 /* 3a: Enable RC6 */
201− set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
202+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
202203
203204 rc6->ctl_enable =
204205 GEN6_RC_CTL_HW_ENABLE |
@@ -210,8 +211,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) · 5 unmodified lines
210211 * - Render/Media PG need to be disabled with RC6.
211212 */
212213 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
213− set(uncore, GEN9_PG_ENABLE,
214− GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
214+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
215+ GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
215216 }
216217
217218 static void gen8_rc6_enable(struct intel_rc6 *rc6)
@@ -221,13 +222,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6) · 3 unmodified lines
221222 enum intel_engine_id id;
222223
223224 /* 2b: Program RC6 thresholds.*/
224− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
225− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
226− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
225+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
226+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
227+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
227228 for_each_engine(engine, rc6_to_gt(rc6), id)
228− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
229− set(uncore, GEN6_RC_SLEEP, 0);
230− set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
229+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
230+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
231+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
231232
232233 /* 3: Enable RC6 */
233234 rc6->ctl_enable =
@@ -245,20 +246,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) · 11 unmodified lines
245246 u32 rc6vids, rc6_mask;
246247 int ret;
247248
248− set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
249− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
250− set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
251− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
252− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
249+ intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
250+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
251+ intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
252+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
253+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
253254
254255 for_each_engine(engine, rc6_to_gt(rc6), id)
255− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
256+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
256257
257− set(uncore, GEN6_RC_SLEEP, 0);
258− set(uncore, GEN6_RC1e_THRESHOLD, 1000);
259− set(uncore, GEN6_RC6_THRESHOLD, 50000);
260− set(uncore, GEN6_RC6p_THRESHOLD, 150000);
261− set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
258+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
259+ intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
260+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
261+ intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
262+ intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
262263
263264 /* We don't use those on Haswell */
264265 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -372,22 +373,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) · 107 unmodified lines
372373 enum intel_engine_id id;
373374
374375 /* 2a: Program RC6 thresholds.*/
375− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
376− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
377− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
376+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
377+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
378+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
378379
379380 for_each_engine(engine, rc6_to_gt(rc6), id)
380− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
381− set(uncore, GEN6_RC_SLEEP, 0);
381+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
382+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
382383
383384 /* TO threshold set to 500 us (0x186 * 1.28 us) */
384− set(uncore, GEN6_RC6_THRESHOLD, 0x186);
385+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
385386
386387 /* Allows RC6 residency counter to work */
387− set(uncore, VLV_COUNTER_CONTROL,
388− _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
389− VLV_MEDIA_RC6_COUNT_EN |
390− VLV_RENDER_RC6_COUNT_EN));
388+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
389+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
390+ VLV_MEDIA_RC6_COUNT_EN |
391+ VLV_RENDER_RC6_COUNT_EN));
391392
392393 /* 3: Enable RC6 */
393394 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
@@ -399,22 +400,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) · 5 unmodified lines
399400 struct intel_engine_cs *engine;
400401 enum intel_engine_id id;
401402
402− set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
403− set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
404− set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
403+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
404+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
405+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
405406
406407 for_each_engine(engine, rc6_to_gt(rc6), id)
407− set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
408+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
408409
409− set(uncore, GEN6_RC6_THRESHOLD, 0x557);
410+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
410411
411412 /* Allows RC6 residency counter to work */
412− set(uncore, VLV_COUNTER_CONTROL,
413− _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
414− VLV_MEDIA_RC0_COUNT_EN |
415− VLV_RENDER_RC0_COUNT_EN |
416− VLV_MEDIA_RC6_COUNT_EN |
417− VLV_RENDER_RC6_COUNT_EN));
413+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
414+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
415+ VLV_MEDIA_RC0_COUNT_EN |
416+ VLV_RENDER_RC0_COUNT_EN |
417+ VLV_MEDIA_RC6_COUNT_EN |
418+ VLV_RENDER_RC6_COUNT_EN));
418419
419420 rc6->ctl_enable =
420421 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
@@ -575,9 +576,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) · 154 unmodified lines
575576
576577 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
577578 if (GRAPHICS_VER(i915) >= 9)
578− set(uncore, GEN9_PG_ENABLE, 0);
579− set(uncore, GEN6_RC_CONTROL, 0);
580− set(uncore, GEN6_RC_STATE, 0);
579+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
580+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
581+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
581582 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
582583 }
583584
@@ -684,7 +685,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6) · 100 unmodified lines
684685 return;
685686
686687 /* Restore HW timers for automatic RC6 entry while busy */
687− set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
688+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
688689 }
689690
690691 void intel_rc6_park(struct intel_rc6 *rc6)
@@ -704,7 +705,7 @@ void intel_rc6_park(struct intel_rc6 *rc6) · 13 unmodified lines
704705 return;
705706
706707 /* Turn off the HW timers and go directly to rc6 */
707− set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
708+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
708709
709710 if (HAS_RC6pp(rc6_to_i915(rc6)))
710711 target = 0x6; /* deepest rc6 */
@@ -712,7 +713,7 @@ void intel_rc6_park(struct intel_rc6 *rc6) · 1 unmodified line
712713 target = 0x5; /* deep rc6 */
713714 else
714715 target = 0x4; /* normal rc6 */
715− set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
716+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
716717 }
717718
718719 void intel_rc6_disable(struct intel_rc6 *rc6)
@@ -735,7 +736,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6) · 16 unmodified lines
735736
736737 /* We want the BIOS C6 state preserved across loads for MTL */
737738 if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
738− set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
739+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
739740
740741 pctx = fetch_and_zero(&rc6->pctx);
741742 if (pctx)
@@ -766,18 +767,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) · 24 unmodified lines
766767 * before we have set the default VLV_COUNTER_CONTROL value. So always
767768 * set the high bit to be safe.
768769 */
769− set(uncore, VLV_COUNTER_CONTROL,
770− _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
770+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
771+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
771772 upper = intel_uncore_read_fw(uncore, reg);
772773 do {
773774 tmp = upper;
774775
775− set(uncore, VLV_COUNTER_CONTROL,
776− _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
776+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
777+ _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
777778 lower = intel_uncore_read_fw(uncore, reg);
778779
779− set(uncore, VLV_COUNTER_CONTROL,
780− _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
780+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
781+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
781782 upper = intel_uncore_read_fw(uncore, reg);
782783 } while (upper != tmp && --loop);
783784
drivers/gpu/drm/i915/gt/intel_workarounds.c+41−15
@@ -812,11 +812,25 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, · 811 unmodified lines
812812 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
813813 }
814814
815+static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
816+ struct i915_wa_list *wal)
817+{
818+ struct drm_i915_private *i915 = engine->i915;
819+
820+ dg2_ctx_gt_tuning_init(engine, wal);
821+
822+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
823+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
824+ wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
825+}
826+
815827 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
816828 struct i915_wa_list *wal)
817829 {
818830 struct drm_i915_private *i915 = engine->i915;
819831
832+ mtl_ctx_gt_tuning_init(engine, wal);
833+
820834 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
821835 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
822836 /* Wa_14014947963 */
@@ -1695,14 +1709,20 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) · 872 unmodified lines
16951709 static void
16961710 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
16971711 {
1712+ /* Wa_14018778641 / Wa_18018781329 */
1713+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1714+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1715+
1716+ /* Wa_22016670082 */
1717+ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1718+
16981719 if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
16991720 IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
17001721 /* Wa_14014830051 */
17011722 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
17021723
1703− /* Wa_18018781329 */
1704− wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1705− wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1724+ /* Wa_14015795083 */
1725+ wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
17061726 }
17071727
17081728 /*
@@ -1715,17 +1735,16 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) · 6 unmodified lines
17151735 static void
17161736 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
17171737 {
1718− if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
1719− /*
1720− * Wa_18018781329
1721− *
1722− * Note that although these registers are MCR on the primary
1723− * GT, the media GT's versions are regular singleton registers.
1724− */
1725− wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1726− wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1727− wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1728− }
1738+ /*
1739+ * Wa_14018778641
1740+ * Wa_18018781329
1741+ *
1742+ * Note that although these registers are MCR on the primary
1743+ * GT, the media GT's versions are regular singleton registers.
1744+ */
1745+ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1746+ wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1747+ wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
17291748
17301749 debug_dump_steering(gt);
17311750 }
@@ -1743,6 +1762,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) · 11 unmodified lines
17431762 */
17441763 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
17451764 {
1765+ if (IS_METEORLAKE(gt->i915)) {
1766+ if (gt->type != GT_MEDIA)
1767+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1768+
1769+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1770+ }
1771+
17461772 if (IS_PONTEVECCHIO(gt->i915)) {
17471773 wa_mcr_write(wal, XEHPC_L3SCRUB,
17481774 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
@@ -2939,7 +2965,7 @@ static void · 1190 unmodified lines
29392965 add_render_compute_tuning_settings(struct drm_i915_private *i915,
29402966 struct i915_wa_list *wal)
29412967 {
2942− if (IS_DG2(i915))
2968+ if (IS_METEORLAKE(i915) || IS_DG2(i915))
29432969 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
29442970
29452971 /*
drivers/gpu/drm/i915/gt/selftest_engine_pm.c+2−1
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/sort.h>
77
8+#include "gt/intel_gt_print.h"
89 #include "i915_selftest.h"
910 #include "intel_engine_regs.h"
1011 #include "intel_gpu_commands.h"
@@ -402,7 +403,7 @@ static int live_engine_pm(void *arg) · 391 unmodified lines
402403
403404 /* gt wakeref is async (deferred to workqueue) */
404405 if (intel_gt_pm_wait_for_idle(gt)) {
405− pr_err("GT failed to idle\n");
406+ gt_err(gt, "GT failed to idle\n");
406407 return -EINVAL;
407408 }
408409 }
drivers/gpu/drm/i915/gt/selftest_migrate.c+25−22
@@ -137,7 +137,7 @@ err_free_src: · 136 unmodified lines
137137 static int intel_context_copy_ccs(struct intel_context *ce,
138138 const struct i915_deps *deps,
139139 struct scatterlist *sg,
140− enum i915_cache_level cache_level,
140+ unsigned int pat_index,
141141 bool write_to_ccs,
142142 struct i915_request **out)
143143 {
@@ -185,7 +185,7 @@ static int intel_context_copy_ccs(struct intel_context *ce, · 41 unmodified lines
185185 if (err)
186186 goto out_rq;
187187
188− len = emit_pte(rq, &it, cache_level, true, offset, CHUNK_SZ);
188+ len = emit_pte(rq, &it, pat_index, true, offset, CHUNK_SZ);
189189 if (len <= 0) {
190190 err = len;
191191 goto out_rq;
@@ -223,7 +223,7 @@ intel_migrate_ccs_copy(struct intel_migrate *m, · 31 unmodified lines
223223 struct i915_gem_ww_ctx *ww,
224224 const struct i915_deps *deps,
225225 struct scatterlist *sg,
226− enum i915_cache_level cache_level,
226+ unsigned int pat_index,
227227 bool write_to_ccs,
228228 struct i915_request **out)
229229 {
@@ -243,7 +243,7 @@ intel_migrate_ccs_copy(struct intel_migrate *m, · 13 unmodified lines
243243 if (err)
244244 goto out;
245245
246− err = intel_context_copy_ccs(ce, deps, sg, cache_level,
246+ err = intel_context_copy_ccs(ce, deps, sg, pat_index,
247247 write_to_ccs, out);
248248
249249 intel_context_unpin(ce);
@@ -300,7 +300,7 @@ static int clear(struct intel_migrate *migrate, · 50 unmodified lines
300300 /* Write the obj data into ccs surface */
301301 err = intel_migrate_ccs_copy(migrate, &ww, NULL,
302302 obj->mm.pages->sgl,
303− obj->cache_level,
303+ obj->pat_index,
304304 true, &rq);
305305 if (rq && !err) {
306306 if (i915_request_wait(rq, 0, HZ) < 0) {
@@ -351,7 +351,7 @@ static int clear(struct intel_migrate *migrate, · 44 unmodified lines
351351
352352 err = intel_migrate_ccs_copy(migrate, &ww, NULL,
353353 obj->mm.pages->sgl,
354− obj->cache_level,
354+ obj->pat_index,
355355 false, &rq);
356356 if (rq && !err) {
357357 if (i915_request_wait(rq, 0, HZ) < 0) {
@@ -414,9 +414,9 @@ static int __migrate_copy(struct intel_migrate *migrate, · 56 unmodified lines
414414 struct i915_request **out)
415415 {
416416 return intel_migrate_copy(migrate, ww, NULL,
417− src->mm.pages->sgl, src->cache_level,
417+ src->mm.pages->sgl, src->pat_index,
418418 i915_gem_object_is_lmem(src),
419− dst->mm.pages->sgl, dst->cache_level,
419+ dst->mm.pages->sgl, dst->pat_index,
420420 i915_gem_object_is_lmem(dst),
421421 out);
422422 }
@@ -428,9 +428,9 @@ static int __global_copy(struct intel_migrate *migrate, · 5 unmodified lines
428428 struct i915_request **out)
429429 {
430430 return intel_context_migrate_copy(migrate->context, NULL,
431− src->mm.pages->sgl, src->cache_level,
431+ src->mm.pages->sgl, src->pat_index,
432432 i915_gem_object_is_lmem(src),
433− dst->mm.pages->sgl, dst->cache_level,
433+ dst->mm.pages->sgl, dst->pat_index,
434434 i915_gem_object_is_lmem(dst),
435435 out);
436436 }
@@ -455,7 +455,7 @@ static int __migrate_clear(struct intel_migrate *migrate, · 18 unmodified lines
455455 {
456456 return intel_migrate_clear(migrate, ww, NULL,
457457 obj->mm.pages->sgl,
458− obj->cache_level,
458+ obj->pat_index,
459459 i915_gem_object_is_lmem(obj),
460460 value, out);
461461 }
@@ -468,7 +468,7 @@ static int __global_clear(struct intel_migrate *migrate, · 6 unmodified lines
468468 {
469469 return intel_context_migrate_clear(migrate->context, NULL,
470470 obj->mm.pages->sgl,
471− obj->cache_level,
471+ obj->pat_index,
472472 i915_gem_object_is_lmem(obj),
473473 value, out);
474474 }
@@ -648,7 +648,7 @@ static int live_emit_pte_full_ring(void *arg) · 173 unmodified lines
648648 */
649649 pr_info("%s emite_pte ring space=%u\n", __func__, rq->ring->space);
650650 it = sg_sgt(obj->mm.pages->sgl);
651− len = emit_pte(rq, &it, obj->cache_level, false, 0, CHUNK_SZ);
651+ len = emit_pte(rq, &it, obj->pat_index, false, 0, CHUNK_SZ);
652652 if (!len) {
653653 err = -EINVAL;
654654 goto out_rq;
@@ -844,7 +844,7 @@ static int wrap_ktime_compare(const void *A, const void *B) · 189 unmodified lines
844844
845845 static int __perf_clear_blt(struct intel_context *ce,
846846 struct scatterlist *sg,
847− enum i915_cache_level cache_level,
847+ unsigned int pat_index,
848848 bool is_lmem,
849849 size_t sz)
850850 {
@@ -858,7 +858,7 @@ static int __perf_clear_blt(struct intel_context *ce, · 7 unmodified lines
858858
859859 t0 = ktime_get();
860860
861− err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
861+ err = intel_context_migrate_clear(ce, NULL, sg, pat_index,
862862 is_lmem, 0, &rq);
863863 if (rq) {
864864 if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
@@ -904,7 +904,8 @@ static int perf_clear_blt(void *arg) · 39 unmodified lines
904904
905905 err = __perf_clear_blt(gt->migrate.context,
906906 dst->mm.pages->sgl,
907− I915_CACHE_NONE,
907+ i915_gem_get_pat_index(gt->i915,
908+ I915_CACHE_NONE),
908909 i915_gem_object_is_lmem(dst),
909910 sizes[i]);
910911
@@ -919,10 +920,10 @@ static int perf_clear_blt(void *arg) · 8 unmodified lines
919920
920921 static int __perf_copy_blt(struct intel_context *ce,
921922 struct scatterlist *src,
922− enum i915_cache_level src_cache_level,
923+ unsigned int src_pat_index,
923924 bool src_is_lmem,
924925 struct scatterlist *dst,
925− enum i915_cache_level dst_cache_level,
926+ unsigned int dst_pat_index,
926927 bool dst_is_lmem,
927928 size_t sz)
928929 {
@@ -937,9 +938,9 @@ static int __perf_copy_blt(struct intel_context *ce, · 8 unmodified lines
937938 t0 = ktime_get();
938939
939940 err = intel_context_migrate_copy(ce, NULL,
940− src, src_cache_level,
941+ src, src_pat_index,
941942 src_is_lmem,
942− dst, dst_cache_level,
943+ dst, dst_pat_index,
943944 dst_is_lmem,
944945 &rq);
945946 if (rq) {
@@ -994,10 +995,12 @@ static int perf_copy_blt(void *arg) · 48 unmodified lines
994995
995996 err = __perf_copy_blt(gt->migrate.context,
996997 src->mm.pages->sgl,
997− I915_CACHE_NONE,
998+ i915_gem_get_pat_index(gt->i915,
999+ I915_CACHE_NONE),
9981000 i915_gem_object_is_lmem(src),
9991001 dst->mm.pages->sgl,
1000− I915_CACHE_NONE,
1002+ i915_gem_get_pat_index(gt->i915,
1003+ I915_CACHE_NONE),
10011004 i915_gem_object_is_lmem(dst),
10021005 sz);
10031006
drivers/gpu/drm/i915/gt/selftest_mocs.c+2−1
@@ -131,13 +131,14 @@ static int read_mocs_table(struct i915_request *rq, · 130 unmodified lines
131131 const struct drm_i915_mocs_table *table,
132132 u32 *offset)
133133 {
134+ struct intel_gt *gt = rq->engine->gt;
134135 u32 addr;
135136
136137 if (!table)
137138 return 0;
138139
139140 if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
140− addr = global_mocs_offset();
141+ addr = global_mocs_offset() + gt->uncore->gsi_offset;
141142 else
142143 addr = mocs_offset(rq->engine);
143144
drivers/gpu/drm/i915/gt/selftest_reset.c+6−2
@@ -86,7 +86,9 @@ __igt_reset_stolen(struct intel_gt *gt, · 85 unmodified lines
8686
8787 ggtt->vm.insert_page(&ggtt->vm, dma,
8888 ggtt->error_capture.start,
89− I915_CACHE_NONE, 0);
89+ i915_gem_get_pat_index(gt->i915,
90+ I915_CACHE_NONE),
91+ 0);
9092 mb();
9193
9294 s = io_mapping_map_wc(&ggtt->iomap,
@@ -127,7 +129,9 @@ __igt_reset_stolen(struct intel_gt *gt, · 34 unmodified lines
127129
128130 ggtt->vm.insert_page(&ggtt->vm, dma,
129131 ggtt->error_capture.start,
130− I915_CACHE_NONE, 0);
132+ i915_gem_get_pat_index(gt->i915,
133+ I915_CACHE_NONE),
134+ 0);
131135 mb();
132136
133137 s = io_mapping_map_wc(&ggtt->iomap,
drivers/gpu/drm/i915/gt/selftest_slpc.c+37−5
@@ -70,6 +70,31 @@ static int slpc_set_freq(struct intel_gt *gt, u32 freq) · 69 unmodified lines
7070 return err;
7171 }
7272
73+static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max)
74+{
75+ int err;
76+
77+ err = slpc_set_max_freq(slpc, max);
78+ if (err) {
79+ pr_err("Unable to restore max freq");
80+ return err;
81+ }
82+
83+ err = slpc_set_min_freq(slpc, min);
84+ if (err) {
85+ pr_err("Unable to restore min freq");
86+ return err;
87+ }
88+
89+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, false);
90+ if (err) {
91+ pr_err("Unable to restore efficient freq");
92+ return err;
93+ }
94+
95+ return 0;
96+}
97+
7398 static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power)
7499 {
75100 int err = 0;
@@ -268,8 +293,7 @@ static int run_test(struct intel_gt *gt, int test_type) · 192 unmodified lines
268293
269294 /*
270295 * Set min frequency to RPn so that we can test the whole
271− * range of RPn-RP0. This also turns off efficient freq
272− * usage and makes results more predictable.
296+ * range of RPn-RP0.
273297 */
274298 err = slpc_set_min_freq(slpc, slpc->min_freq);
275299 if (err) {
@@ -277,6 +301,15 @@ static int run_test(struct intel_gt *gt, int test_type) · 1 unmodified line
277301 return err;
278302 }
279303
304+ /*
305+ * Turn off efficient frequency so RPn/RP0 ranges are obeyed.
306+ */
307+ err = intel_guc_slpc_set_ignore_eff_freq(slpc, true);
308+ if (err) {
309+ pr_err("Unable to turn off efficient freq!");
310+ return err;
311+ }
312+
280313 intel_gt_pm_wait_for_idle(gt);
281314 intel_gt_pm_get(gt);
282315 for_each_engine(engine, gt, id) {
@@ -358,9 +391,8 @@ static int run_test(struct intel_gt *gt, int test_type) · 75 unmodified lines
358391 break;
359392 }
360393
361− /* Restore min/max frequencies */
362− slpc_set_max_freq(slpc, slpc_max_freq);
363− slpc_set_min_freq(slpc, slpc_min_freq);
394+ /* Restore min/max/efficient frequencies */
395+ err = slpc_restore_freq(slpc, slpc_min_freq, slpc_max_freq);
364396
365397 if (igt_flush_test(gt->i915))
366398 err = -EIO;
drivers/gpu/drm/i915/gt/selftest_timeline.c+1−1
@@ -836,7 +836,7 @@ static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt, · 835 unmodified lines
836836 return PTR_ERR(obj);
837837
838838 /* keep the same cache settings as timeline */
839− i915_gem_object_set_cache_coherency(obj, tl->hwsp_ggtt->obj->cache_level);
839+ i915_gem_object_set_pat_index(obj, tl->hwsp_ggtt->obj->pat_index);
840840 w->map = i915_gem_object_pin_map_unlocked(obj,
841841 page_unmask_bits(tl->hwsp_ggtt->obj->mm.mapping));
842842 if (IS_ERR(w->map)) {
drivers/gpu/drm/i915/gt/selftest_tlb.c+3−1
@@ -36,6 +36,8 @@ pte_tlbinv(struct intel_context *ce, · 35 unmodified lines
3636 u64 length,
3737 struct rnd_state *prng)
3838 {
39+ const unsigned int pat_index =
40+ i915_gem_get_pat_index(ce->vm->i915, I915_CACHE_NONE);
3941 struct drm_i915_gem_object *batch;
4042 struct drm_mm_node vb_node;
4143 struct i915_request *rq;
@@ -155,7 +157,7 @@ pte_tlbinv(struct intel_context *ce, · 113 unmodified lines
155157 /* Flip the PTE between A and B */
156158 if (i915_gem_object_is_lmem(vb->obj))
157159 pte_flags |= PTE_LM;
158− ce->vm->insert_entries(ce->vm, &vb_res, 0, pte_flags);
160+ ce->vm->insert_entries(ce->vm, &vb_res, pat_index, pte_flags);
159161
160162 /* Flush the PTE update to concurrent HW */
161163 tlbinv(ce->vm, addr & -length, length);
drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h+1−0
@@ -44,6 +44,7 @@ enum intel_guc_load_status { · 43 unmodified lines
4444 enum intel_bootrom_load_status {
4545 INTEL_BOOTROM_STATUS_NO_KEY_FOUND = 0x13,
4646 INTEL_BOOTROM_STATUS_AES_PROD_KEY_FOUND = 0x1A,
47+ INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE = 0x2B,
4748 INTEL_BOOTROM_STATUS_RSA_FAILED = 0x50,
4849 INTEL_BOOTROM_STATUS_PAVPC_FAILED = 0x73,
4950 INTEL_BOOTROM_STATUS_WOPCM_FAILED = 0x74,
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h+14−6
@@ -12,7 +12,7 @@ · 11 unmodified lines
1212 struct intel_guc;
1313 struct file;
1414
15−/**
15+/*
1616 * struct __guc_capture_bufstate
1717 *
1818 * Book-keeping structure used to track read and write pointers
@@ -26,7 +26,7 @@ struct __guc_capture_bufstate { · 7 unmodified lines
2626 u32 wr;
2727 };
2828
29−/**
29+/*
3030 * struct __guc_capture_parsed_output - extracted error capture node
3131 *
3232 * A single unit of extracted error-capture output data grouped together
@@ -58,7 +58,7 @@ struct __guc_capture_parsed_output { · 25 unmodified lines
5858 #define GCAP_PARSED_REGLIST_INDEX_ENGINST BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
5959 };
6060
61−/**
61+/*
6262 * struct guc_debug_capture_list_header / struct guc_debug_capture_list
6363 *
6464 * As part of ADS registration, these header structures (followed by
@@ -76,7 +76,7 @@ struct guc_debug_capture_list { · 11 unmodified lines
7676 struct guc_mmio_reg regs[];
7777 } __packed;
7878
79−/**
79+/*
8080 * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
8181 *
8282 * intel_guc_capture module uses these structures to maintain static
@@ -101,7 +101,7 @@ struct __guc_mmio_reg_descr_group { · 18 unmodified lines
101101 struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */
102102 };
103103
104−/**
104+/*
105105 * struct guc_state_capture_header_t / struct guc_state_capture_t /
106106 * guc_state_capture_group_header_t / guc_state_capture_group_t
107107 *
@@ -148,7 +148,7 @@ struct guc_state_capture_group_t { · 40 unmodified lines
148148 struct guc_state_capture_t capture_entries[];
149149 } __packed;
150150
151−/**
151+/*
152152 * struct __guc_capture_ads_cache
153153 *
154154 * A structure to cache register lists that were populated and registered
@@ -187,6 +187,10 @@ struct intel_guc_state_capture { · 32 unmodified lines
187187 struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
188188 [GUC_CAPTURE_LIST_TYPE_MAX]
189189 [GUC_MAX_ENGINE_CLASSES];
190+
191+ /**
192+ * @ads_null_cache: ADS null cache.
193+ */
190194 void *ads_null_cache;
191195
192196 /**
@@ -202,6 +206,10 @@ struct intel_guc_state_capture { · 9 unmodified lines
202206 struct list_head cachelist;
203207 #define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)
204208 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
209+
210+ /**
211+ * @max_mmio_per_node: Max MMIO per node.
212+ */
205213 int max_mmio_per_node;
206214
207215 /**
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c+23−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #define GSC_FW_STATUS_REG _MMIO(0x116C40)
1414 #define GSC_FW_CURRENT_STATE REG_GENMASK(3, 0)
1515 #define GSC_FW_CURRENT_STATE_RESET 0
16+#define GSC_FW_PROXY_STATE_NORMAL 5
1617 #define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
1718
1819 static bool gsc_is_in_reset(struct intel_uncore *uncore)
@@ -23,6 +24,15 @@ static bool gsc_is_in_reset(struct intel_uncore *uncore) · 4 unmodified lines
2324 GSC_FW_CURRENT_STATE_RESET;
2425 }
2526
27+bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
28+{
29+ struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
30+ u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
31+
32+ return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
33+ GSC_FW_PROXY_STATE_NORMAL;
34+}
35+
2636 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
2737 {
2838 struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
@@ -110,6 +120,13 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc) · 81 unmodified lines
110120 if (obj->base.size < gsc->fw.size)
111121 return -ENOSPC;
112122
123+ /*
124+ * Wa_22016122933: For MTL the shared memory needs to be mapped
125+ * as WC on CPU side and UC (PAT index 2) on GPU side
126+ */
127+ if (IS_METEORLAKE(i915))
128+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
129+
113130 dst = i915_gem_object_pin_map_unlocked(obj,
114131 i915_coherent_map_type(i915, obj, true));
115132 if (IS_ERR(dst))
@@ -125,6 +142,12 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc) · 9 unmodified lines
125142 memset(dst, 0, obj->base.size);
126143 memcpy(dst, src, gsc->fw.size);
127144
145+ /*
146+ * Wa_22016122933: Making sure the data in dst is
147+ * visible to GSC right away
148+ */
149+ intel_guc_write_barrier(&gt->uc.guc);
150+
128151 i915_gem_object_unpin_map(gsc->fw.obj);
129152 i915_gem_object_unpin_map(obj);
130153
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h+1−0
@@ -13,5 +13,6 @@ struct intel_uncore; · 12 unmodified lines
1313
1414 int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
1515 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
16+bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc);
1617
1718 #endif
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c+424−0
@@ -0,0 +1,424 @@
1+// SPDX-License-Identifier: MIT
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#include <linux/component.h>
7+
8+#include "drm/i915_component.h"
9+#include "drm/i915_gsc_proxy_mei_interface.h"
10+
11+#include "gt/intel_gt.h"
12+#include "gt/intel_gt_print.h"
13+#include "intel_gsc_proxy.h"
14+#include "intel_gsc_uc.h"
15+#include "intel_gsc_uc_heci_cmd_submit.h"
16+#include "i915_drv.h"
17+#include "i915_reg.h"
18+
19+/*
20+ * GSC proxy:
21+ * The GSC uC needs to communicate with the CSME to perform certain operations.
22+ * Since the GSC can't perform this communication directly on platforms where it
23+ * is integrated in GT, i915 needs to transfer the messages from GSC to CSME
24+ * and back. i915 must manually start the proxy flow after the GSC is loaded to
25+ * signal to GSC that we're ready to handle its messages and allow it to query
26+ * its init data from CSME; GSC will then trigger an HECI2 interrupt if it needs
27+ * to send messages to CSME again.
28+ * The proxy flow is as follow:
29+ * 1 - i915 submits a request to GSC asking for the message to CSME
30+ * 2 - GSC replies with the proxy header + payload for CSME
31+ * 3 - i915 sends the reply from GSC as-is to CSME via the mei proxy component
32+ * 4 - CSME replies with the proxy header + payload for GSC
33+ * 5 - i915 submits a request to GSC with the reply from CSME
34+ * 6 - GSC replies either with a new header + payload (same as step 2, so we
35+ * restart from there) or with an end message.
36+ */
37+
38+/*
39+ * The component should load quite quickly in most cases, but it could take
40+ * a bit. Using a very big timeout just to cover the worst case scenario
41+ */
42+#define GSC_PROXY_INIT_TIMEOUT_MS 20000
43+
44+/* the protocol supports up to 32K in each direction */
45+#define GSC_PROXY_BUFFER_SIZE SZ_32K
46+#define GSC_PROXY_CHANNEL_SIZE (GSC_PROXY_BUFFER_SIZE * 2)
47+#define GSC_PROXY_MAX_MSG_SIZE (GSC_PROXY_BUFFER_SIZE - sizeof(struct intel_gsc_mtl_header))
48+
49+/* FW-defined proxy header */
50+struct intel_gsc_proxy_header {
51+ /*
52+ * hdr:
53+ * Bits 0-7: type of the proxy message (see enum intel_gsc_proxy_type)
54+ * Bits 8-15: rsvd
55+ * Bits 16-31: length in bytes of the payload following the proxy header
56+ */
57+ u32 hdr;
58+#define GSC_PROXY_TYPE GENMASK(7, 0)
59+#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
60+
61+ u32 source; /* Source of the Proxy message */
62+ u32 destination; /* Destination of the Proxy message */
63+#define GSC_PROXY_ADDRESSING_KMD 0x10000
64+#define GSC_PROXY_ADDRESSING_GSC 0x20000
65+#define GSC_PROXY_ADDRESSING_CSME 0x30000
66+
67+ u32 status; /* Command status */
68+} __packed;
69+
70+/* FW-defined proxy types */
71+enum intel_gsc_proxy_type {
72+ GSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,
73+ GSC_PROXY_MSG_TYPE_PROXY_QUERY = 1,
74+ GSC_PROXY_MSG_TYPE_PROXY_PAYLOAD = 2,
75+ GSC_PROXY_MSG_TYPE_PROXY_END = 3,
76+ GSC_PROXY_MSG_TYPE_PROXY_NOTIFICATION = 4,
77+};
78+
79+struct gsc_proxy_msg {
80+ struct intel_gsc_mtl_header header;
81+ struct intel_gsc_proxy_header proxy_header;
82+} __packed;
83+
84+static int proxy_send_to_csme(struct intel_gsc_uc *gsc)
85+{
86+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
87+ struct i915_gsc_proxy_component *comp = gsc->proxy.component;
88+ struct intel_gsc_mtl_header *hdr;
89+ void *in = gsc->proxy.to_csme;
90+ void *out = gsc->proxy.to_gsc;
91+ u32 in_size;
92+ int ret;
93+
94+ /* CSME msg only includes the proxy */
95+ hdr = in;
96+ in += sizeof(struct intel_gsc_mtl_header);
97+ out += sizeof(struct intel_gsc_mtl_header);
98+
99+ in_size = hdr->message_size - sizeof(struct intel_gsc_mtl_header);
100+
101+ /* the message must contain at least the proxy header */
102+ if (in_size < sizeof(struct intel_gsc_proxy_header) ||
103+ in_size > GSC_PROXY_MAX_MSG_SIZE) {
104+ gt_err(gt, "Invalid CSME message size: %u\n", in_size);
105+ return -EINVAL;
106+ }
107+
108+ ret = comp->ops->send(comp->mei_dev, in, in_size);
109+ if (ret < 0) {
110+ gt_err(gt, "Failed to send CSME message\n");
111+ return ret;
112+ }
113+
114+ ret = comp->ops->recv(comp->mei_dev, out, GSC_PROXY_MAX_MSG_SIZE);
115+ if (ret < 0) {
116+ gt_err(gt, "Failed to receive CSME message\n");
117+ return ret;
118+ }
119+
120+ return ret;
121+}
122+
123+static int proxy_send_to_gsc(struct intel_gsc_uc *gsc)
124+{
125+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
126+ u32 *marker = gsc->proxy.to_csme; /* first dw of the reply header */
127+ u64 addr_in = i915_ggtt_offset(gsc->proxy.vma);
128+ u64 addr_out = addr_in + GSC_PROXY_BUFFER_SIZE;
129+ u32 size = ((struct gsc_proxy_msg *)gsc->proxy.to_gsc)->header.message_size;
130+ int err;
131+
132+ /* the message must contain at least the gsc and proxy headers */
133+ if (size < sizeof(struct gsc_proxy_msg) || size > GSC_PROXY_BUFFER_SIZE) {
134+ gt_err(gt, "Invalid GSC proxy message size: %u\n", size);
135+ return -EINVAL;
136+ }
137+
138+ /* clear the message marker */
139+ *marker = 0;
140+
141+ /* make sure the marker write is flushed */
142+ wmb();
143+
144+ /* send the request */
145+ err = intel_gsc_uc_heci_cmd_submit_packet(gsc, addr_in, size,
146+ addr_out, GSC_PROXY_BUFFER_SIZE);
147+
148+ if (!err) {
149+ /* wait for the reply to show up */
150+ err = wait_for(*marker != 0, 300);
151+ if (err)
152+ gt_err(gt, "Failed to get a proxy reply from gsc\n");
153+ }
154+
155+ return err;
156+}
157+
158+static int validate_proxy_header(struct intel_gsc_proxy_header *header,
159+ u32 source, u32 dest)
160+{
161+ u32 type = FIELD_GET(GSC_PROXY_TYPE, header->hdr);
162+ u32 length = FIELD_GET(GSC_PROXY_PAYLOAD_LENGTH, header->hdr);
163+ int ret = 0;
164+
165+ if (header->destination != dest || header->source != source) {
166+ ret = -ENOEXEC;
167+ goto fail;
168+ }
169+
170+ switch (type) {
171+ case GSC_PROXY_MSG_TYPE_PROXY_PAYLOAD:
172+ if (length > 0)
173+ break;
174+ fallthrough;
175+ case GSC_PROXY_MSG_TYPE_PROXY_INVALID:
176+ ret = -EIO;
177+ goto fail;
178+ default:
179+ break;
180+ }
181+
182+fail:
183+ return ret;
184+}
185+
186+static int proxy_query(struct intel_gsc_uc *gsc)
187+{
188+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
189+ struct gsc_proxy_msg *to_gsc = gsc->proxy.to_gsc;
190+ struct gsc_proxy_msg *to_csme = gsc->proxy.to_csme;
191+ int ret;
192+
193+ intel_gsc_uc_heci_cmd_emit_mtl_header(&to_gsc->header,
194+ HECI_MEADDRESS_PROXY,
195+ sizeof(struct gsc_proxy_msg),
196+ 0);
197+
198+ to_gsc->proxy_header.hdr =
199+ FIELD_PREP(GSC_PROXY_TYPE, GSC_PROXY_MSG_TYPE_PROXY_QUERY) |
200+ FIELD_PREP(GSC_PROXY_PAYLOAD_LENGTH, 0);
201+
202+ to_gsc->proxy_header.source = GSC_PROXY_ADDRESSING_KMD;
203+ to_gsc->proxy_header.destination = GSC_PROXY_ADDRESSING_GSC;
204+ to_gsc->proxy_header.status = 0;
205+
206+ while (1) {
207+ /* clear the GSC response header space */
208+ memset(gsc->proxy.to_csme, 0, sizeof(struct gsc_proxy_msg));
209+
210+ /* send proxy message to GSC */
211+ ret = proxy_send_to_gsc(gsc);
212+ if (ret) {
213+ gt_err(gt, "failed to send proxy message to GSC! %d\n", ret);
214+ goto proxy_error;
215+ }
216+
217+ /* stop if this was the last message */
218+ if (FIELD_GET(GSC_PROXY_TYPE, to_csme->proxy_header.hdr) ==
219+ GSC_PROXY_MSG_TYPE_PROXY_END)
220+ break;
221+
222+ /* make sure the GSC-to-CSME proxy header is sane */
223+ ret = validate_proxy_header(&to_csme->proxy_header,
224+ GSC_PROXY_ADDRESSING_GSC,
225+ GSC_PROXY_ADDRESSING_CSME);
226+ if (ret) {
227+ gt_err(gt, "invalid GSC to CSME proxy header! %d\n", ret);
228+ goto proxy_error;
229+ }
230+
231+ /* send the GSC message to the CSME */
232+ ret = proxy_send_to_csme(gsc);
233+ if (ret < 0) {
234+ gt_err(gt, "failed to send proxy message to CSME! %d\n", ret);
235+ goto proxy_error;
236+ }
237+
238+ /* update the GSC message size with the returned value from CSME */
239+ to_gsc->header.message_size = ret + sizeof(struct intel_gsc_mtl_header);
240+
241+ /* make sure the CSME-to-GSC proxy header is sane */
242+ ret = validate_proxy_header(&to_gsc->proxy_header,
243+ GSC_PROXY_ADDRESSING_CSME,
244+ GSC_PROXY_ADDRESSING_GSC);
245+ if (ret) {
246+ gt_err(gt, "invalid CSME to GSC proxy header! %d\n", ret);
247+ goto proxy_error;
248+ }
249+ }
250+
251+proxy_error:
252+ return ret < 0 ? ret : 0;
253+}
254+
255+int intel_gsc_proxy_request_handler(struct intel_gsc_uc *gsc)
256+{
257+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
258+ int err;
259+
260+ if (!gsc->proxy.component_added)
261+ return -ENODEV;
262+
263+ assert_rpm_wakelock_held(gt->uncore->rpm);
264+
265+ /* when GSC is loaded, we can queue this before the component is bound */
266+ err = wait_for(gsc->proxy.component, GSC_PROXY_INIT_TIMEOUT_MS);
267+ if (err) {
268+ gt_err(gt, "GSC proxy component didn't bind within the expected timeout\n");
269+ return -EIO;
270+ }
271+
272+ mutex_lock(&gsc->proxy.mutex);
273+ if (!gsc->proxy.component) {
274+ gt_err(gt, "GSC proxy worker called without the component being bound!\n");
275+ err = -EIO;
276+ } else {
277+ /*
278+ * write the status bit to clear it and allow new proxy
279+ * interrupts to be generated while we handle the current
280+ * request, but be sure not to write the reset bit
281+ */
282+ intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
283+ HECI_H_CSR_RST, HECI_H_CSR_IS);
284+ err = proxy_query(gsc);
285+ }
286+ mutex_unlock(&gsc->proxy.mutex);
287+ return err;
288+}
289+
290+void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir)
291+{
292+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
293+
294+ if (unlikely(!iir))
295+ return;
296+
297+ lockdep_assert_held(gt->irq_lock);
298+
299+ if (!gsc->proxy.component) {
300+ gt_err(gt, "GSC proxy irq received without the component being bound!\n");
301+ return;
302+ }
303+
304+ gsc->gsc_work_actions |= GSC_ACTION_SW_PROXY;
305+ queue_work(gsc->wq, &gsc->work);
306+}
307+
308+static int i915_gsc_proxy_component_bind(struct device *i915_kdev,
309+ struct device *mei_kdev, void *data)
310+{
311+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
312+ struct intel_gt *gt = i915->media_gt;
313+ struct intel_gsc_uc *gsc = &gt->uc.gsc;
314+ intel_wakeref_t wakeref;
315+
316+ /* enable HECI2 IRQs */
317+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
318+ intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
319+ HECI_H_CSR_RST, HECI_H_CSR_IE);
320+
321+ mutex_lock(&gsc->proxy.mutex);
322+ gsc->proxy.component = data;
323+ gsc->proxy.component->mei_dev = mei_kdev;
324+ mutex_unlock(&gsc->proxy.mutex);
325+
326+ return 0;
327+}
328+
329+static void i915_gsc_proxy_component_unbind(struct device *i915_kdev,
330+ struct device *mei_kdev, void *data)
331+{
332+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
333+ struct intel_gt *gt = i915->media_gt;
334+ struct intel_gsc_uc *gsc = &gt->uc.gsc;
335+ intel_wakeref_t wakeref;
336+
337+ mutex_lock(&gsc->proxy.mutex);
338+ gsc->proxy.component = NULL;
339+ mutex_unlock(&gsc->proxy.mutex);
340+
341+ /* disable HECI2 IRQs */
342+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
343+ intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
344+ HECI_H_CSR_IE | HECI_H_CSR_RST, 0);
345+}
346+
347+static const struct component_ops i915_gsc_proxy_component_ops = {
348+ .bind = i915_gsc_proxy_component_bind,
349+ .unbind = i915_gsc_proxy_component_unbind,
350+};
351+
352+static int proxy_channel_alloc(struct intel_gsc_uc *gsc)
353+{
354+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
355+ struct i915_vma *vma;
356+ void *vaddr;
357+ int err;
358+
359+ err = intel_guc_allocate_and_map_vma(&gt->uc.guc, GSC_PROXY_CHANNEL_SIZE,
360+ &vma, &vaddr);
361+ if (err)
362+ return err;
363+
364+ gsc->proxy.vma = vma;
365+ gsc->proxy.to_gsc = vaddr;
366+ gsc->proxy.to_csme = vaddr + GSC_PROXY_BUFFER_SIZE;
367+
368+ return 0;
369+}
370+
371+static void proxy_channel_free(struct intel_gsc_uc *gsc)
372+{
373+ if (!gsc->proxy.vma)
374+ return;
375+
376+ gsc->proxy.to_gsc = NULL;
377+ gsc->proxy.to_csme = NULL;
378+ i915_vma_unpin_and_release(&gsc->proxy.vma, I915_VMA_RELEASE_MAP);
379+}
380+
381+void intel_gsc_proxy_fini(struct intel_gsc_uc *gsc)
382+{
383+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
384+ struct drm_i915_private *i915 = gt->i915;
385+
386+ if (fetch_and_zero(&gsc->proxy.component_added))
387+ component_del(i915->drm.dev, &i915_gsc_proxy_component_ops);
388+
389+ proxy_channel_free(gsc);
390+}
391+
392+int intel_gsc_proxy_init(struct intel_gsc_uc *gsc)
393+{
394+ int err;
395+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
396+ struct drm_i915_private *i915 = gt->i915;
397+
398+ mutex_init(&gsc->proxy.mutex);
399+
400+ if (!IS_ENABLED(CONFIG_INTEL_MEI_GSC_PROXY)) {
401+ gt_info(gt, "can't init GSC proxy due to missing mei component\n");
402+ return -ENODEV;
403+ }
404+
405+ err = proxy_channel_alloc(gsc);
406+ if (err)
407+ return err;
408+
409+ err = component_add_typed(i915->drm.dev, &i915_gsc_proxy_component_ops,
410+ I915_COMPONENT_GSC_PROXY);
411+ if (err < 0) {
412+ gt_err(gt, "Failed to add GSC_PROXY component (%d)\n", err);
413+ goto out_free;
414+ }
415+
416+ gsc->proxy.component_added = true;
417+
418+ return 0;
419+
420+out_free:
421+ proxy_channel_free(gsc);
422+ return err;
423+}
424+
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h+18−0
@@ -0,0 +1,18 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#ifndef _INTEL_GSC_PROXY_H_
7+#define _INTEL_GSC_PROXY_H_
8+
9+#include <linux/types.h>
10+
11+struct intel_gsc_uc;
12+
13+int intel_gsc_proxy_init(struct intel_gsc_uc *gsc);
14+void intel_gsc_proxy_fini(struct intel_gsc_uc *gsc);
15+int intel_gsc_proxy_request_handler(struct intel_gsc_uc *gsc);
16+void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir);
17+
18+#endif
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c+72−4
@@ -10,15 +10,60 @@ · 9 unmodified lines
1010 #include "intel_gsc_uc.h"
1111 #include "intel_gsc_fw.h"
1212 #include "i915_drv.h"
13+#include "intel_gsc_proxy.h"
1314
1415 static void gsc_work(struct work_struct *work)
1516 {
1617 struct intel_gsc_uc *gsc = container_of(work, typeof(*gsc), work);
1718 struct intel_gt *gt = gsc_uc_to_gt(gsc);
1819 intel_wakeref_t wakeref;
20+ u32 actions;
21+ int ret;
22+
23+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
24+
25+ spin_lock_irq(gt->irq_lock);
26+ actions = gsc->gsc_work_actions;
27+ gsc->gsc_work_actions = 0;
28+ spin_unlock_irq(gt->irq_lock);
29+
30+ if (actions & GSC_ACTION_FW_LOAD) {
31+ ret = intel_gsc_uc_fw_upload(gsc);
32+ if (ret == -EEXIST) /* skip proxy if not a new load */
33+ actions &= ~GSC_ACTION_FW_LOAD;
34+ else if (ret)
35+ goto out_put;
36+ }
37+
38+ if (actions & (GSC_ACTION_FW_LOAD | GSC_ACTION_SW_PROXY)) {
39+ if (!intel_gsc_uc_fw_init_done(gsc)) {
40+ gt_err(gt, "Proxy request received with GSC not loaded!\n");
41+ goto out_put;
42+ }
43+
44+ ret = intel_gsc_proxy_request_handler(gsc);
45+ if (ret)
46+ goto out_put;
47+
48+ /* mark the GSC FW init as done the first time we run this */
49+ if (actions & GSC_ACTION_FW_LOAD) {
50+ /*
51+ * If there is a proxy establishment error, the GSC might still
52+ * complete the request handling cleanly, so we need to check the
53+ * status register to check if the proxy init was actually successful
54+ */
55+ if (intel_gsc_uc_fw_proxy_init_done(gsc)) {
56+ drm_dbg(&gt->i915->drm, "GSC Proxy initialized\n");
57+ intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_RUNNING);
58+ } else {
59+ drm_err(&gt->i915->drm,
60+ "GSC status reports proxy init not complete\n");
61+ }
62+ }
63+ }
1964
20− with_intel_runtime_pm(gt->uncore->rpm, wakeref)
21− intel_gsc_uc_fw_upload(gsc);
65+out_put:
66+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
2267 }
2368
2469 static bool gsc_engine_supported(struct intel_gt *gt)
@@ -43,6 +88,8 @@ static bool gsc_engine_supported(struct intel_gt *gt) · 18 unmodified lines
4388
4489 void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)
4590 {
91+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
92+
4693 intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);
4794 INIT_WORK(&gsc->work, gsc_work);
4895
@@ -50,10 +97,16 @@ void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc) · 1 unmodified line
5097 * GT with it being not fully setup hence check device info's
5198 * engine mask
5299 */
53− if (!gsc_engine_supported(gsc_uc_to_gt(gsc))) {
100+ if (!gsc_engine_supported(gt)) {
54101 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
55102 return;
56103 }
104+
105+ gsc->wq = alloc_ordered_workqueue("i915_gsc", 0);
106+ if (!gsc->wq) {
107+ gt_err(gt, "failed to allocate WQ for GSC, disabling FW\n");
108+ intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
109+ }
57110 }
58111
59112 int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
@@ -88,6 +141,9 @@ int intel_gsc_uc_init(struct intel_gsc_uc *gsc) · 28 unmodified lines
88141
89142 gsc->ce = ce;
90143
144+ /* if we fail to init proxy we still want to load GSC for PM */
145+ intel_gsc_proxy_init(gsc);
146+
91147 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_LOADABLE);
92148
93149 return 0;
@@ -107,6 +163,12 @@ void intel_gsc_uc_fini(struct intel_gsc_uc *gsc) · 13 unmodified lines
107163 return;
108164
109165 flush_work(&gsc->work);
166+ if (gsc->wq) {
167+ destroy_workqueue(gsc->wq);
168+ gsc->wq = NULL;
169+ }
170+
171+ intel_gsc_proxy_fini(gsc);
110172
111173 if (gsc->ce)
112174 intel_engine_destroy_pinned_context(fetch_and_zero(&gsc->ce));
@@ -145,11 +207,17 @@ void intel_gsc_uc_resume(struct intel_gsc_uc *gsc) · 32 unmodified lines
145207
146208 void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc)
147209 {
210+ struct intel_gt *gt = gsc_uc_to_gt(gsc);
211+
148212 if (!intel_uc_fw_is_loadable(&gsc->fw))
149213 return;
150214
151215 if (intel_gsc_uc_fw_init_done(gsc))
152216 return;
153217
154− queue_work(system_unbound_wq, &gsc->work);
218+ spin_lock_irq(gt->irq_lock);
219+ gsc->gsc_work_actions |= GSC_ACTION_FW_LOAD;
220+ spin_unlock_irq(gt->irq_lock);
221+
222+ queue_work(gsc->wq, &gsc->work);
155223 }
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h+16−1
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010
1111 struct i915_vma;
1212 struct intel_context;
13+struct i915_gsc_proxy_component;
1314
1415 struct intel_gsc_uc {
1516 /* Generic uC firmware management */
@@ -19,7 +20,21 @@ struct intel_gsc_uc { · 3 unmodified lines
1920 struct i915_vma *local; /* private memory for GSC usage */
2021 struct intel_context *ce; /* for submission to GSC FW via GSC engine */
2122
22− struct work_struct work; /* for delayed load */
23+ /* for delayed load and proxy handling */
24+ struct workqueue_struct *wq;
25+ struct work_struct work;
26+ u32 gsc_work_actions; /* protected by gt->irq_lock */
27+#define GSC_ACTION_FW_LOAD BIT(0)
28+#define GSC_ACTION_SW_PROXY BIT(1)
29+
30+ struct {
31+ struct i915_gsc_proxy_component *component;
32+ bool component_added;
33+ struct i915_vma *vma;
34+ void *to_gsc;
35+ void *to_csme;
36+ struct mutex mutex; /* protects the tee channel binding */
37+ } proxy;
2338 };
2439
2540 void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc);
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c+102−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright © 2023 Intel Corporation
44 */
55
6+#include "gt/intel_context.h"
67 #include "gt/intel_engine_pm.h"
78 #include "gt/intel_gpu_commands.h"
89 #include "gt/intel_gt.h"
@@ -107,3 +108,104 @@ void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header, · 98 unmodified lines
107108 header->header_version = MTL_GSC_HEADER_VERSION;
108109 header->message_size = message_size;
109110 }
111+
112+static void
113+emit_gsc_heci_pkt_nonpriv(u32 *cmd, struct intel_gsc_heci_non_priv_pkt *pkt)
114+{
115+ *cmd++ = GSC_HECI_CMD_PKT;
116+ *cmd++ = lower_32_bits(pkt->addr_in);
117+ *cmd++ = upper_32_bits(pkt->addr_in);
118+ *cmd++ = pkt->size_in;
119+ *cmd++ = lower_32_bits(pkt->addr_out);
120+ *cmd++ = upper_32_bits(pkt->addr_out);
121+ *cmd++ = pkt->size_out;
122+ *cmd++ = 0;
123+ *cmd++ = MI_BATCH_BUFFER_END;
124+}
125+
126+int
127+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
128+ struct intel_context *ce,
129+ struct intel_gsc_heci_non_priv_pkt *pkt,
130+ u32 *cmd, int timeout_ms)
131+{
132+ struct intel_engine_cs *engine;
133+ struct i915_gem_ww_ctx ww;
134+ struct i915_request *rq;
135+ int err, trials = 0;
136+
137+ i915_gem_ww_ctx_init(&ww, false);
138+retry:
139+ err = i915_gem_object_lock(pkt->bb_vma->obj, &ww);
140+ if (err)
141+ goto out_ww;
142+ err = i915_gem_object_lock(pkt->heci_pkt_vma->obj, &ww);
143+ if (err)
144+ goto out_ww;
145+ err = intel_context_pin_ww(ce, &ww);
146+ if (err)
147+ goto out_ww;
148+
149+ rq = i915_request_create(ce);
150+ if (IS_ERR(rq)) {
151+ err = PTR_ERR(rq);
152+ goto out_unpin_ce;
153+ }
154+
155+ emit_gsc_heci_pkt_nonpriv(cmd, pkt);
156+
157+ err = i915_vma_move_to_active(pkt->bb_vma, rq, 0);
158+ if (err)
159+ goto out_rq;
160+ err = i915_vma_move_to_active(pkt->heci_pkt_vma, rq, EXEC_OBJECT_WRITE);
161+ if (err)
162+ goto out_rq;
163+
164+ engine = rq->context->engine;
165+ if (engine->emit_init_breadcrumb) {
166+ err = engine->emit_init_breadcrumb(rq);
167+ if (err)
168+ goto out_rq;
169+ }
170+
171+ err = engine->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0);
172+ if (err)
173+ goto out_rq;
174+
175+ err = ce->engine->emit_flush(rq, 0);
176+ if (err)
177+ drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
178+ "Failed emit-flush for gsc-heci-non-priv-pkterr=%d\n", err);
179+
180+out_rq:
181+ i915_request_get(rq);
182+
183+ if (unlikely(err))
184+ i915_request_set_error_once(rq, err);
185+
186+ i915_request_add(rq);
187+
188+ if (!err) {
189+ if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
190+ msecs_to_jiffies(timeout_ms)) < 0)
191+ err = -ETIME;
192+ }
193+
194+ i915_request_put(rq);
195+
196+out_unpin_ce:
197+ intel_context_unpin(ce);
198+out_ww:
199+ if (err == -EDEADLK) {
200+ err = i915_gem_ww_ctx_backoff(&ww);
201+ if (!err) {
202+ if (++trials < 10)
203+ goto retry;
204+ else
205+ err = EAGAIN;
206+ }
207+ }
208+ i915_gem_ww_ctx_fini(&ww);
209+
210+ return err;
211+}
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h+26−1
@@ -8,12 +8,16 @@ · 7 unmodified lines
88
99 #include <linux/types.h>
1010
11+struct i915_vma;
12+struct intel_context;
1113 struct intel_gsc_uc;
14+
1215 struct intel_gsc_mtl_header {
1316 u32 validity_marker;
1417 #define GSC_HECI_VALIDITY_MARKER 0xA578875A
1518
1619 u8 heci_client_id;
20+#define HECI_MEADDRESS_PROXY 10
1721 #define HECI_MEADDRESS_PXP 17
1822 #define HECI_MEADDRESS_HDCP 18
1923
@@ -47,7 +51,8 @@ struct intel_gsc_mtl_header { · 27 unmodified lines
4751 * we distinguish the flags using OUTFLAG or INFLAG
4852 */
4953 u32 flags;
50−#define GSC_OUTFLAG_MSG_PENDING 1
54+#define GSC_OUTFLAG_MSG_PENDING BIT(0)
55+#define GSC_INFLAG_MSG_CLEANUP BIT(1)
5156
5257 u32 status;
5358 } __packed;
@@ -58,4 +63,24 @@ int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, · 4 unmodified lines
5863 void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
5964 u8 heci_client_id, u32 message_size,
6065 u64 host_session_id);
66+
67+struct intel_gsc_heci_non_priv_pkt {
68+ u64 addr_in;
69+ u32 size_in;
70+ u64 addr_out;
71+ u32 size_out;
72+ struct i915_vma *heci_pkt_vma;
73+ struct i915_vma *bb_vma;
74+};
75+
76+void
77+intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
78+ u8 heci_client_id, u32 msg_size,
79+ u64 host_session_id);
80+
81+int
82+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
83+ struct intel_context *ce,
84+ struct intel_gsc_heci_non_priv_pkt *pkt,
85+ u32 *cs, int timeout_ms);
6186 #endif
drivers/gpu/drm/i915/gt/uc/intel_guc.c+7−0
@@ -744,6 +744,13 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) · 743 unmodified lines
744744 if (IS_ERR(obj))
745745 return ERR_CAST(obj);
746746
747+ /*
748+ * Wa_22016122933: For MTL the shared memory needs to be mapped
749+ * as WC on CPU side and UC (PAT index 2) on GPU side
750+ */
751+ if (IS_METEORLAKE(gt->i915))
752+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
753+
747754 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
748755 if (IS_ERR(vma))
749756 goto err;
drivers/gpu/drm/i915/gt/uc/intel_guc.h+1−0
@@ -42,6 +42,7 @@ struct intel_guc { · 41 unmodified lines
4242 /** @capture: the error-state-capture module's data and objects */
4343 struct intel_guc_state_capture *capture;
4444
45+ /** @dbgfs_node: debugfs node */
4546 struct dentry *dbgfs_node;
4647
4748 /** @sched_engine: Global engine used to submit requests to GuC */
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c+35−1
@@ -643,6 +643,39 @@ static void guc_init_golden_context(struct intel_guc *guc) · 642 unmodified lines
643643 GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
644644 }
645645
646+static u32 guc_get_capture_engine_mask(struct iosys_map *info_map, u32 capture_class)
647+{
648+ u32 mask;
649+
650+ switch (capture_class) {
651+ case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
652+ mask = info_map_read(info_map, engine_enabled_masks[GUC_RENDER_CLASS]);
653+ mask |= info_map_read(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]);
654+ break;
655+
656+ case GUC_CAPTURE_LIST_CLASS_VIDEO:
657+ mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEO_CLASS]);
658+ break;
659+
660+ case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
661+ mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]);
662+ break;
663+
664+ case GUC_CAPTURE_LIST_CLASS_BLITTER:
665+ mask = info_map_read(info_map, engine_enabled_masks[GUC_BLITTER_CLASS]);
666+ break;
667+
668+ case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
669+ mask = info_map_read(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]);
670+ break;
671+
672+ default:
673+ mask = 0;
674+ }
675+
676+ return mask;
677+}
678+
646679 static int
647680 guc_capture_prep_lists(struct intel_guc *guc)
648681 {
@@ -678,9 +711,10 @@ guc_capture_prep_lists(struct intel_guc *guc) · 29 unmodified lines
678711
679712 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
680713 for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
714+ u32 engine_mask = guc_get_capture_engine_mask(&info_map, j);
681715
682716 /* null list if we dont have said engine or list */
683− if (!info_map_read(&info_map, engine_enabled_masks[j])) {
717+ if (!engine_mask) {
684718 if (ads_is_mapped) {
685719 ads_blob_write(guc, ads.capture_class[i][j], null_ggtt);
686720 ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt);
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c+121−148
@@ -30,13 +30,15 @@ · 29 unmodified lines
3030 #define COMMON_BASE_GLOBAL \
3131 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
3232
33−#define COMMON_GEN9BASE_GLOBAL \
34− { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
35− { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
33+#define COMMON_GEN8BASE_GLOBAL \
3634 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
3735 { DONE_REG, 0, 0, "DONE_REG" }, \
3836 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
3937
38+#define GEN8_GLOBAL \
39+ { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
40+ { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
41+
4042 #define COMMON_GEN12BASE_GLOBAL \
4143 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
4244 { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
@@ -94,66 +96,65 @@ · 51 unmodified lines
9496 { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \
9597 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" }
9698
97−/* XE_LPD - Global */
98−static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
99+/* XE_LP Global */
100+static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
99101 COMMON_BASE_GLOBAL,
100− COMMON_GEN9BASE_GLOBAL,
102+ COMMON_GEN8BASE_GLOBAL,
101103 COMMON_GEN12BASE_GLOBAL,
102104 };
103105
104−/* XE_LPD - Render / Compute Per-Class */
105−static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
106+/* XE_LP Render / Compute Per-Class */
107+static const struct __guc_mmio_reg_descr xe_lp_rc_class_regs[] = {
106108 COMMON_BASE_HAS_EU,
107109 COMMON_BASE_RENDER,
108110 COMMON_GEN12BASE_RENDER,
109111 };
110112
111−/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
112−static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
113+/* GEN8+ Render / Compute Per-Engine-Instance */
114+static const struct __guc_mmio_reg_descr gen8_rc_inst_regs[] = {
113115 COMMON_BASE_ENGINE_INSTANCE,
114116 };
115117
116−/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */
117−static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {
118+/* GEN8+ Media Decode/Encode Per-Engine-Instance */
119+static const struct __guc_mmio_reg_descr gen8_vd_inst_regs[] = {
118120 COMMON_BASE_ENGINE_INSTANCE,
119121 };
120122
121−/* XE_LPD - Video Enhancement Per-Class */
122−static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = {
123+/* XE_LP Video Enhancement Per-Class */
124+static const struct __guc_mmio_reg_descr xe_lp_vec_class_regs[] = {
123125 COMMON_GEN12BASE_VEC,
124126 };
125127
126−/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */
127−static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {
128+/* GEN8+ Video Enhancement Per-Engine-Instance */
129+static const struct __guc_mmio_reg_descr gen8_vec_inst_regs[] = {
128130 COMMON_BASE_ENGINE_INSTANCE,
129131 };
130132
131−/* GEN9/XE_LPD - Blitter Per-Engine-Instance */
132−static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
133+/* GEN8+ Blitter Per-Engine-Instance */
134+static const struct __guc_mmio_reg_descr gen8_blt_inst_regs[] = {
133135 COMMON_BASE_ENGINE_INSTANCE,
134136 };
135137
136−/* XE_LPD - GSC Per-Engine-Instance */
137−static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
138+/* XE_LP - GSC Per-Engine-Instance */
139+static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
138140 COMMON_BASE_ENGINE_INSTANCE,
139141 };
140142
141−/* GEN9 - Global */
142−static const struct __guc_mmio_reg_descr default_global_regs[] = {
143+/* GEN8 - Global */
144+static const struct __guc_mmio_reg_descr gen8_global_regs[] = {
143145 COMMON_BASE_GLOBAL,
144− COMMON_GEN9BASE_GLOBAL,
146+ COMMON_GEN8BASE_GLOBAL,
147+ GEN8_GLOBAL,
145148 };
146149
147−static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
150+static const struct __guc_mmio_reg_descr gen8_rc_class_regs[] = {
148151 COMMON_BASE_HAS_EU,
149152 COMMON_BASE_RENDER,
150153 };
151154
152155 /*
153− * Empty lists:
154− * GEN9/XE_LPD - Blitter Per-Class
155− * GEN9/XE_LPD - Media Decode/Encode Per-Class
156− * GEN9 - VEC Class
156+ * Empty list to prevent warnings about unknown class/instance types
157+ * as not all class/instanace types have entries on all platforms.
157158 */
158159 static const struct __guc_mmio_reg_descr empty_regs_list[] = {
159160 };
@@ -171,37 +172,33 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { · 11 unmodified lines
171172 }
172173
173174 /* List of lists */
174−static const struct __guc_mmio_reg_descr_group default_lists[] = {
175− MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
176− MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
177− MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
178− MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
179− MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
180− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
181− MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
182− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
183− MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
184− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
185− MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
186− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
187− MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
175+static const struct __guc_mmio_reg_descr_group gen8_lists[] = {
176+ MAKE_REGLIST(gen8_global_regs, PF, GLOBAL, 0),
177+ MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
178+ MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
179+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
180+ MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
181+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
182+ MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
183+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
184+ MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
185+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
186+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
188187 {}
189188 };
190189
191−static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {
192− MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0),
193− MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
194− MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
195− MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
196− MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
197− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
198− MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
199− MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
200− MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
201− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
202− MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
203− MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
204− MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
190+static const struct __guc_mmio_reg_descr_group xe_lp_lists[] = {
191+ MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
192+ MAKE_REGLIST(xe_lp_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
193+ MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
194+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
195+ MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
196+ MAKE_REGLIST(xe_lp_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
197+ MAKE_REGLIST(gen8_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
198+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
199+ MAKE_REGLIST(gen8_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
200+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
201+ MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
205202 {}
206203 };
207204
@@ -257,11 +254,15 @@ struct __ext_steer_reg { · 49 unmodified lines
257254 i915_mcr_reg_t reg;
258255 };
259256
260−static const struct __ext_steer_reg xe_extregs[] = {
257+static const struct __ext_steer_reg gen8_extregs[] = {
261258 {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
262259 {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
263260 };
264261
262+static const struct __ext_steer_reg xehpg_extregs[] = {
263+ {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
264+};
265+
265266 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
266267 const struct __ext_steer_reg *extlist,
267268 int slice_id, int subslice_id)
@@ -292,8 +293,8 @@ __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, · 24 unmodified lines
292293 }
293294
294295 static void
295−guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc,
296− const struct __guc_mmio_reg_descr_group *lists)
296+guc_capture_alloc_steered_lists(struct intel_guc *guc,
297+ const struct __guc_mmio_reg_descr_group *lists)
297298 {
298299 struct intel_gt *gt = guc_to_gt(guc);
299300 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0;
@@ -301,74 +302,20 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, · 1 unmodified line
301302 struct __guc_mmio_reg_descr_group *extlists;
302303 struct __guc_mmio_reg_descr *extarray;
303304 struct sseu_dev_info *sseu;
305+ bool has_xehpg_extregs;
304306
305− /* In XE_LPD we only have steered registers for the render-class */
307+ /* steered registers currently only exist for the render-class */
306308 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
307− GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);
309+ GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
310+ GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE);
308311 /* skip if extlists was previously allocated */
309312 if (!list || guc->capture->extlists)
310313 return;
311314
312− num_steer_regs = ARRAY_SIZE(xe_extregs);
313−
314− sseu = &gt->info.sseu;
315− for_each_ss_steering(iter, gt, slice, subslice)
316− num_tot_regs += num_steer_regs;
317−
318− if (!num_tot_regs)
319− return;
320−
321− /* allocate an extra for an end marker */
322− extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL);
323− if (!extlists)
324− return;
315+ has_xehpg_extregs = GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55);
325316
326− if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {
327− kfree(extlists);
328− return;
329− }
330−
331− extarray = extlists[0].extlist;
332− for_each_ss_steering(iter, gt, slice, subslice) {
333− for (i = 0; i < num_steer_regs; ++i) {
334− __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
335− ++extarray;
336− }
337− }
338−
339− guc->capture->extlists = extlists;
340−}
341−
342−static const struct __ext_steer_reg xehpg_extregs[] = {
343− {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
344−};
345−
346−static bool __has_xehpg_extregs(u32 ipver)
347−{
348− return (ipver >= IP_VER(12, 55));
349−}
350−
351−static void
352−guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
353− const struct __guc_mmio_reg_descr_group *lists,
354− u32 ipver)
355−{
356− struct intel_gt *gt = guc_to_gt(guc);
357− struct sseu_dev_info *sseu;
358− int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
359− const struct __guc_mmio_reg_descr_group *list;
360− struct __guc_mmio_reg_descr_group *extlists;
361− struct __guc_mmio_reg_descr *extarray;
362−
363− /* In XE_LP / HPG we only have render-class steering registers during error-capture */
364− list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
365− GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);
366− /* skip if extlists was previously allocated */
367− if (!list || guc->capture->extlists)
368− return;
369−
370− num_steer_regs = ARRAY_SIZE(xe_extregs);
371− if (__has_xehpg_extregs(ipver))
317+ num_steer_regs = ARRAY_SIZE(gen8_extregs);
318+ if (has_xehpg_extregs)
372319 num_steer_regs += ARRAY_SIZE(xehpg_extregs);
373320
374321 sseu = &gt->info.sseu;
@@ -390,11 +337,12 @@ guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, · 15 unmodified lines
390337
391338 extarray = extlists[0].extlist;
392339 for_each_ss_steering(iter, gt, slice, subslice) {
393− for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {
394− __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
340+ for (i = 0; i < ARRAY_SIZE(gen8_extregs); ++i) {
341+ __fill_ext_reg(extarray, &gen8_extregs[i], slice, subslice);
395342 ++extarray;
396343 }
397− if (__has_xehpg_extregs(ipver)) {
344+
345+ if (has_xehpg_extregs) {
398346 for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {
399347 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);
400348 ++extarray;
@@ -410,26 +358,22 @@ static const struct __guc_mmio_reg_descr_group * · 9 unmodified lines
410358 guc_capture_get_device_reglist(struct intel_guc *guc)
411359 {
412360 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
361+ const struct __guc_mmio_reg_descr_group *lists;
413362
414− if (GRAPHICS_VER(i915) > 11) {
415− /*
416− * For certain engine classes, there are slice and subslice
417− * level registers requiring steering. We allocate and populate
418− * these at init time based on hw config add it as an extension
419− * list at the end of the pre-populated render list.
420− */
421− if (IS_DG2(i915))
422− guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55));
423− else if (IS_XEHPSDV(i915))
424− guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50));
425− else
426− guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);
363+ if (GRAPHICS_VER(i915) >= 12)
364+ lists = xe_lp_lists;
365+ else
366+ lists = gen8_lists;
427367
428− return xe_lpd_lists;
429− }
368+ /*
369+ * For certain engine classes, there are slice and subslice
370+ * level registers requiring steering. We allocate and populate
371+ * these at init time based on hw config add it as an extension
372+ * list at the end of the pre-populated render list.
373+ */
374+ guc_capture_alloc_steered_lists(guc, lists);
430375
431− /* if GuC submission is enabled on a non-POR platform, just use a common baseline */
432− return default_lists;
376+ return lists;
433377 }
434378
435379 static const char *
@@ -453,17 +397,15 @@ static const char * · 17 unmodified lines
453397 __stringify_engclass(u32 class)
454398 {
455399 switch (class) {
456− case GUC_RENDER_CLASS:
457− return "Render";
458− case GUC_VIDEO_CLASS:
400+ case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE:
401+ return "Render/Compute";
402+ case GUC_CAPTURE_LIST_CLASS_VIDEO:
459403 return "Video";
460− case GUC_VIDEOENHANCE_CLASS:
404+ case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE:
461405 return "VideoEnhance";
462− case GUC_BLITTER_CLASS:
406+ case GUC_CAPTURE_LIST_CLASS_BLITTER:
463407 return "Blitter";
464− case GUC_COMPUTE_CLASS:
465− return "Compute";
466− case GUC_GSC_OTHER_CLASS:
408+ case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
467409 return "GSC-Other";
468410 default:
469411 break;
@@ -1593,6 +1535,36 @@ void intel_guc_capture_free_node(struct intel_engine_coredump *ee) · 1123 unmodified lines
15931535 ee->guc_capture_node = NULL;
15941536 }
15951537
1538+bool intel_guc_capture_is_matching_engine(struct intel_gt *gt,
1539+ struct intel_context *ce,
1540+ struct intel_engine_cs *engine)
1541+{
1542+ struct __guc_capture_parsed_output *n;
1543+ struct intel_guc *guc;
1544+
1545+ if (!gt || !ce || !engine)
1546+ return false;
1547+
1548+ guc = &gt->uc.guc;
1549+ if (!guc->capture)
1550+ return false;
1551+
1552+ /*
1553+ * Look for a matching GuC reported error capture node from
1554+ * the internal output link-list based on lrca, guc-id and engine
1555+ * identification.
1556+ */
1557+ list_for_each_entry(n, &guc->capture->outlist, link) {
1558+ if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(engine->guc_id) &&
1559+ n->eng_class == GUC_ID_TO_ENGINE_CLASS(engine->guc_id) &&
1560+ n->guc_id == ce->guc_id.id &&
1561+ (n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK))
1562+ return true;
1563+ }
1564+
1565+ return false;
1566+}
1567+
15961568 void intel_guc_capture_get_matching_node(struct intel_gt *gt,
15971569 struct intel_engine_coredump *ee,
15981570 struct intel_context *ce)
@@ -1608,6 +1580,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt, · 9 unmodified lines
16081580 return;
16091581
16101582 GEM_BUG_ON(ee->guc_capture_node);
1583+
16111584 /*
16121585 * Look for a matching GuC reported error capture node from
16131586 * the internal output link-list based on lrca, guc-id and engine
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h+3−0
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 struct drm_i915_error_state_buf;
1212 struct guc_gt_system_info;
1313 struct intel_engine_coredump;
14+struct intel_engine_cs;
1415 struct intel_context;
1516 struct intel_gt;
1617 struct intel_guc;
@@ -20,6 +21,8 @@ int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *m, · 3 unmodified lines
2021 const struct intel_engine_coredump *ee);
2122 void intel_guc_capture_get_matching_node(struct intel_gt *gt, struct intel_engine_coredump *ee,
2223 struct intel_context *ce);
24+bool intel_guc_capture_is_matching_engine(struct intel_gt *gt, struct intel_context *ce,
25+ struct intel_engine_cs *engine);
2326 void intel_guc_capture_process(struct intel_guc *guc);
2427 int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
2528 void **outptr);
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c+59−0
@@ -13,6 +13,30 @@ · 12 unmodified lines
1313 #include "intel_guc_ct.h"
1414 #include "intel_guc_print.h"
1515
16+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
17+enum {
18+ CT_DEAD_ALIVE = 0,
19+ CT_DEAD_SETUP,
20+ CT_DEAD_WRITE,
21+ CT_DEAD_DEADLOCK,
22+ CT_DEAD_H2G_HAS_ROOM,
23+ CT_DEAD_READ,
24+ CT_DEAD_PROCESS_FAILED,
25+};
26+
27+static void ct_dead_ct_worker_func(struct work_struct *w);
28+
29+#define CT_DEAD(ct, reason) \
30+ do { \
31+ if (!(ct)->dead_ct_reported) { \
32+ (ct)->dead_ct_reason |= 1 << CT_DEAD_##reason; \
33+ queue_work(system_unbound_wq, &(ct)->dead_ct_worker); \
34+ } \
35+ } while (0)
36+#else
37+#define CT_DEAD(ct, reason) do { } while (0)
38+#endif
39+
1640 static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
1741 {
1842 return container_of(ct, struct intel_guc, ct);
@@ -93,6 +117,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) · 74 unmodified lines
93117 spin_lock_init(&ct->requests.lock);
94118 INIT_LIST_HEAD(&ct->requests.pending);
95119 INIT_LIST_HEAD(&ct->requests.incoming);
120+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
121+ INIT_WORK(&ct->dead_ct_worker, ct_dead_ct_worker_func);
122+#endif
96123 INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
97124 tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func);
98125 init_waitqueue_head(&ct->wq);
@@ -319,11 +346,16 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) · 220 unmodified lines
319346
320347 ct->enabled = true;
321348 ct->stall_time = KTIME_MAX;
349+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
350+ ct->dead_ct_reported = false;
351+ ct->dead_ct_reason = CT_DEAD_ALIVE;
352+#endif
322353
323354 return 0;
324355
325356 err_out:
326357 CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
358+ CT_DEAD(ct, SETUP);
327359 return err;
328360 }
329361
@@ -434,6 +466,7 @@ static int ct_write(struct intel_guc_ct *ct, · 104 unmodified lines
434466 corrupted:
435467 CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
436468 desc->head, desc->tail, desc->status);
469+ CT_DEAD(ct, WRITE);
437470 ctb->broken = true;
438471 return -EPIPE;
439472 }
@@ -504,6 +537,7 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) · 64 unmodified lines
504537 CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
505538 CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
506539
540+ CT_DEAD(ct, DEADLOCK);
507541 ct->ctbs.send.broken = true;
508542 }
509543
@@ -552,6 +586,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) · 42 unmodified lines
552586 head, ctb->size);
553587 desc->status |= GUC_CTB_STATUS_OVERFLOW;
554588 ctb->broken = true;
589+ CT_DEAD(ct, H2G_HAS_ROOM);
555590 return false;
556591 }
557592
@@ -902,12 +937,19 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) · 344 unmodified lines
902937 /* now update descriptor */
903938 WRITE_ONCE(desc->head, head);
904939
940+ /*
941+ * Wa_22016122933: Making sure the head update is
942+ * visible to GuC right away
943+ */
944+ intel_guc_write_barrier(ct_to_guc(ct));
945+
905946 return available - len;
906947
907948 corrupted:
908949 CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
909950 desc->head, desc->tail, desc->status);
910951 ctb->broken = true;
952+ CT_DEAD(ct, READ);
911953 return -EPIPE;
912954 }
913955
@@ -1057,6 +1099,7 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct) · 143 unmodified lines
10571099 if (unlikely(err)) {
10581100 CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
10591101 ERR_PTR(err), 4 * request->size, request->msg);
1102+ CT_DEAD(ct, PROCESS_FAILED);
10601103 ct_free_msg(request);
10611104 }
10621105
@@ -1233,3 +1276,19 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, · 170 unmodified lines
12331276 drm_printf(p, "Tail: %u\n",
12341277 ct->ctbs.recv.desc->tail);
12351278 }
1279+
1280+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
1281+static void ct_dead_ct_worker_func(struct work_struct *w)
1282+{
1283+ struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, dead_ct_worker);
1284+ struct intel_guc *guc = ct_to_guc(ct);
1285+
1286+ if (ct->dead_ct_reported)
1287+ return;
1288+
1289+ ct->dead_ct_reported = true;
1290+
1291+ guc_info(guc, "CTB is dead - reason=0x%X\n", ct->dead_ct_reason);
1292+ intel_klog_error_capture(guc_to_gt(guc), (intel_engine_mask_t)~0U);
1293+}
1294+#endif
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h+6−0
@@ -85,6 +85,12 @@ struct intel_guc_ct { · 84 unmodified lines
8585
8686 /** @stall_time: time of first time a CTB submission is stalled */
8787 ktime_t stall_time;
88+
89+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
90+ int dead_ct_reason;
91+ bool dead_ct_reported;
92+ struct work_struct dead_ct_worker;
93+#endif
8894 };
8995
9096 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c+10−2
@@ -129,6 +129,7 @@ static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool · 128 unmodified lines
129129 case INTEL_BOOTROM_STATUS_RC6CTXCONFIG_FAILED:
130130 case INTEL_BOOTROM_STATUS_MPUMAP_INCORRECT:
131131 case INTEL_BOOTROM_STATUS_EXCEPTION:
132+ case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
132133 *success = false;
133134 return true;
134135 }
@@ -190,8 +191,10 @@ static int guc_wait_ucode(struct intel_guc *guc) · 55 unmodified lines
190191 if (!ret || !success)
191192 break;
192193
193− guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz\n",
194− count, intel_rps_read_actual_frequency(&uncore->gt->rps));
194+ guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n",
195+ count, intel_rps_read_actual_frequency(&uncore->gt->rps), status,
196+ REG_FIELD_GET(GS_BOOTROM_MASK, status),
197+ REG_FIELD_GET(GS_UKERNEL_MASK, status));
195198 }
196199 after = ktime_get();
197200 delta = ktime_sub(after, before);
@@ -219,6 +222,11 @@ static int guc_wait_ucode(struct intel_guc *guc) · 21 unmodified lines
219222 guc_info(guc, "firmware signature verification failed\n");
220223 ret = -ENOEXEC;
221224 break;
225+
226+ case INTEL_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE:
227+ guc_info(guc, "firmware production part check failure\n");
228+ ret = -ENOEXEC;
229+ break;
222230 }
223231
224232 switch (ukernel) {
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h+10−1
@@ -411,6 +411,15 @@ enum guc_capture_type { · 410 unmodified lines
411411 GUC_CAPTURE_LIST_TYPE_MAX,
412412 };
413413
414+/* Class indecies for capture_class and capture_instance arrays */
415+enum {
416+ GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0,
417+ GUC_CAPTURE_LIST_CLASS_VIDEO = 1,
418+ GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,
419+ GUC_CAPTURE_LIST_CLASS_BLITTER = 3,
420+ GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,
421+};
422+
414423 /* GuC Additional Data Struct */
415424 struct guc_ads {
416425 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
@@ -451,7 +460,7 @@ enum guc_log_buffer_type { · 34 unmodified lines
451460 GUC_MAX_LOG_BUFFER
452461 };
453462
454−/**
463+/*
455464 * struct guc_log_buffer_state - GuC log buffer state
456465 *
457466 * Below state structure is used for coordination of retrieval of GuC firmware
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c+29−11
@@ -277,6 +277,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) · 276 unmodified lines
277277
278278 slpc->max_freq_softlimit = 0;
279279 slpc->min_freq_softlimit = 0;
280+ slpc->ignore_eff_freq = false;
280281 slpc->min_is_rpmax = false;
281282
282283 slpc->boost_freq = 0;
@@ -457,6 +458,29 @@ int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val) · 174 unmodified lines
457458 return ret;
458459 }
459460
461+int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
462+{
463+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
464+ intel_wakeref_t wakeref;
465+ int ret;
466+
467+ mutex_lock(&slpc->lock);
468+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
469+
470+ ret = slpc_set_param(slpc,
471+ SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
472+ val);
473+ if (ret)
474+ guc_probe_error(slpc_to_guc(slpc), "Failed to set efficient freq(%d): %pe\n",
475+ val, ERR_PTR(ret));
476+ else
477+ slpc->ignore_eff_freq = val;
478+
479+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
480+ mutex_unlock(&slpc->lock);
481+ return ret;
482+}
483+
460484 /**
461485 * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
462486 * @slpc: pointer to intel_guc_slpc.
@@ -482,16 +506,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) · 19 unmodified lines
482506 mutex_lock(&slpc->lock);
483507 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
484508
485− /* Ignore efficient freq if lower min freq is requested */
486− ret = slpc_set_param(slpc,
487− SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
488− val < slpc->rp1_freq);
489− if (ret) {
490− guc_probe_error(slpc_to_guc(slpc), "Failed to toggle efficient freq: %pe\n",
491− ERR_PTR(ret));
492− goto out;
493− }
494−
495509 ret = slpc_set_param(slpc,
496510 SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
497511 val);
@@ -499,7 +513,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) · 1 unmodified line
499513 if (!ret)
500514 slpc->min_freq_softlimit = val;
501515
502−out:
503516 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
504517 mutex_unlock(&slpc->lock);
505518
@@ -752,6 +765,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) · 246 unmodified lines
752765 /* Set cached media freq ratio mode */
753766 intel_guc_slpc_set_media_ratio_mode(slpc, slpc->media_ratio_mode);
754767
768+ /* Set cached value of ignore efficient freq */
769+ intel_guc_slpc_set_ignore_eff_freq(slpc, slpc->ignore_eff_freq);
770+
755771 return 0;
756772 }
757773
@@ -821,6 +837,8 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p · 63 unmodified lines
821837 slpc_decode_min_freq(slpc));
822838 drm_printf(p, "\twaitboosts: %u\n",
823839 slpc->num_boosts);
840+ drm_printf(p, "\tBoosts outstanding: %u\n",
841+ atomic_read(&slpc->num_waiters));
824842 }
825843 }
826844
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h+1−0
@@ -46,5 +46,6 @@ void intel_guc_slpc_boost(struct intel_guc_slpc *slpc); · 45 unmodified lines
4646 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
4747 int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
4848 int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);
49+int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
4950
5051 #endif
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h+1−0
@@ -31,6 +31,7 @@ struct intel_guc_slpc { · 30 unmodified lines
3131 /* frequency softlimits */
3232 u32 min_freq_softlimit;
3333 u32 max_freq_softlimit;
34+ bool ignore_eff_freq;
3435
3536 /* cached media ratio mode */
3637 u32 media_ratio_mode;
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c+65−10
@@ -1402,13 +1402,34 @@ static void __update_guc_busyness_stats(struct intel_guc *guc) · 1401 unmodified lines
14021402 spin_unlock_irqrestore(&guc->timestamp.lock, flags);
14031403 }
14041404
1405+static void __guc_context_update_stats(struct intel_context *ce)
1406+{
1407+ struct intel_guc *guc = ce_to_guc(ce);
1408+ unsigned long flags;
1409+
1410+ spin_lock_irqsave(&guc->timestamp.lock, flags);
1411+ lrc_update_runtime(ce);
1412+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
1413+}
1414+
1415+static void guc_context_update_stats(struct intel_context *ce)
1416+{
1417+ if (!intel_context_pin_if_active(ce))
1418+ return;
1419+
1420+ __guc_context_update_stats(ce);
1421+ intel_context_unpin(ce);
1422+}
1423+
14051424 static void guc_timestamp_ping(struct work_struct *wrk)
14061425 {
14071426 struct intel_guc *guc = container_of(wrk, typeof(*guc),
14081427 timestamp.work.work);
14091428 struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
14101429 struct intel_gt *gt = guc_to_gt(guc);
1430+ struct intel_context *ce;
14111431 intel_wakeref_t wakeref;
1432+ unsigned long index;
14121433 int srcu, ret;
14131434
14141435 /*
@@ -1424,6 +1445,10 @@ static void guc_timestamp_ping(struct work_struct *wrk) · 9 unmodified lines
14241445 with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
14251446 __update_guc_busyness_stats(guc);
14261447
1448+ /* adjust context stats for overflow */
1449+ xa_for_each(&guc->context_lookup, index, ce)
1450+ guc_context_update_stats(ce);
1451+
14271452 intel_gt_reset_unlock(gt, srcu);
14281453
14291454 guc_enable_busyness_worker(guc);
@@ -1629,16 +1654,16 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) · 199 unmodified lines
16291654
16301655 static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
16311656 {
1632− if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
1633− return;
1634−
1635− intel_engine_stop_cs(engine);
1636−
16371657 /*
16381658 * Wa_22011802037: In addition to stopping the cs, we need
16391659 * to wait for any pending mi force wakeups
16401660 */
1641− intel_engine_wait_for_pending_mi_fw(engine);
1661+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
1662+ (GRAPHICS_VER(engine->i915) >= 11 &&
1663+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
1664+ intel_engine_stop_cs(engine);
1665+ intel_engine_wait_for_pending_mi_fw(engine);
1666+ }
16421667 }
16431668
16441669 static void guc_reset_nop(struct intel_engine_cs *engine)
@@ -2774,6 +2799,7 @@ static void guc_context_unpin(struct intel_context *ce) · 1129 unmodified lines
27742799 {
27752800 struct intel_guc *guc = ce_to_guc(ce);
27762801
2802+ __guc_context_update_stats(ce);
27772803 unpin_guc_id(guc, ce);
27782804 lrc_unpin(ce);
27792805
@@ -3455,6 +3481,7 @@ static void remove_from_context(struct i915_request *rq) · 675 unmodified lines
34553481 }
34563482
34573483 static const struct intel_context_ops guc_context_ops = {
3484+ .flags = COPS_RUNTIME_CYCLES,
34583485 .alloc = guc_context_alloc,
34593486
34603487 .close = guc_context_close,
@@ -3473,6 +3500,8 @@ static const struct intel_context_ops guc_context_ops = { · 12 unmodified lines
34733500
34743501 .sched_disable = guc_context_sched_disable,
34753502
3503+ .update_stats = guc_context_update_stats,
3504+
34763505 .reset = lrc_reset,
34773506 .destroy = guc_context_destroy,
34783507
@@ -3728,6 +3757,7 @@ static int guc_virtual_context_alloc(struct intel_context *ce) · 249 unmodified lines
37283757 }
37293758
37303759 static const struct intel_context_ops virtual_guc_context_ops = {
3760+ .flags = COPS_RUNTIME_CYCLES,
37313761 .alloc = guc_virtual_context_alloc,
37323762
37333763 .close = guc_context_close,
@@ -3745,6 +3775,7 @@ static const struct intel_context_ops virtual_guc_context_ops = { · 11 unmodified lines
37453775 .exit = guc_virtual_context_exit,
37463776
37473777 .sched_disable = guc_context_sched_disable,
3778+ .update_stats = guc_context_update_stats,
37483779
37493780 .destroy = guc_context_destroy,
37503781
@@ -4697,13 +4728,37 @@ static void capture_error_state(struct intel_guc *guc, · 946 unmodified lines
46974728 {
46984729 struct intel_gt *gt = guc_to_gt(guc);
46994730 struct drm_i915_private *i915 = gt->i915;
4700− struct intel_engine_cs *engine = __context_to_physical_engine(ce);
47014731 intel_wakeref_t wakeref;
4732+ intel_engine_mask_t engine_mask;
4733+
4734+ if (intel_engine_is_virtual(ce->engine)) {
4735+ struct intel_engine_cs *e;
4736+ intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;
4737+
4738+ engine_mask = 0;
4739+ for_each_engine_masked(e, ce->engine->gt, virtual_mask, tmp) {
4740+ bool match = intel_guc_capture_is_matching_engine(gt, ce, e);
4741+
4742+ if (match) {
4743+ intel_engine_set_hung_context(e, ce);
4744+ engine_mask |= e->mask;
4745+ atomic_inc(&i915->gpu_error.reset_engine_count[e->uabi_class]);
4746+ }
4747+ }
4748+
4749+ if (!engine_mask) {
4750+ guc_warn(guc, "No matching physical engine capture for virtual engine context 0x%04X / %s",
4751+ ce->guc_id.id, ce->engine->name);
4752+ engine_mask = ~0U;
4753+ }
4754+ } else {
4755+ intel_engine_set_hung_context(ce->engine, ce);
4756+ engine_mask = ce->engine->mask;
4757+ atomic_inc(&i915->gpu_error.reset_engine_count[ce->engine->uabi_class]);
4758+ }
47024759
4703− intel_engine_set_hung_context(engine, ce);
47044760 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
4705− i915_capture_error_state(gt, engine->mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE);
4706− atomic_inc(&i915->gpu_error.reset_engine_count[engine->uabi_class]);
4761+ i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE);
47074762 }
47084763
47094764 static void guc_context_replay(struct intel_context *ce)
drivers/gpu/drm/i915/gt/uc/intel_uc.c+14−2
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 #include "intel_uc.h"
1919
2020 #include "i915_drv.h"
21+#include "i915_hwmon.h"
2122
2223 static const struct intel_uc_ops uc_ops_off;
2324 static const struct intel_uc_ops uc_ops_on;
@@ -431,6 +432,9 @@ static bool uc_is_wopcm_locked(struct intel_uc *uc) · 407 unmodified lines
431432
432433 static int __uc_check_hw(struct intel_uc *uc)
433434 {
435+ if (uc->fw_table_invalid)
436+ return -EIO;
437+
434438 if (!intel_uc_supports_guc(uc))
435439 return 0;
436440
@@ -461,6 +465,7 @@ static int __uc_init_hw(struct intel_uc *uc) · 24 unmodified lines
461465 struct intel_guc *guc = &uc->guc;
462466 struct intel_huc *huc = &uc->huc;
463467 int ret, attempts;
468+ bool pl1en = false;
464469
465470 GEM_BUG_ON(!intel_uc_supports_guc(uc));
466471 GEM_BUG_ON(!intel_uc_wants_guc(uc));
@@ -491,6 +496,9 @@ static int __uc_init_hw(struct intel_uc *uc) · 24 unmodified lines
491496 else
492497 attempts = 1;
493498
499+ /* Disable a potentially low PL1 power limit to allow freq to be raised */
500+ i915_hwmon_power_max_disable(gt->i915, &pl1en);
501+
494502 intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
495503
496504 while (attempts--) {
@@ -500,7 +508,7 @@ static int __uc_init_hw(struct intel_uc *uc) · 3 unmodified lines
500508 */
501509 ret = __uc_sanitize(uc);
502510 if (ret)
503− goto err_out;
511+ goto err_rps;
504512
505513 intel_huc_fw_upload(huc);
506514 intel_guc_ads_reset(guc);
@@ -547,6 +555,8 @@ static int __uc_init_hw(struct intel_uc *uc) · 40 unmodified lines
547555 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
548556 }
549557
558+ i915_hwmon_power_max_restore(gt->i915, pl1en);
559+
550560 guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
551561 guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
552562
@@ -559,10 +569,12 @@ err_submission: · 6 unmodified lines
559569 intel_guc_submission_disable(guc);
560570 err_log_capture:
561571 __uc_capture_load_err_log(uc);
562−err_out:
572+err_rps:
563573 /* Return GT back to RPn */
564574 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
565575
576+ i915_hwmon_power_max_restore(gt->i915, pl1en);
577+err_out:
566578 __uc_sanitize(uc);
567579
568580 if (!ret) {
drivers/gpu/drm/i915/gt/uc/intel_uc.h+1−0
@@ -36,6 +36,7 @@ struct intel_uc { · 35 unmodified lines
3636 struct drm_i915_gem_object *load_err_log;
3737
3838 bool reset_in_progress;
39+ bool fw_table_invalid;
3940 };
4041
4142 void intel_uc_init_early(struct intel_uc *uc);
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c+154−84
@@ -17,6 +17,12 @@ · 16 unmodified lines
1717 #include "i915_drv.h"
1818 #include "i915_reg.h"
1919
20+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
21+#define UNEXPECTED gt_probe_error
22+#else
23+#define UNEXPECTED gt_notice
24+#endif
25+
2026 static inline struct intel_gt *
2127 ____uc_fw_to_gt(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type)
2228 {
@@ -79,14 +85,15 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, · 56 unmodified lines
7985 * security fixes, etc. to be enabled.
8086 */
8187 #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
82− fw_def(DG2, 0, guc_maj(dg2, 70, 5)) \
83− fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 5)) \
88+ fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 6, 6)) \
89+ fw_def(DG2, 0, guc_maj(dg2, 70, 5, 1)) \
90+ fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 5, 1)) \
8491 fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \
8592 fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \
86− fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 5)) \
93+ fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 5, 1)) \
8794 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \
8895 fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \
89− fw_def(DG1, 0, guc_maj(dg1, 70, 5)) \
96+ fw_def(DG1, 0, guc_maj(dg1, 70, 5, 1)) \
9097 fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
9198 fw_def(TIGERLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
9299 fw_def(JASPERLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \
@@ -140,7 +147,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, · 47 unmodified lines
140147 __stringify(patch_) ".bin"
141148
142149 /* Minor for internal driver use, not part of file name */
143−#define MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_) \
150+#define MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_) \
144151 __MAKE_UC_FW_PATH_MAJOR(prefix_, "guc", major_)
145152
146153 #define MAKE_GUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \
@@ -196,9 +203,9 @@ struct __packed uc_fw_blob { · 49 unmodified lines
196203 { UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
197204 .legacy = true }
198205
199−#define GUC_FW_BLOB(prefix_, major_, minor_) \
200− UC_FW_BLOB_NEW(major_, minor_, 0, false, \
201− MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_))
206+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
207+ UC_FW_BLOB_NEW(major_, minor_, patch_, false, \
208+ MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_, patch_))
202209
203210 #define GUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
204211 UC_FW_BLOB_OLD(major_, minor_, patch_, \
@@ -232,20 +239,22 @@ struct fw_blobs_by_type { · 27 unmodified lines
232239 u32 count;
233240 };
234241
242+static const struct uc_fw_platform_requirement blobs_guc[] = {
243+ INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, GUC_FW_BLOB_MMP)
244+};
245+
246+static const struct uc_fw_platform_requirement blobs_huc[] = {
247+ INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB, HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
248+};
249+
250+static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] = {
251+ [INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
252+ [INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
253+};
254+
235255 static void
236256 __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
237257 {
238− static const struct uc_fw_platform_requirement blobs_guc[] = {
239− INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, GUC_FW_BLOB_MMP)
240− };
241− static const struct uc_fw_platform_requirement blobs_huc[] = {
242− INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB, HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
243− };
244− static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] = {
245− [INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
246− [INTEL_UC_FW_TYPE_HUC] = { blobs_huc, ARRAY_SIZE(blobs_huc) },
247− };
248− static bool verified[INTEL_UC_FW_NUM_TYPES];
249258 const struct uc_fw_platform_requirement *fw_blobs;
250259 enum intel_platform p = INTEL_INFO(i915)->platform;
251260 u32 fw_count;
@@ -285,6 +294,11 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) · 33 unmodified lines
285294 continue;
286295
287296 if (uc_fw->file_selected.path) {
297+ /*
298+ * Continuing an earlier search after a found blob failed to load.
299+ * Once the previously chosen path has been found, clear it out
300+ * and let the search continue from there.
301+ */
288302 if (uc_fw->file_selected.path == blob->path)
289303 uc_fw->file_selected.path = NULL;
290304
@@ -295,6 +309,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) · 4 unmodified lines
295309 uc_fw->file_wanted.path = blob->path;
296310 uc_fw->file_wanted.ver.major = blob->major;
297311 uc_fw->file_wanted.ver.minor = blob->minor;
312+ uc_fw->file_wanted.ver.patch = blob->patch;
298313 uc_fw->loaded_via_gsc = blob->loaded_via_gsc;
299314 found = true;
300315 break;
@@ -304,76 +319,111 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) · 3 unmodified lines
304319 /* Failed to find a match for the last attempt?! */
305320 uc_fw->file_selected.path = NULL;
306321 }
322+}
307323
308− /* make sure the list is ordered as expected */
309− if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified[uc_fw->type]) {
310− verified[uc_fw->type] = true;
324+static bool validate_fw_table_type(struct drm_i915_private *i915, enum intel_uc_fw_type type)
325+{
326+ const struct uc_fw_platform_requirement *fw_blobs;
327+ u32 fw_count;
328+ int i, j;
329+
330+ if (type >= ARRAY_SIZE(blobs_all)) {
331+ drm_err(&i915->drm, "No blob array for %s\n", intel_uc_fw_type_repr(type));
332+ return false;
333+ }
334+
335+ fw_blobs = blobs_all[type].blobs;
336+ fw_count = blobs_all[type].count;
337+
338+ if (!fw_count)
339+ return true;
311340
312− for (i = 1; i < fw_count; i++) {
313− /* Next platform is good: */
314− if (fw_blobs[i].p < fw_blobs[i - 1].p)
341+ /* make sure the list is ordered as expected */
342+ for (i = 1; i < fw_count; i++) {
343+ /* Versionless file names must be unique per platform: */
344+ for (j = i + 1; j < fw_count; j++) {
345+ /* Same platform? */
346+ if (fw_blobs[i].p != fw_blobs[j].p)
315347 continue;
316348
317− /* Next platform revision is good: */
318− if (fw_blobs[i].p == fw_blobs[i - 1].p &&
319− fw_blobs[i].rev < fw_blobs[i - 1].rev)
349+ if (fw_blobs[i].blob.path != fw_blobs[j].blob.path)
320350 continue;
321351
322− /* Platform/revision must be in order: */
323− if (fw_blobs[i].p != fw_blobs[i - 1].p ||
324− fw_blobs[i].rev != fw_blobs[i - 1].rev)
325− goto bad;
352+ drm_err(&i915->drm, "Duplicate %s blobs: %s r%u %s%d.%d.%d [%s] matches %s%d.%d.%d [%s]\n",
353+ intel_uc_fw_type_repr(type),
354+ intel_platform_name(fw_blobs[j].p), fw_blobs[j].rev,
355+ fw_blobs[j].blob.legacy ? "L" : "v",
356+ fw_blobs[j].blob.major, fw_blobs[j].blob.minor,
357+ fw_blobs[j].blob.patch, fw_blobs[j].blob.path,
358+ fw_blobs[i].blob.legacy ? "L" : "v",
359+ fw_blobs[i].blob.major, fw_blobs[i].blob.minor,
360+ fw_blobs[i].blob.patch, fw_blobs[i].blob.path);
361+ }
326362
327− /* Next major version is good: */
328− if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
329− continue;
363+ /* Next platform is good: */
364+ if (fw_blobs[i].p < fw_blobs[i - 1].p)
365+ continue;
330366
331− /* New must be before legacy: */
332− if (!fw_blobs[i].blob.legacy && fw_blobs[i - 1].blob.legacy)
333− goto bad;
367+ /* Next platform revision is good: */
368+ if (fw_blobs[i].p == fw_blobs[i - 1].p &&
369+ fw_blobs[i].rev < fw_blobs[i - 1].rev)
370+ continue;
334371
335− /* New to legacy also means 0.0 to X.Y (HuC), or X.0 to X.Y (GuC) */
336− if (fw_blobs[i].blob.legacy && !fw_blobs[i - 1].blob.legacy) {
337− if (!fw_blobs[i - 1].blob.major)
338− continue;
372+ /* Platform/revision must be in order: */
373+ if (fw_blobs[i].p != fw_blobs[i - 1].p ||
374+ fw_blobs[i].rev != fw_blobs[i - 1].rev)
375+ goto bad;
339376
340− if (fw_blobs[i].blob.major == fw_blobs[i - 1].blob.major)
341− continue;
342− }
377+ /* Next major version is good: */
378+ if (fw_blobs[i].blob.major < fw_blobs[i - 1].blob.major)
379+ continue;
343380
344− /* Major versions must be in order: */
345− if (fw_blobs[i].blob.major != fw_blobs[i - 1].blob.major)
346− goto bad;
381+ /* New must be before legacy: */
382+ if (!fw_blobs[i].blob.legacy && fw_blobs[i - 1].blob.legacy)
383+ goto bad;
347384
348− /* Next minor version is good: */
349− if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
385+ /* New to legacy also means 0.0 to X.Y (HuC), or X.0 to X.Y (GuC) */
386+ if (fw_blobs[i].blob.legacy && !fw_blobs[i - 1].blob.legacy) {
387+ if (!fw_blobs[i - 1].blob.major)
350388 continue;
351389
352− /* Minor versions must be in order: */
353− if (fw_blobs[i].blob.minor != fw_blobs[i - 1].blob.minor)
354− goto bad;
355−
356− /* Patch versions must be in order: */
357− if (fw_blobs[i].blob.patch <= fw_blobs[i - 1].blob.patch)
390+ if (fw_blobs[i].blob.major == fw_blobs[i - 1].blob.major)
358391 continue;
392+ }
359393
360−bad:
361− drm_err(&i915->drm, "Invalid %s blob order: %s r%u %s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
362− intel_uc_fw_type_repr(uc_fw->type),
363− intel_platform_name(fw_blobs[i - 1].p), fw_blobs[i - 1].rev,
364− fw_blobs[i - 1].blob.legacy ? "L" : "v",
365− fw_blobs[i - 1].blob.major,
366− fw_blobs[i - 1].blob.minor,
367− fw_blobs[i - 1].blob.patch,
368− intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev,
369− fw_blobs[i].blob.legacy ? "L" : "v",
370− fw_blobs[i].blob.major,
371− fw_blobs[i].blob.minor,
372− fw_blobs[i].blob.patch);
394+ /* Major versions must be in order: */
395+ if (fw_blobs[i].blob.major != fw_blobs[i - 1].blob.major)
396+ goto bad;
373397
374− uc_fw->file_selected.path = NULL;
375− }
398+ /* Next minor version is good: */
399+ if (fw_blobs[i].blob.minor < fw_blobs[i - 1].blob.minor)
400+ continue;
401+
402+ /* Minor versions must be in order: */
403+ if (fw_blobs[i].blob.minor != fw_blobs[i - 1].blob.minor)
404+ goto bad;
405+
406+ /* Patch versions must be in order and unique: */
407+ if (fw_blobs[i].blob.patch < fw_blobs[i - 1].blob.patch)
408+ continue;
409+
410+bad:
411+ drm_err(&i915->drm, "Invalid %s blob order: %s r%u %s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
412+ intel_uc_fw_type_repr(type),
413+ intel_platform_name(fw_blobs[i - 1].p), fw_blobs[i - 1].rev,
414+ fw_blobs[i - 1].blob.legacy ? "L" : "v",
415+ fw_blobs[i - 1].blob.major,
416+ fw_blobs[i - 1].blob.minor,
417+ fw_blobs[i - 1].blob.patch,
418+ intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev,
419+ fw_blobs[i].blob.legacy ? "L" : "v",
420+ fw_blobs[i].blob.major,
421+ fw_blobs[i].blob.minor,
422+ fw_blobs[i].blob.patch);
423+ return false;
376424 }
425+
426+ return true;
377427 }
378428
379429 static const char *__override_guc_firmware_path(struct drm_i915_private *i915)
@@ -428,7 +478,8 @@ static void __uc_fw_user_override(struct drm_i915_private *i915, struct intel_uc · 48 unmodified lines
428478 void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
429479 enum intel_uc_fw_type type)
430480 {
431− struct drm_i915_private *i915 = ____uc_fw_to_gt(uc_fw, type)->i915;
481+ struct intel_gt *gt = ____uc_fw_to_gt(uc_fw, type);
482+ struct drm_i915_private *i915 = gt->i915;
432483
433484 /*
434485 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status
@@ -441,6 +492,12 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw, · 6 unmodified lines
441492 uc_fw->type = type;
442493
443494 if (HAS_GT_UC(i915)) {
495+ if (!validate_fw_table_type(i915, type)) {
496+ gt->uc.fw_table_invalid = true;
497+ intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
498+ return;
499+ }
500+
444501 __uc_fw_auto_select(i915, uc_fw);
445502 __uc_fw_user_override(i915, uc_fw);
446503 }
@@ -782,10 +839,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) · 335 unmodified lines
782839 if (uc_fw->file_wanted.ver.major && uc_fw->file_selected.ver.major) {
783840 /* Check the file's major version was as it claimed */
784841 if (uc_fw->file_selected.ver.major != uc_fw->file_wanted.ver.major) {
785− gt_notice(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
786− intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
787− uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor,
788− uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor);
842+ UNEXPECTED(gt, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
843+ intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
844+ uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor,
845+ uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor);
789846 if (!intel_uc_fw_is_overridden(uc_fw)) {
790847 err = -ENOEXEC;
791848 goto fail;
@@ -793,6 +850,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) · 1 unmodified line
793850 } else {
794851 if (uc_fw->file_selected.ver.minor < uc_fw->file_wanted.ver.minor)
795852 old_ver = true;
853+ else if ((uc_fw->file_selected.ver.minor == uc_fw->file_wanted.ver.minor) &&
854+ (uc_fw->file_selected.ver.patch < uc_fw->file_wanted.ver.patch))
855+ old_ver = true;
796856 }
797857 }
798858
@@ -800,12 +860,16 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) · 1 unmodified line
800860 /* Preserve the version that was really wanted */
801861 memcpy(&uc_fw->file_wanted, &file_ideal, sizeof(uc_fw->file_wanted));
802862
803− gt_notice(gt, "%s firmware %s (%d.%d) is recommended, but only %s (%d.%d) was found\n",
804− intel_uc_fw_type_repr(uc_fw->type),
805− uc_fw->file_wanted.path,
806− uc_fw->file_wanted.ver.major, uc_fw->file_wanted.ver.minor,
807− uc_fw->file_selected.path,
808− uc_fw->file_selected.ver.major, uc_fw->file_selected.ver.minor);
863+ UNEXPECTED(gt, "%s firmware %s (%d.%d.%d) is recommended, but only %s (%d.%d.%d) was found\n",
864+ intel_uc_fw_type_repr(uc_fw->type),
865+ uc_fw->file_wanted.path,
866+ uc_fw->file_wanted.ver.major,
867+ uc_fw->file_wanted.ver.minor,
868+ uc_fw->file_wanted.ver.patch,
869+ uc_fw->file_selected.path,
870+ uc_fw->file_selected.ver.major,
871+ uc_fw->file_selected.ver.minor,
872+ uc_fw->file_selected.ver.patch);
809873 gt_info(gt, "Consider updating your linux-firmware pkg or downloading from %s\n",
810874 INTEL_UC_FIRMWARE_URL);
811875 }
@@ -893,9 +957,15 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw) · 81 unmodified lines
893957 pte_flags |= PTE_LM;
894958
895959 if (ggtt->vm.raw_insert_entries)
896− ggtt->vm.raw_insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
960+ ggtt->vm.raw_insert_entries(&ggtt->vm, dummy,
961+ i915_gem_get_pat_index(ggtt->vm.i915,
962+ I915_CACHE_NONE),
963+ pte_flags);
897964 else
898− ggtt->vm.insert_entries(&ggtt->vm, dummy, I915_CACHE_NONE, pte_flags);
965+ ggtt->vm.insert_entries(&ggtt->vm, dummy,
966+ i915_gem_get_pat_index(ggtt->vm.i915,
967+ I915_CACHE_NONE),
968+ pte_flags);
899969 }
900970
901971 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
drivers/gpu/drm/i915/gvt/aperture_gm.c+1−1
@@ -330,7 +330,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu) · 329 unmodified lines
330330 /**
331331 * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU
332332 * @vgpu: vGPU
333− * @param: vGPU creation params
333+ * @conf: vGPU creation params
334334 *
335335 * This function is used to allocate HW resource for a vGPU. User specifies
336336 * the resource configuration through the creation params.
drivers/gpu/drm/i915/i915_active.h+7−7
@@ -49,9 +49,9 @@ void i915_active_noop(struct dma_fence *fence, struct dma_fence_cb *cb); · 48 unmodified lines
4949
5050 /**
5151 * __i915_active_fence_init - prepares the activity tracker for use
52− * @active - the active tracker
53− * @fence - initial fence to track, can be NULL
54− * @func - a callback when then the tracker is retired (becomes idle),
52+ * @active: the active tracker
53+ * @fence: initial fence to track, can be NULL
54+ * @fn: a callback when then the tracker is retired (becomes idle),
5555 * can be NULL
5656 *
5757 * i915_active_fence_init() prepares the embedded @active struct for use as
@@ -77,8 +77,8 @@ __i915_active_fence_set(struct i915_active_fence *active, · 19 unmodified lines
7777
7878 /**
7979 * i915_active_fence_set - updates the tracker to watch the current fence
80− * @active - the active tracker
81− * @rq - the request to watch
80+ * @active: the active tracker
81+ * @rq: the request to watch
8282 *
8383 * i915_active_fence_set() watches the given @rq for completion. While
8484 * that @rq is busy, the @active reports busy. When that @rq is signaled
@@ -89,7 +89,7 @@ i915_active_fence_set(struct i915_active_fence *active, · 4 unmodified lines
8989 struct i915_request *rq);
9090 /**
9191 * i915_active_fence_get - return a reference to the active fence
92− * @active - the active tracker
92+ * @active: the active tracker
9393 *
9494 * i915_active_fence_get() returns a reference to the active fence,
9595 * or NULL if the active tracker is idle. The reference is obtained under RCU,
@@ -111,7 +111,7 @@ i915_active_fence_get(struct i915_active_fence *active) · 15 unmodified lines
111111
112112 /**
113113 * i915_active_fence_isset - report whether the active tracker is assigned
114− * @active - the active tracker
114+ * @active: the active tracker
115115 *
116116 * i915_active_fence_isset() returns true if the active tracker is currently
117117 * assigned to a fence. Due to the lazy retiring, that fence may be idle
drivers/gpu/drm/i915/i915_debugfs.c+43−10
@@ -139,21 +139,54 @@ static const char *stringify_vma_type(const struct i915_vma *vma) · 138 unmodified lines
139139 return "ppgtt";
140140 }
141141
142−static const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
143−{
144− switch (type) {
145− case I915_CACHE_NONE: return " uncached";
146− case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
147− case I915_CACHE_L3_LLC: return " L3+LLC";
148− case I915_CACHE_WT: return " WT";
149− default: return "";
142+static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
143+{
144+ struct drm_i915_private *i915 = obj_to_i915(obj);
145+
146+ if (IS_METEORLAKE(i915)) {
147+ switch (obj->pat_index) {
148+ case 0: return " WB";
149+ case 1: return " WT";
150+ case 2: return " UC";
151+ case 3: return " WB (1-Way Coh)";
152+ case 4: return " WB (2-Way Coh)";
153+ default: return " not defined";
154+ }
155+ } else if (IS_PONTEVECCHIO(i915)) {
156+ switch (obj->pat_index) {
157+ case 0: return " UC";
158+ case 1: return " WC";
159+ case 2: return " WT";
160+ case 3: return " WB";
161+ case 4: return " WT (CLOS1)";
162+ case 5: return " WB (CLOS1)";
163+ case 6: return " WT (CLOS2)";
164+ case 7: return " WT (CLOS2)";
165+ default: return " not defined";
166+ }
167+ } else if (GRAPHICS_VER(i915) >= 12) {
168+ switch (obj->pat_index) {
169+ case 0: return " WB";
170+ case 1: return " WC";
171+ case 2: return " WT";
172+ case 3: return " UC";
173+ default: return " not defined";
174+ }
175+ } else {
176+ switch (obj->pat_index) {
177+ case 0: return " UC";
178+ case 1: return HAS_LLC(i915) ?
179+ " LLC" : " snooped";
180+ case 2: return " L3+LLC";
181+ case 3: return " WT";
182+ default: return " not defined";
183+ }
150184 }
151185 }
152186
153187 void
154188 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
155189 {
156− struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
157190 struct i915_vma *vma;
158191 int pin_count = 0;
159192
@@ -165,7 +198,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) · 5 unmodified lines
165198 obj->base.size / 1024,
166199 obj->read_domains,
167200 obj->write_domain,
168− i915_cache_level_str(dev_priv, obj->cache_level),
201+ i915_cache_level_str(obj),
169202 obj->mm.dirty ? " dirty" : "",
170203 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
171204 if (obj->base.name)
drivers/gpu/drm/i915/i915_drm_client.c+1−5
@@ -147,11 +147,7 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct file *f) · 146 unmodified lines
147147 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
148148 seq_printf(m, "drm-client-id:\t%u\n", client->id);
149149
150− /*
151− * Temporarily skip showing client engine information with GuC submission till
152− * fetching engine busyness is implemented in the GuC submission backend
153− */
154− if (GRAPHICS_VER(i915) < 8 || intel_uc_uses_guc_submission(&i915->gt0.uc))
150+ if (GRAPHICS_VER(i915) < 8)
155151 return;
156152
157153 for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)
drivers/gpu/drm/i915/i915_drv.h+195−196
@@ -382,11 +382,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) · 381 unmodified lines
382382 }
383383
384384 /* Simple iterator over all initialised engines */
385−#define for_each_engine(engine__, dev_priv__, id__) \
385+#define for_each_engine(engine__, gt__, id__) \
386386 for ((id__) = 0; \
387387 (id__) < I915_NUM_ENGINES; \
388388 (id__)++) \
389− for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
389+ for_each_if ((engine__) = (gt__)->engine[(id__)])
390390
391391 /* Iterator over subset of engines selected by mask */
392392 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
@@ -408,13 +408,13 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) · 15 unmodified lines
408408 (engine__) && (engine__)->uabi_class == (class__); \
409409 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
410410
411−#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
411+#define INTEL_INFO(i915) (&(i915)->__info)
412412 #define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
413−#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
413+#define RUNTIME_INFO(i915) (&(i915)->__runtime)
414414 #define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)
415−#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
415+#define DRIVER_CAPS(i915) (&(i915)->caps)
416416
417−#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
417+#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
418418
419419 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
420420
@@ -434,7 +434,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) · 13 unmodified lines
434434 #define IS_DISPLAY_VER(i915, from, until) \
435435 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
436436
437−#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
437+#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
438438
439439 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
440440 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
@@ -519,135 +519,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 78 unmodified lines
519519 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
520520 }
521521
522−#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
523−#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
524−
525−#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
526−#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
527−#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
528−#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
529−#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
530−#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
531−#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
532−#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
533−#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
534−#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
535−#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
536−#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
537−#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
538−#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
539−#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
540−#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
541−#define IS_IRONLAKE_M(dev_priv) \
542− (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
543−#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
544−#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
545−#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
546− INTEL_INFO(dev_priv)->gt == 1)
547−#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
548−#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
549−#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
550−#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
551−#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
552−#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
553−#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
554−#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
555−#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
556−#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
557−#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
558−#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
559− IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
560−#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
561−#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
562−#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
563−#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
564−#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
565−#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
566−#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
567−#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
568−#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
569−
570−#define IS_METEORLAKE_M(dev_priv) \
571− IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
572−#define IS_METEORLAKE_P(dev_priv) \
573− IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
574−#define IS_DG2_G10(dev_priv) \
575− IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
576−#define IS_DG2_G11(dev_priv) \
577− IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
578−#define IS_DG2_G12(dev_priv) \
579− IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
580−#define IS_ADLS_RPLS(dev_priv) \
581− IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
582−#define IS_ADLP_N(dev_priv) \
583− IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
584−#define IS_ADLP_RPLP(dev_priv) \
585− IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
586−#define IS_ADLP_RPLU(dev_priv) \
587− IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
588−#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
589− (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
590−#define IS_BDW_ULT(dev_priv) \
591− IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
592−#define IS_BDW_ULX(dev_priv) \
593− IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
594−#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
595− INTEL_INFO(dev_priv)->gt == 3)
596−#define IS_HSW_ULT(dev_priv) \
597− IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
598−#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
599− INTEL_INFO(dev_priv)->gt == 3)
600−#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
601− INTEL_INFO(dev_priv)->gt == 1)
522+#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
523+#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
524+
525+#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
526+#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
527+#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
528+#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
529+#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
530+#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
531+#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
532+#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
533+#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
534+#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
535+#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
536+#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
537+#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
538+#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
539+#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
540+#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
541+#define IS_IRONLAKE_M(i915) \
542+ (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
543+#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
544+#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
545+#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
546+ INTEL_INFO(i915)->gt == 1)
547+#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
548+#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
549+#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
550+#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
551+#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
552+#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
553+#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
554+#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
555+#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
556+#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
557+#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
558+#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
559+ IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
560+#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
561+#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
562+#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
563+#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
564+#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
565+#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
566+#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
567+#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
568+#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
569+
570+#define IS_METEORLAKE_M(i915) \
571+ IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
572+#define IS_METEORLAKE_P(i915) \
573+ IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
574+#define IS_DG2_G10(i915) \
575+ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
576+#define IS_DG2_G11(i915) \
577+ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
578+#define IS_DG2_G12(i915) \
579+ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
580+#define IS_ADLS_RPLS(i915) \
581+ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
582+#define IS_ADLP_N(i915) \
583+ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
584+#define IS_ADLP_RPLP(i915) \
585+ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
586+#define IS_ADLP_RPLU(i915) \
587+ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
588+#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
589+ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
590+#define IS_BDW_ULT(i915) \
591+ IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
592+#define IS_BDW_ULX(i915) \
593+ IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
594+#define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \
595+ INTEL_INFO(i915)->gt == 3)
596+#define IS_HSW_ULT(i915) \
597+ IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
598+#define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \
599+ INTEL_INFO(i915)->gt == 3)
600+#define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \
601+ INTEL_INFO(i915)->gt == 1)
602602 /* ULX machines are also considered ULT. */
603−#define IS_HSW_ULX(dev_priv) \
604− IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
605−#define IS_SKL_ULT(dev_priv) \
606− IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
607−#define IS_SKL_ULX(dev_priv) \
608− IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
609−#define IS_KBL_ULT(dev_priv) \
610− IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
611−#define IS_KBL_ULX(dev_priv) \
612− IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
613−#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
614− INTEL_INFO(dev_priv)->gt == 2)
615−#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
616− INTEL_INFO(dev_priv)->gt == 3)
617−#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
618− INTEL_INFO(dev_priv)->gt == 4)
619−#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
620− INTEL_INFO(dev_priv)->gt == 2)
621−#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
622− INTEL_INFO(dev_priv)->gt == 3)
623−#define IS_CFL_ULT(dev_priv) \
624− IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
625−#define IS_CFL_ULX(dev_priv) \
626− IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
627−#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
628− INTEL_INFO(dev_priv)->gt == 2)
629−#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
630− INTEL_INFO(dev_priv)->gt == 3)
631−
632−#define IS_CML_ULT(dev_priv) \
633− IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
634−#define IS_CML_ULX(dev_priv) \
635− IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
636−#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
637− INTEL_INFO(dev_priv)->gt == 2)
638−
639−#define IS_ICL_WITH_PORT_F(dev_priv) \
640− IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
641−
642−#define IS_TGL_UY(dev_priv) \
643− IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
603+#define IS_HSW_ULX(i915) \
604+ IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
605+#define IS_SKL_ULT(i915) \
606+ IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
607+#define IS_SKL_ULX(i915) \
608+ IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
609+#define IS_KBL_ULT(i915) \
610+ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
611+#define IS_KBL_ULX(i915) \
612+ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
613+#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \
614+ INTEL_INFO(i915)->gt == 2)
615+#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \
616+ INTEL_INFO(i915)->gt == 3)
617+#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \
618+ INTEL_INFO(i915)->gt == 4)
619+#define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \
620+ INTEL_INFO(i915)->gt == 2)
621+#define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \
622+ INTEL_INFO(i915)->gt == 3)
623+#define IS_CFL_ULT(i915) \
624+ IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
625+#define IS_CFL_ULX(i915) \
626+ IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
627+#define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \
628+ INTEL_INFO(i915)->gt == 2)
629+#define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \
630+ INTEL_INFO(i915)->gt == 3)
631+
632+#define IS_CML_ULT(i915) \
633+ IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
634+#define IS_CML_ULX(i915) \
635+ IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
636+#define IS_CML_GT2(i915) (IS_COMETLAKE(i915) && \
637+ INTEL_INFO(i915)->gt == 2)
638+
639+#define IS_ICL_WITH_PORT_F(i915) \
640+ IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
641+
642+#define IS_TGL_UY(i915) \
643+ IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
644644
645645 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
646646
647−#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
648− (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
649−#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
650− (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
647+#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
648+ (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
649+#define IS_KBL_DISPLAY_STEP(i915, since, until) \
650+ (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
651651
652652 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
653653 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -723,9 +723,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 69 unmodified lines
723723 (IS_PONTEVECCHIO(__i915) && \
724724 IS_GRAPHICS_STEP(__i915, since, until))
725725
726−#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
727−#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
728−#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
726+#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
727+#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
728+#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
729729
730730 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
731731 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
@@ -750,122 +750,121 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 18 unmodified lines
750750 #define CCS_MASK(gt) \
751751 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
752752
753−#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
753+#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
754754
755755 /*
756756 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
757757 * All later gens can run the final buffer from the ppgtt
758758 */
759−#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
759+#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
760760
761−#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
762−#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
763−#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
764−#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
765−#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
766−#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
761+#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
762+#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
763+#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
764+#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
765+#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
766+#define HAS_WT(i915) HAS_EDRAM(i915)
767767
768−#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
768+#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
769769
770−#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
771− (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
772−#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
773− (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
770+#define HAS_LOGICAL_RING_CONTEXTS(i915) \
771+ (INTEL_INFO(i915)->has_logical_ring_contexts)
772+#define HAS_LOGICAL_RING_ELSQ(i915) \
773+ (INTEL_INFO(i915)->has_logical_ring_elsq)
774774
775−#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
775+#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
776776
777−#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
778−#define HAS_PPGTT(dev_priv) \
779− (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
780−#define HAS_FULL_PPGTT(dev_priv) \
781− (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
777+#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
778+#define HAS_PPGTT(i915) \
779+ (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
780+#define HAS_FULL_PPGTT(i915) \
781+ (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
782782
783−#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
783+#define HAS_PAGE_SIZES(i915, sizes) ({ \
784784 GEM_BUG_ON((sizes) == 0); \
785− ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
785+ ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
786786 })
787787
788788 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
789−#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
789+#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
790790
791−#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
792− (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
791+#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
792+ (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
793793
794794 /* WaRsDisableCoarsePowerGating:skl,cnl */
795−#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
796− (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
795+#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
796+ (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
797797
798798 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
799799 * rows, which changed the alignment requirements and fence programming.
800800 */
801−#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
802− !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
801+#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
802+ !(IS_I915G(i915) || IS_I915GM(i915)))
803803
804+#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
805+#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
806+#define HAS_RC6pp(i915) (false) /* HW was never validated */
804807
805−#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
806−#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
807−#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
808+#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
808809
809−#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
810+#define HAS_HECI_PXP(i915) \
811+ (INTEL_INFO(i915)->has_heci_pxp)
810812
811−#define HAS_HECI_PXP(dev_priv) \
812− (INTEL_INFO(dev_priv)->has_heci_pxp)
813+#define HAS_HECI_GSCFI(i915) \
814+ (INTEL_INFO(i915)->has_heci_gscfi)
813815
814−#define HAS_HECI_GSCFI(dev_priv) \
815− (INTEL_INFO(dev_priv)->has_heci_gscfi)
816+#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
816817
817−#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
818+#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
819+#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
818820
819−#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
820−#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
821−
822−#define HAS_OA_BPC_REPORTING(dev_priv) \
823− (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
824−#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
825− (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
826−#define HAS_OAM(dev_priv) \
827− (INTEL_INFO(dev_priv)->has_oam)
821+#define HAS_OA_BPC_REPORTING(i915) \
822+ (INTEL_INFO(i915)->has_oa_bpc_reporting)
823+#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
824+ (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
825+#define HAS_OAM(i915) \
826+ (INTEL_INFO(i915)->has_oam)
828827
829828 /*
830829 * Set this flag, when platform requires 64K GTT page sizes or larger for
831830 * device local memory access.
832831 */
833−#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
832+#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
834833
835834 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
836835 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
837836
838−#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
837+#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
839838
840839 /*
841840 * Platform has the dedicated compression control state for each lmem surfaces
842841 * stored in lmem to support the 3D and media compression formats.
843842 */
844−#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
843+#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
845844
846−#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
845+#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
847846
848−#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
847+#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
849848
850−#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
849+#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
851850
852851 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
853852
854853 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
855854
856855 /* DPF == dynamic parity feature */
857−#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
858−#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
859− 2 : HAS_L3_DPF(dev_priv))
856+#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
857+#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
858+ 2 : HAS_L3_DPF(i915))
860859
861860 /* Only valid when HAS_DISPLAY() is true */
862−#define INTEL_DISPLAY_ENABLED(dev_priv) \
863− (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
864− !(dev_priv)->params.disable_display && \
865− !intel_opregion_headless_sku(dev_priv))
861+#define INTEL_DISPLAY_ENABLED(i915) \
862+ (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
863+ !(i915)->params.disable_display && \
864+ !intel_opregion_headless_sku(i915))
866865
867−#define HAS_GUC_DEPRIVILEGE(dev_priv) \
868− (INTEL_INFO(dev_priv)->has_guc_deprivilege)
866+#define HAS_GUC_DEPRIVILEGE(i915) \
867+ (INTEL_INFO(i915)->has_guc_deprivilege)
869868
870869 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
871870
drivers/gpu/drm/i915/i915_gem.c+23−4
@@ -420,8 +420,11 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, · 419 unmodified lines
420420 page_length = remain < page_length ? remain : page_length;
421421 if (drm_mm_node_allocated(&node)) {
422422 ggtt->vm.insert_page(&ggtt->vm,
423− i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
424− node.start, I915_CACHE_NONE, 0);
423+ i915_gem_object_get_dma_address(obj,
424+ offset >> PAGE_SHIFT),
425+ node.start,
426+ i915_gem_get_pat_index(i915,
427+ I915_CACHE_NONE), 0);
425428 } else {
426429 page_base += offset & PAGE_MASK;
427430 }
@@ -598,8 +601,11 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, · 170 unmodified lines
598601 /* flush the write before we modify the GGTT */
599602 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
600603 ggtt->vm.insert_page(&ggtt->vm,
601− i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
602− node.start, I915_CACHE_NONE, 0);
604+ i915_gem_object_get_dma_address(obj,
605+ offset >> PAGE_SHIFT),
606+ node.start,
607+ i915_gem_get_pat_index(i915,
608+ I915_CACHE_NONE), 0);
603609 wmb(); /* flush modifications to the GGTT (insert_page) */
604610 } else {
605611 page_base += offset & PAGE_MASK;
@@ -1142,6 +1148,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv) · 536 unmodified lines
11421148 unsigned int i;
11431149 int ret;
11441150
1151+ /*
1152+ * In the proccess of replacing cache_level with pat_index a tricky
1153+ * dependency is created on the definition of the enum i915_cache_level.
1154+ * in case this enum is changed, PTE encode would be broken.
1155+ * Add a WARNING here. And remove when we completely quit using this
1156+ * enum
1157+ */
1158+ BUILD_BUG_ON(I915_CACHE_NONE != 0 ||
1159+ I915_CACHE_LLC != 1 ||
1160+ I915_CACHE_L3_LLC != 2 ||
1161+ I915_CACHE_WT != 3 ||
1162+ I915_MAX_CACHE_LEVEL != 4);
1163+
11451164 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
11461165 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
11471166 RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;
drivers/gpu/drm/i915/i915_getparam.c+7−0
@@ -5,6 +5,8 @@ · 4 unmodified lines
55 #include "gem/i915_gem_mman.h"
66 #include "gt/intel_engine_user.h"
77
8+#include "pxp/intel_pxp.h"
9+
810 #include "i915_cmd_parser.h"
911 #include "i915_drv.h"
1012 #include "i915_getparam.h"
@@ -102,6 +104,11 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, · 91 unmodified lines
102104 if (value < 0)
103105 return value;
104106 break;
107+ case I915_PARAM_PXP_STATUS:
108+ value = intel_pxp_get_readiness_status(i915->pxp);
109+ if (value < 0)
110+ return value;
111+ break;
105112 case I915_PARAM_MMAP_GTT_VERSION:
106113 /* Though we've started our numbering from 1, and so class all
107114 * earlier versions as 0, in effect their value is undefined as
drivers/gpu/drm/i915/i915_gpu_error.c+147−6
@@ -808,10 +808,15 @@ static void err_print_gt_engines(struct drm_i915_error_state_buf *m, · 807 unmodified lines
808808 for (ee = gt->engine; ee; ee = ee->next) {
809809 const struct i915_vma_coredump *vma;
810810
811− if (ee->guc_capture_node)
812− intel_guc_capture_print_engine_node(m, ee);
813− else
811+ if (gt->uc && gt->uc->guc.is_guc_capture) {
812+ if (ee->guc_capture_node)
813+ intel_guc_capture_print_engine_node(m, ee);
814+ else
815+ err_printf(m, " Missing GuC capture node for %s\n",
816+ ee->engine->name);
817+ } else {
814818 error_print_engine(m, ee);
819+ }
815820
816821 err_printf(m, " hung: %u\n", ee->hung);
817822 err_printf(m, " engine reset count: %u\n", ee->reset_count);
@@ -1117,10 +1122,14 @@ i915_vma_coredump_create(const struct intel_gt *gt, · 299 unmodified lines
11171122 mutex_lock(&ggtt->error_mutex);
11181123 if (ggtt->vm.raw_insert_page)
11191124 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1120− I915_CACHE_NONE, 0);
1125+ i915_gem_get_pat_index(gt->i915,
1126+ I915_CACHE_NONE),
1127+ 0);
11211128 else
11221129 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1123− I915_CACHE_NONE, 0);
1130+ i915_gem_get_pat_index(gt->i915,
1131+ I915_CACHE_NONE),
1132+ 0);
11241133 mb();
11251134
11261135 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
@@ -2162,7 +2171,7 @@ void i915_error_state_store(struct i915_gpu_coredump *error) · 1035 unmodified lines
21622171 * i915_capture_error_state - capture an error record for later analysis
21632172 * @gt: intel_gt which originated the hang
21642173 * @engine_mask: hung engines
2165− *
2174+ * @dump_flags: dump flags
21662175 *
21672176 * Should be called when an error is detected (either a hang or an error
21682177 * interrupt) to capture error state from the time of the error. Fills
@@ -2219,3 +2228,135 @@ void i915_disable_error_state(struct drm_i915_private *i915, int err) · 50 unmodified lines
22192228 i915->gpu_error.first_error = ERR_PTR(err);
22202229 spin_unlock_irq(&i915->gpu_error.lock);
22212230 }
2231+
2232+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
2233+void intel_klog_error_capture(struct intel_gt *gt,
2234+ intel_engine_mask_t engine_mask)
2235+{
2236+ static int g_count;
2237+ struct drm_i915_private *i915 = gt->i915;
2238+ struct i915_gpu_coredump *error;
2239+ intel_wakeref_t wakeref;
2240+ size_t buf_size = PAGE_SIZE * 128;
2241+ size_t pos_err;
2242+ char *buf, *ptr, *next;
2243+ int l_count = g_count++;
2244+ int line = 0;
2245+
2246+ /* Can't allocate memory during a reset */
2247+ if (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
2248+ drm_err(&gt->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",
2249+ l_count, line++);
2250+ return;
2251+ }
2252+
2253+ error = READ_ONCE(i915->gpu_error.first_error);
2254+ if (error) {
2255+ drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n",
2256+ l_count, line++);
2257+ i915_reset_error_state(i915);
2258+ }
2259+
2260+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
2261+ error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);
2262+
2263+ if (IS_ERR(error)) {
2264+ drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n",
2265+ l_count, line++, PTR_ERR(error));
2266+ return;
2267+ }
2268+
2269+ buf = kvmalloc(buf_size, GFP_KERNEL);
2270+ if (!buf) {
2271+ drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n",
2272+ l_count, line++);
2273+ i915_gpu_coredump_put(error);
2274+ return;
2275+ }
2276+
2277+ drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n",
2278+ l_count, line++, __builtin_return_address(0));
2279+
2280+ /* Largest string length safe to print via dmesg */
2281+# define MAX_CHUNK 800
2282+
2283+ pos_err = 0;
2284+ while (1) {
2285+ ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1);
2286+
2287+ if (got <= 0)
2288+ break;
2289+
2290+ buf[got] = 0;
2291+ pos_err += got;
2292+
2293+ ptr = buf;
2294+ while (got > 0) {
2295+ size_t count;
2296+ char tag[2];
2297+
2298+ next = strnchr(ptr, got, '\n');
2299+ if (next) {
2300+ count = next - ptr;
2301+ *next = 0;
2302+ tag[0] = '>';
2303+ tag[1] = '<';
2304+ } else {
2305+ count = got;
2306+ tag[0] = '}';
2307+ tag[1] = '{';
2308+ }
2309+
2310+ if (count > MAX_CHUNK) {
2311+ size_t pos;
2312+ char *ptr2 = ptr;
2313+
2314+ for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {
2315+ char chr = ptr[pos];
2316+
2317+ ptr[pos] = 0;
2318+ drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n",
2319+ l_count, line++, ptr2);
2320+ ptr[pos] = chr;
2321+ ptr2 = ptr + pos;
2322+
2323+ /*
2324+ * If spewing large amounts of data via a serial console,
2325+ * this can be a very slow process. So be friendly and try
2326+ * not to cause 'softlockup on CPU' problems.
2327+ */
2328+ cond_resched();
2329+ }
2330+
2331+ if (ptr2 < (ptr + count))
2332+ drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2333+ l_count, line++, tag[0], ptr2, tag[1]);
2334+ else if (tag[0] == '>')
2335+ drm_info(&i915->drm, "[Capture/%d.%d] ><\n",
2336+ l_count, line++);
2337+ } else {
2338+ drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2339+ l_count, line++, tag[0], ptr, tag[1]);
2340+ }
2341+
2342+ ptr = next;
2343+ got -= count;
2344+ if (next) {
2345+ ptr++;
2346+ got--;
2347+ }
2348+
2349+ /* As above. */
2350+ cond_resched();
2351+ }
2352+
2353+ if (got)
2354+ drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n",
2355+ l_count, line++, got);
2356+ }
2357+
2358+ kvfree(buf);
2359+
2360+ drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);
2361+}
2362+#endif
drivers/gpu/drm/i915/i915_gpu_error.h+10−0
@@ -258,6 +258,16 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, · 257 unmodified lines
258258 #define CORE_DUMP_FLAG_NONE 0x0
259259 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
260260
261+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
262+void intel_klog_error_capture(struct intel_gt *gt,
263+ intel_engine_mask_t engine_mask);
264+#else
265+static inline void intel_klog_error_capture(struct intel_gt *gt,
266+ intel_engine_mask_t engine_mask)
267+{
268+}
269+#endif
270+
261271 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
262272
263273 __printf(2, 3)
drivers/gpu/drm/i915/i915_hwmon.c+75−12
@@ -50,6 +50,8 @@ struct hwm_drvdata { · 49 unmodified lines
5050 struct hwm_energy_info ei; /* Energy info for energy1_input */
5151 char name[12];
5252 int gt_n;
53+ bool reset_in_progress;
54+ wait_queue_head_t waitq;
5355 };
5456
5557 struct i915_hwmon {
@@ -396,31 +398,56 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) · 340 unmodified lines
396398 {
397399 struct i915_hwmon *hwmon = ddat->hwmon;
398400 intel_wakeref_t wakeref;
401+ DEFINE_WAIT(wait);
402+ int ret = 0;
399403 u32 nval;
400404
401− /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */
402− if (val == PL1_DISABLE) {
405+ /* Block waiting for GuC reset to complete when needed */
406+ for (;;) {
403407 mutex_lock(&hwmon->hwmon_lock);
404− with_intel_runtime_pm(ddat->uncore->rpm, wakeref) {
405− intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
406− PKG_PWR_LIM_1_EN, 0);
407− nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
408+
409+ prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE);
410+
411+ if (!hwmon->ddat.reset_in_progress)
412+ break;
413+
414+ if (signal_pending(current)) {
415+ ret = -EINTR;
416+ break;
408417 }
418+
409419 mutex_unlock(&hwmon->hwmon_lock);
410420
421+ schedule();
422+ }
423+ finish_wait(&ddat->waitq, &wait);
424+ if (ret)
425+ goto unlock;
426+
427+ wakeref = intel_runtime_pm_get(ddat->uncore->rpm);
428+
429+ /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */
430+ if (val == PL1_DISABLE) {
431+ intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
432+ PKG_PWR_LIM_1_EN, 0);
433+ nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
434+
411435 if (nval & PKG_PWR_LIM_1_EN)
412− return -ENODEV;
413− return 0;
436+ ret = -ENODEV;
437+ goto exit;
414438 }
415439
416440 /* Computation in 64-bits to avoid overflow. Round to nearest. */
417441 nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);
418442 nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval);
419443
420− hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
421− PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1,
422− nval);
423− return 0;
444+ intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit,
445+ PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval);
446+exit:
447+ intel_runtime_pm_put(ddat->uncore->rpm, wakeref);
448+unlock:
449+ mutex_unlock(&hwmon->hwmon_lock);
450+ return ret;
424451 }
425452
426453 static int
@@ -470,6 +497,41 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) · 43 unmodified lines
470497 }
471498 }
472499
500+void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old)
501+{
502+ struct i915_hwmon *hwmon = i915->hwmon;
503+ u32 r;
504+
505+ if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
506+ return;
507+
508+ mutex_lock(&hwmon->hwmon_lock);
509+
510+ hwmon->ddat.reset_in_progress = true;
511+ r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
512+ PKG_PWR_LIM_1_EN, 0);
513+ *old = !!(r & PKG_PWR_LIM_1_EN);
514+
515+ mutex_unlock(&hwmon->hwmon_lock);
516+}
517+
518+void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old)
519+{
520+ struct i915_hwmon *hwmon = i915->hwmon;
521+
522+ if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
523+ return;
524+
525+ mutex_lock(&hwmon->hwmon_lock);
526+
527+ intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit,
528+ PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0);
529+ hwmon->ddat.reset_in_progress = false;
530+ wake_up_all(&hwmon->ddat.waitq);
531+
532+ mutex_unlock(&hwmon->hwmon_lock);
533+}
534+
473535 static umode_t
474536 hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
475537 {
@@ -742,6 +804,7 @@ void i915_hwmon_register(struct drm_i915_private *i915) · 266 unmodified lines
742804 ddat->uncore = &i915->uncore;
743805 snprintf(ddat->name, sizeof(ddat->name), "i915");
744806 ddat->gt_n = -1;
807+ init_waitqueue_head(&ddat->waitq);
745808
746809 for_each_gt(gt, i915, i) {
747810 ddat_gt = hwmon->ddat_gt + i;
drivers/gpu/drm/i915/i915_hwmon.h+7−0
@@ -7,14 +7,21 @@ · 6 unmodified lines
77 #ifndef __I915_HWMON_H__
88 #define __I915_HWMON_H__
99
10+#include <linux/types.h>
11+
1012 struct drm_i915_private;
13+struct intel_gt;
1114
1215 #if IS_REACHABLE(CONFIG_HWMON)
1316 void i915_hwmon_register(struct drm_i915_private *i915);
1417 void i915_hwmon_unregister(struct drm_i915_private *i915);
18+void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old);
19+void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old);
1520 #else
1621 static inline void i915_hwmon_register(struct drm_i915_private *i915) { };
1722 static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { };
23+static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { };
24+static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { };
1825 #endif
1926
2027 #endif /* __I915_HWMON_H__ */
drivers/gpu/drm/i915/i915_irq.c+11−6
@@ -738,12 +738,15 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv) · 737 unmodified lines
738738
739739 static void dg1_irq_reset(struct drm_i915_private *dev_priv)
740740 {
741− struct intel_gt *gt = to_gt(dev_priv);
742− struct intel_uncore *uncore = gt->uncore;
741+ struct intel_uncore *uncore = &dev_priv->uncore;
742+ struct intel_gt *gt;
743+ unsigned int i;
743744
744745 dg1_master_intr_disable(dev_priv->uncore.regs);
745746
746− gen11_gt_irq_reset(gt);
747+ for_each_gt(gt, dev_priv, i)
748+ gen11_gt_irq_reset(gt);
749+
747750 gen11_display_irq_reset(dev_priv);
748751
749752 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -856,11 +859,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) · 106 unmodified lines
856859
857860 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
858861 {
859− struct intel_gt *gt = to_gt(dev_priv);
860− struct intel_uncore *uncore = gt->uncore;
862+ struct intel_uncore *uncore = &dev_priv->uncore;
861863 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
864+ struct intel_gt *gt;
865+ unsigned int i;
862866
863− gen11_gt_irq_postinstall(gt);
867+ for_each_gt(gt, dev_priv, i)
868+ gen11_gt_irq_postinstall(gt);
864869
865870 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
866871
drivers/gpu/drm/i915/i915_pci.c+71−9
@@ -30,6 +30,7 @@ · 29 unmodified lines
3030 #include "display/intel_display_driver.h"
3131 #include "gt/intel_gt_regs.h"
3232 #include "gt/intel_sa_media.h"
33+#include "gem/i915_gem_object_types.h"
3334
3435 #include "i915_driver.h"
3536 #include "i915_drv.h"
@@ -42,6 +43,38 @@ · 6 unmodified lines
4243 .__runtime.graphics.ip.ver = (x), \
4344 .__runtime.media.ip.ver = (x)
4445
46+#define LEGACY_CACHELEVEL \
47+ .cachelevel_to_pat = { \
48+ [I915_CACHE_NONE] = 0, \
49+ [I915_CACHE_LLC] = 1, \
50+ [I915_CACHE_L3_LLC] = 2, \
51+ [I915_CACHE_WT] = 3, \
52+ }
53+
54+#define TGL_CACHELEVEL \
55+ .cachelevel_to_pat = { \
56+ [I915_CACHE_NONE] = 3, \
57+ [I915_CACHE_LLC] = 0, \
58+ [I915_CACHE_L3_LLC] = 0, \
59+ [I915_CACHE_WT] = 2, \
60+ }
61+
62+#define PVC_CACHELEVEL \
63+ .cachelevel_to_pat = { \
64+ [I915_CACHE_NONE] = 0, \
65+ [I915_CACHE_LLC] = 3, \
66+ [I915_CACHE_L3_LLC] = 3, \
67+ [I915_CACHE_WT] = 2, \
68+ }
69+
70+#define MTL_CACHELEVEL \
71+ .cachelevel_to_pat = { \
72+ [I915_CACHE_NONE] = 2, \
73+ [I915_CACHE_LLC] = 3, \
74+ [I915_CACHE_L3_LLC] = 3, \
75+ [I915_CACHE_WT] = 1, \
76+ }
77+
4578 /* Keep in gen based order, and chronological order within a gen */
4679
4780 #define GEN_DEFAULT_PAGE_SIZES \
@@ -61,8 +94,10 @@ · 13 unmodified lines
6194 .has_snoop = true, \
6295 .has_coherent_ggtt = false, \
6396 .dma_mask_size = 32, \
97+ .max_pat_index = 3, \
6498 GEN_DEFAULT_PAGE_SIZES, \
65− GEN_DEFAULT_REGIONS
99+ GEN_DEFAULT_REGIONS, \
100+ LEGACY_CACHELEVEL
66101
67102 #define I845_FEATURES \
68103 GEN(2), \
@@ -74,8 +109,10 @@ · 5 unmodified lines
74109 .has_snoop = true, \
75110 .has_coherent_ggtt = false, \
76111 .dma_mask_size = 32, \
112+ .max_pat_index = 3, \
77113 GEN_DEFAULT_PAGE_SIZES, \
78− GEN_DEFAULT_REGIONS
114+ GEN_DEFAULT_REGIONS, \
115+ LEGACY_CACHELEVEL
79116
80117 static const struct intel_device_info i830_info = {
81118 I830_FEATURES,
@@ -105,8 +142,10 @@ static const struct intel_device_info i865g_info = { · 23 unmodified lines
105142 .has_snoop = true, \
106143 .has_coherent_ggtt = true, \
107144 .dma_mask_size = 32, \
145+ .max_pat_index = 3, \
108146 GEN_DEFAULT_PAGE_SIZES, \
109− GEN_DEFAULT_REGIONS
147+ GEN_DEFAULT_REGIONS, \
148+ LEGACY_CACHELEVEL
110149
111150 static const struct intel_device_info i915g_info = {
112151 GEN3_FEATURES,
@@ -166,8 +205,10 @@ static const struct intel_device_info pnv_m_info = { · 53 unmodified lines
166205 .has_snoop = true, \
167206 .has_coherent_ggtt = true, \
168207 .dma_mask_size = 36, \
208+ .max_pat_index = 3, \
169209 GEN_DEFAULT_PAGE_SIZES, \
170− GEN_DEFAULT_REGIONS
210+ GEN_DEFAULT_REGIONS, \
211+ LEGACY_CACHELEVEL
171212
172213 static const struct intel_device_info i965g_info = {
173214 GEN4_FEATURES,
@@ -208,8 +249,10 @@ static const struct intel_device_info gm45_info = { · 34 unmodified lines
208249 /* ilk does support rc6, but we do not implement [power] contexts */ \
209250 .has_rc6 = 0, \
210251 .dma_mask_size = 36, \
252+ .max_pat_index = 3, \
211253 GEN_DEFAULT_PAGE_SIZES, \
212− GEN_DEFAULT_REGIONS
254+ GEN_DEFAULT_REGIONS, \
255+ LEGACY_CACHELEVEL
213256
214257 static const struct intel_device_info ilk_d_info = {
215258 GEN5_FEATURES,
@@ -234,10 +277,12 @@ static const struct intel_device_info ilk_m_info = { · 18 unmodified lines
234277 .has_rc6p = 0, \
235278 .has_rps = true, \
236279 .dma_mask_size = 40, \
280+ .max_pat_index = 3, \
237281 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
238282 .__runtime.ppgtt_size = 31, \
239283 GEN_DEFAULT_PAGE_SIZES, \
240− GEN_DEFAULT_REGIONS
284+ GEN_DEFAULT_REGIONS, \
285+ LEGACY_CACHELEVEL
241286
242287 #define SNB_D_PLATFORM \
243288 GEN6_FEATURES, \
@@ -280,10 +325,12 @@ static const struct intel_device_info snb_m_gt2_info = { · 36 unmodified lines
280325 .has_reset_engine = true, \
281326 .has_rps = true, \
282327 .dma_mask_size = 40, \
328+ .max_pat_index = 3, \
283329 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
284330 .__runtime.ppgtt_size = 31, \
285331 GEN_DEFAULT_PAGE_SIZES, \
286− GEN_DEFAULT_REGIONS
332+ GEN_DEFAULT_REGIONS, \
333+ LEGACY_CACHELEVEL
287334
288335 #define IVB_D_PLATFORM \
289336 GEN7_FEATURES, \
@@ -332,6 +379,7 @@ static const struct intel_device_info vlv_info = { · 42 unmodified lines
332379 .has_reset_engine = true,
333380 .has_rps = true,
334381 .dma_mask_size = 40,
382+ .max_pat_index = 3,
335383 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
336384 .__runtime.ppgtt_size = 31,
337385 .has_snoop = true,
@@ -339,6 +387,7 @@ static const struct intel_device_info vlv_info = { · 1 unmodified line
339387 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
340388 GEN_DEFAULT_PAGE_SIZES,
341389 GEN_DEFAULT_REGIONS,
390+ LEGACY_CACHELEVEL,
342391 };
343392
344393 #define G75_FEATURES \
@@ -416,6 +465,7 @@ static const struct intel_device_info chv_info = { · 71 unmodified lines
416465 .has_rps = true,
417466 .has_logical_ring_contexts = 1,
418467 .dma_mask_size = 39,
468+ .max_pat_index = 3,
419469 .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
420470 .__runtime.ppgtt_size = 32,
421471 .has_reset_engine = 1,
@@ -423,6 +473,7 @@ static const struct intel_device_info chv_info = { · 1 unmodified line
423473 .has_coherent_ggtt = false,
424474 GEN_DEFAULT_PAGE_SIZES,
425475 GEN_DEFAULT_REGIONS,
476+ LEGACY_CACHELEVEL,
426477 };
427478
428479 #define GEN9_DEFAULT_PAGE_SIZES \
@@ -482,8 +533,10 @@ static const struct intel_device_info skl_gt4_info = { · 53 unmodified lines
482533 .has_reset_engine = 1, \
483534 .has_snoop = true, \
484535 .has_coherent_ggtt = false, \
536+ .max_pat_index = 3, \
485537 GEN9_DEFAULT_PAGE_SIZES, \
486− GEN_DEFAULT_REGIONS
538+ GEN_DEFAULT_REGIONS, \
539+ LEGACY_CACHELEVEL
487540
488541 static const struct intel_device_info bxt_info = {
489542 GEN9_LP_FEATURES,
@@ -587,8 +640,10 @@ static const struct intel_device_info jsl_info = { · 97 unmodified lines
587640 #define GEN12_FEATURES \
588641 GEN11_FEATURES, \
589642 GEN(12), \
643+ TGL_CACHELEVEL, \
590644 .has_global_mocs = 1, \
591− .has_pxp = 1
645+ .has_pxp = 1, \
646+ .max_pat_index = 3
592647
593648 static const struct intel_device_info tgl_info = {
594649 GEN12_FEATURES,
@@ -653,6 +708,7 @@ static const struct intel_device_info adl_p_info = { · 58 unmodified lines
653708 .__runtime.graphics.ip.ver = 12, \
654709 .__runtime.graphics.ip.rel = 50, \
655710 XE_HP_PAGE_SIZES, \
711+ TGL_CACHELEVEL, \
656712 .dma_mask_size = 46, \
657713 .has_3d_pipeline = 1, \
658714 .has_64bit_reloc = 1, \
@@ -671,6 +727,7 @@ static const struct intel_device_info adl_p_info = { · 12 unmodified lines
671727 .has_reset_engine = 1, \
672728 .has_rps = 1, \
673729 .has_runtime_pm = 1, \
730+ .max_pat_index = 3, \
674731 .__runtime.ppgtt_size = 48, \
675732 .__runtime.ppgtt_type = INTEL_PPGTT_FULL
676733
@@ -740,11 +797,13 @@ static const struct intel_device_info pvc_info = { · 63 unmodified lines
740797 .__runtime.media.ip.rel = 60,
741798 PLATFORM(INTEL_PONTEVECCHIO),
742799 .has_flat_ccs = 0,
800+ .max_pat_index = 7,
743801 .__runtime.platform_engine_mask =
744802 BIT(BCS0) |
745803 BIT(VCS0) |
746804 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
747805 .require_force_probe = 1,
806+ PVC_CACHELEVEL,
748807 };
749808
750809 static const struct intel_gt_definition xelpmp_extra_gt[] = {
@@ -774,9 +833,12 @@ static const struct intel_device_info mtl_info = { · 23 unmodified lines
774833 .has_llc = 0,
775834 .has_mslice_steering = 0,
776835 .has_snoop = 1,
836+ .max_pat_index = 4,
837+ .has_pxp = 1,
777838 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
778839 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
779840 .require_force_probe = 1,
841+ MTL_CACHELEVEL,
780842 };
781843
782844 #undef PLATFORM
drivers/gpu/drm/i915/i915_perf.c+1−0
@@ -5300,6 +5300,7 @@ void i915_perf_fini(struct drm_i915_private *i915) · 5299 unmodified lines
53005300
53015301 /**
53025302 * i915_perf_ioctl_version - Version of the i915-perf subsystem
5303+ * @i915: The i915 device
53035304 *
53045305 * This version number is used by userspace to detect available features.
53055306 */
drivers/gpu/drm/i915/i915_perf_oa_regs.h+0−4
@@ -134,10 +134,6 @@ · 133 unmodified lines
134134 #define GDT_CHICKEN_BITS _MMIO(0x9840)
135135 #define GT_NOA_ENABLE 0x00000080
136136
137−#define GEN12_SQCNT1 _MMIO(0x8718)
138−#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
139−#define GEN12_SQCNT1_OABPC REG_BIT(29)
140−
141137 /* Gen12 OAM unit */
142138 #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
143139 #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
drivers/gpu/drm/i915/i915_pmu.c+205−85
@@ -10,6 +10,7 @@ · 9 unmodified lines
1010 #include "gt/intel_engine_pm.h"
1111 #include "gt/intel_engine_regs.h"
1212 #include "gt/intel_engine_user.h"
13+#include "gt/intel_gt.h"
1314 #include "gt/intel_gt_pm.h"
1415 #include "gt/intel_gt_regs.h"
1516 #include "gt/intel_rc6.h"
@@ -50,16 +51,26 @@ static u8 engine_event_instance(struct perf_event *event) · 34 unmodified lines
5051 return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
5152 }
5253
53−static bool is_engine_config(u64 config)
54+static bool is_engine_config(const u64 config)
5455 {
5556 return config < __I915_PMU_OTHER(0);
5657 }
5758
59+static unsigned int config_gt_id(const u64 config)
60+{
61+ return config >> __I915_PMU_GT_SHIFT;
62+}
63+
64+static u64 config_counter(const u64 config)
65+{
66+ return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
67+}
68+
5869 static unsigned int other_bit(const u64 config)
5970 {
6071 unsigned int val;
6172
62− switch (config) {
73+ switch (config_counter(config)) {
6374 case I915_PMU_ACTUAL_FREQUENCY:
6475 val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
6576 break;
@@ -77,7 +88,9 @@ static unsigned int other_bit(const u64 config) · 11 unmodified lines
7788 return -1;
7889 }
7990
80− return I915_ENGINE_SAMPLE_COUNT + val;
91+ return I915_ENGINE_SAMPLE_COUNT +
92+ config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
93+ val;
8194 }
8295
8396 static unsigned int config_bit(const u64 config)
@@ -88,9 +101,20 @@ static unsigned int config_bit(const u64 config) · 4 unmodified lines
88101 return other_bit(config);
89102 }
90103
91−static u64 config_mask(u64 config)
104+static u32 config_mask(const u64 config)
92105 {
93− return BIT_ULL(config_bit(config));
106+ unsigned int bit = config_bit(config);
107+
108+ if (__builtin_constant_p(config))
109+ BUILD_BUG_ON(bit >
110+ BITS_PER_TYPE(typeof_member(struct i915_pmu,
111+ enable)) - 1);
112+ else
113+ WARN_ON_ONCE(bit >
114+ BITS_PER_TYPE(typeof_member(struct i915_pmu,
115+ enable)) - 1);
116+
117+ return BIT(config_bit(config));
94118 }
95119
96120 static bool is_engine_event(struct perf_event *event)
@@ -103,6 +127,18 @@ static unsigned int event_bit(struct perf_event *event) · 6 unmodified lines
103127 return config_bit(event->attr.config);
104128 }
105129
130+static u32 frequency_enabled_mask(void)
131+{
132+ unsigned int i;
133+ u32 mask = 0;
134+
135+ for (i = 0; i < I915_PMU_MAX_GTS; i++)
136+ mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
137+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
138+
139+ return mask;
140+}
141+
106142 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
107143 {
108144 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -119,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) · 10 unmodified lines
119155 * Mask out all the ones which do not need the timer, or in
120156 * other words keep all the ones that could need the timer.
121157 */
122− enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
123− config_mask(I915_PMU_REQUESTED_FREQUENCY) |
124− ENGINE_SAMPLE_MASK;
158+ enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
125159
126160 /*
127161 * When the GPU is idle per-engine counters do not need to be
@@ -163,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt) · 35 unmodified lines
163197 return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
164198 }
165199
200+static unsigned int
201+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
202+{
203+ unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
204+
205+ GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
206+
207+ return idx;
208+}
209+
210+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
211+{
212+ return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
213+}
214+
215+static void
216+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
217+{
218+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
219+}
220+
221+static void
222+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)
223+{
224+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, mul);
225+}
226+
166227 static u64 get_rc6(struct intel_gt *gt)
167228 {
168229 struct drm_i915_private *i915 = gt->i915;
230+ const unsigned int gt_id = gt->info.id;
169231 struct i915_pmu *pmu = &i915->pmu;
170232 unsigned long flags;
171233 bool awake = false;
@@ -180,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt) · 8 unmodified lines
180242 spin_lock_irqsave(&pmu->lock, flags);
181243
182244 if (awake) {
183− pmu->sample[__I915_SAMPLE_RC6].cur = val;
245+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
184246 } else {
185247 /*
186248 * We think we are runtime suspended.
@@ -189,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt) · 2 unmodified lines
189251 * on top of the last known real value, as the approximated RC6
190252 * counter value.
191253 */
192− val = ktime_since_raw(pmu->sleep_last);
193− val += pmu->sample[__I915_SAMPLE_RC6].cur;
254+ val = ktime_since_raw(pmu->sleep_last[gt_id]);
255+ val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
194256 }
195257
196− if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)
197− val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;
258+ if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED))
259+ val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED);
198260 else
199− pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;
261+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val);
200262
201263 spin_unlock_irqrestore(&pmu->lock, flags);
202264
@@ -206,22 +268,29 @@ static u64 get_rc6(struct intel_gt *gt) · 3 unmodified lines
206268 static void init_rc6(struct i915_pmu *pmu)
207269 {
208270 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
209− intel_wakeref_t wakeref;
271+ struct intel_gt *gt;
272+ unsigned int i;
210273
211− with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref) {
212− pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
213− pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur =
214− pmu->sample[__I915_SAMPLE_RC6].cur;
215− pmu->sleep_last = ktime_get_raw();
274+ for_each_gt(gt, i915, i) {
275+ intel_wakeref_t wakeref;
276+
277+ with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
278+ u64 val = __get_rc6(gt);
279+
280+ store_sample(pmu, i, __I915_SAMPLE_RC6, val);
281+ store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
282+ val);
283+ pmu->sleep_last[i] = ktime_get_raw();
284+ }
216285 }
217286 }
218287
219−static void park_rc6(struct drm_i915_private *i915)
288+static void park_rc6(struct intel_gt *gt)
220289 {
221− struct i915_pmu *pmu = &i915->pmu;
290+ struct i915_pmu *pmu = &gt->i915->pmu;
222291
223− pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
224− pmu->sleep_last = ktime_get_raw();
292+ store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt));
293+ pmu->sleep_last[gt->info.id] = ktime_get_raw();
225294 }
226295
227296 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
@@ -235,29 +304,31 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) · 7 unmodified lines
235304 }
236305 }
237306
238−void i915_pmu_gt_parked(struct drm_i915_private *i915)
307+void i915_pmu_gt_parked(struct intel_gt *gt)
239308 {
240− struct i915_pmu *pmu = &i915->pmu;
309+ struct i915_pmu *pmu = &gt->i915->pmu;
241310
242311 if (!pmu->base.event_init)
243312 return;
244313
245314 spin_lock_irq(&pmu->lock);
246315
247− park_rc6(i915);
316+ park_rc6(gt);
248317
249318 /*
250319 * Signal sampling timer to stop if only engine events are enabled and
251320 * GPU went idle.
252321 */
253− pmu->timer_enabled = pmu_needs_timer(pmu, false);
322+ pmu->unparked &= ~BIT(gt->info.id);
323+ if (pmu->unparked == 0)
324+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
254325
255326 spin_unlock_irq(&pmu->lock);
256327 }
257328
258−void i915_pmu_gt_unparked(struct drm_i915_private *i915)
329+void i915_pmu_gt_unparked(struct intel_gt *gt)
259330 {
260− struct i915_pmu *pmu = &i915->pmu;
331+ struct i915_pmu *pmu = &gt->i915->pmu;
261332
262333 if (!pmu->base.event_init)
263334 return;
@@ -267,7 +338,10 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915) · 3 unmodified lines
267338 /*
268339 * Re-enable sampling timer when GPU goes active.
269340 */
270− __i915_pmu_maybe_start_timer(pmu);
341+ if (pmu->unparked == 0)
342+ __i915_pmu_maybe_start_timer(pmu);
343+
344+ pmu->unparked |= BIT(gt->info.id);
271345
272346 spin_unlock_irq(&pmu->lock);
273347 }
@@ -338,6 +412,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) · 64 unmodified lines
338412 return;
339413
340414 for_each_engine(engine, gt, id) {
415+ if (!engine->pmu.enable)
416+ continue;
417+
341418 if (!intel_engine_pm_get_if_awake(engine))
342419 continue;
343420
@@ -353,34 +430,30 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) · 9 unmodified lines
353430 }
354431 }
355432
356−static void
357−add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
358−{
359− sample->cur += mul_u32_u32(val, mul);
360−}
361−
362−static bool frequency_sampling_enabled(struct i915_pmu *pmu)
433+static bool
434+frequency_sampling_enabled(struct i915_pmu *pmu, unsigned int gt)
363435 {
364436 return pmu->enable &
365− (config_mask(I915_PMU_ACTUAL_FREQUENCY) |
366− config_mask(I915_PMU_REQUESTED_FREQUENCY));
437+ (config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt)) |
438+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt)));
367439 }
368440
369441 static void
370442 frequency_sample(struct intel_gt *gt, unsigned int period_ns)
371443 {
372444 struct drm_i915_private *i915 = gt->i915;
445+ const unsigned int gt_id = gt->info.id;
373446 struct i915_pmu *pmu = &i915->pmu;
374447 struct intel_rps *rps = &gt->rps;
375448
376− if (!frequency_sampling_enabled(pmu))
449+ if (!frequency_sampling_enabled(pmu, gt_id))
377450 return;
378451
379452 /* Report 0/0 (actual/requested) frequency while parked. */
380453 if (!intel_gt_pm_get_if_awake(gt))
381454 return;
382455
383− if (pmu->enable & config_mask(I915_PMU_ACTUAL_FREQUENCY)) {
456+ if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {
384457 u32 val;
385458
386459 /*
@@ -396,12 +469,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) · 9 unmodified lines
396469 if (!val)
397470 val = intel_gpu_freq(rps, rps->cur_freq);
398471
399− add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],
472+ add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_ACT,
400473 val, period_ns / 1000);
401474 }
402475
403− if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {
404− add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
476+ if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) {
477+ add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ,
405478 intel_rps_get_requested_frequency(rps),
406479 period_ns / 1000);
407480 }
@@ -414,8 +487,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) · 6 unmodified lines
414487 struct drm_i915_private *i915 =
415488 container_of(hrtimer, struct drm_i915_private, pmu.timer);
416489 struct i915_pmu *pmu = &i915->pmu;
417− struct intel_gt *gt = to_gt(i915);
418490 unsigned int period_ns;
491+ struct intel_gt *gt;
492+ unsigned int i;
419493 ktime_t now;
420494
421495 if (!READ_ONCE(pmu->timer_enabled))
@@ -431,8 +505,14 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) · 9 unmodified lines
431505 * grabbing the forcewake. However the potential error from timer call-
432506 * back delay greatly dominates this so we keep it simple.
433507 */
434− engines_sample(gt, period_ns);
435− frequency_sample(gt, period_ns);
508+
509+ for_each_gt(gt, i915, i) {
510+ if (!(pmu->unparked & BIT(i)))
511+ continue;
512+
513+ engines_sample(gt, period_ns);
514+ frequency_sample(gt, period_ns);
515+ }
436516
437517 hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
438518
@@ -473,7 +553,13 @@ config_status(struct drm_i915_private *i915, u64 config) · 34 unmodified lines
473553 {
474554 struct intel_gt *gt = to_gt(i915);
475555
476− switch (config) {
556+ unsigned int gt_id = config_gt_id(config);
557+ unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
558+
559+ if (gt_id > max_gt_id)
560+ return -ENOENT;
561+
562+ switch (config_counter(config)) {
477563 case I915_PMU_ACTUAL_FREQUENCY:
478564 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
479565 /* Requires a mutex for sampling! */
@@ -484,6 +570,8 @@ config_status(struct drm_i915_private *i915, u64 config) · 4 unmodified lines
484570 return -ENODEV;
485571 break;
486572 case I915_PMU_INTERRUPTS:
573+ if (gt_id)
574+ return -ENOENT;
487575 break;
488576 case I915_PMU_RC6_RESIDENCY:
489577 if (!gt->rc6.supported)
@@ -581,22 +669,27 @@ static u64 __i915_pmu_event_read(struct perf_event *event) · 91 unmodified lines
581669 val = engine->pmu.sample[sample].cur;
582670 }
583671 } else {
584− switch (event->attr.config) {
672+ const unsigned int gt_id = config_gt_id(event->attr.config);
673+ const u64 config = config_counter(event->attr.config);
674+
675+ switch (config) {
585676 case I915_PMU_ACTUAL_FREQUENCY:
586677 val =
587− div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,
678+ div_u64(read_sample(pmu, gt_id,
679+ __I915_SAMPLE_FREQ_ACT),
588680 USEC_PER_SEC /* to MHz */);
589681 break;
590682 case I915_PMU_REQUESTED_FREQUENCY:
591683 val =
592− div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,
684+ div_u64(read_sample(pmu, gt_id,
685+ __I915_SAMPLE_FREQ_REQ),
593686 USEC_PER_SEC /* to MHz */);
594687 break;
595688 case I915_PMU_INTERRUPTS:
596689 val = READ_ONCE(pmu->irq_count);
597690 break;
598691 case I915_PMU_RC6_RESIDENCY:
599− val = get_rc6(to_gt(i915));
692+ val = get_rc6(i915->gt[gt_id]);
600693 break;
601694 case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
602695 val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
@@ -633,11 +726,10 @@ static void i915_pmu_enable(struct perf_event *event) · 30 unmodified lines
633726 {
634727 struct drm_i915_private *i915 =
635728 container_of(event->pmu, typeof(*i915), pmu.base);
729+ const unsigned int bit = event_bit(event);
636730 struct i915_pmu *pmu = &i915->pmu;
637731 unsigned long flags;
638− unsigned int bit;
639732
640− bit = event_bit(event);
641733 if (bit == -1)
642734 goto update;
643735
@@ -651,7 +743,7 @@ static void i915_pmu_enable(struct perf_event *event) · 7 unmodified lines
651743 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
652744 GEM_BUG_ON(pmu->enable_count[bit] == ~0);
653745
654− pmu->enable |= BIT_ULL(bit);
746+ pmu->enable |= BIT(bit);
655747 pmu->enable_count[bit]++;
656748
657749 /*
@@ -698,7 +790,7 @@ static void i915_pmu_disable(struct perf_event *event) · 40 unmodified lines
698790 {
699791 struct drm_i915_private *i915 =
700792 container_of(event->pmu, typeof(*i915), pmu.base);
701− unsigned int bit = event_bit(event);
793+ const unsigned int bit = event_bit(event);
702794 struct i915_pmu *pmu = &i915->pmu;
703795 unsigned long flags;
704796
@@ -734,7 +826,7 @@ static void i915_pmu_disable(struct perf_event *event) · 29 unmodified lines
734826 * bitmask when the last listener on an event goes away.
735827 */
736828 if (--pmu->enable_count[bit] == 0) {
737− pmu->enable &= ~BIT_ULL(bit);
829+ pmu->enable &= ~BIT(bit);
738830 pmu->timer_enabled &= pmu_needs_timer(pmu, true);
739831 }
740832
@@ -848,11 +940,20 @@ static const struct attribute_group i915_pmu_cpumask_attr_group = { · 107 unmodified lines
848940 .attrs = i915_cpumask_attrs,
849941 };
850942
851−#define __event(__config, __name, __unit) \
943+#define __event(__counter, __name, __unit) \
852944 { \
853− .config = (__config), \
945+ .counter = (__counter), \
854946 .name = (__name), \
855947 .unit = (__unit), \
948+ .global = false, \
949+}
950+
951+#define __global_event(__counter, __name, __unit) \
952+{ \
953+ .counter = (__counter), \
954+ .name = (__name), \
955+ .unit = (__unit), \
956+ .global = true, \
856957 }
857958
858959 #define __engine_event(__sample, __name) \
@@ -891,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu) · 32 unmodified lines
891992 {
892993 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
893994 static const struct {
894− u64 config;
995+ unsigned int counter;
895996 const char *name;
896997 const char *unit;
998+ bool global;
897999 } events[] = {
898− __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
899− __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),
900− __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
901− __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
902− __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, "software-gt-awake-time", "ns"),
1000+ __event(0, "actual-frequency", "M"),
1001+ __event(1, "requested-frequency", "M"),
1002+ __global_event(2, "interrupts", NULL),
1003+ __event(3, "rc6-residency", "ns"),
1004+ __event(4, "software-gt-awake-time", "ns"),
9031005 };
9041006 static const struct {
9051007 enum drm_i915_pmu_engine_sample sample;
@@ -914,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu) · 8 unmodified lines
9141016 struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
9151017 struct attribute **attr = NULL, **attr_iter;
9161018 struct intel_engine_cs *engine;
917− unsigned int i;
1019+ struct intel_gt *gt;
1020+ unsigned int i, j;
9181021
9191022 /* Count how many counters we will be exposing. */
920− for (i = 0; i < ARRAY_SIZE(events); i++) {
921− if (!config_status(i915, events[i].config))
922− count++;
1023+ for_each_gt(gt, i915, j) {
1024+ for (i = 0; i < ARRAY_SIZE(events); i++) {
1025+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
1026+
1027+ if (!config_status(i915, config))
1028+ count++;
1029+ }
9231030 }
9241031
9251032 for_each_uabi_engine(engine, i915) {
@@ -949,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu) · 23 unmodified lines
9491056 attr_iter = attr;
9501057
9511058 /* Initialize supported non-engine counters. */
952− for (i = 0; i < ARRAY_SIZE(events); i++) {
953− char *str;
954−
955− if (config_status(i915, events[i].config))
956− continue;
957−
958− str = kstrdup(events[i].name, GFP_KERNEL);
959− if (!str)
960− goto err;
1059+ for_each_gt(gt, i915, j) {
1060+ for (i = 0; i < ARRAY_SIZE(events); i++) {
1061+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
1062+ char *str;
9611063
962− *attr_iter++ = &i915_iter->attr.attr;
963− i915_iter = add_i915_attr(i915_iter, str, events[i].config);
1064+ if (config_status(i915, config))
1065+ continue;
9641066
965− if (events[i].unit) {
966− str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
1067+ if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1068+ str = kstrdup(events[i].name, GFP_KERNEL);
1069+ else
1070+ str = kasprintf(GFP_KERNEL, "%s-gt%u",
1071+ events[i].name, j);
9671072 if (!str)
9681073 goto err;
9691074
970− *attr_iter++ = &pmu_iter->attr.attr;
971− pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
1075+ *attr_iter++ = &i915_iter->attr.attr;
1076+ i915_iter = add_i915_attr(i915_iter, str, config);
1077+
1078+ if (events[i].unit) {
1079+ if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1080+ str = kasprintf(GFP_KERNEL, "%s.unit",
1081+ events[i].name);
1082+ else
1083+ str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
1084+ events[i].name, j);
1085+ if (!str)
1086+ goto err;
1087+
1088+ *attr_iter++ = &pmu_iter->attr.attr;
1089+ pmu_iter = add_pmu_attr(pmu_iter, str,
1090+ events[i].unit);
1091+ }
9721092 }
9731093 }
9741094
drivers/gpu/drm/i915/i915_pmu.h+18−10
@@ -13,8 +13,9 @@ · 12 unmodified lines
1313 #include <uapi/drm/i915_drm.h>
1414
1515 struct drm_i915_private;
16+struct intel_gt;
1617
17−/**
18+/*
1819 * Non-engine events that we need to track enabled-disabled transition and
1920 * current state.
2021 */
@@ -25,7 +26,7 @@ enum i915_pmu_tracked_events { · 4 unmodified lines
2526 __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
2627 };
2728
28−/**
29+/*
2930 * Slots used from the sampling timer (non-engine events) with some extras for
3031 * convenience.
3132 */
@@ -37,13 +38,16 @@ enum { · 5 unmodified lines
3738 __I915_NUM_PMU_SAMPLERS
3839 };
3940
40−/**
41+#define I915_PMU_MAX_GTS 2
42+
43+/*
4144 * How many different events we track in the global PMU mask.
4245 *
4346 * It is also used to know to needed number of event reference counters.
4447 */
4548 #define I915_PMU_MASK_BITS \
46− (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
49+ (I915_ENGINE_SAMPLE_COUNT + \
50+ I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT)
4751
4852 #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
4953
@@ -75,6 +79,10 @@ struct i915_pmu { · 25 unmodified lines
7579 * @lock: Lock protecting enable mask and ref count handling.
7680 */
7781 spinlock_t lock;
82+ /**
83+ * @unparked: GT unparked mask.
84+ */
85+ unsigned int unparked;
7886 /**
7987 * @timer: Timer for internal i915 PMU sampling.
8088 */
@@ -119,11 +127,11 @@ struct i915_pmu { · 38 unmodified lines
119127 * Only global counters are held here, while the per-engine ones are in
120128 * struct intel_engine_cs.
121129 */
122− struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
130+ struct i915_pmu_sample sample[I915_PMU_MAX_GTS * __I915_NUM_PMU_SAMPLERS];
123131 /**
124132 * @sleep_last: Last time GT parked for RC6 estimation.
125133 */
126− ktime_t sleep_last;
134+ ktime_t sleep_last[I915_PMU_MAX_GTS];
127135 /**
128136 * @irq_count: Number of interrupts
129137 *
@@ -151,15 +159,15 @@ int i915_pmu_init(void); · 21 unmodified lines
151159 void i915_pmu_exit(void);
152160 void i915_pmu_register(struct drm_i915_private *i915);
153161 void i915_pmu_unregister(struct drm_i915_private *i915);
154−void i915_pmu_gt_parked(struct drm_i915_private *i915);
155−void i915_pmu_gt_unparked(struct drm_i915_private *i915);
162+void i915_pmu_gt_parked(struct intel_gt *gt);
163+void i915_pmu_gt_unparked(struct intel_gt *gt);
156164 #else
157165 static inline int i915_pmu_init(void) { return 0; }
158166 static inline void i915_pmu_exit(void) {}
159167 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
160168 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
161−static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
162−static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
169+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
170+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
163171 #endif
164172
165173 #endif
drivers/gpu/drm/i915/i915_request.h+26−26
@@ -172,7 +172,7 @@ enum { · 171 unmodified lines
172172 I915_FENCE_FLAG_COMPOSITE,
173173 };
174174
175−/**
175+/*
176176 * Request queue structure.
177177 *
178178 * The request queue allows us to note sequence numbers that have been emitted
@@ -198,7 +198,7 @@ struct i915_request { · 19 unmodified lines
198198
199199 struct drm_i915_private *i915;
200200
201− /**
201+ /*
202202 * Context and ring buffer related to this request
203203 * Contexts are refcounted, so when this request is associated with a
204204 * context, we must increment the context's refcount, to guarantee that
@@ -251,9 +251,9 @@ struct i915_request { · 46 unmodified lines
251251 };
252252 struct llist_head execute_cb;
253253 struct i915_sw_fence semaphore;
254− /**
255− * @submit_work: complete submit fence from an IRQ if needed for
256− * locking hierarchy reasons.
254+ /*
255+ * complete submit fence from an IRQ if needed for locking hierarchy
256+ * reasons.
257257 */
258258 struct irq_work submit_work;
259259
@@ -277,35 +277,35 @@ struct i915_request { · 17 unmodified lines
277277 */
278278 const u32 *hwsp_seqno;
279279
280− /** Position in the ring of the start of the request */
280+ /* Position in the ring of the start of the request */
281281 u32 head;
282282
283− /** Position in the ring of the start of the user packets */
283+ /* Position in the ring of the start of the user packets */
284284 u32 infix;
285285
286− /**
286+ /*
287287 * Position in the ring of the start of the postfix.
288288 * This is required to calculate the maximum available ring space
289289 * without overwriting the postfix.
290290 */
291291 u32 postfix;
292292
293− /** Position in the ring of the end of the whole request */
293+ /* Position in the ring of the end of the whole request */
294294 u32 tail;
295295
296− /** Position in the ring of the end of any workarounds after the tail */
296+ /* Position in the ring of the end of any workarounds after the tail */
297297 u32 wa_tail;
298298
299− /** Preallocate space in the ring for the emitting the request */
299+ /* Preallocate space in the ring for the emitting the request */
300300 u32 reserved_space;
301301
302− /** Batch buffer pointer for selftest internal use. */
302+ /* Batch buffer pointer for selftest internal use. */
303303 I915_SELFTEST_DECLARE(struct i915_vma *batch);
304304
305305 struct i915_vma_resource *batch_res;
306306
307307 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
308− /**
308+ /*
309309 * Additional buffers requested by userspace to be captured upon
310310 * a GPU hang. The vma/obj on this list are protected by their
311311 * active reference - all objects on this list must also be
@@ -314,29 +314,29 @@ struct i915_request { · 2 unmodified lines
314314 struct i915_capture_list *capture_list;
315315 #endif
316316
317− /** Time at which this request was emitted, in jiffies. */
317+ /* Time at which this request was emitted, in jiffies. */
318318 unsigned long emitted_jiffies;
319319
320− /** timeline->request entry for this request */
320+ /* timeline->request entry for this request */
321321 struct list_head link;
322322
323− /** Watchdog support fields. */
323+ /* Watchdog support fields. */
324324 struct i915_request_watchdog {
325325 struct llist_node link;
326326 struct hrtimer timer;
327327 } watchdog;
328328
329− /**
330− * @guc_fence_link: Requests may need to be stalled when using GuC
331− * submission waiting for certain GuC operations to complete. If that is
332− * the case, stalled requests are added to a per context list of stalled
333− * requests. The below list_head is the link in that list. Protected by
329+ /*
330+ * Requests may need to be stalled when using GuC submission waiting for
331+ * certain GuC operations to complete. If that is the case, stalled
332+ * requests are added to a per context list of stalled requests. The
333+ * below list_head is the link in that list. Protected by
334334 * ce->guc_state.lock.
335335 */
336336 struct list_head guc_fence_link;
337337
338− /**
339− * @guc_prio: Priority level while the request is in flight. Differs
338+ /*
339+ * Priority level while the request is in flight. Differs
340340 * from i915 scheduler priority. See comment above
341341 * I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP for details. Protected by
342342 * ce->guc_active.lock. Two special values (GUC_PRIO_INIT and
@@ -348,8 +348,8 @@ struct i915_request { · 5 unmodified lines
348348 #define GUC_PRIO_FINI 0xfe
349349 u8 guc_prio;
350350
351− /**
352− * @hucq: wait queue entry used to wait on the HuC load to complete
351+ /*
352+ * wait queue entry used to wait on the HuC load to complete
353353 */
354354 wait_queue_entry_t hucq;
355355
@@ -473,7 +473,7 @@ i915_request_has_initial_breadcrumb(const struct i915_request *rq) · 117 unmodified lines
473473 return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
474474 }
475475
476−/**
476+/*
477477 * Returns true if seq1 is later than seq2.
478478 */
479479 static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
drivers/gpu/drm/i915/i915_scatterlist.h+4−5
@@ -157,8 +157,7 @@ bool i915_sg_trim(struct sg_table *orig_st); · 156 unmodified lines
157157 */
158158 struct i915_refct_sgt_ops {
159159 /**
160− * release() - Free the memory of the struct i915_refct_sgt
161− * @ref: struct kref that is embedded in the struct i915_refct_sgt
160+ * @release: Free the memory of the struct i915_refct_sgt
162161 */
163162 void (*release)(struct kref *ref);
164163 };
@@ -181,7 +180,7 @@ struct i915_refct_sgt { · 16 unmodified lines
181180
182181 /**
183182 * i915_refct_sgt_put - Put a refcounted sg-table
184− * @rsgt the struct i915_refct_sgt to put.
183+ * @rsgt: the struct i915_refct_sgt to put.
185184 */
186185 static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
187186 {
@@ -191,7 +190,7 @@ static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt) · 3 unmodified lines
191190
192191 /**
193192 * i915_refct_sgt_get - Get a refcounted sg-table
194− * @rsgt the struct i915_refct_sgt to get.
193+ * @rsgt: the struct i915_refct_sgt to get.
195194 */
196195 static inline struct i915_refct_sgt *
197196 i915_refct_sgt_get(struct i915_refct_sgt *rsgt)
@@ -203,7 +202,7 @@ i915_refct_sgt_get(struct i915_refct_sgt *rsgt) · 5 unmodified lines
203202 /**
204203 * __i915_refct_sgt_init - Initialize a refcounted sg-list with a custom
205204 * operations structure
206− * @rsgt The struct i915_refct_sgt to initialize.
205+ * @rsgt: The struct i915_refct_sgt to initialize.
207206 * @size: Size in bytes of the underlying memory buffer.
208207 * @ops: A customized operations structure in case the refcounted sg-list
209208 * is embedded into another structure.
drivers/gpu/drm/i915/i915_utils.h+1−1
@@ -250,7 +250,7 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) · 249 unmodified lines
250250 }
251251 }
252252
253−/**
253+/*
254254 * __wait_for - magic wait macro
255255 *
256256 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
drivers/gpu/drm/i915/i915_vma.c+8−8
@@ -315,7 +315,7 @@ struct i915_vma_work { · 314 unmodified lines
315315 struct i915_vma_resource *vma_res;
316316 struct drm_i915_gem_object *obj;
317317 struct i915_sw_dma_fence_cb cb;
318− enum i915_cache_level cache_level;
318+ unsigned int pat_index;
319319 unsigned int flags;
320320 };
321321
@@ -334,7 +334,7 @@ static void __vma_bind(struct dma_fence_work *work) · 12 unmodified lines
334334 return;
335335
336336 vma_res->ops->bind_vma(vma_res->vm, &vw->stash,
337− vma_res, vw->cache_level, vw->flags);
337+ vma_res, vw->pat_index, vw->flags);
338338 }
339339
340340 static void __vma_release(struct dma_fence_work *work)
@@ -426,7 +426,7 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, · 85 unmodified lines
426426 /**
427427 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
428428 * @vma: VMA to map
429− * @cache_level: mapping cache level
429+ * @pat_index: PAT index to set in PTE
430430 * @flags: flags like global or local mapping
431431 * @work: preallocated worker for allocating and binding the PTE
432432 * @vma_res: pointer to a preallocated vma resource. The resource is either
@@ -437,7 +437,7 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, · 4 unmodified lines
437437 * Note that DMA addresses are also the only part of the SG table we care about.
438438 */
439439 int i915_vma_bind(struct i915_vma *vma,
440− enum i915_cache_level cache_level,
440+ unsigned int pat_index,
441441 u32 flags,
442442 struct i915_vma_work *work,
443443 struct i915_vma_resource *vma_res)
@@ -507,7 +507,7 @@ int i915_vma_bind(struct i915_vma *vma, · 63 unmodified lines
507507 struct dma_fence *prev;
508508
509509 work->vma_res = i915_vma_resource_get(vma->resource);
510− work->cache_level = cache_level;
510+ work->pat_index = pat_index;
511511 work->flags = bind_flags;
512512
513513 /*
@@ -537,7 +537,7 @@ int i915_vma_bind(struct i915_vma *vma, · 23 unmodified lines
537537
538538 return ret;
539539 }
540− vma->ops->bind_vma(vma->vm, NULL, vma->resource, cache_level,
540+ vma->ops->bind_vma(vma->vm, NULL, vma->resource, pat_index,
541541 bind_flags);
542542 }
543543
@@ -814,7 +814,7 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, · 270 unmodified lines
814814 color = 0;
815815
816816 if (i915_vm_has_cache_coloring(vma->vm))
817− color = vma->obj->cache_level;
817+ color = vma->obj->pat_index;
818818
819819 if (flags & PIN_OFFSET_FIXED) {
820820 u64 offset = flags & PIN_OFFSET_MASK;
@@ -1518,7 +1518,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, · 697 unmodified lines
15181518
15191519 GEM_BUG_ON(!vma->pages);
15201520 err = i915_vma_bind(vma,
1521− vma->obj->cache_level,
1521+ vma->obj->pat_index,
15221522 flags, work, vma_res);
15231523 vma_res = NULL;
15241524 if (err)
drivers/gpu/drm/i915/i915_vma.h+2−2
@@ -132,7 +132,7 @@ static inline u64 __i915_vma_size(const struct i915_vma *vma) · 131 unmodified lines
132132 }
133133
134134 /**
135− * i915_vma_offset - Obtain the va range size of the vma
135+ * i915_vma_size - Obtain the va range size of the vma
136136 * @vma: The vma
137137 *
138138 * GPU virtual address space may be allocated with padding. This
@@ -250,7 +250,7 @@ i915_vma_compare(struct i915_vma *vma, · 111 unmodified lines
250250
251251 struct i915_vma_work *i915_vma_work(void);
252252 int i915_vma_bind(struct i915_vma *vma,
253− enum i915_cache_level cache_level,
253+ unsigned int pat_index,
254254 u32 flags,
255255 struct i915_vma_work *work,
256256 struct i915_vma_resource *vma_res);
drivers/gpu/drm/i915/i915_vma_resource.h+28−18
@@ -33,6 +33,27 @@ struct i915_page_sizes { · 32 unmodified lines
3333 unsigned int sg;
3434 };
3535
36+/**
37+ * struct i915_vma_bindinfo - Information needed for async bind
38+ * only but that can be dropped after the bind has taken place.
39+ * Consider making this a separate argument to the bind_vma
40+ * op, coalescing with other arguments like vm, stash, cache_level
41+ * and flags
42+ * @pages: The pages sg-table.
43+ * @page_sizes: Page sizes of the pages.
44+ * @pages_rsgt: Refcounted sg-table when delayed object destruction
45+ * is supported. May be NULL.
46+ * @readonly: Whether the vma should be bound read-only.
47+ * @lmem: Whether the vma points to lmem.
48+ */
49+struct i915_vma_bindinfo {
50+ struct sg_table *pages;
51+ struct i915_page_sizes page_sizes;
52+ struct i915_refct_sgt *pages_rsgt;
53+ bool readonly:1;
54+ bool lmem:1;
55+};
56+
3657 /**
3758 * struct i915_vma_resource - Snapshotted unbind information.
3859 * @unbind_fence: Fence to mark unbinding complete. Note that this fence
@@ -47,6 +68,7 @@ struct i915_page_sizes { · 8 unmodified lines
4768 * @chain: Pointer to struct i915_sw_fence used to await dependencies.
4869 * @rb: Rb node for the vm's pending unbind interval tree.
4970 * @__subtree_last: Interval tree private member.
71+ * @wakeref: wakeref.
5072 * @vm: non-refcounted pointer to the vm. This is for internal use only and
5173 * this member is cleared after vm_resource unbind.
5274 * @mr: The memory region of the object pointed to by the vma.
@@ -88,25 +110,13 @@ struct i915_vma_resource { · 35 unmodified lines
88110 intel_wakeref_t wakeref;
89111
90112 /**
91− * struct i915_vma_bindinfo - Information needed for async bind
92− * only but that can be dropped after the bind has taken place.
93− * Consider making this a separate argument to the bind_vma
94− * op, coalescing with other arguments like vm, stash, cache_level
95− * and flags
96− * @pages: The pages sg-table.
97− * @page_sizes: Page sizes of the pages.
98− * @pages_rsgt: Refcounted sg-table when delayed object destruction
99− * is supported. May be NULL.
100− * @readonly: Whether the vma should be bound read-only.
101− * @lmem: Whether the vma points to lmem.
113+ * @bi: Information needed for async bind only but that can be dropped
114+ * after the bind has taken place.
115+ *
116+ * Consider making this a separate argument to the bind_vma op,
117+ * coalescing with other arguments like vm, stash, cache_level and flags
102118 */
103− struct i915_vma_bindinfo {
104− struct sg_table *pages;
105− struct i915_page_sizes page_sizes;
106− struct i915_refct_sgt *pages_rsgt;
107− bool readonly:1;
108− bool lmem:1;
109− } bi;
119+ struct i915_vma_bindinfo bi;
110120
111121 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
112122 struct intel_memory_region *mr;
drivers/gpu/drm/i915/i915_vma_types.h+0−2
@@ -32,8 +32,6 @@ · 31 unmodified lines
3232
3333 #include "gem/i915_gem_object_types.h"
3434
35−enum i915_cache_level;
36−
3735 /**
3836 * DOC: Global GTT views
3937 *
drivers/gpu/drm/i915/intel_device_info.h+5−0
@@ -35,6 +35,8 @@ · 34 unmodified lines
3535 #include "gt/intel_context_types.h"
3636 #include "gt/intel_sseu.h"
3737
38+#include "gem/i915_gem_object_types.h"
39+
3840 struct drm_printer;
3941 struct drm_i915_private;
4042 struct intel_gt_definition;
@@ -245,6 +247,9 @@ struct intel_device_info { · 204 unmodified lines
245247 * Initial runtime info. Do not access outside of i915_driver_create().
246248 */
247249 const struct intel_runtime_info __runtime;
250+
251+ u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
252+ u32 max_pat_index;
248253 };
249254
250255 struct intel_driver_caps {
drivers/gpu/drm/i915/pxp/intel_pxp.c+78−24
@@ -12,7 +12,9 @@ · 11 unmodified lines
1212 #include "i915_drv.h"
1313
1414 #include "intel_pxp.h"
15+#include "intel_pxp_gsccs.h"
1516 #include "intel_pxp_irq.h"
17+#include "intel_pxp_regs.h"
1618 #include "intel_pxp_session.h"
1719 #include "intel_pxp_tee.h"
1820 #include "intel_pxp_types.h"
@@ -60,21 +62,22 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp) · 41 unmodified lines
6062 return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid;
6163 }
6264
63−/* KCR register definitions */
64−#define KCR_INIT _MMIO(0x320f0)
65−/* Setting KCR Init bit is required after system boot */
66−#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
65+static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
66+{
67+ u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
68+ _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
69+
70+ intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
71+}
6772
68−static void kcr_pxp_enable(struct intel_gt *gt)
73+static void kcr_pxp_enable(const struct intel_pxp *pxp)
6974 {
70− intel_uncore_write(gt->uncore, KCR_INIT,
71− _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
75+ kcr_pxp_set_status(pxp, true);
7276 }
7377
74−static void kcr_pxp_disable(struct intel_gt *gt)
78+static void kcr_pxp_disable(const struct intel_pxp *pxp)
7579 {
76− intel_uncore_write(gt->uncore, KCR_INIT,
77− _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
80+ kcr_pxp_set_status(pxp, false);
7881 }
7982
8083 static int create_vcs_context(struct intel_pxp *pxp)
@@ -126,13 +129,21 @@ static void pxp_init_full(struct intel_pxp *pxp) · 45 unmodified lines
126129 init_completion(&pxp->termination);
127130 complete_all(&pxp->termination);
128131
132+ if (pxp->ctrl_gt->type == GT_MEDIA)
133+ pxp->kcr_base = MTL_KCR_BASE;
134+ else
135+ pxp->kcr_base = GEN12_KCR_BASE;
136+
129137 intel_pxp_session_management_init(pxp);
130138
131139 ret = create_vcs_context(pxp);
132140 if (ret)
133141 return;
134142
135− ret = intel_pxp_tee_component_init(pxp);
143+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
144+ ret = intel_pxp_gsccs_init(pxp);
145+ else
146+ ret = intel_pxp_tee_component_init(pxp);
136147 if (ret)
137148 goto out_context;
138149
@@ -165,9 +176,12 @@ static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_p · 26 unmodified lines
165176 /*
166177 * For MTL onwards, PXP-controller-GT needs to have a valid GSC engine
167178 * on the media GT. NOTE: if we have a media-tile with a GSC-engine,
168− * the VDBOX is already present so skip that check
179+ * the VDBOX is already present so skip that check. We also have to
180+ * ensure the GSC and HUC firmware are coming online
169181 */
170− if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0))
182+ if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0) &&
183+ intel_uc_fw_is_loadable(&i915->media_gt->uc.gsc.fw) &&
184+ intel_uc_fw_is_loadable(&i915->media_gt->uc.huc.fw))
171185 return i915->media_gt;
172186
173187 /*
@@ -207,7 +221,9 @@ int intel_pxp_init(struct drm_i915_private *i915) · 33 unmodified lines
207221 if (!i915->pxp)
208222 return -ENOMEM;
209223
224+ /* init common info used by all feature-mode usages*/
210225 i915->pxp->ctrl_gt = gt;
226+ mutex_init(&i915->pxp->tee_mutex);
211227
212228 /*
213229 * If full PXP feature is not available but HuC is loaded by GSC on pre-MTL
@@ -229,7 +245,10 @@ void intel_pxp_fini(struct drm_i915_private *i915) · 15 unmodified lines
229245
230246 i915->pxp->arb_is_valid = false;
231247
232− intel_pxp_tee_component_fini(i915->pxp);
248+ if (HAS_ENGINE(i915->pxp->ctrl_gt, GSC0))
249+ intel_pxp_gsccs_fini(i915->pxp);
250+ else
251+ intel_pxp_tee_component_fini(i915->pxp);
233252
234253 destroy_vcs_context(i915->pxp);
235254
@@ -270,8 +289,18 @@ static bool pxp_component_bound(struct intel_pxp *pxp) · 34 unmodified lines
270289 return bound;
271290 }
272291
292+int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp)
293+{
294+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
295+ return GSCFW_MAX_ROUND_TRIP_LATENCY_MS;
296+ else
297+ return 250;
298+}
299+
273300 static int __pxp_global_teardown_final(struct intel_pxp *pxp)
274301 {
302+ int timeout;
303+
275304 if (!pxp->arb_is_valid)
276305 return 0;
277306 /*
@@ -281,7 +310,9 @@ static int __pxp_global_teardown_final(struct intel_pxp *pxp) · 3 unmodified lines
281310 intel_pxp_mark_termination_in_progress(pxp);
282311 intel_pxp_terminate(pxp, false);
283312
284− if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(250)))
313+ timeout = intel_pxp_get_backend_timeout_ms(pxp);
314+
315+ if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(timeout)))
285316 return -ETIMEDOUT;
286317
287318 return 0;
@@ -289,6 +320,8 @@ static int __pxp_global_teardown_final(struct intel_pxp *pxp) · 1 unmodified line
289320
290321 static int __pxp_global_teardown_restart(struct intel_pxp *pxp)
291322 {
323+ int timeout;
324+
292325 if (pxp->arb_is_valid)
293326 return 0;
294327 /*
@@ -297,7 +330,9 @@ static int __pxp_global_teardown_restart(struct intel_pxp *pxp) · 2 unmodified lines
297330 */
298331 pxp_queue_termination(pxp);
299332
300− if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(250)))
333+ timeout = intel_pxp_get_backend_timeout_ms(pxp);
334+
335+ if (!wait_for_completion_timeout(&pxp->termination, msecs_to_jiffies(timeout)))
301336 return -ETIMEDOUT;
302337
303338 return 0;
@@ -324,6 +359,26 @@ void intel_pxp_end(struct intel_pxp *pxp) · 20 unmodified lines
324359 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
325360 }
326361
362+/*
363+ * this helper is used by both intel_pxp_start and by
364+ * the GET_PARAM IOCTL that user space calls. Thus, the
365+ * return values here should match the UAPI spec.
366+ */
367+int intel_pxp_get_readiness_status(struct intel_pxp *pxp)
368+{
369+ if (!intel_pxp_is_enabled(pxp))
370+ return -ENODEV;
371+
372+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0)) {
373+ if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp), 250))
374+ return 2;
375+ } else {
376+ if (wait_for(pxp_component_bound(pxp), 250))
377+ return 2;
378+ }
379+ return 1;
380+}
381+
327382 /*
328383 * the arb session is restarted from the irq work when we receive the
329384 * termination completion interrupt
@@ -332,11 +387,11 @@ int intel_pxp_start(struct intel_pxp *pxp) · 2 unmodified lines
332387 {
333388 int ret = 0;
334389
335− if (!intel_pxp_is_enabled(pxp))
336− return -ENODEV;
337−
338− if (wait_for(pxp_component_bound(pxp), 250))
339− return -ENXIO;
390+ ret = intel_pxp_get_readiness_status(pxp);
391+ if (ret < 0)
392+ return ret;
393+ else if (ret > 1)
394+ return -EIO; /* per UAPI spec, user may retry later */
340395
341396 mutex_lock(&pxp->arb_mutex);
342397
@@ -357,14 +412,13 @@ unlock: · 14 unmodified lines
357412
358413 void intel_pxp_init_hw(struct intel_pxp *pxp)
359414 {
360− kcr_pxp_enable(pxp->ctrl_gt);
415+ kcr_pxp_enable(pxp);
361416 intel_pxp_irq_enable(pxp);
362417 }
363418
364419 void intel_pxp_fini_hw(struct intel_pxp *pxp)
365420 {
366− kcr_pxp_disable(pxp->ctrl_gt);
367−
421+ kcr_pxp_disable(pxp);
368422 intel_pxp_irq_disable(pxp);
369423 }
370424
drivers/gpu/drm/i915/pxp/intel_pxp.h+2−0
@@ -26,6 +26,8 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); · 25 unmodified lines
2626 void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
2727 void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);
2828
29+int intel_pxp_get_readiness_status(struct intel_pxp *pxp);
30+int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp);
2931 int intel_pxp_start(struct intel_pxp *pxp);
3032 void intel_pxp_end(struct intel_pxp *pxp);
3133
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h+24−0
@@ -11,6 +11,10 @@ · 10 unmodified lines
1111
1212 /* PXP-Cmd-Op definitions */
1313 #define PXP43_CMDID_START_HUC_AUTH 0x0000003A
14+#define PXP43_CMDID_INIT_SESSION 0x00000036
15+
16+/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
17+#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K)
1418
1519 /* PXP-Input-Packet: HUC-Authentication */
1620 struct pxp43_start_huc_auth_in {
@@ -23,4 +27,24 @@ struct pxp43_start_huc_auth_out { · 6 unmodified lines
2327 struct pxp_cmd_header header;
2428 } __packed;
2529
30+/* PXP-Input-Packet: Init PXP session */
31+struct pxp43_create_arb_in {
32+ struct pxp_cmd_header header;
33+ /* header.stream_id fields for vesion 4.3 of Init PXP session: */
34+ #define PXP43_INIT_SESSION_VALID BIT(0)
35+ #define PXP43_INIT_SESSION_APPTYPE BIT(1)
36+ #define PXP43_INIT_SESSION_APPID GENMASK(17, 2)
37+ u32 protection_mode;
38+ #define PXP43_INIT_SESSION_PROTECTION_ARB 0x2
39+ u32 sub_session_id;
40+ u32 init_flags;
41+ u32 rsvd[12];
42+} __packed;
43+
44+/* PXP-Input-Packet: Init PXP session */
45+struct pxp43_create_arb_out {
46+ struct pxp_cmd_header header;
47+ u32 rsvd[8];
48+} __packed;
49+
2650 #endif /* __INTEL_PXP_FW_INTERFACE_43_H__ */
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c+5−1
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414
1515 #include "intel_pxp.h"
1616 #include "intel_pxp_debugfs.h"
17+#include "intel_pxp_gsccs.h"
1718 #include "intel_pxp_irq.h"
1819 #include "intel_pxp_types.h"
1920
@@ -45,6 +46,7 @@ static int pxp_terminate_set(void *data, u64 val) · 25 unmodified lines
4546 {
4647 struct intel_pxp *pxp = data;
4748 struct intel_gt *gt = pxp->ctrl_gt;
49+ int timeout_ms;
4850
4951 if (!intel_pxp_is_active(pxp))
5052 return -ENODEV;
@@ -54,8 +56,10 @@ static int pxp_terminate_set(void *data, u64 val) · 3 unmodified lines
5456 intel_pxp_irq_handler(pxp, GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT);
5557 spin_unlock_irq(gt->irq_lock);
5658
59+ timeout_ms = intel_pxp_get_backend_timeout_ms(pxp);
60+
5761 if (!wait_for_completion_timeout(&pxp->termination,
58− msecs_to_jiffies(100)))
62+ msecs_to_jiffies(timeout_ms)))
5963 return -ETIMEDOUT;
6064
6165 return 0;
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c+444−0
@@ -0,0 +1,444 @@
1+// SPDX-License-Identifier: MIT
2+/*
3+ * Copyright(c) 2023 Intel Corporation.
4+ */
5+
6+#include "gem/i915_gem_internal.h"
7+
8+#include "gt/intel_context.h"
9+#include "gt/uc/intel_gsc_fw.h"
10+#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
11+
12+#include "i915_drv.h"
13+#include "intel_pxp.h"
14+#include "intel_pxp_cmd_interface_42.h"
15+#include "intel_pxp_cmd_interface_43.h"
16+#include "intel_pxp_gsccs.h"
17+#include "intel_pxp_types.h"
18+
19+static bool
20+is_fw_err_platform_config(u32 type)
21+{
22+ switch (type) {
23+ case PXP_STATUS_ERROR_API_VERSION:
24+ case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
25+ case PXP_STATUS_PLATFCONFIG_KF1_BAD:
26+ return true;
27+ default:
28+ break;
29+ }
30+ return false;
31+}
32+
33+static const char *
34+fw_err_to_string(u32 type)
35+{
36+ switch (type) {
37+ case PXP_STATUS_ERROR_API_VERSION:
38+ return "ERR_API_VERSION";
39+ case PXP_STATUS_NOT_READY:
40+ return "ERR_NOT_READY";
41+ case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
42+ case PXP_STATUS_PLATFCONFIG_KF1_BAD:
43+ return "ERR_PLATFORM_CONFIG";
44+ default:
45+ break;
46+ }
47+ return NULL;
48+}
49+
50+static int
51+gsccs_send_message(struct intel_pxp *pxp,
52+ void *msg_in, size_t msg_in_size,
53+ void *msg_out, size_t msg_out_size_max,
54+ size_t *msg_out_len,
55+ u64 *gsc_msg_handle_retry)
56+{
57+ struct intel_gt *gt = pxp->ctrl_gt;
58+ struct drm_i915_private *i915 = gt->i915;
59+ struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
60+ struct intel_gsc_mtl_header *header = exec_res->pkt_vaddr;
61+ struct intel_gsc_heci_non_priv_pkt pkt;
62+ size_t max_msg_size;
63+ u32 reply_size;
64+ int ret;
65+
66+ if (!exec_res->ce)
67+ return -ENODEV;
68+
69+ max_msg_size = PXP43_MAX_HECI_INOUT_SIZE - sizeof(*header);
70+
71+ if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size)
72+ return -ENOSPC;
73+
74+ if (!exec_res->pkt_vma || !exec_res->bb_vma)
75+ return -ENOENT;
76+
77+ GEM_BUG_ON(exec_res->pkt_vma->size < (2 * PXP43_MAX_HECI_INOUT_SIZE));
78+
79+ mutex_lock(&pxp->tee_mutex);
80+
81+ memset(header, 0, sizeof(*header));
82+ intel_gsc_uc_heci_cmd_emit_mtl_header(header, HECI_MEADDRESS_PXP,
83+ msg_in_size + sizeof(*header),
84+ exec_res->host_session_handle);
85+
86+ /* check if this is a host-session-handle cleanup call (empty packet) */
87+ if (!msg_in && !msg_out)
88+ header->flags |= GSC_INFLAG_MSG_CLEANUP;
89+
90+ /* copy caller provided gsc message handle if this is polling for a prior msg completion */
91+ header->gsc_message_handle = *gsc_msg_handle_retry;
92+
93+ /* NOTE: zero size packets are used for session-cleanups */
94+ if (msg_in && msg_in_size)
95+ memcpy(exec_res->pkt_vaddr + sizeof(*header), msg_in, msg_in_size);
96+
97+ pkt.addr_in = i915_vma_offset(exec_res->pkt_vma);
98+ pkt.size_in = header->message_size;
99+ pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_INOUT_SIZE;
100+ pkt.size_out = msg_out_size_max + sizeof(*header);
101+ pkt.heci_pkt_vma = exec_res->pkt_vma;
102+ pkt.bb_vma = exec_res->bb_vma;
103+
104+ /*
105+ * Before submitting, let's clear-out the validity marker on the reply offset.
106+ * We use offset PXP43_MAX_HECI_INOUT_SIZE for reply location so point header there.
107+ */
108+ header = exec_res->pkt_vaddr + PXP43_MAX_HECI_INOUT_SIZE;
109+ header->validity_marker = 0;
110+
111+ ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&gt->uc.gsc,
112+ exec_res->ce, &pkt, exec_res->bb_vaddr,
113+ GSC_REPLY_LATENCY_MS);
114+ if (ret) {
115+ drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);
116+ goto unlock;
117+ }
118+
119+ /* Response validity marker, status and busyness */
120+ if (header->validity_marker != GSC_HECI_VALIDITY_MARKER) {
121+ drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n");
122+ ret = -EINVAL;
123+ goto unlock;
124+ }
125+ if (header->status != 0) {
126+ drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n",
127+ header->status);
128+ ret = -EINVAL;
129+ goto unlock;
130+ }
131+ if (header->flags & GSC_OUTFLAG_MSG_PENDING) {
132+ drm_dbg(&i915->drm, "gsc PXP reply is busy\n");
133+ /*
134+ * When the GSC firmware replies with pending bit, it means that the requested
135+ * operation has begun but the completion is pending and the caller needs
136+ * to re-request with the gsc_message_handle that was returned by the firmware.
137+ * until the pending bit is turned off.
138+ */
139+ *gsc_msg_handle_retry = header->gsc_message_handle;
140+ ret = -EAGAIN;
141+ goto unlock;
142+ }
143+
144+ reply_size = header->message_size - sizeof(*header);
145+ if (reply_size > msg_out_size_max) {
146+ drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
147+ reply_size, msg_out_size_max);
148+ reply_size = msg_out_size_max;
149+ }
150+
151+ if (msg_out)
152+ memcpy(msg_out, exec_res->pkt_vaddr + PXP43_MAX_HECI_INOUT_SIZE + sizeof(*header),
153+ reply_size);
154+ if (msg_out_len)
155+ *msg_out_len = reply_size;
156+
157+unlock:
158+ mutex_unlock(&pxp->tee_mutex);
159+ return ret;
160+}
161+
162+static int
163+gsccs_send_message_retry_complete(struct intel_pxp *pxp,
164+ void *msg_in, size_t msg_in_size,
165+ void *msg_out, size_t msg_out_size_max,
166+ size_t *msg_out_len)
167+{
168+ u64 gsc_session_retry = 0;
169+ int ret, tries = 0;
170+
171+ /*
172+ * Keep sending request if GSC firmware was busy. Based on fw specs +
173+ * sw overhead (and testing) we expect a worst case pending-bit delay of
174+ * GSC_PENDING_RETRY_MAXCOUNT x GSC_PENDING_RETRY_PAUSE_MS millisecs.
175+ */
176+ do {
177+ ret = gsccs_send_message(pxp, msg_in, msg_in_size, msg_out, msg_out_size_max,
178+ msg_out_len, &gsc_session_retry);
179+ /* Only try again if gsc says so */
180+ if (ret != -EAGAIN)
181+ break;
182+
183+ msleep(GSC_PENDING_RETRY_PAUSE_MS);
184+ } while (++tries < GSC_PENDING_RETRY_MAXCOUNT);
185+
186+ return ret;
187+}
188+
189+bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp)
190+{
191+ /*
192+ * GSC-fw loading, HuC-fw loading, HuC-fw authentication and
193+ * GSC-proxy init flow (requiring an mei component driver)
194+ * must all occur first before we can start requesting for PXP
195+ * sessions. Checking for completion on HuC authentication and
196+ * gsc-proxy init flow (the last set of dependencies that
197+ * are out of order) will suffice.
198+ */
199+ if (intel_huc_is_authenticated(&pxp->ctrl_gt->uc.huc) &&
200+ intel_gsc_uc_fw_proxy_init_done(&pxp->ctrl_gt->uc.gsc))
201+ return true;
202+
203+ return false;
204+}
205+
206+int intel_pxp_gsccs_create_session(struct intel_pxp *pxp,
207+ int arb_session_id)
208+{
209+ struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
210+ struct pxp43_create_arb_in msg_in = {0};
211+ struct pxp43_create_arb_out msg_out = {0};
212+ int ret;
213+
214+ msg_in.header.api_version = PXP_APIVER(4, 3);
215+ msg_in.header.command_id = PXP43_CMDID_INIT_SESSION;
216+ msg_in.header.stream_id = (FIELD_PREP(PXP43_INIT_SESSION_APPID, arb_session_id) |
217+ FIELD_PREP(PXP43_INIT_SESSION_VALID, 1) |
218+ FIELD_PREP(PXP43_INIT_SESSION_APPTYPE, 0));
219+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
220+ msg_in.protection_mode = PXP43_INIT_SESSION_PROTECTION_ARB;
221+
222+ ret = gsccs_send_message_retry_complete(pxp,
223+ &msg_in, sizeof(msg_in),
224+ &msg_out, sizeof(msg_out), NULL);
225+ if (ret) {
226+ drm_err(&i915->drm, "Failed to init session %d, ret=[%d]\n", arb_session_id, ret);
227+ } else if (msg_out.header.status != 0) {
228+ if (is_fw_err_platform_config(msg_out.header.status)) {
229+ drm_info_once(&i915->drm,
230+ "PXP init-session-%d failed due to BIOS/SOC:0x%08x:%s\n",
231+ arb_session_id, msg_out.header.status,
232+ fw_err_to_string(msg_out.header.status));
233+ } else {
234+ drm_dbg(&i915->drm, "PXP init-session-%d failed 0x%08x:%st:\n",
235+ arb_session_id, msg_out.header.status,
236+ fw_err_to_string(msg_out.header.status));
237+ drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n",
238+ msg_in.header.command_id, msg_in.header.api_version);
239+ }
240+ }
241+
242+ return ret;
243+}
244+
245+void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id)
246+{
247+ struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
248+ struct pxp42_inv_stream_key_in msg_in = {0};
249+ struct pxp42_inv_stream_key_out msg_out = {0};
250+ int ret = 0;
251+
252+ /*
253+ * Stream key invalidation reuses the same version 4.2 input/output
254+ * command format but firmware requires 4.3 API interaction
255+ */
256+ msg_in.header.api_version = PXP_APIVER(4, 3);
257+ msg_in.header.command_id = PXP42_CMDID_INVALIDATE_STREAM_KEY;
258+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
259+
260+ msg_in.header.stream_id = FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_VALID, 1);
261+ msg_in.header.stream_id |= FIELD_PREP(PXP_CMDHDR_EXTDATA_APP_TYPE, 0);
262+ msg_in.header.stream_id |= FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_ID, session_id);
263+
264+ ret = gsccs_send_message_retry_complete(pxp,
265+ &msg_in, sizeof(msg_in),
266+ &msg_out, sizeof(msg_out), NULL);
267+ if (ret) {
268+ drm_err(&i915->drm, "Failed to inv-stream-key-%u, ret=[%d]\n",
269+ session_id, ret);
270+ } else if (msg_out.header.status != 0) {
271+ if (is_fw_err_platform_config(msg_out.header.status)) {
272+ drm_info_once(&i915->drm,
273+ "PXP inv-stream-key-%u failed due to BIOS/SOC :0x%08x:%s\n",
274+ session_id, msg_out.header.status,
275+ fw_err_to_string(msg_out.header.status));
276+ } else {
277+ drm_dbg(&i915->drm, "PXP inv-stream-key-%u failed 0x%08x:%s:\n",
278+ session_id, msg_out.header.status,
279+ fw_err_to_string(msg_out.header.status));
280+ drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n",
281+ msg_in.header.command_id, msg_in.header.api_version);
282+ }
283+ }
284+}
285+
286+static void
287+gsccs_cleanup_fw_host_session_handle(struct intel_pxp *pxp)
288+{
289+ struct drm_i915_private *i915 = pxp->ctrl_gt->i915;
290+ int ret;
291+
292+ ret = gsccs_send_message_retry_complete(pxp, NULL, 0, NULL, 0, NULL);
293+ if (ret)
294+ drm_dbg(&i915->drm, "Failed to send gsccs msg host-session-cleanup: ret=[%d]\n",
295+ ret);
296+}
297+
298+static void
299+gsccs_destroy_execution_resource(struct intel_pxp *pxp)
300+{
301+ struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
302+
303+ if (exec_res->host_session_handle)
304+ gsccs_cleanup_fw_host_session_handle(pxp);
305+ if (exec_res->ce)
306+ intel_context_put(exec_res->ce);
307+ if (exec_res->bb_vma)
308+ i915_vma_unpin_and_release(&exec_res->bb_vma, I915_VMA_RELEASE_MAP);
309+ if (exec_res->pkt_vma)
310+ i915_vma_unpin_and_release(&exec_res->pkt_vma, I915_VMA_RELEASE_MAP);
311+
312+ memset(exec_res, 0, sizeof(*exec_res));
313+}
314+
315+static int
316+gsccs_create_buffer(struct intel_gt *gt,
317+ const char *bufname, size_t size,
318+ struct i915_vma **vma, void **map)
319+{
320+ struct drm_i915_private *i915 = gt->i915;
321+ struct drm_i915_gem_object *obj;
322+ int err = 0;
323+
324+ obj = i915_gem_object_create_internal(i915, size);
325+ if (IS_ERR(obj)) {
326+ drm_err(&i915->drm, "Failed to allocate gsccs backend %s.\n", bufname);
327+ err = PTR_ERR(obj);
328+ goto out_none;
329+ }
330+
331+ *vma = i915_vma_instance(obj, gt->vm, NULL);
332+ if (IS_ERR(*vma)) {
333+ drm_err(&i915->drm, "Failed to vma-instance gsccs backend %s.\n", bufname);
334+ err = PTR_ERR(*vma);
335+ goto out_put;
336+ }
337+
338+ /* return a virtual pointer */
339+ *map = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(i915, obj, true));
340+ if (IS_ERR(*map)) {
341+ drm_err(&i915->drm, "Failed to map gsccs backend %s.\n", bufname);
342+ err = PTR_ERR(*map);
343+ goto out_put;
344+ }
345+
346+ /* all PXP sessions commands are treated as non-privileged */
347+ err = i915_vma_pin(*vma, 0, 0, PIN_USER);
348+ if (err) {
349+ drm_err(&i915->drm, "Failed to vma-pin gsccs backend %s.\n", bufname);
350+ goto out_unmap;
351+ }
352+
353+ return 0;
354+
355+out_unmap:
356+ i915_gem_object_unpin_map(obj);
357+out_put:
358+ i915_gem_object_put(obj);
359+out_none:
360+ *vma = NULL;
361+ *map = NULL;
362+
363+ return err;
364+}
365+
366+static int
367+gsccs_allocate_execution_resource(struct intel_pxp *pxp)
368+{
369+ struct intel_gt *gt = pxp->ctrl_gt;
370+ struct gsccs_session_resources *exec_res = &pxp->gsccs_res;
371+ struct intel_engine_cs *engine = gt->engine[GSC0];
372+ struct intel_context *ce;
373+ int err = 0;
374+
375+ /*
376+ * First, ensure the GSC engine is present.
377+ * NOTE: Backend would only be called with the correct gt.
378+ */
379+ if (!engine)
380+ return -ENODEV;
381+
382+ /*
383+ * Now, allocate, pin and map two objects, one for the heci message packet
384+ * and another for the batch buffer we submit into GSC engine (that includes the packet).
385+ * NOTE: GSC-CS backend is currently only supported on MTL, so we allocate shmem.
386+ */
387+ err = gsccs_create_buffer(pxp->ctrl_gt, "Heci Packet",
388+ 2 * PXP43_MAX_HECI_INOUT_SIZE,
389+ &exec_res->pkt_vma, &exec_res->pkt_vaddr);
390+ if (err)
391+ return err;
392+
393+ err = gsccs_create_buffer(pxp->ctrl_gt, "Batch Buffer", PAGE_SIZE,
394+ &exec_res->bb_vma, &exec_res->bb_vaddr);
395+ if (err)
396+ goto free_pkt;
397+
398+ /* Finally, create an intel_context to be used during the submission */
399+ ce = intel_context_create(engine);
400+ if (IS_ERR(ce)) {
401+ drm_err(&gt->i915->drm, "Failed creating gsccs backend ctx\n");
402+ err = PTR_ERR(ce);
403+ goto free_batch;
404+ }
405+
406+ i915_vm_put(ce->vm);
407+ ce->vm = i915_vm_get(pxp->ctrl_gt->vm);
408+ exec_res->ce = ce;
409+
410+ /* initialize host-session-handle (for all i915-to-gsc-firmware PXP cmds) */
411+ get_random_bytes(&exec_res->host_session_handle, sizeof(exec_res->host_session_handle));
412+
413+ return 0;
414+
415+free_batch:
416+ i915_vma_unpin_and_release(&exec_res->bb_vma, I915_VMA_RELEASE_MAP);
417+free_pkt:
418+ i915_vma_unpin_and_release(&exec_res->pkt_vma, I915_VMA_RELEASE_MAP);
419+ memset(exec_res, 0, sizeof(*exec_res));
420+
421+ return err;
422+}
423+
424+void intel_pxp_gsccs_fini(struct intel_pxp *pxp)
425+{
426+ intel_wakeref_t wakeref;
427+
428+ gsccs_destroy_execution_resource(pxp);
429+ with_intel_runtime_pm(&pxp->ctrl_gt->i915->runtime_pm, wakeref)
430+ intel_pxp_fini_hw(pxp);
431+}
432+
433+int intel_pxp_gsccs_init(struct intel_pxp *pxp)
434+{
435+ int ret;
436+ intel_wakeref_t wakeref;
437+
438+ ret = gsccs_allocate_execution_resource(pxp);
439+ if (!ret) {
440+ with_intel_runtime_pm(&pxp->ctrl_gt->i915->runtime_pm, wakeref)
441+ intel_pxp_init_hw(pxp);
442+ }
443+ return ret;
444+}
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h+43−0
@@ -0,0 +1,43 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright(c) 2022, Intel Corporation. All rights reserved.
4+ */
5+
6+#ifndef __INTEL_PXP_GSCCS_H__
7+#define __INTEL_PXP_GSCCS_H__
8+
9+#include <linux/types.h>
10+
11+struct intel_pxp;
12+
13+#define GSC_REPLY_LATENCY_MS 210
14+/*
15+ * Max FW response time is 200ms, to which we add 10ms to account for overhead
16+ * such as request preparation, GuC submission to hw and pipeline completion times.
17+ */
18+#define GSC_PENDING_RETRY_MAXCOUNT 40
19+#define GSC_PENDING_RETRY_PAUSE_MS 50
20+#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)
21+
22+#ifdef CONFIG_DRM_I915_PXP
23+void intel_pxp_gsccs_fini(struct intel_pxp *pxp);
24+int intel_pxp_gsccs_init(struct intel_pxp *pxp);
25+
26+int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id);
27+void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);
28+
29+#else
30+static inline void intel_pxp_gsccs_fini(struct intel_pxp *pxp)
31+{
32+}
33+
34+static inline int intel_pxp_gsccs_init(struct intel_pxp *pxp)
35+{
36+ return 0;
37+}
38+
39+#endif
40+
41+bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp);
42+
43+#endif /*__INTEL_PXP_GSCCS_H__ */
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c+2−1
@@ -43,8 +43,9 @@ void intel_pxp_resume_complete(struct intel_pxp *pxp) · 42 unmodified lines
4343 * The PXP component gets automatically unbound when we go into S3 and
4444 * re-bound after we come out, so in that scenario we can defer the
4545 * hw init to the bind call.
46+ * NOTE: GSC-CS backend doesn't rely on components.
4647 */
47− if (!pxp->pxp_component)
48+ if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
4849 return;
4950
5051 intel_pxp_init_hw(pxp);
drivers/gpu/drm/i915/pxp/intel_pxp_regs.h+27−0
@@ -0,0 +1,27 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright(c) 2023, Intel Corporation. All rights reserved.
4+ */
5+
6+#ifndef __INTEL_PXP_REGS_H__
7+#define __INTEL_PXP_REGS_H__
8+
9+#include "i915_reg_defs.h"
10+
11+/* KCR subsystem register base address */
12+#define GEN12_KCR_BASE 0x32000
13+#define MTL_KCR_BASE 0x386000
14+
15+/* KCR enable/disable control */
16+#define KCR_INIT(base) _MMIO((base) + 0xf0)
17+
18+/* Setting KCR Init bit is required after system boot */
19+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
20+
21+/* KCR hwdrm session in play status 0-31 */
22+#define KCR_SIP(base) _MMIO((base) + 0x260)
23+
24+/* PXP global terminate register for session termination */
25+#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
26+
27+#endif /* __INTEL_PXP_REGS_H__ */
drivers/gpu/drm/i915/pxp/intel_pxp_session.c+14−11
@@ -7,17 +7,14 @@ · 6 unmodified lines
77
88 #include "intel_pxp.h"
99 #include "intel_pxp_cmd.h"
10+#include "intel_pxp_gsccs.h"
1011 #include "intel_pxp_session.h"
1112 #include "intel_pxp_tee.h"
1213 #include "intel_pxp_types.h"
14+#include "intel_pxp_regs.h"
1315
1416 #define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
1517
16−#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
17−
18−/* PXP global terminate register for session termination */
19−#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
20−
2118 static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
2219 {
2320 struct intel_uncore *uncore = pxp->ctrl_gt->uncore;
@@ -26,7 +23,7 @@ static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id) · 2 unmodified lines
2623
2724 /* if we're suspended the session is considered off */
2825 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
29− sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
26+ sip = intel_uncore_read(uncore, KCR_SIP(pxp->kcr_base));
3027
3128 return sip & BIT(id);
3229 }
@@ -44,10 +41,10 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla · 11 unmodified lines
4441 return in_play ? -ENODEV : 0;
4542
4643 ret = intel_wait_for_register(uncore,
47− GEN12_KCR_SIP,
44+ KCR_SIP(pxp->kcr_base),
4845 mask,
4946 in_play ? mask : 0,
50− 100);
47+ 250);
5148
5249 intel_runtime_pm_put(uncore->rpm, wakeref);
5350
@@ -66,7 +63,10 @@ static int pxp_create_arb_session(struct intel_pxp *pxp) · 12 unmodified lines
6663 return -EEXIST;
6764 }
6865
69− ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
66+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
67+ ret = intel_pxp_gsccs_create_session(pxp, ARB_SESSION);
68+ else
69+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
7070 if (ret) {
7171 drm_err(&gt->i915->drm, "tee cmd for arb session creation failed\n");
7272 return ret;
@@ -108,9 +108,12 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp) · 35 unmodified lines
108108 return ret;
109109 }
110110
111− intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
111+ intel_uncore_write(gt->uncore, KCR_GLOBAL_TERMINATE(pxp->kcr_base), 1);
112112
113− intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);
113+ if (HAS_ENGINE(gt, GSC0))
114+ intel_pxp_gsccs_end_arb_fw_session(pxp, ARB_SESSION);
115+ else
116+ intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);
114117
115118 return ret;
116119 }
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c+0−2
@@ -284,8 +284,6 @@ int intel_pxp_tee_component_init(struct intel_pxp *pxp) · 283 unmodified lines
284284 struct intel_gt *gt = pxp->ctrl_gt;
285285 struct drm_i915_private *i915 = gt->i915;
286286
287− mutex_init(&pxp->tee_mutex);
288−
289287 ret = alloc_streaming_command(pxp);
290288 if (ret)
291289 return ret;
drivers/gpu/drm/i915/pxp/intel_pxp_types.h+23−1
@@ -26,6 +26,26 @@ struct intel_pxp { · 25 unmodified lines
2626 */
2727 struct intel_gt *ctrl_gt;
2828
29+ /**
30+ * @kcr_base: base mmio offset for the KCR engine which is different on legacy platforms
31+ * vs newer platforms where the KCR is inside the media-tile.
32+ */
33+ u32 kcr_base;
34+
35+ /**
36+ * @gsccs_res: resources for request submission for platforms that have a GSC engine.
37+ */
38+ struct gsccs_session_resources {
39+ u64 host_session_handle; /* used by firmware to link commands to sessions */
40+ struct intel_context *ce; /* context for gsc command submission */
41+
42+ struct i915_vma *pkt_vma; /* GSC FW cmd packet vma */
43+ void *pkt_vaddr; /* GSC FW cmd packet virt pointer */
44+
45+ struct i915_vma *bb_vma; /* HECI_PKT batch buffer vma */
46+ void *bb_vaddr; /* HECI_PKT batch buffer virt pointer */
47+ } gsccs_res;
48+
2949 /**
3050 * @pxp_component: i915_pxp_component struct of the bound mei_pxp
3151 * module. Only set and cleared inside component bind/unbind functions,
@@ -33,7 +53,9 @@ struct intel_pxp { · 1 unmodified line
3353 */
3454 struct i915_pxp_component *pxp_component;
3555
36− /* @dev_link: Enforce module relationship for power management ordering. */
56+ /**
57+ * @dev_link: Enforce module relationship for power management ordering.
58+ */
3759 struct device_link *dev_link;
3860 /**
3961 * @pxp_component_added: track if the pxp component has been added.
drivers/gpu/drm/i915/selftests/i915_gem.c+4−1
@@ -57,7 +57,10 @@ static void trash_stolen(struct drm_i915_private *i915) · 56 unmodified lines
5757 u32 __iomem *s;
5858 int x;
5959
60− ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
60+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
61+ i915_gem_get_pat_index(i915,
62+ I915_CACHE_NONE),
63+ 0);
6164
6265 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
6366 for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
drivers/gpu/drm/i915/selftests/i915_gem_evict.c+5−3
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 #include "gem/selftests/igt_gem_utils.h"
2828 #include "gem/selftests/mock_context.h"
2929 #include "gt/intel_gt.h"
30+#include "gt/intel_gt_print.h"
3031
3132 #include "i915_selftest.h"
3233
@@ -245,7 +246,7 @@ static int igt_evict_for_cache_color(void *arg) · 212 unmodified lines
245246 struct drm_mm_node target = {
246247 .start = I915_GTT_PAGE_SIZE * 2,
247248 .size = I915_GTT_PAGE_SIZE,
248− .color = I915_CACHE_LLC,
249+ .color = i915_gem_get_pat_index(gt->i915, I915_CACHE_LLC),
249250 };
250251 struct drm_i915_gem_object *obj;
251252 struct i915_vma *vma;
@@ -308,7 +309,7 @@ static int igt_evict_for_cache_color(void *arg) · 56 unmodified lines
308309 /* Attempt to remove the first *pinned* vma, by removing the (empty)
309310 * neighbour -- this should fail.
310311 */
311− target.color = I915_CACHE_L3_LLC;
312+ target.color = i915_gem_get_pat_index(gt->i915, I915_CACHE_L3_LLC);
312313
313314 mutex_lock(&ggtt->vm.mutex);
314315 err = i915_gem_evict_for_node(&ggtt->vm, NULL, &target, 0);
@@ -507,7 +508,8 @@ static int igt_evict_contexts(void *arg) · 192 unmodified lines
507508 }
508509 err = intel_gt_wait_for_idle(engine->gt, HZ * 3);
509510 if (err) {
510− pr_err("Failed to idle GT (on %s)", engine->name);
511+ gt_err(engine->gt, "Failed to idle GT (on %s)",
512+ engine->name);
511513 break;
512514 }
513515 }
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c+10−5
@@ -135,7 +135,7 @@ fake_dma_object(struct drm_i915_private *i915, u64 size) · 134 unmodified lines
135135
136136 obj->write_domain = I915_GEM_DOMAIN_CPU;
137137 obj->read_domains = I915_GEM_DOMAIN_CPU;
138− obj->cache_level = I915_CACHE_NONE;
138+ obj->pat_index = i915_gem_get_pat_index(i915, I915_CACHE_NONE);
139139
140140 /* Preallocate the "backing storage" */
141141 if (i915_gem_object_pin_pages_unlocked(obj))
@@ -359,7 +359,9 @@ alloc_vm_end: · 217 unmodified lines
359359
360360 with_intel_runtime_pm(vm->gt->uncore->rpm, wakeref)
361361 vm->insert_entries(vm, mock_vma_res,
362− I915_CACHE_NONE, 0);
362+ i915_gem_get_pat_index(vm->i915,
363+ I915_CACHE_NONE),
364+ 0);
363365 }
364366 count = n;
365367
@@ -1377,7 +1379,10 @@ static int igt_ggtt_page(void *arg) · 1011 unmodified lines
13771379
13781380 ggtt->vm.insert_page(&ggtt->vm,
13791381 i915_gem_object_get_dma_address(obj, 0),
1380− offset, I915_CACHE_NONE, 0);
1382+ offset,
1383+ i915_gem_get_pat_index(i915,
1384+ I915_CACHE_NONE),
1385+ 0);
13811386 }
13821387
13831388 order = i915_random_order(count, &prng);
@@ -1510,7 +1515,7 @@ static int reserve_gtt_with_resource(struct i915_vma *vma, u64 offset) · 126 unmodified lines
15101515 mutex_lock(&vm->mutex);
15111516 err = i915_gem_gtt_reserve(vm, NULL, &vma->node, obj->base.size,
15121517 offset,
1513− obj->cache_level,
1518+ obj->pat_index,
15141519 0);
15151520 if (!err) {
15161521 i915_vma_resource_init_from_vma(vma_res, vma);
@@ -1690,7 +1695,7 @@ static int insert_gtt_with_resource(struct i915_vma *vma) · 173 unmodified lines
16901695
16911696 mutex_lock(&vm->mutex);
16921697 err = i915_gem_gtt_insert(vm, NULL, &vma->node, obj->base.size, 0,
1693− obj->cache_level, 0, vm->total, 0);
1698+ obj->pat_index, 0, vm->total, 0);
16941699 if (!err) {
16951700 i915_vma_resource_init_from_vma(vma_res, vma);
16961701 vma->resource = vma_res;
drivers/gpu/drm/i915/selftests/igt_live_test.c+28−19
@@ -6,6 +6,7 @@ · 5 unmodified lines
66
77 #include "i915_drv.h"
88 #include "gt/intel_gt.h"
9+#include "gt/intel_gt_print.h"
910
1011 #include "../i915_selftest.h"
1112 #include "igt_flush_test.h"
@@ -16,27 +17,31 @@ int igt_live_test_begin(struct igt_live_test *t, · 4 unmodified lines
1617 const char *func,
1718 const char *name)
1819 {
19− struct intel_gt *gt = to_gt(i915);
2020 struct intel_engine_cs *engine;
2121 enum intel_engine_id id;
22+ struct intel_gt *gt;
23+ unsigned int i;
2224 int err;
2325
2426 t->i915 = i915;
2527 t->func = func;
2628 t->name = name;
2729
28− err = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
29− if (err) {
30− pr_err("%s(%s): failed to idle before, with err=%d!",
31− func, name, err);
32− return err;
33− }
30+ for_each_gt(gt, i915, i) {
3431
35− t->reset_global = i915_reset_count(&i915->gpu_error);
32+ err = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
33+ if (err) {
34+ gt_err(gt, "%s(%s): GT failed to idle before, with err=%d!",
35+ func, name, err);
36+ return err;
37+ }
3638
37− for_each_engine(engine, gt, id)
38− t->reset_engine[id] =
39+ for_each_engine(engine, gt, id)
40+ t->reset_engine[id] =
3941 i915_reset_engine_count(&i915->gpu_error, engine);
42+ }
43+
44+ t->reset_global = i915_reset_count(&i915->gpu_error);
4045
4146 return 0;
4247 }
@@ -46,6 +51,8 @@ int igt_live_test_end(struct igt_live_test *t) · 3 unmodified lines
4651 struct drm_i915_private *i915 = t->i915;
4752 struct intel_engine_cs *engine;
4853 enum intel_engine_id id;
54+ struct intel_gt *gt;
55+ unsigned int i;
4956
5057 if (igt_flush_test(i915))
5158 return -EIO;
@@ -57,16 +64,18 @@ int igt_live_test_end(struct igt_live_test *t) · 5 unmodified lines
5764 return -EIO;
5865 }
5966
60− for_each_engine(engine, to_gt(i915), id) {
61− if (t->reset_engine[id] ==
62− i915_reset_engine_count(&i915->gpu_error, engine))
63− continue;
67+ for_each_gt(gt, i915, i) {
68+ for_each_engine(engine, gt, id) {
69+ if (t->reset_engine[id] ==
70+ i915_reset_engine_count(&i915->gpu_error, engine))
71+ continue;
6472
65− pr_err("%s(%s): engine '%s' was reset %d times!\n",
66− t->func, t->name, engine->name,
67− i915_reset_engine_count(&i915->gpu_error, engine) -
68− t->reset_engine[id]);
69− return -EIO;
73+ gt_err(gt, "%s(%s): engine '%s' was reset %d times!\n",
74+ t->func, t->name, engine->name,
75+ i915_reset_engine_count(&i915->gpu_error, engine) -
76+ t->reset_engine[id]);
77+ return -EIO;
78+ }
7079 }
7180
7281 return 0;
drivers/gpu/drm/i915/selftests/intel_memory_region.c+3−1
@@ -1070,7 +1070,9 @@ static int igt_lmem_write_cpu(void *arg) · 1069 unmodified lines
10701070 /* Put the pages into a known state -- from the gpu for added fun */
10711071 intel_engine_pm_get(engine);
10721072 err = intel_context_migrate_clear(engine->gt->migrate.context, NULL,
1073− obj->mm.pages->sgl, I915_CACHE_NONE,
1073+ obj->mm.pages->sgl,
1074+ i915_gem_get_pat_index(i915,
1075+ I915_CACHE_NONE),
10741076 true, 0xdeadbeaf, &rq);
10751077 if (rq) {
10761078 dma_resv_add_fence(obj->base.resv, &rq->fence,
drivers/gpu/drm/i915/selftests/mock_gem_device.c+9−0
@@ -123,7 +123,9 @@ struct drm_i915_private *mock_gem_device(void) · 122 unmodified lines
123123 static struct dev_iommu fake_iommu = { .priv = (void *)-1 };
124124 #endif
125125 struct drm_i915_private *i915;
126+ struct intel_device_info *i915_info;
126127 struct pci_dev *pdev;
128+ unsigned int i;
127129 int ret;
128130
129131 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
@@ -180,6 +182,13 @@ struct drm_i915_private *mock_gem_device(void) · 50 unmodified lines
180182 I915_GTT_PAGE_SIZE_2M;
181183
182184 RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
185+
186+ /* simply use legacy cache level for mock device */
187+ i915_info = (struct intel_device_info *)INTEL_INFO(i915);
188+ i915_info->max_pat_index = 3;
189+ for (i = 0; i < I915_MAX_CACHE_LEVEL; i++)
190+ i915_info->cachelevel_to_pat[i] = i;
191+
183192 intel_memory_regions_hw_probe(i915);
184193
185194 spin_lock_init(&i915->gpu_error.lock);
drivers/gpu/drm/i915/selftests/mock_gtt.c+4−4
@@ -27,21 +27,21 @@ · 26 unmodified lines
2727 static void mock_insert_page(struct i915_address_space *vm,
2828 dma_addr_t addr,
2929 u64 offset,
30− enum i915_cache_level level,
30+ unsigned int pat_index,
3131 u32 flags)
3232 {
3333 }
3434
3535 static void mock_insert_entries(struct i915_address_space *vm,
3636 struct i915_vma_resource *vma_res,
37− enum i915_cache_level level, u32 flags)
37+ unsigned int pat_index, u32 flags)
3838 {
3939 }
4040
4141 static void mock_bind_ppgtt(struct i915_address_space *vm,
4242 struct i915_vm_pt_stash *stash,
4343 struct i915_vma_resource *vma_res,
44− enum i915_cache_level cache_level,
44+ unsigned int pat_index,
4545 u32 flags)
4646 {
4747 GEM_BUG_ON(flags & I915_VMA_GLOBAL_BIND);
@@ -94,7 +94,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) · 46 unmodified lines
9494 static void mock_bind_ggtt(struct i915_address_space *vm,
9595 struct i915_vm_pt_stash *stash,
9696 struct i915_vma_resource *vma_res,
97− enum i915_cache_level cache_level,
97+ unsigned int pat_index,
9898 u32 flags)
9999 {
100100 }
drivers/gpu/drm/imx/lcdc/imx-lcdc.c+2−2
@@ -400,8 +400,8 @@ static int imx_lcdc_probe(struct platform_device *pdev) · 399 unmodified lines
400400
401401 lcdc = devm_drm_dev_alloc(dev, &imx_lcdc_drm_driver,
402402 struct imx_lcdc, drm);
403− if (!lcdc)
404− return -ENOMEM;
403+ if (IS_ERR(lcdc))
404+ return PTR_ERR(lcdc);
405405
406406 drm = &lcdc->drm;
407407
drivers/gpu/drm/meson/meson_drv.c+1−1
@@ -285,7 +285,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) · 284 unmodified lines
285285 * Remove early framebuffers (ie. simplefb). The framebuffer can be
286286 * located anywhere in RAM
287287 */
288− ret = drm_aperture_remove_framebuffers(false, &meson_driver);
288+ ret = drm_aperture_remove_framebuffers(&meson_driver);
289289 if (ret)
290290 goto free_drm;
291291
drivers/gpu/drm/meson/meson_venc.c+16−16
@@ -186,7 +186,7 @@ union meson_hdmi_venc_mode { · 185 unmodified lines
186186 } encp;
187187 };
188188
189−union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
189+static union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
190190 .enci = {
191191 .hso_begin = 5,
192192 .hso_end = 129,
@@ -206,7 +206,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { · 13 unmodified lines
206206 },
207207 };
208208
209−union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
209+static union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
210210 .enci = {
211211 .hso_begin = 3,
212212 .hso_end = 129,
@@ -226,7 +226,7 @@ union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { · 13 unmodified lines
226226 },
227227 };
228228
229−union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
229+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
230230 .encp = {
231231 .dvi_settings = 0x21,
232232 .video_mode = 0x4000,
@@ -272,7 +272,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { · 39 unmodified lines
272272 },
273273 };
274274
275−union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
275+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
276276 .encp = {
277277 .dvi_settings = 0x21,
278278 .video_mode = 0x4000,
@@ -318,7 +318,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { · 39 unmodified lines
318318 },
319319 };
320320
321−union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
321+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
322322 .encp = {
323323 .dvi_settings = 0x2029,
324324 .video_mode = 0x4040,
@@ -360,7 +360,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { · 35 unmodified lines
360360 },
361361 };
362362
363−union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
363+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
364364 .encp = {
365365 .dvi_settings = 0x202d,
366366 .video_mode = 0x4040,
@@ -405,7 +405,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { · 38 unmodified lines
405405 },
406406 };
407407
408−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
408+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
409409 .encp = {
410410 .dvi_settings = 0x2029,
411411 .video_mode = 0x5ffc,
@@ -454,7 +454,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { · 42 unmodified lines
454454 },
455455 };
456456
457−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
457+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
458458 .encp = {
459459 .dvi_settings = 0x202d,
460460 .video_mode = 0x5ffc,
@@ -503,7 +503,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { · 42 unmodified lines
503503 },
504504 };
505505
506−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
506+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
507507 .encp = {
508508 .dvi_settings = 0xd,
509509 .video_mode = 0x4040,
@@ -552,7 +552,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { · 42 unmodified lines
552552 },
553553 };
554554
555−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
555+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
556556 .encp = {
557557 .dvi_settings = 0x1,
558558 .video_mode = 0x4040,
@@ -596,7 +596,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { · 37 unmodified lines
596596 },
597597 };
598598
599−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
599+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
600600 .encp = {
601601 .dvi_settings = 0xd,
602602 .video_mode = 0x4040,
@@ -644,7 +644,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { · 41 unmodified lines
644644 },
645645 };
646646
647−union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
647+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
648648 .encp = {
649649 .dvi_settings = 0x1,
650650 .video_mode = 0x4040,
@@ -688,7 +688,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { · 37 unmodified lines
688688 },
689689 };
690690
691−union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
691+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
692692 .encp = {
693693 .dvi_settings = 0x1,
694694 .video_mode = 0x4040,
@@ -730,7 +730,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = { · 35 unmodified lines
730730 },
731731 };
732732
733−union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
733+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
734734 .encp = {
735735 .dvi_settings = 0x1,
736736 .video_mode = 0x4040,
@@ -772,7 +772,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = { · 35 unmodified lines
772772 },
773773 };
774774
775−union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
775+static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
776776 .encp = {
777777 .dvi_settings = 0x1,
778778 .video_mode = 0x4040,
@@ -814,7 +814,7 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = { · 35 unmodified lines
814814 },
815815 };
816816
817−struct meson_hdmi_venc_vic_mode {
817+static struct meson_hdmi_venc_vic_mode {
818818 unsigned int vic;
819819 union meson_hdmi_venc_mode *mode;
820820 } meson_hdmi_venc_vic_modes[] = {
drivers/gpu/drm/msm/msm_drv.c+1−1
@@ -455,7 +455,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) · 454 unmodified lines
455455 goto err_deinit_vram;
456456
457457 /* the fw fb could be anywhere in memory */
458− ret = drm_aperture_remove_framebuffers(false, drv);
458+ ret = drm_aperture_remove_framebuffers(drv);
459459 if (ret)
460460 goto err_msm_uninit;
461461
drivers/gpu/drm/msm/msm_fbdev.c+3−3
@@ -121,9 +121,9 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, · 120 unmodified lines
121121
122122 drm_fb_helper_fill_info(fbi, helper, sizes);
123123
124− fbi->screen_base = msm_gem_get_vaddr(bo);
125− if (IS_ERR(fbi->screen_base)) {
126− ret = PTR_ERR(fbi->screen_base);
124+ fbi->screen_buffer = msm_gem_get_vaddr(bo);
125+ if (IS_ERR(fbi->screen_buffer)) {
126+ ret = PTR_ERR(fbi->screen_buffer);
127127 goto fail;
128128 }
129129 fbi->screen_size = bo->size;
drivers/gpu/drm/nouveau/dispnv50/disp.c+1−0
@@ -64,6 +64,7 @@ · 63 unmodified lines
6464 #include "nouveau_connector.h"
6565 #include "nouveau_encoder.h"
6666 #include "nouveau_fence.h"
67+#include "nv50_display.h"
6768
6869 #include <subdev/bios/dp.h>
6970
drivers/gpu/drm/nouveau/include/nvif/if0012.h+3−1
@@ -2,6 +2,8 @@ · 1 unmodified line
22 #ifndef __NVIF_IF0012_H__
33 #define __NVIF_IF0012_H__
44
5+#include <drm/display/drm_dp.h>
6+
57 union nvif_outp_args {
68 struct nvif_outp_v0 {
79 __u8 version;
@@ -63,7 +65,7 @@ union nvif_outp_acquire_args { · 55 unmodified lines
6365 __u8 hda;
6466 __u8 mst;
6567 __u8 pad04[4];
66− __u8 dpcd[16];
68+ __u8 dpcd[DP_RECEIVER_CAP_SIZE];
6769 } dp;
6870 };
6971 } v0;
drivers/gpu/drm/nouveau/nouveau_debugfs.c+10−9
@@ -73,13 +73,14 @@ nouveau_debugfs_pstate_get(struct seq_file *m, void *data) · 72 unmodified lines
7373 {
7474 struct drm_device *drm = m->private;
7575 struct nouveau_debugfs *debugfs = nouveau_debugfs(drm);
76− struct nvif_object *ctrl = &debugfs->ctrl;
76+ struct nvif_object *ctrl;
7777 struct nvif_control_pstate_info_v0 info = {};
7878 int ret, i;
7979
8080 if (!debugfs)
8181 return -ENODEV;
8282
83+ ctrl = &debugfs->ctrl;
8384 ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_INFO, &info, sizeof(info));
8485 if (ret)
8586 return ret;
@@ -119,19 +120,19 @@ nouveau_debugfs_pstate_get(struct seq_file *m, void *data) · 33 unmodified lines
119120
120121 if (state >= 0) {
121122 if (info.ustate_ac == state)
122− seq_printf(m, " AC");
123+ seq_puts(m, " AC");
123124 if (info.ustate_dc == state)
124− seq_printf(m, " DC");
125+ seq_puts(m, " DC");
125126 if (info.pstate == state)
126− seq_printf(m, " *");
127+ seq_puts(m, " *");
127128 } else {
128129 if (info.ustate_ac < -1)
129− seq_printf(m, " AC");
130+ seq_puts(m, " AC");
130131 if (info.ustate_dc < -1)
131− seq_printf(m, " DC");
132+ seq_puts(m, " DC");
132133 }
133134
134− seq_printf(m, "\n");
135+ seq_putc(m, '\n');
135136 }
136137
137138 return 0;
@@ -144,7 +145,6 @@ nouveau_debugfs_pstate_set(struct file *file, const char __user *ubuf, · 6 unmodified lines
144145 struct seq_file *m = file->private_data;
145146 struct drm_device *drm = m->private;
146147 struct nouveau_debugfs *debugfs = nouveau_debugfs(drm);
147− struct nvif_object *ctrl = &debugfs->ctrl;
148148 struct nvif_control_pstate_user_v0 args = { .pwrsrc = -EINVAL };
149149 char buf[32] = {}, *tmp, *cur = buf;
150150 long value, ret;
@@ -188,7 +188,8 @@ nouveau_debugfs_pstate_set(struct file *file, const char __user *ubuf, · 37 unmodified lines
188188 return ret;
189189 }
190190
191− ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_USER, &args, sizeof(args));
191+ ret = nvif_mthd(&debugfs->ctrl, NVIF_CONTROL_PSTATE_USER,
192+ &args, sizeof(args));
192193 pm_runtime_put_autosuspend(drm->dev);
193194 if (ret < 0)
194195 return ret;
drivers/gpu/drm/nouveau/nouveau_hwmon.c+1−1
@@ -211,7 +211,7 @@ static const struct attribute_group temp1_auto_point_sensor_group = { · 210 unmodified lines
211211
212212 #define N_ATTR_GROUPS 3
213213
214−static const struct hwmon_channel_info *nouveau_info[] = {
214+static const struct hwmon_channel_info * const nouveau_info[] = {
215215 HWMON_CHANNEL_INFO(chip,
216216 HWMON_C_UPDATE_INTERVAL),
217217 HWMON_CHANNEL_INFO(temp,
drivers/gpu/drm/nouveau/nv50_display.h+1−3
@@ -31,7 +31,5 @@ · 30 unmodified lines
3131 #include "nouveau_reg.h"
3232
3333 int nv50_display_create(struct drm_device *);
34−void nv50_display_destroy(struct drm_device *);
35−int nv50_display_init(struct drm_device *);
36−void nv50_display_fini(struct drm_device *);
34+
3735 #endif /* __NV50_DISPLAY_H__ */
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h+2−1
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 #define __NVKM_DISP_OUTP_H__
44 #include "priv.h"
55
6+#include <drm/display/drm_dp.h>
67 #include <subdev/bios.h>
78 #include <subdev/bios/dcb.h>
89 #include <subdev/bios/dp.h>
@@ -42,7 +43,7 @@ struct nvkm_outp { · 33 unmodified lines
4243 bool aux_pwr_pu;
4344 u8 lttpr[6];
4445 u8 lttprs;
45− u8 dpcd[16];
46+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
4647
4748 struct {
4849 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */
drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c+1−1
@@ -146,7 +146,7 @@ nvkm_uoutp_mthd_release(struct nvkm_outp *outp, void *argv, u32 argc) · 145 unmodified lines
146146 }
147147
148148 static int
149−nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[16],
149+nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE],
150150 u8 link_nr, u8 link_bw, bool hda, bool mst)
151151 {
152152 int ret;
drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c+1−2
@@ -59,7 +59,6 @@ int · 58 unmodified lines
5959 nvbios_power_budget_header(struct nvkm_bios *bios,
6060 struct nvbios_power_budget *budget)
6161 {
62− struct nvkm_subdev *subdev = &bios->subdev;
6362 u8 ver, hdr, cnt, len, cap_entry;
6463 u32 header;
6564
@@ -82,7 +81,7 @@ nvbios_power_budget_header(struct nvkm_bios *bios, · 16 unmodified lines
8281 }
8382
8483 if (cap_entry >= cnt && cap_entry != 0xff) {
85− nvkm_warn(subdev,
84+ nvkm_warn(&bios->subdev,
8685 "invalid cap_entry in power budget table found\n");
8786 budget->cap_entry = 0xff;
8887 return -EINVAL;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c+1−1
@@ -417,7 +417,6 @@ nvkm_pstate_new(struct nvkm_clk *clk, int idx) · 416 unmodified lines
417417 return 0;
418418
419419 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
420− cstate = &pstate->base;
421420 if (!pstate)
422421 return -ENOMEM;
423422
@@ -427,6 +426,7 @@ nvkm_pstate_new(struct nvkm_clk *clk, int idx) · 3 unmodified lines
427426 pstate->fanspeed = perfE.fanspeed;
428427 pstate->pcie_speed = perfE.pcie_speed;
429428 pstate->pcie_width = perfE.pcie_width;
429+ cstate = &pstate->base;
430430 cstate->voltage = perfE.voltage;
431431 cstate->domain[nv_clk_src_core] = perfE.core;
432432 cstate->domain[nv_clk_src_shader] = perfE.shader;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c+1−1
@@ -45,7 +45,7 @@ ga102_gsp_nofw(struct nvkm_gsp *gsp, int ver, const struct nvkm_gsp_fwif *fwif) · 44 unmodified lines
4545 return 0;
4646 }
4747
48−struct nvkm_gsp_fwif
48+static struct nvkm_gsp_fwif
4949 ga102_gsps[] = {
5050 { -1, ga102_gsp_nofw, &ga102_gsp },
5151 {}
drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c+3−4
@@ -114,18 +114,17 @@ nvkm_pcie_init(struct nvkm_pci *pci) · 113 unmodified lines
114114 int
115115 nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
116116 {
117− struct nvkm_subdev *subdev = &pci->subdev;
117+ struct nvkm_subdev *subdev;
118118 enum nvkm_pcie_speed cur_speed, max_speed;
119− struct pci_bus *pbus;
120119 int ret;
121120
122121 if (!pci || !pci_is_pcie(pci->pdev))
123122 return 0;
124− pbus = pci->pdev->bus;
125123
126124 if (!pci->func->pcie.set_link)
127125 return -ENOSYS;
128126
127+ subdev = &pci->subdev;
129128 nvkm_trace(subdev, "requested %s\n", nvkm_pcie_speeds[speed]);
130129
131130 if (pci->func->pcie.version(pci) < 2) {
@@ -134,7 +133,7 @@ nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) · 2 unmodified lines
134133 }
135134
136135 cur_speed = pci->func->pcie.cur_speed(pci);
137− max_speed = min(nvkm_pcie_speed(pbus->max_bus_speed),
136+ max_speed = min(nvkm_pcie_speed(pci->pdev->bus->max_bus_speed),
138137 pci->func->pcie.max_speed(pci));
139138
140139 nvkm_trace(subdev, "current speed: %s\n", nvkm_pcie_speeds[cur_speed]);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c+1−1
@@ -98,10 +98,10 @@ nvkm_fanpwm_create(struct nvkm_therm *therm, struct dcb_gpio_func *func) · 97 unmodified lines
9898 return -ENODEV;
9999
100100 fan = kzalloc(sizeof(*fan), GFP_KERNEL);
101− therm->fan = &fan->base;
102101 if (!fan)
103102 return -ENOMEM;
104103
104+ therm->fan = &fan->base;
105105 fan->base.type = "PWM";
106106 fan->base.get = nvkm_fanpwm_get;
107107 fan->base.set = nvkm_fanpwm_set;
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c+1−1
@@ -100,10 +100,10 @@ nvkm_fantog_create(struct nvkm_therm *therm, struct dcb_gpio_func *func) · 99 unmodified lines
100100 }
101101
102102 fan = kzalloc(sizeof(*fan), GFP_KERNEL);
103− therm->fan = &fan->base;
104103 if (!fan)
105104 return -ENOMEM;
106105
106+ therm->fan = &fan->base;
107107 fan->base.type = "toggle";
108108 fan->base.get = nvkm_fantog_get;
109109 fan->base.set = nvkm_fantog_set;
drivers/gpu/drm/panel/Kconfig+7−0
@@ -553,6 +553,13 @@ config DRM_PANEL_SAMSUNG_S6D27A1 · 552 unmodified lines
553553 This panel can be found in Samsung Galaxy Ace 2
554554 GT-I8160 mobile phone.
555555
556+config DRM_PANEL_SAMSUNG_S6D7AA0
557+ tristate "Samsung S6D7AA0 MIPI-DSI video mode panel controller"
558+ depends on OF
559+ depends on BACKLIGHT_CLASS_DEVICE
560+ select DRM_MIPI_DSI
561+ select VIDEOMODE_HELPERS
562+
556563 config DRM_PANEL_SAMSUNG_S6E3HA2
557564 tristate "Samsung S6E3HA2 DSI video mode panel"
558565 depends on OF
drivers/gpu/drm/panel/Makefile+1−0
@@ -54,6 +54,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o · 53 unmodified lines
5454 obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
5555 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o
5656 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o
57+obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o
5758 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
5859 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
5960 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c+241−163
@@ -36,6 +36,7 @@ struct panel_desc { · 35 unmodified lines
3636 const struct panel_init_cmd *init_cmds;
3737 unsigned int lanes;
3838 bool discharge_on_disable;
39+ bool lp11_before_reset;
3940 };
4041
4142 struct boe_panel {
@@ -451,11 +452,14 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 409 unmodified lines
451452 _INIT_DCS_CMD(0xFF, 0x20),
452453 _INIT_DCS_CMD(0xFB, 0x01),
453454 _INIT_DCS_CMD(0x05, 0xD1),
454− _INIT_DCS_CMD(0x0D, 0x63),
455− _INIT_DCS_CMD(0x07, 0x8C),
455+ _INIT_DCS_CMD(0x06, 0xC0),
456+ _INIT_DCS_CMD(0x07, 0x87),
456457 _INIT_DCS_CMD(0x08, 0x4B),
458+
459+ _INIT_DCS_CMD(0x0D, 0x63),
457460 _INIT_DCS_CMD(0x0E, 0x91),
458461 _INIT_DCS_CMD(0x0F, 0x69),
462+ _INIT_DCS_CMD(0x94, 0x00),
459463 _INIT_DCS_CMD(0x95, 0xF5),
460464 _INIT_DCS_CMD(0x96, 0xF5),
461465 _INIT_DCS_CMD(0x9D, 0x00),
@@ -463,98 +467,96 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 1 unmodified line
463467 _INIT_DCS_CMD(0x69, 0x98),
464468 _INIT_DCS_CMD(0x75, 0xA2),
465469 _INIT_DCS_CMD(0x77, 0xB3),
470+
471+ _INIT_DCS_CMD(0x58, 0x43),
466472 _INIT_DCS_CMD(0xFF, 0x24),
467473 _INIT_DCS_CMD(0xFB, 0x01),
468474 _INIT_DCS_CMD(0x91, 0x44),
469− _INIT_DCS_CMD(0x92, 0x7A),
470− _INIT_DCS_CMD(0x93, 0x1A),
471− _INIT_DCS_CMD(0x94, 0x40),
472− _INIT_DCS_CMD(0x9A, 0x08),
475+ _INIT_DCS_CMD(0x92, 0x4C),
476+ _INIT_DCS_CMD(0x94, 0x86),
473477 _INIT_DCS_CMD(0x60, 0x96),
474478 _INIT_DCS_CMD(0x61, 0xD0),
475479 _INIT_DCS_CMD(0x63, 0x70),
476− _INIT_DCS_CMD(0xC2, 0xCF),
477− _INIT_DCS_CMD(0x9B, 0x0F),
478− _INIT_DCS_CMD(0x9A, 0x08),
480+ _INIT_DCS_CMD(0xC2, 0xCA),
481+
479482 _INIT_DCS_CMD(0x00, 0x03),
480483 _INIT_DCS_CMD(0x01, 0x03),
481484 _INIT_DCS_CMD(0x02, 0x03),
482− _INIT_DCS_CMD(0x03, 0x03),
483− _INIT_DCS_CMD(0x04, 0x03),
484− _INIT_DCS_CMD(0x05, 0x03),
485− _INIT_DCS_CMD(0x06, 0x22),
486− _INIT_DCS_CMD(0x07, 0x06),
487− _INIT_DCS_CMD(0x08, 0x00),
488− _INIT_DCS_CMD(0x09, 0x1D),
489− _INIT_DCS_CMD(0x0A, 0x1C),
490− _INIT_DCS_CMD(0x0B, 0x13),
491− _INIT_DCS_CMD(0x0C, 0x12),
492− _INIT_DCS_CMD(0x0D, 0x11),
493− _INIT_DCS_CMD(0x0E, 0x10),
494− _INIT_DCS_CMD(0x0F, 0x0F),
495− _INIT_DCS_CMD(0x10, 0x0E),
496− _INIT_DCS_CMD(0x11, 0x0D),
497− _INIT_DCS_CMD(0x12, 0x0C),
485+ _INIT_DCS_CMD(0x03, 0x29),
486+ _INIT_DCS_CMD(0x04, 0x22),
487+ _INIT_DCS_CMD(0x05, 0x22),
488+ _INIT_DCS_CMD(0x06, 0x0B),
489+ _INIT_DCS_CMD(0x07, 0x1D),
490+ _INIT_DCS_CMD(0x08, 0x1C),
491+ _INIT_DCS_CMD(0x09, 0x05),
492+ _INIT_DCS_CMD(0x0A, 0x08),
493+ _INIT_DCS_CMD(0x0B, 0x09),
494+ _INIT_DCS_CMD(0x0C, 0x0A),
495+ _INIT_DCS_CMD(0x0D, 0x0C),
496+ _INIT_DCS_CMD(0x0E, 0x0D),
497+ _INIT_DCS_CMD(0x0F, 0x0E),
498+ _INIT_DCS_CMD(0x10, 0x0F),
499+ _INIT_DCS_CMD(0x11, 0x10),
500+ _INIT_DCS_CMD(0x12, 0x11),
498501 _INIT_DCS_CMD(0x13, 0x04),
499− _INIT_DCS_CMD(0x14, 0x03),
502+ _INIT_DCS_CMD(0x14, 0x00),
500503 _INIT_DCS_CMD(0x15, 0x03),
501504 _INIT_DCS_CMD(0x16, 0x03),
502505 _INIT_DCS_CMD(0x17, 0x03),
503506 _INIT_DCS_CMD(0x18, 0x03),
504− _INIT_DCS_CMD(0x19, 0x03),
505− _INIT_DCS_CMD(0x1A, 0x03),
506− _INIT_DCS_CMD(0x1B, 0x03),
507− _INIT_DCS_CMD(0x1C, 0x22),
508− _INIT_DCS_CMD(0x1D, 0x06),
509− _INIT_DCS_CMD(0x1E, 0x00),
510− _INIT_DCS_CMD(0x1F, 0x1D),
511− _INIT_DCS_CMD(0x20, 0x1C),
512− _INIT_DCS_CMD(0x21, 0x13),
513− _INIT_DCS_CMD(0x22, 0x12),
514− _INIT_DCS_CMD(0x23, 0x11),
515− _INIT_DCS_CMD(0x24, 0x10),
516− _INIT_DCS_CMD(0x25, 0x0F),
517− _INIT_DCS_CMD(0x26, 0x0E),
518− _INIT_DCS_CMD(0x27, 0x0D),
519− _INIT_DCS_CMD(0x28, 0x0C),
507+ _INIT_DCS_CMD(0x19, 0x29),
508+ _INIT_DCS_CMD(0x1A, 0x22),
509+ _INIT_DCS_CMD(0x1B, 0x22),
510+ _INIT_DCS_CMD(0x1C, 0x0B),
511+ _INIT_DCS_CMD(0x1D, 0x1D),
512+ _INIT_DCS_CMD(0x1E, 0x1C),
513+ _INIT_DCS_CMD(0x1F, 0x05),
514+ _INIT_DCS_CMD(0x20, 0x08),
515+ _INIT_DCS_CMD(0x21, 0x09),
516+ _INIT_DCS_CMD(0x22, 0x0A),
517+ _INIT_DCS_CMD(0x23, 0x0C),
518+ _INIT_DCS_CMD(0x24, 0x0D),
519+ _INIT_DCS_CMD(0x25, 0x0E),
520+ _INIT_DCS_CMD(0x26, 0x0F),
521+ _INIT_DCS_CMD(0x27, 0x10),
522+ _INIT_DCS_CMD(0x28, 0x11),
520523 _INIT_DCS_CMD(0x29, 0x04),
521− _INIT_DCS_CMD(0x2A, 0x03),
524+ _INIT_DCS_CMD(0x2A, 0x00),
522525 _INIT_DCS_CMD(0x2B, 0x03),
523526
524− _INIT_DCS_CMD(0x2F, 0x05),
525− _INIT_DCS_CMD(0x30, 0x32),
526− _INIT_DCS_CMD(0x31, 0x43),
527− _INIT_DCS_CMD(0x33, 0x05),
528− _INIT_DCS_CMD(0x34, 0x32),
529− _INIT_DCS_CMD(0x35, 0x43),
530− _INIT_DCS_CMD(0x37, 0x44),
531− _INIT_DCS_CMD(0x38, 0x40),
527+ _INIT_DCS_CMD(0x2F, 0x0A),
528+ _INIT_DCS_CMD(0x30, 0x35),
529+ _INIT_DCS_CMD(0x37, 0xA7),
532530 _INIT_DCS_CMD(0x39, 0x00),
533− _INIT_DCS_CMD(0x3A, 0x18),
534− _INIT_DCS_CMD(0x3B, 0x00),
535− _INIT_DCS_CMD(0x3D, 0x93),
536− _INIT_DCS_CMD(0xAB, 0x44),
537− _INIT_DCS_CMD(0xAC, 0x40),
531+ _INIT_DCS_CMD(0x3A, 0x46),
532+ _INIT_DCS_CMD(0x3B, 0x32),
533+ _INIT_DCS_CMD(0x3D, 0x12),
534+
535+ _INIT_DCS_CMD(0x3F, 0x33),
536+ _INIT_DCS_CMD(0x40, 0x31),
537+ _INIT_DCS_CMD(0x41, 0x40),
538+ _INIT_DCS_CMD(0x42, 0x42),
539+ _INIT_DCS_CMD(0x47, 0x77),
540+ _INIT_DCS_CMD(0x48, 0x77),
541+ _INIT_DCS_CMD(0x4A, 0x45),
542+ _INIT_DCS_CMD(0x4B, 0x45),
543+ _INIT_DCS_CMD(0x4C, 0x14),
538544
539545 _INIT_DCS_CMD(0x4D, 0x21),
540546 _INIT_DCS_CMD(0x4E, 0x43),
541547 _INIT_DCS_CMD(0x4F, 0x65),
542− _INIT_DCS_CMD(0x50, 0x87),
543− _INIT_DCS_CMD(0x51, 0x78),
544− _INIT_DCS_CMD(0x52, 0x56),
545− _INIT_DCS_CMD(0x53, 0x34),
546− _INIT_DCS_CMD(0x54, 0x21),
547− _INIT_DCS_CMD(0x55, 0x83),
548− _INIT_DCS_CMD(0x56, 0x08),
548+ _INIT_DCS_CMD(0x55, 0x06),
549+ _INIT_DCS_CMD(0x56, 0x06),
549550 _INIT_DCS_CMD(0x58, 0x21),
550− _INIT_DCS_CMD(0x59, 0x40),
551− _INIT_DCS_CMD(0x5A, 0x00),
552− _INIT_DCS_CMD(0x5B, 0x2C),
553− _INIT_DCS_CMD(0x5E, 0x00, 0x10),
551+ _INIT_DCS_CMD(0x59, 0x70),
552+ _INIT_DCS_CMD(0x5A, 0x46),
553+ _INIT_DCS_CMD(0x5B, 0x32),
554+ _INIT_DCS_CMD(0x5C, 0x88),
555+ _INIT_DCS_CMD(0x5E, 0x00, 0x00),
554556 _INIT_DCS_CMD(0x5F, 0x00),
555557
556− _INIT_DCS_CMD(0x7A, 0x00),
557− _INIT_DCS_CMD(0x7B, 0x00),
558+ _INIT_DCS_CMD(0x7A, 0xFF),
559+ _INIT_DCS_CMD(0x7B, 0xFF),
558560 _INIT_DCS_CMD(0x7C, 0x00),
559561 _INIT_DCS_CMD(0x7D, 0x00),
560562 _INIT_DCS_CMD(0x7E, 0x20),
@@ -564,152 +566,183 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
564566 _INIT_DCS_CMD(0x82, 0x08),
565567 _INIT_DCS_CMD(0x97, 0x02),
566568 _INIT_DCS_CMD(0xC5, 0x10),
569+
570+ _INIT_DCS_CMD(0xD7, 0x55),
571+ _INIT_DCS_CMD(0xD8, 0x55),
572+ _INIT_DCS_CMD(0xD9, 0x23),
567573 _INIT_DCS_CMD(0xDA, 0x05),
568574 _INIT_DCS_CMD(0xDB, 0x01),
569− _INIT_DCS_CMD(0xDC, 0x7A),
575+ _INIT_DCS_CMD(0xDC, 0x65),
570576 _INIT_DCS_CMD(0xDD, 0x55),
571577 _INIT_DCS_CMD(0xDE, 0x27),
572578 _INIT_DCS_CMD(0xDF, 0x01),
573− _INIT_DCS_CMD(0xE0, 0x7A),
579+ _INIT_DCS_CMD(0xE0, 0x65),
574580 _INIT_DCS_CMD(0xE1, 0x01),
575− _INIT_DCS_CMD(0xE2, 0x7A),
581+ _INIT_DCS_CMD(0xE2, 0x65),
576582 _INIT_DCS_CMD(0xE3, 0x01),
577− _INIT_DCS_CMD(0xE4, 0x7A),
583+ _INIT_DCS_CMD(0xE4, 0x65),
578584 _INIT_DCS_CMD(0xE5, 0x01),
579− _INIT_DCS_CMD(0xE6, 0x7A),
585+ _INIT_DCS_CMD(0xE6, 0x65),
580586 _INIT_DCS_CMD(0xE7, 0x00),
581587 _INIT_DCS_CMD(0xE8, 0x00),
582588 _INIT_DCS_CMD(0xE9, 0x01),
583− _INIT_DCS_CMD(0xEA, 0x7A),
589+ _INIT_DCS_CMD(0xEA, 0x65),
584590 _INIT_DCS_CMD(0xEB, 0x01),
585− _INIT_DCS_CMD(0xEE, 0x7A),
591+ _INIT_DCS_CMD(0xEE, 0x65),
586592 _INIT_DCS_CMD(0xEF, 0x01),
587− _INIT_DCS_CMD(0xF0, 0x7A),
588−
593+ _INIT_DCS_CMD(0xF0, 0x65),
589594 _INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00),
595+
590596 _INIT_DCS_CMD(0xFF, 0x25),
591− _INIT_DCS_CMD(0xFB, 0x01),
592597
598+ _INIT_DCS_CMD(0xFB, 0x01),
593599 _INIT_DCS_CMD(0x05, 0x00),
594−
595− _INIT_DCS_CMD(0x13, 0x02),
596− _INIT_DCS_CMD(0x14, 0xDF),
597600 _INIT_DCS_CMD(0xF1, 0x10),
601+
598602 _INIT_DCS_CMD(0x1E, 0x00),
599− _INIT_DCS_CMD(0x1F, 0x00),
600− _INIT_DCS_CMD(0x20, 0x2C),
603+ _INIT_DCS_CMD(0x1F, 0x46),
604+ _INIT_DCS_CMD(0x20, 0x32),
605+
601606 _INIT_DCS_CMD(0x25, 0x00),
602− _INIT_DCS_CMD(0x26, 0x00),
603− _INIT_DCS_CMD(0x27, 0x2C),
607+ _INIT_DCS_CMD(0x26, 0x46),
608+ _INIT_DCS_CMD(0x27, 0x32),
609+
604610 _INIT_DCS_CMD(0x3F, 0x80),
605611 _INIT_DCS_CMD(0x40, 0x00),
606612 _INIT_DCS_CMD(0x43, 0x00),
607613
608− _INIT_DCS_CMD(0x44, 0x18),
609− _INIT_DCS_CMD(0x45, 0x00),
614+ _INIT_DCS_CMD(0x44, 0x46),
615+ _INIT_DCS_CMD(0x45, 0x46),
616+
617+ _INIT_DCS_CMD(0x48, 0x46),
618+ _INIT_DCS_CMD(0x49, 0x32),
610619
611− _INIT_DCS_CMD(0x48, 0x00),
612− _INIT_DCS_CMD(0x49, 0x2C),
613620 _INIT_DCS_CMD(0x5B, 0x80),
621+
614622 _INIT_DCS_CMD(0x5C, 0x00),
615− _INIT_DCS_CMD(0x5D, 0x00),
616− _INIT_DCS_CMD(0x5E, 0x00),
617− _INIT_DCS_CMD(0x61, 0x00),
618− _INIT_DCS_CMD(0x62, 0x2C),
619− _INIT_DCS_CMD(0x68, 0x10),
623+ _INIT_DCS_CMD(0x5D, 0x46),
624+ _INIT_DCS_CMD(0x5E, 0x32),
625+
626+ _INIT_DCS_CMD(0x5F, 0x46),
627+ _INIT_DCS_CMD(0x60, 0x32),
628+
629+ _INIT_DCS_CMD(0x61, 0x46),
630+ _INIT_DCS_CMD(0x62, 0x32),
631+ _INIT_DCS_CMD(0x68, 0x0C),
632+
633+ _INIT_DCS_CMD(0x6C, 0x0D),
634+ _INIT_DCS_CMD(0x6E, 0x0D),
635+ _INIT_DCS_CMD(0x78, 0x00),
636+ _INIT_DCS_CMD(0x79, 0xC5),
637+ _INIT_DCS_CMD(0x7A, 0x0C),
638+ _INIT_DCS_CMD(0x7B, 0xB0),
639+
620640 _INIT_DCS_CMD(0xFF, 0x26),
621641 _INIT_DCS_CMD(0xFB, 0x01),
622642
623643 _INIT_DCS_CMD(0x00, 0xA1),
624644 _INIT_DCS_CMD(0x02, 0x31),
625− _INIT_DCS_CMD(0x0A, 0xF2),
626− _INIT_DCS_CMD(0x04, 0x28),
645+ _INIT_DCS_CMD(0x0A, 0xF4),
646+ _INIT_DCS_CMD(0x04, 0x50),
627647 _INIT_DCS_CMD(0x06, 0x30),
628648 _INIT_DCS_CMD(0x0C, 0x16),
629649 _INIT_DCS_CMD(0x0D, 0x0D),
630650 _INIT_DCS_CMD(0x0F, 0x00),
631651 _INIT_DCS_CMD(0x11, 0x00),
632652 _INIT_DCS_CMD(0x12, 0x50),
633− _INIT_DCS_CMD(0x13, 0x56),
634− _INIT_DCS_CMD(0x14, 0x57),
653+ _INIT_DCS_CMD(0x13, 0x40),
654+ _INIT_DCS_CMD(0x14, 0x58),
635655 _INIT_DCS_CMD(0x15, 0x00),
636656 _INIT_DCS_CMD(0x16, 0x10),
637657 _INIT_DCS_CMD(0x17, 0xA0),
638658 _INIT_DCS_CMD(0x18, 0x86),
639659 _INIT_DCS_CMD(0x22, 0x00),
640660 _INIT_DCS_CMD(0x23, 0x00),
641− _INIT_DCS_CMD(0x19, 0x0D),
642− _INIT_DCS_CMD(0x1A, 0x7F),
643− _INIT_DCS_CMD(0x1B, 0x0C),
644− _INIT_DCS_CMD(0x1C, 0xBF),
645− _INIT_DCS_CMD(0x2A, 0x0D),
646− _INIT_DCS_CMD(0x2B, 0x7F),
647− _INIT_DCS_CMD(0x20, 0x00),
661+
662+ _INIT_DCS_CMD(0x19, 0x0E),
663+ _INIT_DCS_CMD(0x1A, 0x31),
664+ _INIT_DCS_CMD(0x1B, 0x0D),
665+ _INIT_DCS_CMD(0x1C, 0x29),
666+ _INIT_DCS_CMD(0x2A, 0x0E),
667+ _INIT_DCS_CMD(0x2B, 0x31),
648668
649669 _INIT_DCS_CMD(0x1D, 0x00),
650− _INIT_DCS_CMD(0x1E, 0x78),
651− _INIT_DCS_CMD(0x1F, 0x78),
670+ _INIT_DCS_CMD(0x1E, 0x62),
671+ _INIT_DCS_CMD(0x1F, 0x62),
652672
653− _INIT_DCS_CMD(0x2F, 0x03),
654− _INIT_DCS_CMD(0x30, 0x78),
655− _INIT_DCS_CMD(0x33, 0x78),
656− _INIT_DCS_CMD(0x34, 0x66),
657− _INIT_DCS_CMD(0x35, 0x11),
673+ _INIT_DCS_CMD(0x2F, 0x06),
674+ _INIT_DCS_CMD(0x30, 0x62),
675+ _INIT_DCS_CMD(0x31, 0x06),
676+ _INIT_DCS_CMD(0x32, 0x7F),
677+ _INIT_DCS_CMD(0x33, 0x11),
678+ _INIT_DCS_CMD(0x34, 0x89),
679+ _INIT_DCS_CMD(0x35, 0x67),
658680
659− _INIT_DCS_CMD(0x39, 0x10),
660− _INIT_DCS_CMD(0x3A, 0x78),
681+ _INIT_DCS_CMD(0x39, 0x0B),
682+ _INIT_DCS_CMD(0x3A, 0x62),
661683 _INIT_DCS_CMD(0x3B, 0x06),
662684
663685 _INIT_DCS_CMD(0xC8, 0x04),
664− _INIT_DCS_CMD(0xC9, 0x84),
686+ _INIT_DCS_CMD(0xC9, 0x89),
665687 _INIT_DCS_CMD(0xCA, 0x4E),
666688 _INIT_DCS_CMD(0xCB, 0x00),
689+ _INIT_DCS_CMD(0xA9, 0x3F),
690+ _INIT_DCS_CMD(0xAA, 0x3E),
691+ _INIT_DCS_CMD(0xAB, 0x3D),
692+ _INIT_DCS_CMD(0xAC, 0x3C),
693+ _INIT_DCS_CMD(0xAD, 0x3B),
694+ _INIT_DCS_CMD(0xAE, 0x3A),
695+ _INIT_DCS_CMD(0xAF, 0x39),
696+ _INIT_DCS_CMD(0xB0, 0x38),
667697
668− _INIT_DCS_CMD(0xA9, 0x50),
669− _INIT_DCS_CMD(0xAA, 0x4F),
670− _INIT_DCS_CMD(0xAB, 0x4D),
671− _INIT_DCS_CMD(0xAC, 0x4A),
672− _INIT_DCS_CMD(0xAD, 0x48),
673− _INIT_DCS_CMD(0xAE, 0x46),
674698 _INIT_DCS_CMD(0xFF, 0x27),
675699 _INIT_DCS_CMD(0xFB, 0x01),
700+
701+ _INIT_DCS_CMD(0xD0, 0x11),
702+ _INIT_DCS_CMD(0xD1, 0x54),
703+ _INIT_DCS_CMD(0xDE, 0x43),
704+ _INIT_DCS_CMD(0xDF, 0x02),
705+
676706 _INIT_DCS_CMD(0xC0, 0x18),
677707 _INIT_DCS_CMD(0xC1, 0x00),
678708 _INIT_DCS_CMD(0xC2, 0x00),
709+ _INIT_DCS_CMD(0x00, 0x00),
710+ _INIT_DCS_CMD(0xC3, 0x00),
679711 _INIT_DCS_CMD(0x56, 0x06),
712+
680713 _INIT_DCS_CMD(0x58, 0x80),
681− _INIT_DCS_CMD(0x59, 0x75),
714+ _INIT_DCS_CMD(0x59, 0x78),
682715 _INIT_DCS_CMD(0x5A, 0x00),
683− _INIT_DCS_CMD(0x5B, 0x02),
716+ _INIT_DCS_CMD(0x5B, 0x18),
684717 _INIT_DCS_CMD(0x5C, 0x00),
685− _INIT_DCS_CMD(0x5D, 0x00),
718+ _INIT_DCS_CMD(0x5D, 0x01),
686719 _INIT_DCS_CMD(0x5E, 0x20),
687720 _INIT_DCS_CMD(0x5F, 0x10),
688721 _INIT_DCS_CMD(0x60, 0x00),
689− _INIT_DCS_CMD(0x61, 0x2E),
722+ _INIT_DCS_CMD(0x61, 0x1C),
690723 _INIT_DCS_CMD(0x62, 0x00),
691724 _INIT_DCS_CMD(0x63, 0x01),
692− _INIT_DCS_CMD(0x64, 0x43),
693− _INIT_DCS_CMD(0x65, 0x2D),
725+ _INIT_DCS_CMD(0x64, 0x44),
726+ _INIT_DCS_CMD(0x65, 0x1B),
694727 _INIT_DCS_CMD(0x66, 0x00),
695728 _INIT_DCS_CMD(0x67, 0x01),
696− _INIT_DCS_CMD(0x68, 0x43),
729+ _INIT_DCS_CMD(0x68, 0x44),
730+
697731 _INIT_DCS_CMD(0x98, 0x01),
698732 _INIT_DCS_CMD(0xB4, 0x03),
699− _INIT_DCS_CMD(0x9B, 0xBD),
700− _INIT_DCS_CMD(0xA0, 0x90),
701− _INIT_DCS_CMD(0xAB, 0x1B),
702− _INIT_DCS_CMD(0xBC, 0x0C),
733+ _INIT_DCS_CMD(0x9B, 0xBE),
734+
735+ _INIT_DCS_CMD(0xAB, 0x14),
736+ _INIT_DCS_CMD(0xBC, 0x08),
703737 _INIT_DCS_CMD(0xBD, 0x28),
704738
705739 _INIT_DCS_CMD(0xFF, 0x2A),
706740 _INIT_DCS_CMD(0xFB, 0x01),
707−
708741 _INIT_DCS_CMD(0x22, 0x2F),
709742 _INIT_DCS_CMD(0x23, 0x08),
710743
711744 _INIT_DCS_CMD(0x24, 0x00),
712− _INIT_DCS_CMD(0x25, 0x65),
745+ _INIT_DCS_CMD(0x25, 0x62),
713746 _INIT_DCS_CMD(0x26, 0xF8),
714747 _INIT_DCS_CMD(0x27, 0x00),
715748 _INIT_DCS_CMD(0x28, 0x1A),
@@ -719,18 +752,29 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
719752 _INIT_DCS_CMD(0x2D, 0x1A),
720753
721754 _INIT_DCS_CMD(0x64, 0x96),
722− _INIT_DCS_CMD(0x65, 0x00),
755+ _INIT_DCS_CMD(0x65, 0x10),
723756 _INIT_DCS_CMD(0x66, 0x00),
757+ _INIT_DCS_CMD(0x67, 0x96),
758+ _INIT_DCS_CMD(0x68, 0x10),
759+ _INIT_DCS_CMD(0x69, 0x00),
724760 _INIT_DCS_CMD(0x6A, 0x96),
725− _INIT_DCS_CMD(0x6B, 0x00),
761+ _INIT_DCS_CMD(0x6B, 0x10),
726762 _INIT_DCS_CMD(0x6C, 0x00),
727763 _INIT_DCS_CMD(0x70, 0x92),
728− _INIT_DCS_CMD(0x71, 0x00),
764+ _INIT_DCS_CMD(0x71, 0x10),
729765 _INIT_DCS_CMD(0x72, 0x00),
730− _INIT_DCS_CMD(0xA2, 0x33),
766+ _INIT_DCS_CMD(0x79, 0x96),
767+ _INIT_DCS_CMD(0x7A, 0x10),
768+ _INIT_DCS_CMD(0x88, 0x96),
769+ _INIT_DCS_CMD(0x89, 0x10),
770+
771+ _INIT_DCS_CMD(0xA2, 0x3F),
731772 _INIT_DCS_CMD(0xA3, 0x30),
732773 _INIT_DCS_CMD(0xA4, 0xC0),
774+ _INIT_DCS_CMD(0xA5, 0x03),
775+
733776 _INIT_DCS_CMD(0xE8, 0x00),
777+
734778 _INIT_DCS_CMD(0x97, 0x3C),
735779 _INIT_DCS_CMD(0x98, 0x02),
736780 _INIT_DCS_CMD(0x99, 0x95),
@@ -739,38 +783,68 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 2 unmodified lines
739783 _INIT_DCS_CMD(0x9C, 0x0B),
740784 _INIT_DCS_CMD(0x9D, 0x0A),
741785 _INIT_DCS_CMD(0x9E, 0x90),
786+
787+ _INIT_DCS_CMD(0xFF, 0x25),
788+ _INIT_DCS_CMD(0x13, 0x02),
789+ _INIT_DCS_CMD(0x14, 0xD7),
790+ _INIT_DCS_CMD(0xDB, 0x02),
791+ _INIT_DCS_CMD(0xDC, 0xD7),
792+ _INIT_DCS_CMD(0x17, 0xCF),
793+ _INIT_DCS_CMD(0x19, 0x0F),
794+ _INIT_DCS_CMD(0x1B, 0x5B),
795+
796+ _INIT_DCS_CMD(0xFF, 0x20),
797+
798+ _INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
799+ _INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
800+ _INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
801+ _INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
802+
803+ _INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
804+ _INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
805+ _INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
806+ _INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
807+
808+ _INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
809+ _INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
810+ _INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
811+ _INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
812+
813+ _INIT_DCS_CMD(0xFF, 0x21),
814+ _INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
815+ _INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
816+ _INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
817+ _INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
818+
819+ _INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
820+ _INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
821+ _INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
822+ _INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
823+
824+ _INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
825+ _INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
826+ _INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
827+ _INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
828+
742829 _INIT_DCS_CMD(0xFF, 0xF0),
743830 _INIT_DCS_CMD(0xFB, 0x01),
744831 _INIT_DCS_CMD(0x3A, 0x08),
745− _INIT_DCS_CMD(0xFF, 0xD0),
746− _INIT_DCS_CMD(0xFB, 0x01),
747− _INIT_DCS_CMD(0x00, 0x33),
748− _INIT_DCS_CMD(0x08, 0x01),
749− _INIT_DCS_CMD(0x09, 0xBF),
750− _INIT_DCS_CMD(0x2F, 0x33),
751− _INIT_DCS_CMD(0xFF, 0x23),
752− _INIT_DCS_CMD(0xFB, 0x01),
753− _INIT_DCS_CMD(0x00, 0x80),
754− _INIT_DCS_CMD(0x07, 0x00),
755− _INIT_DCS_CMD(0xFF, 0x20),
756− _INIT_DCS_CMD(0xFB, 0x01),
757− _INIT_DCS_CMD(0x30, 0x00),
758− _INIT_DCS_CMD(0xFF, 0x24),
759− _INIT_DCS_CMD(0x5C, 0x88),
760− _INIT_DCS_CMD(0x5D, 0x08),
832+
761833 _INIT_DCS_CMD(0xFF, 0x10),
762834 _INIT_DCS_CMD(0xB9, 0x01),
835+
763836 _INIT_DCS_CMD(0xFF, 0x20),
837+
764838 _INIT_DCS_CMD(0x18, 0x40),
765839 _INIT_DCS_CMD(0xFF, 0x10),
840+
766841 _INIT_DCS_CMD(0xB9, 0x02),
767842 _INIT_DCS_CMD(0xFF, 0x10),
843+
768844 _INIT_DCS_CMD(0xFB, 0x01),
769− _INIT_DCS_CMD(0xBB, 0x13),
770− _INIT_DCS_CMD(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04),
845+ _INIT_DCS_CMD(0xB0, 0x01),
771846 _INIT_DCS_CMD(0x35, 0x00),
772− _INIT_DCS_CMD(0x51, 0x0F, 0xFF),
773− _INIT_DCS_CMD(0x53, 0x24),
847+ _INIT_DCS_CMD(0x3B, 0x03, 0xAE, 0x1A, 0x04, 0x04),
774848 _INIT_DELAY_CMD(100),
775849 _INIT_DCS_CMD(0x11),
776850 _INIT_DELAY_CMD(200),
@@ -780,7 +854,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { · 3 unmodified lines
780854 };
781855
782856 static const struct panel_init_cmd boe_init_cmd[] = {
783− _INIT_DELAY_CMD(24),
784857 _INIT_DCS_CMD(0xB0, 0x05),
785858 _INIT_DCS_CMD(0xB1, 0xE5),
786859 _INIT_DCS_CMD(0xB3, 0x52),
@@ -1366,6 +1439,10 @@ static int boe_panel_prepare(struct drm_panel *panel) · 579 unmodified lines
13661439
13671440 usleep_range(10000, 11000);
13681441
1442+ if (boe->desc->lp11_before_reset) {
1443+ mipi_dsi_dcs_nop(boe->dsi);
1444+ usleep_range(1000, 2000);
1445+ }
13691446 gpiod_set_value(boe->enable_gpio, 1);
13701447 usleep_range(1000, 2000);
13711448 gpiod_set_value(boe->enable_gpio, 0);
@@ -1431,15 +1508,15 @@ static const struct panel_desc boe_tv110c9m_desc = { · 59 unmodified lines
14311508 };
14321509
14331510 static const struct drm_display_mode inx_hj110iz_default_mode = {
1434− .clock = 166594,
1511+ .clock = 168432,
14351512 .hdisplay = 1200,
14361513 .hsync_start = 1200 + 40,
14371514 .hsync_end = 1200 + 40 + 8,
14381515 .htotal = 1200 + 40 + 8 + 28,
14391516 .vdisplay = 2000,
14401517 .vsync_start = 2000 + 26,
1441− .vsync_end = 2000 + 26 + 1,
1442− .vtotal = 2000 + 26 + 1 + 149,
1518+ .vsync_end = 2000 + 26 + 2,
1519+ .vtotal = 2000 + 26 + 2 + 172,
14431520 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
14441521 };
14451522
@@ -1592,6 +1669,7 @@ static const struct panel_desc boe_tv105wum_nw0_desc = { · 146 unmodified lines
15921669 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
15931670 MIPI_DSI_MODE_LPM,
15941671 .init_cmds = boe_init_cmd,
1672+ .lp11_before_reset = true,
15951673 };
15961674
15971675 static const struct drm_display_mode starry_qfh032011_53g_default_mode = {
drivers/gpu/drm/panel/panel-novatek-nt36523.c+566−3
@@ -5,6 +5,7 @@ · 4 unmodified lines
55 * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
66 */
77
8+#include <linux/backlight.h>
89 #include <linux/delay.h>
910 #include <linux/gpio/consumer.h>
1011 #include <linux/module.h>
@@ -12,6 +13,8 @@ · 1 unmodified line
1213 #include <linux/of_graph.h>
1314 #include <linux/regulator/consumer.h>
1415
16+#include <video/mipi_display.h>
17+
1518 #include <drm/drm_connector.h>
1619 #include <drm/drm_crtc.h>
1720 #include <drm/drm_mipi_dsi.h>
@@ -30,6 +33,7 @@ struct panel_info { · 12 unmodified lines
3033 struct drm_panel panel;
3134 struct mipi_dsi_device *dsi[2];
3235 const struct panel_desc *desc;
36+ enum drm_panel_orientation orientation;
3337
3438 struct gpio_desc *reset_gpio;
3539 struct backlight_device *backlight;
@@ -53,6 +57,7 @@ struct panel_desc { · 17 unmodified lines
5357 int (*init_sequence)(struct panel_info *pinfo);
5458
5559 bool is_dual_dsi;
60+ bool has_dcs_backlight;
5661 };
5762
5863 static inline struct panel_info *to_panel_info(struct drm_panel *panel)
@@ -478,6 +483,456 @@ static int elish_csot_init_sequence(struct panel_info *pinfo) · 419 unmodified lines
478483 return 0;
479484 }
480485
486+static int j606f_boe_init_sequence(struct panel_info *pinfo)
487+{
488+ struct mipi_dsi_device *dsi = pinfo->dsi[0];
489+ struct device *dev = &dsi->dev;
490+ int ret;
491+
492+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
493+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
494+ mipi_dsi_dcs_write_seq(dsi, 0x05, 0xd9);
495+ mipi_dsi_dcs_write_seq(dsi, 0x07, 0x78);
496+ mipi_dsi_dcs_write_seq(dsi, 0x08, 0x5a);
497+ mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x63);
498+ mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x91);
499+ mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x73);
500+ mipi_dsi_dcs_write_seq(dsi, 0x95, 0xeb);
501+ mipi_dsi_dcs_write_seq(dsi, 0x96, 0xeb);
502+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x11);
503+ mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x66);
504+ mipi_dsi_dcs_write_seq(dsi, 0x75, 0xa2);
505+ mipi_dsi_dcs_write_seq(dsi, 0x77, 0xb3);
506+ mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
507+ 0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
508+ mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
509+ 0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
510+ mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
511+ 0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
512+ mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
513+ 0xfd, 0x03, 0xff);
514+ mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
515+ 0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
516+ mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
517+ 0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
518+ mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
519+ 0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
520+ mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
521+ 0xfd, 0x03, 0xff);
522+ mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4d, 0x00, 0x6d, 0x00,
523+ 0x89, 0x00, 0xa1, 0x00, 0xb6, 0x00, 0xc9);
524+ mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xda, 0x01, 0x13, 0x01, 0x3c, 0x01, 0x7e, 0x01,
525+ 0xab, 0x01, 0xf7, 0x02, 0x2f, 0x02, 0x31);
526+ mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x67, 0x02, 0xa6, 0x02, 0xd1, 0x03, 0x08, 0x03,
527+ 0x2e, 0x03, 0x5b, 0x03, 0x6b, 0x03, 0x7b);
528+ mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03,
529+ 0xfd, 0x03, 0xff);
530+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x21);
531+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
532+ mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
533+ 0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
534+ mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
535+ 0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
536+ mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
537+ 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
538+ mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
539+ 0xf5, 0x03, 0xf7);
540+ mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
541+ 0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
542+ mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
543+ 0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
544+ mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
545+ 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
546+ mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
547+ 0xf5, 0x03, 0xf7);
548+ mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00,
549+ 0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1);
550+ mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01,
551+ 0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29);
552+ mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03,
553+ 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73);
554+ mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03,
555+ 0xf5, 0x03, 0xf7);
556+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x23);
557+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
558+ mipi_dsi_dcs_write_seq(dsi, 0x00, 0x80);
559+ mipi_dsi_dcs_write_seq(dsi, 0x07, 0x00);
560+ mipi_dsi_dcs_write_seq(dsi, 0x11, 0x01);
561+ mipi_dsi_dcs_write_seq(dsi, 0x12, 0x77);
562+ mipi_dsi_dcs_write_seq(dsi, 0x15, 0x07);
563+ mipi_dsi_dcs_write_seq(dsi, 0x16, 0x07);
564+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
565+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
566+ mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
567+ mipi_dsi_dcs_write_seq(dsi, 0x01, 0x00);
568+ mipi_dsi_dcs_write_seq(dsi, 0x02, 0x1c);
569+ mipi_dsi_dcs_write_seq(dsi, 0x03, 0x1c);
570+ mipi_dsi_dcs_write_seq(dsi, 0x04, 0x1d);
571+ mipi_dsi_dcs_write_seq(dsi, 0x05, 0x1d);
572+ mipi_dsi_dcs_write_seq(dsi, 0x06, 0x04);
573+ mipi_dsi_dcs_write_seq(dsi, 0x07, 0x04);
574+ mipi_dsi_dcs_write_seq(dsi, 0x08, 0x0f);
575+ mipi_dsi_dcs_write_seq(dsi, 0x09, 0x0f);
576+ mipi_dsi_dcs_write_seq(dsi, 0x0a, 0x0e);
577+ mipi_dsi_dcs_write_seq(dsi, 0x0b, 0x0e);
578+ mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x0d);
579+ mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0d);
580+ mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x0c);
581+ mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0c);
582+ mipi_dsi_dcs_write_seq(dsi, 0x10, 0x08);
583+ mipi_dsi_dcs_write_seq(dsi, 0x11, 0x08);
584+ mipi_dsi_dcs_write_seq(dsi, 0x12, 0x00);
585+ mipi_dsi_dcs_write_seq(dsi, 0x13, 0x00);
586+ mipi_dsi_dcs_write_seq(dsi, 0x14, 0x00);
587+ mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
588+ mipi_dsi_dcs_write_seq(dsi, 0x16, 0x00);
589+ mipi_dsi_dcs_write_seq(dsi, 0x17, 0x00);
590+ mipi_dsi_dcs_write_seq(dsi, 0x18, 0x1c);
591+ mipi_dsi_dcs_write_seq(dsi, 0x19, 0x1c);
592+ mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x1d);
593+ mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x1d);
594+ mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x04);
595+ mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x04);
596+ mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x0f);
597+ mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x0f);
598+ mipi_dsi_dcs_write_seq(dsi, 0x20, 0x0e);
599+ mipi_dsi_dcs_write_seq(dsi, 0x21, 0x0e);
600+ mipi_dsi_dcs_write_seq(dsi, 0x22, 0x0d);
601+ mipi_dsi_dcs_write_seq(dsi, 0x23, 0x0d);
602+ mipi_dsi_dcs_write_seq(dsi, 0x24, 0x0c);
603+ mipi_dsi_dcs_write_seq(dsi, 0x25, 0x0c);
604+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x08);
605+ mipi_dsi_dcs_write_seq(dsi, 0x27, 0x08);
606+ mipi_dsi_dcs_write_seq(dsi, 0x28, 0x00);
607+ mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
608+ mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x00);
609+ mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
610+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x20);
611+ mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x0a);
612+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x44);
613+ mipi_dsi_dcs_write_seq(dsi, 0x33, 0x0c);
614+ mipi_dsi_dcs_write_seq(dsi, 0x34, 0x32);
615+ mipi_dsi_dcs_write_seq(dsi, 0x37, 0x44);
616+ mipi_dsi_dcs_write_seq(dsi, 0x38, 0x40);
617+ mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
618+
619+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x9a);
620+ if (ret < 0) {
621+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
622+ return ret;
623+ }
624+
625+ mipi_dsi_dcs_write_seq(dsi, 0x3b, 0xa0);
626+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x42);
627+ mipi_dsi_dcs_write_seq(dsi, 0x3f, 0x06);
628+ mipi_dsi_dcs_write_seq(dsi, 0x43, 0x06);
629+ mipi_dsi_dcs_write_seq(dsi, 0x47, 0x66);
630+ mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x9a);
631+ mipi_dsi_dcs_write_seq(dsi, 0x4b, 0xa0);
632+ mipi_dsi_dcs_write_seq(dsi, 0x4c, 0x91);
633+ mipi_dsi_dcs_write_seq(dsi, 0x4d, 0x21);
634+ mipi_dsi_dcs_write_seq(dsi, 0x4e, 0x43);
635+
636+ ret = mipi_dsi_dcs_set_display_brightness(dsi, 18);
637+ if (ret < 0) {
638+ dev_err(dev, "Failed to set display brightness: %d\n", ret);
639+ return ret;
640+ }
641+
642+ mipi_dsi_dcs_write_seq(dsi, 0x52, 0x34);
643+ mipi_dsi_dcs_write_seq(dsi, 0x55, 0x82, 0x02);
644+ mipi_dsi_dcs_write_seq(dsi, 0x56, 0x04);
645+ mipi_dsi_dcs_write_seq(dsi, 0x58, 0x21);
646+ mipi_dsi_dcs_write_seq(dsi, 0x59, 0x30);
647+ mipi_dsi_dcs_write_seq(dsi, 0x5a, 0xba);
648+ mipi_dsi_dcs_write_seq(dsi, 0x5b, 0xa0);
649+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00, 0x06);
650+ mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x00);
651+ mipi_dsi_dcs_write_seq(dsi, 0x65, 0x82);
652+ mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x20);
653+ mipi_dsi_dcs_write_seq(dsi, 0x7f, 0x3c);
654+ mipi_dsi_dcs_write_seq(dsi, 0x82, 0x04);
655+ mipi_dsi_dcs_write_seq(dsi, 0x97, 0xc0);
656+ mipi_dsi_dcs_write_seq(dsi, 0xb6,
657+ 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
658+ 0x05, 0x00, 0x00);
659+ mipi_dsi_dcs_write_seq(dsi, 0x92, 0xc4);
660+ mipi_dsi_dcs_write_seq(dsi, 0x93, 0x1a);
661+ mipi_dsi_dcs_write_seq(dsi, 0x94, 0x5f);
662+ mipi_dsi_dcs_write_seq(dsi, 0xd7, 0x55);
663+ mipi_dsi_dcs_write_seq(dsi, 0xda, 0x0a);
664+ mipi_dsi_dcs_write_seq(dsi, 0xde, 0x08);
665+ mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
666+ mipi_dsi_dcs_write_seq(dsi, 0xdc, 0xc4);
667+ mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
668+ mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
669+ mipi_dsi_dcs_write_seq(dsi, 0xe0, 0xc4);
670+ mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
671+ mipi_dsi_dcs_write_seq(dsi, 0xe2, 0xc4);
672+ mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
673+ mipi_dsi_dcs_write_seq(dsi, 0xe4, 0xc4);
674+ mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
675+ mipi_dsi_dcs_write_seq(dsi, 0xe6, 0xc4);
676+ mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x88);
677+ mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x08);
678+ mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x88);
679+ mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x08);
680+ mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x90);
681+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
682+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
683+ mipi_dsi_dcs_write_seq(dsi, 0x05, 0x00);
684+ mipi_dsi_dcs_write_seq(dsi, 0x19, 0x07);
685+ mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xba);
686+ mipi_dsi_dcs_write_seq(dsi, 0x20, 0xa0);
687+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xba);
688+ mipi_dsi_dcs_write_seq(dsi, 0x27, 0xa0);
689+ mipi_dsi_dcs_write_seq(dsi, 0x33, 0xba);
690+ mipi_dsi_dcs_write_seq(dsi, 0x34, 0xa0);
691+ mipi_dsi_dcs_write_seq(dsi, 0x3f, 0xe0);
692+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_VSYNC_TIMING, 0x00);
693+ mipi_dsi_dcs_write_seq(dsi, 0x44, 0x00);
694+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_GET_SCANLINE, 0x40);
695+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0xba);
696+ mipi_dsi_dcs_write_seq(dsi, 0x49, 0xa0);
697+ mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
698+ mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
699+ mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
700+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0xd0);
701+ mipi_dsi_dcs_write_seq(dsi, 0x61, 0xba);
702+ mipi_dsi_dcs_write_seq(dsi, 0x62, 0xa0);
703+ mipi_dsi_dcs_write_seq(dsi, 0xf1, 0x10);
704+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
705+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
706+ mipi_dsi_dcs_write_seq(dsi, 0x64, 0x16);
707+ mipi_dsi_dcs_write_seq(dsi, 0x67, 0x16);
708+ mipi_dsi_dcs_write_seq(dsi, 0x6a, 0x16);
709+ mipi_dsi_dcs_write_seq(dsi, 0x70, 0x30);
710+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_START, 0xf3);
711+ mipi_dsi_dcs_write_seq(dsi, 0xa3, 0xff);
712+ mipi_dsi_dcs_write_seq(dsi, 0xa4, 0xff);
713+ mipi_dsi_dcs_write_seq(dsi, 0xa5, 0xff);
714+ mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x08);
715+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
716+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
717+ mipi_dsi_dcs_write_seq(dsi, 0x00, 0xa1);
718+ mipi_dsi_dcs_write_seq(dsi, 0x0a, 0xf2);
719+ mipi_dsi_dcs_write_seq(dsi, 0x04, 0x28);
720+ mipi_dsi_dcs_write_seq(dsi, 0x06, 0x30);
721+ mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x13);
722+ mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x0a);
723+ mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x0a);
724+ mipi_dsi_dcs_write_seq(dsi, 0x11, 0x00);
725+ mipi_dsi_dcs_write_seq(dsi, 0x12, 0x50);
726+ mipi_dsi_dcs_write_seq(dsi, 0x13, 0x51);
727+ mipi_dsi_dcs_write_seq(dsi, 0x14, 0x65);
728+ mipi_dsi_dcs_write_seq(dsi, 0x15, 0x00);
729+ mipi_dsi_dcs_write_seq(dsi, 0x16, 0x10);
730+ mipi_dsi_dcs_write_seq(dsi, 0x17, 0xa0);
731+ mipi_dsi_dcs_write_seq(dsi, 0x18, 0x86);
732+ mipi_dsi_dcs_write_seq(dsi, 0x19, 0x11);
733+ mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7b);
734+ mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x10);
735+ mipi_dsi_dcs_write_seq(dsi, 0x1c, 0xbb);
736+ mipi_dsi_dcs_write_seq(dsi, 0x22, 0x00);
737+ mipi_dsi_dcs_write_seq(dsi, 0x23, 0x00);
738+ mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x11);
739+ mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7b);
740+ mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x00);
741+ mipi_dsi_dcs_write_seq(dsi, 0x1e, 0xc3);
742+ mipi_dsi_dcs_write_seq(dsi, 0x1f, 0xc3);
743+ mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
744+ mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
745+ mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x05);
746+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0xc3);
747+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x00);
748+ mipi_dsi_dcs_write_seq(dsi, 0x32, 0xc3);
749+ mipi_dsi_dcs_write_seq(dsi, 0x39, 0x00);
750+
751+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0xc3);
752+ if (ret < 0) {
753+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
754+ return ret;
755+ }
756+
757+ mipi_dsi_dcs_write_seq(dsi, 0x20, 0x01);
758+ mipi_dsi_dcs_write_seq(dsi, 0x33, 0x11);
759+ mipi_dsi_dcs_write_seq(dsi, 0x34, 0x78);
760+ mipi_dsi_dcs_write_seq(dsi, 0x35, 0x16);
761+ mipi_dsi_dcs_write_seq(dsi, 0xc8, 0x04);
762+ mipi_dsi_dcs_write_seq(dsi, 0xc9, 0x82);
763+ mipi_dsi_dcs_write_seq(dsi, 0xca, 0x4e);
764+ mipi_dsi_dcs_write_seq(dsi, 0xcb, 0x00);
765+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_READ_PPS_CONTINUE, 0x4c);
766+ mipi_dsi_dcs_write_seq(dsi, 0xaa, 0x47);
767+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x27);
768+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
769+ mipi_dsi_dcs_write_seq(dsi, 0x56, 0x06);
770+ mipi_dsi_dcs_write_seq(dsi, 0x58, 0x80);
771+ mipi_dsi_dcs_write_seq(dsi, 0x59, 0x53);
772+ mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x00);
773+ mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x14);
774+ mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
775+ mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x01);
776+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20);
777+ mipi_dsi_dcs_write_seq(dsi, 0x5f, 0x10);
778+ mipi_dsi_dcs_write_seq(dsi, 0x60, 0x00);
779+ mipi_dsi_dcs_write_seq(dsi, 0x61, 0x1d);
780+ mipi_dsi_dcs_write_seq(dsi, 0x62, 0x00);
781+ mipi_dsi_dcs_write_seq(dsi, 0x63, 0x01);
782+ mipi_dsi_dcs_write_seq(dsi, 0x64, 0x24);
783+ mipi_dsi_dcs_write_seq(dsi, 0x65, 0x1c);
784+ mipi_dsi_dcs_write_seq(dsi, 0x66, 0x00);
785+ mipi_dsi_dcs_write_seq(dsi, 0x67, 0x01);
786+ mipi_dsi_dcs_write_seq(dsi, 0x68, 0x25);
787+ mipi_dsi_dcs_write_seq(dsi, 0x00, 0x00);
788+ mipi_dsi_dcs_write_seq(dsi, 0x78, 0x00);
789+ mipi_dsi_dcs_write_seq(dsi, 0xc3, 0x00);
790+ mipi_dsi_dcs_write_seq(dsi, 0xd1, 0x24);
791+ mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x30);
792+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
793+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
794+ mipi_dsi_dcs_write_seq(dsi, 0x22, 0x2f);
795+ mipi_dsi_dcs_write_seq(dsi, 0x23, 0x08);
796+ mipi_dsi_dcs_write_seq(dsi, 0x24, 0x00);
797+ mipi_dsi_dcs_write_seq(dsi, 0x25, 0xc3);
798+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0xf8);
799+ mipi_dsi_dcs_write_seq(dsi, 0x27, 0x00);
800+ mipi_dsi_dcs_write_seq(dsi, 0x28, 0x1a);
801+ mipi_dsi_dcs_write_seq(dsi, 0x29, 0x00);
802+ mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x1a);
803+ mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x00);
804+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_LUT, 0x1a);
805+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0xe0);
806+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
807+ mipi_dsi_dcs_write_seq(dsi, 0x14, 0x60);
808+ mipi_dsi_dcs_write_seq(dsi, 0x16, 0xc0);
809+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0xf0);
810+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
811+
812+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x08);
813+ if (ret < 0) {
814+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
815+ return ret;
816+ }
817+
818+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
819+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
820+
821+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x5d);
822+ if (ret < 0) {
823+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
824+ return ret;
825+ }
826+
827+ mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x60);
828+ mipi_dsi_dcs_write_seq(dsi, 0x4a, 0x5d);
829+ mipi_dsi_dcs_write_seq(dsi, 0x4b, 0x60);
830+ mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x70);
831+ mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x60);
832+ mipi_dsi_dcs_write_seq(dsi, 0x91, 0x44);
833+ mipi_dsi_dcs_write_seq(dsi, 0x92, 0x75);
834+ mipi_dsi_dcs_write_seq(dsi, 0xdb, 0x05);
835+ mipi_dsi_dcs_write_seq(dsi, 0xdc, 0x75);
836+ mipi_dsi_dcs_write_seq(dsi, 0xdd, 0x22);
837+ mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x05);
838+ mipi_dsi_dcs_write_seq(dsi, 0xe0, 0x75);
839+ mipi_dsi_dcs_write_seq(dsi, 0xe1, 0x05);
840+ mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x75);
841+ mipi_dsi_dcs_write_seq(dsi, 0xe3, 0x05);
842+ mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x75);
843+ mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x05);
844+ mipi_dsi_dcs_write_seq(dsi, 0xe6, 0x75);
845+ mipi_dsi_dcs_write_seq(dsi, 0x5c, 0x00);
846+ mipi_dsi_dcs_write_seq(dsi, 0x5d, 0x00);
847+ mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x00);
848+ mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x00);
849+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
850+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
851+ mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x70);
852+ mipi_dsi_dcs_write_seq(dsi, 0x20, 0x60);
853+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_GAMMA_CURVE, 0x70);
854+ mipi_dsi_dcs_write_seq(dsi, 0x27, 0x60);
855+ mipi_dsi_dcs_write_seq(dsi, 0x33, 0x70);
856+ mipi_dsi_dcs_write_seq(dsi, 0x34, 0x60);
857+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x70);
858+ mipi_dsi_dcs_write_seq(dsi, 0x49, 0x60);
859+ mipi_dsi_dcs_write_seq(dsi, 0x5b, 0x00);
860+ mipi_dsi_dcs_write_seq(dsi, 0x61, 0x70);
861+ mipi_dsi_dcs_write_seq(dsi, 0x62, 0x60);
862+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
863+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
864+ mipi_dsi_dcs_write_seq(dsi, 0x02, 0x31);
865+ mipi_dsi_dcs_write_seq(dsi, 0x19, 0x0a);
866+ mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x7f);
867+ mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x0a);
868+ mipi_dsi_dcs_write_seq(dsi, 0x1c, 0x0c);
869+ mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x0a);
870+ mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x7f);
871+ mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x75);
872+ mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x75);
873+ mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
874+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, 0x75);
875+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_COLUMNS, 0x05);
876+ mipi_dsi_dcs_write_seq(dsi, 0x32, 0x8d);
877+
878+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x75);
879+ if (ret < 0) {
880+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
881+ return ret;
882+ }
883+
884+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
885+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
886+ mipi_dsi_dcs_write_seq(dsi, 0x25, 0x75);
887+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
888+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
889+ mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x01);
890+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
891+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
892+ mipi_dsi_dcs_write_seq(dsi, 0x18, 0x40);
893+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
894+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
895+ mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x02);
896+
897+ ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
898+ if (ret < 0) {
899+ dev_err(dev, "Failed to set tear on: %d\n", ret);
900+ return ret;
901+ }
902+
903+ mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13);
904+ mipi_dsi_dcs_write_seq(dsi, 0x3b, 0x03, 0x5f, 0x1a, 0x04, 0x04);
905+ mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
906+ usleep_range(10000, 11000);
907+ mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
908+
909+ ret = mipi_dsi_dcs_set_display_brightness(dsi, 0);
910+ if (ret < 0) {
911+ dev_err(dev, "Failed to set display brightness: %d\n", ret);
912+ return ret;
913+ }
914+
915+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
916+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
917+ mipi_dsi_dcs_write_seq(dsi, 0x68, 0x05, 0x01);
918+
919+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
920+ if (ret < 0) {
921+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
922+ return ret;
923+ }
924+ msleep(100);
925+
926+ ret = mipi_dsi_dcs_set_display_on(dsi);
927+ if (ret < 0) {
928+ dev_err(dev, "Failed to set display on: %d\n", ret);
929+ return ret;
930+ }
931+ msleep(30);
932+
933+ return 0;
934+}
935+
481936 static const struct drm_display_mode elish_boe_modes[] = {
482937 {
483938 /* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz preferred */
@@ -508,6 +963,22 @@ static const struct drm_display_mode elish_csot_modes[] = { · 24 unmodified lines
508963 },
509964 };
510965
966+static const struct drm_display_mode j606f_boe_modes[] = {
967+ {
968+ .clock = (1200 + 58 + 2 + 60) * (2000 + 26 + 2 + 93) * 60 / 1000,
969+ .hdisplay = 1200,
970+ .hsync_start = 1200 + 58,
971+ .hsync_end = 1200 + 58 + 2,
972+ .htotal = 1200 + 58 + 2 + 60,
973+ .vdisplay = 2000,
974+ .vsync_start = 2000 + 26,
975+ .vsync_end = 2000 + 26 + 2,
976+ .vtotal = 2000 + 26 + 2 + 93,
977+ .width_mm = 143,
978+ .height_mm = 235,
979+ },
980+};
981+
511982 static const struct panel_desc elish_boe_desc = {
512983 .modes = elish_boe_modes,
513984 .num_modes = ARRAY_SIZE(elish_boe_modes),
@@ -544,6 +1015,20 @@ static const struct panel_desc elish_csot_desc = { · 30 unmodified lines
5441015 .is_dual_dsi = true,
5451016 };
5461017
1018+static const struct panel_desc j606f_boe_desc = {
1019+ .modes = j606f_boe_modes,
1020+ .num_modes = ARRAY_SIZE(j606f_boe_modes),
1021+ .width_mm = 143,
1022+ .height_mm = 235,
1023+ .bpc = 8,
1024+ .lanes = 4,
1025+ .format = MIPI_DSI_FMT_RGB888,
1026+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1027+ MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
1028+ .init_sequence = j606f_boe_init_sequence,
1029+ .has_dcs_backlight = true,
1030+};
1031+
5471032 static void nt36523_reset(struct panel_info *pinfo)
5481033 {
5491034 gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
@@ -672,13 +1157,74 @@ static int nt36523_get_modes(struct drm_panel *panel, · 122 unmodified lines
6721157 return pinfo->desc->num_modes;
6731158 }
6741159
1160+static enum drm_panel_orientation nt36523_get_orientation(struct drm_panel *panel)
1161+{
1162+ struct panel_info *pinfo = to_panel_info(panel);
1163+
1164+ return pinfo->orientation;
1165+}
1166+
6751167 static const struct drm_panel_funcs nt36523_panel_funcs = {
6761168 .disable = nt36523_disable,
6771169 .prepare = nt36523_prepare,
6781170 .unprepare = nt36523_unprepare,
6791171 .get_modes = nt36523_get_modes,
1172+ .get_orientation = nt36523_get_orientation,
6801173 };
6811174
1175+static int nt36523_bl_update_status(struct backlight_device *bl)
1176+{
1177+ struct mipi_dsi_device *dsi = bl_get_data(bl);
1178+ u16 brightness = backlight_get_brightness(bl);
1179+ int ret;
1180+
1181+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
1182+
1183+ ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
1184+ if (ret < 0)
1185+ return ret;
1186+
1187+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
1188+
1189+ return 0;
1190+}
1191+
1192+static int nt36523_bl_get_brightness(struct backlight_device *bl)
1193+{
1194+ struct mipi_dsi_device *dsi = bl_get_data(bl);
1195+ u16 brightness;
1196+ int ret;
1197+
1198+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
1199+
1200+ ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
1201+ if (ret < 0)
1202+ return ret;
1203+
1204+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
1205+
1206+ return brightness;
1207+}
1208+
1209+static const struct backlight_ops nt36523_bl_ops = {
1210+ .update_status = nt36523_bl_update_status,
1211+ .get_brightness = nt36523_bl_get_brightness,
1212+};
1213+
1214+static struct backlight_device *nt36523_create_backlight(struct mipi_dsi_device *dsi)
1215+{
1216+ struct device *dev = &dsi->dev;
1217+ const struct backlight_properties props = {
1218+ .type = BACKLIGHT_RAW,
1219+ .brightness = 512,
1220+ .max_brightness = 4095,
1221+ .scale = BACKLIGHT_SCALE_NON_LINEAR,
1222+ };
1223+
1224+ return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
1225+ &nt36523_bl_ops, &props);
1226+}
1227+
6821228 static int nt36523_probe(struct mipi_dsi_device *dsi)
6831229 {
6841230 struct device *dev = &dsi->dev;
@@ -730,9 +1276,22 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 45 unmodified lines
7301276 mipi_dsi_set_drvdata(dsi, pinfo);
7311277 drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI);
7321278
733− ret = drm_panel_of_backlight(&pinfo->panel);
734− if (ret)
735− return dev_err_probe(dev, ret, "failed to get backlight\n");
1279+ ret = of_drm_get_panel_orientation(dev->of_node, &pinfo->orientation);
1280+ if (ret < 0) {
1281+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
1282+ return ret;
1283+ }
1284+
1285+ if (pinfo->desc->has_dcs_backlight) {
1286+ pinfo->panel.backlight = nt36523_create_backlight(dsi);
1287+ if (IS_ERR(pinfo->panel.backlight))
1288+ return dev_err_probe(dev, PTR_ERR(pinfo->panel.backlight),
1289+ "Failed to create backlight\n");
1290+ } else {
1291+ ret = drm_panel_of_backlight(&pinfo->panel);
1292+ if (ret)
1293+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
1294+ }
7361295
7371296 drm_panel_add(&pinfo->panel);
7381297
@@ -750,6 +1309,10 @@ static int nt36523_probe(struct mipi_dsi_device *dsi) · 11 unmodified lines
7501309 }
7511310
7521311 static const struct of_device_id nt36523_of_match[] = {
1312+ {
1313+ .compatible = "lenovo,j606f-boe-nt36523w",
1314+ .data = &j606f_boe_desc,
1315+ },
7531316 {
7541317 .compatible = "xiaomi,elish-boe-nt36523",
7551318 .data = &elish_boe_desc,
drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c+585−0
@@ -0,0 +1,585 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Samsung S6D7AA0 MIPI-DSI TFT LCD controller drm_panel driver.
4+ *
5+ * Copyright (C) 2022 Artur Weber <aweber.kernel@gmail.com>
6+ */
7+
8+#include <linux/backlight.h>
9+#include <linux/delay.h>
10+#include <linux/gpio/consumer.h>
11+#include <linux/module.h>
12+#include <linux/regulator/consumer.h>
13+#include <linux/of.h>
14+#include <linux/of_device.h>
15+
16+#include <video/mipi_display.h>
17+#include <drm/drm_mipi_dsi.h>
18+#include <drm/drm_modes.h>
19+#include <drm/drm_panel.h>
20+
21+/* Manufacturer command set */
22+#define MCS_BL_CTL 0xc3
23+#define MCS_OTP_RELOAD 0xd0
24+#define MCS_PASSWD1 0xf0
25+#define MCS_PASSWD2 0xf1
26+#define MCS_PASSWD3 0xfc
27+
28+struct s6d7aa0 {
29+ struct drm_panel panel;
30+ struct mipi_dsi_device *dsi;
31+ struct gpio_desc *reset_gpio;
32+ struct regulator_bulk_data supplies[2];
33+ const struct s6d7aa0_panel_desc *desc;
34+};
35+
36+struct s6d7aa0_panel_desc {
37+ unsigned int panel_type;
38+ int (*init_func)(struct s6d7aa0 *ctx);
39+ int (*off_func)(struct s6d7aa0 *ctx);
40+ const struct drm_display_mode *drm_mode;
41+ unsigned long mode_flags;
42+ u32 bus_flags;
43+ bool has_backlight;
44+ bool use_passwd3;
45+};
46+
47+enum s6d7aa0_panels {
48+ S6D7AA0_PANEL_LSL080AL02,
49+ S6D7AA0_PANEL_LSL080AL03,
50+ S6D7AA0_PANEL_LTL101AT01,
51+};
52+
53+static inline struct s6d7aa0 *panel_to_s6d7aa0(struct drm_panel *panel)
54+{
55+ return container_of(panel, struct s6d7aa0, panel);
56+}
57+
58+static void s6d7aa0_reset(struct s6d7aa0 *ctx)
59+{
60+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
61+ msleep(50);
62+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
63+ msleep(50);
64+}
65+
66+static int s6d7aa0_lock(struct s6d7aa0 *ctx, bool lock)
67+{
68+ struct mipi_dsi_device *dsi = ctx->dsi;
69+ int ret = 0;
70+
71+ if (lock) {
72+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5);
73+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5);
74+ if (ctx->desc->use_passwd3)
75+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a);
76+ } else {
77+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a);
78+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a);
79+ if (ctx->desc->use_passwd3)
80+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0xa5, 0xa5);
81+ }
82+
83+ return ret;
84+}
85+
86+static int s6d7aa0_on(struct s6d7aa0 *ctx)
87+{
88+ struct mipi_dsi_device *dsi = ctx->dsi;
89+ struct device *dev = &dsi->dev;
90+ int ret;
91+
92+ ret = ctx->desc->init_func(ctx);
93+ if (ret < 0) {
94+ dev_err(dev, "Failed to initialize panel: %d\n", ret);
95+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
96+ return ret;
97+ }
98+
99+ ret = mipi_dsi_dcs_set_display_on(dsi);
100+ if (ret < 0) {
101+ dev_err(dev, "Failed to set display on: %d\n", ret);
102+ return ret;
103+ }
104+
105+ return 0;
106+}
107+
108+static int s6d7aa0_off(struct s6d7aa0 *ctx)
109+{
110+ struct mipi_dsi_device *dsi = ctx->dsi;
111+ struct device *dev = &dsi->dev;
112+ int ret;
113+
114+ ret = ctx->desc->off_func(ctx);
115+ if (ret < 0) {
116+ dev_err(dev, "Panel-specific off function failed: %d\n", ret);
117+ return ret;
118+ }
119+
120+ ret = mipi_dsi_dcs_set_display_off(dsi);
121+ if (ret < 0) {
122+ dev_err(dev, "Failed to set display off: %d\n", ret);
123+ return ret;
124+ }
125+ msleep(64);
126+
127+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
128+ if (ret < 0) {
129+ dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
130+ return ret;
131+ }
132+ msleep(120);
133+
134+ return 0;
135+}
136+
137+static int s6d7aa0_prepare(struct drm_panel *panel)
138+{
139+ struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
140+ struct device *dev = &ctx->dsi->dev;
141+ int ret;
142+
143+ ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
144+ if (ret < 0) {
145+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
146+ return ret;
147+ }
148+
149+ s6d7aa0_reset(ctx);
150+
151+ ret = s6d7aa0_on(ctx);
152+ if (ret < 0) {
153+ dev_err(dev, "Failed to initialize panel: %d\n", ret);
154+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
155+ return ret;
156+ }
157+
158+ return 0;
159+}
160+
161+static int s6d7aa0_disable(struct drm_panel *panel)
162+{
163+ struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
164+ struct device *dev = &ctx->dsi->dev;
165+ int ret;
166+
167+ ret = s6d7aa0_off(ctx);
168+ if (ret < 0)
169+ dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
170+
171+ return 0;
172+}
173+
174+static int s6d7aa0_unprepare(struct drm_panel *panel)
175+{
176+ struct s6d7aa0 *ctx = panel_to_s6d7aa0(panel);
177+
178+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
179+ regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
180+
181+ return 0;
182+}
183+
184+/* Backlight control code */
185+
186+static int s6d7aa0_bl_update_status(struct backlight_device *bl)
187+{
188+ struct mipi_dsi_device *dsi = bl_get_data(bl);
189+ u16 brightness = backlight_get_brightness(bl);
190+ int ret;
191+
192+ ret = mipi_dsi_dcs_set_display_brightness(dsi, brightness);
193+ if (ret < 0)
194+ return ret;
195+
196+ return 0;
197+}
198+
199+static int s6d7aa0_bl_get_brightness(struct backlight_device *bl)
200+{
201+ struct mipi_dsi_device *dsi = bl_get_data(bl);
202+ u16 brightness;
203+ int ret;
204+
205+ ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
206+ if (ret < 0)
207+ return ret;
208+
209+ return brightness & 0xff;
210+}
211+
212+static const struct backlight_ops s6d7aa0_bl_ops = {
213+ .update_status = s6d7aa0_bl_update_status,
214+ .get_brightness = s6d7aa0_bl_get_brightness,
215+};
216+
217+static struct backlight_device *
218+s6d7aa0_create_backlight(struct mipi_dsi_device *dsi)
219+{
220+ struct device *dev = &dsi->dev;
221+ const struct backlight_properties props = {
222+ .type = BACKLIGHT_RAW,
223+ .brightness = 255,
224+ .max_brightness = 255,
225+ };
226+
227+ return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
228+ &s6d7aa0_bl_ops, &props);
229+}
230+
231+/* Initialization code and structures for LSL080AL02 panel */
232+
233+static int s6d7aa0_lsl080al02_init(struct s6d7aa0 *ctx)
234+{
235+ struct mipi_dsi_device *dsi = ctx->dsi;
236+ struct device *dev = &dsi->dev;
237+ int ret;
238+
239+ usleep_range(20000, 25000);
240+
241+ ret = s6d7aa0_lock(ctx, false);
242+ if (ret < 0) {
243+ dev_err(dev, "Failed to unlock registers: %d\n", ret);
244+ return ret;
245+ }
246+
247+ mipi_dsi_dcs_write_seq(dsi, MCS_OTP_RELOAD, 0x00, 0x10);
248+ usleep_range(1000, 1500);
249+
250+ /* SEQ_B6_PARAM_8_R01 */
251+ mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x10);
252+
253+ /* BL_CTL_ON */
254+ mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x28);
255+
256+ usleep_range(5000, 6000);
257+
258+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x04);
259+
260+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
261+ if (ret < 0) {
262+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
263+ return ret;
264+ }
265+
266+ msleep(120);
267+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
268+
269+ ret = s6d7aa0_lock(ctx, true);
270+ if (ret < 0) {
271+ dev_err(dev, "Failed to lock registers: %d\n", ret);
272+ return ret;
273+ }
274+
275+ ret = mipi_dsi_dcs_set_display_on(dsi);
276+ if (ret < 0) {
277+ dev_err(dev, "Failed to set display on: %d\n", ret);
278+ return ret;
279+ }
280+
281+ return 0;
282+}
283+
284+static int s6d7aa0_lsl080al02_off(struct s6d7aa0 *ctx)
285+{
286+ struct mipi_dsi_device *dsi = ctx->dsi;
287+
288+ /* BL_CTL_OFF */
289+ mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x20);
290+
291+ return 0;
292+}
293+
294+static const struct drm_display_mode s6d7aa0_lsl080al02_mode = {
295+ .clock = (800 + 16 + 4 + 140) * (1280 + 8 + 4 + 4) * 60 / 1000,
296+ .hdisplay = 800,
297+ .hsync_start = 800 + 16,
298+ .hsync_end = 800 + 16 + 4,
299+ .htotal = 800 + 16 + 4 + 140,
300+ .vdisplay = 1280,
301+ .vsync_start = 1280 + 8,
302+ .vsync_end = 1280 + 8 + 4,
303+ .vtotal = 1280 + 8 + 4 + 4,
304+ .width_mm = 108,
305+ .height_mm = 173,
306+};
307+
308+static const struct s6d7aa0_panel_desc s6d7aa0_lsl080al02_desc = {
309+ .panel_type = S6D7AA0_PANEL_LSL080AL02,
310+ .init_func = s6d7aa0_lsl080al02_init,
311+ .off_func = s6d7aa0_lsl080al02_off,
312+ .drm_mode = &s6d7aa0_lsl080al02_mode,
313+ .mode_flags = MIPI_DSI_MODE_VSYNC_FLUSH | MIPI_DSI_MODE_VIDEO_NO_HFP,
314+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
315+
316+ .has_backlight = false,
317+ .use_passwd3 = false,
318+};
319+
320+/* Initialization code and structures for LSL080AL03 panel */
321+
322+static int s6d7aa0_lsl080al03_init(struct s6d7aa0 *ctx)
323+{
324+ struct mipi_dsi_device *dsi = ctx->dsi;
325+ struct device *dev = &dsi->dev;
326+ int ret;
327+
328+ usleep_range(20000, 25000);
329+
330+ ret = s6d7aa0_lock(ctx, false);
331+ if (ret < 0) {
332+ dev_err(dev, "Failed to unlock registers: %d\n", ret);
333+ return ret;
334+ }
335+
336+ if (ctx->desc->panel_type == S6D7AA0_PANEL_LSL080AL03) {
337+ mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0xc7, 0x00, 0x29);
338+ mipi_dsi_dcs_write_seq(dsi, 0xbc, 0x01, 0x4e, 0xa0);
339+ mipi_dsi_dcs_write_seq(dsi, 0xfd, 0x16, 0x10, 0x11, 0x23,
340+ 0x09);
341+ mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x00, 0x02, 0x03, 0x21,
342+ 0x80, 0x78);
343+ } else if (ctx->desc->panel_type == S6D7AA0_PANEL_LTL101AT01) {
344+ mipi_dsi_dcs_write_seq(dsi, MCS_BL_CTL, 0x40, 0x00, 0x08);
345+ mipi_dsi_dcs_write_seq(dsi, 0xbc, 0x01, 0x4e, 0x0b);
346+ mipi_dsi_dcs_write_seq(dsi, 0xfd, 0x16, 0x10, 0x11, 0x23,
347+ 0x09);
348+ mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x00, 0x02, 0x03, 0x21,
349+ 0x80, 0x68);
350+ }
351+
352+ mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x51);
353+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
354+ mipi_dsi_dcs_write_seq(dsi, 0xf2, 0x02, 0x08, 0x08);
355+
356+ usleep_range(10000, 11000);
357+
358+ mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x80, 0x80, 0x30);
359+ mipi_dsi_dcs_write_seq(dsi, 0xcd,
360+ 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e,
361+ 0x2e, 0x2e, 0x2e, 0x2e, 0x2e);
362+ mipi_dsi_dcs_write_seq(dsi, 0xce,
363+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
364+ 0x00, 0x00, 0x00, 0x00, 0x00);
365+ mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x03);
366+
367+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
368+ if (ret < 0) {
369+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
370+ return ret;
371+ }
372+
373+ ret = s6d7aa0_lock(ctx, true);
374+ if (ret < 0) {
375+ dev_err(dev, "Failed to lock registers: %d\n", ret);
376+ return ret;
377+ }
378+
379+ ret = mipi_dsi_dcs_set_display_on(dsi);
380+ if (ret < 0) {
381+ dev_err(dev, "Failed to set display on: %d\n", ret);
382+ return ret;
383+ }
384+
385+ return 0;
386+}
387+
388+static int s6d7aa0_lsl080al03_off(struct s6d7aa0 *ctx)
389+{
390+ struct mipi_dsi_device *dsi = ctx->dsi;
391+
392+ mipi_dsi_dcs_write_seq(dsi, 0x22, 0x00);
393+
394+ return 0;
395+}
396+
397+static const struct drm_display_mode s6d7aa0_lsl080al03_mode = {
398+ .clock = (768 + 18 + 16 + 126) * (1024 + 8 + 2 + 6) * 60 / 1000,
399+ .hdisplay = 768,
400+ .hsync_start = 768 + 18,
401+ .hsync_end = 768 + 18 + 16,
402+ .htotal = 768 + 18 + 16 + 126,
403+ .vdisplay = 1024,
404+ .vsync_start = 1024 + 8,
405+ .vsync_end = 1024 + 8 + 2,
406+ .vtotal = 1024 + 8 + 2 + 6,
407+ .width_mm = 122,
408+ .height_mm = 163,
409+};
410+
411+static const struct s6d7aa0_panel_desc s6d7aa0_lsl080al03_desc = {
412+ .panel_type = S6D7AA0_PANEL_LSL080AL03,
413+ .init_func = s6d7aa0_lsl080al03_init,
414+ .off_func = s6d7aa0_lsl080al03_off,
415+ .drm_mode = &s6d7aa0_lsl080al03_mode,
416+ .mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET,
417+ .bus_flags = 0,
418+
419+ .has_backlight = true,
420+ .use_passwd3 = true,
421+};
422+
423+/* Initialization structures for LTL101AT01 panel */
424+
425+static const struct drm_display_mode s6d7aa0_ltl101at01_mode = {
426+ .clock = (768 + 96 + 16 + 184) * (1024 + 8 + 2 + 6) * 60 / 1000,
427+ .hdisplay = 768,
428+ .hsync_start = 768 + 96,
429+ .hsync_end = 768 + 96 + 16,
430+ .htotal = 768 + 96 + 16 + 184,
431+ .vdisplay = 1024,
432+ .vsync_start = 1024 + 8,
433+ .vsync_end = 1024 + 8 + 2,
434+ .vtotal = 1024 + 8 + 2 + 6,
435+ .width_mm = 148,
436+ .height_mm = 197,
437+};
438+
439+static const struct s6d7aa0_panel_desc s6d7aa0_ltl101at01_desc = {
440+ .panel_type = S6D7AA0_PANEL_LTL101AT01,
441+ .init_func = s6d7aa0_lsl080al03_init, /* Similar init to LSL080AL03 */
442+ .off_func = s6d7aa0_lsl080al03_off,
443+ .drm_mode = &s6d7aa0_ltl101at01_mode,
444+ .mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET,
445+ .bus_flags = 0,
446+
447+ .has_backlight = true,
448+ .use_passwd3 = true,
449+};
450+
451+static int s6d7aa0_get_modes(struct drm_panel *panel,
452+ struct drm_connector *connector)
453+{
454+ struct drm_display_mode *mode;
455+ struct s6d7aa0 *ctx;
456+
457+ ctx = container_of(panel, struct s6d7aa0, panel);
458+ if (!ctx)
459+ return -EINVAL;
460+
461+ mode = drm_mode_duplicate(connector->dev, ctx->desc->drm_mode);
462+ if (!mode)
463+ return -ENOMEM;
464+
465+ drm_mode_set_name(mode);
466+
467+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
468+ connector->display_info.width_mm = mode->width_mm;
469+ connector->display_info.height_mm = mode->height_mm;
470+ connector->display_info.bus_flags = ctx->desc->bus_flags;
471+ drm_mode_probed_add(connector, mode);
472+
473+ return 1;
474+}
475+
476+static const struct drm_panel_funcs s6d7aa0_panel_funcs = {
477+ .disable = s6d7aa0_disable,
478+ .prepare = s6d7aa0_prepare,
479+ .unprepare = s6d7aa0_unprepare,
480+ .get_modes = s6d7aa0_get_modes,
481+};
482+
483+static int s6d7aa0_probe(struct mipi_dsi_device *dsi)
484+{
485+ struct device *dev = &dsi->dev;
486+ struct s6d7aa0 *ctx;
487+ int ret;
488+
489+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
490+ if (!ctx)
491+ return -ENOMEM;
492+
493+ ctx->desc = of_device_get_match_data(dev);
494+ if (!ctx->desc)
495+ return -ENODEV;
496+
497+ ctx->supplies[0].supply = "power";
498+ ctx->supplies[1].supply = "vmipi";
499+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
500+ ctx->supplies);
501+ if (ret < 0)
502+ return dev_err_probe(dev, ret, "Failed to get regulators\n");
503+
504+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
505+ if (IS_ERR(ctx->reset_gpio))
506+ return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
507+ "Failed to get reset-gpios\n");
508+
509+ ctx->dsi = dsi;
510+ mipi_dsi_set_drvdata(dsi, ctx);
511+
512+ dsi->lanes = 4;
513+ dsi->format = MIPI_DSI_FMT_RGB888;
514+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
515+ | ctx->desc->mode_flags;
516+
517+ drm_panel_init(&ctx->panel, dev, &s6d7aa0_panel_funcs,
518+ DRM_MODE_CONNECTOR_DSI);
519+ ctx->panel.prepare_prev_first = true;
520+
521+ ret = drm_panel_of_backlight(&ctx->panel);
522+ if (ret)
523+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
524+
525+ /* Use DSI-based backlight as fallback if available */
526+ if (ctx->desc->has_backlight && !ctx->panel.backlight) {
527+ ctx->panel.backlight = s6d7aa0_create_backlight(dsi);
528+ if (IS_ERR(ctx->panel.backlight))
529+ return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight),
530+ "Failed to create backlight\n");
531+ }
532+
533+ drm_panel_add(&ctx->panel);
534+
535+ ret = mipi_dsi_attach(dsi);
536+ if (ret < 0) {
537+ dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
538+ drm_panel_remove(&ctx->panel);
539+ return ret;
540+ }
541+
542+ return 0;
543+}
544+
545+static void s6d7aa0_remove(struct mipi_dsi_device *dsi)
546+{
547+ struct s6d7aa0 *ctx = mipi_dsi_get_drvdata(dsi);
548+ int ret;
549+
550+ ret = mipi_dsi_detach(dsi);
551+ if (ret < 0)
552+ dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
553+
554+ drm_panel_remove(&ctx->panel);
555+}
556+
557+static const struct of_device_id s6d7aa0_of_match[] = {
558+ {
559+ .compatible = "samsung,lsl080al02",
560+ .data = &s6d7aa0_lsl080al02_desc
561+ },
562+ {
563+ .compatible = "samsung,lsl080al03",
564+ .data = &s6d7aa0_lsl080al03_desc
565+ },
566+ {
567+ .compatible = "samsung,ltl101at01",
568+ .data = &s6d7aa0_ltl101at01_desc
569+ },
570+ { /* sentinel */ }
571+};
572+
573+static struct mipi_dsi_driver s6d7aa0_driver = {
574+ .probe = s6d7aa0_probe,
575+ .remove = s6d7aa0_remove,
576+ .driver = {
577+ .name = "panel-samsung-s6d7aa0",
578+ .of_match_table = s6d7aa0_of_match,
579+ },
580+};
581+module_mipi_dsi_driver(s6d7aa0_driver);
582+
583+MODULE_AUTHOR("Artur Weber <aweber.kernel@gmail.com>");
584+MODULE_DESCRIPTION("Samsung S6D7AA0 MIPI-DSI LCD controller driver");
585+MODULE_LICENSE("GPL");
drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c+6−37
@@ -28,9 +28,6 @@ struct sharp_nt_panel { · 27 unmodified lines
2828 struct gpio_desc *reset_gpio;
2929
3030 bool prepared;
31− bool enabled;
32−
33− const struct drm_display_mode *mode;
3431 };
3532
3633 static inline struct sharp_nt_panel *to_sharp_nt_panel(struct drm_panel *panel)
@@ -97,19 +94,6 @@ static int sharp_nt_panel_off(struct sharp_nt_panel *sharp_nt) · 60 unmodified lines
9794 return 0;
9895 }
9996
100−
101−static int sharp_nt_panel_disable(struct drm_panel *panel)
102−{
103− struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
104−
105− if (!sharp_nt->enabled)
106− return 0;
107−
108− sharp_nt->enabled = false;
109−
110− return 0;
111−}
112−
11397 static int sharp_nt_panel_unprepare(struct drm_panel *panel)
11498 {
11599 struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
@@ -179,28 +163,16 @@ poweroff: · 63 unmodified lines
179163 return ret;
180164 }
181165
182−static int sharp_nt_panel_enable(struct drm_panel *panel)
183−{
184− struct sharp_nt_panel *sharp_nt = to_sharp_nt_panel(panel);
185−
186− if (sharp_nt->enabled)
187− return 0;
188−
189− sharp_nt->enabled = true;
190−
191− return 0;
192−}
193−
194166 static const struct drm_display_mode default_mode = {
195− .clock = 41118,
167+ .clock = (540 + 48 + 32 + 80) * (960 + 3 + 10 + 15) * 60 / 1000,
196168 .hdisplay = 540,
197169 .hsync_start = 540 + 48,
198− .hsync_end = 540 + 48 + 80,
199− .htotal = 540 + 48 + 80 + 32,
170+ .hsync_end = 540 + 48 + 32,
171+ .htotal = 540 + 48 + 32 + 80,
200172 .vdisplay = 960,
201173 .vsync_start = 960 + 3,
202− .vsync_end = 960 + 3 + 15,
203− .vtotal = 960 + 3 + 15 + 1,
174+ .vsync_end = 960 + 3 + 10,
175+ .vtotal = 960 + 3 + 10 + 15,
204176 };
205177
206178 static int sharp_nt_panel_get_modes(struct drm_panel *panel,
@@ -227,10 +199,8 @@ static int sharp_nt_panel_get_modes(struct drm_panel *panel, · 20 unmodified lines
227199 }
228200
229201 static const struct drm_panel_funcs sharp_nt_panel_funcs = {
230− .disable = sharp_nt_panel_disable,
231202 .unprepare = sharp_nt_panel_unprepare,
232203 .prepare = sharp_nt_panel_prepare,
233− .enable = sharp_nt_panel_enable,
234204 .get_modes = sharp_nt_panel_get_modes,
235205 };
236206
@@ -239,8 +209,6 @@ static int sharp_nt_panel_add(struct sharp_nt_panel *sharp_nt) · 2 unmodified lines
239209 struct device *dev = &sharp_nt->dsi->dev;
240210 int ret;
241211
242− sharp_nt->mode = &default_mode;
243−
244212 sharp_nt->supply = devm_regulator_get(dev, "avdd");
245213 if (IS_ERR(sharp_nt->supply))
246214 return PTR_ERR(sharp_nt->supply);
@@ -280,6 +248,7 @@ static int sharp_nt_panel_probe(struct mipi_dsi_device *dsi) · 33 unmodified lines
280248 dsi->lanes = 2;
281249 dsi->format = MIPI_DSI_FMT_RGB888;
282250 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
251+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
283252 MIPI_DSI_MODE_VIDEO_HSE |
284253 MIPI_DSI_CLOCK_NON_CONTINUOUS |
285254 MIPI_DSI_MODE_NO_EOT_PACKET;
drivers/gpu/drm/panel/panel-simple.c+69−0
@@ -1211,6 +1211,37 @@ static const struct panel_desc bananapi_s070wv20_ct16 = { · 1210 unmodified lines
12111211 },
12121212 };
12131213
1214+static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1215+ .pixelclock = { 69922000, 71000000, 72293000 },
1216+ .hactive = { 1280, 1280, 1280 },
1217+ .hfront_porch = { 48, 48, 48 },
1218+ .hback_porch = { 80, 80, 80 },
1219+ .hsync_len = { 32, 32, 32 },
1220+ .vactive = { 800, 800, 800 },
1221+ .vfront_porch = { 3, 3, 3 },
1222+ .vback_porch = { 14, 14, 14 },
1223+ .vsync_len = { 6, 6, 6 },
1224+};
1225+
1226+static const struct panel_desc boe_ev121wxm_n10_1850 = {
1227+ .timings = &boe_ev121wxm_n10_1850_timing,
1228+ .num_timings = 1,
1229+ .bpc = 8,
1230+ .size = {
1231+ .width = 261,
1232+ .height = 163,
1233+ },
1234+ .delay = {
1235+ .prepare = 9,
1236+ .enable = 300,
1237+ .unprepare = 300,
1238+ .disable = 560,
1239+ },
1240+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1241+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1242+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1243+};
1244+
12141245 static const struct drm_display_mode boe_hv070wsa_mode = {
12151246 .clock = 42105,
12161247 .hdisplay = 1024,
@@ -2142,6 +2173,38 @@ static const struct panel_desc innolux_at070tn92 = { · 925 unmodified lines
21422173 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
21432174 };
21442175
2176+static const struct display_timing innolux_g070ace_l01_timing = {
2177+ .pixelclock = { 25200000, 35000000, 35700000 },
2178+ .hactive = { 800, 800, 800 },
2179+ .hfront_porch = { 30, 32, 87 },
2180+ .hback_porch = { 30, 32, 87 },
2181+ .hsync_len = { 1, 1, 1 },
2182+ .vactive = { 480, 480, 480 },
2183+ .vfront_porch = { 3, 3, 3 },
2184+ .vback_porch = { 13, 13, 13 },
2185+ .vsync_len = { 1, 1, 4 },
2186+ .flags = DISPLAY_FLAGS_DE_HIGH,
2187+};
2188+
2189+static const struct panel_desc innolux_g070ace_l01 = {
2190+ .timings = &innolux_g070ace_l01_timing,
2191+ .num_timings = 1,
2192+ .bpc = 8,
2193+ .size = {
2194+ .width = 152,
2195+ .height = 91,
2196+ },
2197+ .delay = {
2198+ .prepare = 10,
2199+ .enable = 50,
2200+ .disable = 50,
2201+ .unprepare = 500,
2202+ },
2203+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2204+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2205+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2206+};
2207+
21452208 static const struct display_timing innolux_g070y2_l01_timing = {
21462209 .pixelclock = { 28000000, 29500000, 32000000 },
21472210 .hactive = { 800, 800, 800 },
@@ -3984,6 +4047,9 @@ static const struct of_device_id platform_of_match[] = { · 1836 unmodified lines
39844047 }, {
39854048 .compatible = "bananapi,s070wv20-ct16",
39864049 .data = &bananapi_s070wv20_ct16,
4050+ }, {
4051+ .compatible = "boe,ev121wxm-n10-1850",
4052+ .data = &boe_ev121wxm_n10_1850,
39874053 }, {
39884054 .compatible = "boe,hv070wsa-100",
39894055 .data = &boe_hv070wsa
@@ -4098,6 +4164,9 @@ static const struct of_device_id platform_of_match[] = { · 108 unmodified lines
40984164 }, {
40994165 .compatible = "innolux,at070tn92",
41004166 .data = &innolux_at070tn92,
4167+ }, {
4168+ .compatible = "innolux,g070ace-l01",
4169+ .data = &innolux_g070ace_l01,
41014170 }, {
41024171 .compatible = "innolux,g070y2-l01",
41034172 .data = &innolux_g070y2_l01,
drivers/gpu/drm/panel/panel-sitronix-st7703.c+99−3
@@ -28,6 +28,7 @@ · 27 unmodified lines
2828 /* Manufacturer specific Commands send via DSI */
2929 #define ST7703_CMD_ALL_PIXEL_OFF 0x22
3030 #define ST7703_CMD_ALL_PIXEL_ON 0x23
31+#define ST7703_CMD_SETAPID 0xB1
3132 #define ST7703_CMD_SETDISP 0xB2
3233 #define ST7703_CMD_SETRGBIF 0xB3
3334 #define ST7703_CMD_SETCYC 0xB4
@@ -41,12 +42,15 @@ · 7 unmodified lines
4142 #define ST7703_CMD_UNKNOWN_BF 0xBF
4243 #define ST7703_CMD_SETSCR 0xC0
4344 #define ST7703_CMD_SETPOWER 0xC1
45+#define ST7703_CMD_SETECO 0xC6
46+#define ST7703_CMD_SETIO 0xC7
47+#define ST7703_CMD_SETCABC 0xC8
4448 #define ST7703_CMD_SETPANEL 0xCC
45−#define ST7703_CMD_UNKNOWN_C6 0xC6
4649 #define ST7703_CMD_SETGAMMA 0xE0
4750 #define ST7703_CMD_SETEQ 0xE3
4851 #define ST7703_CMD_SETGIP1 0xE9
4952 #define ST7703_CMD_SETGIP2 0xEA
53+#define ST7703_CMD_UNKNOWN_EF 0xEF
5054
5155 struct st7703 {
5256 struct device *dev;
@@ -249,8 +253,7 @@ static int xbd599_init_sequence(struct st7703 *ctx) · 196 unmodified lines
249253 * ESD_DET_TIME_SEL = 0 frames
250254 */);
251255
252− /* Undocumented command. */
253− mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_C6, 0x01, 0x00, 0xFF, 0xFF, 0x00);
256+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00);
254257
255258 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
256259 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
@@ -338,6 +341,98 @@ static const struct st7703_panel_desc xbd599_desc = { · 81 unmodified lines
338341 .init_sequence = xbd599_init_sequence,
339342 };
340343
344+static int rg353v2_init_sequence(struct st7703 *ctx)
345+{
346+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
347+
348+ /*
349+ * Init sequence was supplied by the panel vendor.
350+ */
351+
352+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
353+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00,
354+ 0xda, 0x80);
355+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70);
356+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
357+ 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
358+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
359+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a);
360+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92);
361+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22,
362+ 0xf0, 0x63);
363+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05,
364+ 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00,
365+ 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a,
366+ 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
367+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47);
368+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
369+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
370+ 0x00, 0x00, 0x12, 0x50, 0x00);
371+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32,
372+ 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33,
373+ 0x33);
374+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
375+ 0x00, 0xff);
376+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
377+ 0x00, 0x00);
378+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
379+ 0x02);
380+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b);
381+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d,
382+ 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d,
383+ 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07,
384+ 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c,
385+ 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a);
386+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
387+ 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
388+ 0xc0, 0x10);
389+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00,
390+ 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80,
391+ 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00,
392+ 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,
393+ 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88,
394+ 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35,
395+ 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
396+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
397+ 0x00, 0x00, 0x00);
398+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
399+ 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
400+ 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88,
401+ 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42,
402+ 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00,
403+ 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
404+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
405+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
406+ 0x00);
407+ mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
408+
409+ return 0;
410+}
411+
412+static const struct drm_display_mode rg353v2_mode = {
413+ .hdisplay = 640,
414+ .hsync_start = 640 + 40,
415+ .hsync_end = 640 + 40 + 2,
416+ .htotal = 640 + 40 + 2 + 80,
417+ .vdisplay = 480,
418+ .vsync_start = 480 + 18,
419+ .vsync_end = 480 + 18 + 2,
420+ .vtotal = 480 + 18 + 2 + 28,
421+ .clock = 24150,
422+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
423+ .width_mm = 70,
424+ .height_mm = 57,
425+};
426+
427+static const struct st7703_panel_desc rg353v2_desc = {
428+ .mode = &rg353v2_mode,
429+ .lanes = 4,
430+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
431+ MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_LPM,
432+ .format = MIPI_DSI_FMT_RGB888,
433+ .init_sequence = rg353v2_init_sequence,
434+};
435+
341436 static int st7703_enable(struct drm_panel *panel)
342437 {
343438 struct st7703 *ctx = panel_to_st7703(panel);
@@ -598,6 +693,7 @@ static void st7703_remove(struct mipi_dsi_device *dsi) · 254 unmodified lines
598693 }
599694
600695 static const struct of_device_id st7703_of_match[] = {
696+ { .compatible = "anbernic,rg353v-panel-v2", .data = &rg353v2_desc },
601697 { .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },
602698 { .compatible = "xingbangda,xbd599", .data = &xbd599_desc },
603699 { /* sentinel */ }
drivers/gpu/drm/rockchip/cdn-dp-core.c+2−3
@@ -273,10 +273,9 @@ static int cdn_dp_connector_get_modes(struct drm_connector *connector) · 272 unmodified lines
273273 edid->width_cm, edid->height_cm);
274274
275275 dp->sink_has_audio = drm_detect_monitor_audio(edid);
276+
277+ drm_connector_update_edid_property(connector, edid);
276278 ret = drm_add_edid_modes(connector, edid);
277− if (ret)
278− drm_connector_update_edid_property(connector,
279− edid);
280279 }
281280 mutex_unlock(&dp->lock);
282281
drivers/gpu/drm/rockchip/rockchip_drm_drv.c+1−1
@@ -140,7 +140,7 @@ static int rockchip_drm_bind(struct device *dev) · 139 unmodified lines
140140 int ret;
141141
142142 /* Remove existing drivers that may own the framebuffer memory. */
143− ret = drm_aperture_remove_framebuffers(false, &rockchip_drm_driver);
143+ ret = drm_aperture_remove_framebuffers(&rockchip_drm_driver);
144144 if (ret) {
145145 DRM_DEV_ERROR(dev,
146146 "Failed to remove existing framebuffers - %d.\n",
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