History

Merge tag 'arm-fixes-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann: "Here are a couple of bug fixes, mostly for devicetree files NXP i.MX: - Use correct voltage on some i.MX8M board device trees to avoid hardware damage - Code fixes for a compiler warning and incorrect reference counting, both harmless. - Fix the i.MX8M SoC driver to correctly identify imx8mp - Fix watchdog configuration in imx6ul-kontron device tree. Broadcom: - A small regression fix for the Raspberry-Pi firmware driver - A Kconfig change to use the correct timer driver on Northstar - A DT fix for the Luxul XWC-2000 machine - Two more DT fixes for NSP SoCs STmicroelectronics STI - Revert one broken patch for L2 cache configuration ARM Versatile Express: - Fix a regression by reverting a broken DT cleanup TEE drivers: - MAINTAINERS: change tee mailing list" * tag 'arm-fixes-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: Revert "ARM: sti: Implement dummy L2 cache's write_sec" soc: imx8m: fix build warning ARM: imx6: add missing put_device() call in imx6q_suspend_init() ARM: imx5: add missing put_device() call in imx_suspend_alloc_ocram() soc: imx8m: Correct i.MX8MP UID fuse offset ARM: dts: imx6ul-kontron: Change WDOG_ANY signal from push-pull to open-drain ARM: dts: imx6ul-kontron: Move watchdog from Kontron i.MX6UL/ULL board to SoM arm64: dts: imx8mm-beacon: Fix voltages on LDO1 and LDO2 arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range arm64: dts: imx8mm-evk: correct ldo1/ldo2 voltage range ARM: dts: NSP: Correct FA2 mailbox node ARM: bcm2835: Fix integer overflow in rpi_firmware_print_firmware_revision() MAINTAINERS: change tee mailing list ARM: dts: NSP: Disable PL330 by default, add dma-coherent property ARM: bcm: Select ARM_TIMER_SP804 for ARCH_BCM_NSP ARM: dts: BCM5301X: Add missing memory "device_type" for Luxul XWC-2000 arm: dts: vexpress: Move mcc node back into motherboard node

Linus Torvalds committed 6 years ago

Commit e44b59c2 parents 668f532 42d3f7e22 files · +152 −118Browse files

Unified · Split

22 files
  1. MAINTAINERS +3 −3
  2. arch/arm/boot/dts/bcm-nsp.dtsi +6 −4
  3. arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +1 −0
  4. arch/arm/boot/dts/bcm958522er.dts +4 −0
  5. arch/arm/boot/dts/bcm958525er.dts +4 −0
  6. arch/arm/boot/dts/bcm958525xmc.dts +4 −0
  7. arch/arm/boot/dts/bcm958622hr.dts +4 −0
  8. arch/arm/boot/dts/bcm958623hr.dts +4 −0
  9. arch/arm/boot/dts/bcm958625hr.dts +4 −0
  10. arch/arm/boot/dts/bcm958625k.dts +4 −0
  11. arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +0 −13
  12. arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +13 −0
  13. arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +73 −73
  14. arch/arm/mach-bcm/Kconfig +1 −0
  15. arch/arm/mach-imx/pm-imx5.c +4 −2
  16. arch/arm/mach-imx/pm-imx6.c +6 −4
  17. arch/arm/mach-sti/board-dt.c +0 −9
  18. arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +2 −2
  19. arch/arm64/boot/dts/freescale/imx8mm-evk.dts +2 −2
  20. arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +2 −2
  21. drivers/firmware/raspberrypi.c +4 −1
  22. drivers/soc/imx/soc-imx8m.c +7 −3
MAINTAINERS+3−3
@@ -12695,13 +12695,13 @@ F: arch/mips/boot/dts/ralink/omega2p.dts · 12694 unmodified lines
12695 12695
12696OP-TEE DRIVER12696OP-TEE DRIVER
12697M: Jens Wiklander <jens.wiklander@linaro.org>12697M: Jens Wiklander <jens.wiklander@linaro.org>
12698L: tee-dev@lists.linaro.org12698L: op-tee@lists.trustedfirmware.org
12699S: Maintained12699S: Maintained
12700F: drivers/tee/optee/12700F: drivers/tee/optee/
12701 12701
12702OP-TEE RANDOM NUMBER GENERATOR (RNG) DRIVER12702OP-TEE RANDOM NUMBER GENERATOR (RNG) DRIVER
12703M: Sumit Garg <sumit.garg@linaro.org>12703M: Sumit Garg <sumit.garg@linaro.org>
12704L: tee-dev@lists.linaro.org12704L: op-tee@lists.trustedfirmware.org
12705S: Maintained12705S: Maintained
12706F: drivers/char/hw_random/optee-rng.c12706F: drivers/char/hw_random/optee-rng.c
12707 12707
@@ -16774,7 +16774,7 @@ F: include/media/i2c/tw9910.h · 4066 unmodified lines
16774 16774
16775TEE SUBSYSTEM16775TEE SUBSYSTEM
16776M: Jens Wiklander <jens.wiklander@linaro.org>16776M: Jens Wiklander <jens.wiklander@linaro.org>
16777L: tee-dev@lists.linaro.org16777L: op-tee@lists.trustedfirmware.org
16778S: Maintained16778S: Maintained
16779F: Documentation/tee.txt16779F: Documentation/tee.txt
16780F: drivers/tee/16780F: drivers/tee/
arch/arm/boot/dts/bcm-nsp.dtsi+6−4
@@ -200,7 +200,7 @@ · 199 unmodified lines
200 status = "disabled";200 status = "disabled";
201 };201 };
202 202
203 dma@20000 {203 dma: dma@20000 {
204 compatible = "arm,pl330", "arm,primecell";204 compatible = "arm,pl330", "arm,primecell";
205 reg = <0x20000 0x1000>;205 reg = <0x20000 0x1000>;
206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,6 +215,8 @@ · 8 unmodified lines
215 clocks = <&iprocslow>;215 clocks = <&iprocslow>;
216 clock-names = "apb_pclk";216 clock-names = "apb_pclk";
217 #dma-cells = <1>;217 #dma-cells = <1>;
218 dma-coherent;
219 status = "disabled";
218 };220 };
219 221
220 sdio: sdhci@21000 {222 sdio: sdhci@21000 {
@@ -257,10 +259,10 @@ · 36 unmodified lines
257 status = "disabled";259 status = "disabled";
258 };260 };
259 261
260 mailbox: mailbox@25000 {262 mailbox: mailbox@25c00 {
261 compatible = "brcm,iproc-fa2-mbox";263 compatible = "brcm,iproc-fa2-mbox";
262 reg = <0x25000 0x445>;264 reg = <0x25c00 0x400>;
263 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;265 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
264 #mbox-cells = <1>;266 #mbox-cells = <1>;
265 brcm,rx-status-len = <32>;267 brcm,rx-status-len = <32>;
266 brcm,use-bcm-hdr;268 brcm,use-bcm-hdr;
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts+1−0
@@ -17,6 +17,7 @@ · 16 unmodified lines
17 };17 };
18 18
19 memory {19 memory {
20 device_type = "memory";
20 reg = <0x00000000 0x0800000021 reg = <0x00000000 0x08000000
21 0x88000000 0x18000000>;22 0x88000000 0x18000000>;
22 };23 };
arch/arm/boot/dts/bcm958522er.dts+4−0
@@ -58,6 +58,10 @@ · 57 unmodified lines
58 58
59/* USB 3 support needed to be complete */59/* USB 3 support needed to be complete */
60 60
61&dma {
62 status = "okay";
63};
64
61&amac0 {65&amac0 {
62 status = "okay";66 status = "okay";
63};67};
arch/arm/boot/dts/bcm958525er.dts+4−0
@@ -58,6 +58,10 @@ · 57 unmodified lines
58 58
59/* USB 3 support needed to be complete */59/* USB 3 support needed to be complete */
60 60
61&dma {
62 status = "okay";
63};
64
61&amac0 {65&amac0 {
62 status = "okay";66 status = "okay";
63};67};
arch/arm/boot/dts/bcm958525xmc.dts+4−0
@@ -58,6 +58,10 @@ · 57 unmodified lines
58 58
59/* XHCI support needed to be complete */59/* XHCI support needed to be complete */
60 60
61&dma {
62 status = "okay";
63};
64
61&amac0 {65&amac0 {
62 status = "okay";66 status = "okay";
63};67};
arch/arm/boot/dts/bcm958622hr.dts+4−0
@@ -58,6 +58,10 @@ · 57 unmodified lines
58 58
59/* USB 3 and SLIC support needed to be complete */59/* USB 3 and SLIC support needed to be complete */
60 60
61&dma {
62 status = "okay";
63};
64
61&amac0 {65&amac0 {
62 status = "okay";66 status = "okay";
63};67};
arch/arm/boot/dts/bcm958623hr.dts+4−0
@@ -58,6 +58,10 @@ · 57 unmodified lines
58 58
59/* USB 3 and SLIC support needed to be complete */59/* USB 3 and SLIC support needed to be complete */
60 60
61&dma {
62 status = "okay";
63};
64
61&amac0 {65&amac0 {
62 status = "okay";66 status = "okay";
63};67};
arch/arm/boot/dts/bcm958625hr.dts+4−0
@@ -69,6 +69,10 @@ · 68 unmodified lines
69 status = "okay";69 status = "okay";
70};70};
71 71
72&dma {
73 status = "okay";
74};
75
72&amac0 {76&amac0 {
73 status = "okay";77 status = "okay";
74};78};
arch/arm/boot/dts/bcm958625k.dts+4−0
@@ -48,6 +48,10 @@ · 47 unmodified lines
48 };48 };
49};49};
50 50
51&dma {
52 status = "okay";
53};
54
51&amac0 {55&amac0 {
52 status = "okay";56 status = "okay";
53};57};
arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi+0−13
@@ -232,13 +232,6 @@ · 231 unmodified lines
232 status = "okay";232 status = "okay";
233};233};
234 234
235&wdog1 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_wdog>;
238 fsl,ext-reset-output;
239 status = "okay";
240};
241
242&iomuxc {235&iomuxc {
243 pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;236 pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
244 237
@@ -409,10 +402,4 @@ · 164 unmodified lines
409 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9402 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
410 >;403 >;
411 };404 };
412
413 pinctrl_wdog: wdoggrp {
414 fsl,pins = <
415 MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
416 >;
417 };
418};405};
arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi+13−0
@@ -57,6 +57,13 @@ · 56 unmodified lines
57 status = "okay";57 status = "okay";
58};58};
59 59
60&wdog1 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_wdog>;
63 fsl,ext-reset-output;
64 status = "okay";
65};
66
60&iomuxc {67&iomuxc {
61 pinctrl-names = "default";68 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_reset_out>;69 pinctrl-0 = <&pinctrl_reset_out>;
@@ -106,4 +113,10 @@ · 43 unmodified lines
106 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0113 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
107 >;114 >;
108 };115 };
116
117 pinctrl_wdog: wdoggrp {
118 fsl,pins = <
119 MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
120 >;
121 };
109};122};
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi+73−73
@@ -100,79 +100,6 @@ · 99 unmodified lines
100 };100 };
101 };101 };
102 102
103 mcc {
104 compatible = "arm,vexpress,config-bus";
105 arm,vexpress,config-bridge = <&v2m_sysreg>;
106
107 oscclk0 {
108 /* MCC static memory clock */
109 compatible = "arm,vexpress-osc";
110 arm,vexpress-sysreg,func = <1 0>;
111 freq-range = <25000000 60000000>;
112 #clock-cells = <0>;
113 clock-output-names = "v2m:oscclk0";
114 };
115
116 v2m_oscclk1: oscclk1 {
117 /* CLCD clock */
118 compatible = "arm,vexpress-osc";
119 arm,vexpress-sysreg,func = <1 1>;
120 freq-range = <23750000 65000000>;
121 #clock-cells = <0>;
122 clock-output-names = "v2m:oscclk1";
123 };
124
125 v2m_oscclk2: oscclk2 {
126 /* IO FPGA peripheral clock */
127 compatible = "arm,vexpress-osc";
128 arm,vexpress-sysreg,func = <1 2>;
129 freq-range = <24000000 24000000>;
130 #clock-cells = <0>;
131 clock-output-names = "v2m:oscclk2";
132 };
133
134 volt-vio {
135 /* Logic level voltage */
136 compatible = "arm,vexpress-volt";
137 arm,vexpress-sysreg,func = <2 0>;
138 regulator-name = "VIO";
139 regulator-always-on;
140 label = "VIO";
141 };
142
143 temp-mcc {
144 /* MCC internal operating temperature */
145 compatible = "arm,vexpress-temp";
146 arm,vexpress-sysreg,func = <4 0>;
147 label = "MCC";
148 };
149
150 reset {
151 compatible = "arm,vexpress-reset";
152 arm,vexpress-sysreg,func = <5 0>;
153 };
154
155 muxfpga {
156 compatible = "arm,vexpress-muxfpga";
157 arm,vexpress-sysreg,func = <7 0>;
158 };
159
160 shutdown {
161 compatible = "arm,vexpress-shutdown";
162 arm,vexpress-sysreg,func = <8 0>;
163 };
164
165 reboot {
166 compatible = "arm,vexpress-reboot";
167 arm,vexpress-sysreg,func = <9 0>;
168 };
169
170 dvimode {
171 compatible = "arm,vexpress-dvimode";
172 arm,vexpress-sysreg,func = <11 0>;
173 };
174 };
175
176 bus@8000000 {103 bus@8000000 {
177 motherboard-bus {104 motherboard-bus {
178 model = "V2M-P1";105 model = "V2M-P1";
@@ -435,6 +362,79 @@ · 256 unmodified lines
435 };362 };
436 };363 };
437 };364 };
365
366 mcc {
367 compatible = "arm,vexpress,config-bus";
368 arm,vexpress,config-bridge = <&v2m_sysreg>;
369
370 oscclk0 {
371 /* MCC static memory clock */
372 compatible = "arm,vexpress-osc";
373 arm,vexpress-sysreg,func = <1 0>;
374 freq-range = <25000000 60000000>;
375 #clock-cells = <0>;
376 clock-output-names = "v2m:oscclk0";
377 };
378
379 v2m_oscclk1: oscclk1 {
380 /* CLCD clock */
381 compatible = "arm,vexpress-osc";
382 arm,vexpress-sysreg,func = <1 1>;
383 freq-range = <23750000 65000000>;
384 #clock-cells = <0>;
385 clock-output-names = "v2m:oscclk1";
386 };
387
388 v2m_oscclk2: oscclk2 {
389 /* IO FPGA peripheral clock */
390 compatible = "arm,vexpress-osc";
391 arm,vexpress-sysreg,func = <1 2>;
392 freq-range = <24000000 24000000>;
393 #clock-cells = <0>;
394 clock-output-names = "v2m:oscclk2";
395 };
396
397 volt-vio {
398 /* Logic level voltage */
399 compatible = "arm,vexpress-volt";
400 arm,vexpress-sysreg,func = <2 0>;
401 regulator-name = "VIO";
402 regulator-always-on;
403 label = "VIO";
404 };
405
406 temp-mcc {
407 /* MCC internal operating temperature */
408 compatible = "arm,vexpress-temp";
409 arm,vexpress-sysreg,func = <4 0>;
410 label = "MCC";
411 };
412
413 reset {
414 compatible = "arm,vexpress-reset";
415 arm,vexpress-sysreg,func = <5 0>;
416 };
417
418 muxfpga {
419 compatible = "arm,vexpress-muxfpga";
420 arm,vexpress-sysreg,func = <7 0>;
421 };
422
423 shutdown {
424 compatible = "arm,vexpress-shutdown";
425 arm,vexpress-sysreg,func = <8 0>;
426 };
427
428 reboot {
429 compatible = "arm,vexpress-reboot";
430 arm,vexpress-sysreg,func = <9 0>;
431 };
432
433 dvimode {
434 compatible = "arm,vexpress-dvimode";
435 arm,vexpress-sysreg,func = <11 0>;
436 };
437 };
438 };438 };
439 };439 };
440 };440 };
arch/arm/mach-bcm/Kconfig+1−0
@@ -53,6 +53,7 @@ config ARCH_BCM_NSP · 52 unmodified lines
53 select ARM_ERRATA_75432253 select ARM_ERRATA_754322
54 select ARM_ERRATA_77542054 select ARM_ERRATA_775420
55 select ARM_ERRATA_764369 if SMP55 select ARM_ERRATA_764369 if SMP
56 select ARM_TIMER_SP804
56 select THERMAL57 select THERMAL
57 select THERMAL_OF58 select THERMAL_OF
58 help59 help
arch/arm/mach-imx/pm-imx5.c+4−2
@@ -295,14 +295,14 @@ static int __init imx_suspend_alloc_ocram( · 294 unmodified lines
295 if (!ocram_pool) {295 if (!ocram_pool) {
296 pr_warn("%s: ocram pool unavailable!\n", __func__);296 pr_warn("%s: ocram pool unavailable!\n", __func__);
297 ret = -ENODEV;297 ret = -ENODEV;
298 goto put_node;298 goto put_device;
299 }299 }
300 300
301 ocram_base = gen_pool_alloc(ocram_pool, size);301 ocram_base = gen_pool_alloc(ocram_pool, size);
302 if (!ocram_base) {302 if (!ocram_base) {
303 pr_warn("%s: unable to alloc ocram!\n", __func__);303 pr_warn("%s: unable to alloc ocram!\n", __func__);
304 ret = -ENOMEM;304 ret = -ENOMEM;
305 goto put_node;305 goto put_device;
306 }306 }
307 307
308 phys = gen_pool_virt_to_phys(ocram_pool, ocram_base);308 phys = gen_pool_virt_to_phys(ocram_pool, ocram_base);
@@ -312,6 +312,8 @@ static int __init imx_suspend_alloc_ocram( · 3 unmodified lines
312 if (virt_out)312 if (virt_out)
313 *virt_out = virt;313 *virt_out = virt;
314 314
315put_device:
316 put_device(&pdev->dev);
315put_node:317put_node:
316 of_node_put(node);318 of_node_put(node);
317 319
arch/arm/mach-imx/pm-imx6.c+6−4
@@ -493,14 +493,14 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) · 492 unmodified lines
493 if (!ocram_pool) {493 if (!ocram_pool) {
494 pr_warn("%s: ocram pool unavailable!\n", __func__);494 pr_warn("%s: ocram pool unavailable!\n", __func__);
495 ret = -ENODEV;495 ret = -ENODEV;
496 goto put_node;496 goto put_device;
497 }497 }
498 498
499 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);499 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
500 if (!ocram_base) {500 if (!ocram_base) {
501 pr_warn("%s: unable to alloc ocram!\n", __func__);501 pr_warn("%s: unable to alloc ocram!\n", __func__);
502 ret = -ENOMEM;502 ret = -ENOMEM;
503 goto put_node;503 goto put_device;
504 }504 }
505 505
506 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);506 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
@@ -523,7 +523,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) · 16 unmodified lines
523 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);523 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
524 if (ret) {524 if (ret) {
525 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);525 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
526 goto put_node;526 goto put_device;
527 }527 }
528 528
529 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);529 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
@@ -570,7 +570,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) · 40 unmodified lines
570 &imx6_suspend,570 &imx6_suspend,
571 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));571 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
572 572
573 goto put_node;573 goto put_device;
574 574
575pl310_cache_map_failed:575pl310_cache_map_failed:
576 iounmap(pm_info->gpc_base.vbase);576 iounmap(pm_info->gpc_base.vbase);
@@ -580,6 +580,8 @@ iomuxc_map_failed: · 3 unmodified lines
580 iounmap(pm_info->src_base.vbase);580 iounmap(pm_info->src_base.vbase);
581src_map_failed:581src_map_failed:
582 iounmap(pm_info->mmdc_base.vbase);582 iounmap(pm_info->mmdc_base.vbase);
583put_device:
584 put_device(&pdev->dev);
583put_node:585put_node:
584 of_node_put(node);586 of_node_put(node);
585 587
arch/arm/mach-sti/board-dt.c+0−9
@@ -20,14 +20,6 @@ static const char *const stih41x_dt_match[] __initconst = { · 19 unmodified lines
20 NULL20 NULL
21};21};
22 22
23static void sti_l2_write_sec(unsigned long val, unsigned reg)
24{
25 /*
26 * We can't write to secure registers as we are in non-secure
27 * mode, until we have some SMI service available.
28 */
29}
30
31DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")23DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
32 .dt_compat = stih41x_dt_match,24 .dt_compat = stih41x_dt_match,
33 .l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE |25 .l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE |
@@ -36,5 +28,4 @@ DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree") · 2 unmodified lines
36 L2C_AUX_CTRL_WAY_SIZE(4),28 L2C_AUX_CTRL_WAY_SIZE(4),
37 .l2c_aux_mask = 0xc0000fff,29 .l2c_aux_mask = 0xc0000fff,
38 .smp = smp_ops(sti_smp_ops),30 .smp = smp_ops(sti_smp_ops),
39 .l2c_write_sec = sti_l2_write_sec,
40MACHINE_END31MACHINE_END
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi+2−2
@@ -136,7 +136,7 @@ · 135 unmodified lines
136 136
137 ldo1_reg: LDO1 {137 ldo1_reg: LDO1 {
138 regulator-name = "LDO1";138 regulator-name = "LDO1";
139 regulator-min-microvolt = <3000000>;139 regulator-min-microvolt = <1600000>;
140 regulator-max-microvolt = <3300000>;140 regulator-max-microvolt = <3300000>;
141 regulator-boot-on;141 regulator-boot-on;
142 regulator-always-on;142 regulator-always-on;
@@ -144,7 +144,7 @@ · 1 unmodified line
144 144
145 ldo2_reg: LDO2 {145 ldo2_reg: LDO2 {
146 regulator-name = "LDO2";146 regulator-name = "LDO2";
147 regulator-min-microvolt = <900000>;147 regulator-min-microvolt = <800000>;
148 regulator-max-microvolt = <900000>;148 regulator-max-microvolt = <900000>;
149 regulator-boot-on;149 regulator-boot-on;
150 regulator-always-on;150 regulator-always-on;
arch/arm64/boot/dts/freescale/imx8mm-evk.dts+2−2
@@ -208,7 +208,7 @@ · 207 unmodified lines
208 208
209 ldo1_reg: LDO1 {209 ldo1_reg: LDO1 {
210 regulator-name = "LDO1";210 regulator-name = "LDO1";
211 regulator-min-microvolt = <3000000>;211 regulator-min-microvolt = <1600000>;
212 regulator-max-microvolt = <3300000>;212 regulator-max-microvolt = <3300000>;
213 regulator-boot-on;213 regulator-boot-on;
214 regulator-always-on;214 regulator-always-on;
@@ -216,7 +216,7 @@ · 1 unmodified line
216 216
217 ldo2_reg: LDO2 {217 ldo2_reg: LDO2 {
218 regulator-name = "LDO2";218 regulator-name = "LDO2";
219 regulator-min-microvolt = <900000>;219 regulator-min-microvolt = <800000>;
220 regulator-max-microvolt = <900000>;220 regulator-max-microvolt = <900000>;
221 regulator-boot-on;221 regulator-boot-on;
222 regulator-always-on;222 regulator-always-on;
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts+2−2
@@ -113,7 +113,7 @@ · 112 unmodified lines
113 113
114 ldo1_reg: LDO1 {114 ldo1_reg: LDO1 {
115 regulator-name = "LDO1";115 regulator-name = "LDO1";
116 regulator-min-microvolt = <3000000>;116 regulator-min-microvolt = <1600000>;
117 regulator-max-microvolt = <3300000>;117 regulator-max-microvolt = <3300000>;
118 regulator-boot-on;118 regulator-boot-on;
119 regulator-always-on;119 regulator-always-on;
@@ -121,7 +121,7 @@ · 1 unmodified line
121 121
122 ldo2_reg: LDO2 {122 ldo2_reg: LDO2 {
123 regulator-name = "LDO2";123 regulator-name = "LDO2";
124 regulator-min-microvolt = <900000>;124 regulator-min-microvolt = <800000>;
125 regulator-max-microvolt = <900000>;125 regulator-max-microvolt = <900000>;
126 regulator-boot-on;126 regulator-boot-on;
127 regulator-always-on;127 regulator-always-on;
drivers/firmware/raspberrypi.c+4−1
@@ -181,6 +181,7 @@ EXPORT_SYMBOL_GPL(rpi_firmware_property); · 180 unmodified lines
181static void181static void
182rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)182rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)
183{183{
184 time64_t date_and_time;
184 u32 packet;185 u32 packet;
185 int ret = rpi_firmware_property(fw,186 int ret = rpi_firmware_property(fw,
186 RPI_FIRMWARE_GET_FIRMWARE_REVISION,187 RPI_FIRMWARE_GET_FIRMWARE_REVISION,
@@ -189,7 +190,9 @@ rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) · 2 unmodified lines
189 if (ret)190 if (ret)
190 return;191 return;
191 192
192 dev_info(fw->cl.dev, "Attached to firmware from %ptT\n", &packet);193 /* This is not compatible with y2038 */
194 date_and_time = packet;
195 dev_info(fw->cl.dev, "Attached to firmware from %ptT\n", &date_and_time);
193}196}
194 197
195static void198static void
drivers/soc/imx/soc-imx8m.c+7−3
@@ -22,6 +22,8 @@ · 21 unmodified lines
22#define OCOTP_UID_LOW 0x41022#define OCOTP_UID_LOW 0x410
23#define OCOTP_UID_HIGH 0x42023#define OCOTP_UID_HIGH 0x420
24 24
25#define IMX8MP_OCOTP_UID_OFFSET 0x10
26
25/* Same as ANADIG_DIGPROG_IMX7D */27/* Same as ANADIG_DIGPROG_IMX7D */
26#define ANADIG_DIGPROG_IMX8MM 0x80028#define ANADIG_DIGPROG_IMX8MM 0x800
27 29
@@ -87,6 +89,8 @@ static void __init imx8mm_soc_uid(void) · 59 unmodified lines
87{89{
88 void __iomem *ocotp_base;90 void __iomem *ocotp_base;
89 struct device_node *np;91 struct device_node *np;
92 u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
93 IMX8MP_OCOTP_UID_OFFSET : 0;
90 94
91 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");95 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
92 if (!np)96 if (!np)
@@ -95,9 +99,9 @@ static void __init imx8mm_soc_uid(void) · 2 unmodified lines
95 ocotp_base = of_iomap(np, 0);99 ocotp_base = of_iomap(np, 0);
96 WARN_ON(!ocotp_base);100 WARN_ON(!ocotp_base);
97 101
98 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);102 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
99 soc_uid <<= 32;103 soc_uid <<= 32;
100 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);104 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
101 105
102 iounmap(ocotp_base);106 iounmap(ocotp_base);
103 of_node_put(np);107 of_node_put(np);
@@ -146,7 +150,7 @@ static const struct imx8_soc_data imx8mp_soc_data = { · 42 unmodified lines
146 .soc_revision = imx8mm_soc_revision,150 .soc_revision = imx8mm_soc_revision,
147};151};
148 152
149static const struct of_device_id imx8_soc_match[] = {153static __maybe_unused const struct of_device_id imx8_soc_match[] = {
150 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },154 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
151 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },155 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
152 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },156 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },

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