History

Merge tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC udpates from Vineet Gupta: - updates for various platforms - boot log updates for upcoming HS48 family of cores (dual issue) * tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz ARC: fix allnoconfig build warning ARCv2: boot log: identify HS48 cores (dual issue) ARC: boot log: decontaminate ARCv2 ISA_CONFIG register arc: remove redundant UTS_MACHINE define in arch/arc/Makefile ARC: [plat-eznps] Update platform maintainer as Noam left ARC: [plat-hsdk] use actual clk driver to manage cpu clk ARC: [*defconfig] Reenable soft lock-up detector ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency ARC: [plat-axs103] Add temporary quirk to reset ethernet IP

Linus Torvalds committed 9 years ago

Commit ed0f72f2 parents eab26ad ab8eb7d17 files · +130 −28Browse files

Unified · Split

17 files
  1. MAINTAINERS +2 −1
  2. arch/arc/Kconfig +1 −1
  3. arch/arc/Makefile +0 −2
  4. arch/arc/boot/dts/axs10x_mb.dtsi +8 −1
  5. arch/arc/boot/dts/hsdk.dts +29 −3
  6. arch/arc/configs/axs101_defconfig +1 −1
  7. arch/arc/configs/axs103_defconfig +1 −1
  8. arch/arc/configs/axs103_smp_defconfig +1 −1
  9. arch/arc/configs/haps_hs_smp_defconfig +1 −1
  10. arch/arc/configs/hsdk_defconfig +2 −1
  11. arch/arc/configs/vdk_hs38_defconfig +1 −1
  12. arch/arc/configs/vdk_hs38_smp_defconfig +1 −1
  13. arch/arc/include/asm/arcregs.h +6 −5
  14. arch/arc/kernel/setup.c +25 −7
  15. arch/arc/plat-axs10x/axs10x.c +7 −0
  16. arch/arc/plat-hsdk/Kconfig +2 −1
  17. arch/arc/plat-hsdk/platform.c +42 −0
MAINTAINERS+2−1
@@ -5259,7 +5259,8 @@ S: Maintained · 5258 unmodified lines
52595259 F: drivers/iommu/exynos-iommu.c
52605260
52615261 EZchip NPS platform support
5262−M: Noam Camus <noamc@ezchip.com>
5262+M: Elad Kanfi <eladkan@mellanox.com>
5263+M: Vineet Gupta <vgupta@synopsys.com>
52635264 S: Supported
52645265 F: arch/arc/plat-eznps
52655266 F: arch/arc/boot/dts/eznps.dts
arch/arc/Kconfig+1−1
@@ -24,7 +24,7 @@ config ARC · 23 unmodified lines
2424 select GENERIC_SMP_IDLE_THREAD
2525 select HAVE_ARCH_KGDB
2626 select HAVE_ARCH_TRACEHOOK
27− select HAVE_FUTEX_CMPXCHG
27+ select HAVE_FUTEX_CMPXCHG if FUTEX
2828 select HAVE_IOREMAP_PROT
2929 select HAVE_KPROBES
3030 select HAVE_KRETPROBES
arch/arc/Makefile+0−2
@@ -6,8 +6,6 @@ · 5 unmodified lines
66 # published by the Free Software Foundation.
77 #
88
9−UTS_MACHINE := arc
10−
119 ifeq ($(CROSS_COMPILE),)
1210 ifndef CONFIG_CPU_BIG_ENDIAN
1311 CROSS_COMPILE := arc-linux-
arch/arc/boot/dts/axs10x_mb.dtsi+8−1
@@ -44,7 +44,14 @@ · 43 unmodified lines
4444
4545 mmcclk: mmcclk {
4646 compatible = "fixed-clock";
47− clock-frequency = <50000000>;
47+ /*
48+ * DW sdio controller has external ciu clock divider
49+ * controlled via register in SDIO IP. It divides
50+ * sdio_ref_clk (which comes from CGU) by 16 for
51+ * default. So default mmcclk clock (which comes
52+ * to sdk_in) is 25000000 Hz.
53+ */
54+ clock-frequency = <25000000>;
4855 #clock-cells = <0>;
4956 };
5057
arch/arc/boot/dts/hsdk.dts+29−3
@@ -12,6 +12,7 @@ · 11 unmodified lines
1212 /dts-v1/;
1313
1414 #include <dt-bindings/net/ti-dp83867.h>
15+#include <dt-bindings/reset/snps,hsdk-reset.h>
1516
1617 / {
1718 model = "snps,hsdk";
@@ -57,10 +58,10 @@ · 39 unmodified lines
5758 };
5859 };
5960
60− core_clk: core-clk {
61+ input_clk: input-clk {
6162 #clock-cells = <0>;
6263 compatible = "fixed-clock";
63− clock-frequency = <500000000>;
64+ clock-frequency = <33333333>;
6465 };
6566
6667 cpu_intc: cpu-interrupt-controller {
@@ -102,6 +103,19 @@ · 35 unmodified lines
102103
103104 ranges = <0x00000000 0xf0000000 0x10000000>;
104105
106+ cgu_rst: reset-controller@8a0 {
107+ compatible = "snps,hsdk-reset";
108+ #reset-cells = <1>;
109+ reg = <0x8A0 0x4>, <0xFF0 0x4>;
110+ };
111+
112+ core_clk: core-clk@0 {
113+ compatible = "snps,hsdk-core-pll-clock";
114+ reg = <0x00 0x10>, <0x14B8 0x4>;
115+ #clock-cells = <0>;
116+ clocks = <&input_clk>;
117+ };
118+
105119 serial: serial@5000 {
106120 compatible = "snps,dw-apb-uart";
107121 reg = <0x5000 0x100>;
@@ -120,7 +134,17 @@ · 12 unmodified lines
120134
121135 mmcclk_ciu: mmcclk-ciu {
122136 compatible = "fixed-clock";
123− clock-frequency = <100000000>;
137+ /*
138+ * DW sdio controller has external ciu clock divider
139+ * controlled via register in SDIO IP. Due to its
140+ * unexpected default value (it should devide by 1
141+ * but it devides by 8) SDIO IP uses wrong clock and
142+ * works unstable (see STAR 9001204800)
143+ * So add temporary fix and change clock frequency
144+ * from 100000000 to 12500000 Hz until we fix dw sdio
145+ * driver itself.
146+ */
147+ clock-frequency = <12500000>;
124148 #clock-cells = <0>;
125149 };
126150
@@ -141,6 +165,8 @@ · 14 unmodified lines
141165 clocks = <&gmacclk>;
142166 clock-names = "stmmaceth";
143167 phy-handle = <&phy0>;
168+ resets = <&cgu_rst HSDK_ETH_RESET>;
169+ reset-names = "stmmaceth";
144170
145171 mdio {
146172 #address-cells = <1>;
arch/arc/configs/axs101_defconfig+1−1
@@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y · 104 unmodified lines
105105 # CONFIG_ENABLE_WARN_DEPRECATED is not set
106106 # CONFIG_ENABLE_MUST_CHECK is not set
107107 CONFIG_STRIP_ASM_SYMS=y
108−CONFIG_LOCKUP_DETECTOR=y
108+CONFIG_SOFTLOCKUP_DETECTOR=y
109109 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
110110 # CONFIG_SCHED_DEBUG is not set
111111 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/axs103_defconfig+1−1
@@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y · 103 unmodified lines
104104 # CONFIG_ENABLE_WARN_DEPRECATED is not set
105105 # CONFIG_ENABLE_MUST_CHECK is not set
106106 CONFIG_STRIP_ASM_SYMS=y
107−CONFIG_LOCKUP_DETECTOR=y
107+CONFIG_SOFTLOCKUP_DETECTOR=y
108108 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
109109 # CONFIG_SCHED_DEBUG is not set
110110 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/axs103_smp_defconfig+1−1
@@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y · 106 unmodified lines
107107 # CONFIG_ENABLE_WARN_DEPRECATED is not set
108108 # CONFIG_ENABLE_MUST_CHECK is not set
109109 CONFIG_STRIP_ASM_SYMS=y
110−CONFIG_LOCKUP_DETECTOR=y
110+CONFIG_SOFTLOCKUP_DETECTOR=y
111111 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
112112 # CONFIG_SCHED_DEBUG is not set
113113 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/haps_hs_smp_defconfig+1−1
@@ -84,5 +84,5 @@ CONFIG_TMPFS=y · 83 unmodified lines
8484 CONFIG_NFS_FS=y
8585 # CONFIG_ENABLE_WARN_DEPRECATED is not set
8686 # CONFIG_ENABLE_MUST_CHECK is not set
87−CONFIG_LOCKUP_DETECTOR=y
87+CONFIG_SOFTLOCKUP_DETECTOR=y
8888 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/hsdk_defconfig+2−1
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y · 62 unmodified lines
6363 CONFIG_MMC_SDHCI_PLTFM=y
6464 CONFIG_MMC_DW=y
6565 # CONFIG_IOMMU_SUPPORT is not set
66+CONFIG_RESET_HSDK=y
6667 CONFIG_EXT3_FS=y
6768 CONFIG_VFAT_FS=y
6869 CONFIG_TMPFS=y
@@ -72,7 +73,7 @@ CONFIG_NLS_ISO8859_1=y · 3 unmodified lines
7273 # CONFIG_ENABLE_WARN_DEPRECATED is not set
7374 # CONFIG_ENABLE_MUST_CHECK is not set
7475 CONFIG_STRIP_ASM_SYMS=y
75−CONFIG_LOCKUP_DETECTOR=y
76+CONFIG_SOFTLOCKUP_DETECTOR=y
7677 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
7778 # CONFIG_SCHED_DEBUG is not set
7879 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/vdk_hs38_defconfig+1−1
@@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y · 93 unmodified lines
9494 # CONFIG_ENABLE_MUST_CHECK is not set
9595 CONFIG_STRIP_ASM_SYMS=y
9696 CONFIG_DEBUG_SHIRQ=y
97−CONFIG_LOCKUP_DETECTOR=y
97+CONFIG_SOFTLOCKUP_DETECTOR=y
9898 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
9999 # CONFIG_SCHED_DEBUG is not set
100100 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/configs/vdk_hs38_smp_defconfig+1−1
@@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y · 97 unmodified lines
9898 # CONFIG_ENABLE_MUST_CHECK is not set
9999 CONFIG_STRIP_ASM_SYMS=y
100100 CONFIG_DEBUG_SHIRQ=y
101−CONFIG_LOCKUP_DETECTOR=y
101+CONFIG_SOFTLOCKUP_DETECTOR=y
102102 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
103103 # CONFIG_SCHED_DEBUG is not set
104104 # CONFIG_DEBUG_PREEMPT is not set
arch/arc/include/asm/arcregs.h+6−5
@@ -98,6 +98,7 @@ · 97 unmodified lines
9898
9999 /* Auxiliary registers */
100100 #define AUX_IDENTITY 4
101+#define AUX_EXEC_CTRL 8
101102 #define AUX_INTR_VEC_BASE 0x25
102103 #define AUX_VOL 0x5e
103104
@@ -135,12 +136,12 @@ struct bcr_identity { · 31 unmodified lines
135136 #endif
136137 };
137138
138−struct bcr_isa {
139+struct bcr_isa_arcv2 {
139140 #ifdef CONFIG_CPU_BIG_ENDIAN
140141 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
141− pad1:11, atomic1:1, ver:8;
142+ pad1:12, ver:8;
142143 #else
143− unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
144+ unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
144145 ldd:1, pad2:4, div_rem:4;
145146 #endif
146147 };
@@ -263,13 +264,13 @@ struct cpuinfo_arc { · 116 unmodified lines
263264 struct cpuinfo_arc_mmu mmu;
264265 struct cpuinfo_arc_bpu bpu;
265266 struct bcr_identity core;
266− struct bcr_isa isa;
267+ struct bcr_isa_arcv2 isa;
267268 const char *details, *name;
268269 unsigned int vec_base;
269270 struct cpuinfo_arc_ccm iccm, dccm;
270271 struct {
271272 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
272− fpu_sp:1, fpu_dp:1, pad2:6,
273+ fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
273274 debug:1, ap:1, smart:1, rtt:1, pad3:4,
274275 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
275276 } extn;
arch/arc/kernel/setup.c+25−7
@@ -51,6 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = { · 50 unmodified lines
5151 { 0x51, "R2.0" },
5252 { 0x52, "R2.1" },
5353 { 0x53, "R3.0" },
54+ { 0x54, "R4.0" },
5455 #endif
5556 { 0x00, NULL }
5657 };
@@ -62,6 +63,7 @@ static const struct id_to_str arc_cpu_nm[] = { · 5 unmodified lines
6263 #else
6364 { 0x40, "ARC EM" },
6465 { 0x50, "ARC HS38" },
66+ { 0x54, "ARC HS48" },
6567 #endif
6668 { 0x00, "Unknown" }
6769 };
@@ -119,11 +121,11 @@ static void read_arc_build_cfg_regs(void) · 51 unmodified lines
119121 struct bcr_generic bcr;
120122 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
121123 const struct id_to_str *tbl;
124+ struct bcr_isa_arcv2 isa;
122125
123126 FIX_PTR(cpu);
124127
125128 READ_BCR(AUX_IDENTITY, cpu->core);
126− READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
127129
128130 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
129131 if (cpu->core.family == tbl->id) {
@@ -133,7 +135,7 @@ static void read_arc_build_cfg_regs(void) · 3 unmodified lines
133135 }
134136
135137 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
136− if ((cpu->core.family & 0xF0) == tbl->id)
138+ if ((cpu->core.family & 0xF4) == tbl->id)
137139 break;
138140 }
139141 cpu->name = tbl->str;
@@ -192,6 +194,14 @@ static void read_arc_build_cfg_regs(void) · 52 unmodified lines
192194 cpu->bpu.full = bpu.ft;
193195 cpu->bpu.num_cache = 256 << bpu.bce;
194196 cpu->bpu.num_pred = 2048 << bpu.pte;
197+
198+ if (cpu->core.family >= 0x54) {
199+ unsigned int exec_ctrl;
200+
201+ READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
202+ cpu->extn.dual_iss_exist = 1;
203+ cpu->extn.dual_iss_enb = exec_ctrl & 1;
204+ }
195205 }
196206
197207 READ_BCR(ARC_REG_AP_BCR, bcr);
@@ -205,18 +215,25 @@ static void read_arc_build_cfg_regs(void) · 7 unmodified lines
205215
206216 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
207217
218+ READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
219+
208220 /* some hacks for lack of feature BCR info in old ARC700 cores */
209221 if (is_isa_arcompact()) {
210− if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
222+ if (!isa.ver) /* ISA BCR absent, use Kconfig info */
211223 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
212− else
213− cpu->isa.atomic = cpu->isa.atomic1;
224+ else {
225+ /* ARC700_BUILD only has 2 bits of isa info */
226+ struct bcr_generic bcr = *(struct bcr_generic *)&isa;
227+ cpu->isa.atomic = bcr.info & 1;
228+ }
214229
215230 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
216231
217232 /* there's no direct way to distinguish 750 vs. 770 */
218233 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
219234 cpu->name = "ARC750";
235+ } else {
236+ cpu->isa = isa;
220237 }
221238 }
222239
@@ -232,10 +249,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) · 9 unmodified lines
232249 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
233250 core->family, core->cpu_id, core->chip_id);
234251
235− n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
252+ n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
236253 cpu_id, cpu->name, cpu->details,
237254 is_isa_arcompact() ? "ARCompact" : "ARCv2",
238− IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
255+ IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
256+ IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
239257
240258 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
241259 IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
arch/arc/plat-axs10x/axs10x.c+7−0
@@ -111,6 +111,13 @@ static void __init axs10x_early_init(void) · 110 unmodified lines
111111
112112 axs10x_enable_gpio_intc_wire();
113113
114+ /*
115+ * Reset ethernet IP core.
116+ * TODO: get rid of this quirk after axs10x reset driver (or simple
117+ * reset driver) will be available in upstream.
118+ */
119+ iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
120+
114121 scnprintf(mb, 32, "MainBoard v%d", mb_rev);
115122 axs10x_print_board_ver(CREG_MB_VER, mb);
116123 }
arch/arc/plat-hsdk/Kconfig+2−1
@@ -6,4 +6,5 @@ · 5 unmodified lines
66 #
77
88 menuconfig ARC_SOC_HSDK
9− bool "ARC HS Development Kit SOC"
9+ bool "ARC HS Development Kit SOC"
10+ select CLK_HSDK
arch/arc/plat-hsdk/platform.c+42−0
@@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu) · 37 unmodified lines
3838 #define CREG_PAE (CREG_BASE + 0x180)
3939 #define CREG_PAE_UPDATE (CREG_BASE + 0x194)
4040
41+#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
42+#define CREG_CORE_IF_CLK_DIV_2 0x1
43+#define CGU_BASE ARC_PERIPHERAL_BASE
44+#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
45+#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
46+#define CGU_PLL_STATUS_LOCK BIT(0)
47+#define CGU_PLL_STATUS_ERR BIT(1)
48+#define CGU_PLL_CTRL_1GHZ 0x3A10
49+#define HSDK_PLL_LOCK_TIMEOUT 500
50+
51+#define HSDK_PLL_LOCKED() \
52+ !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
53+
54+#define HSDK_PLL_ERR() \
55+ !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
56+
57+static void __init hsdk_set_cpu_freq_1ghz(void)
58+{
59+ u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
60+
61+ /*
62+ * As we set cpu clock which exceeds 500MHz, the divider for the interface
63+ * clock must be programmed to div-by-2.
64+ */
65+ iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
66+
67+ /* Set cpu clock to 1GHz */
68+ iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
69+
70+ while (!HSDK_PLL_LOCKED() && timeout--)
71+ cpu_relax();
72+
73+ if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
74+ pr_err("Failed to setup CPU frequency to 1GHz!");
75+}
76+
4177 static void __init hsdk_init_early(void)
4278 {
4379 /*
@@ -52,6 +88,12 @@ static void __init hsdk_init_early(void) · 8 unmodified lines
5288
5389 /* Really apply settings made above */
5490 writel(1, (void __iomem *) CREG_PAE_UPDATE);
91+
92+ /*
93+ * Setup CPU frequency to 1GHz.
94+ * TODO: remove it after smart hsdk pll driver will be introduced.
95+ */
96+ hsdk_set_cpu_freq_1ghz();
5597 }
5698
5799 static const char *hsdk_compat[] __initconst = {

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