History

Merge tag 'drm-intel-next-fixes-2018-10-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Fix GPU hang on MacBook2,1 when booting in EFI mode (Bugzilla #105637) - Fix garbled console on Y tiled BIOS framebuffer configs (Bugzilla #108264) - Fix black screen on certain eDP panels eg. Dell XPS 9350 (Bugzilla #107489 and #105338) - MST fixes that Rodrigo dropped from drm-intel-fixes and bunch of Icelake fixes - Then assorted proactive code fixes caught by CI or developers

Dave Airlie committed 8 years ago

Commit f2bfc712 parents c13bbf4 835fe6d12 files · +227 −104Browse files

Unified · Split

12 files
  1. drivers/gpu/drm/i915/i915_debugfs.c +1 −1
  2. drivers/gpu/drm/i915/i915_gem.c +2 −10
  3. drivers/gpu/drm/i915/i915_reg.h +3 −0
  4. drivers/gpu/drm/i915/intel_csr.c +1 −0
  5. drivers/gpu/drm/i915/intel_ddi.c +26 −10
  6. drivers/gpu/drm/i915/intel_display.c +107 −44
  7. drivers/gpu/drm/i915/intel_dp.c +31 −1
  8. drivers/gpu/drm/i915/intel_dp_link_training.c +9 −17
  9. drivers/gpu/drm/i915/intel_dp_mst.c +20 −21
  10. drivers/gpu/drm/i915/intel_drv.h +2 −0
  11. drivers/gpu/drm/i915/intel_sprite.c +22 −0
  12. drivers/gpu/drm/i915/selftests/i915_gem_object.c +3 −0
drivers/gpu/drm/i915/i915_debugfs.c+1−1
@@ -4189,7 +4189,7 @@ i915_drop_caches_set(void *data, u64 val) · 4188 unmodified lines
4189 I915_WAIT_LOCKED,4189 I915_WAIT_LOCKED,
4190 MAX_SCHEDULE_TIMEOUT);4190 MAX_SCHEDULE_TIMEOUT);
4191 4191
4192 if (val & DROP_RESET_SEQNO) {4192 if (ret == 0 && val & DROP_RESET_SEQNO) {
4193 intel_runtime_pm_get(i915);4193 intel_runtime_pm_get(i915);
4194 ret = i915_gem_set_global_seqno(&i915->drm, 1);4194 ret = i915_gem_set_global_seqno(&i915->drm, 1);
4195 intel_runtime_pm_put(i915);4195 intel_runtime_pm_put(i915);
drivers/gpu/drm/i915/i915_gem.c+2−10
@@ -1127,11 +1127,7 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, · 1126 unmodified lines
1127 offset = offset_in_page(args->offset);1127 offset = offset_in_page(args->offset);
1128 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {1128 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1129 struct page *page = i915_gem_object_get_page(obj, idx);1129 struct page *page = i915_gem_object_get_page(obj, idx);
1130 int length;1130 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
1131
1132 length = remain;
1133 if (offset + length > PAGE_SIZE)
1134 length = PAGE_SIZE - offset;
1135 1131
1136 ret = shmem_pread(page, offset, length, user_data,1132 ret = shmem_pread(page, offset, length, user_data,
1137 page_to_phys(page) & obj_do_bit17_swizzling,1133 page_to_phys(page) & obj_do_bit17_swizzling,
@@ -1575,11 +1571,7 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, · 437 unmodified lines
1575 offset = offset_in_page(args->offset);1571 offset = offset_in_page(args->offset);
1576 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {1572 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1577 struct page *page = i915_gem_object_get_page(obj, idx);1573 struct page *page = i915_gem_object_get_page(obj, idx);
1578 int length;1574 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
1579
1580 length = remain;
1581 if (offset + length > PAGE_SIZE)
1582 length = PAGE_SIZE - offset;
1583 1575
1584 ret = shmem_pwrite(page, offset, length, user_data,1576 ret = shmem_pwrite(page, offset, length, user_data,
1585 page_to_phys(page) & obj_do_bit17_swizzling,1577 page_to_phys(page) & obj_do_bit17_swizzling,
drivers/gpu/drm/i915/i915_reg.h+3−0
@@ -9339,6 +9339,9 @@ enum skl_power_gate { · 9338 unmodified lines
9339#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)9339#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
9340#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \9340#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9341 (port) + 10))9341 (port) + 10))
9342#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
9343#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
9344 21 : (tc_port) + 12))
9342#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \9345#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9343 (port) * 2)9346 (port) * 2)
9344#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))9347#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
drivers/gpu/drm/i915/intel_csr.c+1−0
@@ -35,6 +35,7 @@ · 34 unmodified lines
35 */35 */
36 36
37#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"37#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
38MODULE_FIRMWARE(I915_CSR_ICL);
38#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)39#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
39 40
40#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"41#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
drivers/gpu/drm/i915/intel_ddi.c+26−10
@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por · 915 unmodified lines
916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
917 917
918 if (IS_ICELAKE(dev_priv)) {918 if (IS_ICELAKE(dev_priv)) {
919 if (port == PORT_A || port == PORT_B)919 if (intel_port_is_combophy(dev_priv, port))
920 icl_get_combo_buf_trans(dev_priv, port,920 icl_get_combo_buf_trans(dev_priv, port,
921 INTEL_OUTPUT_HDMI, &n_entries);921 INTEL_OUTPUT_HDMI, &n_entries);
922 else922 else
@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, · 612 unmodified lines
1535 uint32_t pll_id;1535 uint32_t pll_id;
1536 1536
1537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);1537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538 if (port == PORT_A || port == PORT_B) {1538 if (intel_port_is_combophy(dev_priv, port)) {
1539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))1539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);1540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541 else1541 else
@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) · 693 unmodified lines
2235 int n_entries;2235 int n_entries;
2236 2236
2237 if (IS_ICELAKE(dev_priv)) {2237 if (IS_ICELAKE(dev_priv)) {
2238 if (port == PORT_A || port == PORT_B)2238 if (intel_port_is_combophy(dev_priv, port))
2239 icl_get_combo_buf_trans(dev_priv, port, encoder->type,2239 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2240 &n_entries);2240 &n_entries);
2241 else2241 else
@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, · 427 unmodified lines
2669 u32 level,2669 u32 level,
2670 enum intel_output_type type)2670 enum intel_output_type type)
2671{2671{
2672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2672 enum port port = encoder->port;2673 enum port port = encoder->port;
2673 2674
2674 if (port == PORT_A || port == PORT_B)2675 if (intel_port_is_combophy(dev_priv, port))
2675 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);2676 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2676 else2677 else
2677 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);2678 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2732,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) · 54 unmodified lines
2732 return DDI_BUF_TRANS_SELECT(level);2733 return DDI_BUF_TRANS_SELECT(level);
2733}2734}
2734 2735
2736static inline
2737uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2738 enum port port)
2739{
2740 if (intel_port_is_combophy(dev_priv, port)) {
2741 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2742 } else if (intel_port_is_tc(dev_priv, port)) {
2743 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2744
2745 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2746 }
2747
2748 return 0;
2749}
2750
2735void icl_map_plls_to_ports(struct drm_crtc *crtc,2751void icl_map_plls_to_ports(struct drm_crtc *crtc,
2736 struct intel_crtc_state *crtc_state,2752 struct intel_crtc_state *crtc_state,
2737 struct drm_atomic_state *old_state)2753 struct drm_atomic_state *old_state)
@@ -2755,16 +2771,16 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc, · 17 unmodified lines
2755 mutex_lock(&dev_priv->dpll_lock);2771 mutex_lock(&dev_priv->dpll_lock);
2756 2772
2757 val = I915_READ(DPCLKA_CFGCR0_ICL);2773 val = I915_READ(DPCLKA_CFGCR0_ICL);
2758 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);2774 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2759 2775
2760 if (port == PORT_A || port == PORT_B) {2776 if (intel_port_is_combophy(dev_priv, port)) {
2761 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);2777 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2762 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);2778 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2763 I915_WRITE(DPCLKA_CFGCR0_ICL, val);2779 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2764 POSTING_READ(DPCLKA_CFGCR0_ICL);2780 POSTING_READ(DPCLKA_CFGCR0_ICL);
2765 }2781 }
2766 2782
2767 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);2783 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2768 I915_WRITE(DPCLKA_CFGCR0_ICL, val);2784 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2769 2785
2770 mutex_unlock(&dev_priv->dpll_lock);2786 mutex_unlock(&dev_priv->dpll_lock);
@@ -2792,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc, · 21 unmodified lines
2792 mutex_lock(&dev_priv->dpll_lock);2808 mutex_lock(&dev_priv->dpll_lock);
2793 I915_WRITE(DPCLKA_CFGCR0_ICL,2809 I915_WRITE(DPCLKA_CFGCR0_ICL,
2794 I915_READ(DPCLKA_CFGCR0_ICL) |2810 I915_READ(DPCLKA_CFGCR0_ICL) |
2795 DPCLKA_CFGCR0_DDI_CLK_OFF(port));2811 icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2796 mutex_unlock(&dev_priv->dpll_lock);2812 mutex_unlock(&dev_priv->dpll_lock);
2797 }2813 }
2798}2814}
@@ -2810,7 +2826,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 11 unmodified lines
2810 mutex_lock(&dev_priv->dpll_lock);2826 mutex_lock(&dev_priv->dpll_lock);
2811 2827
2812 if (IS_ICELAKE(dev_priv)) {2828 if (IS_ICELAKE(dev_priv)) {
2813 if (port >= PORT_C)2829 if (!intel_port_is_combophy(dev_priv, port))
2814 I915_WRITE(DDI_CLK_SEL(port),2830 I915_WRITE(DDI_CLK_SEL(port),
2815 icl_pll_to_ddi_pll_sel(encoder, pll));2831 icl_pll_to_ddi_pll_sel(encoder, pll));
2816 } else if (IS_CANNONLAKE(dev_priv)) {2832 } else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2868,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) · 35 unmodified lines
2852 enum port port = encoder->port;2868 enum port port = encoder->port;
2853 2869
2854 if (IS_ICELAKE(dev_priv)) {2870 if (IS_ICELAKE(dev_priv)) {
2855 if (port >= PORT_C)2871 if (!intel_port_is_combophy(dev_priv, port))
2856 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);2872 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2857 } else if (IS_CANNONLAKE(dev_priv)) {2873 } else if (IS_CANNONLAKE(dev_priv)) {
2858 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |2874 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
drivers/gpu/drm/i915/intel_display.c+107−44
@@ -2722,6 +2722,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, · 2721 unmodified lines
2722 if (size_aligned * 2 > dev_priv->stolen_usable_size)2722 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2723 return false;2723 return false;
2724 2724
2725 switch (fb->modifier) {
2726 case DRM_FORMAT_MOD_LINEAR:
2727 case I915_FORMAT_MOD_X_TILED:
2728 case I915_FORMAT_MOD_Y_TILED:
2729 break;
2730 default:
2731 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2732 fb->modifier);
2733 return false;
2734 }
2735
2725 mutex_lock(&dev->struct_mutex);2736 mutex_lock(&dev->struct_mutex);
2726 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,2737 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2727 base_aligned,2738 base_aligned,
@@ -2731,8 +2742,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, · 3 unmodified lines
2731 if (!obj)2742 if (!obj)
2732 return false;2743 return false;
2733 2744
2734 if (plane_config->tiling == I915_TILING_X)2745 switch (plane_config->tiling) {
2735 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;2746 case I915_TILING_NONE:
2747 break;
2748 case I915_TILING_X:
2749 case I915_TILING_Y:
2750 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2751 break;
2752 default:
2753 MISSING_CASE(plane_config->tiling);
2754 return false;
2755 }
2736 2756
2737 mode_cmd.pixel_format = fb->format->format;2757 mode_cmd.pixel_format = fb->format->format;
2738 mode_cmd.width = fb->width;2758 mode_cmd.width = fb->width;
@@ -2764,20 +2784,33 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state, · 25 unmodified lines
2764 2784
2765 plane_state->base.visible = visible;2785 plane_state->base.visible = visible;
2766 2786
2767 /* FIXME pre-g4x don't work like this */2787 if (visible)
2768 if (visible) {
2769 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);2788 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2770 crtc_state->active_planes |= BIT(plane->id);2789 else
2771 } else {
2772 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);2790 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2773 crtc_state->active_planes &= ~BIT(plane->id);
2774 }
2775 2791
2776 DRM_DEBUG_KMS("%s active planes 0x%x\n",2792 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2777 crtc_state->base.crtc->name,2793 crtc_state->base.crtc->name,
2778 crtc_state->active_planes);2794 crtc_state->active_planes);
2779}2795}
2780 2796
2797static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2798{
2799 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2800 struct drm_plane *plane;
2801
2802 /*
2803 * Active_planes aliases if multiple "primary" or cursor planes
2804 * have been used on the same (or wrong) pipe. plane_mask uses
2805 * unique ids, hence we can use that to reconstruct active_planes.
2806 */
2807 crtc_state->active_planes = 0;
2808
2809 drm_for_each_plane_mask(plane, &dev_priv->drm,
2810 crtc_state->base.plane_mask)
2811 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2812}
2813
2781static void intel_plane_disable_noatomic(struct intel_crtc *crtc,2814static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2782 struct intel_plane *plane)2815 struct intel_plane *plane)
2783{2816{
@@ -2787,6 +2820,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc, · 3 unmodified lines
2787 to_intel_plane_state(plane->base.state);2820 to_intel_plane_state(plane->base.state);
2788 2821
2789 intel_set_plane_visible(crtc_state, plane_state, false);2822 intel_set_plane_visible(crtc_state, plane_state, false);
2823 fixup_active_planes(crtc_state);
2790 2824
2791 if (plane->id == PLANE_PRIMARY)2825 if (plane->id == PLANE_PRIMARY)
2792 intel_pre_disable_primary_noatomic(&crtc->base);2826 intel_pre_disable_primary_noatomic(&crtc->base);
@@ -2805,7 +2839,6 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, · 12 unmodified lines
2805 struct drm_i915_gem_object *obj;2839 struct drm_i915_gem_object *obj;
2806 struct drm_plane *primary = intel_crtc->base.primary;2840 struct drm_plane *primary = intel_crtc->base.primary;
2807 struct drm_plane_state *plane_state = primary->state;2841 struct drm_plane_state *plane_state = primary->state;
2808 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2809 struct intel_plane *intel_plane = to_intel_plane(primary);2842 struct intel_plane *intel_plane = to_intel_plane(primary);
2810 struct intel_plane_state *intel_state =2843 struct intel_plane_state *intel_state =
2811 to_intel_plane_state(plane_state);2844 to_intel_plane_state(plane_state);
@@ -2900,10 +2933,6 @@ valid_fb: · 88 unmodified lines
2900 plane_state->fb = fb;2933 plane_state->fb = fb;
2901 plane_state->crtc = &intel_crtc->base;2934 plane_state->crtc = &intel_crtc->base;
2902 2935
2903 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2904 to_intel_plane_state(plane_state),
2905 true);
2906
2907 atomic_or(to_intel_plane(primary)->frontbuffer_bit,2936 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2908 &obj->frontbuffer_bits);2937 &obj->frontbuffer_bits);
2909}2938}
@@ -3151,6 +3180,10 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) · 241 unmodified lines
3151 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);3180 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3152 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);3181 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3153 3182
3183 ret = intel_plane_check_stride(plane_state);
3184 if (ret)
3185 return ret;
3186
3154 if (!plane_state->base.visible)3187 if (!plane_state->base.visible)
3155 return 0;3188 return 0;
3156 3189
@@ -3286,10 +3319,15 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) · 129 unmodified lines
3286 int src_x = plane_state->base.src.x1 >> 16;3319 int src_x = plane_state->base.src.x1 >> 16;
3287 int src_y = plane_state->base.src.y1 >> 16;3320 int src_y = plane_state->base.src.y1 >> 16;
3288 u32 offset;3321 u32 offset;
3322 int ret;
3289 3323
3290 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);3324 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3291 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);3325 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3292 3326
3327 ret = intel_plane_check_stride(plane_state);
3328 if (ret)
3329 return ret;
3330
3293 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);3331 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3294 3332
3295 if (INTEL_GEN(dev_priv) >= 4)3333 if (INTEL_GEN(dev_priv) >= 4)
@@ -5923,6 +5961,17 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) · 2627 unmodified lines
5923 I915_WRITE(BCLRPAT(crtc->pipe), 0);5961 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5924}5962}
5925 5963
5964bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
5965{
5966 if (port == PORT_NONE)
5967 return false;
5968
5969 if (IS_ICELAKE(dev_priv))
5970 return port <= PORT_B;
5971
5972 return false;
5973}
5974
5926bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)5975bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
5927{5976{
5928 if (IS_ICELAKE(dev_priv))5977 if (IS_ICELAKE(dev_priv))
@@ -8847,6 +8896,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, · 2918 unmodified lines
8847 fb->modifier = I915_FORMAT_MOD_X_TILED;8896 fb->modifier = I915_FORMAT_MOD_X_TILED;
8848 break;8897 break;
8849 case PLANE_CTL_TILED_Y:8898 case PLANE_CTL_TILED_Y:
8899 plane_config->tiling = I915_TILING_Y;
8850 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)8900 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8851 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;8901 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8852 else8902 else
@@ -9683,10 +9733,15 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) · 830 unmodified lines
9683 unsigned int rotation = plane_state->base.rotation;9733 unsigned int rotation = plane_state->base.rotation;
9684 int src_x, src_y;9734 int src_x, src_y;
9685 u32 offset;9735 u32 offset;
9736 int ret;
9686 9737
9687 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);9738 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
9688 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);9739 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
9689 9740
9741 ret = intel_plane_check_stride(plane_state);
9742 if (ret)
9743 return ret;
9744
9690 src_x = plane_state->base.src_x >> 16;9745 src_x = plane_state->base.src_x >> 16;
9691 src_y = plane_state->base.src_y >> 16;9746 src_y = plane_state->base.src_y >> 16;
9692 9747
@@ -15436,17 +15491,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) · 5743 unmodified lines
15436 POSTING_READ(DPLL(pipe));15491 POSTING_READ(DPLL(pipe));
15437}15492}
15438 15493
15439static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15440 struct intel_plane *plane)
15441{
15442 enum pipe pipe;
15443
15444 if (!plane->get_hw_state(plane, &pipe))
15445 return true;
15446
15447 return pipe == crtc->pipe;
15448}
15449
15450static void15494static void
15451intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)15495intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15452{15496{
@@ -15458,13 +15502,20 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) · 5 unmodified lines
15458 for_each_intel_crtc(&dev_priv->drm, crtc) {15502 for_each_intel_crtc(&dev_priv->drm, crtc) {
15459 struct intel_plane *plane =15503 struct intel_plane *plane =
15460 to_intel_plane(crtc->base.primary);15504 to_intel_plane(crtc->base.primary);
15505 struct intel_crtc *plane_crtc;
15506 enum pipe pipe;
15461 15507
15462 if (intel_plane_mapping_ok(crtc, plane))15508 if (!plane->get_hw_state(plane, &pipe))
15509 continue;
15510
15511 if (pipe == crtc->pipe)
15463 continue;15512 continue;
15464 15513
15465 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",15514 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15466 plane->base.name);15515 plane->base.name);
15467 intel_plane_disable_noatomic(crtc, plane);15516
15517 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15518 intel_plane_disable_noatomic(plane_crtc, plane);
15468 }15519 }
15469}15520}
15470 15521
@@ -15512,13 +15563,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, · 41 unmodified lines
15512 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);15563 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15513 }15564 }
15514 15565
15515 /* restore vblank interrupts to correct state */
15516 drm_crtc_vblank_reset(&crtc->base);
15517 if (crtc->active) {15566 if (crtc->active) {
15518 struct intel_plane *plane;15567 struct intel_plane *plane;
15519 15568
15520 drm_crtc_vblank_on(&crtc->base);
15521
15522 /* Disable everything but the primary plane */15569 /* Disable everything but the primary plane */
15523 for_each_intel_plane_on_crtc(dev, crtc, plane) {15570 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15524 const struct intel_plane_state *plane_state =15571 const struct intel_plane_state *plane_state =
@@ -15636,23 +15683,32 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) · 111 unmodified lines
15636}15683}
15637 15684
15638/* FIXME read out full plane state for all planes */15685/* FIXME read out full plane state for all planes */
15639static void readout_plane_state(struct intel_crtc *crtc)15686static void readout_plane_state(struct drm_i915_private *dev_priv)
15640{15687{
15641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15642 struct intel_crtc_state *crtc_state =
15643 to_intel_crtc_state(crtc->base.state);
15644 struct intel_plane *plane;15688 struct intel_plane *plane;
15689 struct intel_crtc *crtc;
15645 15690
15646 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {15691 for_each_intel_plane(&dev_priv->drm, plane) {
15647 struct intel_plane_state *plane_state =15692 struct intel_plane_state *plane_state =
15648 to_intel_plane_state(plane->base.state);15693 to_intel_plane_state(plane->base.state);
15649 enum pipe pipe;15694 struct intel_crtc_state *crtc_state;
15695 enum pipe pipe = PIPE_A;
15650 bool visible;15696 bool visible;
15651 15697
15652 visible = plane->get_hw_state(plane, &pipe);15698 visible = plane->get_hw_state(plane, &pipe);
15653 15699
15700 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15701 crtc_state = to_intel_crtc_state(crtc->base.state);
15702
15654 intel_set_plane_visible(crtc_state, plane_state, visible);15703 intel_set_plane_visible(crtc_state, plane_state, visible);
15655 }15704 }
15705
15706 for_each_intel_crtc(&dev_priv->drm, crtc) {
15707 struct intel_crtc_state *crtc_state =
15708 to_intel_crtc_state(crtc->base.state);
15709
15710 fixup_active_planes(crtc_state);
15711 }
15656}15712}
15657 15713
15658static void intel_modeset_readout_hw_state(struct drm_device *dev)15714static void intel_modeset_readout_hw_state(struct drm_device *dev)
@@ -15684,13 +15740,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) · 25 unmodified lines
15684 if (crtc_state->base.active)15740 if (crtc_state->base.active)
15685 dev_priv->active_crtcs |= 1 << crtc->pipe;15741 dev_priv->active_crtcs |= 1 << crtc->pipe;
15686 15742
15687 readout_plane_state(crtc);
15688
15689 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",15743 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15690 crtc->base.base.id, crtc->base.name,15744 crtc->base.base.id, crtc->base.name,
15691 enableddisabled(crtc_state->base.active));15745 enableddisabled(crtc_state->base.active));
15692 }15746 }
15693 15747
15748 readout_plane_state(dev_priv);
15749
15694 for (i = 0; i < dev_priv->num_shared_dpll; i++) {15750 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15695 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];15751 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15696 15752
@@ -15860,7 +15916,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 163 unmodified lines
15860 struct drm_modeset_acquire_ctx *ctx)15916 struct drm_modeset_acquire_ctx *ctx)
15861{15917{
15862 struct drm_i915_private *dev_priv = to_i915(dev);15918 struct drm_i915_private *dev_priv = to_i915(dev);
15863 enum pipe pipe;
15864 struct intel_crtc *crtc;15919 struct intel_crtc *crtc;
15865 struct intel_encoder *encoder;15920 struct intel_encoder *encoder;
15866 int i;15921 int i;
@@ -15873,15 +15928,23 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 6 unmodified lines
15873 /* HW state is read out, now we need to sanitize this mess. */15928 /* HW state is read out, now we need to sanitize this mess. */
15874 get_encoder_power_domains(dev_priv);15929 get_encoder_power_domains(dev_priv);
15875 15930
15876 intel_sanitize_plane_mapping(dev_priv);15931 /*
15932 * intel_sanitize_plane_mapping() may need to do vblank
15933 * waits, so we need vblank interrupts restored beforehand.
15934 */
15935 for_each_intel_crtc(&dev_priv->drm, crtc) {
15936 drm_crtc_vblank_reset(&crtc->base);
15877 15937
15878 for_each_intel_encoder(dev, encoder) {15938 if (crtc->active)
15879 intel_sanitize_encoder(encoder);15939 drm_crtc_vblank_on(&crtc->base);
15880 }15940 }
15881 15941
15882 for_each_pipe(dev_priv, pipe) {15942 intel_sanitize_plane_mapping(dev_priv);
15883 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15884 15943
15944 for_each_intel_encoder(dev, encoder)
15945 intel_sanitize_encoder(encoder);
15946
15947 for_each_intel_crtc(&dev_priv->drm, crtc) {
15885 intel_sanitize_crtc(crtc, ctx);15948 intel_sanitize_crtc(crtc, ctx);
15886 intel_dump_pipe_config(crtc, crtc->config,15949 intel_dump_pipe_config(crtc, crtc->config,
15887 "[setup_hw_state]");15950 "[setup_hw_state]");
drivers/gpu/drm/i915/intel_dp.c+31−1
@@ -557,6 +557,22 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, · 556 unmodified lines
557 return true;557 return true;
558}558}
559 559
560static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
561 int link_rate,
562 uint8_t lane_count)
563{
564 const struct drm_display_mode *fixed_mode =
565 intel_dp->attached_connector->panel.fixed_mode;
566 int mode_rate, max_rate;
567
568 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
569 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
570 if (mode_rate > max_rate)
571 return false;
572
573 return true;
574}
575
560int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,576int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
561 int link_rate, uint8_t lane_count)577 int link_rate, uint8_t lane_count)
562{578{
@@ -566,9 +582,23 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, · 3 unmodified lines
566 intel_dp->num_common_rates,582 intel_dp->num_common_rates,
567 link_rate);583 link_rate);
568 if (index > 0) {584 if (index > 0) {
585 if (intel_dp_is_edp(intel_dp) &&
586 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
587 intel_dp->common_rates[index - 1],
588 lane_count)) {
589 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
590 return 0;
591 }
569 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];592 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
570 intel_dp->max_link_lane_count = lane_count;593 intel_dp->max_link_lane_count = lane_count;
571 } else if (lane_count > 1) {594 } else if (lane_count > 1) {
595 if (intel_dp_is_edp(intel_dp) &&
596 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
597 intel_dp_max_common_rate(intel_dp),
598 lane_count >> 1)) {
599 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
600 return 0;
601 }
572 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);602 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
573 intel_dp->max_link_lane_count = lane_count >> 1;603 intel_dp->max_link_lane_count = lane_count >> 1;
574 } else {604 } else {
@@ -3704,7 +3734,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) · 3129 unmodified lines
3704 uint32_t signal_levels, mask = 0;3734 uint32_t signal_levels, mask = 0;
3705 uint8_t train_set = intel_dp->train_set[0];3735 uint8_t train_set = intel_dp->train_set[0];
3706 3736
3707 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {3737 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3708 signal_levels = bxt_signal_levels(intel_dp);3738 signal_levels = bxt_signal_levels(intel_dp);
3709 } else if (HAS_DDI(dev_priv)) {3739 } else if (HAS_DDI(dev_priv)) {
3710 signal_levels = ddi_signal_levels(intel_dp);3740 signal_levels = ddi_signal_levels(intel_dp);
drivers/gpu/drm/i915/intel_dp_link_training.c+9−17
@@ -367,22 +367,14 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) · 366 unmodified lines
367 return;367 return;
368 368
369 failure_handling:369 failure_handling:
370 /* Dont fallback and prune modes if its eDP */370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
371 if (!intel_dp_is_edp(intel_dp)) {371 intel_connector->base.base.id,
372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",372 intel_connector->base.name,
373 intel_connector->base.base.id,373 intel_dp->link_rate, intel_dp->lane_count);
374 intel_connector->base.name,374 if (!intel_dp_get_link_train_fallback_values(intel_dp,
375 intel_dp->link_rate, intel_dp->lane_count);375 intel_dp->link_rate,
376 if (!intel_dp_get_link_train_fallback_values(intel_dp,376 intel_dp->lane_count))
377 intel_dp->link_rate,377 /* Schedule a Hotplug Uevent to userspace to start modeset */
378 intel_dp->lane_count))378 schedule_work(&intel_connector->modeset_retry_work);
379 /* Schedule a Hotplug Uevent to userspace to start modeset */
380 schedule_work(&intel_connector->modeset_retry_work);
381 } else {
382 DRM_ERROR("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
383 intel_connector->base.base.id,
384 intel_connector->base.name,
385 intel_dp->link_rate, intel_dp->lane_count);
386 }
387 return;379 return;
388}380}
drivers/gpu/drm/i915/intel_dp_mst.c+20−21
@@ -38,11 +38,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, · 37 unmodified lines
38 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);38 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
39 struct intel_digital_port *intel_dig_port = intel_mst->primary;39 struct intel_digital_port *intel_dig_port = intel_mst->primary;
40 struct intel_dp *intel_dp = &intel_dig_port->dp;40 struct intel_dp *intel_dp = &intel_dig_port->dp;
41 struct intel_connector *connector =41 struct drm_connector *connector = conn_state->connector;
42 to_intel_connector(conn_state->connector);42 void *port = to_intel_connector(connector)->port;
43 struct drm_atomic_state *state = pipe_config->base.state;43 struct drm_atomic_state *state = pipe_config->base.state;
44 int bpp;44 int bpp;
45 int lane_count, slots;45 int lane_count, slots = 0;
46 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;46 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
47 int mst_pbn;47 int mst_pbn;
48 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,48 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
@@ -70,17 +70,23 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, · 21 unmodified lines
70 70
71 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);71 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
72 72
73 if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, connector->port))73 if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, port))
74 pipe_config->has_audio = true;74 pipe_config->has_audio = true;
75 75
76 mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);76 mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
77 pipe_config->pbn = mst_pbn;77 pipe_config->pbn = mst_pbn;
78 78
79 slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,79 /* Zombie connectors can't have VCPI slots */
80 connector->port, mst_pbn);80 if (READ_ONCE(connector->registered)) {
81 if (slots < 0) {81 slots = drm_dp_atomic_find_vcpi_slots(state,
82 DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots);82 &intel_dp->mst_mgr,
83 return false;83 port,
84 mst_pbn);
85 if (slots < 0) {
86 DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
87 slots);
88 return false;
89 }
84 }90 }
85 91
86 intel_link_compute_m_n(bpp, lane_count,92 intel_link_compute_m_n(bpp, lane_count,
@@ -307,9 +313,8 @@ static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) · 220 unmodified lines
307 struct edid *edid;313 struct edid *edid;
308 int ret;314 int ret;
309 315
310 if (!intel_dp) {316 if (!READ_ONCE(connector->registered))
311 return intel_connector_update_modes(connector, NULL);317 return intel_connector_update_modes(connector, NULL);
312 }
313 318
314 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);319 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
315 ret = intel_connector_update_modes(connector, edid);320 ret = intel_connector_update_modes(connector, edid);
@@ -324,9 +329,10 @@ intel_dp_mst_detect(struct drm_connector *connector, bool force) · 8 unmodified lines
324 struct intel_connector *intel_connector = to_intel_connector(connector);329 struct intel_connector *intel_connector = to_intel_connector(connector);
325 struct intel_dp *intel_dp = intel_connector->mst_port;330 struct intel_dp *intel_dp = intel_connector->mst_port;
326 331
327 if (!intel_dp)332 if (!READ_ONCE(connector->registered))
328 return connector_status_disconnected;333 return connector_status_disconnected;
329 return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port);334 return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr,
335 intel_connector->port);
330}336}
331 337
332static void338static void
@@ -366,7 +372,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, · 33 unmodified lines
366 int bpp = 24; /* MST uses fixed bpp */372 int bpp = 24; /* MST uses fixed bpp */
367 int max_rate, mode_rate, max_lanes, max_link_clock;373 int max_rate, mode_rate, max_lanes, max_link_clock;
368 374
369 if (!intel_dp)375 if (!READ_ONCE(connector->registered))
370 return MODE_ERROR;376 return MODE_ERROR;
371 377
372 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)378 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -398,8 +404,6 @@ static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *c · 25 unmodified lines
398 struct intel_dp *intel_dp = intel_connector->mst_port;404 struct intel_dp *intel_dp = intel_connector->mst_port;
399 struct intel_crtc *crtc = to_intel_crtc(state->crtc);405 struct intel_crtc *crtc = to_intel_crtc(state->crtc);
400 406
401 if (!intel_dp)
402 return NULL;
403 return &intel_dp->mst_encoders[crtc->pipe]->base.base;407 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
404}408}
405 409
@@ -499,7 +503,6 @@ static void intel_dp_register_mst_connector(struct drm_connector *connector) · 93 unmodified lines
499static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,503static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
500 struct drm_connector *connector)504 struct drm_connector *connector)
501{505{
502 struct intel_connector *intel_connector = to_intel_connector(connector);
503 struct drm_i915_private *dev_priv = to_i915(connector->dev);506 struct drm_i915_private *dev_priv = to_i915(connector->dev);
504 507
505 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);
@@ -508,10 +511,6 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 2 unmodified lines
508 if (dev_priv->fbdev)511 if (dev_priv->fbdev)
509 drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper,512 drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper,
510 connector);513 connector);
511 /* prevent race with the check in ->detect */
512 drm_modeset_lock(&connector->dev->mode_config.connection_mutex, NULL);
513 intel_connector->mst_port = NULL;
514 drm_modeset_unlock(&connector->dev->mode_config.connection_mutex);
515 514
516 drm_connector_put(connector);515 drm_connector_put(connector);
517}516}
drivers/gpu/drm/i915/intel_drv.h+2−0
@@ -1517,6 +1517,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, · 1516 unmodified lines
1517 struct intel_encoder *encoder);1517 struct intel_encoder *encoder);
1518struct drm_display_mode *1518struct drm_display_mode *
1519intel_encoder_current_mode(struct intel_encoder *encoder);1519intel_encoder_current_mode(struct intel_encoder *encoder);
1520bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1520bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);1521bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1521enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,1522enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1522 enum port port);1523 enum port port);
@@ -2140,6 +2141,7 @@ unsigned int skl_plane_max_stride(struct intel_plane *plane, · 617 unmodified lines
2140 unsigned int rotation);2141 unsigned int rotation);
2141int skl_plane_check(struct intel_crtc_state *crtc_state,2142int skl_plane_check(struct intel_crtc_state *crtc_state,
2142 struct intel_plane_state *plane_state);2143 struct intel_plane_state *plane_state);
2144int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2143int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);2145int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2144int chv_plane_check_rotation(const struct intel_plane_state *plane_state);2146int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2145 2147
drivers/gpu/drm/i915/intel_sprite.c+22−0
@@ -230,6 +230,28 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) · 229 unmodified lines
230#endif230#endif
231}231}
232 232
233int intel_plane_check_stride(const struct intel_plane_state *plane_state)
234{
235 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
236 const struct drm_framebuffer *fb = plane_state->base.fb;
237 unsigned int rotation = plane_state->base.rotation;
238 u32 stride, max_stride;
239
240 /* FIXME other color planes? */
241 stride = plane_state->color_plane[0].stride;
242 max_stride = plane->max_stride(plane, fb->format->format,
243 fb->modifier, rotation);
244
245 if (stride > max_stride) {
246 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
247 fb->base.id, stride,
248 plane->base.base.id, plane->base.name, max_stride);
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
233int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)255int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
234{256{
235 const struct drm_framebuffer *fb = plane_state->base.fb;257 const struct drm_framebuffer *fb = plane_state->base.fb;
drivers/gpu/drm/i915/selftests/i915_gem_object.c+3−0
@@ -501,6 +501,8 @@ static bool assert_mmap_offset(struct drm_i915_private *i915, · 500 unmodified lines
501 501
502static void disable_retire_worker(struct drm_i915_private *i915)502static void disable_retire_worker(struct drm_i915_private *i915)
503{503{
504 i915_gem_shrinker_unregister(i915);
505
504 mutex_lock(&i915->drm.struct_mutex);506 mutex_lock(&i915->drm.struct_mutex);
505 if (!i915->gt.active_requests++) {507 if (!i915->gt.active_requests++) {
506 intel_runtime_pm_get(i915);508 intel_runtime_pm_get(i915);
@@ -613,6 +615,7 @@ out_park: · 106 unmodified lines
613 else615 else
614 queue_delayed_work(i915->wq, &i915->gt.idle_work, 0);616 queue_delayed_work(i915->wq, &i915->gt.idle_work, 0);
615 mutex_unlock(&i915->drm.struct_mutex);617 mutex_unlock(&i915->drm.struct_mutex);
618 i915_gem_shrinker_register(i915);
616 return err;619 return err;
617err_obj:620err_obj:
618 i915_gem_object_put(obj);621 i915_gem_object_put(obj);