History

Merge tag 'drm-intel-next-fixes-2018-10-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Fix GPU hang on MacBook2,1 when booting in EFI mode (Bugzilla #105637) - Fix garbled console on Y tiled BIOS framebuffer configs (Bugzilla #108264) - Fix black screen on certain eDP panels eg. Dell XPS 9350 (Bugzilla #107489 and #105338) - MST fixes that Rodrigo dropped from drm-intel-fixes and bunch of Icelake fixes - Then assorted proactive code fixes caught by CI or developers

Dave Airlie committed 8 years ago

Commit f2bfc712 parents c13bbf4 835fe6d12 files · +227 −104Browse files

Unified · Split

12 files
  1. drivers/gpu/drm/i915/i915_debugfs.c +1 −1
  2. drivers/gpu/drm/i915/i915_gem.c +2 −10
  3. drivers/gpu/drm/i915/i915_reg.h +3 −0
  4. drivers/gpu/drm/i915/intel_csr.c +1 −0
  5. drivers/gpu/drm/i915/intel_ddi.c +26 −10
  6. drivers/gpu/drm/i915/intel_display.c +107 −44
  7. drivers/gpu/drm/i915/intel_dp.c +31 −1
  8. drivers/gpu/drm/i915/intel_dp_link_training.c +9 −17
  9. drivers/gpu/drm/i915/intel_dp_mst.c +20 −21
  10. drivers/gpu/drm/i915/intel_drv.h +2 −0
  11. drivers/gpu/drm/i915/intel_sprite.c +22 −0
  12. drivers/gpu/drm/i915/selftests/i915_gem_object.c +3 −0
drivers/gpu/drm/i915/i915_debugfs.c+1−1
@@ -4189,7 +4189,7 @@ i915_drop_caches_set(void *data, u64 val) · 4188 unmodified lines
41894189 I915_WAIT_LOCKED,
41904190 MAX_SCHEDULE_TIMEOUT);
41914191
4192− if (val & DROP_RESET_SEQNO) {
4192+ if (ret == 0 && val & DROP_RESET_SEQNO) {
41934193 intel_runtime_pm_get(i915);
41944194 ret = i915_gem_set_global_seqno(&i915->drm, 1);
41954195 intel_runtime_pm_put(i915);
drivers/gpu/drm/i915/i915_gem.c+2−10
@@ -1127,11 +1127,7 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, · 1126 unmodified lines
11271127 offset = offset_in_page(args->offset);
11281128 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
11291129 struct page *page = i915_gem_object_get_page(obj, idx);
1130− int length;
1131−
1132− length = remain;
1133− if (offset + length > PAGE_SIZE)
1134− length = PAGE_SIZE - offset;
1130+ unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
11351131
11361132 ret = shmem_pread(page, offset, length, user_data,
11371133 page_to_phys(page) & obj_do_bit17_swizzling,
@@ -1575,11 +1571,7 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, · 437 unmodified lines
15751571 offset = offset_in_page(args->offset);
15761572 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
15771573 struct page *page = i915_gem_object_get_page(obj, idx);
1578− int length;
1579−
1580− length = remain;
1581− if (offset + length > PAGE_SIZE)
1582− length = PAGE_SIZE - offset;
1574+ unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
15831575
15841576 ret = shmem_pwrite(page, offset, length, user_data,
15851577 page_to_phys(page) & obj_do_bit17_swizzling,
drivers/gpu/drm/i915/i915_reg.h+3−0
@@ -9339,6 +9339,9 @@ enum skl_power_gate { · 9338 unmodified lines
93399339 #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
93409340 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
93419341 (port) + 10))
9342+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
9343+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
9344+ 21 : (tc_port) + 12))
93429345 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
93439346 (port) * 2)
93449347 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
drivers/gpu/drm/i915/intel_csr.c+1−0
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 */
3636
3737 #define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
38+MODULE_FIRMWARE(I915_CSR_ICL);
3839 #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
3940
4041 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
drivers/gpu/drm/i915/intel_ddi.c+26−10
@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por · 915 unmodified lines
916916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
917917
918918 if (IS_ICELAKE(dev_priv)) {
919− if (port == PORT_A || port == PORT_B)
919+ if (intel_port_is_combophy(dev_priv, port))
920920 icl_get_combo_buf_trans(dev_priv, port,
921921 INTEL_OUTPUT_HDMI, &n_entries);
922922 else
@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, · 612 unmodified lines
15351535 uint32_t pll_id;
15361536
15371537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538− if (port == PORT_A || port == PORT_B) {
1538+ if (intel_port_is_combophy(dev_priv, port)) {
15391539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
15401540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
15411541 else
@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) · 693 unmodified lines
22352235 int n_entries;
22362236
22372237 if (IS_ICELAKE(dev_priv)) {
2238− if (port == PORT_A || port == PORT_B)
2238+ if (intel_port_is_combophy(dev_priv, port))
22392239 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
22402240 &n_entries);
22412241 else
@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, · 427 unmodified lines
26692669 u32 level,
26702670 enum intel_output_type type)
26712671 {
2672+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
26722673 enum port port = encoder->port;
26732674
2674− if (port == PORT_A || port == PORT_B)
2675+ if (intel_port_is_combophy(dev_priv, port))
26752676 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
26762677 else
26772678 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2732,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) · 54 unmodified lines
27322733 return DDI_BUF_TRANS_SELECT(level);
27332734 }
27342735
2736+static inline
2737+uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2738+ enum port port)
2739+{
2740+ if (intel_port_is_combophy(dev_priv, port)) {
2741+ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2742+ } else if (intel_port_is_tc(dev_priv, port)) {
2743+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2744+
2745+ return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2746+ }
2747+
2748+ return 0;
2749+}
2750+
27352751 void icl_map_plls_to_ports(struct drm_crtc *crtc,
27362752 struct intel_crtc_state *crtc_state,
27372753 struct drm_atomic_state *old_state)
@@ -2755,16 +2771,16 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc, · 17 unmodified lines
27552771 mutex_lock(&dev_priv->dpll_lock);
27562772
27572773 val = I915_READ(DPCLKA_CFGCR0_ICL);
2758− WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2774+ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
27592775
2760− if (port == PORT_A || port == PORT_B) {
2776+ if (intel_port_is_combophy(dev_priv, port)) {
27612777 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
27622778 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
27632779 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
27642780 POSTING_READ(DPCLKA_CFGCR0_ICL);
27652781 }
27662782
2767− val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2783+ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
27682784 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
27692785
27702786 mutex_unlock(&dev_priv->dpll_lock);
@@ -2792,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc, · 21 unmodified lines
27922808 mutex_lock(&dev_priv->dpll_lock);
27932809 I915_WRITE(DPCLKA_CFGCR0_ICL,
27942810 I915_READ(DPCLKA_CFGCR0_ICL) |
2795− DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2811+ icl_dpclka_cfgcr0_clk_off(dev_priv, port));
27962812 mutex_unlock(&dev_priv->dpll_lock);
27972813 }
27982814 }
@@ -2810,7 +2826,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 11 unmodified lines
28102826 mutex_lock(&dev_priv->dpll_lock);
28112827
28122828 if (IS_ICELAKE(dev_priv)) {
2813− if (port >= PORT_C)
2829+ if (!intel_port_is_combophy(dev_priv, port))
28142830 I915_WRITE(DDI_CLK_SEL(port),
28152831 icl_pll_to_ddi_pll_sel(encoder, pll));
28162832 } else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2868,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) · 35 unmodified lines
28522868 enum port port = encoder->port;
28532869
28542870 if (IS_ICELAKE(dev_priv)) {
2855− if (port >= PORT_C)
2871+ if (!intel_port_is_combophy(dev_priv, port))
28562872 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
28572873 } else if (IS_CANNONLAKE(dev_priv)) {
28582874 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
drivers/gpu/drm/i915/intel_display.c+107−44
@@ -2722,6 +2722,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, · 2721 unmodified lines
27222722 if (size_aligned * 2 > dev_priv->stolen_usable_size)
27232723 return false;
27242724
2725+ switch (fb->modifier) {
2726+ case DRM_FORMAT_MOD_LINEAR:
2727+ case I915_FORMAT_MOD_X_TILED:
2728+ case I915_FORMAT_MOD_Y_TILED:
2729+ break;
2730+ default:
2731+ DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2732+ fb->modifier);
2733+ return false;
2734+ }
2735+
27252736 mutex_lock(&dev->struct_mutex);
27262737 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
27272738 base_aligned,
@@ -2731,8 +2742,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, · 3 unmodified lines
27312742 if (!obj)
27322743 return false;
27332744
2734− if (plane_config->tiling == I915_TILING_X)
2735− obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2745+ switch (plane_config->tiling) {
2746+ case I915_TILING_NONE:
2747+ break;
2748+ case I915_TILING_X:
2749+ case I915_TILING_Y:
2750+ obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2751+ break;
2752+ default:
2753+ MISSING_CASE(plane_config->tiling);
2754+ return false;
2755+ }
27362756
27372757 mode_cmd.pixel_format = fb->format->format;
27382758 mode_cmd.width = fb->width;
@@ -2764,20 +2784,33 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state, · 25 unmodified lines
27642784
27652785 plane_state->base.visible = visible;
27662786
2767− /* FIXME pre-g4x don't work like this */
2768− if (visible) {
2787+ if (visible)
27692788 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2770− crtc_state->active_planes |= BIT(plane->id);
2771− } else {
2789+ else
27722790 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2773− crtc_state->active_planes &= ~BIT(plane->id);
2774− }
27752791
27762792 DRM_DEBUG_KMS("%s active planes 0x%x\n",
27772793 crtc_state->base.crtc->name,
27782794 crtc_state->active_planes);
27792795 }
27802796
2797+static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2798+{
2799+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2800+ struct drm_plane *plane;
2801+
2802+ /*
2803+ * Active_planes aliases if multiple "primary" or cursor planes
2804+ * have been used on the same (or wrong) pipe. plane_mask uses
2805+ * unique ids, hence we can use that to reconstruct active_planes.
2806+ */
2807+ crtc_state->active_planes = 0;
2808+
2809+ drm_for_each_plane_mask(plane, &dev_priv->drm,
2810+ crtc_state->base.plane_mask)
2811+ crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2812+}
2813+
27812814 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
27822815 struct intel_plane *plane)
27832816 {
@@ -2787,6 +2820,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc, · 3 unmodified lines
27872820 to_intel_plane_state(plane->base.state);
27882821
27892822 intel_set_plane_visible(crtc_state, plane_state, false);
2823+ fixup_active_planes(crtc_state);
27902824
27912825 if (plane->id == PLANE_PRIMARY)
27922826 intel_pre_disable_primary_noatomic(&crtc->base);
@@ -2805,7 +2839,6 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, · 12 unmodified lines
28052839 struct drm_i915_gem_object *obj;
28062840 struct drm_plane *primary = intel_crtc->base.primary;
28072841 struct drm_plane_state *plane_state = primary->state;
2808− struct drm_crtc_state *crtc_state = intel_crtc->base.state;
28092842 struct intel_plane *intel_plane = to_intel_plane(primary);
28102843 struct intel_plane_state *intel_state =
28112844 to_intel_plane_state(plane_state);
@@ -2900,10 +2933,6 @@ valid_fb: · 88 unmodified lines
29002933 plane_state->fb = fb;
29012934 plane_state->crtc = &intel_crtc->base;
29022935
2903− intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2904− to_intel_plane_state(plane_state),
2905− true);
2906−
29072936 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
29082937 &obj->frontbuffer_bits);
29092938 }
@@ -3151,6 +3180,10 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) · 241 unmodified lines
31513180 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
31523181 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
31533182
3183+ ret = intel_plane_check_stride(plane_state);
3184+ if (ret)
3185+ return ret;
3186+
31543187 if (!plane_state->base.visible)
31553188 return 0;
31563189
@@ -3286,10 +3319,15 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) · 129 unmodified lines
32863319 int src_x = plane_state->base.src.x1 >> 16;
32873320 int src_y = plane_state->base.src.y1 >> 16;
32883321 u32 offset;
3322+ int ret;
32893323
32903324 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
32913325 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
32923326
3327+ ret = intel_plane_check_stride(plane_state);
3328+ if (ret)
3329+ return ret;
3330+
32933331 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
32943332
32953333 if (INTEL_GEN(dev_priv) >= 4)
@@ -5923,6 +5961,17 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) · 2627 unmodified lines
59235961 I915_WRITE(BCLRPAT(crtc->pipe), 0);
59245962 }
59255963
5964+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
5965+{
5966+ if (port == PORT_NONE)
5967+ return false;
5968+
5969+ if (IS_ICELAKE(dev_priv))
5970+ return port <= PORT_B;
5971+
5972+ return false;
5973+}
5974+
59265975 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
59275976 {
59285977 if (IS_ICELAKE(dev_priv))
@@ -8847,6 +8896,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, · 2918 unmodified lines
88478896 fb->modifier = I915_FORMAT_MOD_X_TILED;
88488897 break;
88498898 case PLANE_CTL_TILED_Y:
8899+ plane_config->tiling = I915_TILING_Y;
88508900 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
88518901 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
88528902 else
@@ -9683,10 +9733,15 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) · 830 unmodified lines
96839733 unsigned int rotation = plane_state->base.rotation;
96849734 int src_x, src_y;
96859735 u32 offset;
9736+ int ret;
96869737
96879738 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
96889739 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
96899740
9741+ ret = intel_plane_check_stride(plane_state);
9742+ if (ret)
9743+ return ret;
9744+
96909745 src_x = plane_state->base.src_x >> 16;
96919746 src_y = plane_state->base.src_y >> 16;
96929747
@@ -15436,17 +15491,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) · 5743 unmodified lines
1543615491 POSTING_READ(DPLL(pipe));
1543715492 }
1543815493
15439−static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15440− struct intel_plane *plane)
15441−{
15442− enum pipe pipe;
15443−
15444− if (!plane->get_hw_state(plane, &pipe))
15445− return true;
15446−
15447− return pipe == crtc->pipe;
15448−}
15449−
1545015494 static void
1545115495 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
1545215496 {
@@ -15458,13 +15502,20 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) · 5 unmodified lines
1545815502 for_each_intel_crtc(&dev_priv->drm, crtc) {
1545915503 struct intel_plane *plane =
1546015504 to_intel_plane(crtc->base.primary);
15505+ struct intel_crtc *plane_crtc;
15506+ enum pipe pipe;
1546115507
15462− if (intel_plane_mapping_ok(crtc, plane))
15508+ if (!plane->get_hw_state(plane, &pipe))
15509+ continue;
15510+
15511+ if (pipe == crtc->pipe)
1546315512 continue;
1546415513
1546515514 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
1546615515 plane->base.name);
15467− intel_plane_disable_noatomic(crtc, plane);
15516+
15517+ plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15518+ intel_plane_disable_noatomic(plane_crtc, plane);
1546815519 }
1546915520 }
1547015521
@@ -15512,13 +15563,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, · 41 unmodified lines
1551215563 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
1551315564 }
1551415565
15515− /* restore vblank interrupts to correct state */
15516− drm_crtc_vblank_reset(&crtc->base);
1551715566 if (crtc->active) {
1551815567 struct intel_plane *plane;
1551915568
15520− drm_crtc_vblank_on(&crtc->base);
15521−
1552215569 /* Disable everything but the primary plane */
1552315570 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1552415571 const struct intel_plane_state *plane_state =
@@ -15636,23 +15683,32 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) · 111 unmodified lines
1563615683 }
1563715684
1563815685 /* FIXME read out full plane state for all planes */
15639−static void readout_plane_state(struct intel_crtc *crtc)
15686+static void readout_plane_state(struct drm_i915_private *dev_priv)
1564015687 {
15641− struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15642− struct intel_crtc_state *crtc_state =
15643− to_intel_crtc_state(crtc->base.state);
1564415688 struct intel_plane *plane;
15689+ struct intel_crtc *crtc;
1564515690
15646− for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15691+ for_each_intel_plane(&dev_priv->drm, plane) {
1564715692 struct intel_plane_state *plane_state =
1564815693 to_intel_plane_state(plane->base.state);
15649− enum pipe pipe;
15694+ struct intel_crtc_state *crtc_state;
15695+ enum pipe pipe = PIPE_A;
1565015696 bool visible;
1565115697
1565215698 visible = plane->get_hw_state(plane, &pipe);
1565315699
15700+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15701+ crtc_state = to_intel_crtc_state(crtc->base.state);
15702+
1565415703 intel_set_plane_visible(crtc_state, plane_state, visible);
1565515704 }
15705+
15706+ for_each_intel_crtc(&dev_priv->drm, crtc) {
15707+ struct intel_crtc_state *crtc_state =
15708+ to_intel_crtc_state(crtc->base.state);
15709+
15710+ fixup_active_planes(crtc_state);
15711+ }
1565615712 }
1565715713
1565815714 static void intel_modeset_readout_hw_state(struct drm_device *dev)
@@ -15684,13 +15740,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) · 25 unmodified lines
1568415740 if (crtc_state->base.active)
1568515741 dev_priv->active_crtcs |= 1 << crtc->pipe;
1568615742
15687− readout_plane_state(crtc);
15688−
1568915743 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
1569015744 crtc->base.base.id, crtc->base.name,
1569115745 enableddisabled(crtc_state->base.active));
1569215746 }
1569315747
15748+ readout_plane_state(dev_priv);
15749+
1569415750 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1569515751 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
1569615752
@@ -15860,7 +15916,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 163 unmodified lines
1586015916 struct drm_modeset_acquire_ctx *ctx)
1586115917 {
1586215918 struct drm_i915_private *dev_priv = to_i915(dev);
15863− enum pipe pipe;
1586415919 struct intel_crtc *crtc;
1586515920 struct intel_encoder *encoder;
1586615921 int i;
@@ -15873,15 +15928,23 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 6 unmodified lines
1587315928 /* HW state is read out, now we need to sanitize this mess. */
1587415929 get_encoder_power_domains(dev_priv);
1587515930
15876− intel_sanitize_plane_mapping(dev_priv);
15931+ /*
15932+ * intel_sanitize_plane_mapping() may need to do vblank
15933+ * waits, so we need vblank interrupts restored beforehand.
15934+ */
15935+ for_each_intel_crtc(&dev_priv->drm, crtc) {
15936+ drm_crtc_vblank_reset(&crtc->base);
1587715937
15878− for_each_intel_encoder(dev, encoder) {
15879− intel_sanitize_encoder(encoder);
15938+ if (crtc->active)
15939+ drm_crtc_vblank_on(&crtc->base);
1588015940 }
1588115941
15882− for_each_pipe(dev_priv, pipe) {
15883− crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15942+ intel_sanitize_plane_mapping(dev_priv);
1588415943
15944+ for_each_intel_encoder(dev, encoder)
15945+ intel_sanitize_encoder(encoder);
15946+
15947+ for_each_intel_crtc(&dev_priv->drm, crtc) {
1588515948 intel_sanitize_crtc(crtc, ctx);
1588615949 intel_dump_pipe_config(crtc, crtc->config,
1588715950 "[setup_hw_state]");
drivers/gpu/drm/i915/intel_dp.c+31−1
@@ -557,6 +557,22 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, · 556 unmodified lines
557557 return true;
558558 }
559559
560+static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
561+ int link_rate,
562+ uint8_t lane_count)
563+{
564+ const struct drm_display_mode *fixed_mode =
565+ intel_dp->attached_connector->panel.fixed_mode;
566+ int mode_rate, max_rate;
567+
568+ mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
569+ max_rate = intel_dp_max_data_rate(link_rate, lane_count);
570+ if (mode_rate > max_rate)
571+ return false;
572+
573+ return true;
574+}
575+
560576 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
561577 int link_rate, uint8_t lane_count)
562578 {
@@ -566,9 +582,23 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, · 3 unmodified lines
566582 intel_dp->num_common_rates,
567583 link_rate);
568584 if (index > 0) {
585+ if (intel_dp_is_edp(intel_dp) &&
586+ !intel_dp_can_link_train_fallback_for_edp(intel_dp,
587+ intel_dp->common_rates[index - 1],
588+ lane_count)) {
589+ DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
590+ return 0;
591+ }
569592 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
570593 intel_dp->max_link_lane_count = lane_count;
571594 } else if (lane_count > 1) {
595+ if (intel_dp_is_edp(intel_dp) &&
596+ !intel_dp_can_link_train_fallback_for_edp(intel_dp,
597+ intel_dp_max_common_rate(intel_dp),
598+ lane_count >> 1)) {
599+ DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
600+ return 0;
601+ }
572602 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
573603 intel_dp->max_link_lane_count = lane_count >> 1;
574604 } else {
@@ -3704,7 +3734,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) · 3129 unmodified lines
37043734 uint32_t signal_levels, mask = 0;
37053735 uint8_t train_set = intel_dp->train_set[0];
37063736
3707− if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3737+ if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
37083738 signal_levels = bxt_signal_levels(intel_dp);
37093739 } else if (HAS_DDI(dev_priv)) {
37103740 signal_levels = ddi_signal_levels(intel_dp);
drivers/gpu/drm/i915/intel_dp_link_training.c+9−17
@@ -367,22 +367,14 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) · 366 unmodified lines
367367 return;
368368
369369 failure_handling:
370− /* Dont fallback and prune modes if its eDP */
371− if (!intel_dp_is_edp(intel_dp)) {
372− DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
373− intel_connector->base.base.id,
374− intel_connector->base.name,
375− intel_dp->link_rate, intel_dp->lane_count);
376− if (!intel_dp_get_link_train_fallback_values(intel_dp,
377− intel_dp->link_rate,
378− intel_dp->lane_count))
379− /* Schedule a Hotplug Uevent to userspace to start modeset */
380− schedule_work(&intel_connector->modeset_retry_work);
381− } else {
382− DRM_ERROR("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
383− intel_connector->base.base.id,
384− intel_connector->base.name,
385− intel_dp->link_rate, intel_dp->lane_count);
386− }
370+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
371+ intel_connector->base.base.id,
372+ intel_connector->base.name,
373+ intel_dp->link_rate, intel_dp->lane_count);
374+ if (!intel_dp_get_link_train_fallback_values(intel_dp,
375+ intel_dp->link_rate,
376+ intel_dp->lane_count))
377+ /* Schedule a Hotplug Uevent to userspace to start modeset */
378+ schedule_work(&intel_connector->modeset_retry_work);
387379 return;
388380 }
drivers/gpu/drm/i915/intel_dp_mst.c+20−21
@@ -38,11 +38,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, · 37 unmodified lines
3838 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
3939 struct intel_digital_port *intel_dig_port = intel_mst->primary;
4040 struct intel_dp *intel_dp = &intel_dig_port->dp;
41− struct intel_connector *connector =
42− to_intel_connector(conn_state->connector);
41+ struct drm_connector *connector = conn_state->connector;
42+ void *port = to_intel_connector(connector)->port;
4343 struct drm_atomic_state *state = pipe_config->base.state;
4444 int bpp;
45− int lane_count, slots;
45+ int lane_count, slots = 0;
4646 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
4747 int mst_pbn;
4848 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
@@ -70,17 +70,23 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, · 21 unmodified lines
7070
7171 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
7272
73− if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, connector->port))
73+ if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, port))
7474 pipe_config->has_audio = true;
7575
7676 mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
7777 pipe_config->pbn = mst_pbn;
7878
79− slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
80− connector->port, mst_pbn);
81− if (slots < 0) {
82− DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots);
83− return false;
79+ /* Zombie connectors can't have VCPI slots */
80+ if (READ_ONCE(connector->registered)) {
81+ slots = drm_dp_atomic_find_vcpi_slots(state,
82+ &intel_dp->mst_mgr,
83+ port,
84+ mst_pbn);
85+ if (slots < 0) {
86+ DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
87+ slots);
88+ return false;
89+ }
8490 }
8591
8692 intel_link_compute_m_n(bpp, lane_count,
@@ -307,9 +313,8 @@ static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) · 220 unmodified lines
307313 struct edid *edid;
308314 int ret;
309315
310− if (!intel_dp) {
316+ if (!READ_ONCE(connector->registered))
311317 return intel_connector_update_modes(connector, NULL);
312− }
313318
314319 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
315320 ret = intel_connector_update_modes(connector, edid);
@@ -324,9 +329,10 @@ intel_dp_mst_detect(struct drm_connector *connector, bool force) · 8 unmodified lines
324329 struct intel_connector *intel_connector = to_intel_connector(connector);
325330 struct intel_dp *intel_dp = intel_connector->mst_port;
326331
327− if (!intel_dp)
332+ if (!READ_ONCE(connector->registered))
328333 return connector_status_disconnected;
329− return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port);
334+ return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr,
335+ intel_connector->port);
330336 }
331337
332338 static void
@@ -366,7 +372,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, · 33 unmodified lines
366372 int bpp = 24; /* MST uses fixed bpp */
367373 int max_rate, mode_rate, max_lanes, max_link_clock;
368374
369− if (!intel_dp)
375+ if (!READ_ONCE(connector->registered))
370376 return MODE_ERROR;
371377
372378 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -398,8 +404,6 @@ static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *c · 25 unmodified lines
398404 struct intel_dp *intel_dp = intel_connector->mst_port;
399405 struct intel_crtc *crtc = to_intel_crtc(state->crtc);
400406
401− if (!intel_dp)
402− return NULL;
403407 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
404408 }
405409
@@ -499,7 +503,6 @@ static void intel_dp_register_mst_connector(struct drm_connector *connector) · 93 unmodified lines
499503 static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
500504 struct drm_connector *connector)
501505 {
502− struct intel_connector *intel_connector = to_intel_connector(connector);
503506 struct drm_i915_private *dev_priv = to_i915(connector->dev);
504507
505508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);
@@ -508,10 +511,6 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 2 unmodified lines
508511 if (dev_priv->fbdev)
509512 drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper,
510513 connector);
511− /* prevent race with the check in ->detect */
512− drm_modeset_lock(&connector->dev->mode_config.connection_mutex, NULL);
513− intel_connector->mst_port = NULL;
514− drm_modeset_unlock(&connector->dev->mode_config.connection_mutex);
515514
516515 drm_connector_put(connector);
517516 }
drivers/gpu/drm/i915/intel_drv.h+2−0
@@ -1517,6 +1517,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, · 1516 unmodified lines
15171517 struct intel_encoder *encoder);
15181518 struct drm_display_mode *
15191519 intel_encoder_current_mode(struct intel_encoder *encoder);
1520+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
15201521 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
15211522 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
15221523 enum port port);
@@ -2140,6 +2141,7 @@ unsigned int skl_plane_max_stride(struct intel_plane *plane, · 617 unmodified lines
21402141 unsigned int rotation);
21412142 int skl_plane_check(struct intel_crtc_state *crtc_state,
21422143 struct intel_plane_state *plane_state);
2144+int intel_plane_check_stride(const struct intel_plane_state *plane_state);
21432145 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
21442146 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
21452147
drivers/gpu/drm/i915/intel_sprite.c+22−0
@@ -230,6 +230,28 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) · 229 unmodified lines
230230 #endif
231231 }
232232
233+int intel_plane_check_stride(const struct intel_plane_state *plane_state)
234+{
235+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
236+ const struct drm_framebuffer *fb = plane_state->base.fb;
237+ unsigned int rotation = plane_state->base.rotation;
238+ u32 stride, max_stride;
239+
240+ /* FIXME other color planes? */
241+ stride = plane_state->color_plane[0].stride;
242+ max_stride = plane->max_stride(plane, fb->format->format,
243+ fb->modifier, rotation);
244+
245+ if (stride > max_stride) {
246+ DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
247+ fb->base.id, stride,
248+ plane->base.base.id, plane->base.name, max_stride);
249+ return -EINVAL;
250+ }
251+
252+ return 0;
253+}
254+
233255 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
234256 {
235257 const struct drm_framebuffer *fb = plane_state->base.fb;
drivers/gpu/drm/i915/selftests/i915_gem_object.c+3−0
@@ -501,6 +501,8 @@ static bool assert_mmap_offset(struct drm_i915_private *i915, · 500 unmodified lines
501501
502502 static void disable_retire_worker(struct drm_i915_private *i915)
503503 {
504+ i915_gem_shrinker_unregister(i915);
505+
504506 mutex_lock(&i915->drm.struct_mutex);
505507 if (!i915->gt.active_requests++) {
506508 intel_runtime_pm_get(i915);
@@ -613,6 +615,7 @@ out_park: · 106 unmodified lines
613615 else
614616 queue_delayed_work(i915->wq, &i915->gt.idle_work, 0);
615617 mutex_unlock(&i915->drm.struct_mutex);
618+ i915_gem_shrinker_register(i915);
616619 return err;
617620 err_obj:
618621 i915_gem_object_put(obj);