Updates for 5.1: - GDS fixes - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface - GPUVM fixes - PCIE DPM switching fixes for vega20 - Vega10 uclk DPM regression fix - DC Freesync fixes - DC ABM fixes - Various DC cleanups
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| @@ -523,6 +523,7 @@ struct drm_amdgpu_gem_va { · 522 unmodified lines | |||
| 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 | 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
| 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 | 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
| 526 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 | ||
| 526 | 527 | ||
| 527 | struct drm_amdgpu_cs_chunk { | 528 | struct drm_amdgpu_cs_chunk { |
| 528 | __u32 chunk_id; | 529 | __u32 chunk_id; |
| @@ -565,6 +566,11 @@ union drm_amdgpu_cs { · 36 unmodified lines | |||
| 565 | * caches (L2/vL1/sL1/I$). */ | 566 | * caches (L2/vL1/sL1/I$). */ |
| 566 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | 567 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) |
| 567 | 568 | ||
| 569 | /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. | ||
| 570 | * This will reset wave ID counters for the IB. | ||
| 571 | */ | ||
| 572 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) | ||
| 573 | |||
| 568 | struct drm_amdgpu_cs_chunk_ib { | 574 | struct drm_amdgpu_cs_chunk_ib { |
| 569 | __u32 _pad; | 575 | __u32 _pad; |
| 570 | /** AMDGPU_IB_FLAG_* */ | 576 | /** AMDGPU_IB_FLAG_* */ |