Use 6.1.0 register offset and remove unused variable. v2: clean up logic (Alex)
Unified · Split
| @@ -28,6 +28,9 @@ · 27 unmodified lines | ||
| 28 | 28 | #include "hdp/hdp_6_0_0_sh_mask.h" |
| 29 | 29 | #include <uapi/linux/kfd_ioctl.h> |
| 30 | 30 | |
| 31 | +#define regHDP_CLK_CNTL_V6_1 0xd5 | |
| 32 | +#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0 | |
| 33 | + | |
| 31 | 34 | static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, |
| 32 | 35 | struct amdgpu_ring *ring) |
| 33 | 36 | { |
| @@ -40,7 +43,7 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, · 6 unmodified lines | ||
| 40 | 43 | static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, |
| 41 | 44 | bool enable) |
| 42 | 45 | { |
| 43 | − uint32_t hdp_clk_cntl, hdp_clk_cntl1; | |
| 46 | + uint32_t hdp_clk_cntl; | |
| 44 | 47 | uint32_t hdp_mem_pwr_cntl; |
| 45 | 48 | |
| 46 | 49 | if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | |
| @@ -48,14 +51,20 @@ static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, · 1 unmodified line | ||
| 48 | 51 | AMD_CG_SUPPORT_HDP_SD))) |
| 49 | 52 | return; |
| 50 | 53 | |
| 51 | − hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); | |
| 54 | + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0)) | |
| 55 | + hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); | |
| 56 | + else | |
| 57 | + hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); | |
| 52 | 58 | hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); |
| 53 | 59 | |
| 54 | 60 | /* Before doing clock/power mode switch, |
| 55 | 61 | * forced on IPH & RC clock */ |
| 56 | 62 | hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, |
| 57 | 63 | RC_MEM_CLK_SOFT_OVERRIDE, 1); |
| 58 | − WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); | |
| 64 | + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0)) | |
| 65 | + WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); | |
| 66 | + else | |
| 67 | + WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); | |
| 59 | 68 | |
| 60 | 69 | /* disable clock and power gating before any changing */ |
| 61 | 70 | hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, |
| @@ -117,7 +126,10 @@ static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, · 55 unmodified lines | ||
| 117 | 126 | /* disable IPH & RC clock override after clock/power mode changing */ |
| 118 | 127 | hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, |
| 119 | 128 | RC_MEM_CLK_SOFT_OVERRIDE, 0); |
| 120 | − WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); | |
| 129 | + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(6, 1, 0)) | |
| 130 | + WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); | |
| 131 | + else | |
| 132 | + WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); | |
| 121 | 133 | } |
| 122 | 134 | |
| 123 | 135 | static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, |