History

Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next

- Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support

Stephen Boyd committed 7 years ago

Commit f6111b95 parents 2ed3b91 f14382d 043f44a 6e4fcc3 5834fd736 files · +2424 −710Browse files

Unified · Split

36 files
  1. Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt +2 −1
  2. arch/powerpc/platforms/512x/clock-commonclk.c +6 −3
  3. drivers/clk/clk-divider.c +20 −4
  4. drivers/clk/clk-fractional-divider.c +19 −3
  5. drivers/clk/clk-gate.c +19 −3
  6. drivers/clk/clk-highbank.c +10 −13
  7. drivers/clk/clk-multiplier.c +19 −3
  8. drivers/clk/clk-mux.c +19 −3
  9. drivers/clk/clk-xgene.c +3 −3
  10. drivers/clk/clk.c +26 −20
  11. drivers/clk/hisilicon/clk-hisi-phase.c +2 −2
  12. drivers/clk/imx/clk-divider-gate.c +10 −10
  13. drivers/clk/imx/clk-sccg-pll.c +6 −6
  14. drivers/clk/meson/axg-audio.c +718 −501
  15. drivers/clk/meson/axg-audio.h +6 −10
  16. drivers/clk/meson/clk-pll.c +26 −0
  17. drivers/clk/meson/clk-pll.h +1 −0
  18. drivers/clk/meson/g12a-aoclk.h +0 −2
  19. drivers/clk/meson/g12a.c +631 −0
  20. drivers/clk/meson/g12a.h +30 −1
  21. drivers/clk/meson/meson8b.c +733 −1
  22. drivers/clk/meson/meson8b.h +26 −1
  23. drivers/clk/nxp/clk-lpc18xx-ccu.c +3 −3
  24. drivers/clk/nxp/clk-lpc18xx-cgu.c +12 −12
  25. drivers/clk/nxp/clk-lpc32xx.c +3 −4
  26. drivers/clk/rockchip/clk-ddr.c +1 −1
  27. drivers/clk/rockchip/clk-half-divider.c +3 −3
  28. drivers/clk/tegra/clk-tegra124.c +2 −2
  29. drivers/clk/tegra/clk-tegra210.c +3 −3
  30. drivers/clk/zynq/clkc.c +3 −3
  31. drivers/clk/zynq/pll.c +9 −9
  32. include/dt-bindings/clock/axg-audio-clkc.h +10 −20
  33. include/dt-bindings/clock/g12a-aoclkc.h +2 −0
  34. include/dt-bindings/clock/g12a-clkc.h +5 −0
  35. include/dt-bindings/clock/meson8b-clkc.h +5 −1
  36. include/linux/clk-provider.h +31 −59
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt+2−1
@@ -6,7 +6,8 @@ devices. · 5 unmodified lines
6 6
7Required Properties:7Required Properties:
8 8
9- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D9- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
10 "amlogic,g12a-audio-clkc" for G12A.
10- reg : physical base address of the clock controller and length of11- reg : physical base address of the clock controller and length of
11 memory mapped region.12 memory mapped region.
12- clocks : a list of phandle + clock-specifier pairs for the clocks listed13- clocks : a list of phandle + clock-specifier pairs for the clocks listed
arch/powerpc/platforms/512x/clock-commonclk.c+6−3
@@ -239,6 +239,7 @@ static inline struct clk *mpc512x_clk_divider( · 238 unmodified lines
239 const char *name, const char *parent_name, u8 clkflags,239 const char *name, const char *parent_name, u8 clkflags,
240 u32 __iomem *reg, u8 pos, u8 len, int divflags)240 u32 __iomem *reg, u8 pos, u8 len, int divflags)
241{241{
242 divflags |= CLK_DIVIDER_BIG_ENDIAN;
242 return clk_register_divider(NULL, name, parent_name, clkflags,243 return clk_register_divider(NULL, name, parent_name, clkflags,
243 reg, pos, len, divflags, &clklock);244 reg, pos, len, divflags, &clklock);
244}245}
@@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable( · 5 unmodified lines
250{251{
251 u8 divflags;252 u8 divflags;
252 253
253 divflags = 0;254 divflags = CLK_DIVIDER_BIG_ENDIAN;
254 return clk_register_divider_table(NULL, name, parent_name, 0,255 return clk_register_divider_table(NULL, name, parent_name, 0,
255 reg, pos, len, divflags,256 reg, pos, len, divflags,
256 divtab, &clklock);257 divtab, &clklock);
@@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated( · 4 unmodified lines
261 u32 __iomem *reg, u8 pos)262 u32 __iomem *reg, u8 pos)
262{263{
263 int clkflags;264 int clkflags;
265 u8 gateflags;
264 266
265 clkflags = CLK_SET_RATE_PARENT;267 clkflags = CLK_SET_RATE_PARENT;
268 gateflags = CLK_GATE_BIG_ENDIAN;
266 return clk_register_gate(NULL, name, parent_name, clkflags,269 return clk_register_gate(NULL, name, parent_name, clkflags,
267 reg, pos, 0, &clklock);270 reg, pos, gateflags, &clklock);
268}271}
269 272
270static inline struct clk *mpc512x_clk_muxed(const char *name,273static inline struct clk *mpc512x_clk_muxed(const char *name,
@@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name, · 4 unmodified lines
275 u8 muxflags;278 u8 muxflags;
276 279
277 clkflags = CLK_SET_RATE_PARENT;280 clkflags = CLK_SET_RATE_PARENT;
278 muxflags = 0;281 muxflags = CLK_MUX_BIG_ENDIAN;
279 return clk_register_mux(NULL, name,282 return clk_register_mux(NULL, name,
280 parent_names, parent_count, clkflags,283 parent_names, parent_count, clkflags,
281 reg, pos, len, muxflags, &clklock);284 reg, pos, len, muxflags, &clklock);
drivers/clk/clk-divider.c+20−4
@@ -25,6 +25,22 @@ · 24 unmodified lines
25 * parent - fixed parent. No clk_set_parent support25 * parent - fixed parent. No clk_set_parent support
26 */26 */
27 27
28static inline u32 clk_div_readl(struct clk_divider *divider)
29{
30 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
31 return ioread32be(divider->reg);
32
33 return readl(divider->reg);
34}
35
36static inline void clk_div_writel(struct clk_divider *divider, u32 val)
37{
38 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
39 iowrite32be(val, divider->reg);
40 else
41 writel(val, divider->reg);
42}
43
28static unsigned int _get_table_maxdiv(const struct clk_div_table *table,44static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
29 u8 width)45 u8 width)
30{46{
@@ -135,7 +151,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, · 104 unmodified lines
135 struct clk_divider *divider = to_clk_divider(hw);151 struct clk_divider *divider = to_clk_divider(hw);
136 unsigned int val;152 unsigned int val;
137 153
138 val = clk_readl(divider->reg) >> divider->shift;154 val = clk_div_readl(divider) >> divider->shift;
139 val &= clk_div_mask(divider->width);155 val &= clk_div_mask(divider->width);
140 156
141 return divider_recalc_rate(hw, parent_rate, val, divider->table,157 return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -370,7 +386,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, · 228 unmodified lines
370 if (divider->flags & CLK_DIVIDER_READ_ONLY) {386 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
371 u32 val;387 u32 val;
372 388
373 val = clk_readl(divider->reg) >> divider->shift;389 val = clk_div_readl(divider) >> divider->shift;
374 val &= clk_div_mask(divider->width);390 val &= clk_div_mask(divider->width);
375 391
376 return divider_ro_round_rate(hw, rate, prate, divider->table,392 return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -420,11 +436,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, · 43 unmodified lines
420 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {436 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
421 val = clk_div_mask(divider->width) << (divider->shift + 16);437 val = clk_div_mask(divider->width) << (divider->shift + 16);
422 } else {438 } else {
423 val = clk_readl(divider->reg);439 val = clk_div_readl(divider);
424 val &= ~(clk_div_mask(divider->width) << divider->shift);440 val &= ~(clk_div_mask(divider->width) << divider->shift);
425 }441 }
426 val |= (u32)value << divider->shift;442 val |= (u32)value << divider->shift;
427 clk_writel(val, divider->reg);443 clk_div_writel(divider, val);
428 444
429 if (divider->lock)445 if (divider->lock)
430 spin_unlock_irqrestore(divider->lock, flags);446 spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/clk-fractional-divider.c+19−3
@@ -13,6 +13,22 @@ · 12 unmodified lines
13#include <linux/slab.h>13#include <linux/slab.h>
14#include <linux/rational.h>14#include <linux/rational.h>
15 15
16static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
17{
18 if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
19 return ioread32be(fd->reg);
20
21 return readl(fd->reg);
22}
23
24static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
25{
26 if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
27 iowrite32be(val, fd->reg);
28 else
29 writel(val, fd->reg);
30}
31
16static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,32static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
17 unsigned long parent_rate)33 unsigned long parent_rate)
18{34{
@@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, · 8 unmodified lines
27 else43 else
28 __acquire(fd->lock);44 __acquire(fd->lock);
29 45
30 val = clk_readl(fd->reg);46 val = clk_fd_readl(fd);
31 47
32 if (fd->lock)48 if (fd->lock)
33 spin_unlock_irqrestore(fd->lock, flags);49 spin_unlock_irqrestore(fd->lock, flags);
@@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, · 81 unmodified lines
115 else131 else
116 __acquire(fd->lock);132 __acquire(fd->lock);
117 133
118 val = clk_readl(fd->reg);134 val = clk_fd_readl(fd);
119 val &= ~(fd->mmask | fd->nmask);135 val &= ~(fd->mmask | fd->nmask);
120 val |= (m << fd->mshift) | (n << fd->nshift);136 val |= (m << fd->mshift) | (n << fd->nshift);
121 clk_writel(val, fd->reg);137 clk_fd_writel(fd, val);
122 138
123 if (fd->lock)139 if (fd->lock)
124 spin_unlock_irqrestore(fd->lock, flags);140 spin_unlock_irqrestore(fd->lock, flags);
drivers/clk/clk-gate.c+19−3
@@ -23,6 +23,22 @@ · 22 unmodified lines
23 * parent - fixed parent. No clk_set_parent support23 * parent - fixed parent. No clk_set_parent support
24 */24 */
25 25
26static inline u32 clk_gate_readl(struct clk_gate *gate)
27{
28 if (gate->flags & CLK_GATE_BIG_ENDIAN)
29 return ioread32be(gate->reg);
30
31 return readl(gate->reg);
32}
33
34static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
35{
36 if (gate->flags & CLK_GATE_BIG_ENDIAN)
37 iowrite32be(val, gate->reg);
38 else
39 writel(val, gate->reg);
40}
41
26/*42/*
27 * It works on following logic:43 * It works on following logic:
28 *44 *
@@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) · 26 unmodified lines
55 if (set)71 if (set)
56 reg |= BIT(gate->bit_idx);72 reg |= BIT(gate->bit_idx);
57 } else {73 } else {
58 reg = clk_readl(gate->reg);74 reg = clk_gate_readl(gate);
59 75
60 if (set)76 if (set)
61 reg |= BIT(gate->bit_idx);77 reg |= BIT(gate->bit_idx);
@@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) · 1 unmodified line
63 reg &= ~BIT(gate->bit_idx);79 reg &= ~BIT(gate->bit_idx);
64 }80 }
65 81
66 clk_writel(reg, gate->reg);82 clk_gate_writel(gate, reg);
67 83
68 if (gate->lock)84 if (gate->lock)
69 spin_unlock_irqrestore(gate->lock, flags);85 spin_unlock_irqrestore(gate->lock, flags);
@@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) · 18 unmodified lines
88 u32 reg;104 u32 reg;
89 struct clk_gate *gate = to_clk_gate(hw);105 struct clk_gate *gate = to_clk_gate(hw);
90 106
91 reg = clk_readl(gate->reg);107 reg = clk_gate_readl(gate);
92 108
93 /* if a set bit disables this clk, flip it before masking */109 /* if a set bit disables this clk, flip it before masking */
94 if (gate->flags & CLK_GATE_SET_TO_DISABLE)110 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
drivers/clk/clk-highbank.c+10−13
@@ -17,7 +17,6 @@ · 16 unmodified lines
17#include <linux/kernel.h>17#include <linux/kernel.h>
18#include <linux/slab.h>18#include <linux/slab.h>
19#include <linux/err.h>19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/clk-provider.h>20#include <linux/clk-provider.h>
22#include <linux/io.h>21#include <linux/io.h>
23#include <linux/of.h>22#include <linux/of.h>
@@ -272,7 +271,7 @@ static const struct clk_ops periclk_ops = { · 248 unmodified lines
272 .set_rate = clk_periclk_set_rate,271 .set_rate = clk_periclk_set_rate,
273};272};
274 273
275static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)274static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
276{275{
277 u32 reg;276 u32 reg;
278 struct hb_clk *hb_clk;277 struct hb_clk *hb_clk;
@@ -284,11 +283,11 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk · 5 unmodified lines
284 283
285 rc = of_property_read_u32(node, "reg", &reg);284 rc = of_property_read_u32(node, "reg", &reg);
286 if (WARN_ON(rc))285 if (WARN_ON(rc))
287 return NULL;286 return;
288 287
289 hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);288 hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
290 if (WARN_ON(!hb_clk))289 if (WARN_ON(!hb_clk))
291 return NULL;290 return;
292 291
293 /* Map system registers */292 /* Map system registers */
294 srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");293 srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
@@ -301,7 +300,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk · 6 unmodified lines
301 300
302 init.name = clk_name;301 init.name = clk_name;
303 init.ops = ops;302 init.ops = ops;
304 init.flags = 0;303 init.flags = clkflags;
305 parent_name = of_clk_get_parent_name(node, 0);304 parent_name = of_clk_get_parent_name(node, 0);
306 init.parent_names = &parent_name;305 init.parent_names = &parent_name;
307 init.num_parents = 1;306 init.num_parents = 1;
@@ -311,33 +310,31 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk · 3 unmodified lines
311 rc = clk_hw_register(NULL, &hb_clk->hw);310 rc = clk_hw_register(NULL, &hb_clk->hw);
312 if (WARN_ON(rc)) {311 if (WARN_ON(rc)) {
313 kfree(hb_clk);312 kfree(hb_clk);
314 return NULL;313 return;
315 }314 }
316 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);315 of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
317 return hb_clk->hw.clk;
318}316}
319 317
320static void __init hb_pll_init(struct device_node *node)318static void __init hb_pll_init(struct device_node *node)
321{319{
322 hb_clk_init(node, &clk_pll_ops);320 hb_clk_init(node, &clk_pll_ops, 0);
323}321}
324CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);322CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
325 323
326static void __init hb_a9periph_init(struct device_node *node)324static void __init hb_a9periph_init(struct device_node *node)
327{325{
328 hb_clk_init(node, &a9periphclk_ops);326 hb_clk_init(node, &a9periphclk_ops, 0);
329}327}
330CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);328CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
331 329
332static void __init hb_a9bus_init(struct device_node *node)330static void __init hb_a9bus_init(struct device_node *node)
333{331{
334 struct clk *clk = hb_clk_init(node, &a9bclk_ops);332 hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
335 clk_prepare_enable(clk);
336}333}
337CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);334CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
338 335
339static void __init hb_emmc_init(struct device_node *node)336static void __init hb_emmc_init(struct device_node *node)
340{337{
341 hb_clk_init(node, &periclk_ops);338 hb_clk_init(node, &periclk_ops, 0);
342}339}
343CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);340CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
drivers/clk/clk-multiplier.c+19−3
@@ -11,6 +11,22 @@ · 10 unmodified lines
11#include <linux/of.h>11#include <linux/of.h>
12#include <linux/slab.h>12#include <linux/slab.h>
13 13
14static inline u32 clk_mult_readl(struct clk_multiplier *mult)
15{
16 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
17 return ioread32be(mult->reg);
18
19 return readl(mult->reg);
20}
21
22static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
23{
24 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
25 iowrite32be(val, mult->reg);
26 else
27 writel(val, mult->reg);
28}
29
14static unsigned long __get_mult(struct clk_multiplier *mult,30static unsigned long __get_mult(struct clk_multiplier *mult,
15 unsigned long rate,31 unsigned long rate,
16 unsigned long parent_rate)32 unsigned long parent_rate)
@@ -27,7 +43,7 @@ static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw, · 10 unmodified lines
27 struct clk_multiplier *mult = to_clk_multiplier(hw);43 struct clk_multiplier *mult = to_clk_multiplier(hw);
28 unsigned long val;44 unsigned long val;
29 45
30 val = clk_readl(mult->reg) >> mult->shift;46 val = clk_mult_readl(mult) >> mult->shift;
31 val &= GENMASK(mult->width - 1, 0);47 val &= GENMASK(mult->width - 1, 0);
32 48
33 if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)49 if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
@@ -118,10 +134,10 @@ static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate, · 84 unmodified lines
118 else134 else
119 __acquire(mult->lock);135 __acquire(mult->lock);
120 136
121 val = clk_readl(mult->reg);137 val = clk_mult_readl(mult);
122 val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);138 val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);
123 val |= factor << mult->shift;139 val |= factor << mult->shift;
124 clk_writel(val, mult->reg);140 clk_mult_writel(mult, val);
125 141
126 if (mult->lock)142 if (mult->lock)
127 spin_unlock_irqrestore(mult->lock, flags);143 spin_unlock_irqrestore(mult->lock, flags);
drivers/clk/clk-mux.c+19−3
@@ -23,6 +23,22 @@ · 22 unmodified lines
23 * parent - parent is adjustable through clk_set_parent23 * parent - parent is adjustable through clk_set_parent
24 */24 */
25 25
26static inline u32 clk_mux_readl(struct clk_mux *mux)
27{
28 if (mux->flags & CLK_MUX_BIG_ENDIAN)
29 return ioread32be(mux->reg);
30
31 return readl(mux->reg);
32}
33
34static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
35{
36 if (mux->flags & CLK_MUX_BIG_ENDIAN)
37 iowrite32be(val, mux->reg);
38 else
39 writel(val, mux->reg);
40}
41
26int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,42int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
27 unsigned int val)43 unsigned int val)
28{44{
@@ -73,7 +89,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) · 44 unmodified lines
73 struct clk_mux *mux = to_clk_mux(hw);89 struct clk_mux *mux = to_clk_mux(hw);
74 u32 val;90 u32 val;
75 91
76 val = clk_readl(mux->reg) >> mux->shift;92 val = clk_mux_readl(mux) >> mux->shift;
77 val &= mux->mask;93 val &= mux->mask;
78 94
79 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);95 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
@@ -94,12 +110,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) · 14 unmodified lines
94 if (mux->flags & CLK_MUX_HIWORD_MASK) {110 if (mux->flags & CLK_MUX_HIWORD_MASK) {
95 reg = mux->mask << (mux->shift + 16);111 reg = mux->mask << (mux->shift + 16);
96 } else {112 } else {
97 reg = clk_readl(mux->reg);113 reg = clk_mux_readl(mux);
98 reg &= ~(mux->mask << mux->shift);114 reg &= ~(mux->mask << mux->shift);
99 }115 }
100 val = val << mux->shift;116 val = val << mux->shift;
101 reg |= val;117 reg |= val;
102 clk_writel(reg, mux->reg);118 clk_mux_writel(mux, reg);
103 119
104 if (mux->lock)120 if (mux->lock)
105 spin_unlock_irqrestore(mux->lock, flags);121 spin_unlock_irqrestore(mux->lock, flags);
drivers/clk/clk-xgene.c+3−3
@@ -262,7 +262,7 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw, · 261 unmodified lines
262 else262 else
263 __acquire(fd->lock);263 __acquire(fd->lock);
264 264
265 val = clk_readl(fd->reg);265 val = readl(fd->reg);
266 266
267 if (fd->lock)267 if (fd->lock)
268 spin_unlock_irqrestore(fd->lock, flags);268 spin_unlock_irqrestore(fd->lock, flags);
@@ -333,10 +333,10 @@ static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate, · 64 unmodified lines
333 else333 else
334 __acquire(fd->lock);334 __acquire(fd->lock);
335 335
336 val = clk_readl(fd->reg);336 val = readl(fd->reg);
337 val &= ~fd->mask;337 val &= ~fd->mask;
338 val |= (scale << fd->shift);338 val |= (scale << fd->shift);
339 clk_writel(val, fd->reg);339 writel(val, fd->reg);
340 340
341 if (fd->lock)341 if (fd->lock)
342 spin_unlock_irqrestore(fd->lock, flags);342 spin_unlock_irqrestore(fd->lock, flags);
drivers/clk/clk.c+26−20
@@ -347,23 +347,18 @@ unsigned int __clk_get_enable_count(struct clk *clk) · 346 unmodified lines
347 347
348static unsigned long clk_core_get_rate_nolock(struct clk_core *core)348static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
349{349{
350 unsigned long ret;350 if (!core)
351 351 return 0;
352 if (!core) {
353 ret = 0;
354 goto out;
355 }
356
357 ret = core->rate;
358
359 if (!core->num_parents)
360 goto out;
361 352
362 if (!core->parent)353 if (!core->num_parents || core->parent)
363 ret = 0;354 return core->rate;
364 355
365out:356 /*
366 return ret;357 * Clk must have a parent because num_parents > 0 but the parent isn't
358 * known yet. Best to return 0 as the rate of this clk until we can
359 * properly recalc the rate based on the parent's rate.
360 */
361 return 0;
367}362}
368 363
369unsigned long clk_hw_get_rate(const struct clk_hw *hw)364unsigned long clk_hw_get_rate(const struct clk_hw *hw)
@@ -524,9 +519,15 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, · 154 unmodified lines
524EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);519EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
525 520
526/*521/*
522 * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a mux type clk
523 * @hw: mux type clk to determine rate on
524 * @req: rate request, also used to return preferred parent and frequencies
525 *
527 * Helper for finding best parent to provide a given frequency. This can be used526 * Helper for finding best parent to provide a given frequency. This can be used
528 * directly as a determine_rate callback (e.g. for a mux), or from a more527 * directly as a determine_rate callback (e.g. for a mux), or from a more
529 * complex clock that may combine a mux with other operations.528 * complex clock that may combine a mux with other operations.
529 *
530 * Returns: 0 on success, -EERROR value on error
530 */531 */
531int __clk_mux_determine_rate(struct clk_hw *hw,532int __clk_mux_determine_rate(struct clk_hw *hw,
532 struct clk_rate_request *req)533 struct clk_rate_request *req)
@@ -3318,8 +3319,10 @@ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw, · 2785 unmodified lines
3318 * @dev: device that is registering this clock3319 * @dev: device that is registering this clock
3319 * @hw: link to hardware-specific clock data3320 * @hw: link to hardware-specific clock data
3320 *3321 *
3321 * clk_register is the primary interface for populating the clock tree with new3322 * clk_register is the *deprecated* interface for populating the clock tree with
3322 * clock nodes. It returns a pointer to the newly allocated struct clk which3323 * new clock nodes. Use clk_hw_register() instead.
3324 *
3325 * Returns: a pointer to the newly allocated struct clk which
3323 * cannot be dereferenced by driver code but may be used in conjunction with the3326 * cannot be dereferenced by driver code but may be used in conjunction with the
3324 * rest of the clock API. In the event of an error clk_register will return an3327 * rest of the clock API. In the event of an error clk_register will return an
3325 * error code; drivers must test for an error code after calling clk_register.3328 * error code; drivers must test for an error code after calling clk_register.
@@ -3575,9 +3578,10 @@ static void devm_clk_hw_release(struct device *dev, void *res) · 249 unmodified lines
3575 * @dev: device that is registering this clock3578 * @dev: device that is registering this clock
3576 * @hw: link to hardware-specific clock data3579 * @hw: link to hardware-specific clock data
3577 *3580 *
3578 * Managed clk_register(). Clocks returned from this function are3581 * Managed clk_register(). This function is *deprecated*, use devm_clk_hw_register() instead.
3579 * automatically clk_unregister()ed on driver detach. See clk_register() for3582 *
3580 * more information.3583 * Clocks returned from this function are automatically clk_unregister()ed on
3584 * driver detach. See clk_register() for more information.
3581 */3585 */
3582struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)3586struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
3583{3587{
@@ -3895,6 +3899,8 @@ EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get); · 311 unmodified lines
3895 * @np: Device node pointer associated with clock provider3899 * @np: Device node pointer associated with clock provider
3896 * @clk_src_get: callback for decoding clock3900 * @clk_src_get: callback for decoding clock
3897 * @data: context pointer for @clk_src_get callback.3901 * @data: context pointer for @clk_src_get callback.
3902 *
3903 * This function is *deprecated*. Use of_clk_add_hw_provider() instead.
3898 */3904 */
3899int of_clk_add_provider(struct device_node *np,3905int of_clk_add_provider(struct device_node *np,
3900 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,3906 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
drivers/clk/hisilicon/clk-hisi-phase.c+2−2
@@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees) · 74 unmodified lines
75 75
76 spin_lock_irqsave(phase->lock, flags);76 spin_lock_irqsave(phase->lock, flags);
77 77
78 val = clk_readl(phase->reg);78 val = readl(phase->reg);
79 val &= ~phase->mask;79 val &= ~phase->mask;
80 val |= regval << phase->shift;80 val |= regval << phase->shift;
81 clk_writel(val, phase->reg);81 writel(val, phase->reg);
82 82
83 spin_unlock_irqrestore(phase->lock, flags);83 spin_unlock_irqrestore(phase->lock, flags);
84 84
drivers/clk/imx/clk-divider-gate.c+10−10
@@ -29,7 +29,7 @@ static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw, · 28 unmodified lines
29 struct clk_divider *div = to_clk_divider(hw);29 struct clk_divider *div = to_clk_divider(hw);
30 unsigned int val;30 unsigned int val;
31 31
32 val = clk_readl(div->reg) >> div->shift;32 val = readl(div->reg) >> div->shift;
33 val &= clk_div_mask(div->width);33 val &= clk_div_mask(div->width);
34 if (!val)34 if (!val)
35 return 0;35 return 0;
@@ -51,7 +51,7 @@ static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw, · 15 unmodified lines
51 if (!clk_hw_is_enabled(hw)) {51 if (!clk_hw_is_enabled(hw)) {
52 val = div_gate->cached_val;52 val = div_gate->cached_val;
53 } else {53 } else {
54 val = clk_readl(div->reg) >> div->shift;54 val = readl(div->reg) >> div->shift;
55 val &= clk_div_mask(div->width);55 val &= clk_div_mask(div->width);
56 }56 }
57 57
@@ -87,10 +87,10 @@ static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate, · 29 unmodified lines
87 spin_lock_irqsave(div->lock, flags);87 spin_lock_irqsave(div->lock, flags);
88 88
89 if (clk_hw_is_enabled(hw)) {89 if (clk_hw_is_enabled(hw)) {
90 val = clk_readl(div->reg);90 val = readl(div->reg);
91 val &= ~(clk_div_mask(div->width) << div->shift);91 val &= ~(clk_div_mask(div->width) << div->shift);
92 val |= (u32)value << div->shift;92 val |= (u32)value << div->shift;
93 clk_writel(val, div->reg);93 writel(val, div->reg);
94 } else {94 } else {
95 div_gate->cached_val = value;95 div_gate->cached_val = value;
96 }96 }
@@ -114,9 +114,9 @@ static int clk_divider_enable(struct clk_hw *hw) · 17 unmodified lines
114 114
115 spin_lock_irqsave(div->lock, flags);115 spin_lock_irqsave(div->lock, flags);
116 /* restore div val */116 /* restore div val */
117 val = clk_readl(div->reg);117 val = readl(div->reg);
118 val |= div_gate->cached_val << div->shift;118 val |= div_gate->cached_val << div->shift;
119 clk_writel(val, div->reg);119 writel(val, div->reg);
120 120
121 spin_unlock_irqrestore(div->lock, flags);121 spin_unlock_irqrestore(div->lock, flags);
122 122
@@ -133,10 +133,10 @@ static void clk_divider_disable(struct clk_hw *hw) · 10 unmodified lines
133 spin_lock_irqsave(div->lock, flags);133 spin_lock_irqsave(div->lock, flags);
134 134
135 /* store the current div val */135 /* store the current div val */
136 val = clk_readl(div->reg) >> div->shift;136 val = readl(div->reg) >> div->shift;
137 val &= clk_div_mask(div->width);137 val &= clk_div_mask(div->width);
138 div_gate->cached_val = val;138 div_gate->cached_val = val;
139 clk_writel(0, div->reg);139 writel(0, div->reg);
140 140
141 spin_unlock_irqrestore(div->lock, flags);141 spin_unlock_irqrestore(div->lock, flags);
142}142}
@@ -146,7 +146,7 @@ static int clk_divider_is_enabled(struct clk_hw *hw) · 3 unmodified lines
146 struct clk_divider *div = to_clk_divider(hw);146 struct clk_divider *div = to_clk_divider(hw);
147 u32 val;147 u32 val;
148 148
149 val = clk_readl(div->reg) >> div->shift;149 val = readl(div->reg) >> div->shift;
150 val &= clk_div_mask(div->width);150 val &= clk_div_mask(div->width);
151 151
152 return val ? 1 : 0;152 return val ? 1 : 0;
@@ -206,7 +206,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, · 53 unmodified lines
206 div_gate->divider.hw.init = &init;206 div_gate->divider.hw.init = &init;
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
208 /* cache gate status */208 /* cache gate status */
209 val = clk_readl(reg) >> shift;209 val = readl(reg) >> shift;
210 val &= clk_div_mask(width);210 val &= clk_div_mask(width);
211 div_gate->cached_val = val;211 div_gate->cached_val = val;
212 212
drivers/clk/imx/clk-sccg-pll.c+6−6
@@ -348,7 +348,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw, · 347 unmodified lines
348 348
349 temp64 = parent_rate;349 temp64 = parent_rate;
350 350
351 val = clk_readl(pll->base + PLL_CFG0);351 val = readl(pll->base + PLL_CFG0);
352 if (val & SSCG_PLL_BYPASS2_MASK) {352 if (val & SSCG_PLL_BYPASS2_MASK) {
353 temp64 = parent_rate;353 temp64 = parent_rate;
354 } else if (val & SSCG_PLL_BYPASS1_MASK) {354 } else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -371,10 +371,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate, · 16 unmodified lines
371 u32 val;371 u32 val;
372 372
373 /* set bypass here too since the parent might be the same */373 /* set bypass here too since the parent might be the same */
374 val = clk_readl(pll->base + PLL_CFG0);374 val = readl(pll->base + PLL_CFG0);
375 val &= ~SSCG_PLL_BYPASS_MASK;375 val &= ~SSCG_PLL_BYPASS_MASK;
376 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);376 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
377 clk_writel(val, pll->base + PLL_CFG0);377 writel(val, pll->base + PLL_CFG0);
378 378
379 val = readl_relaxed(pll->base + PLL_CFG2);379 val = readl_relaxed(pll->base + PLL_CFG2);
380 val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);380 val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -395,7 +395,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw) · 14 unmodified lines
395 u32 val;395 u32 val;
396 u8 ret = pll->parent;396 u8 ret = pll->parent;
397 397
398 val = clk_readl(pll->base + PLL_CFG0);398 val = readl(pll->base + PLL_CFG0);
399 if (val & SSCG_PLL_BYPASS2_MASK)399 if (val & SSCG_PLL_BYPASS2_MASK)
400 ret = pll->bypass2;400 ret = pll->bypass2;
401 else if (val & SSCG_PLL_BYPASS1_MASK)401 else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -408,10 +408,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index) · 6 unmodified lines
408 struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);408 struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
409 u32 val;409 u32 val;
410 410
411 val = clk_readl(pll->base + PLL_CFG0);411 val = readl(pll->base + PLL_CFG0);
412 val &= ~SSCG_PLL_BYPASS_MASK;412 val &= ~SSCG_PLL_BYPASS_MASK;
413 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);413 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
414 clk_writel(val, pll->base + PLL_CFG0);414 writel(val, pll->base + PLL_CFG0);
415 415
416 return clk_sccg_pll_wait_lock(pll);416 return clk_sccg_pll_wait_lock(pll);
417}417}
drivers/clk/meson/axg-audio.c+718−501
@@ -20,18 +20,18 @@ · 19 unmodified lines
20#include "clk-phase.h"20#include "clk-phase.h"
21#include "sclk-div.h"21#include "sclk-div.h"
22 22
23#define AXG_MST_IN_COUNT 823#define AUD_MST_IN_COUNT 8
24#define AXG_SLV_SCLK_COUNT 1024#define AUD_SLV_SCLK_COUNT 10
25#define AXG_SLV_LRCLK_COUNT 1025#define AUD_SLV_LRCLK_COUNT 10
26 26
27#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \27#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \
28struct clk_regmap axg_##_name = { \28struct clk_regmap aud_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \29 .data = &(struct clk_regmap_gate_data){ \
30 .offset = (_reg), \30 .offset = (_reg), \
31 .bit_idx = (_bit), \31 .bit_idx = (_bit), \
32 }, \32 }, \
33 .hw.init = &(struct clk_init_data) { \33 .hw.init = &(struct clk_init_data) { \
34 .name = "axg_"#_name, \34 .name = "aud_"#_name, \
35 .ops = &clk_regmap_gate_ops, \35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \36 .parent_names = (const char *[]){ _pname }, \
37 .num_parents = 1, \37 .num_parents = 1, \
@@ -39,8 +39,8 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
39 }, \39 }, \
40}40}
41 41
42#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \42#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
43struct clk_regmap axg_##_name = { \43struct clk_regmap aud_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \44 .data = &(struct clk_regmap_mux_data){ \
45 .offset = (_reg), \45 .offset = (_reg), \
46 .mask = (_mask), \46 .mask = (_mask), \
@@ -48,7 +48,7 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
48 .flags = (_dflags), \48 .flags = (_dflags), \
49 }, \49 }, \
50 .hw.init = &(struct clk_init_data){ \50 .hw.init = &(struct clk_init_data){ \
51 .name = "axg_"#_name, \51 .name = "aud_"#_name, \
52 .ops = &clk_regmap_mux_ops, \52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \53 .parent_names = (_pnames), \
54 .num_parents = ARRAY_SIZE(_pnames), \54 .num_parents = ARRAY_SIZE(_pnames), \
@@ -56,8 +56,8 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
56 }, \56 }, \
57}57}
58 58
59#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \59#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
60struct clk_regmap axg_##_name = { \60struct clk_regmap aud_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \61 .data = &(struct clk_regmap_div_data){ \
62 .offset = (_reg), \62 .offset = (_reg), \
63 .shift = (_shift), \63 .shift = (_shift), \
@@ -65,7 +65,7 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
65 .flags = (_dflags), \65 .flags = (_dflags), \
66 }, \66 }, \
67 .hw.init = &(struct clk_init_data){ \67 .hw.init = &(struct clk_init_data){ \
68 .name = "axg_"#_name, \68 .name = "aud_"#_name, \
69 .ops = &clk_regmap_divider_ops, \69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \70 .parent_names = (const char *[]) { _pname }, \
71 .num_parents = 1, \71 .num_parents = 1, \
@@ -73,109 +73,113 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
73 }, \73 }, \
74}74}
75 75
76#define AXG_PCLK_GATE(_name, _bit) \76#define AUD_PCLK_GATE(_name, _bit) \
77 AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)
78 78
79/* Audio peripheral clocks */79/* Audio peripheral clocks */
80static AXG_PCLK_GATE(ddr_arb, 0);80static AUD_PCLK_GATE(ddr_arb, 0);
81static AXG_PCLK_GATE(pdm, 1);81static AUD_PCLK_GATE(pdm, 1);
82static AXG_PCLK_GATE(tdmin_a, 2);82static AUD_PCLK_GATE(tdmin_a, 2);
83static AXG_PCLK_GATE(tdmin_b, 3);83static AUD_PCLK_GATE(tdmin_b, 3);
84static AXG_PCLK_GATE(tdmin_c, 4);84static AUD_PCLK_GATE(tdmin_c, 4);
85static AXG_PCLK_GATE(tdmin_lb, 5);85static AUD_PCLK_GATE(tdmin_lb, 5);
86static AXG_PCLK_GATE(tdmout_a, 6);86static AUD_PCLK_GATE(tdmout_a, 6);
87static AXG_PCLK_GATE(tdmout_b, 7);87static AUD_PCLK_GATE(tdmout_b, 7);
88static AXG_PCLK_GATE(tdmout_c, 8);88static AUD_PCLK_GATE(tdmout_c, 8);
89static AXG_PCLK_GATE(frddr_a, 9);89static AUD_PCLK_GATE(frddr_a, 9);
90static AXG_PCLK_GATE(frddr_b, 10);90static AUD_PCLK_GATE(frddr_b, 10);
91static AXG_PCLK_GATE(frddr_c, 11);91static AUD_PCLK_GATE(frddr_c, 11);
92static AXG_PCLK_GATE(toddr_a, 12);92static AUD_PCLK_GATE(toddr_a, 12);
93static AXG_PCLK_GATE(toddr_b, 13);93static AUD_PCLK_GATE(toddr_b, 13);
94static AXG_PCLK_GATE(toddr_c, 14);94static AUD_PCLK_GATE(toddr_c, 14);
95static AXG_PCLK_GATE(loopback, 15);95static AUD_PCLK_GATE(loopback, 15);
96static AXG_PCLK_GATE(spdifin, 16);96static AUD_PCLK_GATE(spdifin, 16);
97static AXG_PCLK_GATE(spdifout, 17);97static AUD_PCLK_GATE(spdifout, 17);
98static AXG_PCLK_GATE(resample, 18);98static AUD_PCLK_GATE(resample, 18);
99static AXG_PCLK_GATE(power_detect, 19);99static AUD_PCLK_GATE(power_detect, 19);
100static AUD_PCLK_GATE(spdifout_b, 21);
100 101
101/* Audio Master Clocks */102/* Audio Master Clocks */
102static const char * const mst_mux_parent_names[] = {103static const char * const mst_mux_parent_names[] = {
103 "axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3",104 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",
104 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",105 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",
105};106};
106 107
107#define AXG_MST_MUX(_name, _reg, _flag) \108#define AUD_MST_MUX(_name, _reg, _flag) \
108 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \109 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
109 mst_mux_parent_names, CLK_SET_RATE_PARENT)110 mst_mux_parent_names, CLK_SET_RATE_PARENT)
110 111
111#define AXG_MST_MCLK_MUX(_name, _reg) \112#define AUD_MST_MCLK_MUX(_name, _reg) \
112 AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)113 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
113 114
114#define AXG_MST_SYS_MUX(_name, _reg) \115#define AUD_MST_SYS_MUX(_name, _reg) \
115 AXG_MST_MUX(_name, _reg, 0)116 AUD_MST_MUX(_name, _reg, 0)
116 117
117static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);118static AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
118static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);119static AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
119static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);120static AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
120static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);121static AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
121static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);122static AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
122static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);123static AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
123static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);124static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
124static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);125static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
125static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);126static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
126static AXG_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);127static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
127 128static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
128#define AXG_MST_DIV(_name, _reg, _flag) \129
129 AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag, \130#define AUD_MST_DIV(_name, _reg, _flag) \
130 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \131 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
131 132 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \
132#define AXG_MST_MCLK_DIV(_name, _reg) \133
133 AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)134#define AUD_MST_MCLK_DIV(_name, _reg) \
134 135 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
135#define AXG_MST_SYS_DIV(_name, _reg) \136
136 AXG_MST_DIV(_name, _reg, 0)137#define AUD_MST_SYS_DIV(_name, _reg) \
137 138 AUD_MST_DIV(_name, _reg, 0)
138static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);139
139static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);140static AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
140static AXG_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);141static AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
141static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);142static AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
142static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);143static AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
143static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);144static AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
144static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);145static AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
145static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);146static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
146static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);147static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
147static AXG_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);148static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
148 149static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
149#define AXG_MST_MCLK_GATE(_name, _reg) \150static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
150 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \151
151 CLK_SET_RATE_PARENT)152#define AUD_MST_MCLK_GATE(_name, _reg) \
152 153 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \
153static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);154 CLK_SET_RATE_PARENT)
154static AXG_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);155
155static AXG_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);156static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
156static AXG_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);157static AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
157static AXG_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);158static AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
158static AXG_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);159static AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
159static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);160static AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
160static AXG_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);161static AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
161static AXG_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);162static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
162static AXG_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);163static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
164static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
165static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
166static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
163 167
164/* Sample Clocks */168/* Sample Clocks */
165#define AXG_MST_SCLK_PRE_EN(_name, _reg) \169#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
166 AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \170 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
167 "axg_mst_"#_name"_mclk", 0)171 "aud_mst_"#_name"_mclk", 0)
168 172
169static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);173static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
170static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);174static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
171static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);175static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
172static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);176static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
173static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);177static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
174static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);178static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
175 179
176#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \180#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
177 _hi_shift, _hi_width, _pname, _iflags) \181 _hi_shift, _hi_width, _pname, _iflags) \
178struct clk_regmap axg_##_name = { \182struct clk_regmap aud_##_name = { \
179 .data = &(struct meson_sclk_div_data) { \183 .data = &(struct meson_sclk_div_data) { \
180 .div = { \184 .div = { \
181 .reg_off = (_reg), \185 .reg_off = (_reg), \
@@ -189,7 +193,7 @@ struct clk_regmap axg_##_name = { \ · 7 unmodified lines
189 }, \193 }, \
190 }, \194 }, \
191 .hw.init = &(struct clk_init_data) { \195 .hw.init = &(struct clk_init_data) { \
192 .name = "axg_"#_name, \196 .name = "aud_"#_name, \
193 .ops = &meson_sclk_div_ops, \197 .ops = &meson_sclk_div_ops, \
194 .parent_names = (const char *[]) { _pname }, \198 .parent_names = (const char *[]) { _pname }, \
195 .num_parents = 1, \199 .num_parents = 1, \
@@ -197,32 +201,32 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
197 }, \201 }, \
198}202}
199 203
200#define AXG_MST_SCLK_DIV(_name, _reg) \204#define AUD_MST_SCLK_DIV(_name, _reg) \
201 AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \205 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
202 "axg_mst_"#_name"_sclk_pre_en", \206 "aud_mst_"#_name"_sclk_pre_en", \
203 CLK_SET_RATE_PARENT)207 CLK_SET_RATE_PARENT)
204 208
205static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);209static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
206static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);210static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
207static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);211static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
208static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);212static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
209static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);213static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
210static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);214static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
211 215
212#define AXG_MST_SCLK_POST_EN(_name, _reg) \216#define AUD_MST_SCLK_POST_EN(_name, _reg) \
213 AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \217 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
214 "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)218 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
215 219
216static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);220static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
217static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);221static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
218static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);222static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
219static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);223static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
220static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);224static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
221static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);225static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
222 226
223#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \227#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
224 _pname, _iflags) \228 _pname, _iflags) \
225struct clk_regmap axg_##_name = { \229struct clk_regmap aud_##_name = { \
226 .data = &(struct meson_clk_triphase_data) { \230 .data = &(struct meson_clk_triphase_data) { \
227 .ph0 = { \231 .ph0 = { \
228 .reg_off = (_reg), \232 .reg_off = (_reg), \
@@ -241,7 +245,7 @@ struct clk_regmap axg_##_name = { \ · 12 unmodified lines
241 }, \245 }, \
242 }, \246 }, \
243 .hw.init = &(struct clk_init_data) { \247 .hw.init = &(struct clk_init_data) { \
244 .name = "axg_"#_name, \248 .name = "aud_"#_name, \
245 .ops = &meson_clk_triphase_ops, \249 .ops = &meson_clk_triphase_ops, \
246 .parent_names = (const char *[]) { _pname }, \250 .parent_names = (const char *[]) { _pname }, \
247 .num_parents = 1, \251 .num_parents = 1, \
@@ -249,87 +253,87 @@ struct clk_regmap axg_##_name = { \ · 1 unmodified line
249 }, \253 }, \
250}254}
251 255
252#define AXG_MST_SCLK(_name, _reg) \256#define AUD_MST_SCLK(_name, _reg) \
253 AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \257 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
254 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)258 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
255 259
256static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);260static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
257static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);261static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
258static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);262static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
259static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);263static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
260static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);264static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
261static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);265static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
262 266
263#define AXG_MST_LRCLK_DIV(_name, _reg) \267#define AUD_MST_LRCLK_DIV(_name, _reg) \
264 AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \268 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
265 "axg_mst_"#_name"_sclk_post_en", 0) \269 "aud_mst_"#_name"_sclk_post_en", 0) \
266 270
267static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);271static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
268static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);272static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
269static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);273static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
270static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);274static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
271static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);275static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
272static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);276static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
273 277
274#define AXG_MST_LRCLK(_name, _reg) \278#define AUD_MST_LRCLK(_name, _reg) \
275 AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \279 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
276 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)280 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
277 281
278static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);282static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
279static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);283static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
280static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);284static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
281static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);285static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
282static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);286static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
283static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);287static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
284 288
285static const char * const tdm_sclk_parent_names[] = {289static const char * const tdm_sclk_parent_names[] = {
286 "axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk",290 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
287 "axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk",291 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
288 "axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2",292 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",
289 "axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5",293 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",
290 "axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8",294 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",
291 "axg_slv_sclk9"295 "aud_slv_sclk9"
292};296};
293 297
294#define AXG_TDM_SCLK_MUX(_name, _reg) \298#define AUD_TDM_SCLK_MUX(_name, _reg) \
295 AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \299 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
296 CLK_MUX_ROUND_CLOSEST, \300 CLK_MUX_ROUND_CLOSEST, \
297 tdm_sclk_parent_names, 0)301 tdm_sclk_parent_names, 0)
298 302
299static AXG_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);303static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
300static AXG_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);304static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
301static AXG_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);305static AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
302static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);306static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
303static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);307static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
304static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);308static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
305static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);309static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
306 310
307#define AXG_TDM_SCLK_PRE_EN(_name, _reg) \311#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
308 AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \312 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
309 "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)313 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
310 314
311static AXG_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);315static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
312static AXG_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);316static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
313static AXG_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);317static AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
314static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);318static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
315static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);319static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
316static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);320static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
317static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);321static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
318 322
319#define AXG_TDM_SCLK_POST_EN(_name, _reg) \323#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
320 AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \324 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
321 "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)325 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
322 326
323static AXG_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);327static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
324static AXG_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);328static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
325static AXG_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);329static AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
326static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);330static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
327static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);331static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
328static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);332static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
329static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);333static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
330 334
331#define AXG_TDM_SCLK(_name, _reg) \335#define AUD_TDM_SCLK(_name, _reg) \
332 struct clk_regmap axg_tdm##_name##_sclk = { \336 struct clk_regmap aud_tdm##_name##_sclk = { \
333 .data = &(struct meson_clk_phase_data) { \337 .data = &(struct meson_clk_phase_data) { \
334 .ph = { \338 .ph = { \
335 .reg_off = (_reg), \339 .reg_off = (_reg), \
@@ -338,44 +342,83 @@ static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 2 unmodified lines
338 }, \342 }, \
339 }, \343 }, \
340 .hw.init = &(struct clk_init_data) { \344 .hw.init = &(struct clk_init_data) { \
341 .name = "axg_tdm"#_name"_sclk", \345 .name = "aud_tdm"#_name"_sclk", \
342 .ops = &meson_clk_phase_ops, \346 .ops = &meson_clk_phase_ops, \
343 .parent_names = (const char *[]) \347 .parent_names = (const char *[]) \
344 { "axg_tdm"#_name"_sclk_post_en" }, \348 { "aud_tdm"#_name"_sclk_post_en" }, \
345 .num_parents = 1, \349 .num_parents = 1, \
346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \350 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
347 }, \351 }, \
348}352}
349 353
350static AXG_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);354static AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
351static AXG_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);355static AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
352static AXG_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);356static AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
353static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);357static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
354static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);358static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
355static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);359static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
356static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);360static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
357 361
358static const char * const tdm_lrclk_parent_names[] = {362static const char * const tdm_lrclk_parent_names[] = {
359 "axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk",363 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
360 "axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk",364 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
361 "axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2",365 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",
362 "axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5",366 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",
363 "axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8",367 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",
364 "axg_slv_lrclk9"368 "aud_slv_lrclk9"
365};369};
366 370
367#define AXG_TDM_LRLCK(_name, _reg) \371#define AUD_TDM_LRLCK(_name, _reg) \
368 AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \372 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
369 CLK_MUX_ROUND_CLOSEST, \373 CLK_MUX_ROUND_CLOSEST, \
370 tdm_lrclk_parent_names, 0)374 tdm_lrclk_parent_names, 0)
375
376static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
377static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
378static AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
379static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
380static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
381static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
382static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
383
384/* G12a Pad control */
385#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
386 AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
387 CLK_SET_RATE_NO_REPARENT)
388
389static const char * const mclk_pad_ctrl_parent_names[] = {
390 "aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",
391 "aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",
392};
393
394static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
395 mclk_pad_ctrl_parent_names);
396static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
397 mclk_pad_ctrl_parent_names);
398
399static const char * const lrclk_pad_ctrl_parent_names[] = {
400 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
401 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
402};
371 403
372static AXG_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);404static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
373static AXG_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);405 lrclk_pad_ctrl_parent_names);
374static AXG_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);406static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
375static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);407 lrclk_pad_ctrl_parent_names);
376static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);408static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
377static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);409 lrclk_pad_ctrl_parent_names);
378static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);410
411static const char * const sclk_pad_ctrl_parent_names[] = {
412 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
413 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
414};
415
416static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
417 sclk_pad_ctrl_parent_names);
418static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
419 sclk_pad_ctrl_parent_names);
420static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
421 sclk_pad_ctrl_parent_names);
379 422
380/*423/*
381 * Array of all clocks provided by this provider424 * Array of all clocks provided by this provider
@@ -383,255 +426,416 @@ static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 1 unmodified line
383 */426 */
384static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {427static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
385 .hws = {428 .hws = {
386 [AUD_CLKID_DDR_ARB] = &axg_ddr_arb.hw,429 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
387 [AUD_CLKID_PDM] = &axg_pdm.hw,430 [AUD_CLKID_PDM] = &aud_pdm.hw,
388 [AUD_CLKID_TDMIN_A] = &axg_tdmin_a.hw,431 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
389 [AUD_CLKID_TDMIN_B] = &axg_tdmin_b.hw,432 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
390 [AUD_CLKID_TDMIN_C] = &axg_tdmin_c.hw,433 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
391 [AUD_CLKID_TDMIN_LB] = &axg_tdmin_lb.hw,434 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
392 [AUD_CLKID_TDMOUT_A] = &axg_tdmout_a.hw,435 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
393 [AUD_CLKID_TDMOUT_B] = &axg_tdmout_b.hw,436 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
394 [AUD_CLKID_TDMOUT_C] = &axg_tdmout_c.hw,437 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
395 [AUD_CLKID_FRDDR_A] = &axg_frddr_a.hw,438 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
396 [AUD_CLKID_FRDDR_B] = &axg_frddr_b.hw,439 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
397 [AUD_CLKID_FRDDR_C] = &axg_frddr_c.hw,440 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
398 [AUD_CLKID_TODDR_A] = &axg_toddr_a.hw,441 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
399 [AUD_CLKID_TODDR_B] = &axg_toddr_b.hw,442 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
400 [AUD_CLKID_TODDR_C] = &axg_toddr_c.hw,443 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
401 [AUD_CLKID_LOOPBACK] = &axg_loopback.hw,444 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
402 [AUD_CLKID_SPDIFIN] = &axg_spdifin.hw,445 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
403 [AUD_CLKID_SPDIFOUT] = &axg_spdifout.hw,446 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
404 [AUD_CLKID_RESAMPLE] = &axg_resample.hw,447 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
405 [AUD_CLKID_POWER_DETECT] = &axg_power_detect.hw,448 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
406 [AUD_CLKID_MST_A_MCLK_SEL] = &axg_mst_a_mclk_sel.hw,449 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
407 [AUD_CLKID_MST_B_MCLK_SEL] = &axg_mst_b_mclk_sel.hw,450 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
408 [AUD_CLKID_MST_C_MCLK_SEL] = &axg_mst_c_mclk_sel.hw,451 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
409 [AUD_CLKID_MST_D_MCLK_SEL] = &axg_mst_d_mclk_sel.hw,452 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
410 [AUD_CLKID_MST_E_MCLK_SEL] = &axg_mst_e_mclk_sel.hw,453 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
411 [AUD_CLKID_MST_F_MCLK_SEL] = &axg_mst_f_mclk_sel.hw,454 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
412 [AUD_CLKID_MST_A_MCLK_DIV] = &axg_mst_a_mclk_div.hw,455 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
413 [AUD_CLKID_MST_B_MCLK_DIV] = &axg_mst_b_mclk_div.hw,456 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
414 [AUD_CLKID_MST_C_MCLK_DIV] = &axg_mst_c_mclk_div.hw,457 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
415 [AUD_CLKID_MST_D_MCLK_DIV] = &axg_mst_d_mclk_div.hw,458 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
416 [AUD_CLKID_MST_E_MCLK_DIV] = &axg_mst_e_mclk_div.hw,459 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
417 [AUD_CLKID_MST_F_MCLK_DIV] = &axg_mst_f_mclk_div.hw,460 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
418 [AUD_CLKID_MST_A_MCLK] = &axg_mst_a_mclk.hw,461 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
419 [AUD_CLKID_MST_B_MCLK] = &axg_mst_b_mclk.hw,462 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
420 [AUD_CLKID_MST_C_MCLK] = &axg_mst_c_mclk.hw,463 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
421 [AUD_CLKID_MST_D_MCLK] = &axg_mst_d_mclk.hw,464 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
422 [AUD_CLKID_MST_E_MCLK] = &axg_mst_e_mclk.hw,465 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
423 [AUD_CLKID_MST_F_MCLK] = &axg_mst_f_mclk.hw,466 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &axg_spdifout_clk_sel.hw,467 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &axg_spdifout_clk_div.hw,468 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
426 [AUD_CLKID_SPDIFOUT_CLK] = &axg_spdifout_clk.hw,469 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &axg_spdifin_clk_sel.hw,470 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &axg_spdifin_clk_div.hw,471 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
429 [AUD_CLKID_SPDIFIN_CLK] = &axg_spdifin_clk.hw,472 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
430 [AUD_CLKID_PDM_DCLK_SEL] = &axg_pdm_dclk_sel.hw,473 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
431 [AUD_CLKID_PDM_DCLK_DIV] = &axg_pdm_dclk_div.hw,474 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
432 [AUD_CLKID_PDM_DCLK] = &axg_pdm_dclk.hw,475 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
433 [AUD_CLKID_PDM_SYSCLK_SEL] = &axg_pdm_sysclk_sel.hw,476 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
434 [AUD_CLKID_PDM_SYSCLK_DIV] = &axg_pdm_sysclk_div.hw,477 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
435 [AUD_CLKID_PDM_SYSCLK] = &axg_pdm_sysclk.hw,478 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &axg_mst_a_sclk_pre_en.hw,479 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &axg_mst_b_sclk_pre_en.hw,480 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &axg_mst_c_sclk_pre_en.hw,481 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &axg_mst_d_sclk_pre_en.hw,482 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &axg_mst_e_sclk_pre_en.hw,483 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &axg_mst_f_sclk_pre_en.hw,484 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
442 [AUD_CLKID_MST_A_SCLK_DIV] = &axg_mst_a_sclk_div.hw,485 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
443 [AUD_CLKID_MST_B_SCLK_DIV] = &axg_mst_b_sclk_div.hw,486 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
444 [AUD_CLKID_MST_C_SCLK_DIV] = &axg_mst_c_sclk_div.hw,487 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
445 [AUD_CLKID_MST_D_SCLK_DIV] = &axg_mst_d_sclk_div.hw,488 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
446 [AUD_CLKID_MST_E_SCLK_DIV] = &axg_mst_e_sclk_div.hw,489 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
447 [AUD_CLKID_MST_F_SCLK_DIV] = &axg_mst_f_sclk_div.hw,490 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &axg_mst_a_sclk_post_en.hw,491 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &axg_mst_b_sclk_post_en.hw,492 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &axg_mst_c_sclk_post_en.hw,493 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &axg_mst_d_sclk_post_en.hw,494 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &axg_mst_e_sclk_post_en.hw,495 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &axg_mst_f_sclk_post_en.hw,496 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
454 [AUD_CLKID_MST_A_SCLK] = &axg_mst_a_sclk.hw,497 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
455 [AUD_CLKID_MST_B_SCLK] = &axg_mst_b_sclk.hw,498 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
456 [AUD_CLKID_MST_C_SCLK] = &axg_mst_c_sclk.hw,499 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
457 [AUD_CLKID_MST_D_SCLK] = &axg_mst_d_sclk.hw,500 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
458 [AUD_CLKID_MST_E_SCLK] = &axg_mst_e_sclk.hw,501 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
459 [AUD_CLKID_MST_F_SCLK] = &axg_mst_f_sclk.hw,502 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
460 [AUD_CLKID_MST_A_LRCLK_DIV] = &axg_mst_a_lrclk_div.hw,503 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
461 [AUD_CLKID_MST_B_LRCLK_DIV] = &axg_mst_b_lrclk_div.hw,504 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
462 [AUD_CLKID_MST_C_LRCLK_DIV] = &axg_mst_c_lrclk_div.hw,505 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
463 [AUD_CLKID_MST_D_LRCLK_DIV] = &axg_mst_d_lrclk_div.hw,506 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
464 [AUD_CLKID_MST_E_LRCLK_DIV] = &axg_mst_e_lrclk_div.hw,507 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
465 [AUD_CLKID_MST_F_LRCLK_DIV] = &axg_mst_f_lrclk_div.hw,508 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
466 [AUD_CLKID_MST_A_LRCLK] = &axg_mst_a_lrclk.hw,509 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
467 [AUD_CLKID_MST_B_LRCLK] = &axg_mst_b_lrclk.hw,510 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
468 [AUD_CLKID_MST_C_LRCLK] = &axg_mst_c_lrclk.hw,511 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
469 [AUD_CLKID_MST_D_LRCLK] = &axg_mst_d_lrclk.hw,512 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
470 [AUD_CLKID_MST_E_LRCLK] = &axg_mst_e_lrclk.hw,513 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
471 [AUD_CLKID_MST_F_LRCLK] = &axg_mst_f_lrclk.hw,514 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &axg_tdmin_a_sclk_sel.hw,515 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &axg_tdmin_b_sclk_sel.hw,516 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &axg_tdmin_c_sclk_sel.hw,517 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &axg_tdmin_lb_sclk_sel.hw,518 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &axg_tdmout_a_sclk_sel.hw,519 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &axg_tdmout_b_sclk_sel.hw,520 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &axg_tdmout_c_sclk_sel.hw,521 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &axg_tdmin_a_sclk_pre_en.hw,522 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &axg_tdmin_b_sclk_pre_en.hw,523 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &axg_tdmin_c_sclk_pre_en.hw,524 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw,525 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw,526 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw,527 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw,528 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw,529 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw,530 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw,531 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw,532 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw,533 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw,534 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw,535 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
493 [AUD_CLKID_TDMIN_A_SCLK] = &axg_tdmin_a_sclk.hw,536 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
494 [AUD_CLKID_TDMIN_B_SCLK] = &axg_tdmin_b_sclk.hw,537 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
495 [AUD_CLKID_TDMIN_C_SCLK] = &axg_tdmin_c_sclk.hw,538 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
496 [AUD_CLKID_TDMIN_LB_SCLK] = &axg_tdmin_lb_sclk.hw,539 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
497 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,540 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
498 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,541 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
499 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,542 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
500 [AUD_CLKID_TDMIN_A_LRCLK] = &axg_tdmin_a_lrclk.hw,543 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
501 [AUD_CLKID_TDMIN_B_LRCLK] = &axg_tdmin_b_lrclk.hw,544 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
502 [AUD_CLKID_TDMIN_C_LRCLK] = &axg_tdmin_c_lrclk.hw,545 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
503 [AUD_CLKID_TDMIN_LB_LRCLK] = &axg_tdmin_lb_lrclk.hw,546 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
504 [AUD_CLKID_TDMOUT_A_LRCLK] = &axg_tdmout_a_lrclk.hw,547 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
505 [AUD_CLKID_TDMOUT_B_LRCLK] = &axg_tdmout_b_lrclk.hw,548 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
506 [AUD_CLKID_TDMOUT_C_LRCLK] = &axg_tdmout_c_lrclk.hw,549 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
507 [NR_CLKS] = NULL,550 [NR_CLKS] = NULL,
508 },551 },
509 .num = NR_CLKS,552 .num = NR_CLKS,
510};553};
511 554
512/* Convenience table to populate regmap in .probe() */555/*
513static struct clk_regmap *const axg_audio_clk_regmaps[] = {556 * Array of all G12A clocks provided by this provider
514 &axg_ddr_arb,557 * The input clocks of the controller will be populated at runtime
515 &axg_pdm,558 */
516 &axg_tdmin_a,559static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
517 &axg_tdmin_b,560 .hws = {
518 &axg_tdmin_c,561 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
519 &axg_tdmin_lb,562 [AUD_CLKID_PDM] = &aud_pdm.hw,
520 &axg_tdmout_a,563 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
521 &axg_tdmout_b,564 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
522 &axg_tdmout_c,565 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
523 &axg_frddr_a,566 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
524 &axg_frddr_b,567 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
525 &axg_frddr_c,568 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
526 &axg_toddr_a,569 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
527 &axg_toddr_b,570 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
528 &axg_toddr_c,571 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
529 &axg_loopback,572 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
530 &axg_spdifin,573 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
531 &axg_spdifout,574 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
532 &axg_resample,575 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
533 &axg_power_detect,576 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
534 &axg_mst_a_mclk_sel,577 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
535 &axg_mst_b_mclk_sel,578 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
536 &axg_mst_c_mclk_sel,579 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
537 &axg_mst_d_mclk_sel,580 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
538 &axg_mst_e_mclk_sel,581 [AUD_CLKID_SPDIFOUT_B] = &aud_spdifout_b.hw,
539 &axg_mst_f_mclk_sel,582 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
540 &axg_mst_a_mclk_div,583 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
541 &axg_mst_b_mclk_div,584 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
542 &axg_mst_c_mclk_div,585 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
543 &axg_mst_d_mclk_div,586 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
544 &axg_mst_e_mclk_div,587 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
545 &axg_mst_f_mclk_div,588 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
546 &axg_mst_a_mclk,589 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
547 &axg_mst_b_mclk,590 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
548 &axg_mst_c_mclk,591 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
549 &axg_mst_d_mclk,592 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
550 &axg_mst_e_mclk,593 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
551 &axg_mst_f_mclk,594 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
552 &axg_spdifout_clk_sel,595 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
553 &axg_spdifout_clk_div,596 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
554 &axg_spdifout_clk,597 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
555 &axg_spdifin_clk_sel,598 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
556 &axg_spdifin_clk_div,599 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
557 &axg_spdifin_clk,600 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
558 &axg_pdm_dclk_sel,601 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
559 &axg_pdm_dclk_div,602 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
560 &axg_pdm_dclk,603 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &aud_spdifout_b_clk_sel.hw,
561 &axg_pdm_sysclk_sel,604 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &aud_spdifout_b_clk_div.hw,
562 &axg_pdm_sysclk_div,605 [AUD_CLKID_SPDIFOUT_B_CLK] = &aud_spdifout_b_clk.hw,
563 &axg_pdm_sysclk,606 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
564 &axg_mst_a_sclk_pre_en,607 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
565 &axg_mst_b_sclk_pre_en,608 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
566 &axg_mst_c_sclk_pre_en,609 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
567 &axg_mst_d_sclk_pre_en,610 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
568 &axg_mst_e_sclk_pre_en,611 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
569 &axg_mst_f_sclk_pre_en,612 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
570 &axg_mst_a_sclk_div,613 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
571 &axg_mst_b_sclk_div,614 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
572 &axg_mst_c_sclk_div,615 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
573 &axg_mst_d_sclk_div,616 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
574 &axg_mst_e_sclk_div,617 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
575 &axg_mst_f_sclk_div,618 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
576 &axg_mst_a_sclk_post_en,619 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
577 &axg_mst_b_sclk_post_en,620 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
578 &axg_mst_c_sclk_post_en,621 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
579 &axg_mst_d_sclk_post_en,622 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
580 &axg_mst_e_sclk_post_en,623 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
581 &axg_mst_f_sclk_post_en,624 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
582 &axg_mst_a_sclk,625 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
583 &axg_mst_b_sclk,626 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
584 &axg_mst_c_sclk,627 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
585 &axg_mst_d_sclk,628 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
586 &axg_mst_e_sclk,629 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
587 &axg_mst_f_sclk,630 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
588 &axg_mst_a_lrclk_div,631 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
589 &axg_mst_b_lrclk_div,632 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
590 &axg_mst_c_lrclk_div,633 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
591 &axg_mst_d_lrclk_div,634 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
592 &axg_mst_e_lrclk_div,635 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
593 &axg_mst_f_lrclk_div,636 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
594 &axg_mst_a_lrclk,637 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
595 &axg_mst_b_lrclk,638 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
596 &axg_mst_c_lrclk,639 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
597 &axg_mst_d_lrclk,640 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
598 &axg_mst_e_lrclk,641 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
599 &axg_mst_f_lrclk,642 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
600 &axg_tdmin_a_sclk_sel,643 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
601 &axg_tdmin_b_sclk_sel,644 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
602 &axg_tdmin_c_sclk_sel,645 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
603 &axg_tdmin_lb_sclk_sel,646 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
604 &axg_tdmout_a_sclk_sel,647 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
605 &axg_tdmout_b_sclk_sel,648 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
606 &axg_tdmout_c_sclk_sel,649 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
607 &axg_tdmin_a_sclk_pre_en,650 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
608 &axg_tdmin_b_sclk_pre_en,651 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
609 &axg_tdmin_c_sclk_pre_en,652 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
610 &axg_tdmin_lb_sclk_pre_en,653 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
611 &axg_tdmout_a_sclk_pre_en,654 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
612 &axg_tdmout_b_sclk_pre_en,655 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
613 &axg_tdmout_c_sclk_pre_en,656 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
614 &axg_tdmin_a_sclk_post_en,657 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
615 &axg_tdmin_b_sclk_post_en,658 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
616 &axg_tdmin_c_sclk_post_en,659 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
617 &axg_tdmin_lb_sclk_post_en,660 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
618 &axg_tdmout_a_sclk_post_en,661 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
619 &axg_tdmout_b_sclk_post_en,662 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
620 &axg_tdmout_c_sclk_post_en,663 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
621 &axg_tdmin_a_sclk,664 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
622 &axg_tdmin_b_sclk,665 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
623 &axg_tdmin_c_sclk,666 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
624 &axg_tdmin_lb_sclk,667 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
625 &axg_tdmout_a_sclk,668 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
626 &axg_tdmout_b_sclk,669 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
627 &axg_tdmout_c_sclk,670 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
628 &axg_tdmin_a_lrclk,671 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
629 &axg_tdmin_b_lrclk,672 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
630 &axg_tdmin_c_lrclk,673 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
631 &axg_tdmin_lb_lrclk,674 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
632 &axg_tdmout_a_lrclk,675 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
633 &axg_tdmout_b_lrclk,676 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
634 &axg_tdmout_c_lrclk,677 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
678 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
679 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
680 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
681 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
682 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
683 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
684 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
685 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
686 [AUD_CLKID_TDM_MCLK_PAD0] = &aud_tdm_mclk_pad_0.hw,
687 [AUD_CLKID_TDM_MCLK_PAD1] = &aud_tdm_mclk_pad_1.hw,
688 [AUD_CLKID_TDM_LRCLK_PAD0] = &aud_tdm_lrclk_pad_0.hw,
689 [AUD_CLKID_TDM_LRCLK_PAD1] = &aud_tdm_lrclk_pad_1.hw,
690 [AUD_CLKID_TDM_LRCLK_PAD2] = &aud_tdm_lrclk_pad_2.hw,
691 [AUD_CLKID_TDM_SCLK_PAD0] = &aud_tdm_sclk_pad_0.hw,
692 [AUD_CLKID_TDM_SCLK_PAD1] = &aud_tdm_sclk_pad_1.hw,
693 [AUD_CLKID_TDM_SCLK_PAD2] = &aud_tdm_sclk_pad_2.hw,
694 [NR_CLKS] = NULL,
695 },
696 .num = NR_CLKS,
697};
698
699/* Convenience table to populate regmap in .probe()
700 * Note that this table is shared between both AXG and G12A,
701 * with spdifout_b clocks being exclusive to G12A. Since those
702 * clocks are not declared within the AXG onecell table, we do not
703 * feel the need to have separate AXG/G12A regmap tables.
704 */
705static struct clk_regmap *const aud_clk_regmaps[] = {
706 &aud_ddr_arb,
707 &aud_pdm,
708 &aud_tdmin_a,
709 &aud_tdmin_b,
710 &aud_tdmin_c,
711 &aud_tdmin_lb,
712 &aud_tdmout_a,
713 &aud_tdmout_b,
714 &aud_tdmout_c,
715 &aud_frddr_a,
716 &aud_frddr_b,
717 &aud_frddr_c,
718 &aud_toddr_a,
719 &aud_toddr_b,
720 &aud_toddr_c,
721 &aud_loopback,
722 &aud_spdifin,
723 &aud_spdifout,
724 &aud_resample,
725 &aud_power_detect,
726 &aud_spdifout_b,
727 &aud_mst_a_mclk_sel,
728 &aud_mst_b_mclk_sel,
729 &aud_mst_c_mclk_sel,
730 &aud_mst_d_mclk_sel,
731 &aud_mst_e_mclk_sel,
732 &aud_mst_f_mclk_sel,
733 &aud_mst_a_mclk_div,
734 &aud_mst_b_mclk_div,
735 &aud_mst_c_mclk_div,
736 &aud_mst_d_mclk_div,
737 &aud_mst_e_mclk_div,
738 &aud_mst_f_mclk_div,
739 &aud_mst_a_mclk,
740 &aud_mst_b_mclk,
741 &aud_mst_c_mclk,
742 &aud_mst_d_mclk,
743 &aud_mst_e_mclk,
744 &aud_mst_f_mclk,
745 &aud_spdifout_clk_sel,
746 &aud_spdifout_clk_div,
747 &aud_spdifout_clk,
748 &aud_spdifin_clk_sel,
749 &aud_spdifin_clk_div,
750 &aud_spdifin_clk,
751 &aud_pdm_dclk_sel,
752 &aud_pdm_dclk_div,
753 &aud_pdm_dclk,
754 &aud_pdm_sysclk_sel,
755 &aud_pdm_sysclk_div,
756 &aud_pdm_sysclk,
757 &aud_mst_a_sclk_pre_en,
758 &aud_mst_b_sclk_pre_en,
759 &aud_mst_c_sclk_pre_en,
760 &aud_mst_d_sclk_pre_en,
761 &aud_mst_e_sclk_pre_en,
762 &aud_mst_f_sclk_pre_en,
763 &aud_mst_a_sclk_div,
764 &aud_mst_b_sclk_div,
765 &aud_mst_c_sclk_div,
766 &aud_mst_d_sclk_div,
767 &aud_mst_e_sclk_div,
768 &aud_mst_f_sclk_div,
769 &aud_mst_a_sclk_post_en,
770 &aud_mst_b_sclk_post_en,
771 &aud_mst_c_sclk_post_en,
772 &aud_mst_d_sclk_post_en,
773 &aud_mst_e_sclk_post_en,
774 &aud_mst_f_sclk_post_en,
775 &aud_mst_a_sclk,
776 &aud_mst_b_sclk,
777 &aud_mst_c_sclk,
778 &aud_mst_d_sclk,
779 &aud_mst_e_sclk,
780 &aud_mst_f_sclk,
781 &aud_mst_a_lrclk_div,
782 &aud_mst_b_lrclk_div,
783 &aud_mst_c_lrclk_div,
784 &aud_mst_d_lrclk_div,
785 &aud_mst_e_lrclk_div,
786 &aud_mst_f_lrclk_div,
787 &aud_mst_a_lrclk,
788 &aud_mst_b_lrclk,
789 &aud_mst_c_lrclk,
790 &aud_mst_d_lrclk,
791 &aud_mst_e_lrclk,
792 &aud_mst_f_lrclk,
793 &aud_tdmin_a_sclk_sel,
794 &aud_tdmin_b_sclk_sel,
795 &aud_tdmin_c_sclk_sel,
796 &aud_tdmin_lb_sclk_sel,
797 &aud_tdmout_a_sclk_sel,
798 &aud_tdmout_b_sclk_sel,
799 &aud_tdmout_c_sclk_sel,
800 &aud_tdmin_a_sclk_pre_en,
801 &aud_tdmin_b_sclk_pre_en,
802 &aud_tdmin_c_sclk_pre_en,
803 &aud_tdmin_lb_sclk_pre_en,
804 &aud_tdmout_a_sclk_pre_en,
805 &aud_tdmout_b_sclk_pre_en,
806 &aud_tdmout_c_sclk_pre_en,
807 &aud_tdmin_a_sclk_post_en,
808 &aud_tdmin_b_sclk_post_en,
809 &aud_tdmin_c_sclk_post_en,
810 &aud_tdmin_lb_sclk_post_en,
811 &aud_tdmout_a_sclk_post_en,
812 &aud_tdmout_b_sclk_post_en,
813 &aud_tdmout_c_sclk_post_en,
814 &aud_tdmin_a_sclk,
815 &aud_tdmin_b_sclk,
816 &aud_tdmin_c_sclk,
817 &aud_tdmin_lb_sclk,
818 &aud_tdmout_a_sclk,
819 &aud_tdmout_b_sclk,
820 &aud_tdmout_c_sclk,
821 &aud_tdmin_a_lrclk,
822 &aud_tdmin_b_lrclk,
823 &aud_tdmin_c_lrclk,
824 &aud_tdmin_lb_lrclk,
825 &aud_tdmout_a_lrclk,
826 &aud_tdmout_b_lrclk,
827 &aud_tdmout_c_lrclk,
828 &aud_spdifout_b_clk_sel,
829 &aud_spdifout_b_clk_div,
830 &aud_spdifout_b_clk,
831 &aud_tdm_mclk_pad_0,
832 &aud_tdm_mclk_pad_1,
833 &aud_tdm_lrclk_pad_0,
834 &aud_tdm_lrclk_pad_1,
835 &aud_tdm_lrclk_pad_2,
836 &aud_tdm_sclk_pad_0,
837 &aud_tdm_sclk_pad_1,
838 &aud_tdm_sclk_pad_2,
635};839};
636 840
637static int devm_clk_get_enable(struct device *dev, char *id)841static int devm_clk_get_enable(struct device *dev, char *id)
@@ -665,14 +869,13 @@ static int devm_clk_get_enable(struct device *dev, char *id) · 27 unmodified lines
665}869}
666 870
667static int axg_register_clk_hw_input(struct device *dev,871static int axg_register_clk_hw_input(struct device *dev,
668 const char *name,872 const char *name)
669 unsigned int clkid)
670{873{
671 char *clk_name;874 char *clk_name;
672 struct clk_hw *hw;875 struct clk_hw *hw;
673 int err = 0;876 int err = 0;
674 877
675 clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);878 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
676 if (!clk_name)879 if (!clk_name)
677 return -ENOMEM;880 return -ENOMEM;
678 881
@@ -686,8 +889,6 @@ static int axg_register_clk_hw_input(struct device *dev, · 7 unmodified lines
686 if (err != -EPROBE_DEFER)889 if (err != -EPROBE_DEFER)
687 dev_err(dev, "failed to get %s clock", name);890 dev_err(dev, "failed to get %s clock", name);
688 }891 }
689 } else {
690 axg_audio_hw_onecell_data.hws[clkid] = hw;
691 }892 }
692 893
693 kfree(clk_name);894 kfree(clk_name);
@@ -696,8 +897,7 @@ static int axg_register_clk_hw_input(struct device *dev, · 2 unmodified lines
696 897
697static int axg_register_clk_hw_inputs(struct device *dev,898static int axg_register_clk_hw_inputs(struct device *dev,
698 const char *basename,899 const char *basename,
699 unsigned int count,900 unsigned int count)
700 unsigned int clkid)
701{901{
702 char *name;902 char *name;
703 int i, ret;903 int i, ret;
@@ -707,7 +907,7 @@ static int axg_register_clk_hw_inputs(struct device *dev, · 3 unmodified lines
707 if (!name)907 if (!name)
708 return -ENOMEM;908 return -ENOMEM;
709 909
710 ret = axg_register_clk_hw_input(dev, name, clkid + i);910 ret = axg_register_clk_hw_input(dev, name);
711 kfree(name);911 kfree(name);
712 if (ret)912 if (ret)
713 return ret;913 return ret;
@@ -723,15 +923,24 @@ static const struct regmap_config axg_audio_regmap_cfg = { · 9 unmodified lines
723 .max_register = AUDIO_CLK_PDMIN_CTRL1,923 .max_register = AUDIO_CLK_PDMIN_CTRL1,
724};924};
725 925
926struct audioclk_data {
927 struct clk_hw_onecell_data *hw_onecell_data;
928};
929
726static int axg_audio_clkc_probe(struct platform_device *pdev)930static int axg_audio_clkc_probe(struct platform_device *pdev)
727{931{
728 struct device *dev = &pdev->dev;932 struct device *dev = &pdev->dev;
933 const struct audioclk_data *data;
729 struct regmap *map;934 struct regmap *map;
730 struct resource *res;935 struct resource *res;
731 void __iomem *regs;936 void __iomem *regs;
732 struct clk_hw *hw;937 struct clk_hw *hw;
733 int ret, i;938 int ret, i;
734 939
940 data = of_device_get_match_data(dev);
941 if (!data)
942 return -EINVAL;
943
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);944 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 regs = devm_ioremap_resource(dev, res);945 regs = devm_ioremap_resource(dev, res);
737 if (IS_ERR(regs))946 if (IS_ERR(regs))
@@ -755,40 +964,35 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) · 17 unmodified lines
755 }964 }
756 965
757 /* Register the peripheral input clock */966 /* Register the peripheral input clock */
758 hw = meson_clk_hw_register_input(dev, "pclk", "axg_audio_pclk", 0);967 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
759 if (IS_ERR(hw))968 if (IS_ERR(hw))
760 return PTR_ERR(hw);969 return PTR_ERR(hw);
761 970
762 axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
763
764 /* Register optional input master clocks */971 /* Register optional input master clocks */
765 ret = axg_register_clk_hw_inputs(dev, "mst_in",972 ret = axg_register_clk_hw_inputs(dev, "mst_in",
766 AXG_MST_IN_COUNT,973 AUD_MST_IN_COUNT);
767 AUD_CLKID_MST0);
768 if (ret)974 if (ret)
769 return ret;975 return ret;
770 976
771 /* Register optional input slave sclks */977 /* Register optional input slave sclks */
772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",978 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
773 AXG_SLV_SCLK_COUNT,979 AUD_SLV_SCLK_COUNT);
774 AUD_CLKID_SLV_SCLK0);
775 if (ret)980 if (ret)
776 return ret;981 return ret;
777 982
778 /* Register optional input slave lrclks */983 /* Register optional input slave lrclks */
779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",984 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
780 AXG_SLV_LRCLK_COUNT,985 AUD_SLV_LRCLK_COUNT);
781 AUD_CLKID_SLV_LRCLK0);
782 if (ret)986 if (ret)
783 return ret;987 return ret;
784 988
785 /* Populate regmap for the regmap backed clocks */989 /* Populate regmap for the regmap backed clocks */
786 for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++)990 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
787 axg_audio_clk_regmaps[i]->map = map;991 aud_clk_regmaps[i]->map = map;
788 992
789 /* Take care to skip the registered input clocks */993 /* Take care to skip the registered input clocks */
790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {994 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
791 hw = axg_audio_hw_onecell_data.hws[i];995 hw = data->hw_onecell_data->hws[i];
792 /* array might be sparse */996 /* array might be sparse */
793 if (!hw)997 if (!hw)
794 continue;998 continue;
@@ -802,12 +1006,25 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) · 7 unmodified lines
802 }1006 }
803 1007
804 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,1008 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
805 &axg_audio_hw_onecell_data);1009 data->hw_onecell_data);
806}1010}
807 1011
1012static const struct audioclk_data axg_audioclk_data = {
1013 .hw_onecell_data = &axg_audio_hw_onecell_data,
1014};
1015
1016static const struct audioclk_data g12a_audioclk_data = {
1017 .hw_onecell_data = &g12a_audio_hw_onecell_data,
1018};
1019
808static const struct of_device_id clkc_match_table[] = {1020static const struct of_device_id clkc_match_table[] = {
809 { .compatible = "amlogic,axg-audio-clkc" },1021 {
810 {}1022 .compatible = "amlogic,axg-audio-clkc",
1023 .data = &axg_audioclk_data
1024 }, {
1025 .compatible = "amlogic,g12a-audio-clkc",
1026 .data = &g12a_audioclk_data
1027 }, {}
811};1028};
812MODULE_DEVICE_TABLE(of, clkc_match_table);1029MODULE_DEVICE_TABLE(of, clkc_match_table);
813 1030
@@ -820,6 +1037,6 @@ static struct platform_driver axg_audio_driver = { · 6 unmodified lines
820};1037};
821module_platform_driver(axg_audio_driver);1038module_platform_driver(axg_audio_driver);
822 1039
823MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");1040MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
824MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");1041MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
825MODULE_LICENSE("GPL v2");1042MODULE_LICENSE("GPL v2");
drivers/clk/meson/axg-audio.h+6−10
@@ -20,6 +20,8 @@ · 19 unmodified lines
20#define AUDIO_MCLK_D_CTRL 0x01020#define AUDIO_MCLK_D_CTRL 0x010
21#define AUDIO_MCLK_E_CTRL 0x01421#define AUDIO_MCLK_E_CTRL 0x014
22#define AUDIO_MCLK_F_CTRL 0x01822#define AUDIO_MCLK_F_CTRL 0x018
23#define AUDIO_MST_PAD_CTRL0 0x01c
24#define AUDIO_MST_PAD_CTRL1 0x020
23#define AUDIO_MST_A_SCLK_CTRL0 0x04025#define AUDIO_MST_A_SCLK_CTRL0 0x040
24#define AUDIO_MST_A_SCLK_CTRL1 0x04426#define AUDIO_MST_A_SCLK_CTRL1 0x044
25#define AUDIO_MST_B_SCLK_CTRL0 0x04827#define AUDIO_MST_B_SCLK_CTRL0 0x048
@@ -45,21 +47,13 @@ · 19 unmodified lines
45#define AUDIO_CLK_LOCKER_CTRL 0x0A847#define AUDIO_CLK_LOCKER_CTRL 0x0A8
46#define AUDIO_CLK_PDMIN_CTRL0 0x0AC48#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
47#define AUDIO_CLK_PDMIN_CTRL1 0x0B049#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
50#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
48 51
49/*52/*
50 * CLKID index values53 * CLKID index values
51 * These indices are entirely contrived and do not map onto the hardware.54 * These indices are entirely contrived and do not map onto the hardware.
52 */55 */
53 56
54#define AUD_CLKID_PCLK 0
55#define AUD_CLKID_MST0 1
56#define AUD_CLKID_MST1 2
57#define AUD_CLKID_MST2 3
58#define AUD_CLKID_MST3 4
59#define AUD_CLKID_MST4 5
60#define AUD_CLKID_MST5 6
61#define AUD_CLKID_MST6 7
62#define AUD_CLKID_MST7 8
63#define AUD_CLKID_MST_A_MCLK_SEL 5957#define AUD_CLKID_MST_A_MCLK_SEL 59
64#define AUD_CLKID_MST_B_MCLK_SEL 6058#define AUD_CLKID_MST_B_MCLK_SEL 60
65#define AUD_CLKID_MST_C_MCLK_SEL 6159#define AUD_CLKID_MST_C_MCLK_SEL 61
@@ -118,10 +112,12 @@ · 52 unmodified lines
118#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148112#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
119#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149113#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
120#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150114#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
115#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
116#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
121 117
122/* include the CLKIDs which are part of the DT bindings */118/* include the CLKIDs which are part of the DT bindings */
123#include <dt-bindings/clock/axg-audio-clkc.h>119#include <dt-bindings/clock/axg-audio-clkc.h>
124 120
125#define NR_CLKS 151121#define NR_CLKS 163
126 122
127#endif /*__AXG_AUDIO_CLKC_H */123#endif /*__AXG_AUDIO_CLKC_H */
drivers/clk/meson/clk-pll.c+26−0
@@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) · 302 unmodified lines
303 return 1;303 return 1;
304}304}
305 305
306static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
307{
308 meson_clk_pll_init(hw);
309
310 if (meson_clk_pll_wait_lock(hw))
311 return -EIO;
312
313 return 0;
314}
315
306static int meson_clk_pll_enable(struct clk_hw *hw)316static int meson_clk_pll_enable(struct clk_hw *hw)
307{317{
308 struct clk_regmap *clk = to_clk_regmap(hw);318 struct clk_regmap *clk = to_clk_regmap(hw);
@@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, · 78 unmodified lines
387 return 0;397 return 0;
388}398}
389 399
400/*
401 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
402 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
403 * a strict register sequence to enable the PLL.
404 * To simplify, re-use the _init() op to enable the PLL and keep
405 * the other ops except set_rate since the rate is fixed.
406 */
407const struct clk_ops meson_clk_pcie_pll_ops = {
408 .recalc_rate = meson_clk_pll_recalc_rate,
409 .round_rate = meson_clk_pll_round_rate,
410 .is_enabled = meson_clk_pll_is_enabled,
411 .enable = meson_clk_pcie_pll_enable,
412 .disable = meson_clk_pll_disable
413};
414EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
415
390const struct clk_ops meson_clk_pll_ops = {416const struct clk_ops meson_clk_pll_ops = {
391 .init = meson_clk_pll_init,417 .init = meson_clk_pll_init,
392 .recalc_rate = meson_clk_pll_recalc_rate,418 .recalc_rate = meson_clk_pll_recalc_rate,
drivers/clk/meson/clk-pll.h+1−0
@@ -45,5 +45,6 @@ struct meson_clk_pll_data { · 44 unmodified lines
45 45
46extern const struct clk_ops meson_clk_pll_ro_ops;46extern const struct clk_ops meson_clk_pll_ro_ops;
47extern const struct clk_ops meson_clk_pll_ops;47extern const struct clk_ops meson_clk_pll_ops;
48extern const struct clk_ops meson_clk_pcie_pll_ops;
48 49
49#endif /* __MESON_CLK_PLL_H */50#endif /* __MESON_CLK_PLL_H */
drivers/clk/meson/g12a-aoclk.h+0−2
@@ -16,9 +16,7 @@ · 15 unmodified lines
16 * to expose, such as the internal muxes and dividers of composite clocks,16 * to expose, such as the internal muxes and dividers of composite clocks,
17 * will remain defined here.17 * will remain defined here.
18 */18 */
19#define CLKID_AO_SAR_ADC_SEL 16
20#define CLKID_AO_SAR_ADC_DIV 1719#define CLKID_AO_SAR_ADC_DIV 17
21#define CLKID_AO_CTS_OSCIN 19
22#define CLKID_AO_32K_PRE 2020#define CLKID_AO_32K_PRE 20
23#define CLKID_AO_32K_DIV 2121#define CLKID_AO_32K_DIV 21
24#define CLKID_AO_32K_SEL 2222#define CLKID_AO_32K_SEL 22
drivers/clk/meson/g12a.c+631−0
@@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = { · 149 unmodified lines
150 },150 },
151};151};
152 152
153static struct clk_regmap g12a_sys_pll_div16_en = {
154 .data = &(struct clk_regmap_gate_data){
155 .offset = HHI_SYS_CPU_CLK_CNTL1,
156 .bit_idx = 24,
157 },
158 .hw.init = &(struct clk_init_data) {
159 .name = "sys_pll_div16_en",
160 .ops = &clk_regmap_gate_ro_ops,
161 .parent_names = (const char *[]){ "sys_pll" },
162 .num_parents = 1,
163 /*
164 * This clock is used to debug the sys_pll range
165 * Linux should not change it at runtime
166 */
167 },
168};
169
170static struct clk_fixed_factor g12a_sys_pll_div16 = {
171 .mult = 1,
172 .div = 16,
173 .hw.init = &(struct clk_init_data){
174 .name = "sys_pll_div16",
175 .ops = &clk_fixed_factor_ops,
176 .parent_names = (const char *[]){ "sys_pll_div16_en" },
177 .num_parents = 1,
178 },
179};
180
181/* Datasheet names this field as "premux0" */
182static struct clk_regmap g12a_cpu_clk_premux0 = {
183 .data = &(struct clk_regmap_mux_data){
184 .offset = HHI_SYS_CPU_CLK_CNTL0,
185 .mask = 0x3,
186 .shift = 0,
187 },
188 .hw.init = &(struct clk_init_data){
189 .name = "cpu_clk_dyn0_sel",
190 .ops = &clk_regmap_mux_ro_ops,
191 .parent_names = (const char *[]){ IN_PREFIX "xtal",
192 "fclk_div2",
193 "fclk_div3" },
194 .num_parents = 3,
195 },
196};
197
198/* Datasheet names this field as "mux0_divn_tcnt" */
199static struct clk_regmap g12a_cpu_clk_mux0_div = {
200 .data = &(struct clk_regmap_div_data){
201 .offset = HHI_SYS_CPU_CLK_CNTL0,
202 .shift = 4,
203 .width = 6,
204 },
205 .hw.init = &(struct clk_init_data){
206 .name = "cpu_clk_dyn0_div",
207 .ops = &clk_regmap_divider_ro_ops,
208 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
209 .num_parents = 1,
210 },
211};
212
213/* Datasheet names this field as "postmux0" */
214static struct clk_regmap g12a_cpu_clk_postmux0 = {
215 .data = &(struct clk_regmap_mux_data){
216 .offset = HHI_SYS_CPU_CLK_CNTL0,
217 .mask = 0x1,
218 .shift = 2,
219 },
220 .hw.init = &(struct clk_init_data){
221 .name = "cpu_clk_dyn0",
222 .ops = &clk_regmap_mux_ro_ops,
223 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
224 "cpu_clk_dyn0_div" },
225 .num_parents = 2,
226 },
227};
228
229/* Datasheet names this field as "premux1" */
230static struct clk_regmap g12a_cpu_clk_premux1 = {
231 .data = &(struct clk_regmap_mux_data){
232 .offset = HHI_SYS_CPU_CLK_CNTL0,
233 .mask = 0x3,
234 .shift = 16,
235 },
236 .hw.init = &(struct clk_init_data){
237 .name = "cpu_clk_dyn1_sel",
238 .ops = &clk_regmap_mux_ro_ops,
239 .parent_names = (const char *[]){ IN_PREFIX "xtal",
240 "fclk_div2",
241 "fclk_div3" },
242 .num_parents = 3,
243 },
244};
245
246/* Datasheet names this field as "Mux1_divn_tcnt" */
247static struct clk_regmap g12a_cpu_clk_mux1_div = {
248 .data = &(struct clk_regmap_div_data){
249 .offset = HHI_SYS_CPU_CLK_CNTL0,
250 .shift = 20,
251 .width = 6,
252 },
253 .hw.init = &(struct clk_init_data){
254 .name = "cpu_clk_dyn1_div",
255 .ops = &clk_regmap_divider_ro_ops,
256 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
257 .num_parents = 1,
258 },
259};
260
261/* Datasheet names this field as "postmux1" */
262static struct clk_regmap g12a_cpu_clk_postmux1 = {
263 .data = &(struct clk_regmap_mux_data){
264 .offset = HHI_SYS_CPU_CLK_CNTL0,
265 .mask = 0x1,
266 .shift = 18,
267 },
268 .hw.init = &(struct clk_init_data){
269 .name = "cpu_clk_dyn1",
270 .ops = &clk_regmap_mux_ro_ops,
271 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
272 "cpu_clk_dyn1_div" },
273 .num_parents = 2,
274 },
275};
276
277/* Datasheet names this field as "Final_dyn_mux_sel" */
278static struct clk_regmap g12a_cpu_clk_dyn = {
279 .data = &(struct clk_regmap_mux_data){
280 .offset = HHI_SYS_CPU_CLK_CNTL0,
281 .mask = 0x1,
282 .shift = 10,
283 },
284 .hw.init = &(struct clk_init_data){
285 .name = "cpu_clk_dyn",
286 .ops = &clk_regmap_mux_ro_ops,
287 .parent_names = (const char *[]){ "cpu_clk_dyn0",
288 "cpu_clk_dyn1" },
289 .num_parents = 2,
290 },
291};
292
293/* Datasheet names this field as "Final_mux_sel" */
294static struct clk_regmap g12a_cpu_clk = {
295 .data = &(struct clk_regmap_mux_data){
296 .offset = HHI_SYS_CPU_CLK_CNTL0,
297 .mask = 0x1,
298 .shift = 11,
299 },
300 .hw.init = &(struct clk_init_data){
301 .name = "cpu_clk",
302 .ops = &clk_regmap_mux_ro_ops,
303 .parent_names = (const char *[]){ "cpu_clk_dyn",
304 "sys_pll" },
305 .num_parents = 2,
306 },
307};
308
309static struct clk_regmap g12a_cpu_clk_div16_en = {
310 .data = &(struct clk_regmap_gate_data){
311 .offset = HHI_SYS_CPU_CLK_CNTL1,
312 .bit_idx = 1,
313 },
314 .hw.init = &(struct clk_init_data) {
315 .name = "cpu_clk_div16_en",
316 .ops = &clk_regmap_gate_ro_ops,
317 .parent_names = (const char *[]){ "cpu_clk" },
318 .num_parents = 1,
319 /*
320 * This clock is used to debug the cpu_clk range
321 * Linux should not change it at runtime
322 */
323 },
324};
325
326static struct clk_fixed_factor g12a_cpu_clk_div16 = {
327 .mult = 1,
328 .div = 16,
329 .hw.init = &(struct clk_init_data){
330 .name = "cpu_clk_div16",
331 .ops = &clk_fixed_factor_ops,
332 .parent_names = (const char *[]){ "cpu_clk_div16_en" },
333 .num_parents = 1,
334 },
335};
336
337static struct clk_regmap g12a_cpu_clk_apb_div = {
338 .data = &(struct clk_regmap_div_data){
339 .offset = HHI_SYS_CPU_CLK_CNTL1,
340 .shift = 3,
341 .width = 3,
342 .flags = CLK_DIVIDER_POWER_OF_TWO,
343 },
344 .hw.init = &(struct clk_init_data){
345 .name = "cpu_clk_apb_div",
346 .ops = &clk_regmap_divider_ro_ops,
347 .parent_names = (const char *[]){ "cpu_clk" },
348 .num_parents = 1,
349 },
350};
351
352static struct clk_regmap g12a_cpu_clk_apb = {
353 .data = &(struct clk_regmap_gate_data){
354 .offset = HHI_SYS_CPU_CLK_CNTL1,
355 .bit_idx = 1,
356 },
357 .hw.init = &(struct clk_init_data) {
358 .name = "cpu_clk_apb",
359 .ops = &clk_regmap_gate_ro_ops,
360 .parent_names = (const char *[]){ "cpu_clk_apb_div" },
361 .num_parents = 1,
362 /*
363 * This clock is set by the ROM monitor code,
364 * Linux should not change it at runtime
365 */
366 },
367};
368
369static struct clk_regmap g12a_cpu_clk_atb_div = {
370 .data = &(struct clk_regmap_div_data){
371 .offset = HHI_SYS_CPU_CLK_CNTL1,
372 .shift = 6,
373 .width = 3,
374 .flags = CLK_DIVIDER_POWER_OF_TWO,
375 },
376 .hw.init = &(struct clk_init_data){
377 .name = "cpu_clk_atb_div",
378 .ops = &clk_regmap_divider_ro_ops,
379 .parent_names = (const char *[]){ "cpu_clk" },
380 .num_parents = 1,
381 },
382};
383
384static struct clk_regmap g12a_cpu_clk_atb = {
385 .data = &(struct clk_regmap_gate_data){
386 .offset = HHI_SYS_CPU_CLK_CNTL1,
387 .bit_idx = 17,
388 },
389 .hw.init = &(struct clk_init_data) {
390 .name = "cpu_clk_atb",
391 .ops = &clk_regmap_gate_ro_ops,
392 .parent_names = (const char *[]){ "cpu_clk_atb_div" },
393 .num_parents = 1,
394 /*
395 * This clock is set by the ROM monitor code,
396 * Linux should not change it at runtime
397 */
398 },
399};
400
401static struct clk_regmap g12a_cpu_clk_axi_div = {
402 .data = &(struct clk_regmap_div_data){
403 .offset = HHI_SYS_CPU_CLK_CNTL1,
404 .shift = 9,
405 .width = 3,
406 .flags = CLK_DIVIDER_POWER_OF_TWO,
407 },
408 .hw.init = &(struct clk_init_data){
409 .name = "cpu_clk_axi_div",
410 .ops = &clk_regmap_divider_ro_ops,
411 .parent_names = (const char *[]){ "cpu_clk" },
412 .num_parents = 1,
413 },
414};
415
416static struct clk_regmap g12a_cpu_clk_axi = {
417 .data = &(struct clk_regmap_gate_data){
418 .offset = HHI_SYS_CPU_CLK_CNTL1,
419 .bit_idx = 18,
420 },
421 .hw.init = &(struct clk_init_data) {
422 .name = "cpu_clk_axi",
423 .ops = &clk_regmap_gate_ro_ops,
424 .parent_names = (const char *[]){ "cpu_clk_axi_div" },
425 .num_parents = 1,
426 /*
427 * This clock is set by the ROM monitor code,
428 * Linux should not change it at runtime
429 */
430 },
431};
432
433static struct clk_regmap g12a_cpu_clk_trace_div = {
434 .data = &(struct clk_regmap_div_data){
435 .offset = HHI_SYS_CPU_CLK_CNTL1,
436 .shift = 20,
437 .width = 3,
438 .flags = CLK_DIVIDER_POWER_OF_TWO,
439 },
440 .hw.init = &(struct clk_init_data){
441 .name = "cpu_clk_trace_div",
442 .ops = &clk_regmap_divider_ro_ops,
443 .parent_names = (const char *[]){ "cpu_clk" },
444 .num_parents = 1,
445 },
446};
447
448static struct clk_regmap g12a_cpu_clk_trace = {
449 .data = &(struct clk_regmap_gate_data){
450 .offset = HHI_SYS_CPU_CLK_CNTL1,
451 .bit_idx = 23,
452 },
453 .hw.init = &(struct clk_init_data) {
454 .name = "cpu_clk_trace",
455 .ops = &clk_regmap_gate_ro_ops,
456 .parent_names = (const char *[]){ "cpu_clk_trace_div" },
457 .num_parents = 1,
458 /*
459 * This clock is set by the ROM monitor code,
460 * Linux should not change it at runtime
461 */
462 },
463};
464
153static const struct pll_mult_range g12a_gp0_pll_mult_range = {465static const struct pll_mult_range g12a_gp0_pll_mult_range = {
154 .min = 55,466 .min = 55,
155 .max = 255,467 .max = 255,
@@ -302,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = { · 146 unmodified lines
302 },614 },
303};615};
304 616
617/*
618 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
619 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
620 * a strict register sequence to enable the PLL.
621 */
622static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
623 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
624 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
625 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
626 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
627 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
628 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
629 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
630 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
631 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
632 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
633 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
634 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
635};
636
637/* Keep a single entry table for recalc/round_rate() ops */
638static const struct pll_params_table g12a_pcie_pll_table[] = {
639 PLL_PARAMS(150, 1),
640 {0, 0},
641};
642
643static struct clk_regmap g12a_pcie_pll_dco = {
644 .data = &(struct meson_clk_pll_data){
645 .en = {
646 .reg_off = HHI_PCIE_PLL_CNTL0,
647 .shift = 28,
648 .width = 1,
649 },
650 .m = {
651 .reg_off = HHI_PCIE_PLL_CNTL0,
652 .shift = 0,
653 .width = 8,
654 },
655 .n = {
656 .reg_off = HHI_PCIE_PLL_CNTL0,
657 .shift = 10,
658 .width = 5,
659 },
660 .frac = {
661 .reg_off = HHI_PCIE_PLL_CNTL1,
662 .shift = 0,
663 .width = 12,
664 },
665 .l = {
666 .reg_off = HHI_PCIE_PLL_CNTL0,
667 .shift = 31,
668 .width = 1,
669 },
670 .rst = {
671 .reg_off = HHI_PCIE_PLL_CNTL0,
672 .shift = 29,
673 .width = 1,
674 },
675 .table = g12a_pcie_pll_table,
676 .init_regs = g12a_pcie_pll_init_regs,
677 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
678 },
679 .hw.init = &(struct clk_init_data){
680 .name = "pcie_pll_dco",
681 .ops = &meson_clk_pcie_pll_ops,
682 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
683 .num_parents = 1,
684 },
685};
686
687static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
688 .mult = 1,
689 .div = 2,
690 .hw.init = &(struct clk_init_data){
691 .name = "pcie_pll_dco_div2",
692 .ops = &clk_fixed_factor_ops,
693 .parent_names = (const char *[]){ "pcie_pll_dco" },
694 .num_parents = 1,
695 .flags = CLK_SET_RATE_PARENT,
696 },
697};
698
699static struct clk_regmap g12a_pcie_pll_od = {
700 .data = &(struct clk_regmap_div_data){
701 .offset = HHI_PCIE_PLL_CNTL0,
702 .shift = 16,
703 .width = 5,
704 .flags = CLK_DIVIDER_ROUND_CLOSEST |
705 CLK_DIVIDER_ONE_BASED |
706 CLK_DIVIDER_ALLOW_ZERO,
707 },
708 .hw.init = &(struct clk_init_data){
709 .name = "pcie_pll_od",
710 .ops = &clk_regmap_divider_ops,
711 .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
712 .num_parents = 1,
713 .flags = CLK_SET_RATE_PARENT,
714 },
715};
716
717static struct clk_fixed_factor g12a_pcie_pll = {
718 .mult = 1,
719 .div = 2,
720 .hw.init = &(struct clk_init_data){
721 .name = "pcie_pll_pll",
722 .ops = &clk_fixed_factor_ops,
723 .parent_names = (const char *[]){ "pcie_pll_od" },
724 .num_parents = 1,
725 .flags = CLK_SET_RATE_PARENT,
726 },
727};
728
305static struct clk_regmap g12a_hdmi_pll_dco = {729static struct clk_regmap g12a_hdmi_pll_dco = {
306 .data = &(struct meson_clk_pll_data){730 .data = &(struct meson_clk_pll_data){
307 .en = {731 .en = {
@@ -1071,6 +1495,151 @@ static struct clk_regmap g12a_vpu = { · 763 unmodified lines
1071 },1495 },
1072};1496};
1073 1497
1498/* VDEC clocks */
1499
1500static const char * const g12a_vdec_parent_names[] = {
1501 "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1502 "hifi_pll", "gp0_pll",
1503};
1504
1505static struct clk_regmap g12a_vdec_1_sel = {
1506 .data = &(struct clk_regmap_mux_data){
1507 .offset = HHI_VDEC_CLK_CNTL,
1508 .mask = 0x7,
1509 .shift = 9,
1510 .flags = CLK_MUX_ROUND_CLOSEST,
1511 },
1512 .hw.init = &(struct clk_init_data){
1513 .name = "vdec_1_sel",
1514 .ops = &clk_regmap_mux_ops,
1515 .parent_names = g12a_vdec_parent_names,
1516 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1517 .flags = CLK_SET_RATE_PARENT,
1518 },
1519};
1520
1521static struct clk_regmap g12a_vdec_1_div = {
1522 .data = &(struct clk_regmap_div_data){
1523 .offset = HHI_VDEC_CLK_CNTL,
1524 .shift = 0,
1525 .width = 7,
1526 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1527 },
1528 .hw.init = &(struct clk_init_data){
1529 .name = "vdec_1_div",
1530 .ops = &clk_regmap_divider_ops,
1531 .parent_names = (const char *[]){ "vdec_1_sel" },
1532 .num_parents = 1,
1533 .flags = CLK_SET_RATE_PARENT,
1534 },
1535};
1536
1537static struct clk_regmap g12a_vdec_1 = {
1538 .data = &(struct clk_regmap_gate_data){
1539 .offset = HHI_VDEC_CLK_CNTL,
1540 .bit_idx = 8,
1541 },
1542 .hw.init = &(struct clk_init_data) {
1543 .name = "vdec_1",
1544 .ops = &clk_regmap_gate_ops,
1545 .parent_names = (const char *[]){ "vdec_1_div" },
1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT,
1548 },
1549};
1550
1551static struct clk_regmap g12a_vdec_hevcf_sel = {
1552 .data = &(struct clk_regmap_mux_data){
1553 .offset = HHI_VDEC2_CLK_CNTL,
1554 .mask = 0x7,
1555 .shift = 9,
1556 .flags = CLK_MUX_ROUND_CLOSEST,
1557 },
1558 .hw.init = &(struct clk_init_data){
1559 .name = "vdec_hevcf_sel",
1560 .ops = &clk_regmap_mux_ops,
1561 .parent_names = g12a_vdec_parent_names,
1562 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1563 .flags = CLK_SET_RATE_PARENT,
1564 },
1565};
1566
1567static struct clk_regmap g12a_vdec_hevcf_div = {
1568 .data = &(struct clk_regmap_div_data){
1569 .offset = HHI_VDEC2_CLK_CNTL,
1570 .shift = 0,
1571 .width = 7,
1572 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1573 },
1574 .hw.init = &(struct clk_init_data){
1575 .name = "vdec_hevcf_div",
1576 .ops = &clk_regmap_divider_ops,
1577 .parent_names = (const char *[]){ "vdec_hevcf_sel" },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 },
1581};
1582
1583static struct clk_regmap g12a_vdec_hevcf = {
1584 .data = &(struct clk_regmap_gate_data){
1585 .offset = HHI_VDEC2_CLK_CNTL,
1586 .bit_idx = 8,
1587 },
1588 .hw.init = &(struct clk_init_data) {
1589 .name = "vdec_hevcf",
1590 .ops = &clk_regmap_gate_ops,
1591 .parent_names = (const char *[]){ "vdec_hevcf_div" },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 },
1595};
1596
1597static struct clk_regmap g12a_vdec_hevc_sel = {
1598 .data = &(struct clk_regmap_mux_data){
1599 .offset = HHI_VDEC2_CLK_CNTL,
1600 .mask = 0x7,
1601 .shift = 25,
1602 .flags = CLK_MUX_ROUND_CLOSEST,
1603 },
1604 .hw.init = &(struct clk_init_data){
1605 .name = "vdec_hevc_sel",
1606 .ops = &clk_regmap_mux_ops,
1607 .parent_names = g12a_vdec_parent_names,
1608 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1609 .flags = CLK_SET_RATE_PARENT,
1610 },
1611};
1612
1613static struct clk_regmap g12a_vdec_hevc_div = {
1614 .data = &(struct clk_regmap_div_data){
1615 .offset = HHI_VDEC2_CLK_CNTL,
1616 .shift = 16,
1617 .width = 7,
1618 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1619 },
1620 .hw.init = &(struct clk_init_data){
1621 .name = "vdec_hevc_div",
1622 .ops = &clk_regmap_divider_ops,
1623 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627};
1628
1629static struct clk_regmap g12a_vdec_hevc = {
1630 .data = &(struct clk_regmap_gate_data){
1631 .offset = HHI_VDEC2_CLK_CNTL,
1632 .bit_idx = 24,
1633 },
1634 .hw.init = &(struct clk_init_data) {
1635 .name = "vdec_hevc",
1636 .ops = &clk_regmap_gate_ops,
1637 .parent_names = (const char *[]){ "vdec_hevc_div" },
1638 .num_parents = 1,
1639 .flags = CLK_SET_RATE_PARENT,
1640 },
1641};
1642
1074/* VAPB Clock */1643/* VAPB Clock */
1075 1644
1076static const char * const g12a_vapb_parent_names[] = {1645static const char * const g12a_vapb_parent_names[] = {
@@ -2167,6 +2736,39 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { · 1090 unmodified lines
2167 [CLKID_MALI] = &g12a_mali.hw,2736 [CLKID_MALI] = &g12a_mali.hw,
2168 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,2737 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
2169 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,2738 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
2739 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
2740 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
2741 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
2742 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
2743 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
2744 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
2745 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
2746 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
2747 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
2748 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
2749 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
2750 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
2751 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
2752 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
2753 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
2754 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
2755 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
2756 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
2757 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
2758 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
2759 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
2760 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
2761 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
2762 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
2763 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
2764 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
2765 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
2766 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
2767 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
2768 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
2769 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
2770 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
2771 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
2170 [NR_CLKS] = NULL,2772 [NR_CLKS] = NULL,
2171 },2773 },
2172 .num = NR_CLKS,2774 .num = NR_CLKS,
@@ -2335,6 +2937,35 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { · 162 unmodified lines
2335 &g12a_mali_1,2937 &g12a_mali_1,
2336 &g12a_mali,2938 &g12a_mali,
2337 &g12a_mpll_50m,2939 &g12a_mpll_50m,
2940 &g12a_sys_pll_div16_en,
2941 &g12a_cpu_clk_premux0,
2942 &g12a_cpu_clk_mux0_div,
2943 &g12a_cpu_clk_postmux0,
2944 &g12a_cpu_clk_premux1,
2945 &g12a_cpu_clk_mux1_div,
2946 &g12a_cpu_clk_postmux1,
2947 &g12a_cpu_clk_dyn,
2948 &g12a_cpu_clk,
2949 &g12a_cpu_clk_div16_en,
2950 &g12a_cpu_clk_apb_div,
2951 &g12a_cpu_clk_apb,
2952 &g12a_cpu_clk_atb_div,
2953 &g12a_cpu_clk_atb,
2954 &g12a_cpu_clk_axi_div,
2955 &g12a_cpu_clk_axi,
2956 &g12a_cpu_clk_trace_div,
2957 &g12a_cpu_clk_trace,
2958 &g12a_pcie_pll_od,
2959 &g12a_pcie_pll_dco,
2960 &g12a_vdec_1_sel,
2961 &g12a_vdec_1_div,
2962 &g12a_vdec_1,
2963 &g12a_vdec_hevc_sel,
2964 &g12a_vdec_hevc_div,
2965 &g12a_vdec_hevc,
2966 &g12a_vdec_hevcf_sel,
2967 &g12a_vdec_hevcf_div,
2968 &g12a_vdec_hevcf,
2338};2969};
2339 2970
2340static const struct meson_eeclkc_data g12a_clkc_data = {2971static const struct meson_eeclkc_data g12a_clkc_data = {
drivers/clk/meson/g12a.h+30−1
@@ -50,6 +50,7 @@ · 49 unmodified lines
50#define HHI_GCLK_MPEG2 0x14850#define HHI_GCLK_MPEG2 0x148
51#define HHI_GCLK_OTHER 0x15051#define HHI_GCLK_OTHER 0x150
52#define HHI_GCLK_OTHER2 0x15452#define HHI_GCLK_OTHER2 0x154
53#define HHI_SYS_CPU_CLK_CNTL1 0x15c
53#define HHI_VID_CLK_DIV 0x16454#define HHI_VID_CLK_DIV 0x164
54#define HHI_MPEG_CLK_CNTL 0x17455#define HHI_MPEG_CLK_CNTL 0x174
55#define HHI_AUD_CLK_CNTL 0x17856#define HHI_AUD_CLK_CNTL 0x178
@@ -166,8 +167,36 @@ · 110 unmodified lines
166#define CLKID_MALI_0_DIV 170167#define CLKID_MALI_0_DIV 170
167#define CLKID_MALI_1_DIV 173168#define CLKID_MALI_1_DIV 173
168#define CLKID_MPLL_5OM_DIV 176169#define CLKID_MPLL_5OM_DIV 176
170#define CLKID_SYS_PLL_DIV16_EN 178
171#define CLKID_SYS_PLL_DIV16 179
172#define CLKID_CPU_CLK_DYN0_SEL 180
173#define CLKID_CPU_CLK_DYN0_DIV 181
174#define CLKID_CPU_CLK_DYN0 182
175#define CLKID_CPU_CLK_DYN1_SEL 183
176#define CLKID_CPU_CLK_DYN1_DIV 184
177#define CLKID_CPU_CLK_DYN1 185
178#define CLKID_CPU_CLK_DYN 186
179#define CLKID_CPU_CLK_DIV16_EN 188
180#define CLKID_CPU_CLK_DIV16 189
181#define CLKID_CPU_CLK_APB_DIV 190
182#define CLKID_CPU_CLK_APB 191
183#define CLKID_CPU_CLK_ATB_DIV 192
184#define CLKID_CPU_CLK_ATB 193
185#define CLKID_CPU_CLK_AXI_DIV 194
186#define CLKID_CPU_CLK_AXI 195
187#define CLKID_CPU_CLK_TRACE_DIV 196
188#define CLKID_CPU_CLK_TRACE 197
189#define CLKID_PCIE_PLL_DCO 198
190#define CLKID_PCIE_PLL_DCO_DIV2 199
191#define CLKID_PCIE_PLL_OD 200
192#define CLKID_VDEC_1_SEL 202
193#define CLKID_VDEC_1_DIV 203
194#define CLKID_VDEC_HEVC_SEL 205
195#define CLKID_VDEC_HEVC_DIV 206
196#define CLKID_VDEC_HEVCF_SEL 208
197#define CLKID_VDEC_HEVCF_DIV 209
169 198
170#define NR_CLKS 178199#define NR_CLKS 211
171 200
172/* include the CLKIDs that have been made part of the DT binding */201/* include the CLKIDs that have been made part of the DT binding */
173#include <dt-bindings/clock/g12a-clkc.h>202#include <dt-bindings/clock/g12a-clkc.h>
drivers/clk/meson/meson8b.c+733−1
@@ -1703,6 +1703,456 @@ static struct clk_regmap meson8b_mali = { · 1702 unmodified lines
1703 },1703 },
1704};1704};
1705 1705
1706static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
1707 PLL_PARAMS(182, 3),
1708 { /* sentinel */ },
1709};
1710
1711static struct clk_regmap meson8m2_gp_pll_dco = {
1712 .data = &(struct meson_clk_pll_data){
1713 .en = {
1714 .reg_off = HHI_GP_PLL_CNTL,
1715 .shift = 30,
1716 .width = 1,
1717 },
1718 .m = {
1719 .reg_off = HHI_GP_PLL_CNTL,
1720 .shift = 0,
1721 .width = 9,
1722 },
1723 .n = {
1724 .reg_off = HHI_GP_PLL_CNTL,
1725 .shift = 9,
1726 .width = 5,
1727 },
1728 .l = {
1729 .reg_off = HHI_GP_PLL_CNTL,
1730 .shift = 31,
1731 .width = 1,
1732 },
1733 .rst = {
1734 .reg_off = HHI_GP_PLL_CNTL,
1735 .shift = 29,
1736 .width = 1,
1737 },
1738 .table = meson8m2_gp_pll_params_table,
1739 },
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gp_pll_dco",
1742 .ops = &meson_clk_pll_ops,
1743 .parent_names = (const char *[]){ "xtal" },
1744 .num_parents = 1,
1745 },
1746};
1747
1748static struct clk_regmap meson8m2_gp_pll = {
1749 .data = &(struct clk_regmap_div_data){
1750 .offset = HHI_GP_PLL_CNTL,
1751 .shift = 16,
1752 .width = 2,
1753 .flags = CLK_DIVIDER_POWER_OF_TWO,
1754 },
1755 .hw.init = &(struct clk_init_data){
1756 .name = "gp_pll",
1757 .ops = &clk_regmap_divider_ops,
1758 .parent_names = (const char *[]){ "gp_pll_dco" },
1759 .num_parents = 1,
1760 .flags = CLK_SET_RATE_PARENT,
1761 },
1762};
1763
1764static const char * const mmeson8b_vpu_0_1_parent_names[] = {
1765 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1766};
1767
1768static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
1769 "fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
1770};
1771
1772static struct clk_regmap meson8b_vpu_0_sel = {
1773 .data = &(struct clk_regmap_mux_data){
1774 .offset = HHI_VPU_CLK_CNTL,
1775 .mask = 0x3,
1776 .shift = 9,
1777 },
1778 .hw.init = &(struct clk_init_data){
1779 .name = "vpu_0_sel",
1780 .ops = &clk_regmap_mux_ops,
1781 .parent_names = mmeson8b_vpu_0_1_parent_names,
1782 .num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1783 .flags = CLK_SET_RATE_PARENT,
1784 },
1785};
1786
1787static struct clk_regmap meson8m2_vpu_0_sel = {
1788 .data = &(struct clk_regmap_mux_data){
1789 .offset = HHI_VPU_CLK_CNTL,
1790 .mask = 0x3,
1791 .shift = 9,
1792 },
1793 .hw.init = &(struct clk_init_data){
1794 .name = "vpu_0_sel",
1795 .ops = &clk_regmap_mux_ops,
1796 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1797 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1798 .flags = CLK_SET_RATE_PARENT,
1799 },
1800};
1801
1802static struct clk_regmap meson8b_vpu_0_div = {
1803 .data = &(struct clk_regmap_div_data){
1804 .offset = HHI_VPU_CLK_CNTL,
1805 .shift = 0,
1806 .width = 7,
1807 },
1808 .hw.init = &(struct clk_init_data){
1809 .name = "vpu_0_div",
1810 .ops = &clk_regmap_divider_ops,
1811 .parent_names = (const char *[]){ "vpu_0_sel" },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 },
1815};
1816
1817static struct clk_regmap meson8b_vpu_0 = {
1818 .data = &(struct clk_regmap_gate_data){
1819 .offset = HHI_VPU_CLK_CNTL,
1820 .bit_idx = 8,
1821 },
1822 .hw.init = &(struct clk_init_data) {
1823 .name = "vpu_0",
1824 .ops = &clk_regmap_gate_ops,
1825 .parent_names = (const char *[]){ "vpu_0_div" },
1826 .num_parents = 1,
1827 .flags = CLK_SET_RATE_PARENT,
1828 },
1829};
1830
1831static struct clk_regmap meson8b_vpu_1_sel = {
1832 .data = &(struct clk_regmap_mux_data){
1833 .offset = HHI_VPU_CLK_CNTL,
1834 .mask = 0x3,
1835 .shift = 25,
1836 },
1837 .hw.init = &(struct clk_init_data){
1838 .name = "vpu_1_sel",
1839 .ops = &clk_regmap_mux_ops,
1840 .parent_names = mmeson8b_vpu_0_1_parent_names,
1841 .num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1842 .flags = CLK_SET_RATE_PARENT,
1843 },
1844};
1845
1846static struct clk_regmap meson8m2_vpu_1_sel = {
1847 .data = &(struct clk_regmap_mux_data){
1848 .offset = HHI_VPU_CLK_CNTL,
1849 .mask = 0x3,
1850 .shift = 25,
1851 },
1852 .hw.init = &(struct clk_init_data){
1853 .name = "vpu_1_sel",
1854 .ops = &clk_regmap_mux_ops,
1855 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1856 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1857 .flags = CLK_SET_RATE_PARENT,
1858 },
1859};
1860
1861static struct clk_regmap meson8b_vpu_1_div = {
1862 .data = &(struct clk_regmap_div_data){
1863 .offset = HHI_VPU_CLK_CNTL,
1864 .shift = 16,
1865 .width = 7,
1866 },
1867 .hw.init = &(struct clk_init_data){
1868 .name = "vpu_1_div",
1869 .ops = &clk_regmap_divider_ops,
1870 .parent_names = (const char *[]){ "vpu_1_sel" },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 },
1874};
1875
1876static struct clk_regmap meson8b_vpu_1 = {
1877 .data = &(struct clk_regmap_gate_data){
1878 .offset = HHI_VPU_CLK_CNTL,
1879 .bit_idx = 24,
1880 },
1881 .hw.init = &(struct clk_init_data) {
1882 .name = "vpu_1",
1883 .ops = &clk_regmap_gate_ops,
1884 .parent_names = (const char *[]){ "vpu_1_div" },
1885 .num_parents = 1,
1886 .flags = CLK_SET_RATE_PARENT,
1887 },
1888};
1889
1890static struct clk_regmap meson8b_vpu = {
1891 .data = &(struct clk_regmap_mux_data){
1892 .offset = HHI_VPU_CLK_CNTL,
1893 .mask = 1,
1894 .shift = 31,
1895 },
1896 .hw.init = &(struct clk_init_data){
1897 .name = "vpu",
1898 .ops = &clk_regmap_mux_ops,
1899 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1900 .num_parents = 2,
1901 .flags = CLK_SET_RATE_NO_REPARENT,
1902 },
1903};
1904
1905static const char * const meson8b_vdec_parent_names[] = {
1906 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
1907};
1908
1909static struct clk_regmap meson8b_vdec_1_sel = {
1910 .data = &(struct clk_regmap_mux_data){
1911 .offset = HHI_VDEC_CLK_CNTL,
1912 .mask = 0x3,
1913 .shift = 9,
1914 .flags = CLK_MUX_ROUND_CLOSEST,
1915 },
1916 .hw.init = &(struct clk_init_data){
1917 .name = "vdec_1_sel",
1918 .ops = &clk_regmap_mux_ops,
1919 .parent_names = meson8b_vdec_parent_names,
1920 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
1921 .flags = CLK_SET_RATE_PARENT,
1922 },
1923};
1924
1925static struct clk_regmap meson8b_vdec_1_1_div = {
1926 .data = &(struct clk_regmap_div_data){
1927 .offset = HHI_VDEC_CLK_CNTL,
1928 .shift = 0,
1929 .width = 7,
1930 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1931 },
1932 .hw.init = &(struct clk_init_data){
1933 .name = "vdec_1_1_div",
1934 .ops = &clk_regmap_divider_ops,
1935 .parent_names = (const char *[]){ "vdec_1_sel" },
1936 .num_parents = 1,
1937 .flags = CLK_SET_RATE_PARENT,
1938 },
1939};
1940
1941static struct clk_regmap meson8b_vdec_1_1 = {
1942 .data = &(struct clk_regmap_gate_data){
1943 .offset = HHI_VDEC_CLK_CNTL,
1944 .bit_idx = 8,
1945 },
1946 .hw.init = &(struct clk_init_data) {
1947 .name = "vdec_1_1",
1948 .ops = &clk_regmap_gate_ops,
1949 .parent_names = (const char *[]){ "vdec_1_1_div" },
1950 .num_parents = 1,
1951 .flags = CLK_SET_RATE_PARENT,
1952 },
1953};
1954
1955static struct clk_regmap meson8b_vdec_1_2_div = {
1956 .data = &(struct clk_regmap_div_data){
1957 .offset = HHI_VDEC3_CLK_CNTL,
1958 .shift = 0,
1959 .width = 7,
1960 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1961 },
1962 .hw.init = &(struct clk_init_data){
1963 .name = "vdec_1_2_div",
1964 .ops = &clk_regmap_divider_ops,
1965 .parent_names = (const char *[]){ "vdec_1_sel" },
1966 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT,
1968 },
1969};
1970
1971static struct clk_regmap meson8b_vdec_1_2 = {
1972 .data = &(struct clk_regmap_gate_data){
1973 .offset = HHI_VDEC3_CLK_CNTL,
1974 .bit_idx = 8,
1975 },
1976 .hw.init = &(struct clk_init_data) {
1977 .name = "vdec_1_2",
1978 .ops = &clk_regmap_gate_ops,
1979 .parent_names = (const char *[]){ "vdec_1_2_div" },
1980 .num_parents = 1,
1981 .flags = CLK_SET_RATE_PARENT,
1982 },
1983};
1984
1985static struct clk_regmap meson8b_vdec_1 = {
1986 .data = &(struct clk_regmap_mux_data){
1987 .offset = HHI_VDEC3_CLK_CNTL,
1988 .mask = 0x1,
1989 .shift = 15,
1990 .flags = CLK_MUX_ROUND_CLOSEST,
1991 },
1992 .hw.init = &(struct clk_init_data){
1993 .name = "vdec_1",
1994 .ops = &clk_regmap_mux_ops,
1995 .parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
1996 .num_parents = 2,
1997 .flags = CLK_SET_RATE_PARENT,
1998 },
1999};
2000
2001static struct clk_regmap meson8b_vdec_hcodec_sel = {
2002 .data = &(struct clk_regmap_mux_data){
2003 .offset = HHI_VDEC_CLK_CNTL,
2004 .mask = 0x3,
2005 .shift = 25,
2006 .flags = CLK_MUX_ROUND_CLOSEST,
2007 },
2008 .hw.init = &(struct clk_init_data){
2009 .name = "vdec_hcodec_sel",
2010 .ops = &clk_regmap_mux_ops,
2011 .parent_names = meson8b_vdec_parent_names,
2012 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2013 .flags = CLK_SET_RATE_PARENT,
2014 },
2015};
2016
2017static struct clk_regmap meson8b_vdec_hcodec_div = {
2018 .data = &(struct clk_regmap_div_data){
2019 .offset = HHI_VDEC_CLK_CNTL,
2020 .shift = 16,
2021 .width = 7,
2022 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2023 },
2024 .hw.init = &(struct clk_init_data){
2025 .name = "vdec_hcodec_div",
2026 .ops = &clk_regmap_divider_ops,
2027 .parent_names = (const char *[]){ "vdec_hcodec_sel" },
2028 .num_parents = 1,
2029 .flags = CLK_SET_RATE_PARENT,
2030 },
2031};
2032
2033static struct clk_regmap meson8b_vdec_hcodec = {
2034 .data = &(struct clk_regmap_gate_data){
2035 .offset = HHI_VDEC_CLK_CNTL,
2036 .bit_idx = 24,
2037 },
2038 .hw.init = &(struct clk_init_data) {
2039 .name = "vdec_hcodec",
2040 .ops = &clk_regmap_gate_ops,
2041 .parent_names = (const char *[]){ "vdec_hcodec_div" },
2042 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT,
2044 },
2045};
2046
2047static struct clk_regmap meson8b_vdec_2_sel = {
2048 .data = &(struct clk_regmap_mux_data){
2049 .offset = HHI_VDEC2_CLK_CNTL,
2050 .mask = 0x3,
2051 .shift = 9,
2052 .flags = CLK_MUX_ROUND_CLOSEST,
2053 },
2054 .hw.init = &(struct clk_init_data){
2055 .name = "vdec_2_sel",
2056 .ops = &clk_regmap_mux_ops,
2057 .parent_names = meson8b_vdec_parent_names,
2058 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2059 .flags = CLK_SET_RATE_PARENT,
2060 },
2061};
2062
2063static struct clk_regmap meson8b_vdec_2_div = {
2064 .data = &(struct clk_regmap_div_data){
2065 .offset = HHI_VDEC2_CLK_CNTL,
2066 .shift = 0,
2067 .width = 7,
2068 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2069 },
2070 .hw.init = &(struct clk_init_data){
2071 .name = "vdec_2_div",
2072 .ops = &clk_regmap_divider_ops,
2073 .parent_names = (const char *[]){ "vdec_2_sel" },
2074 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT,
2076 },
2077};
2078
2079static struct clk_regmap meson8b_vdec_2 = {
2080 .data = &(struct clk_regmap_gate_data){
2081 .offset = HHI_VDEC2_CLK_CNTL,
2082 .bit_idx = 8,
2083 },
2084 .hw.init = &(struct clk_init_data) {
2085 .name = "vdec_2",
2086 .ops = &clk_regmap_gate_ops,
2087 .parent_names = (const char *[]){ "vdec_2_div" },
2088 .num_parents = 1,
2089 .flags = CLK_SET_RATE_PARENT,
2090 },
2091};
2092
2093static struct clk_regmap meson8b_vdec_hevc_sel = {
2094 .data = &(struct clk_regmap_mux_data){
2095 .offset = HHI_VDEC2_CLK_CNTL,
2096 .mask = 0x3,
2097 .shift = 25,
2098 .flags = CLK_MUX_ROUND_CLOSEST,
2099 },
2100 .hw.init = &(struct clk_init_data){
2101 .name = "vdec_hevc_sel",
2102 .ops = &clk_regmap_mux_ops,
2103 .parent_names = meson8b_vdec_parent_names,
2104 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2105 .flags = CLK_SET_RATE_PARENT,
2106 },
2107};
2108
2109static struct clk_regmap meson8b_vdec_hevc_div = {
2110 .data = &(struct clk_regmap_div_data){
2111 .offset = HHI_VDEC2_CLK_CNTL,
2112 .shift = 16,
2113 .width = 7,
2114 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2115 },
2116 .hw.init = &(struct clk_init_data){
2117 .name = "vdec_hevc_div",
2118 .ops = &clk_regmap_divider_ops,
2119 .parent_names = (const char *[]){ "vdec_hevc_sel" },
2120 .num_parents = 1,
2121 .flags = CLK_SET_RATE_PARENT,
2122 },
2123};
2124
2125static struct clk_regmap meson8b_vdec_hevc_en = {
2126 .data = &(struct clk_regmap_gate_data){
2127 .offset = HHI_VDEC2_CLK_CNTL,
2128 .bit_idx = 24,
2129 },
2130 .hw.init = &(struct clk_init_data) {
2131 .name = "vdec_hevc_en",
2132 .ops = &clk_regmap_gate_ops,
2133 .parent_names = (const char *[]){ "vdec_hevc_div" },
2134 .num_parents = 1,
2135 .flags = CLK_SET_RATE_PARENT,
2136 },
2137};
2138
2139static struct clk_regmap meson8b_vdec_hevc = {
2140 .data = &(struct clk_regmap_mux_data){
2141 .offset = HHI_VDEC2_CLK_CNTL,
2142 .mask = 0x1,
2143 .shift = 31,
2144 .flags = CLK_MUX_ROUND_CLOSEST,
2145 },
2146 .hw.init = &(struct clk_init_data){
2147 .name = "vdec_hevc",
2148 .ops = &clk_regmap_mux_ops,
2149 /* TODO: The second parent is currently unknown */
2150 .parent_names = (const char *[]){ "vdec_hevc_en" },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 },
2154};
2155
1706/* Everything Else (EE) domain gates */2156/* Everything Else (EE) domain gates */
1707 2157
1708static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);2158static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -1966,6 +2416,22 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { · 257 unmodified lines
1966 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,2416 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
1967 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,2417 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
1968 [CLKID_MALI] = &meson8b_mali_0.hw,2418 [CLKID_MALI] = &meson8b_mali_0.hw,
2419 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2420 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2421 [CLKID_VPU] = &meson8b_vpu_0.hw,
2422 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2423 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2424 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
2425 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2426 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2427 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2428 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2429 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2430 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2431 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2432 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2433 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2434 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
1969 [CLK_NR_CLKS] = NULL,2435 [CLK_NR_CLKS] = NULL,
1970 },2436 },
1971 .num = CLK_NR_CLKS,2437 .num = CLK_NR_CLKS,
@@ -2152,6 +2618,240 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { · 180 unmodified lines
2152 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,2618 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2153 [CLKID_MALI_1] = &meson8b_mali_1.hw,2619 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2154 [CLKID_MALI] = &meson8b_mali.hw,2620 [CLKID_MALI] = &meson8b_mali.hw,
2621 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2622 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2623 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
2624 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
2625 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
2626 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
2627 [CLKID_VPU] = &meson8b_vpu.hw,
2628 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2629 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2630 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
2631 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
2632 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
2633 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
2634 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2635 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2636 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2637 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2638 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2639 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2640 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2641 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2642 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2643 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2644 [CLK_NR_CLKS] = NULL,
2645 },
2646 .num = CLK_NR_CLKS,
2647};
2648
2649static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
2650 .hws = {
2651 [CLKID_XTAL] = &meson8b_xtal.hw,
2652 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2653 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2654 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2655 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2656 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2657 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2658 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2659 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2660 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2661 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2662 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2663 [CLKID_CLK81] = &meson8b_clk81.hw,
2664 [CLKID_DDR] = &meson8b_ddr.hw,
2665 [CLKID_DOS] = &meson8b_dos.hw,
2666 [CLKID_ISA] = &meson8b_isa.hw,
2667 [CLKID_PL301] = &meson8b_pl301.hw,
2668 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2669 [CLKID_SPICC] = &meson8b_spicc.hw,
2670 [CLKID_I2C] = &meson8b_i2c.hw,
2671 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2672 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2673 [CLKID_RNG0] = &meson8b_rng0.hw,
2674 [CLKID_UART0] = &meson8b_uart0.hw,
2675 [CLKID_SDHC] = &meson8b_sdhc.hw,
2676 [CLKID_STREAM] = &meson8b_stream.hw,
2677 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2678 [CLKID_SDIO] = &meson8b_sdio.hw,
2679 [CLKID_ABUF] = &meson8b_abuf.hw,
2680 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2681 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2682 [CLKID_SPI] = &meson8b_spi.hw,
2683 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2684 [CLKID_ETH] = &meson8b_eth.hw,
2685 [CLKID_DEMUX] = &meson8b_demux.hw,
2686 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2687 [CLKID_IEC958] = &meson8b_iec958.hw,
2688 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2689 [CLKID_AMCLK] = &meson8b_amclk.hw,
2690 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2691 [CLKID_MIXER] = &meson8b_mixer.hw,
2692 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2693 [CLKID_ADC] = &meson8b_adc.hw,
2694 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2695 [CLKID_AIU] = &meson8b_aiu.hw,
2696 [CLKID_UART1] = &meson8b_uart1.hw,
2697 [CLKID_G2D] = &meson8b_g2d.hw,
2698 [CLKID_USB0] = &meson8b_usb0.hw,
2699 [CLKID_USB1] = &meson8b_usb1.hw,
2700 [CLKID_RESET] = &meson8b_reset.hw,
2701 [CLKID_NAND] = &meson8b_nand.hw,
2702 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2703 [CLKID_USB] = &meson8b_usb.hw,
2704 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2705 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2706 [CLKID_EFUSE] = &meson8b_efuse.hw,
2707 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2708 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2709 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2710 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2711 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2712 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2713 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2714 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2715 [CLKID_DVIN] = &meson8b_dvin.hw,
2716 [CLKID_UART2] = &meson8b_uart2.hw,
2717 [CLKID_SANA] = &meson8b_sana.hw,
2718 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2719 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2720 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2721 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2722 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2723 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2724 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2725 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2726 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2727 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2728 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2729 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2730 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2731 [CLKID_RNG1] = &meson8b_rng1.hw,
2732 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2733 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2734 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2735 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2736 [CLKID_EDP] = &meson8b_edp.hw,
2737 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2738 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2739 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2740 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2741 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2742 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2743 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2744 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2745 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2746 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2747 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2748 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2749 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2750 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2751 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2752 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2753 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2754 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2755 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2756 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2757 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2758 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2759 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2760 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2761 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2762 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2763 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2764 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2765 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2766 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2767 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2768 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2769 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2770 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2771 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2772 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2773 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2774 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2775 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2776 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2777 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2778 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2779 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2780 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2781 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2782 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2783 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2784 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2785 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2786 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2787 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2788 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2789 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2790 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2791 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2792 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2793 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2794 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2795 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2796 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2797 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2798 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2799 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2800 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2801 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2802 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2803 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2804 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2805 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2806 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2807 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2808 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2809 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2810 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2811 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2812 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2813 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2814 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2815 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2816 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2817 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2818 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2819 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2820 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2821 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2822 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2823 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2824 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2825 [CLKID_MALI_0] = &meson8b_mali_0.hw,
2826 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
2827 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2828 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2829 [CLKID_MALI] = &meson8b_mali.hw,
2830 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
2831 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
2832 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
2833 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2834 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
2835 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
2836 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
2837 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
2838 [CLKID_VPU] = &meson8b_vpu.hw,
2839 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2840 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2841 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
2842 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
2843 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
2844 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
2845 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2846 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2847 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2848 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2849 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2850 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2851 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2852 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2853 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2854 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2155 [CLK_NR_CLKS] = NULL,2855 [CLK_NR_CLKS] = NULL,
2156 },2856 },
2157 .num = CLK_NR_CLKS,2857 .num = CLK_NR_CLKS,
@@ -2314,6 +3014,33 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { · 156 unmodified lines
2314 &meson8b_mali_1_div,3014 &meson8b_mali_1_div,
2315 &meson8b_mali_1,3015 &meson8b_mali_1,
2316 &meson8b_mali,3016 &meson8b_mali,
3017 &meson8m2_gp_pll_dco,
3018 &meson8m2_gp_pll,
3019 &meson8b_vpu_0_sel,
3020 &meson8m2_vpu_0_sel,
3021 &meson8b_vpu_0_div,
3022 &meson8b_vpu_0,
3023 &meson8b_vpu_1_sel,
3024 &meson8m2_vpu_1_sel,
3025 &meson8b_vpu_1_div,
3026 &meson8b_vpu_1,
3027 &meson8b_vpu,
3028 &meson8b_vdec_1_sel,
3029 &meson8b_vdec_1_1_div,
3030 &meson8b_vdec_1_1,
3031 &meson8b_vdec_1_2_div,
3032 &meson8b_vdec_1_2,
3033 &meson8b_vdec_1,
3034 &meson8b_vdec_hcodec_sel,
3035 &meson8b_vdec_hcodec_div,
3036 &meson8b_vdec_hcodec,
3037 &meson8b_vdec_2_sel,
3038 &meson8b_vdec_2_div,
3039 &meson8b_vdec_2,
3040 &meson8b_vdec_hevc_sel,
3041 &meson8b_vdec_hevc_div,
3042 &meson8b_vdec_hevc_en,
3043 &meson8b_vdec_hevc,
2317};3044};
2318 3045
2319static const struct meson8b_clk_reset_line {3046static const struct meson8b_clk_reset_line {
@@ -2558,9 +3285,14 @@ static void __init meson8b_clkc_init(struct device_node *np) · 238 unmodified lines
2558 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);3285 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
2559}3286}
2560 3287
3288static void __init meson8m2_clkc_init(struct device_node *np)
3289{
3290 return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3291}
3292
2561CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",3293CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
2562 meson8_clkc_init);3294 meson8_clkc_init);
2563CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",3295CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
2564 meson8b_clkc_init);3296 meson8b_clkc_init);
2565CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",3297CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
2566 meson8b_clkc_init);3298 meson8m2_clkc_init);
drivers/clk/meson/meson8b.h+26−1
@@ -19,6 +19,7 @@ · 18 unmodified lines
19 *19 *
20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
21 */21 */
22#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
22#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */23#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
23#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */24#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
24#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */25#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
@@ -34,7 +35,11 @@ · 9 unmodified lines
34#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */35#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
35#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */36#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
36#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */37#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
38#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
37#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */39#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
40#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
41#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
42#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
38#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */43#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
39#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */44#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
40#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */45#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
@@ -146,8 +151,28 @@ · 105 unmodified lines
146#define CLKID_MALI_1_SEL 178151#define CLKID_MALI_1_SEL 178
147#define CLKID_MALI_1_DIV 179152#define CLKID_MALI_1_DIV 179
148#define CLKID_MALI_1 180153#define CLKID_MALI_1 180
154#define CLKID_GP_PLL_DCO 181
155#define CLKID_GP_PLL 182
156#define CLKID_VPU_0_SEL 183
157#define CLKID_VPU_0_DIV 184
158#define CLKID_VPU_0 185
159#define CLKID_VPU_1_SEL 186
160#define CLKID_VPU_1_DIV 187
161#define CLKID_VPU_1 189
162#define CLKID_VDEC_1_SEL 191
163#define CLKID_VDEC_1_1_DIV 192
164#define CLKID_VDEC_1_1 193
165#define CLKID_VDEC_1_2_DIV 194
166#define CLKID_VDEC_1_2 195
167#define CLKID_VDEC_HCODEC_SEL 197
168#define CLKID_VDEC_HCODEC_DIV 198
169#define CLKID_VDEC_2_SEL 200
170#define CLKID_VDEC_2_DIV 201
171#define CLKID_VDEC_HEVC_SEL 203
172#define CLKID_VDEC_HEVC_DIV 204
173#define CLKID_VDEC_HEVC_EN 205
149 174
150#define CLK_NR_CLKS 181175#define CLK_NR_CLKS 207
151 176
152/*177/*
153 * include the CLKID and RESETID that have178 * include the CLKID and RESETID that have
drivers/clk/nxp/clk-lpc18xx-ccu.c+3−3
@@ -142,7 +142,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable) · 141 unmodified lines
142 * Divider field is write only, so divider stat field must142 * Divider field is write only, so divider stat field must
143 * be read so divider field can be set accordingly.143 * be read so divider field can be set accordingly.
144 */144 */
145 val = clk_readl(gate->reg);145 val = readl(gate->reg);
146 if (val & LPC18XX_CCU_DIVSTAT)146 if (val & LPC18XX_CCU_DIVSTAT)
147 val |= LPC18XX_CCU_DIV;147 val |= LPC18XX_CCU_DIV;
148 148
@@ -155,12 +155,12 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable) · 6 unmodified lines
155 * and the next write should clear the RUN bit.155 * and the next write should clear the RUN bit.
156 */156 */
157 val |= LPC18XX_CCU_AUTO;157 val |= LPC18XX_CCU_AUTO;
158 clk_writel(val, gate->reg);158 writel(val, gate->reg);
159 159
160 val &= ~LPC18XX_CCU_RUN;160 val &= ~LPC18XX_CCU_RUN;
161 }161 }
162 162
163 clk_writel(val, gate->reg);163 writel(val, gate->reg);
164 164
165 return 0;165 return 0;
166}166}
drivers/clk/nxp/clk-lpc18xx-cgu.c+12−12
@@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw, · 351 unmodified lines
352 struct lpc18xx_pll *pll = to_lpc_pll(hw);352 struct lpc18xx_pll *pll = to_lpc_pll(hw);
353 u32 ctrl, mdiv, msel, npdiv;353 u32 ctrl, mdiv, msel, npdiv;
354 354
355 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);355 ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
356 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);356 mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
357 npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);357 npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
358 358
359 if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)359 if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
360 return parent_rate;360 return parent_rate;
@@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, · 54 unmodified lines
415 m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;415 m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
416 416
417 /* Power down PLL, disable clk output and dividers */417 /* Power down PLL, disable clk output and dividers */
418 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);418 ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
419 ctrl |= LPC18XX_PLL0_CTRL_PD;419 ctrl |= LPC18XX_PLL0_CTRL_PD;
420 ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |420 ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
421 LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);421 LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
422 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);422 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
423 423
424 /* Configure new PLL settings */424 /* Configure new PLL settings */
425 clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);425 writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
426 clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);426 writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
427 427
428 /* Power up PLL and wait for lock */428 /* Power up PLL and wait for lock */
429 ctrl &= ~LPC18XX_PLL0_CTRL_PD;429 ctrl &= ~LPC18XX_PLL0_CTRL_PD;
430 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);430 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
431 do {431 do {
432 udelay(10);432 udelay(10);
433 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);433 stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
434 if (stat & LPC18XX_PLL0_STAT_LOCK) {434 if (stat & LPC18XX_PLL0_STAT_LOCK) {
435 ctrl |= LPC18XX_PLL0_CTRL_CLKEN;435 ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
436 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);436 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
437 437
438 return 0;438 return 0;
439 }439 }
@@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw, · 18 unmodified lines
458 bool direct, fbsel;458 bool direct, fbsel;
459 u32 stat, ctrl;459 u32 stat, ctrl;
460 460
461 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);461 stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
462 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);462 ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
463 463
464 direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;464 direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
465 fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;465 fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
drivers/clk/nxp/clk-lpc32xx.c+3−4
@@ -1085,13 +1085,12 @@ struct clk_hw_proto { · 1084 unmodified lines
1085 };1085 };
1086};1086};
1087 1087
1088#define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \1088#define LPC32XX_DEFINE_FIXED(_idx, _rate) \
1089[CLK_PREFIX(_idx)] = { \1089[CLK_PREFIX(_idx)] = { \
1090 .type = CLK_FIXED, \1090 .type = CLK_FIXED, \
1091 { \1091 { \
1092 .f = { \1092 .f = { \
1093 .fixed_rate = (_rate), \1093 .fixed_rate = (_rate), \
1094 .flags = (_flags), \
1095 }, \1094 }, \
1096 }, \1095 }, \
1097}1096}
@@ -1225,7 +1224,7 @@ struct clk_hw_proto { · 127 unmodified lines
1225}1224}
1226 1225
1227static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {1226static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
1228 LPC32XX_DEFINE_FIXED(RTC, 32768, 0),1227 LPC32XX_DEFINE_FIXED(RTC, 32768),
1229 LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),1228 LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
1230 LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),1229 LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
1231 LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),1230 LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
@@ -1468,7 +1467,7 @@ static struct clk * __init lpc32xx_clk_register(u32 id) · 236 unmodified lines
1468 struct clk_fixed_rate *fixed = &clk_hw->f;1467 struct clk_fixed_rate *fixed = &clk_hw->f;
1469 1468
1470 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,1469 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
1471 parents[0], fixed->flags, fixed->fixed_rate);1470 parents[0], 0, fixed->fixed_rate);
1472 break;1471 break;
1473 }1472 }
1474 default:1473 default:
drivers/clk/rockchip/clk-ddr.c+1−1
@@ -82,7 +82,7 @@ static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw) · 81 unmodified lines
82 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);82 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
83 u32 val;83 u32 val;
84 84
85 val = clk_readl(ddrclk->reg_base +85 val = readl(ddrclk->reg_base +
86 ddrclk->mux_offset) >> ddrclk->mux_shift;86 ddrclk->mux_offset) >> ddrclk->mux_shift;
87 val &= GENMASK(ddrclk->mux_width - 1, 0);87 val &= GENMASK(ddrclk->mux_width - 1, 0);
88 88
drivers/clk/rockchip/clk-half-divider.c+3−3
@@ -24,7 +24,7 @@ static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw, · 23 unmodified lines
24 struct clk_divider *divider = to_clk_divider(hw);24 struct clk_divider *divider = to_clk_divider(hw);
25 unsigned int val;25 unsigned int val;
26 26
27 val = clk_readl(divider->reg) >> divider->shift;27 val = readl(divider->reg) >> divider->shift;
28 val &= div_mask(divider->width);28 val &= div_mask(divider->width);
29 val = val * 2 + 3;29 val = val * 2 + 3;
30 30
@@ -124,11 +124,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate, · 93 unmodified lines
124 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {124 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
125 val = div_mask(divider->width) << (divider->shift + 16);125 val = div_mask(divider->width) << (divider->shift + 16);
126 } else {126 } else {
127 val = clk_readl(divider->reg);127 val = readl(divider->reg);
128 val &= ~(div_mask(divider->width) << divider->shift);128 val &= ~(div_mask(divider->width) << divider->shift);
129 }129 }
130 val |= value << divider->shift;130 val |= value << divider->shift;
131 clk_writel(val, divider->reg);131 writel(val, divider->reg);
132 132
133 if (divider->lock)133 if (divider->lock)
134 spin_unlock_irqrestore(divider->lock, flags);134 spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/tegra/clk-tegra124.c+2−2
@@ -1466,9 +1466,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) · 1465 unmodified lines
1466 tegra_pmc_clk_init(pmc_base, tegra124_clks);1466 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1467 1467
1468 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */1468 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1469 plld_base = clk_readl(clk_base + PLLD_BASE);1469 plld_base = readl(clk_base + PLLD_BASE);
1470 plld_base &= ~BIT(25);1470 plld_base &= ~BIT(25);
1471 clk_writel(plld_base, clk_base + PLLD_BASE);1471 writel(plld_base, clk_base + PLLD_BASE);
1472}1472}
1473 1473
1474/**1474/**
drivers/clk/tegra/clk-tegra210.c+3−3
@@ -3557,7 +3557,7 @@ static void __init tegra210_clock_init(struct device_node *np) · 3556 unmodified lines
3557 if (!clks)3557 if (!clks)
3558 return;3558 return;
3559 3559
3560 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;3560 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3561 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;3561 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3562 3562
3563 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,3563 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
@@ -3574,9 +3574,9 @@ static void __init tegra210_clock_init(struct device_node *np) · 10 unmodified lines
3574 tegra_pmc_clk_init(pmc_base, tegra210_clks);3574 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3575 3575
3576 /* For Tegra210, PLLD is the only source for DSIA & DSIB */3576 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3577 value = clk_readl(clk_base + PLLD_BASE);3577 value = readl(clk_base + PLLD_BASE);
3578 value &= ~BIT(25);3578 value &= ~BIT(25);
3579 clk_writel(value, clk_base + PLLD_BASE);3579 writel(value, clk_base + PLLD_BASE);
3580 3580
3581 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;3581 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3582 3582
drivers/clk/zynq/clkc.c+3−3
@@ -158,7 +158,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, · 157 unmodified lines
158 clks[fclk] = clk_register_gate(NULL, clk_name,158 clks[fclk] = clk_register_gate(NULL, clk_name,
159 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,159 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
160 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);160 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
161 enable_reg = clk_readl(fclk_gate_reg) & 1;161 enable_reg = readl(fclk_gate_reg) & 1;
162 if (enable && !enable_reg) {162 if (enable && !enable_reg) {
163 if (clk_prepare_enable(clks[fclk]))163 if (clk_prepare_enable(clks[fclk]))
164 pr_warn("%s: FCLK%u enable failed\n", __func__,164 pr_warn("%s: FCLK%u enable failed\n", __func__,
@@ -287,7 +287,7 @@ static void __init zynq_clk_setup(struct device_node *np) · 122 unmodified lines
287 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);287 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
288 288
289 /* CPU clocks */289 /* CPU clocks */
290 tmp = clk_readl(SLCR_621_TRUE) & 1;290 tmp = readl(SLCR_621_TRUE) & 1;
291 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,291 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
292 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,292 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
293 &armclk_lock);293 &armclk_lock);
@@ -510,7 +510,7 @@ static void __init zynq_clk_setup(struct device_node *np) · 216 unmodified lines
510 &dbgclk_lock);510 &dbgclk_lock);
511 511
512 /* leave debug clocks in the state the bootloader set them up to */512 /* leave debug clocks in the state the bootloader set them up to */
513 tmp = clk_readl(SLCR_DBG_CLK_CTRL);513 tmp = readl(SLCR_DBG_CLK_CTRL);
514 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)514 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
515 if (clk_prepare_enable(clks[dbg_trc]))515 if (clk_prepare_enable(clks[dbg_trc]))
516 pr_warn("%s: trace clk enable failed\n", __func__);516 pr_warn("%s: trace clk enable failed\n", __func__);
drivers/clk/zynq/pll.c+9−9
@@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, · 89 unmodified lines
90 * makes probably sense to redundantly save fbdiv in the struct90 * makes probably sense to redundantly save fbdiv in the struct
91 * zynq_pll to save the IO access.91 * zynq_pll to save the IO access.
92 */92 */
93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>93 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
94 PLLCTRL_FBDIV_SHIFT;94 PLLCTRL_FBDIV_SHIFT;
95 95
96 return parent_rate * fbdiv;96 return parent_rate * fbdiv;
@@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw) · 15 unmodified lines
112 112
113 spin_lock_irqsave(clk->lock, flags);113 spin_lock_irqsave(clk->lock, flags);
114 114
115 reg = clk_readl(clk->pll_ctrl);115 reg = readl(clk->pll_ctrl);
116 116
117 spin_unlock_irqrestore(clk->lock, flags);117 spin_unlock_irqrestore(clk->lock, flags);
118 118
@@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw) · 19 unmodified lines
138 /* Power up PLL and wait for lock */138 /* Power up PLL and wait for lock */
139 spin_lock_irqsave(clk->lock, flags);139 spin_lock_irqsave(clk->lock, flags);
140 140
141 reg = clk_readl(clk->pll_ctrl);141 reg = readl(clk->pll_ctrl);
142 reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);142 reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
143 clk_writel(reg, clk->pll_ctrl);143 writel(reg, clk->pll_ctrl);
144 while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))144 while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
145 ;145 ;
146 146
147 spin_unlock_irqrestore(clk->lock, flags);147 spin_unlock_irqrestore(clk->lock, flags);
@@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw) · 20 unmodified lines
168 /* shut down PLL */168 /* shut down PLL */
169 spin_lock_irqsave(clk->lock, flags);169 spin_lock_irqsave(clk->lock, flags);
170 170
171 reg = clk_readl(clk->pll_ctrl);171 reg = readl(clk->pll_ctrl);
172 reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;172 reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
173 clk_writel(reg, clk->pll_ctrl);173 writel(reg, clk->pll_ctrl);
174 174
175 spin_unlock_irqrestore(clk->lock, flags);175 spin_unlock_irqrestore(clk->lock, flags);
176}176}
@@ -223,9 +223,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent, · 46 unmodified lines
223 223
224 spin_lock_irqsave(pll->lock, flags);224 spin_lock_irqsave(pll->lock, flags);
225 225
226 reg = clk_readl(pll->pll_ctrl);226 reg = readl(pll->pll_ctrl);
227 reg &= ~PLLCTRL_BPQUAL_MASK;227 reg &= ~PLLCTRL_BPQUAL_MASK;
228 clk_writel(reg, pll->pll_ctrl);228 writel(reg, pll->pll_ctrl);
229 229
230 spin_unlock_irqrestore(pll->lock, flags);230 spin_unlock_irqrestore(pll->lock, flags);
231 231
include/dt-bindings/clock/axg-audio-clkc.h+10−20
@@ -7,26 +7,6 @@ · 6 unmodified lines
7#ifndef __AXG_AUDIO_CLKC_BINDINGS_H7#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
8#define __AXG_AUDIO_CLKC_BINDINGS_H8#define __AXG_AUDIO_CLKC_BINDINGS_H
9 9
10#define AUD_CLKID_SLV_SCLK0 9
11#define AUD_CLKID_SLV_SCLK1 10
12#define AUD_CLKID_SLV_SCLK2 11
13#define AUD_CLKID_SLV_SCLK3 12
14#define AUD_CLKID_SLV_SCLK4 13
15#define AUD_CLKID_SLV_SCLK5 14
16#define AUD_CLKID_SLV_SCLK6 15
17#define AUD_CLKID_SLV_SCLK7 16
18#define AUD_CLKID_SLV_SCLK8 17
19#define AUD_CLKID_SLV_SCLK9 18
20#define AUD_CLKID_SLV_LRCLK0 19
21#define AUD_CLKID_SLV_LRCLK1 20
22#define AUD_CLKID_SLV_LRCLK2 21
23#define AUD_CLKID_SLV_LRCLK3 22
24#define AUD_CLKID_SLV_LRCLK4 23
25#define AUD_CLKID_SLV_LRCLK5 24
26#define AUD_CLKID_SLV_LRCLK6 25
27#define AUD_CLKID_SLV_LRCLK7 26
28#define AUD_CLKID_SLV_LRCLK8 27
29#define AUD_CLKID_SLV_LRCLK9 28
30#define AUD_CLKID_DDR_ARB 2910#define AUD_CLKID_DDR_ARB 29
31#define AUD_CLKID_PDM 3011#define AUD_CLKID_PDM 30
32#define AUD_CLKID_TDMIN_A 3112#define AUD_CLKID_TDMIN_A 31
@@ -90,5 +70,15 @@ · 57 unmodified lines
90#define AUD_CLKID_TDMOUT_A_LRCLK 13470#define AUD_CLKID_TDMOUT_A_LRCLK 134
91#define AUD_CLKID_TDMOUT_B_LRCLK 13571#define AUD_CLKID_TDMOUT_B_LRCLK 135
92#define AUD_CLKID_TDMOUT_C_LRCLK 13672#define AUD_CLKID_TDMOUT_C_LRCLK 136
73#define AUD_CLKID_SPDIFOUT_B 151
74#define AUD_CLKID_SPDIFOUT_B_CLK 152
75#define AUD_CLKID_TDM_MCLK_PAD0 155
76#define AUD_CLKID_TDM_MCLK_PAD1 156
77#define AUD_CLKID_TDM_LRCLK_PAD0 157
78#define AUD_CLKID_TDM_LRCLK_PAD1 158
79#define AUD_CLKID_TDM_LRCLK_PAD2 159
80#define AUD_CLKID_TDM_SCLK_PAD0 160
81#define AUD_CLKID_TDM_SCLK_PAD1 161
82#define AUD_CLKID_TDM_SCLK_PAD2 162
93 83
94#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */84#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
include/dt-bindings/clock/g12a-aoclkc.h+2−0
@@ -26,7 +26,9 @@ · 25 unmodified lines
26#define CLKID_AO_M4_FCLK 1326#define CLKID_AO_M4_FCLK 13
27#define CLKID_AO_M4_HCLK 1427#define CLKID_AO_M4_HCLK 14
28#define CLKID_AO_CLK81 1528#define CLKID_AO_CLK81 15
29#define CLKID_AO_SAR_ADC_SEL 16
29#define CLKID_AO_SAR_ADC_CLK 1830#define CLKID_AO_SAR_ADC_CLK 18
31#define CLKID_AO_CTS_OSCIN 19
30#define CLKID_AO_32K 2332#define CLKID_AO_32K 23
31#define CLKID_AO_CEC 2733#define CLKID_AO_CEC 27
32#define CLKID_AO_CTS_RTC_OSCIN 2834#define CLKID_AO_CTS_RTC_OSCIN 28
include/dt-bindings/clock/g12a-clkc.h+5−0
@@ -131,5 +131,10 @@ · 130 unmodified lines
131#define CLKID_MALI_1 174131#define CLKID_MALI_1 174
132#define CLKID_MALI 175132#define CLKID_MALI 175
133#define CLKID_MPLL_5OM 177133#define CLKID_MPLL_5OM 177
134#define CLKID_CPU_CLK 187
135#define CLKID_PCIE_PLL 201
136#define CLKID_VDEC_1 204
137#define CLKID_VDEC_HEVC 207
138#define CLKID_VDEC_HEVCF 210
134 139
135#endif /* __G12A_CLKC_H */140#endif /* __G12A_CLKC_H */
include/dt-bindings/clock/meson8b-clkc.h+5−1
@@ -103,10 +103,14 @@ · 102 unmodified lines
103#define CLKID_MPLL1 94103#define CLKID_MPLL1 94
104#define CLKID_MPLL2 95104#define CLKID_MPLL2 95
105#define CLKID_NAND_CLK 112105#define CLKID_NAND_CLK 112
106#define CLKID_ABP 124
107#define CLKID_APB 124106#define CLKID_APB 124
108#define CLKID_PERIPH 126107#define CLKID_PERIPH 126
109#define CLKID_AXI 128108#define CLKID_AXI 128
110#define CLKID_L2_DRAM 130109#define CLKID_L2_DRAM 130
110#define CLKID_VPU 190
111#define CLKID_VDEC_1 196
112#define CLKID_VDEC_HCODEC 199
113#define CLKID_VDEC_2 202
114#define CLKID_VDEC_HEVC 206
111 115
112#endif /* __MESON8B_CLKC_H */116#endif /* __MESON8B_CLKC_H */
include/linux/clk-provider.h+31−59
@@ -24,7 +24,7 @@ · 23 unmodified lines
24#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */24#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */25#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
26 /* unused */26 /* unused */
27#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */27#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */
28#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */28#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
29#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */29#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
30#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */30#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
@@ -307,7 +307,6 @@ struct clk_fixed_rate { · 276 unmodified lines
307 struct clk_hw hw;307 struct clk_hw hw;
308 unsigned long fixed_rate;308 unsigned long fixed_rate;
309 unsigned long fixed_accuracy;309 unsigned long fixed_accuracy;
310 u8 flags;
311};310};
312 311
313#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)312#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
@@ -349,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np); · 35 unmodified lines
349 * of this register, and mask of gate bits are in higher 16-bit of this348 * of this register, and mask of gate bits are in higher 16-bit of this
350 * register. While setting the gate bits, higher 16-bit should also be349 * register. While setting the gate bits, higher 16-bit should also be
351 * updated to indicate changing gate bits.350 * updated to indicate changing gate bits.
351 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
352 * the gate register. Setting this flag makes the register accesses big
353 * endian.
352 */354 */
353struct clk_gate {355struct clk_gate {
354 struct clk_hw hw;356 struct clk_hw hw;
@@ -362,6 +364,7 @@ struct clk_gate { · 7 unmodified lines
362 364
363#define CLK_GATE_SET_TO_DISABLE BIT(0)365#define CLK_GATE_SET_TO_DISABLE BIT(0)
364#define CLK_GATE_HIWORD_MASK BIT(1)366#define CLK_GATE_HIWORD_MASK BIT(1)
367#define CLK_GATE_BIG_ENDIAN BIT(2)
365 368
366extern const struct clk_ops clk_gate_ops;369extern const struct clk_ops clk_gate_ops;
367struct clk *clk_register_gate(struct device *dev, const char *name,370struct clk *clk_register_gate(struct device *dev, const char *name,
@@ -417,6 +420,9 @@ struct clk_div_table { · 49 unmodified lines
417 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED420 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
418 * except when the value read from the register is zero, the divisor is421 * except when the value read from the register is zero, the divisor is
419 * 2^width of the field.422 * 2^width of the field.
423 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
424 * for the divider register. Setting this flag makes the register accesses
425 * big endian.
420 */426 */
421struct clk_divider {427struct clk_divider {
422 struct clk_hw hw;428 struct clk_hw hw;
@@ -438,6 +444,7 @@ struct clk_divider { · 15 unmodified lines
438#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)444#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
439#define CLK_DIVIDER_READ_ONLY BIT(5)445#define CLK_DIVIDER_READ_ONLY BIT(5)
440#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)446#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
447#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
441 448
442extern const struct clk_ops clk_divider_ops;449extern const struct clk_ops clk_divider_ops;
443extern const struct clk_ops clk_divider_ro_ops;450extern const struct clk_ops clk_divider_ro_ops;
@@ -499,8 +506,13 @@ void clk_hw_unregister_divider(struct clk_hw *hw); · 55 unmodified lines
499 * register, and mask of mux bits are in higher 16-bit of this register.506 * register, and mask of mux bits are in higher 16-bit of this register.
500 * While setting the mux bits, higher 16-bit should also be updated to507 * While setting the mux bits, higher 16-bit should also be updated to
501 * indicate changing mux bits.508 * indicate changing mux bits.
509 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
510 * .get_parent clk_op.
502 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired511 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
503 * frequency.512 * frequency.
513 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
514 * the mux register. Setting this flag makes the register accesses big
515 * endian.
504 */516 */
505struct clk_mux {517struct clk_mux {
506 struct clk_hw hw;518 struct clk_hw hw;
@@ -519,6 +531,7 @@ struct clk_mux { · 12 unmodified lines
519#define CLK_MUX_HIWORD_MASK BIT(2)531#define CLK_MUX_HIWORD_MASK BIT(2)
520#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */532#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
521#define CLK_MUX_ROUND_CLOSEST BIT(4)533#define CLK_MUX_ROUND_CLOSEST BIT(4)
534#define CLK_MUX_BIG_ENDIAN BIT(5)
522 535
523extern const struct clk_ops clk_mux_ops;536extern const struct clk_ops clk_mux_ops;
524extern const struct clk_ops clk_mux_ro_ops;537extern const struct clk_ops clk_mux_ro_ops;
@@ -602,6 +615,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); · 77 unmodified lines
602 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED615 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
603 * is set then the numerator and denominator are both the value read616 * is set then the numerator and denominator are both the value read
604 * plus one.617 * plus one.
618 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
619 * used for the divider register. Setting this flag makes the register
620 * accesses big endian.
605 */621 */
606struct clk_fractional_divider {622struct clk_fractional_divider {
607 struct clk_hw hw;623 struct clk_hw hw;
@@ -622,6 +638,7 @@ struct clk_fractional_divider { · 14 unmodified lines
622#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)638#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
623 639
624#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)640#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
641#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
625 642
626extern const struct clk_ops clk_fractional_divider_ops;643extern const struct clk_ops clk_fractional_divider_ops;
627struct clk *clk_register_fractional_divider(struct device *dev,644struct clk *clk_register_fractional_divider(struct device *dev,
@@ -654,6 +671,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); · 26 unmodified lines
654 * leaving the parent rate unmodified.671 * leaving the parent rate unmodified.
655 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be672 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
656 * rounded to the closest integer instead of the down one.673 * rounded to the closest integer instead of the down one.
674 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
675 * used for the multiplier register. Setting this flag makes the register
676 * accesses big endian.
657 */677 */
658struct clk_multiplier {678struct clk_multiplier {
659 struct clk_hw hw;679 struct clk_hw hw;
@@ -668,6 +688,7 @@ struct clk_multiplier { · 8 unmodified lines
668 688
669#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)689#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
670#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)690#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
691#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
671 692
672extern const struct clk_ops clk_multiplier_ops;693extern const struct clk_ops clk_multiplier_ops;
673 694
@@ -712,16 +733,19 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, · 38 unmodified lines
712 unsigned long flags);733 unsigned long flags);
713void clk_hw_unregister_composite(struct clk_hw *hw);734void clk_hw_unregister_composite(struct clk_hw *hw);
714 735
715/***736/**
716 * struct clk_gpio_gate - gpio gated clock737 * struct clk_gpio - gpio gated clock
717 *738 *
718 * @hw: handle between common and hardware-specific interfaces739 * @hw: handle between common and hardware-specific interfaces
719 * @gpiod: gpio descriptor740 * @gpiod: gpio descriptor
720 *741 *
721 * Clock with a gpio control for enabling and disabling the parent clock.742 * Clock with a gpio control for enabling and disabling the parent clock
722 * Implements .enable, .disable and .is_enabled743 * or switching between two parents by asserting or deasserting the gpio.
744 *
745 * Implements .enable, .disable and .is_enabled or
746 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
747 * is used.
723 */748 */
724
725struct clk_gpio {749struct clk_gpio {
726 struct clk_hw hw;750 struct clk_hw hw;
727 struct gpio_desc *gpiod;751 struct gpio_desc *gpiod;
@@ -738,16 +762,6 @@ struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, · 10 unmodified lines
738 unsigned long flags);762 unsigned long flags);
739void clk_hw_unregister_gpio_gate(struct clk_hw *hw);763void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
740 764
741/**
742 * struct clk_gpio_mux - gpio controlled clock multiplexer
743 *
744 * @hw: see struct clk_gpio
745 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
746 *
747 * Clock with a gpio control for selecting the parent clock.
748 * Implements .get_parent, .set_parent and .determine_rate
749 */
750
751extern const struct clk_ops clk_gpio_mux_ops;765extern const struct clk_ops clk_gpio_mux_ops;
752struct clk *clk_register_gpio_mux(struct device *dev, const char *name,766struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
753 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,767 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
@@ -757,17 +771,6 @@ struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, · 3 unmodified lines
757 unsigned long flags);771 unsigned long flags);
758void clk_hw_unregister_gpio_mux(struct clk_hw *hw);772void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
759 773
760/**
761 * clk_register - allocate a new clock, register it and return an opaque cookie
762 * @dev: device that is registering this clock
763 * @hw: link to hardware-specific clock data
764 *
765 * clk_register is the primary interface for populating the clock tree with new
766 * clock nodes. It returns a pointer to the newly allocated struct clk which
767 * cannot be dereferenced by driver code but may be used in conjuction with the
768 * rest of the clock API. In the event of an error clk_register will return an
769 * error code; drivers must test for an error code after calling clk_register.
770 */
771struct clk *clk_register(struct device *dev, struct clk_hw *hw);774struct clk *clk_register(struct device *dev, struct clk_hw *hw);
772struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);775struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
773 776
@@ -993,37 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index, · 219 unmodified lines
993}996}
994#endif /* CONFIG_OF */997#endif /* CONFIG_OF */
995 998
996/*
997 * wrap access to peripherals in accessor routines
998 * for improved portability across platforms
999 */
1000
1001#if IS_ENABLED(CONFIG_PPC)
1002
1003static inline u32 clk_readl(u32 __iomem *reg)
1004{
1005 return ioread32be(reg);
1006}
1007
1008static inline void clk_writel(u32 val, u32 __iomem *reg)
1009{
1010 iowrite32be(val, reg);
1011}
1012
1013#else /* platform dependent I/O accessors */
1014
1015static inline u32 clk_readl(u32 __iomem *reg)
1016{
1017 return readl(reg);
1018}
1019
1020static inline void clk_writel(u32 val, u32 __iomem *reg)
1021{
1022 writel(val, reg);
1023}
1024
1025#endif /* platform dependent I/O accessors */
1026
1027void clk_gate_restore_context(struct clk_hw *hw);999void clk_gate_restore_context(struct clk_hw *hw);
1028 1000
1029#endif /* CONFIG_COMMON_CLK */1001#endif /* CONFIG_COMMON_CLK */

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