History

Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next

- Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support

Stephen Boyd committed 7 years ago

Commit f6111b95 parents 2ed3b91 f14382d 043f44a 6e4fcc3 5834fd736 files · +2424 −710Browse files

Showing the changes to include/linux (1 of 36 files). Show all

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include/linux/clk-provider.h+31−59
@@ -24,7 +24,7 @@ · 23 unmodified lines
2424 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
2525 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
2626 /* unused */
27−#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
27+#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */
2828 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
2929 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
3030 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
@@ -307,7 +307,6 @@ struct clk_fixed_rate { · 276 unmodified lines
307307 struct clk_hw hw;
308308 unsigned long fixed_rate;
309309 unsigned long fixed_accuracy;
310− u8 flags;
311310 };
312311
313312 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
@@ -349,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np); · 35 unmodified lines
349348 * of this register, and mask of gate bits are in higher 16-bit of this
350349 * register. While setting the gate bits, higher 16-bit should also be
351350 * updated to indicate changing gate bits.
351+ * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
352+ * the gate register. Setting this flag makes the register accesses big
353+ * endian.
352354 */
353355 struct clk_gate {
354356 struct clk_hw hw;
@@ -362,6 +364,7 @@ struct clk_gate { · 7 unmodified lines
362364
363365 #define CLK_GATE_SET_TO_DISABLE BIT(0)
364366 #define CLK_GATE_HIWORD_MASK BIT(1)
367+#define CLK_GATE_BIG_ENDIAN BIT(2)
365368
366369 extern const struct clk_ops clk_gate_ops;
367370 struct clk *clk_register_gate(struct device *dev, const char *name,
@@ -417,6 +420,9 @@ struct clk_div_table { · 49 unmodified lines
417420 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
418421 * except when the value read from the register is zero, the divisor is
419422 * 2^width of the field.
423+ * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
424+ * for the divider register. Setting this flag makes the register accesses
425+ * big endian.
420426 */
421427 struct clk_divider {
422428 struct clk_hw hw;
@@ -438,6 +444,7 @@ struct clk_divider { · 15 unmodified lines
438444 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
439445 #define CLK_DIVIDER_READ_ONLY BIT(5)
440446 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
447+#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
441448
442449 extern const struct clk_ops clk_divider_ops;
443450 extern const struct clk_ops clk_divider_ro_ops;
@@ -499,8 +506,13 @@ void clk_hw_unregister_divider(struct clk_hw *hw); · 55 unmodified lines
499506 * register, and mask of mux bits are in higher 16-bit of this register.
500507 * While setting the mux bits, higher 16-bit should also be updated to
501508 * indicate changing mux bits.
509+ * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
510+ * .get_parent clk_op.
502511 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
503512 * frequency.
513+ * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
514+ * the mux register. Setting this flag makes the register accesses big
515+ * endian.
504516 */
505517 struct clk_mux {
506518 struct clk_hw hw;
@@ -519,6 +531,7 @@ struct clk_mux { · 12 unmodified lines
519531 #define CLK_MUX_HIWORD_MASK BIT(2)
520532 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
521533 #define CLK_MUX_ROUND_CLOSEST BIT(4)
534+#define CLK_MUX_BIG_ENDIAN BIT(5)
522535
523536 extern const struct clk_ops clk_mux_ops;
524537 extern const struct clk_ops clk_mux_ro_ops;
@@ -602,6 +615,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); · 77 unmodified lines
602615 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
603616 * is set then the numerator and denominator are both the value read
604617 * plus one.
618+ * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
619+ * used for the divider register. Setting this flag makes the register
620+ * accesses big endian.
605621 */
606622 struct clk_fractional_divider {
607623 struct clk_hw hw;
@@ -622,6 +638,7 @@ struct clk_fractional_divider { · 14 unmodified lines
622638 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
623639
624640 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
641+#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
625642
626643 extern const struct clk_ops clk_fractional_divider_ops;
627644 struct clk *clk_register_fractional_divider(struct device *dev,
@@ -654,6 +671,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); · 26 unmodified lines
654671 * leaving the parent rate unmodified.
655672 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
656673 * rounded to the closest integer instead of the down one.
674+ * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
675+ * used for the multiplier register. Setting this flag makes the register
676+ * accesses big endian.
657677 */
658678 struct clk_multiplier {
659679 struct clk_hw hw;
@@ -668,6 +688,7 @@ struct clk_multiplier { · 8 unmodified lines
668688
669689 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
670690 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
691+#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
671692
672693 extern const struct clk_ops clk_multiplier_ops;
673694
@@ -712,16 +733,19 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, · 38 unmodified lines
712733 unsigned long flags);
713734 void clk_hw_unregister_composite(struct clk_hw *hw);
714735
715−/***
716− * struct clk_gpio_gate - gpio gated clock
736+/**
737+ * struct clk_gpio - gpio gated clock
717738 *
718739 * @hw: handle between common and hardware-specific interfaces
719740 * @gpiod: gpio descriptor
720741 *
721− * Clock with a gpio control for enabling and disabling the parent clock.
722− * Implements .enable, .disable and .is_enabled
742+ * Clock with a gpio control for enabling and disabling the parent clock
743+ * or switching between two parents by asserting or deasserting the gpio.
744+ *
745+ * Implements .enable, .disable and .is_enabled or
746+ * .get_parent, .set_parent and .determine_rate depending on which clk_ops
747+ * is used.
723748 */
724−
725749 struct clk_gpio {
726750 struct clk_hw hw;
727751 struct gpio_desc *gpiod;
@@ -738,16 +762,6 @@ struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, · 10 unmodified lines
738762 unsigned long flags);
739763 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
740764
741−/**
742− * struct clk_gpio_mux - gpio controlled clock multiplexer
743− *
744− * @hw: see struct clk_gpio
745− * @gpiod: gpio descriptor to select the parent of this clock multiplexer
746− *
747− * Clock with a gpio control for selecting the parent clock.
748− * Implements .get_parent, .set_parent and .determine_rate
749− */
750−
751765 extern const struct clk_ops clk_gpio_mux_ops;
752766 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
753767 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
@@ -757,17 +771,6 @@ struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, · 3 unmodified lines
757771 unsigned long flags);
758772 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
759773
760−/**
761− * clk_register - allocate a new clock, register it and return an opaque cookie
762− * @dev: device that is registering this clock
763− * @hw: link to hardware-specific clock data
764− *
765− * clk_register is the primary interface for populating the clock tree with new
766− * clock nodes. It returns a pointer to the newly allocated struct clk which
767− * cannot be dereferenced by driver code but may be used in conjuction with the
768− * rest of the clock API. In the event of an error clk_register will return an
769− * error code; drivers must test for an error code after calling clk_register.
770− */
771774 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
772775 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
773776
@@ -993,37 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index, · 219 unmodified lines
993996 }
994997 #endif /* CONFIG_OF */
995998
996−/*
997− * wrap access to peripherals in accessor routines
998− * for improved portability across platforms
999− */
1000−
1001−#if IS_ENABLED(CONFIG_PPC)
1002−
1003−static inline u32 clk_readl(u32 __iomem *reg)
1004−{
1005− return ioread32be(reg);
1006−}
1007−
1008−static inline void clk_writel(u32 val, u32 __iomem *reg)
1009−{
1010− iowrite32be(val, reg);
1011−}
1012−
1013−#else /* platform dependent I/O accessors */
1014−
1015−static inline u32 clk_readl(u32 __iomem *reg)
1016−{
1017− return readl(reg);
1018−}
1019−
1020−static inline void clk_writel(u32 val, u32 __iomem *reg)
1021−{
1022− writel(val, reg);
1023−}
1024−
1025−#endif /* platform dependent I/O accessors */
1026−
1027999 void clk_gate_restore_context(struct clk_hw *hw);
10281000
10291001 #endif /* CONFIG_COMMON_CLK */

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