drm/radeon: add GET_PARAM/INFO support for Z pipes

Needed for occlusion queries on rv530 chips.

Alex Deucher committed 17 years ago

Commit f779b3e1 parent 17782d910 files · +39 −4Browse files

Unified · Split

10 files

@@ -448,6 +448,7 @@ void r300_gpu_init(struct radeon_device *rdev) · 447 unmodified lines
448	448	/* rv350,rv370,rv380 */
449	449	rdev->num_gb_pipes = 1;
450	450	}
	451	+ rdev->num_z_pipes = 1;
451	452	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
452	453	switch (rdev->num_gb_pipes) {
453	454	case 2:
@@ -486,7 +487,8 @@ void r300_gpu_init(struct radeon_device *rdev) · 32 unmodified lines
486	487	printk(KERN_WARNING "Failed to wait MC idle while "
487	488	"programming pipes. Bad things might happen.\n");
488	489	}
489		− DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
	490	+ DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
	491	+ rdev->num_gb_pipes, rdev->num_z_pipes);
490	492	}
491	493
492	494	int r300_ga_reset(struct radeon_device *rdev)

@@ -165,7 +165,18 @@ void r420_pipes_init(struct radeon_device *rdev) · 164 unmodified lines
165	165	printk(KERN_WARNING "Failed to wait GUI idle while "
166	166	"programming pipes. Bad things might happen.\n");
167	167	}
168		− DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
	168	+
	169	+ if (rdev->family == CHIP_RV530) {
	170	+ tmp = RREG32(RV530_GB_PIPE_SELECT2);
	171	+ if ((tmp & 3) == 3)
	172	+ rdev->num_z_pipes = 2;
	173	+ else
	174	+ rdev->num_z_pipes = 1;
	175	+ } else
	176	+ rdev->num_z_pipes = 1;
	177	+
	178	+ DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
	179	+ rdev->num_gb_pipes, rdev->num_z_pipes);
169	180	}
170	181
171	182	void r420_gpu_init(struct radeon_device *rdev)

@@ -177,7 +177,6 @@ void r520_gpu_init(struct radeon_device *rdev) · 176 unmodified lines
177	177	*/
178	178	/* workaround for RV530 */
179	179	if (rdev->family == CHIP_RV530) {
180		− WREG32(0x4124, 1);
181	180	WREG32(0x4128, 0xFF);
182	181	}
183	182	r420_pipes_init(rdev);

@@ -655,6 +655,7 @@ struct radeon_device { · 654 unmodified lines
655	655	int usec_timeout;
656	656	enum radeon_pll_errata pll_errata;
657	657	int num_gb_pipes;
	658	+ int num_z_pipes;
658	659	int disp_priority;
659	660	/* BIOS */
660	661	uint8_t *bios;

@@ -406,6 +406,15 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) · 405 unmodified lines
406	406	{
407	407	uint32_t gb_tile_config, gb_pipe_sel = 0;
408	408
	409	+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
	410	+ uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
	411	+ if ((z_pipe_sel & 3) == 3)
	412	+ dev_priv->num_z_pipes = 2;
	413	+ else
	414	+ dev_priv->num_z_pipes = 1;
	415	+ } else
	416	+ dev_priv->num_z_pipes = 1;
	417	+
409	418	/* RS4xx/RS6xx/R4xx/R5xx */
410	419	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
411	420	gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);

@@ -100,9 +100,10 @@ · 99 unmodified lines
100	100	* 1.28- Add support for VBL on CRTC2
101	101	* 1.29- R500 3D cmd buffer support
102	102	* 1.30- Add support for occlusion queries
	103	+ * 1.31- Add support for num Z pipes from GET_PARAM
103	104	*/
104	105	#define DRIVER_MAJOR 1
105		−#define DRIVER_MINOR 30
	106	+#define DRIVER_MINOR 31
106	107	#define DRIVER_PATCHLEVEL 0
107	108
108	109	/*
@@ -329,6 +330,7 @@ typedef struct drm_radeon_private { · 220 unmodified lines
329	330	resource_size_t fb_aper_offset;
330	331
331	332	int num_gb_pipes;
	333	+ int num_z_pipes;
332	334	int track_flush;
333	335	drm_local_map_t *mmio;
334	336
@@ -689,6 +691,7 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga · 354 unmodified lines
689	691
690	692	/* pipe config regs */
691	693	#define R400_GB_PIPE_SELECT 0x402c
	694	+#define RV530_GB_PIPE_SELECT2 0x4124
692	695	#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
693	696	#define R300_GB_TILE_CONFIG 0x4018
694	697	# define R300_ENABLE_TILING (1 << 0)

@@ -95,6 +95,9 @@ int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 94 unmodified lines
95	95	case RADEON_INFO_NUM_GB_PIPES:
96	96	value = rdev->num_gb_pipes;
97	97	break;
	98	+ case RADEON_INFO_NUM_Z_PIPES:
	99	+ value = rdev->num_z_pipes;
	100	+ break;
98	101	default:
99	102	DRM_DEBUG("Invalid request %d\n", info->request);
100	103	return -EINVAL;

@@ -3081,6 +3081,9 @@ static int radeon_cp_getparam(struct drm_device dev, void data, struct drm_fil · 3080 unmodified lines
3081	3081	case RADEON_PARAM_NUM_GB_PIPES:
3082	3082	value = dev_priv->num_gb_pipes;
3083	3083	break;
	3084	+ case RADEON_PARAM_NUM_Z_PIPES:
	3085	+ value = dev_priv->num_z_pipes;
	3086	+ break;
3084	3087	default:
3085	3088	DRM_DEBUG("Invalid parameter %d\n", param->param);
3086	3089	return -EINVAL;

@@ -709,6 +709,7 @@ typedef struct drm_radeon_indirect { · 708 unmodified lines
709	709	#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
710	710	#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
711	711	#define RADEON_PARAM_DEVICE_ID 16
	712	+#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
712	713
713	714	typedef struct drm_radeon_getparam {
714	715	int param;
@@ -897,6 +898,7 @@ struct drm_radeon_cs { · 182 unmodified lines
897	898
898	899	#define RADEON_INFO_DEVICE_ID 0x00
899	900	#define RADEON_INFO_NUM_GB_PIPES 0x01
	901	+#define RADEON_INFO_NUM_Z_PIPES 0x02
900	902
901	903	struct drm_radeon_info {
902	904	uint32_t request;