drm/msm: Add per-instance submit queues

Currently the behavior of a command stream is provided by the user application during submission and the application is expected to internally maintain the settings for each 'context' or 'rendering queue' and specify the correct ones. This works okay for simple cases but as applications become more complex we will want to set context specific flags and do various permission checks to allow certain contexts to enable additional privileges. Add kernel-side submit queues to be analogous to 'contexts' or 'rendering queues' on the application side. Each file descriptor instance will maintain its own list of queues. Queues cannot be shared between file descriptors. For backwards compatibility context id '0' is defined as a default context specifying no priority and no special flags. This is intended to be the usual configuration for 99% of applications so that a garden variety application can function correctly without creating a queue. Only those applications requiring the specific benefit of different queues need create one.

Jordan Crouse committed 9 years ago

Commit f7de1541 parent 0033e1b8 files · +250 −16Browse files

Unified · Split

8 files

drivers/gpu/drm/msm/Makefile +2 −1
drivers/gpu/drm/msm/msm_drv.c +48 −8
drivers/gpu/drm/msm/msm_drv.h +15 −5
drivers/gpu/drm/msm/msm_gem.h +1 −0
drivers/gpu/drm/msm/msm_gem_submit.c +12 −2
drivers/gpu/drm/msm/msm_gpu.h +15 −0
drivers/gpu/drm/msm/msm_submitqueue.c +135 −0
include/uapi/drm/msm_drm.h +22 −0

drivers/gpu/drm/msm/Makefile+2−1

@@ -57,7 +57,8 @@ msm-y := \ · 56 unmodified lines
57	57	msm_iommu.o \
58	58	msm_perf.o \
59	59	msm_rd.o \
60		− msm_ringbuffer.o
	60	+ msm_ringbuffer.o \
	61	+ msm_submitqueue.o
61	62
62	63	msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
63	64	msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o

drivers/gpu/drm/msm/msm_drv.c+48−8

@@ -29,9 +29,12 @@ · 28 unmodified lines
29	29	* - 1.0.0 - initial interface
30	30	* - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
31	31	* - 1.2.0 - adds explicit fence support for submit ioctl
	32	+ * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
	33	+ * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
	34	+ * MSM_GEM_INFO ioctl.
32	35	*/
33	36	#define MSM_VERSION_MAJOR 1
34		−#define MSM_VERSION_MINOR 2
	37	+#define MSM_VERSION_MINOR 3
35	38	#define MSM_VERSION_PATCHLEVEL 0
36	39
37	40	static void msm_fb_output_poll_changed(struct drm_device *dev)
@@ -504,24 +507,37 @@ static void load_gpu(struct drm_device *dev) · 466 unmodified lines
504	507	mutex_unlock(&init_lock);
505	508	}
506	509
507		−static int msm_open(struct drm_device dev, struct drm_file file)
	510	+static int context_init(struct drm_file *file)
508	511	{
509	512	struct msm_file_private *ctx;
510	513
511		− /* For now, load gpu on open.. to avoid the requirement of having
512		− * firmware in the initrd.
513		− */
514		− load_gpu(dev);
515		−
516	514	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
517	515	if (!ctx)
518	516	return -ENOMEM;
519	517
	518	+ msm_submitqueue_init(ctx);
	519	+
520	520	file->driver_priv = ctx;
521	521
522	522	return 0;
523	523	}
524	524
	525	+static int msm_open(struct drm_device dev, struct drm_file file)
	526	+{
	527	+ /* For now, load gpu on open.. to avoid the requirement of having
	528	+ * firmware in the initrd.
	529	+ */
	530	+ load_gpu(dev);
	531	+
	532	+ return context_init(file);
	533	+}
	534	+
	535	+static void context_close(struct msm_file_private *ctx)
	536	+{
	537	+ msm_submitqueue_close(ctx);
	538	+ kfree(ctx);
	539	+}
	540	+
525	541	static void msm_postclose(struct drm_device dev, struct drm_file file)
526	542	{
527	543	struct msm_drm_private *priv = dev->dev_private;
@@ -532,7 +548,7 @@ static void msm_postclose(struct drm_device dev, struct drm_file file) · 4 unmodified lines
532	548	priv->lastctx = NULL;
533	549	mutex_unlock(&dev->struct_mutex);
534	550
535		− kfree(ctx);
	551	+ context_close(ctx);
536	552	}
537	553
538	554	static void msm_lastclose(struct drm_device *dev)
@@ -777,6 +793,28 @@ unlock: · 238 unmodified lines
777	793	return ret;
778	794	}
779	795
	796	+
	797	+static int msm_ioctl_submitqueue_new(struct drm_device dev, void data,
	798	+ struct drm_file *file)
	799	+{
	800	+ struct drm_msm_submitqueue *args = data;
	801	+
	802	+ if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
	803	+ return -EINVAL;
	804	+
	805	+ return msm_submitqueue_create(file->driver_priv, args->prio,
	806	+ args->flags, &args->id);
	807	+}
	808	+
	809	+
	810	+static int msm_ioctl_submitqueue_close(struct drm_device dev, void data,
	811	+ struct drm_file *file)
	812	+{
	813	+ u32 id = (u32 ) data;
	814	+
	815	+ return msm_submitqueue_remove(file->driver_priv, id);
	816	+}
	817	+
780	818	static const struct drm_ioctl_desc msm_ioctls[] = {
781	819	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH\|DRM_RENDER_ALLOW),
782	820	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH\|DRM_RENDER_ALLOW),
@@ -786,6 +824,8 @@ static const struct drm_ioctl_desc msm_ioctls[] = { · 3 unmodified lines
786	824	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH\|DRM_RENDER_ALLOW),
787	825	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH\|DRM_RENDER_ALLOW),
788	826	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH\|DRM_RENDER_ALLOW),
	827	+ DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH\|DRM_RENDER_ALLOW),
	828	+ DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH\|DRM_RENDER_ALLOW),
789	829	};
790	830
791	831	static const struct vm_operations_struct vm_ops = {

drivers/gpu/drm/msm/msm_drv.h+15−5

@@ -56,11 +56,9 @@ struct msm_gem_address_space; · 55 unmodified lines
56	56	struct msm_gem_vma;
57	57
58	58	struct msm_file_private {
59		− /* currently we don't do anything useful with this.. but when
60		− * per-context address spaces are supported we'd keep track of
61		− * the context's page-tables here.
62		− */
63		− int dummy;
	59	+ rwlock_t queuelock;
	60	+ struct list_head submitqueues;
	61	+ int queueid;
64	62	};
65	63
66	64	enum msm_mdp_plane_property {
@@ -319,6 +317,18 @@ void __iomem msm_ioremap(struct platform_device pdev, const char *name, · 252 unmodified lines
319	317	void msm_writel(u32 data, void __iomem *addr);
320	318	u32 msm_readl(const void __iomem *addr);
321	319
	320	+struct msm_gpu_submitqueue;
	321	+int msm_submitqueue_init(struct msm_file_private *ctx);
	322	+struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
	323	+ u32 id);
	324	+int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio,
	325	+ u32 flags, u32 *id);
	326	+int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
	327	+void msm_submitqueue_close(struct msm_file_private *ctx);
	328	+
	329	+void msm_submitqueue_destroy(struct kref *kref);
	330	+
	331	+
322	332	#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
323	333	#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
324	334

drivers/gpu/drm/msm/msm_gem.h+1−0

@@ -142,6 +142,7 @@ struct msm_gem_submit { · 141 unmodified lines
142	142	struct list_head bo_list;
143	143	struct ww_acquire_ctx ticket;
144	144	struct dma_fence *fence;
	145	+ struct msm_gpu_submitqueue *queue;
145	146	struct pid pid; / submitting process */
146	147	bool valid; /* true if no cmdstream patching needed */
147	148	unsigned int nr_cmds;

drivers/gpu/drm/msm/msm_gem_submit.c+12−2

@@ -31,7 +31,8 @@ · 30 unmodified lines
31	31	#define BO_PINNED 0x2000
32	32
33	33	static struct msm_gem_submit submit_create(struct drm_device dev,
34		− struct msm_gpu *gpu, uint32_t nr_bos, uint32_t nr_cmds)
	34	+ struct msm_gpu gpu, struct msm_gpu_submitqueue queue,
	35	+ uint32_t nr_bos, uint32_t nr_cmds)
35	36	{
36	37	struct msm_gem_submit *submit;
37	38	uint64_t sz = sizeof(submit) + ((u64)nr_bos sizeof(submit->bos[0])) +
@@ -49,6 +50,7 @@ static struct msm_gem_submit submit_create(struct drm_device dev, · 11 unmodified lines
49	50	submit->fence = NULL;
50	51	submit->pid = get_pid(task_pid(current));
51	52	submit->cmd = (void *)&submit->bos[nr_bos];
	53	+ submit->queue = queue;
52	54
53	55	/* initially, until copy_from_user() and bo lookup succeeds: */
54	56	submit->nr_bos = 0;
@@ -66,6 +68,8 @@ void msm_gem_submit_free(struct msm_gem_submit *submit) · 11 unmodified lines
66	68	dma_fence_put(submit->fence);
67	69	list_del(&submit->node);
68	70	put_pid(submit->pid);
	71	+ msm_submitqueue_put(submit->queue);
	72	+
69	73	kfree(submit);
70	74	}
71	75
@@ -405,6 +409,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 333 unmodified lines
405	409	struct msm_gpu *gpu = priv->gpu;
406	410	struct dma_fence *in_fence = NULL;
407	411	struct sync_file *sync_file = NULL;
	412	+ struct msm_gpu_submitqueue *queue;
408	413	int out_fence_fd = -1;
409	414	unsigned i;
410	415	int ret;
@@ -421,6 +426,10 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 10 unmodified lines
421	426	if (MSM_PIPE_FLAGS(args->flags) & ~MSM_SUBMIT_FLAGS)
422	427	return -EINVAL;
423	428
	429	+ queue = msm_submitqueue_get(ctx, args->queueid);
	430	+ if (!queue)
	431	+ return -ENOENT;
	432	+
424	433	if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
425	434	in_fence = sync_file_get_fence(args->fence_fd);
426	435
@@ -451,7 +460,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 24 unmodified lines
451	460	}
452	461	priv->struct_mutex_task = current;
453	462
454		− submit = submit_create(dev, gpu, args->nr_bos, args->nr_cmds);
	463	+ submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds);
455	464	if (!submit) {
456	465	ret = -ENOMEM;
457	466	goto out_unlock;
@@ -535,6 +544,7 @@ int msm_ioctl_gem_submit(struct drm_device dev, void data, · 77 unmodified lines
535	544	submit->nr_cmds = i;
536	545
537	546	submit->fence = msm_fence_alloc(gpu->fctx);
	547	+
538	548	if (IS_ERR(submit->fence)) {
539	549	ret = PTR_ERR(submit->fence);
540	550	submit->fence = NULL;

drivers/gpu/drm/msm/msm_gpu.h+15−0

@@ -150,6 +150,15 @@ struct msm_gpu_perfcntr { · 149 unmodified lines
150	150	const char *name;
151	151	};
152	152
	153	+struct msm_gpu_submitqueue {
	154	+ int id;
	155	+ u32 flags;
	156	+ u32 prio;
	157	+ int faults;
	158	+ struct list_head node;
	159	+ struct kref ref;
	160	+};
	161	+
153	162	static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
154	163	{
155	164	msm_writel(data, gpu->mmio + (reg << 2));
@@ -223,4 +232,10 @@ struct msm_gpu adreno_load_gpu(struct drm_device dev); · 67 unmodified lines
223	232	void __init adreno_register(void);
224	233	void __exit adreno_unregister(void);
225	234
	235	+static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
	236	+{
	237	+ if (queue)
	238	+ kref_put(&queue->ref, msm_submitqueue_destroy);
	239	+}
	240	+
226	241	#endif /* __MSM_GPU_H__ */

drivers/gpu/drm/msm/msm_submitqueue.c+135−0

@@ -0,0 +1,135 @@
	1	+/* Copyright (c) 2017 The Linux Foundation. All rights reserved.
	2	+ *
	3	+ * This program is free software; you can redistribute it and/or modify
	4	+ * it under the terms of the GNU General Public License version 2 and
	5	+ * only version 2 as published by the Free Software Foundation.
	6	+ *
	7	+ * This program is distributed in the hope that it will be useful,
	8	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	+ * GNU General Public License for more details.
	11	+ *
	12	+ */
	13	+
	14	+#include <linux/kref.h>
	15	+#include "msm_gpu.h"
	16	+
	17	+void msm_submitqueue_destroy(struct kref *kref)
	18	+{
	19	+ struct msm_gpu_submitqueue *queue = container_of(kref,
	20	+ struct msm_gpu_submitqueue, ref);
	21	+
	22	+ kfree(queue);
	23	+}
	24	+
	25	+struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
	26	+ u32 id)
	27	+{
	28	+ struct msm_gpu_submitqueue *entry;
	29	+
	30	+ if (!ctx)
	31	+ return NULL;
	32	+
	33	+ read_lock(&ctx->queuelock);
	34	+
	35	+ list_for_each_entry(entry, &ctx->submitqueues, node) {
	36	+ if (entry->id == id) {
	37	+ kref_get(&entry->ref);
	38	+ read_unlock(&ctx->queuelock);
	39	+
	40	+ return entry;
	41	+ }
	42	+ }
	43	+
	44	+ read_unlock(&ctx->queuelock);
	45	+ return NULL;
	46	+}
	47	+
	48	+void msm_submitqueue_close(struct msm_file_private *ctx)
	49	+{
	50	+ struct msm_gpu_submitqueue entry, tmp;
	51	+
	52	+ if (!ctx)
	53	+ return;
	54	+
	55	+ /*
	56	+ * No lock needed in close and there won't
	57	+ * be any more user ioctls coming our way
	58	+ */
	59	+ list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node)
	60	+ msm_submitqueue_put(entry);
	61	+}
	62	+
	63	+int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, u32 flags,
	64	+ u32 *id)
	65	+{
	66	+ struct msm_gpu_submitqueue *queue;
	67	+
	68	+ if (!ctx)
	69	+ return -ENODEV;
	70	+
	71	+ queue = kzalloc(sizeof(*queue), GFP_KERNEL);
	72	+
	73	+ if (!queue)
	74	+ return -ENOMEM;
	75	+
	76	+ kref_init(&queue->ref);
	77	+ queue->flags = flags;
	78	+ queue->prio = prio;
	79	+
	80	+ write_lock(&ctx->queuelock);
	81	+
	82	+ queue->id = ctx->queueid++;
	83	+
	84	+ if (id)
	85	+ *id = queue->id;
	86	+
	87	+ list_add_tail(&queue->node, &ctx->submitqueues);
	88	+
	89	+ write_unlock(&ctx->queuelock);
	90	+
	91	+ return 0;
	92	+}
	93	+
	94	+int msm_submitqueue_init(struct msm_file_private *ctx)
	95	+{
	96	+ if (!ctx)
	97	+ return 0;
	98	+
	99	+ INIT_LIST_HEAD(&ctx->submitqueues);
	100	+
	101	+ rwlock_init(&ctx->queuelock);
	102	+
	103	+ return msm_submitqueue_create(ctx, 2, 0, NULL);
	104	+}
	105	+
	106	+int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id)
	107	+{
	108	+ struct msm_gpu_submitqueue *entry;
	109	+
	110	+ if (!ctx)
	111	+ return 0;
	112	+
	113	+ /*
	114	+ * id 0 is the "default" queue and can't be destroyed
	115	+ * by the user
	116	+ */
	117	+ if (!id)
	118	+ return -ENOENT;
	119	+
	120	+ write_lock(&ctx->queuelock);
	121	+
	122	+ list_for_each_entry(entry, &ctx->submitqueues, node) {
	123	+ if (entry->id == id) {
	124	+ list_del(&entry->node);
	125	+ write_unlock(&ctx->queuelock);
	126	+
	127	+ msm_submitqueue_put(entry);
	128	+ return 0;
	129	+ }
	130	+ }
	131	+
	132	+ write_unlock(&ctx->queuelock);
	133	+ return -ENOENT;
	134	+}
	135	+

include/uapi/drm/msm_drm.h+22−0

@@ -218,6 +218,7 @@ struct drm_msm_gem_submit { · 217 unmodified lines
218	218	__u64 bos; /* in, ptr to array of submit_bo's */
219	219	__u64 cmds; /* in, ptr to array of submit_cmd's */
220	220	__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
	221	+ __u32 queueid; /* in, submitqueue id */
221	222	};
222	223
223	224	/* The normal way to synchronize with the GPU is just to CPU_PREP on
@@ -254,6 +255,20 @@ struct drm_msm_gem_madvise { · 30 unmodified lines
254	255	__u32 retained; /* out, whether backing store still exists */
255	256	};
256	257
	258	+/*
	259	+ * Draw queues allow the user to set specific submission parameter. Command
	260	+ * submissions specify a specific submitqueue to use. ID 0 is reserved for
	261	+ * backwards compatibility as a "default" submitqueue
	262	+ */
	263	+
	264	+#define MSM_SUBMITQUEUE_FLAGS (0)
	265	+
	266	+struct drm_msm_submitqueue {
	267	+ __u32 flags; /* in, MSM_SUBMITQUEUE_x */
	268	+ __u32 prio; /* in, Priority level */
	269	+ __u32 id; /* out, identifier */
	270	+};
	271	+
257	272	#define DRM_MSM_GET_PARAM 0x00
258	273	/* placeholder:
259	274	#define DRM_MSM_SET_PARAM 0x01
@@ -265,6 +280,11 @@ struct drm_msm_gem_madvise { · 5 unmodified lines
265	280	#define DRM_MSM_GEM_SUBMIT 0x06
266	281	#define DRM_MSM_WAIT_FENCE 0x07
267	282	#define DRM_MSM_GEM_MADVISE 0x08
	283	+/* placeholder:
	284	+#define DRM_MSM_GEM_SVM_NEW 0x09
	285	+ */
	286	+#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
	287	+#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
268	288
269	289	#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
270	290	#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
@@ -274,6 +294,8 @@ struct drm_msm_gem_madvise { · 3 unmodified lines
274	294	#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
275	295	#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
276	296	#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
	297	+#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
	298	+#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
277	299
278	300	#if defined(__cplusplus)
279	301	}

drm/msm: Add per-instance submit queues

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