Pull chrome platform updates from Benson Leung: "cros_ec_typec: - Add support for switch control and alternate modes to the Chrome EC Type C port driver - Add basic suspend/resume support sensorhub: - Fix timestamp overflow issue - Fix legacy timestamp spreading on Nami systems cros_ec_proto: - After removing all users of, stop exporting cros_ec_cmd_xfer - Check for missing EC_CMD_HOST_EVENT_GET_WAKE_MASK and ignore wakeups on old ECs misc: - Documentation warning cleanup - Fix double unlock issue in ishtp" * tag 'tag-chrome-platform-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux: (21 commits) platform/chrome: cros_ec_proto: check for missing EC_CMD_HOST_EVENT_GET_WAKE_MASK platform/chrome: cros_ec_proto: ignore unnecessary wakeups on old ECs platform/chrome: cros_ec_sensorhub: Simplify legacy timestamp spreading platform/chrome: cros_ec_proto: Do not export cros_ec_cmd_xfer() platform/chrome: cros_ec_typec: Unregister partner on error platform/chrome: cros_ec_sensorhub: Fix EC timestamp overflow platform/chrome: cros_ec_typec: Add PM support platform/chrome: cros_ec_typec: Use workqueue for port update platform/chrome: cros_ec_typec: Add a dependency on USB_ROLE_SWITCH platform/chrome: cros_ec_ishtp: Fix a double-unlock issue platform/chrome: cros_ec_rpmsg: Document missing struct parameters platform/chrome: cros_ec_spi: Document missing function parameters platform/chrome: cros_ec_typec: Add TBT compat support platform/chrome: cros_ec: Add TBT pd_ctrl fields platform/chrome: cros_ec_typec: Make configure_mux static platform/chrome: cros_ec_typec: Support DP alt mode platform/chrome: cros_ec_typec: Add USB mux control platform/chrome: cros_ec_typec: Register PD CTRL cmd v2 platform/chrome: cros_ec: Update mux state bits platform/chrome: cros_ec_typec: Register Type C switches ...
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| @@ -4917,15 +4917,26 @@ struct ec_response_usb_pd_control_v1 { · 4916 unmodified lines | ||
| 4917 | 4917 | #define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */ |
| 4918 | 4918 | #define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */ |
| 4919 | 4919 | |
| 4920 | +/* Active/Passive Cable */ | |
| 4921 | +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) | |
| 4922 | +/* Optical/Non-optical cable */ | |
| 4923 | +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) | |
| 4924 | +/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ | |
| 4925 | +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) | |
| 4926 | +/* Active Link Uni-Direction */ | |
| 4927 | +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) | |
| 4928 | + | |
| 4920 | 4929 | struct ec_response_usb_pd_control_v2 { |
| 4921 | 4930 | uint8_t enabled; |
| 4922 | 4931 | uint8_t role; |
| 4923 | 4932 | uint8_t polarity; |
| 4924 | 4933 | char state[32]; |
| 4925 | − uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */ | |
| 4926 | − uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ | |
| 4927 | − /* CL:1500994 Current cable type */ | |
| 4928 | − uint8_t reserved_cable_type; | |
| 4934 | + uint8_t cc_state; /* enum pd_cc_states representing cc state */ | |
| 4935 | + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ | |
| 4936 | + uint8_t reserved; /* Reserved for future use */ | |
| 4937 | + uint8_t control_flags; /* USB_PD_CTRL_*flags */ | |
| 4938 | + uint8_t cable_speed; /* TBT_SS_* cable speed */ | |
| 4939 | + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ | |
| 4929 | 4940 | } __ec_align1; |
| 4930 | 4941 | |
| 4931 | 4942 | #define EC_CMD_USB_PD_PORTS 0x0102 |
| @@ -5207,11 +5218,15 @@ struct ec_params_usb_pd_mux_info { · 275 unmodified lines | ||
| 5207 | 5218 | } __ec_align1; |
| 5208 | 5219 | |
| 5209 | 5220 | /* Flags representing mux state */ |
| 5210 | −#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ | |
| 5211 | −#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ | |
| 5212 | −#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ | |
| 5213 | −#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ | |
| 5214 | −#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ | |
| 5221 | +#define USB_PD_MUX_NONE 0 /* Open switch */ | |
| 5222 | +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ | |
| 5223 | +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ | |
| 5224 | +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ | |
| 5225 | +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ | |
| 5226 | +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ | |
| 5227 | +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ | |
| 5228 | +#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ | |
| 5229 | +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ | |
| 5215 | 5230 | |
| 5216 | 5231 | struct ec_response_usb_pd_mux_info { |
| 5217 | 5232 | uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ |
| @@ -216,9 +216,6 @@ int cros_ec_prepare_tx(struct cros_ec_device *ec_dev, · 215 unmodified lines | ||
| 216 | 216 | int cros_ec_check_result(struct cros_ec_device *ec_dev, |
| 217 | 217 | struct cros_ec_command *msg); |
| 218 | 218 | |
| 219 | −int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev, | |
| 220 | − struct cros_ec_command *msg); | |
| 221 | − | |
| 222 | 219 | int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev, |
| 223 | 220 | struct cros_ec_command *msg); |
| 224 | 221 | |