History

Merge branch 'net-hns3-updates-for-next'

Huazhong Tan says: ==================== net: hns3: updates for -next There are several updates relating to the interrupt coalesce for the HNS3 ethernet driver. based on the frame quantity). a fixed value in code. based on the gap time). its new usage. change log: V4 - remove #5~#10 from this series, which needs more discussion. V3 - fix a typo error in #1 reported by Jakub Kicinski. rewrite #9 commit log. remove #11 from this series. V2 - reorder #2 & #3 to fix compiler error. fix some checkpatch warnings in #10 & #11. previous version: V3: https://patchwork.ozlabs.org/project/netdev/cover/1605151998-12633-1-git-send-email-tanhuazhong@huawei.com/ V2: https://patchwork.ozlabs.org/project/netdev/cover/1604892159-19990-1-git-send-email-tanhuazhong@huawei.com/ V1: https://patchwork.ozlabs.org/project/netdev/cover/1604730681-32559-1-git-send-email-tanhuazhong@huawei.com/ ====================

Jakub Kicinski committed 5 years ago

Commit fccf1112 parents 0676a4e de25bcc9 files · +182 −37Browse files

Unified · Split

9 files
  1. drivers/net/ethernet/hisilicon/hns3/hnae3.h +1 −0
  2. drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +1 −0
  3. drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +75 −24
  4. drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +15 −2
  5. drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c +60 −11
  6. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +8 −0
  7. drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +7 −0
  8. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h +8 −0
  9. drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +7 −0
drivers/net/ethernet/hisilicon/hns3/hnae3.h+1−0
@@ -278,6 +278,7 @@ struct hnae3_dev_specs { · 277 unmodified lines
278 u16 rss_ind_tbl_size;278 u16 rss_ind_tbl_size;
279 u16 rss_key_size;279 u16 rss_key_size;
280 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */280 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
281 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
281 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */282 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
282};283};
283 284
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c+1−0
@@ -349,6 +349,7 @@ static void hns3_dbg_dev_specs(struct hnae3_handle *h) · 348 unmodified lines
349 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);349 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
350 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);350 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
351 dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max);351 dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max);
352 dev_info(priv->dev, "MAX INT GL: %u\n", dev_specs->max_int_gl);
352}353}
353 354
354static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,355static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+75−24
@@ -211,8 +211,8 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, · 210 unmodified lines
211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
212 */212 */
213 213
214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
215 !tqp_vector->rx_group.coal.gl_adapt_enable)215 !tqp_vector->rx_group.coal.adapt_enable)
216 /* According to the hardware, the range of rl_reg is216 /* According to the hardware, the range of rl_reg is
217 * 0-59 and the unit is 4.217 * 0-59 and the unit is 4.
218 */218 */
@@ -224,48 +224,99 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, · 5 unmodified lines
224void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,224void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
225 u32 gl_value)225 u32 gl_value)
226{226{
227 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);227 u32 new_val;
228 228
229 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);229 if (tqp_vector->rx_group.coal.unit_1us)
230 new_val = gl_value | HNS3_INT_GL_1US;
231 else
232 new_val = hns3_gl_usec_to_reg(gl_value);
233
234 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
230}235}
231 236
232void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,237void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
233 u32 gl_value)238 u32 gl_value)
234{239{
235 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);240 u32 new_val;
241
242 if (tqp_vector->tx_group.coal.unit_1us)
243 new_val = gl_value | HNS3_INT_GL_1US;
244 else
245 new_val = hns3_gl_usec_to_reg(gl_value);
246
247 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
248}
249
250void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
251 u32 ql_value)
252{
253 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
254}
236 255
237 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);256void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
257 u32 ql_value)
258{
259 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
238}260}
239 261
240static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,262static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
241 struct hns3_nic_priv *priv)263 struct hns3_nic_priv *priv)
242{264{
265 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
266 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
267 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
268
243 /* initialize the configuration for interrupt coalescing.269 /* initialize the configuration for interrupt coalescing.
244 * 1. GL (Interrupt Gap Limiter)270 * 1. GL (Interrupt Gap Limiter)
245 * 2. RL (Interrupt Rate Limiter)271 * 2. RL (Interrupt Rate Limiter)
272 * 3. QL (Interrupt Quantity Limiter)
246 *273 *
247 * Default: enable interrupt coalescing self-adaptive and GL274 * Default: enable interrupt coalescing self-adaptive and GL
248 */275 */
249 tqp_vector->tx_group.coal.gl_adapt_enable = 1;276 tx_coal->adapt_enable = 1;
250 tqp_vector->rx_group.coal.gl_adapt_enable = 1;277 rx_coal->adapt_enable = 1;
278
279 tx_coal->int_gl = HNS3_INT_GL_50K;
280 rx_coal->int_gl = HNS3_INT_GL_50K;
251 281
252 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;282 rx_coal->flow_level = HNS3_FLOW_LOW;
253 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;283 tx_coal->flow_level = HNS3_FLOW_LOW;
284
285 /* device version above V3(include V3), GL can configure 1us
286 * unit, so uses 1us unit.
287 */
288 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
289 tx_coal->unit_1us = 1;
290 rx_coal->unit_1us = 1;
291 }
254 292
255 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;293 if (ae_dev->dev_specs.int_ql_max) {
256 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;294 tx_coal->ql_enable = 1;
295 rx_coal->ql_enable = 1;
296 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
297 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
298 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
299 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
300 }
257}301}
258 302
259static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,303static void
260 struct hns3_nic_priv *priv)304hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
305 struct hns3_nic_priv *priv)
261{306{
307 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
308 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
262 struct hnae3_handle *h = priv->ae_handle;309 struct hnae3_handle *h = priv->ae_handle;
263 310
264 hns3_set_vector_coalesce_tx_gl(tqp_vector,311 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
265 tqp_vector->tx_group.coal.int_gl);312 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
266 hns3_set_vector_coalesce_rx_gl(tqp_vector,
267 tqp_vector->rx_group.coal.int_gl);
268 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);313 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
314
315 if (tx_coal->ql_enable)
316 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
317
318 if (rx_coal->ql_enable)
319 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
269}320}
270 321
271static int hns3_nic_set_real_num_queue(struct net_device *netdev)322static int hns3_nic_set_real_num_queue(struct net_device *netdev)
@@ -3333,14 +3384,14 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) · 3061 unmodified lines
3333 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))3384 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3334 return;3385 return;
3335 3386
3336 if (rx_group->coal.gl_adapt_enable) {3387 if (rx_group->coal.adapt_enable) {
3337 rx_update = hns3_get_new_int_gl(rx_group);3388 rx_update = hns3_get_new_int_gl(rx_group);
3338 if (rx_update)3389 if (rx_update)
3339 hns3_set_vector_coalesce_rx_gl(tqp_vector,3390 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3340 rx_group->coal.int_gl);3391 rx_group->coal.int_gl);
3341 }3392 }
3342 3393
3343 if (tx_group->coal.gl_adapt_enable) {3394 if (tx_group->coal.adapt_enable) {
3344 tx_update = hns3_get_new_int_gl(tx_group);3395 tx_update = hns3_get_new_int_gl(tx_group);
3345 if (tx_update)3396 if (tx_update)
3346 hns3_set_vector_coalesce_tx_gl(tqp_vector,3397 hns3_set_vector_coalesce_tx_gl(tqp_vector,
@@ -3536,7 +3587,7 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) · 189 unmodified lines
3536 3587
3537 for (i = 0; i < priv->vector_num; i++) {3588 for (i = 0; i < priv->vector_num; i++) {
3538 tqp_vector = &priv->tqp_vector[i];3589 tqp_vector = &priv->tqp_vector[i];
3539 hns3_vector_gl_rl_init_hw(tqp_vector, priv);3590 hns3_vector_coalesce_init_hw(tqp_vector, priv);
3540 tqp_vector->num_tqps = 0;3591 tqp_vector->num_tqps = 0;
3541 }3592 }
3542 3593
@@ -3632,7 +3683,7 @@ static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) · 89 unmodified lines
3632 tqp_vector->idx = i;3683 tqp_vector->idx = i;
3633 tqp_vector->mask_addr = vector[i].io_addr;3684 tqp_vector->mask_addr = vector[i].io_addr;
3634 tqp_vector->vector_irq = vector[i].vector;3685 tqp_vector->vector_irq = vector[i].vector;
3635 hns3_vector_gl_rl_init(tqp_vector, priv);3686 hns3_vector_coalesce_init(tqp_vector, priv);
3636 }3687 }
3637 3688
3638out:3689out:
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h+15−2
@@ -181,6 +181,8 @@ enum hns3_nic_state { · 180 unmodified lines
181#define HNS3_VECTOR_GL2_OFFSET 0x300181#define HNS3_VECTOR_GL2_OFFSET 0x300
182#define HNS3_VECTOR_RL_OFFSET 0x900182#define HNS3_VECTOR_RL_OFFSET 0x900
183#define HNS3_VECTOR_RL_EN_B 6183#define HNS3_VECTOR_RL_EN_B 6
184#define HNS3_VECTOR_TX_QL_OFFSET 0xe00
185#define HNS3_VECTOR_RX_QL_OFFSET 0xf00
184 186
185#define HNS3_RING_EN_B 0187#define HNS3_RING_EN_B 0
186 188
@@ -418,18 +420,25 @@ enum hns3_flow_level_range { · 231 unmodified lines
418 HNS3_FLOW_ULTRA = 3,420 HNS3_FLOW_ULTRA = 3,
419};421};
420 422
421#define HNS3_INT_GL_MAX 0x1FE0
422#define HNS3_INT_GL_50K 0x0014423#define HNS3_INT_GL_50K 0x0014
423#define HNS3_INT_GL_20K 0x0032424#define HNS3_INT_GL_20K 0x0032
424#define HNS3_INT_GL_18K 0x0036425#define HNS3_INT_GL_18K 0x0036
425#define HNS3_INT_GL_8K 0x007C426#define HNS3_INT_GL_8K 0x007C
426 427
428#define HNS3_INT_GL_1US BIT(31)
429
427#define HNS3_INT_RL_MAX 0x00EC430#define HNS3_INT_RL_MAX 0x00EC
428#define HNS3_INT_RL_ENABLE_MASK 0x40431#define HNS3_INT_RL_ENABLE_MASK 0x40
429 432
433#define HNS3_INT_QL_DEFAULT_CFG 0x20
434
430struct hns3_enet_coalesce {435struct hns3_enet_coalesce {
431 u16 int_gl;436 u16 int_gl;
432 u8 gl_adapt_enable;437 u16 int_ql;
438 u16 int_ql_max;
439 u8 adapt_enable:1;
440 u8 ql_enable:1;
441 u8 unit_1us:1;
433 enum hns3_flow_level_range flow_level;442 enum hns3_flow_level_range flow_level;
434};443};
435 444
@@ -595,6 +604,10 @@ void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, · 159 unmodified lines
595 u32 gl_value);604 u32 gl_value);
596void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,605void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
597 u32 rl_value);606 u32 rl_value);
607void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
608 u32 ql_value);
609void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
610 u32 ql_value);
598 611
599void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);612void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
600void hns3_request_update_promisc_mode(struct hnae3_handle *handle);613void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c+60−11
@@ -1105,9 +1105,9 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue, · 1104 unmodified lines
1105 rx_vector = priv->ring[queue_num + queue].tqp_vector;1105 rx_vector = priv->ring[queue_num + queue].tqp_vector;
1106 1106
1107 cmd->use_adaptive_tx_coalesce =1107 cmd->use_adaptive_tx_coalesce =
1108 tx_vector->tx_group.coal.gl_adapt_enable;1108 tx_vector->tx_group.coal.adapt_enable;
1109 cmd->use_adaptive_rx_coalesce =1109 cmd->use_adaptive_rx_coalesce =
1110 rx_vector->rx_group.coal.gl_adapt_enable;1110 rx_vector->rx_group.coal.adapt_enable;
1111 1111
1112 cmd->tx_coalesce_usecs = tx_vector->tx_group.coal.int_gl;1112 cmd->tx_coalesce_usecs = tx_vector->tx_group.coal.int_gl;
1113 cmd->rx_coalesce_usecs = rx_vector->rx_group.coal.int_gl;1113 cmd->rx_coalesce_usecs = rx_vector->rx_group.coal.int_gl;
@@ -1115,6 +1115,9 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue, · 1 unmodified line
1115 cmd->tx_coalesce_usecs_high = h->kinfo.int_rl_setting;1115 cmd->tx_coalesce_usecs_high = h->kinfo.int_rl_setting;
1116 cmd->rx_coalesce_usecs_high = h->kinfo.int_rl_setting;1116 cmd->rx_coalesce_usecs_high = h->kinfo.int_rl_setting;
1117 1117
1118 cmd->tx_max_coalesced_frames = tx_vector->tx_group.coal.int_ql;
1119 cmd->rx_max_coalesced_frames = rx_vector->rx_group.coal.int_ql;
1120
1118 return 0;1121 return 0;
1119}1122}
1120 1123
@@ -1127,22 +1130,30 @@ static int hns3_get_coalesce(struct net_device *netdev, · 6 unmodified lines
1127static int hns3_check_gl_coalesce_para(struct net_device *netdev,1130static int hns3_check_gl_coalesce_para(struct net_device *netdev,
1128 struct ethtool_coalesce *cmd)1131 struct ethtool_coalesce *cmd)
1129{1132{
1133 struct hnae3_handle *handle = hns3_get_handle(netdev);
1134 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1130 u32 rx_gl, tx_gl;1135 u32 rx_gl, tx_gl;
1131 1136
1132 if (cmd->rx_coalesce_usecs > HNS3_INT_GL_MAX) {1137 if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {
1133 netdev_err(netdev,1138 netdev_err(netdev,
1134 "Invalid rx-usecs value, rx-usecs range is 0-%d\n",1139 "invalid rx-usecs value, rx-usecs range is 0-%u\n",
1135 HNS3_INT_GL_MAX);1140 ae_dev->dev_specs.max_int_gl);
1136 return -EINVAL;1141 return -EINVAL;
1137 }1142 }
1138 1143
1139 if (cmd->tx_coalesce_usecs > HNS3_INT_GL_MAX) {1144 if (cmd->tx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {
1140 netdev_err(netdev,1145 netdev_err(netdev,
1141 "Invalid tx-usecs value, tx-usecs range is 0-%d\n",1146 "invalid tx-usecs value, tx-usecs range is 0-%u\n",
1142 HNS3_INT_GL_MAX);1147 ae_dev->dev_specs.max_int_gl);
1143 return -EINVAL;1148 return -EINVAL;
1144 }1149 }
1145 1150
1151 /* device version above V3(include V3), GL uses 1us unit,
1152 * so the round down is not needed.
1153 */
1154 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1155 return 0;
1156
1146 rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs);1157 rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs);
1147 if (rx_gl != cmd->rx_coalesce_usecs) {1158 if (rx_gl != cmd->rx_coalesce_usecs) {
1148 netdev_info(netdev,1159 netdev_info(netdev,
@@ -1188,6 +1199,29 @@ static int hns3_check_rl_coalesce_para(struct net_device *netdev, · 39 unmodified lines
1188 return 0;1199 return 0;
1189}1200}
1190 1201
1202static int hns3_check_ql_coalesce_param(struct net_device *netdev,
1203 struct ethtool_coalesce *cmd)
1204{
1205 struct hnae3_handle *handle = hns3_get_handle(netdev);
1206 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1207
1208 if ((cmd->tx_max_coalesced_frames || cmd->rx_max_coalesced_frames) &&
1209 !ae_dev->dev_specs.int_ql_max) {
1210 netdev_err(netdev, "coalesced frames is not supported\n");
1211 return -EOPNOTSUPP;
1212 }
1213
1214 if (cmd->tx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max ||
1215 cmd->rx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max) {
1216 netdev_err(netdev,
1217 "invalid coalesced_frames value, range is 0-%u\n",
1218 ae_dev->dev_specs.int_ql_max);
1219 return -ERANGE;
1220 }
1221
1222 return 0;
1223}
1224
1191static int hns3_check_coalesce_para(struct net_device *netdev,1225static int hns3_check_coalesce_para(struct net_device *netdev,
1192 struct ethtool_coalesce *cmd)1226 struct ethtool_coalesce *cmd)
1193{1227{
@@ -1207,6 +1241,10 @@ static int hns3_check_coalesce_para(struct net_device *netdev, · 13 unmodified lines
1207 return ret;1241 return ret;
1208 }1242 }
1209 1243
1244 ret = hns3_check_ql_coalesce_param(netdev, cmd);
1245 if (ret)
1246 return ret;
1247
1210 if (cmd->use_adaptive_tx_coalesce == 1 ||1248 if (cmd->use_adaptive_tx_coalesce == 1 ||
1211 cmd->use_adaptive_rx_coalesce == 1) {1249 cmd->use_adaptive_rx_coalesce == 1) {
1212 netdev_info(netdev,1250 netdev_info(netdev,
@@ -1230,14 +1268,17 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev, · 17 unmodified lines
1230 tx_vector = priv->ring[queue].tqp_vector;1268 tx_vector = priv->ring[queue].tqp_vector;
1231 rx_vector = priv->ring[queue_num + queue].tqp_vector;1269 rx_vector = priv->ring[queue_num + queue].tqp_vector;
1232 1270
1233 tx_vector->tx_group.coal.gl_adapt_enable =1271 tx_vector->tx_group.coal.adapt_enable =
1234 cmd->use_adaptive_tx_coalesce;1272 cmd->use_adaptive_tx_coalesce;
1235 rx_vector->rx_group.coal.gl_adapt_enable =1273 rx_vector->rx_group.coal.adapt_enable =
1236 cmd->use_adaptive_rx_coalesce;1274 cmd->use_adaptive_rx_coalesce;
1237 1275
1238 tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;1276 tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;
1239 rx_vector->rx_group.coal.int_gl = cmd->rx_coalesce_usecs;1277 rx_vector->rx_group.coal.int_gl = cmd->rx_coalesce_usecs;
1240 1278
1279 tx_vector->tx_group.coal.int_ql = cmd->tx_max_coalesced_frames;
1280 rx_vector->rx_group.coal.int_ql = cmd->rx_max_coalesced_frames;
1281
1241 hns3_set_vector_coalesce_tx_gl(tx_vector,1282 hns3_set_vector_coalesce_tx_gl(tx_vector,
1242 tx_vector->tx_group.coal.int_gl);1283 tx_vector->tx_group.coal.int_gl);
1243 hns3_set_vector_coalesce_rx_gl(rx_vector,1284 hns3_set_vector_coalesce_rx_gl(rx_vector,
@@ -1245,6 +1286,13 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev, · 1 unmodified line
1245 1286
1246 hns3_set_vector_coalesce_rl(tx_vector, h->kinfo.int_rl_setting);1287 hns3_set_vector_coalesce_rl(tx_vector, h->kinfo.int_rl_setting);
1247 hns3_set_vector_coalesce_rl(rx_vector, h->kinfo.int_rl_setting);1288 hns3_set_vector_coalesce_rl(rx_vector, h->kinfo.int_rl_setting);
1289
1290 if (tx_vector->tx_group.coal.ql_enable)
1291 hns3_set_vector_coalesce_tx_ql(tx_vector,
1292 tx_vector->tx_group.coal.int_ql);
1293 if (rx_vector->rx_group.coal.ql_enable)
1294 hns3_set_vector_coalesce_rx_ql(rx_vector,
1295 rx_vector->rx_group.coal.int_ql);
1248}1296}
1249 1297
1250static int hns3_set_coalesce(struct net_device *netdev,1298static int hns3_set_coalesce(struct net_device *netdev,
@@ -1471,7 +1519,8 @@ static int hns3_get_module_eeprom(struct net_device *netdev, · 220 unmodified lines
1471#define HNS3_ETHTOOL_COALESCE (ETHTOOL_COALESCE_USECS | \1519#define HNS3_ETHTOOL_COALESCE (ETHTOOL_COALESCE_USECS | \
1472 ETHTOOL_COALESCE_USE_ADAPTIVE | \1520 ETHTOOL_COALESCE_USE_ADAPTIVE | \
1473 ETHTOOL_COALESCE_RX_USECS_HIGH | \1521 ETHTOOL_COALESCE_RX_USECS_HIGH | \
1474 ETHTOOL_COALESCE_TX_USECS_HIGH)1522 ETHTOOL_COALESCE_TX_USECS_HIGH | \
1523 ETHTOOL_COALESCE_MAX_FRAMES)
1475 1524
1476static const struct ethtool_ops hns3vf_ethtool_ops = {1525static const struct ethtool_ops hns3vf_ethtool_ops = {
1477 .supported_coalesce_params = HNS3_ETHTOOL_COALESCE,1526 .supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h+8−0
@@ -1103,6 +1103,14 @@ struct hclge_dev_specs_0_cmd { · 1102 unmodified lines
1103 __le32 max_tm_rate;1103 __le32 max_tm_rate;
1104};1104};
1105 1105
1106#define HCLGE_DEF_MAX_INT_GL 0x1FE0U
1107
1108struct hclge_dev_specs_1_cmd {
1109 __le32 rsv0;
1110 __le16 max_int_gl;
1111 u8 rsv1[18];
1112};
1113
1106int hclge_cmd_init(struct hclge_dev *hdev);1114int hclge_cmd_init(struct hclge_dev *hdev);
1107static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)1115static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1108{1116{
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+7−0
@@ -1366,6 +1366,7 @@ static void hclge_set_default_dev_specs(struct hclge_dev *hdev) · 1365 unmodified lines
1366 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;1366 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1367 ae_dev->dev_specs.rss_key_size = HCLGE_RSS_KEY_SIZE;1367 ae_dev->dev_specs.rss_key_size = HCLGE_RSS_KEY_SIZE;
1368 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;1368 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1369 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1369}1370}
1370 1371
1371static void hclge_parse_dev_specs(struct hclge_dev *hdev,1372static void hclge_parse_dev_specs(struct hclge_dev *hdev,
@@ -1373,14 +1374,18 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev, · 1 unmodified line
1373{1374{
1374 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);1375 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1375 struct hclge_dev_specs_0_cmd *req0;1376 struct hclge_dev_specs_0_cmd *req0;
1377 struct hclge_dev_specs_1_cmd *req1;
1376 1378
1377 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;1379 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1380 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1378 1381
1379 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;1382 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1380 ae_dev->dev_specs.rss_ind_tbl_size =1383 ae_dev->dev_specs.rss_ind_tbl_size =
1381 le16_to_cpu(req0->rss_ind_tbl_size);1384 le16_to_cpu(req0->rss_ind_tbl_size);
1385 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1382 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);1386 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1383 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);1387 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1388 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1384}1389}
1385 1390
1386static void hclge_check_dev_specs(struct hclge_dev *hdev)1391static void hclge_check_dev_specs(struct hclge_dev *hdev)
@@ -1395,6 +1400,8 @@ static void hclge_check_dev_specs(struct hclge_dev *hdev) · 8 unmodified lines
1395 dev_specs->rss_key_size = HCLGE_RSS_KEY_SIZE;1400 dev_specs->rss_key_size = HCLGE_RSS_KEY_SIZE;
1396 if (!dev_specs->max_tm_rate)1401 if (!dev_specs->max_tm_rate)
1397 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;1402 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1403 if (!dev_specs->max_int_gl)
1404 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1398}1405}
1399 1406
1400static int hclge_query_dev_specs(struct hclge_dev *hdev)1407static int hclge_query_dev_specs(struct hclge_dev *hdev)
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h+8−0
@@ -285,6 +285,14 @@ struct hclgevf_dev_specs_0_cmd { · 284 unmodified lines
285 u8 rsv1[5];285 u8 rsv1[5];
286};286};
287 287
288#define HCLGEVF_DEF_MAX_INT_GL 0x1FE0U
289
290struct hclgevf_dev_specs_1_cmd {
291 __le32 rsv0;
292 __le16 max_int_gl;
293 u8 rsv1[18];
294};
295
288static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)296static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
289{297{
290 writel(value, base + reg);298 writel(value, base + reg);
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+7−0
@@ -2991,6 +2991,7 @@ static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) · 2990 unmodified lines
2991 HCLGEVF_MAX_NON_TSO_BD_NUM;2991 HCLGEVF_MAX_NON_TSO_BD_NUM;
2992 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;2992 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2993 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;2993 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
2994 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
2994}2995}
2995 2996
2996static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,2997static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
@@ -2998,13 +2999,17 @@ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, · 1 unmodified line
2998{2999{
2999 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);3000 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3000 struct hclgevf_dev_specs_0_cmd *req0;3001 struct hclgevf_dev_specs_0_cmd *req0;
3002 struct hclgevf_dev_specs_1_cmd *req1;
3001 3003
3002 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;3004 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3005 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
3003 3006
3004 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;3007 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3005 ae_dev->dev_specs.rss_ind_tbl_size =3008 ae_dev->dev_specs.rss_ind_tbl_size =
3006 le16_to_cpu(req0->rss_ind_tbl_size);3009 le16_to_cpu(req0->rss_ind_tbl_size);
3010 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
3007 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);3011 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3012 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
3008}3013}
3009 3014
3010static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)3015static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
@@ -3017,6 +3022,8 @@ static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) · 6 unmodified lines
3017 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;3022 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3018 if (!dev_specs->rss_key_size)3023 if (!dev_specs->rss_key_size)
3019 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;3024 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3025 if (!dev_specs->max_int_gl)
3026 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3020}3027}
3021 3028
3022static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)3029static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)