History

Merge tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access

Linus Torvalds committed 7 years ago

Commit fde7dc62 parents a1240cf 25777e510 files · +134 −58Browse files

Unified · Split

10 files
  1. Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +50 −9
  2. drivers/mailbox/Kconfig +1 −1
  3. drivers/mailbox/arm_mhu.c +4 −7
  4. drivers/mailbox/bcm-flexrm-mailbox.c +2 −4
  5. drivers/mailbox/imx-mailbox.c +2 −2
  6. drivers/mailbox/mailbox.c +4 −2
  7. drivers/mailbox/omap-mailbox.c +26 −17
  8. drivers/mailbox/stm32-ipcc.c +27 −10
  9. drivers/mailbox/tegra-hsp.c +15 −5
  10. include/linux/omap-mailbox.h +3 −1
Documentation/devicetree/bindings/mailbox/omap-mailbox.txt+50−9
@@ -1,4 +1,4 @@
1−OMAP2+ Mailbox Driver
1+OMAP2+ and K3 Mailbox
22 =====================
33
44 The OMAP mailbox hardware facilitates communication between different processors
@@ -7,7 +7,7 @@ various processor subsystems and is connected on an interconnect bus. The · 2 unmodified lines
77 communication is achieved through a set of registers for message storage and
88 interrupt configuration registers.
99
10−Each mailbox IP block has a certain number of h/w fifo queues and output
10+Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
1111 interrupt lines. An output interrupt line is routed to an interrupt controller
1212 within a processor subsystem, and there can be more than one line going to a
1313 specific processor's interrupt controller. The interrupt line connections are
@@ -23,12 +23,16 @@ All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP · 9 unmodified lines
2323 instance. DRA7xx has multiple instances with different number of h/w fifo queues
2424 and interrupt lines between different instances. The interrupt lines can also be
2525 routed to different processor sub-systems on DRA7xx as they are routed through
26−the Crossbar, a kind of interrupt router/multiplexer.
26+the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
27+SoCs has each of these instances form a cluster and combine multiple clusters
28+into a single IP block present within the Main NavSS. The interrupt lines from
29+all these clusters are multiplexed and routed to different processor subsystems
30+over a limited number of common interrupt output lines of an Interrupt Router.
2731
2832 Mailbox Device Node:
2933 ====================
30−A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
31−The sub-mailboxes are represented as child nodes of this parent node.
34+A Mailbox device node is used to represent a Mailbox IP instance/cluster within
35+a SoC. The sub-mailboxes are represented as child nodes of this parent node.
3236
3337 Required properties:
3438 --------------------
@@ -37,12 +41,12 @@ Required properties: · 2 unmodified lines
3741 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
3842 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
3943 AM43xx and DRA7xx SoCs
44+ "ti,am654-mailbox" for K3 AM65x and J721E SoCs
4045 - reg: Contains the mailbox register address range (base
4146 address and length)
4247 - interrupts: Contains the interrupt information for the mailbox
4348 device. The format is dependent on which interrupt
44− controller the OMAP device uses
45−- ti,hwmods: Name of the hwmod associated with the mailbox
49+ controller the Mailbox device uses
4650 - #mbox-cells: Common mailbox binding property to identify the number
4751 of cells required for the mailbox specifier. Should be
4852 1
@@ -50,6 +54,23 @@ Required properties: · 1 unmodified line
5054 device can interrupt
5155 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
5256
57+SoC-specific Required properties:
58+---------------------------------
59+The following are mandatory properties for the OMAP architecture based SoCs
60+only:
61+- ti,hwmods: Name of the hwmod associated with the mailbox. This
62+ should be defined in the mailbox node only if the node
63+ is not defined as a child node of a corresponding sysc
64+ interconnect node.
65+
66+The following are mandatory properties for the K3 AM65x and J721E SoCs only:
67+- interrupt-parent: Should contain a phandle to the TI-SCI interrupt
68+ controller node that is used to dynamically program
69+ the interrupt routes between the IP and the main GIC
70+ controllers. See the following binding for additional
71+ details,
72+ Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
73+
5374 Child Nodes:
5475 ============
5576 A child node is used for representing the actual sub-mailbox device that is
@@ -98,7 +119,7 @@ to be used by the client user. · 42 unmodified lines
98119 Example:
99120 --------
100121
101−/* OMAP4 */
122+1. /* OMAP4 */
102123 mailbox: mailbox@4a0f4000 {
103124 compatible = "ti,omap4-mailbox";
104125 reg = <0x4a0f4000 0x200>;
@@ -123,7 +144,7 @@ dsp { · 18 unmodified lines
123144 ...
124145 };
125146
126−/* AM33xx */
147+2. /* AM33xx */
127148 mailbox: mailbox@480c8000 {
128149 compatible = "ti,omap4-mailbox";
129150 reg = <0x480C8000 0x200>;
@@ -137,3 +158,23 @@ mailbox: mailbox@480c8000 { · 7 unmodified lines
137158 ti,mbox-rx = <0 0 3>;
138159 };
139160 };
161+
162+3. /* AM65x */
163+&cbass_main {
164+ cbass_main_navss: interconnect0 {
165+ mailbox0_cluster0: mailbox@31f80000 {
166+ compatible = "ti,am654-mailbox";
167+ reg = <0x00 0x31f80000 0x00 0x200>;
168+ #mbox-cells = <1>;
169+ ti,mbox-num-users = <4>;
170+ ti,mbox-num-fifos = <16>;
171+ interrupt-parent = <&intr_main_navss>;
172+ interrupts = <164 0>;
173+
174+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
175+ ti,mbox-tx = <1 0 0>;
176+ ti,mbox-rx = <0 0 0>;
177+ };
178+ };
179+ };
180+};
drivers/mailbox/Kconfig+1−1
@@ -54,7 +54,7 @@ config ARMADA_37XX_RWTM_MBOX · 53 unmodified lines
5454
5555 config OMAP2PLUS_MBOX
5656 tristate "OMAP2+ Mailbox framework support"
57− depends on ARCH_OMAP2PLUS
57+ depends on ARCH_OMAP2PLUS || ARCH_K3
5858 help
5959 Mailbox implementation for OMAP family chips with hardware for
6060 interprocessor communication involving DSP, IVA1.0 and IVA2 in
drivers/mailbox/arm_mhu.c+4−7
@@ -5,16 +5,13 @@ · 4 unmodified lines
55 * Author: Jassi Brar <jaswinder.singh@linaro.org>
66 */
77
8−#include <linux/interrupt.h>
9−#include <linux/spinlock.h>
10−#include <linux/mutex.h>
11−#include <linux/delay.h>
12−#include <linux/slab.h>
8+#include <linux/amba/bus.h>
9+#include <linux/device.h>
1310 #include <linux/err.h>
11+#include <linux/interrupt.h>
1412 #include <linux/io.h>
15−#include <linux/module.h>
16−#include <linux/amba/bus.h>
1713 #include <linux/mailbox_controller.h>
14+#include <linux/module.h>
1815
1916 #define INTR_STAT_OFS 0x0
2017 #define INTR_SET_OFS 0x8
drivers/mailbox/bcm-flexrm-mailbox.c+2−4
@@ -1163,8 +1163,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring) · 1162 unmodified lines
11631163
11641164 static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
11651165 {
1166− struct platform_device *pdev = to_platform_device(file->private);
1167− struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
1166+ struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
11681167
11691168 /* Write config in file */
11701169 flexrm_write_config_in_seqfile(mbox, file);
@@ -1174,8 +1173,7 @@ static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset) · 3 unmodified lines
11741173
11751174 static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
11761175 {
1177− struct platform_device *pdev = to_platform_device(file->private);
1178− struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
1176+ struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
11791177
11801178 /* Write stats in file */
11811179 flexrm_write_stats_in_seqfile(mbox, file);
drivers/mailbox/imx-mailbox.c+2−2
@@ -217,8 +217,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) · 216 unmodified lines
217217 if (cp->type == IMX_MU_TYPE_TXDB)
218218 tasklet_kill(&cp->txdb_tasklet);
219219
220− imx_mu_xcr_rmw(priv, 0,
221− IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
220+ imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
221+ IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
222222
223223 free_irq(priv->irq, chan);
224224 }
drivers/mailbox/mailbox.c+4−2
@@ -418,11 +418,13 @@ struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl, · 417 unmodified lines
418418
419419 of_property_for_each_string(np, "mbox-names", prop, mbox_name) {
420420 if (!strncmp(name, mbox_name, strlen(name)))
421− break;
421+ return mbox_request_channel(cl, index);
422422 index++;
423423 }
424424
425− return mbox_request_channel(cl, index);
425+ dev_err(cl->dev, "%s() could not locate channel named \"%s\"\n",
426+ __func__, name);
427+ return ERR_PTR(-EINVAL);
426428 }
427429 EXPORT_SYMBOL_GPL(mbox_request_channel_byname);
428430
drivers/mailbox/omap-mailbox.c+26−17
@@ -3,7 +3,7 @@ · 2 unmodified lines
33 * OMAP mailbox driver
44 *
55 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6− * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
6+ * Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com
77 *
88 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
99 * Suman Anna <s-anna@ti.com>
@@ -141,14 +141,14 @@ void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) · 131 unmodified lines
141141 }
142142
143143 /* Mailbox FIFO handle functions */
144−static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
144+static u32 mbox_fifo_read(struct omap_mbox *mbox)
145145 {
146146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
147147
148− return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);
148+ return mbox_read_reg(mbox->parent, fifo->msg);
149149 }
150150
151−static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
151+static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
152152 {
153153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
154154
@@ -256,14 +256,16 @@ static void mbox_rx_work(struct work_struct *work) · 101 unmodified lines
256256 {
257257 struct omap_mbox_queue *mq =
258258 container_of(work, struct omap_mbox_queue, work);
259− mbox_msg_t msg;
259+ mbox_msg_t data;
260+ u32 msg;
260261 int len;
261262
262263 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
263264 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
264265 WARN_ON(len != sizeof(msg));
266+ data = msg;
265267
266− mbox_chan_received_data(mq->mbox->chan, (void *)msg);
268+ mbox_chan_received_data(mq->mbox->chan, (void *)data);
267269 spin_lock_irq(&mq->lock);
268270 if (mq->full) {
269271 mq->full = false;
@@ -286,7 +288,7 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox) · 16 unmodified lines
286288 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
287289 {
288290 struct omap_mbox_queue *mq = mbox->rxq;
289− mbox_msg_t msg;
291+ u32 msg;
290292 int len;
291293
292294 while (!mbox_fifo_empty(mbox)) {
@@ -540,13 +542,13 @@ static void omap_mbox_chan_shutdown(struct mbox_chan *chan) · 247 unmodified lines
540542 mutex_unlock(&mdev->cfg_lock);
541543 }
542544
543−static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
545+static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
544546 {
545547 int ret = -EBUSY;
546548
547549 if (!mbox_fifo_full(mbox)) {
548550 _omap_mbox_enable_irq(mbox, IRQ_RX);
549− mbox_fifo_write(mbox, (mbox_msg_t)data);
551+ mbox_fifo_write(mbox, msg);
550552 ret = 0;
551553 _omap_mbox_disable_irq(mbox, IRQ_RX);
552554
@@ -558,12 +560,12 @@ static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) · 5 unmodified lines
558560 return ret;
559561 }
560562
561−static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
563+static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
562564 {
563565 int ret = -EBUSY;
564566
565567 if (!mbox_fifo_full(mbox)) {
566− mbox_fifo_write(mbox, (mbox_msg_t)data);
568+ mbox_fifo_write(mbox, msg);
567569 ret = 0;
568570 }
569571
@@ -576,14 +578,15 @@ static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) · 6 unmodified lines
576578 {
577579 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
578580 int ret;
581+ u32 msg = omap_mbox_message(data);
579582
580583 if (!mbox)
581584 return -EINVAL;
582585
583586 if (mbox->send_no_irq)
584− ret = omap_mbox_chan_send_noirq(mbox, data);
587+ ret = omap_mbox_chan_send_noirq(mbox, msg);
585588 else
586− ret = omap_mbox_chan_send(mbox, data);
589+ ret = omap_mbox_chan_send(mbox, msg);
587590
588591 return ret;
589592 }
@@ -656,6 +659,10 @@ static const struct of_device_id omap_mailbox_of_match[] = { · 66 unmodified lines
656659 .compatible = "ti,omap4-mailbox",
657660 .data = &omap4_data,
658661 },
662+ {
663+ .compatible = "ti,am654-mailbox",
664+ .data = &omap4_data,
665+ },
659666 {
660667 /* end */
661668 },
@@ -830,7 +837,10 @@ static int omap_mbox_probe(struct platform_device *pdev) · 168 unmodified lines
830837 mdev->intr_type = intr_type;
831838 mdev->mboxes = list;
832839
833− /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
840+ /*
841+ * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
842+ * IRQ and is needed to run the Tx state machine
843+ */
834844 mdev->controller.txdone_irq = true;
835845 mdev->controller.dev = mdev->dev;
836846 mdev->controller.ops = &omap_mbox_chan_ops;
@@ -899,9 +909,8 @@ static int __init omap_mbox_init(void) · 62 unmodified lines
899909 return err;
900910
901911 /* kfifo size sanity check: alignment and minimal size */
902− mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
903− mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
904− sizeof(mbox_msg_t));
912+ mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
913+ mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
905914
906915 err = platform_driver_register(&omap_mbox_driver);
907916 if (err)
drivers/mailbox/stm32-ipcc.c+27−10
@@ -50,6 +50,7 @@ struct stm32_ipcc { · 49 unmodified lines
5050 void __iomem *reg_base;
5151 void __iomem *reg_proc;
5252 struct clk *clk;
53+ spinlock_t lock; /* protect access to IPCC registers */
5354 int irqs[IPCC_IRQ_NUM];
5455 int wkp;
5556 u32 proc_id;
@@ -58,14 +59,24 @@ struct stm32_ipcc { · 2 unmodified lines
5859 u32 xmr;
5960 };
6061
61−static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
62+static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg,
63+ u32 mask)
6264 {
65+ unsigned long flags;
66+
67+ spin_lock_irqsave(lock, flags);
6368 writel_relaxed(readl_relaxed(reg) | mask, reg);
69+ spin_unlock_irqrestore(lock, flags);
6470 }
6571
66−static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
72+static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg,
73+ u32 mask)
6774 {
75+ unsigned long flags;
76+
77+ spin_lock_irqsave(lock, flags);
6878 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
79+ spin_unlock_irqrestore(lock, flags);
6980 }
7081
7182 static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
@@ -92,7 +103,7 @@ static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data) · 20 unmodified lines
92103
93104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
94105
95− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
106+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
96107 RX_BIT_CHAN(chan));
97108
98109 ret = IRQ_HANDLED;
@@ -121,7 +132,7 @@ static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data) · 22 unmodified lines
121132 dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
122133
123134 /* mask 'tx channel free' interrupt */
124− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
135+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
125136 TX_BIT_CHAN(chan));
126137
127138 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
@@ -141,10 +152,12 @@ static int stm32_ipcc_send_data(struct mbox_chan *link, void *data) · 13 unmodified lines
141152 dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
142153
143154 /* set channel n occupied */
144− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
155+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
156+ TX_BIT_CHAN(chan));
145157
146158 /* unmask 'tx channel free' interrupt */
147− stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
159+ stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
160+ TX_BIT_CHAN(chan));
148161
149162 return 0;
150163 }
@@ -163,7 +176,8 @@ static int stm32_ipcc_startup(struct mbox_chan *link) · 12 unmodified lines
163176 }
164177
165178 /* unmask 'rx channel occupied' interrupt */
166− stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
179+ stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
180+ RX_BIT_CHAN(chan));
167181
168182 return 0;
169183 }
@@ -175,7 +189,7 @@ static void stm32_ipcc_shutdown(struct mbox_chan *link) · 5 unmodified lines
175189 controller);
176190
177191 /* mask rx/tx interrupt */
178− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
192+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
179193 RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
180194
181195 clk_disable_unprepare(ipcc->clk);
@@ -208,6 +222,8 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 26 unmodified lines
208222 if (!ipcc)
209223 return -ENOMEM;
210224
225+ spin_lock_init(&ipcc->lock);
226+
211227 /* proc_id */
212228 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
213229 dev_err(dev, "Missing st,proc-id\n");
@@ -259,9 +275,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev) · 45 unmodified lines
259275 }
260276
261277 /* mask and enable rx/tx irq */
262− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
278+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
263279 RX_BIT_MASK | TX_BIT_MASK);
264− stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);
280+ stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
281+ XCR_RXOIE | XCR_TXOIE);
265282
266283 /* wakeup */
267284 if (of_property_read_bool(np, "wakeup-source")) {
drivers/mailbox/tegra-hsp.c+15−5
@@ -775,18 +775,28 @@ static int __maybe_unused tegra_hsp_resume(struct device *dev) · 774 unmodified lines
775775 {
776776 struct tegra_hsp *hsp = dev_get_drvdata(dev);
777777 unsigned int i;
778+ struct tegra_hsp_doorbell *db;
778779
779− for (i = 0; i < hsp->num_sm; i++) {
780− struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
780+ list_for_each_entry(db, &hsp->doorbells, list) {
781+ if (db && db->channel.chan)
782+ tegra_hsp_doorbell_startup(db->channel.chan);
783+ }
784+
785+ if (hsp->mailboxes) {
786+ for (i = 0; i < hsp->num_sm; i++) {
787+ struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
781788
782− if (mb->channel.chan->cl)
783− tegra_hsp_mailbox_startup(mb->channel.chan);
789+ if (mb->channel.chan->cl)
790+ tegra_hsp_mailbox_startup(mb->channel.chan);
791+ }
784792 }
785793
786794 return 0;
787795 }
788796
789−static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume);
797+static const struct dev_pm_ops tegra_hsp_pm_ops = {
798+ .resume_noirq = tegra_hsp_resume,
799+};
790800
791801 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
792802 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
include/linux/omap-mailbox.h+3−1
@@ -6,7 +6,9 @@ · 5 unmodified lines
66 #ifndef OMAP_MAILBOX_H
77 #define OMAP_MAILBOX_H
88
9−typedef u32 mbox_msg_t;
9+typedef uintptr_t mbox_msg_t;
10+
11+#define omap_mbox_message(data) (u32)(mbox_msg_t)(data)
1012
1113 typedef int __bitwise omap_mbox_irq_t;
1214 #define IRQ_TX ((__force omap_mbox_irq_t) 1)

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