Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access
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| @@ -6,7 +6,9 @@ · 5 unmodified lines | ||
| 6 | 6 | #ifndef OMAP_MAILBOX_H |
| 7 | 7 | #define OMAP_MAILBOX_H |
| 8 | 8 | |
| 9 | −typedef u32 mbox_msg_t; | |
| 9 | +typedef uintptr_t mbox_msg_t; | |
| 10 | + | |
| 11 | +#define omap_mbox_message(data) (u32)(mbox_msg_t)(data) | |
| 10 | 12 | |
| 11 | 13 | typedef int __bitwise omap_mbox_irq_t; |
| 12 | 14 | #define IRQ_TX ((__force omap_mbox_irq_t) 1) |