lael-labs/linux

Documentation/ABI/testing/sysfs-class-cxl+10−0

@@ -223,3 +223,13 @@ Description: write only · 222 unmodified lines
223	Writing 1 will issue a PERST to card which may cause the card	223	Writing 1 will issue a PERST to card which may cause the card
224	to reload the FPGA depending on load_image_on_perst.	224	to reload the FPGA depending on load_image_on_perst.
225	Users: https://github.com/ibm-capi/libcxl	225	Users: https://github.com/ibm-capi/libcxl
		226
		227	What: /sys/class/cxl/<card>/perst_reloads_same_image
		228	Date: July 2015
		229	Contact: linuxppc-dev@lists.ozlabs.org
		230	Description: read/write
		231	Trust that when an image is reloaded via PERST, it will not
		232	have changed.
		233	0 = don't trust, the image may be different (default)
		234	1 = trust that the image will not change.
		235	Users: https://github.com/ibm-capi/libcxl

Documentation/devicetree/bindings/leds/leds-powernv.txt+26−0

@@ -0,0 +1,26 @@
	1	Device Tree binding for LEDs on IBM Power Systems
	2	-------------------------------------------------
	3
	4	Required properties:
	5	- compatible : Should be "ibm,opal-v3-led".
	6	- led-mode : Should be "lightpath" or "guidinglight".
	7
	8	Each location code of FRU/Enclosure must be expressed in the
	9	form of a sub-node.
	10
	11	Required properties for the sub nodes:
	12	- led-types : Supported LED types (attention/identify/fault) provided
	13	in the form of string array.
	14
	15	Example:
	16
	17	leds {
	18	compatible = "ibm,opal-v3-led";
	19	led-mode = "lightpath";
	20
	21	U78C9.001.RST0027-P1-C1 {
	22	led-types = "identify", "fault";
	23	};
	24	...
	25	...
	26	};

Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt+3−0

               interrupt (NAND_EVTER_STAT).  If there is only one,
               that interrupt reports both types of event.
+- little-endian : If this property is absent, the big-endian mode will
+                  be in use as default for registers.
 - ranges : Each range corresponds to a single chipselect, and covers
            the entire access window as configured.
 		#size-cells = <1>;
 		reg = <0x0 0xffe1e000 0 0x2000>;
 		interrupts = <16 2 19 2>;
+		little-endian;
 		/* NOR, NAND Flashes and CPLD on board */
 		ranges = <0x0 0x0 0x0 0xee000000 0x02000000

Documentation/devicetree/bindings/powerpc/fsl/scfg.txt+18−0

@@ -0,0 +1,18 @@
	1	Freescale Supplement configuration unit (SCFG)
	2
	3	SCFG is the supplemental configuration unit, that provides SoC specific
	4	configuration and status registers for the chip. Such as getting PEX port
	5	status.
	6
	7	Required properties:
	8
	9	- compatible: should be "fsl,<chip>-scfg"
	10	- reg: should contain base address and length of SCFG memory-mapped
	11	registers
	12
	13	Example:
	14
	15	scfg: global-utilities@fc000 {
	16	compatible = "fsl,t1040-scfg";
	17	reg = <0xfc000 0x1000>;
	18	};

Documentation/trace/ftrace.txt+5−0

 	  x86-tsc: Architectures may define their own clocks. For
 	  	   example, x86 uses its own TSC cycle clock here.
+	  ppc-tb: This uses the powerpc timebase register value.
+		  This is in sync across CPUs and can also be used
+		  to correlate events across hypervisor/guest if
+		  tb_offset is known.
 	To set a clock, simply echo the clock name into this file.
 	  echo global > trace_clock

arch/powerpc/Kconfig+11−11

 	bool
 	default y
+config ARCH_HAS_DMA_SET_COHERENT_MASK
+        bool
 config PPC
 	bool
 	default y
 	select HAVE_PERF_EVENTS_NMI if PPC64
 	select EDAC_SUPPORT
 	select EDAC_ATOMIC_SCRUB
+	select ARCH_HAS_DMA_SET_COHERENT_MASK
+	select HAVE_ARCH_SECCOMP_FILTER
 config GENERIC_CSUM
 	def_bool CPU_LITTLE_ENDIAN
 	def_bool y
 	depends on NEED_MULTIPLE_NODES
-config PPC_HAS_HASH_64K
-	bool
-	depends on PPC64
-	default n
 config STDBINUTILS
 	bool "Using standard binutils settings"
 	depends on 44x
 	bool "4k page size"
 config PPC_16K_PAGES
-	bool "16k page size" if 44x || PPC_8xx
+	bool "16k page size"
+	depends on 44x || PPC_8xx
 config PPC_64K_PAGES
-	bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
+	bool "64k page size"
-	depends on !PPC_FSL_BOOK3E
+	depends on !PPC_FSL_BOOK3E && (44x || PPC_STD_MMU_64 || PPC_BOOK3E_64)
-	select PPC_HAS_HASH_64K if PPC_STD_MMU_64
 config PPC_256K_PAGES
-	bool "256k page size" if 44x
+	bool "256k page size"
-	depends on !STDBINUTILS
+	depends on 44x && !STDBINUTILS
 	help
 	  Make the page size 256k.

arch/powerpc/Makefile+20−0

@@ -288,6 +288,26 @@ PHONY += pseries_le_defconfig · 287 unmodified lines
288	pseries_le_defconfig:	288	pseries_le_defconfig:
289	$(call merge_into_defconfig,pseries_defconfig,le)	289	$(call merge_into_defconfig,pseries_defconfig,le)
290		290
		291	PHONY += mpc85xx_defconfig
		292	mpc85xx_defconfig:
		293	$(call merge_into_defconfig,mpc85xx_basic_defconfig,\
		294	85xx-32bit 85xx-hw fsl-emb-nonhw)
		295
		296	PHONY += mpc85xx_smp_defconfig
		297	mpc85xx_smp_defconfig:
		298	$(call merge_into_defconfig,mpc85xx_basic_defconfig,\
		299	85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw)
		300
		301	PHONY += corenet32_smp_defconfig
		302	corenet32_smp_defconfig:
		303	$(call merge_into_defconfig,corenet_basic_defconfig,\
		304	85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw)
		305
		306	PHONY += corenet64_smp_defconfig
		307	corenet64_smp_defconfig:
		308	$(call merge_into_defconfig,corenet_basic_defconfig,\
		309	85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw)
		310
291	define archhelp	311	define archhelp
292	@echo '* zImage - Build default images selected by kernel config'	312	@echo '* zImage - Build default images selected by kernel config'
293	@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'	313	@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'

arch/powerpc/boot/dts/fsl/p1022si-post.dtsi+1−1

@@ -175,7 +175,7 @@ · 174 unmodified lines
175		175
176	/include/ "pq3-gpio-0.dtsi"	176	/include/ "pq3-gpio-0.dtsi"
177		177
178	display@10000 {	178	display: display@10000 {
179	compatible = "fsl,diu", "fsl,p1022-diu";	179	compatible = "fsl,diu", "fsl,p1022-diu";
180	reg = <0x10000 1000>;	180	reg = <0x10000 1000>;
181	interrupts = <64 2 0 0>;	181	interrupts = <64 2 0 0>;

arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi+2−0

@@ -50,6 +50,8 @@ · 49 unmodified lines
50	pci0 = &pci0;	50	pci0 = &pci0;
51	pci1 = &pci1;	51	pci1 = &pci1;
52	pci2 = &pci2;	52	pci2 = &pci2;
		53	vga = &display;
		54	display = &display;
53	};	55	};
54		56
55	cpus {	57	cpus {

arch/powerpc/boot/dts/fsl/t1040si-post.dtsi+5−0

 		reg	   = <0xea000 0x4000>;
 	};
+	scfg: global-utilities@fc000 {
+		compatible = "fsl,t1040-scfg";
+		reg = <0xfc000 0x1000>;
+	};
 /include/ "elo3-dma-0.dtsi"
 /include/ "elo3-dma-1.dtsi"
 /include/ "qoriq-espi-0.dtsi"

arch/powerpc/boot/dts/t1023rdb.dts+12−1

 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,ifc-nand";
-			reg = <0x2 0x0 0x10000>;
+			reg = <0x1 0x0 0x10000>;
 		};
 	};
 		};
 		i2c@118100 {
+			current-sensor@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+			current-sensor@41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
 		};
 	};

arch/powerpc/boot/dts/t1024rdb.dts+6−0

 				reg = <0x4c>;
 			};
+			current-sensor@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
 			eeprom@50 {
 				compatible = "atmel,24c256";
 				reg = <0x50>;

arch/powerpc/boot/dts/t1040d4rdb.dts+46−0

@@ -0,0 +1,46 @@
	1	/*
	2	* T1040D4RDB Device Tree Source
	3	*
	4	* Copyright 2015 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/include/ "fsl/t104xsi-pre.dtsi"
	36	/include/ "t104xd4rdb.dtsi"
	37
	38	/ {
	39	model = "fsl,T1040D4RDB";
	40	compatible = "fsl,T1040D4RDB";
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43	interrupt-parent = <&mpic>;
	44	};
	45
	46	/include/ "fsl/t1040si-post.dtsi"

arch/powerpc/boot/dts/t1042d4rdb.dts+53−0

@@ -0,0 +1,53 @@
	1	/*
	2	* T1042D4RDB Device Tree Source
	3	*
	4	* Copyright 2015 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/include/ "fsl/t104xsi-pre.dtsi"
	36	/include/ "t104xd4rdb.dtsi"
	37
	38	/ {
	39	model = "fsl,T1042D4RDB";
	40	compatible = "fsl,T1042D4RDB";
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43	interrupt-parent = <&mpic>;
	44
	45	ifc: localbus@ffe124000 {
	46	cpld@3,0 {
	47	compatible = "fsl,t1040d4rdb-cpld",
	48	"fsl,deepsleep-cpld";
	49	};
	50	};
	51	};
	52
	53	/include/ "fsl/t1040si-post.dtsi"

arch/powerpc/boot/dts/t104xd4rdb.dtsi+205−0

@@ -0,0 +1,205 @@
	1	/*
	2	* T1040D4RDB/T1042D4RDB Device Tree Source
	3	*
	4	* Copyright 2015 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/ {
	36	reserved-memory {
	37	#address-cells = <2>;
	38	#size-cells = <2>;
	39	ranges;
	40
	41	bman_fbpr: bman-fbpr {
	42	size = <0 0x1000000>;
	43	alignment = <0 0x1000000>;
	44	};
	45	qman_fqd: qman-fqd {
	46	size = <0 0x400000>;
	47	alignment = <0 0x400000>;
	48	};
	49	qman_pfdr: qman-pfdr {
	50	size = <0 0x2000000>;
	51	alignment = <0 0x2000000>;
	52	};
	53	};
	54
	55	ifc: localbus@ffe124000 {
	56	reg = <0xf 0xfe124000 0 0x2000>;
	57	ranges = <0 0 0xf 0xe8000000 0x08000000
	58	2 0 0xf 0xff800000 0x00010000
	59	3 0 0xf 0xffdf0000 0x00008000>;
	60
	61	nor@0,0 {
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	compatible = "cfi-flash";
	65	reg = <0x0 0x0 0x8000000>;
	66	bank-width = <2>;
	67	device-width = <1>;
	68	};
	69
	70	nand@2,0 {
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	compatible = "fsl,ifc-nand";
	74	reg = <0x2 0x0 0x10000>;
	75	};
	76
	77	cpld@3,0 {
	78	compatible = "fsl,t1040d4rdb-cpld";
	79	reg = <3 0 0x300>;
	80	};
	81	};
	82
	83	memory {
	84	device_type = "memory";
	85	};
	86
	87	dcsr: dcsr@f00000000 {
	88	ranges = <0x00000000 0xf 0x00000000 0x01072000>;
	89	};
	90
	91	bportals: bman-portals@ff4000000 {
	92	ranges = <0x0 0xf 0xf4000000 0x2000000>;
	93	};
	94
	95	qportals: qman-portals@ff6000000 {
	96	ranges = <0x0 0xf 0xf6000000 0x2000000>;
	97	};
	98
	99	soc: soc@ffe000000 {
	100	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
	101	reg = <0xf 0xfe000000 0 0x00001000>;
	102
	103	spi@110000 {
	104	flash@0 {
	105	#address-cells = <1>;
	106	#size-cells = <1>;
	107	compatible = "micron,n25q512ax3";
	108	reg = <0>;
	109	/* input clock */
	110	spi-max-frequency = <10000000>;
	111	};
	112	};
	113	i2c@118000 {
	114	hwmon@4c {
	115	compatible = "adi,adt7461";
	116	reg = <0x4c>;
	117	};
	118
	119	rtc@68 {
	120	compatible = "dallas,ds1337";
	121	reg = <0x68>;
	122	interrupts = <0x2 0x1 0 0>;
	123	};
	124	};
	125
	126	i2c@118100 {
	127	mux@77 {
	128	/*
	129	* Child nodes of mux depend on which i2c
	130	* devices are connected via the mini PCI
	131	* connector slot1, the mini PCI connector
	132	* slot2, the HDMI connector, and the PEX
	133	* slot. Systems with such devices attached
	134	* should provide a wrapper .dts file that
	135	* includes this one, and adds those nodes
	136	*/
	137	compatible = "nxp,pca9546";
	138	reg = <0x77>;
	139	#address-cells = <1>;
	140	#size-cells = <0>;
	141	};
	142	};
	143
	144	};
	145
	146	pci0: pcie@ffe240000 {
	147	reg = <0xf 0xfe240000 0 0x10000>;
	148	ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000
	149	0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>;
	150	pcie@0 {
	151	ranges = <0x02000000 0 0xe0000000
	152	0x02000000 0 0xe0000000
	153	0 0x10000000
	154
	155	0x01000000 0 0x00000000
	156	0x01000000 0 0x00000000
	157	0 0x00010000>;
	158	};
	159	};
	160
	161	pci1: pcie@ffe250000 {
	162	reg = <0xf 0xfe250000 0 0x10000>;
	163	ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
	164	0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
	165	pcie@0 {
	166	ranges = <0x02000000 0 0xe0000000
	167	0x02000000 0 0xe0000000
	168	0 0x10000000
	169
	170	0x01000000 0 0x00000000
	171	0x01000000 0 0x00000000
	172	0 0x00010000>;
	173	};
	174	};
	175
	176	pci2: pcie@ffe260000 {
	177	reg = <0xf 0xfe260000 0 0x10000>;
	178	ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
	179	0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
	180	pcie@0 {
	181	ranges = <0x02000000 0 0xe0000000
	182	0x02000000 0 0xe0000000
	183	0 0x10000000
	184
	185	0x01000000 0 0x00000000
	186	0x01000000 0 0x00000000
	187	0 0x00010000>;
	188	};
	189	};
	190
	191	pci3: pcie@ffe270000 {
	192	reg = <0xf 0xfe270000 0 0x10000>;
	193	ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
	194	0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
	195	pcie@0 {
	196	ranges = <0x02000000 0 0xe0000000
	197	0x02000000 0 0xe0000000
	198	0 0x10000000
	199
	200	0x01000000 0 0x00000000
	201	0x01000000 0 0x00000000
	202	0 0x00010000>;
	203	};
	204	};
	205	};

arch/powerpc/configs/85xx-32bit.config+5−0

@@ -0,0 +1,5 @@
	1	CONFIG_HIGHMEM=y
	2	CONFIG_KEXEC=y
	3	CONFIG_PPC_85xx=y
	4	CONFIG_PROC_KCORE=y
	5	CONFIG_PHYS_64BIT=y

arch/powerpc/configs/85xx-64bit.config+4−0

@@ -0,0 +1,4 @@
	1	CONFIG_MATH_EMULATION=y
	2	CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
	3	CONFIG_PPC64=y
	4	CONFIG_PPC_BOOK3E_64=y

arch/powerpc/configs/85xx-hw.config+142−0

@@ -0,0 +1,142 @@
	1	CONFIG_AQUANTIA_PHY=y
	2	CONFIG_AT803X_PHY=y
	3	CONFIG_ATA=y
	4	CONFIG_BLK_DEV_SD=y
	5	CONFIG_BLK_DEV_SR_VENDOR=y
	6	CONFIG_BLK_DEV_SR=y
	7	CONFIG_BROADCOM_PHY=y
	8	CONFIG_C293_PCIE=y
	9	CONFIG_CHR_DEV_SG=y
	10	CONFIG_CHR_DEV_ST=y
	11	CONFIG_CICADA_PHY=y
	12	CONFIG_CLK_QORIQ=y
	13	CONFIG_CRYPTO_DEV_FSL_CAAM=y
	14	CONFIG_CRYPTO_DEV_TALITOS=y
	15	CONFIG_DAVICOM_PHY=y
	16	CONFIG_DMADEVICES=y
	17	CONFIG_E1000E=y
	18	CONFIG_E1000=y
	19	CONFIG_EDAC_MM_EDAC=y
	20	CONFIG_EDAC_MPC85XX=y
	21	CONFIG_EDAC=y
	22	CONFIG_EEPROM_AT24=y
	23	CONFIG_EEPROM_LEGACY=y
	24	CONFIG_FB_FSL_DIU=y
	25	CONFIG_FS_ENET=y
	26	CONFIG_FSL_CORENET_CF=y
	27	CONFIG_FSL_DMA=y
	28	CONFIG_FSL_HV_MANAGER=y
	29	CONFIG_FSL_PQ_MDIO=y
	30	CONFIG_FSL_RIO=y
	31	CONFIG_FSL_XGMAC_MDIO=y
	32	CONFIG_GIANFAR=y
	33	CONFIG_GPIO_MPC8XXX=y
	34	CONFIG_HID_A4TECH=y
	35	CONFIG_HID_APPLE=y
	36	CONFIG_HID_BELKIN=y
	37	CONFIG_HID_CHERRY=y
	38	CONFIG_HID_CHICONY=y
	39	CONFIG_HID_CYPRESS=y
	40	CONFIG_HID_EZKEY=y
	41	CONFIG_HID_GYRATION=y
	42	CONFIG_HID_LOGITECH=y
	43	CONFIG_HID_MICROSOFT=y
	44	CONFIG_HID_MONTEREY=y
	45	CONFIG_HID_PANTHERLORD=y
	46	CONFIG_HID_PETALYNX=y
	47	CONFIG_HID_SAMSUNG=y
	48	CONFIG_HID_SUNPLUS=y
	49	CONFIG_I2C_CHARDEV=y
	50	CONFIG_I2C_CPM=m
	51	CONFIG_I2C_MPC=y
	52	CONFIG_I2C_MUX_PCA954x=y
	53	CONFIG_I2C_MUX=y
	54	CONFIG_I2C=y
	55	CONFIG_IGB=y
	56	CONFIG_INPUT_FF_MEMLESS=m
	57	# CONFIG_INPUT_KEYBOARD is not set
	58	# CONFIG_INPUT_MOUSEDEV is not set
	59	# CONFIG_INPUT_MOUSE is not set
	60	CONFIG_MARVELL_PHY=y
	61	CONFIG_MDIO_BUS_MUX_GPIO=y
	62	CONFIG_MDIO_BUS_MUX_MMIOREG=y
	63	CONFIG_MMC_SDHCI_OF_ESDHC=y
	64	CONFIG_MMC_SDHCI_PLTFM=y
	65	CONFIG_MMC_SDHCI=y
	66	CONFIG_MMC=y
	67	CONFIG_MTD_BLOCK=y
	68	CONFIG_MTD_CFI_AMDSTD=y
	69	CONFIG_MTD_CFI_INTELEXT=y
	70	CONFIG_MTD_CFI=y
	71	CONFIG_MTD_CMDLINE_PARTS=y
	72	CONFIG_MTD_M25P80=y
	73	CONFIG_MTD_NAND_FSL_ELBC=y
	74	CONFIG_MTD_NAND_FSL_IFC=y
	75	CONFIG_MTD_NAND=y
	76	CONFIG_MTD_PHYSMAP_OF=y
	77	CONFIG_MTD_PHYSMAP=y
	78	CONFIG_MTD_PLATRAM=y
	79	CONFIG_MTD_SPI_NOR=y
	80	CONFIG_NETDEVICES=y
	81	CONFIG_NVRAM=y
	82	CONFIG_PATA_ALI=y
	83	CONFIG_PATA_SIL680=y
	84	CONFIG_PATA_VIA=y
	85	# CONFIG_PCIEASPM is not set
	86	CONFIG_PCIEPORTBUS=y
	87	CONFIG_PCI_MSI=y
	88	CONFIG_PCI=y
	89	CONFIG_PPC_EPAPR_HV_BYTECHAN=y
	90	# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
	91	CONFIG_QE_GPIO=y
	92	CONFIG_QUICC_ENGINE=y
	93	CONFIG_RAPIDIO=y
	94	CONFIG_RTC_CLASS=y
	95	CONFIG_RTC_DRV_CMOS=y
	96	CONFIG_RTC_DRV_DS1307=y
	97	CONFIG_RTC_DRV_DS1374=y
	98	CONFIG_RTC_DRV_DS3232=y
	99	CONFIG_SATA_AHCI=y
	100	CONFIG_SATA_FSL=y
	101	CONFIG_SATA_SIL24=y
	102	CONFIG_SATA_SIL=y
	103	CONFIG_SCSI_LOGGING=y
	104	CONFIG_SCSI_SYM53C8XX_2=y
	105	CONFIG_SENSORS_INA2XX=y
	106	CONFIG_SENSORS_LM90=y
	107	CONFIG_SERIAL_8250_CONSOLE=y
	108	CONFIG_SERIAL_8250_DETECT_IRQ=y
	109	CONFIG_SERIAL_8250_MANY_PORTS=y
	110	CONFIG_SERIAL_8250_NR_UARTS=6
	111	CONFIG_SERIAL_8250_RSA=y
	112	CONFIG_SERIAL_8250_RUNTIME_UARTS=6
	113	CONFIG_SERIAL_8250=y
	114	CONFIG_SERIAL_QE=m
	115	CONFIG_SERIO_LIBPS2=y
	116	# CONFIG_SND_DRIVERS is not set
	117	CONFIG_SND_INTEL8X0=y
	118	CONFIG_SND_POWERPC_SOC=y
	119	# CONFIG_SND_PPC is not set
	120	CONFIG_SND_SOC=y
	121	# CONFIG_SND_SUPPORT_OLD_API is not set
	122	# CONFIG_SND_USB is not set
	123	CONFIG_SND=y
	124	CONFIG_SOUND=y
	125	CONFIG_SPI_FSL_ESPI=y
	126	CONFIG_SPI_FSL_SPI=y
	127	CONFIG_SPI_GPIO=y
	128	CONFIG_SPI=y
	129	CONFIG_TERANETICS_PHY=y
	130	CONFIG_UCC_GETH=y
	131	CONFIG_USB_EHCI_FSL=y
	132	CONFIG_USB_EHCI_HCD=y
	133	CONFIG_USB_HID=m
	134	CONFIG_USB_MON=y
	135	CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
	136	CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
	137	CONFIG_USB_OHCI_HCD=y
	138	CONFIG_USB_STORAGE=y
	139	CONFIG_USB=y
	140	# CONFIG_VGA_CONSOLE is not set
	141	CONFIG_VIRT_DRIVERS=y
	142	CONFIG_VITESSE_PHY=y

arch/powerpc/configs/85xx-smp.config+2−0

@@ -0,0 +1,2 @@
	1	CONFIG_NR_CPUS=24
	2	CONFIG_SMP=y

arch/powerpc/configs/altivec.config+1−0

@@ -0,0 +1 @@
		1	CONFIG_ALTIVEC=y

arch/powerpc/configs/corenet32_smp_defconfig+0−185

@@ -1,185 +0,0 @@
1	CONFIG_PPC_85xx=y
2	CONFIG_SMP=y
3	CONFIG_NR_CPUS=8
4	CONFIG_SYSVIPC=y
5	CONFIG_POSIX_MQUEUE=y
6	CONFIG_AUDIT=y
7	CONFIG_NO_HZ=y
8	CONFIG_HIGH_RES_TIMERS=y
9	CONFIG_BSD_PROCESS_ACCT=y
10	CONFIG_IKCONFIG=y
11	CONFIG_IKCONFIG_PROC=y
12	CONFIG_LOG_BUF_SHIFT=14
13	CONFIG_BLK_DEV_INITRD=y
14	CONFIG_KALLSYMS_ALL=y
15	CONFIG_EMBEDDED=y
16	CONFIG_PERF_EVENTS=y
17	CONFIG_SLAB=y
18	CONFIG_MODULES=y
19	CONFIG_MODULE_UNLOAD=y
20	CONFIG_MODULE_FORCE_UNLOAD=y
21	CONFIG_MODVERSIONS=y
22	# CONFIG_BLK_DEV_BSG is not set
23	CONFIG_PARTITION_ADVANCED=y
24	CONFIG_MAC_PARTITION=y
25	CONFIG_CORENET_GENERIC=y
26	CONFIG_HIGHMEM=y
27	# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
28	CONFIG_BINFMT_MISC=m
29	CONFIG_KEXEC=y
30	CONFIG_FORCE_MAX_ZONEORDER=13
31	CONFIG_PCI=y
32	CONFIG_PCIEPORTBUS=y
33	# CONFIG_PCIEASPM is not set
34	CONFIG_PCI_MSI=y
35	CONFIG_RAPIDIO=y
36	CONFIG_FSL_RIO=y
37	CONFIG_NET=y
38	CONFIG_PACKET=y
39	CONFIG_UNIX=y
40	CONFIG_XFRM_USER=y
41	CONFIG_XFRM_SUB_POLICY=y
42	CONFIG_XFRM_STATISTICS=y
43	CONFIG_NET_KEY=y
44	CONFIG_NET_KEY_MIGRATE=y
45	CONFIG_INET=y
46	CONFIG_IP_MULTICAST=y
47	CONFIG_IP_ADVANCED_ROUTER=y
48	CONFIG_IP_MULTIPLE_TABLES=y
49	CONFIG_IP_ROUTE_MULTIPATH=y
50	CONFIG_IP_ROUTE_VERBOSE=y
51	CONFIG_IP_PNP=y
52	CONFIG_IP_PNP_DHCP=y
53	CONFIG_IP_PNP_BOOTP=y
54	CONFIG_IP_PNP_RARP=y
55	CONFIG_NET_IPIP=y
56	CONFIG_IP_MROUTE=y
57	CONFIG_IP_PIMSM_V1=y
58	CONFIG_IP_PIMSM_V2=y
59	CONFIG_INET_AH=y
60	CONFIG_INET_ESP=y
61	CONFIG_INET_IPCOMP=y
62	# CONFIG_INET_LRO is not set
63	CONFIG_IPV6=y
64	CONFIG_IP_SCTP=m
65	CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
66	CONFIG_DEVTMPFS=y
67	CONFIG_DEVTMPFS_MOUNT=y
68	CONFIG_MTD=y
69	CONFIG_MTD_CMDLINE_PARTS=y
70	CONFIG_MTD_BLOCK=y
71	CONFIG_MTD_CFI=y
72	CONFIG_MTD_CFI_INTELEXT=y
73	CONFIG_MTD_CFI_AMDSTD=y
74	CONFIG_MTD_PHYSMAP_OF=y
75	CONFIG_MTD_NAND=y
76	CONFIG_MTD_NAND_FSL_ELBC=y
77	CONFIG_MTD_NAND_FSL_IFC=y
78	CONFIG_MTD_SPI_NOR=y
79	CONFIG_BLK_DEV_LOOP=y
80	CONFIG_BLK_DEV_RAM=y
81	CONFIG_BLK_DEV_RAM_SIZE=131072
82	CONFIG_BLK_DEV_SD=y
83	CONFIG_CHR_DEV_ST=y
84	CONFIG_BLK_DEV_SR=y
85	CONFIG_CHR_DEV_SG=y
86	CONFIG_SCSI_LOGGING=y
87	CONFIG_SCSI_SYM53C8XX_2=y
88	CONFIG_ATA=y
89	CONFIG_SATA_AHCI=y
90	CONFIG_SATA_FSL=y
91	CONFIG_SATA_SIL24=y
92	CONFIG_SATA_SIL=y
93	CONFIG_PATA_SIL680=y
94	CONFIG_NETDEVICES=y
95	CONFIG_FSL_PQ_MDIO=y
96	CONFIG_FSL_XGMAC_MDIO=y
97	CONFIG_E1000=y
98	CONFIG_E1000E=y
99	CONFIG_AT803X_PHY=y
100	CONFIG_VITESSE_PHY=y
101	CONFIG_FIXED_PHY=y
102	CONFIG_MDIO_BUS_MUX_GPIO=y
103	CONFIG_MDIO_BUS_MUX_MMIOREG=y
104	# CONFIG_INPUT_MOUSEDEV is not set
105	# CONFIG_INPUT_KEYBOARD is not set
106	# CONFIG_INPUT_MOUSE is not set
107	CONFIG_SERIO_LIBPS2=y
108	# CONFIG_LEGACY_PTYS is not set
109	CONFIG_PPC_EPAPR_HV_BYTECHAN=y
110	CONFIG_SERIAL_8250=y
111	CONFIG_SERIAL_8250_CONSOLE=y
112	CONFIG_SERIAL_8250_MANY_PORTS=y
113	CONFIG_SERIAL_8250_DETECT_IRQ=y
114	CONFIG_SERIAL_8250_RSA=y
115	CONFIG_NVRAM=y
116	CONFIG_I2C=y
117	CONFIG_I2C_CHARDEV=y
118	CONFIG_I2C_MPC=y
119	CONFIG_I2C_MUX=y
120	CONFIG_I2C_MUX_PCA954x=y
121	CONFIG_SPI=y
122	CONFIG_SPI_GPIO=y
123	CONFIG_SPI_FSL_SPI=y
124	CONFIG_SPI_FSL_ESPI=y
125	CONFIG_SENSORS_LM90=y
126	CONFIG_SENSORS_INA2XX=y
127	CONFIG_USB_HID=m
128	CONFIG_USB=y
129	CONFIG_USB_MON=y
130	CONFIG_USB_EHCI_HCD=y
131	CONFIG_USB_EHCI_FSL=y
132	CONFIG_USB_OHCI_HCD=y
133	CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
134	CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
135	CONFIG_USB_STORAGE=y
136	CONFIG_MMC=y
137	CONFIG_MMC_SDHCI=y
138	CONFIG_EDAC=y
139	CONFIG_EDAC_MM_EDAC=y
140	CONFIG_EDAC_MPC85XX=y
141	CONFIG_RTC_CLASS=y
142	CONFIG_RTC_DRV_DS1307=y
143	CONFIG_RTC_DRV_DS1374=y
144	CONFIG_RTC_DRV_DS3232=y
145	CONFIG_UIO=y
146	CONFIG_VIRT_DRIVERS=y
147	CONFIG_FSL_HV_MANAGER=y
148	CONFIG_STAGING=y
149	CONFIG_FSL_CORENET_CF=y
150	CONFIG_CLK_QORIQ=y
151	CONFIG_EXT2_FS=y
152	CONFIG_EXT3_FS=y
153	# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
154	CONFIG_ISO9660_FS=m
155	CONFIG_JOLIET=y
156	CONFIG_ZISOFS=y
157	CONFIG_UDF_FS=m
158	CONFIG_MSDOS_FS=m
159	CONFIG_VFAT_FS=y
160	CONFIG_NTFS_FS=y
161	CONFIG_PROC_KCORE=y
162	CONFIG_TMPFS=y
163	CONFIG_HUGETLBFS=y
164	CONFIG_JFFS2_FS=y
165	CONFIG_CRAMFS=y
166	CONFIG_NFS_FS=y
167	CONFIG_NFS_V4=y
168	CONFIG_ROOT_NFS=y
169	CONFIG_NFSD=m
170	CONFIG_NLS_CODEPAGE_437=y
171	CONFIG_NLS_CODEPAGE_850=y
172	CONFIG_NLS_ISO8859_1=y
173	CONFIG_NLS_UTF8=m
174	CONFIG_DEBUG_INFO=y
175	CONFIG_MAGIC_SYSRQ=y
176	CONFIG_DEBUG_SHIRQ=y
177	CONFIG_DETECT_HUNG_TASK=y
178	CONFIG_RCU_TRACE=y
179	CONFIG_CRYPTO_NULL=y
180	CONFIG_CRYPTO_PCBC=m
181	CONFIG_CRYPTO_MD4=y
182	CONFIG_CRYPTO_SHA256=y
183	CONFIG_CRYPTO_SHA512=y
184	# CONFIG_CRYPTO_ANSI_CPRNG is not set
185	CONFIG_CRYPTO_DEV_FSL_CAAM=y

arch/powerpc/configs/corenet_basic_defconfig+1−0

@@ -0,0 +1 @@
		1	CONFIG_CORENET_GENERIC=y

arch/powerpc/configs/fsl-emb-nonhw.configrenamed from arch/powerpc/configs/corenet64_smp_defconfig+107−157

-CONFIG_PPC64=y
+CONFIG_ADFS_FS=m
-CONFIG_PPC_BOOK3E_64=y
+CONFIG_AFFS_FS=m
-CONFIG_ALTIVEC=y
+CONFIG_AUDIT=y
-CONFIG_SMP=y
+CONFIG_BEFS_FS=m
-CONFIG_NR_CPUS=24
+CONFIG_BFS_FS=m
-CONFIG_SYSVIPC=y
+CONFIG_BINFMT_MISC=m
-CONFIG_FHANDLE=y
+# CONFIG_BLK_DEV_BSG is not set
-CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_BLK_DEV_INITRD=y
-CONFIG_NO_HZ=y
+CONFIG_BLK_DEV_LOOP=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_CGROUP_SCHED=y
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_CGROUPS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CRC_T10DIF=y
+CONFIG_CPUSETS=y
+CONFIG_CRAMFS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DUMMY=y
+CONFIG_EFS_FS=m
 CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
+CONFIG_EXT2_FS=y
-CONFIG_MODULES=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_MODULE_UNLOAD=y
+CONFIG_EXT3_FS=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_FB=y
-CONFIG_MODVERSIONS=y
+CONFIG_FHANDLE=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_FIXED_PHY=y
-CONFIG_PARTITION_ADVANCED=y
+CONFIG_FONT_8x16=y
-CONFIG_MAC_PARTITION=y
+CONFIG_FONT_8x8=y
-CONFIG_CORENET_GENERIC=y
+CONFIG_FONTS=y
-# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
+CONFIG_FORCE_MAX_ZONEORDER=13
-CONFIG_BINFMT_MISC=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_MATH_EMULATION=y
+CONFIG_FRAME_WARN=1024
-CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
+CONFIG_FTL=y
-CONFIG_PCIEPORTBUS=y
+CONFIG_HFS_FS=m
-CONFIG_PCI_MSI=y
+CONFIG_HFSPLUS_FS=m
-CONFIG_RAPIDIO=y
+CONFIG_HIGH_RES_TIMERS=y
-CONFIG_FSL_RIO=y
+CONFIG_HPFS_FS=m
-CONFIG_NET=y
+CONFIG_HUGETLBFS=y
-CONFIG_PACKET=y
+CONFIG_IKCONFIG_PROC=y
-CONFIG_UNIX=y
+CONFIG_IKCONFIG=y
-CONFIG_XFRM_USER=y
+CONFIG_INET_AH=y
-CONFIG_NET_KEY=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
 CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
 CONFIG_IP_MROUTE=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_MULTIPLE_TABLES=y
 CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
-CONFIG_INET_ESP=y
+CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
+CONFIG_IP_PNP_RARP=y
-CONFIG_IPV6=y
+CONFIG_IP_PNP=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
 CONFIG_IP_SCTP=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_IPV6=y
-CONFIG_DEVTMPFS=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_FSL_ELBC=y
-CONFIG_MTD_NAND_FSL_IFC=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_EEPROM_LEGACY=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_ATA=y
-CONFIG_SATA_FSL=y
-CONFIG_SATA_SIL24=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_FSL_PQ_MDIO=y
-CONFIG_FSL_XGMAC_MDIO=y
-CONFIG_E1000E=y
-CONFIG_VITESSE_PHY=y
-CONFIG_FIXED_PHY=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_PPC_EPAPR_HV_BYTECHAN=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MPC=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_FSL_SPI=y
-CONFIG_SPI_FSL_ESPI=y
-CONFIG_SENSORS_LM90=y
-CONFIG_SENSORS_INA2XX=y
-CONFIG_USB_HID=m
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_EDAC=y
-CONFIG_EDAC_MM_EDAC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_DS1374=y
-CONFIG_RTC_DRV_DS3232=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_DMA=y
-CONFIG_VIRT_DRIVERS=y
-CONFIG_FSL_HV_MANAGER=y
-CONFIG_CLK_QORIQ=y
-CONFIG_FSL_CORENET_CF=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS=y
 CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
+CONFIG_KALLSYMS_ALL=y
-CONFIG_UDF_FS=m
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_MAC_PARTITION=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
 CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
+CONFIG_MTD_UBI=y
-CONFIG_NTFS_FS=y
+CONFIG_MTD=y
-CONFIG_PROC_KCORE=y
+CONFIG_NET_IPIP=y
-CONFIG_TMPFS=y
+CONFIG_NET_KEY_MIGRATE=y
-CONFIG_HUGETLBFS=y
+CONFIG_NET_KEY=y
-CONFIG_JFFS2_FS=y
+CONFIG_NET=y
-CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_NFSD=y
-CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
-CONFIG_CRC_T10DIF=y
+CONFIG_NO_HZ=y
-CONFIG_DEBUG_INFO=y
+CONFIG_NTFS_FS=y
-CONFIG_FRAME_WARN=1024
+CONFIG_PACKET=y
-CONFIG_DEBUG_FS=y
+CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_PERF_EVENTS=y
-CONFIG_DEBUG_SHIRQ=y
+CONFIG_POSIX_MQUEUE=y
-CONFIG_DETECT_HUNG_TASK=y
+CONFIG_QNX4FS_FS=m
-CONFIG_CRYPTO_NULL=y
+CONFIG_RCU_TRACE=y
-CONFIG_CRYPTO_PCBC=m
+CONFIG_ROOT_NFS=y
-CONFIG_CRYPTO_MD4=y
+CONFIG_SYSV_FS=m
-CONFIG_CRYPTO_SHA256=y
+CONFIG_SYSVIPC=y
-CONFIG_CRYPTO_SHA512=y
+CONFIG_TMPFS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_UBIFS_FS=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_UDF_FS=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_UFS_FS=m
+CONFIG_UIO=y
+CONFIG_UNIX=y
+CONFIG_VFAT_FS=y
+CONFIG_VXFS_FS=m
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_USER=y
+CONFIG_ZISOFS=y

arch/powerpc/configs/mpc85xx_basic_defconfig+23−0

@@ -0,0 +1,23 @@
	1	CONFIG_MATH_EMULATION=y
	2	CONFIG_MPC8536_DS=y
	3	CONFIG_MPC8540_ADS=y
	4	CONFIG_MPC8560_ADS=y
	5	CONFIG_MPC85xx_CDS=y
	6	CONFIG_MPC85xx_DS=y
	7	CONFIG_MPC85xx_MDS=y
	8	CONFIG_MPC85xx_RDB=y
	9	CONFIG_KSI8560=y
	10	CONFIG_MVME2500=y
	11	CONFIG_P1010_RDB=y
	12	CONFIG_P1022_DS=y
	13	CONFIG_P1022_RDK=y
	14	CONFIG_P1023_RDB=y
	15	CONFIG_SBC8548=y
	16	CONFIG_SOCRATES=y
	17	CONFIG_STX_GP3=y
	18	CONFIG_TQM8540=y
	19	CONFIG_TQM8541=y
	20	CONFIG_TQM8548=y
	21	CONFIG_TQM8555=y
	22	CONFIG_TQM8560=y
	23	CONFIG_XES_MPC85xx=y

arch/powerpc/configs/mpc85xx_defconfig+0−252

@@ -1,252 +0,0 @@
1	CONFIG_PPC_85xx=y
2	CONFIG_PHYS_64BIT=y
3	CONFIG_SYSVIPC=y
4	CONFIG_POSIX_MQUEUE=y
5	CONFIG_AUDIT=y
6	CONFIG_IRQ_DOMAIN_DEBUG=y
7	CONFIG_NO_HZ=y
8	CONFIG_HIGH_RES_TIMERS=y
9	CONFIG_BSD_PROCESS_ACCT=y
10	CONFIG_IKCONFIG=y
11	CONFIG_IKCONFIG_PROC=y
12	CONFIG_LOG_BUF_SHIFT=14
13	CONFIG_BLK_DEV_INITRD=y
14	CONFIG_EXPERT=y
15	CONFIG_KALLSYMS_ALL=y
16	CONFIG_MODULES=y
17	CONFIG_MODULE_UNLOAD=y
18	CONFIG_MODULE_FORCE_UNLOAD=y
19	CONFIG_MODVERSIONS=y
20	# CONFIG_BLK_DEV_BSG is not set
21	CONFIG_PARTITION_ADVANCED=y
22	CONFIG_MAC_PARTITION=y
23	CONFIG_C293_PCIE=y
24	CONFIG_MPC8540_ADS=y
25	CONFIG_MPC8560_ADS=y
26	CONFIG_MPC85xx_CDS=y
27	CONFIG_MPC85xx_MDS=y
28	CONFIG_MPC8536_DS=y
29	CONFIG_MPC85xx_DS=y
30	CONFIG_MPC85xx_RDB=y
31	CONFIG_P1010_RDB=y
32	CONFIG_P1022_DS=y
33	CONFIG_P1022_RDK=y
34	CONFIG_P1023_RDB=y
35	CONFIG_SOCRATES=y
36	CONFIG_KSI8560=y
37	CONFIG_XES_MPC85xx=y
38	CONFIG_STX_GP3=y
39	CONFIG_TQM8540=y
40	CONFIG_TQM8541=y
41	CONFIG_TQM8548=y
42	CONFIG_TQM8555=y
43	CONFIG_TQM8560=y
44	CONFIG_SBC8548=y
45	CONFIG_MVME2500=y
46	CONFIG_QUICC_ENGINE=y
47	CONFIG_QE_GPIO=y
48	CONFIG_HIGHMEM=y
49	CONFIG_BINFMT_MISC=m
50	CONFIG_MATH_EMULATION=y
51	CONFIG_FORCE_MAX_ZONEORDER=12
52	CONFIG_PCI=y
53	CONFIG_PCIEPORTBUS=y
54	# CONFIG_PCIEASPM is not set
55	CONFIG_PCI_MSI=y
56	CONFIG_RAPIDIO=y
57	CONFIG_NET=y
58	CONFIG_PACKET=y
59	CONFIG_UNIX=y
60	CONFIG_XFRM_USER=y
61	CONFIG_NET_KEY=y
62	CONFIG_INET=y
63	CONFIG_IP_MULTICAST=y
64	CONFIG_IP_ADVANCED_ROUTER=y
65	CONFIG_IP_MULTIPLE_TABLES=y
66	CONFIG_IP_ROUTE_MULTIPATH=y
67	CONFIG_IP_ROUTE_VERBOSE=y
68	CONFIG_IP_PNP=y
69	CONFIG_IP_PNP_DHCP=y
70	CONFIG_IP_PNP_BOOTP=y
71	CONFIG_IP_PNP_RARP=y
72	CONFIG_NET_IPIP=y
73	CONFIG_IP_MROUTE=y
74	CONFIG_IP_PIMSM_V1=y
75	CONFIG_IP_PIMSM_V2=y
76	CONFIG_INET_ESP=y
77	# CONFIG_INET_XFRM_MODE_BEET is not set
78	# CONFIG_INET_LRO is not set
79	CONFIG_IPV6=y
80	CONFIG_IP_SCTP=m
81	CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
82	CONFIG_DEVTMPFS=y
83	CONFIG_DEVTMPFS_MOUNT=y
84	CONFIG_MTD=y
85	CONFIG_MTD_CMDLINE_PARTS=y
86	CONFIG_MTD_BLOCK=y
87	CONFIG_FTL=y
88	CONFIG_MTD_CFI=y
89	CONFIG_MTD_CFI_INTELEXT=y
90	CONFIG_MTD_CFI_AMDSTD=y
91	CONFIG_MTD_PHYSMAP=y
92	CONFIG_MTD_PHYSMAP_OF=y
93	CONFIG_MTD_PLATRAM=y
94	CONFIG_MTD_M25P80=y
95	CONFIG_MTD_NAND=y
96	CONFIG_MTD_NAND_FSL_ELBC=y
97	CONFIG_MTD_NAND_FSL_IFC=y
98	CONFIG_MTD_SPI_NOR=y
99	CONFIG_MTD_UBI=y
100	CONFIG_BLK_DEV_LOOP=y
101	CONFIG_BLK_DEV_NBD=y
102	CONFIG_BLK_DEV_RAM=y
103	CONFIG_BLK_DEV_RAM_SIZE=131072
104	CONFIG_EEPROM_AT24=y
105	CONFIG_EEPROM_LEGACY=y
106	CONFIG_BLK_DEV_SD=y
107	CONFIG_CHR_DEV_ST=y
108	CONFIG_BLK_DEV_SR=y
109	CONFIG_CHR_DEV_SG=y
110	CONFIG_SCSI_LOGGING=y
111	CONFIG_ATA=y
112	CONFIG_SATA_AHCI=y
113	CONFIG_SATA_FSL=y
114	CONFIG_SATA_SIL24=y
115	CONFIG_PATA_ALI=y
116	CONFIG_PATA_VIA=y
117	CONFIG_NETDEVICES=y
118	CONFIG_DUMMY=y
119	CONFIG_FS_ENET=y
120	CONFIG_UCC_GETH=y
121	CONFIG_GIANFAR=y
122	CONFIG_E1000=y
123	CONFIG_E1000E=y
124	CONFIG_IGB=y
125	CONFIG_AT803X_PHY=y
126	CONFIG_MARVELL_PHY=y
127	CONFIG_DAVICOM_PHY=y
128	CONFIG_CICADA_PHY=y
129	CONFIG_VITESSE_PHY=y
130	CONFIG_BROADCOM_PHY=y
131	CONFIG_FIXED_PHY=y
132	CONFIG_INPUT_FF_MEMLESS=m
133	# CONFIG_INPUT_MOUSEDEV is not set
134	# CONFIG_INPUT_KEYBOARD is not set
135	# CONFIG_INPUT_MOUSE is not set
136	CONFIG_SERIO_LIBPS2=y
137	CONFIG_SERIAL_8250=y
138	CONFIG_SERIAL_8250_CONSOLE=y
139	CONFIG_SERIAL_8250_NR_UARTS=6
140	CONFIG_SERIAL_8250_RUNTIME_UARTS=6
141	CONFIG_SERIAL_8250_MANY_PORTS=y
142	CONFIG_SERIAL_8250_DETECT_IRQ=y
143	CONFIG_SERIAL_8250_RSA=y
144	CONFIG_SERIAL_QE=m
145	CONFIG_NVRAM=y
146	CONFIG_I2C_CHARDEV=y
147	CONFIG_I2C_CPM=m
148	CONFIG_I2C_MPC=y
149	CONFIG_SPI=y
150	CONFIG_SPI_FSL_SPI=y
151	CONFIG_SPI_FSL_ESPI=y
152	CONFIG_GPIO_MPC8XXX=y
153	CONFIG_SENSORS_LM90=y
154	CONFIG_FB=y
155	CONFIG_FB_FSL_DIU=y
156	# CONFIG_VGA_CONSOLE is not set
157	CONFIG_FRAMEBUFFER_CONSOLE=y
158	CONFIG_SOUND=y
159	CONFIG_SND=y
160	# CONFIG_SND_SUPPORT_OLD_API is not set
161	# CONFIG_SND_DRIVERS is not set
162	CONFIG_SND_INTEL8X0=y
163	# CONFIG_SND_PPC is not set
164	# CONFIG_SND_USB is not set
165	CONFIG_SND_SOC=y
166	CONFIG_SND_POWERPC_SOC=y
167	CONFIG_HID_A4TECH=y
168	CONFIG_HID_APPLE=y
169	CONFIG_HID_BELKIN=y
170	CONFIG_HID_CHERRY=y
171	CONFIG_HID_CHICONY=y
172	CONFIG_HID_CYPRESS=y
173	CONFIG_HID_EZKEY=y
174	CONFIG_HID_GYRATION=y
175	CONFIG_HID_LOGITECH=y
176	CONFIG_HID_MICROSOFT=y
177	CONFIG_HID_MONTEREY=y
178	CONFIG_HID_PANTHERLORD=y
179	CONFIG_HID_PETALYNX=y
180	CONFIG_HID_SAMSUNG=y
181	CONFIG_HID_SUNPLUS=y
182	CONFIG_USB=y
183	CONFIG_USB_MON=y
184	CONFIG_USB_EHCI_HCD=y
185	CONFIG_USB_EHCI_FSL=y
186	CONFIG_USB_OHCI_HCD=y
187	CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
188	CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
189	CONFIG_USB_STORAGE=y
190	CONFIG_MMC=y
191	CONFIG_MMC_SDHCI=y
192	CONFIG_MMC_SDHCI_PLTFM=y
193	CONFIG_MMC_SDHCI_OF_ESDHC=y
194	CONFIG_EDAC=y
195	CONFIG_EDAC_MM_EDAC=y
196	CONFIG_EDAC_MPC85XX=y
197	CONFIG_RTC_CLASS=y
198	CONFIG_RTC_DRV_DS1307=y
199	CONFIG_RTC_DRV_DS1374=y
200	CONFIG_RTC_DRV_DS3232=y
201	CONFIG_RTC_DRV_CMOS=y
202	CONFIG_DMADEVICES=y
203	CONFIG_FSL_DMA=y
204	CONFIG_EXT2_FS=y
205	CONFIG_EXT3_FS=y
206	# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
207	CONFIG_ISO9660_FS=m
208	CONFIG_JOLIET=y
209	CONFIG_ZISOFS=y
210	CONFIG_UDF_FS=m
211	CONFIG_MSDOS_FS=m
212	CONFIG_VFAT_FS=y
213	CONFIG_NTFS_FS=y
214	CONFIG_PROC_KCORE=y
215	CONFIG_TMPFS=y
216	CONFIG_HUGETLBFS=y
217	CONFIG_ADFS_FS=m
218	CONFIG_AFFS_FS=m
219	CONFIG_HFS_FS=m
220	CONFIG_HFSPLUS_FS=m
221	CONFIG_BEFS_FS=m
222	CONFIG_BFS_FS=m
223	CONFIG_EFS_FS=m
224	CONFIG_JFFS2_FS=y
225	CONFIG_JFFS2_FS_DEBUG=1
226	CONFIG_UBIFS_FS=y
227	CONFIG_CRAMFS=y
228	CONFIG_VXFS_FS=m
229	CONFIG_HPFS_FS=m
230	CONFIG_QNX4FS_FS=m
231	CONFIG_SYSV_FS=m
232	CONFIG_UFS_FS=m
233	CONFIG_NFS_FS=y
234	CONFIG_NFS_V4=y
235	CONFIG_ROOT_NFS=y
236	CONFIG_NFSD=y
237	CONFIG_NLS_CODEPAGE_437=y
238	CONFIG_NLS_CODEPAGE_850=y
239	CONFIG_NLS_ISO8859_1=y
240	CONFIG_CRC_T10DIF=y
241	CONFIG_FONTS=y
242	CONFIG_FONT_8x8=y
243	CONFIG_FONT_8x16=y
244	CONFIG_DEBUG_INFO=y
245	CONFIG_DEBUG_FS=y
246	CONFIG_DETECT_HUNG_TASK=y
247	CONFIG_CRYPTO_PCBC=m
248	CONFIG_CRYPTO_SHA256=y
249	CONFIG_CRYPTO_SHA512=y
250	# CONFIG_CRYPTO_ANSI_CPRNG is not set
251	CONFIG_CRYPTO_DEV_FSL_CAAM=y
252	CONFIG_CRYPTO_DEV_TALITOS=y

arch/powerpc/configs/mpc85xx_smp_defconfig+0−244

@@ -1,244 +0,0 @@
1	CONFIG_PPC_85xx=y
2	CONFIG_PHYS_64BIT=y
3	CONFIG_SMP=y
4	CONFIG_NR_CPUS=8
5	CONFIG_SYSVIPC=y
6	CONFIG_POSIX_MQUEUE=y
7	CONFIG_AUDIT=y
8	CONFIG_IRQ_DOMAIN_DEBUG=y
9	CONFIG_NO_HZ=y
10	CONFIG_HIGH_RES_TIMERS=y
11	CONFIG_BSD_PROCESS_ACCT=y
12	CONFIG_IKCONFIG=y
13	CONFIG_IKCONFIG_PROC=y
14	CONFIG_LOG_BUF_SHIFT=14
15	CONFIG_BLK_DEV_INITRD=y
16	CONFIG_EXPERT=y
17	CONFIG_KALLSYMS_ALL=y
18	CONFIG_MODULES=y
19	CONFIG_MODULE_UNLOAD=y
20	CONFIG_MODULE_FORCE_UNLOAD=y
21	CONFIG_MODVERSIONS=y
22	# CONFIG_BLK_DEV_BSG is not set
23	CONFIG_PARTITION_ADVANCED=y
24	CONFIG_MAC_PARTITION=y
25	CONFIG_C293_PCIE=y
26	CONFIG_MPC8540_ADS=y
27	CONFIG_MPC8560_ADS=y
28	CONFIG_MPC85xx_CDS=y
29	CONFIG_MPC85xx_MDS=y
30	CONFIG_MPC8536_DS=y
31	CONFIG_MPC85xx_DS=y
32	CONFIG_MPC85xx_RDB=y
33	CONFIG_P1010_RDB=y
34	CONFIG_P1022_DS=y
35	CONFIG_P1022_RDK=y
36	CONFIG_P1023_RDB=y
37	CONFIG_SOCRATES=y
38	CONFIG_KSI8560=y
39	CONFIG_XES_MPC85xx=y
40	CONFIG_STX_GP3=y
41	CONFIG_TQM8540=y
42	CONFIG_TQM8541=y
43	CONFIG_TQM8548=y
44	CONFIG_TQM8555=y
45	CONFIG_TQM8560=y
46	CONFIG_SBC8548=y
47	CONFIG_QUICC_ENGINE=y
48	CONFIG_QE_GPIO=y
49	CONFIG_HIGHMEM=y
50	CONFIG_BINFMT_MISC=m
51	CONFIG_MATH_EMULATION=y
52	CONFIG_FORCE_MAX_ZONEORDER=12
53	CONFIG_PCI=y
54	CONFIG_PCI_MSI=y
55	CONFIG_RAPIDIO=y
56	CONFIG_NET=y
57	CONFIG_PACKET=y
58	CONFIG_UNIX=y
59	CONFIG_XFRM_USER=y
60	CONFIG_NET_KEY=y
61	CONFIG_INET=y
62	CONFIG_IP_MULTICAST=y
63	CONFIG_IP_ADVANCED_ROUTER=y
64	CONFIG_IP_MULTIPLE_TABLES=y
65	CONFIG_IP_ROUTE_MULTIPATH=y
66	CONFIG_IP_ROUTE_VERBOSE=y
67	CONFIG_IP_PNP=y
68	CONFIG_IP_PNP_DHCP=y
69	CONFIG_IP_PNP_BOOTP=y
70	CONFIG_IP_PNP_RARP=y
71	CONFIG_NET_IPIP=y
72	CONFIG_IP_MROUTE=y
73	CONFIG_IP_PIMSM_V1=y
74	CONFIG_IP_PIMSM_V2=y
75	CONFIG_INET_ESP=y
76	# CONFIG_INET_XFRM_MODE_BEET is not set
77	# CONFIG_INET_LRO is not set
78	CONFIG_IPV6=y
79	CONFIG_IP_SCTP=m
80	CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81	CONFIG_DEVTMPFS=y
82	CONFIG_DEVTMPFS_MOUNT=y
83	CONFIG_MTD=y
84	CONFIG_MTD_CMDLINE_PARTS=y
85	CONFIG_MTD_BLOCK=y
86	CONFIG_FTL=y
87	CONFIG_MTD_CFI=y
88	CONFIG_MTD_CFI_INTELEXT=y
89	CONFIG_MTD_CFI_AMDSTD=y
90	CONFIG_MTD_PHYSMAP_OF=y
91	CONFIG_MTD_NAND=y
92	CONFIG_MTD_NAND_FSL_ELBC=y
93	CONFIG_MTD_NAND_FSL_IFC=y
94	CONFIG_MTD_SPI_NOR=y
95	CONFIG_MTD_UBI=y
96	CONFIG_BLK_DEV_LOOP=y
97	CONFIG_BLK_DEV_NBD=y
98	CONFIG_BLK_DEV_RAM=y
99	CONFIG_BLK_DEV_RAM_SIZE=131072
100	CONFIG_EEPROM_AT24=y
101	CONFIG_EEPROM_LEGACY=y
102	CONFIG_BLK_DEV_SD=y
103	CONFIG_CHR_DEV_ST=y
104	CONFIG_BLK_DEV_SR=y
105	CONFIG_CHR_DEV_SG=y
106	CONFIG_SCSI_LOGGING=y
107	CONFIG_ATA=y
108	CONFIG_SATA_AHCI=y
109	CONFIG_SATA_FSL=y
110	CONFIG_SATA_SIL24=y
111	CONFIG_PATA_ALI=y
112	CONFIG_NETDEVICES=y
113	CONFIG_DUMMY=y
114	CONFIG_FS_ENET=y
115	CONFIG_UCC_GETH=y
116	CONFIG_GIANFAR=y
117	CONFIG_E1000E=y
118	CONFIG_AT803X_PHY=y
119	CONFIG_MARVELL_PHY=y
120	CONFIG_DAVICOM_PHY=y
121	CONFIG_CICADA_PHY=y
122	CONFIG_VITESSE_PHY=y
123	CONFIG_FIXED_PHY=y
124	CONFIG_INPUT_FF_MEMLESS=m
125	# CONFIG_INPUT_MOUSEDEV is not set
126	# CONFIG_INPUT_KEYBOARD is not set
127	# CONFIG_INPUT_MOUSE is not set
128	CONFIG_SERIO_LIBPS2=y
129	CONFIG_SERIAL_8250=y
130	CONFIG_SERIAL_8250_CONSOLE=y
131	CONFIG_SERIAL_8250_NR_UARTS=2
132	CONFIG_SERIAL_8250_RUNTIME_UARTS=2
133	CONFIG_SERIAL_8250_MANY_PORTS=y
134	CONFIG_SERIAL_8250_DETECT_IRQ=y
135	CONFIG_SERIAL_8250_RSA=y
136	CONFIG_SERIAL_QE=m
137	CONFIG_NVRAM=y
138	CONFIG_I2C=y
139	CONFIG_I2C_CHARDEV=y
140	CONFIG_I2C_CPM=m
141	CONFIG_I2C_MPC=y
142	CONFIG_SPI=y
143	CONFIG_SPI_FSL_SPI=y
144	CONFIG_SPI_FSL_ESPI=y
145	CONFIG_GPIO_MPC8XXX=y
146	CONFIG_SENSORS_LM90=y
147	CONFIG_FB=y
148	CONFIG_FB_FSL_DIU=y
149	# CONFIG_VGA_CONSOLE is not set
150	CONFIG_FRAMEBUFFER_CONSOLE=y
151	CONFIG_SOUND=y
152	CONFIG_SND=y
153	# CONFIG_SND_SUPPORT_OLD_API is not set
154	# CONFIG_SND_DRIVERS is not set
155	CONFIG_SND_INTEL8X0=y
156	# CONFIG_SND_PPC is not set
157	# CONFIG_SND_USB is not set
158	CONFIG_SND_SOC=y
159	CONFIG_SND_POWERPC_SOC=y
160	CONFIG_HID_A4TECH=y
161	CONFIG_HID_APPLE=y
162	CONFIG_HID_BELKIN=y
163	CONFIG_HID_CHERRY=y
164	CONFIG_HID_CHICONY=y
165	CONFIG_HID_CYPRESS=y
166	CONFIG_HID_EZKEY=y
167	CONFIG_HID_GYRATION=y
168	CONFIG_HID_LOGITECH=y
169	CONFIG_HID_MICROSOFT=y
170	CONFIG_HID_MONTEREY=y
171	CONFIG_HID_PANTHERLORD=y
172	CONFIG_HID_PETALYNX=y
173	CONFIG_HID_SAMSUNG=y
174	CONFIG_HID_SUNPLUS=y
175	CONFIG_USB=y
176	CONFIG_USB_MON=y
177	CONFIG_USB_EHCI_HCD=y
178	CONFIG_USB_EHCI_FSL=y
179	CONFIG_USB_OHCI_HCD=y
180	CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
181	CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
182	CONFIG_USB_STORAGE=y
183	CONFIG_MMC=y
184	CONFIG_MMC_SDHCI=y
185	CONFIG_MMC_SDHCI_PLTFM=y
186	CONFIG_MMC_SDHCI_OF_ESDHC=y
187	CONFIG_EDAC=y
188	CONFIG_EDAC_MM_EDAC=y
189	CONFIG_RTC_CLASS=y
190	CONFIG_RTC_DRV_DS1307=y
191	CONFIG_RTC_DRV_DS1374=y
192	CONFIG_RTC_DRV_DS3232=y
193	CONFIG_RTC_DRV_CMOS=y
194	CONFIG_DMADEVICES=y
195	CONFIG_FSL_DMA=y
196	CONFIG_EXT2_FS=y
197	CONFIG_EXT3_FS=y
198	# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
199	CONFIG_ISO9660_FS=m
200	CONFIG_JOLIET=y
201	CONFIG_ZISOFS=y
202	CONFIG_UDF_FS=m
203	CONFIG_MSDOS_FS=m
204	CONFIG_VFAT_FS=y
205	CONFIG_NTFS_FS=y
206	CONFIG_PROC_KCORE=y
207	CONFIG_TMPFS=y
208	CONFIG_HUGETLBFS=y
209	CONFIG_ADFS_FS=m
210	CONFIG_AFFS_FS=m
211	CONFIG_HFS_FS=m
212	CONFIG_HFSPLUS_FS=m
213	CONFIG_BEFS_FS=m
214	CONFIG_BFS_FS=m
215	CONFIG_EFS_FS=m
216	CONFIG_JFFS2_FS=y
217	CONFIG_JFFS2_FS_DEBUG=1
218	CONFIG_UBIFS_FS=y
219	CONFIG_CRAMFS=y
220	CONFIG_VXFS_FS=m
221	CONFIG_HPFS_FS=m
222	CONFIG_QNX4FS_FS=m
223	CONFIG_SYSV_FS=m
224	CONFIG_UFS_FS=m
225	CONFIG_NFS_FS=y
226	CONFIG_NFS_V4=y
227	CONFIG_ROOT_NFS=y
228	CONFIG_NFSD=y
229	CONFIG_NLS_CODEPAGE_437=y
230	CONFIG_NLS_CODEPAGE_850=y
231	CONFIG_NLS_ISO8859_1=y
232	CONFIG_CRC_T10DIF=y
233	CONFIG_FONTS=y
234	CONFIG_FONT_8x8=y
235	CONFIG_FONT_8x16=y
236	CONFIG_DEBUG_INFO=y
237	CONFIG_DEBUG_FS=y
238	CONFIG_DETECT_HUNG_TASK=y
239	CONFIG_CRYPTO_PCBC=m
240	CONFIG_CRYPTO_SHA256=y
241	CONFIG_CRYPTO_SHA512=y
242	# CONFIG_CRYPTO_ANSI_CPRNG is not set
243	CONFIG_CRYPTO_DEV_FSL_CAAM=y
244	CONFIG_CRYPTO_DEV_TALITOS=y

arch/powerpc/configs/ppc64_defconfig+3−0

@@ -355,3 +355,6 @@ CONFIG_CRYPTO_DEV_NX_ENCRYPT=m · 354 unmodified lines
355	CONFIG_VIRTUALIZATION=y	355	CONFIG_VIRTUALIZATION=y
356	CONFIG_KVM_BOOK3S_64=m	356	CONFIG_KVM_BOOK3S_64=m
357	CONFIG_KVM_BOOK3S_64_HV=m	357	CONFIG_KVM_BOOK3S_64_HV=m
		358	CONFIG_NEW_LEDS=y
		359	CONFIG_LEDS_CLASS=m
		360	CONFIG_LEDS_POWERNV=m

arch/powerpc/configs/pseries_defconfig+5−1

 CONFIG_HVCS=m
 CONFIG_VIRTIO_CONSOLE=m
 CONFIG_IBM_BSR=m
-CONFIG_GEN_RTC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=y
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=1024
 CONFIG_FB=y
 CONFIG_VIRTUALIZATION=y
 CONFIG_KVM_BOOK3S_64=m
 CONFIG_KVM_BOOK3S_64_HV=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_POWERNV=m

arch/powerpc/include/asm/Kbuild+0−1

@@ -6,5 +6,4 @@ generic-y += local64.h · 5 unmodified lines
6	generic-y += mcs_spinlock.h	6	generic-y += mcs_spinlock.h
7	generic-y += preempt.h	7	generic-y += preempt.h
8	generic-y += rwsem.h	8	generic-y += rwsem.h
9	generic-y += trace_clock.h
10	generic-y += vtime.h	9	generic-y += vtime.h

arch/powerpc/include/asm/archrandom.h+14−14

 static inline int arch_get_random_long(unsigned long *v)
 {
-	if (ppc_md.get_random_long)
-		return ppc_md.get_random_long(v);
 	return 0;
 }
 static inline int arch_get_random_int(unsigned int *v)
+{
+	return 0;
+}
+static inline int arch_get_random_seed_long(unsigned long *v)
+{
+	if (ppc_md.get_random_seed)
+		return ppc_md.get_random_seed(v);
+	return 0;
+}
+static inline int arch_get_random_seed_int(unsigned int *v)
 {
 	unsigned long val;
 	int rc;
 }
 static inline int arch_has_random(void)
-{
-	return !!ppc_md.get_random_long;
-}
-static inline int arch_get_random_seed_long(unsigned long *v)
-{
-	return 0;
-}
-static inline int arch_get_random_seed_int(unsigned int *v)
 {
 	return 0;
 }
 static inline int arch_has_random_seed(void)
 {
-	return 0;
+	return !!ppc_md.get_random_seed;
 }
 #endif /* CONFIG_ARCH_RANDOM */
 #ifdef CONFIG_PPC_POWERNV

arch/powerpc/include/asm/cacheflush.h+6−1

 extern void flush_dcache_icache_page(struct page *page);
 #if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
 extern void __flush_dcache_icache_phys(unsigned long physaddr);
-#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
+#else
+static inline void __flush_dcache_icache_phys(unsigned long physaddr)
+{
+	BUG();
+}
+#endif
 extern void flush_dcache_range(unsigned long start, unsigned long stop);
 #ifdef CONFIG_PPC32

arch/powerpc/include/asm/checksum.h+28−9

@@ -19,15 +19,6 @@ · 18 unmodified lines
19	#else	19	#else
20	extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);	20	extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
21		21
22	/*
23	* computes the checksum of the TCP/UDP pseudo-header
24	* returns a 16-bit checksum, already complemented
25	*/
26	extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
27	unsigned short len,
28	unsigned short proto,
29	__wsum sum);
30
31	/*	22	/*
32	* computes the checksum of a memory block at buff, length len,	23	* computes the checksum of a memory block at buff, length len,
33	* and adds in "sum" (32-bit)	24	* and adds in "sum" (32-bit)
@@ -127,6 +118,34 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, · 93 unmodified lines
127	#endif	118	#endif
128	}	119	}
129		120
		121	/*
		122	* computes the checksum of the TCP/UDP pseudo-header
		123	* returns a 16-bit checksum, already complemented
		124	*/
		125	static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
		126	unsigned short len,
		127	unsigned short proto,
		128	__wsum sum)
		129	{
		130	return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
		131	}
		132
		133	#define HAVE_ARCH_CSUM_ADD
		134	static inline __wsum csum_add(__wsum csum, __wsum addend)
		135	{
		136	#ifdef __powerpc64__
		137	u64 res = (__force u64)csum;
		138
		139	res += (__force u64)addend;
		140	return (__force __wsum)((u32)res + (res >> 32));
		141	#else
		142	asm("addc %0,%0,%1;"
		143	"addze %0,%0;"
		144	: "+r" (csum) : "r" (addend));
		145	return csum;
		146	#endif
		147	}
		148
130	#endif	149	#endif
131	#endif /* __KERNEL__ */	150	#endif /* __KERNEL__ */
132	#endif	151	#endif

arch/powerpc/include/asm/compat.h+7−0

@@ -174,6 +174,13 @@ typedef struct compat_siginfo { · 173 unmodified lines
174	int _band; /* POLL_IN, POLL_OUT, POLL_MSG */	174	int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
175	int _fd;	175	int _fd;
176	} _sigpoll;	176	} _sigpoll;
		177
		178	/* SIGSYS */
		179	struct {
		180	unsigned int _call_addr; /* calling insn */
		181	int _syscall; /* triggering system call number */
		182	unsigned int _arch; /* AUDIT_ARCH_* of syscall */
		183	} _sigsys;
177	} _sifields;	184	} _sifields;
178	} compat_siginfo_t;	185	} compat_siginfo_t;
179		186

arch/powerpc/include/asm/device.h+9−6

@@ -10,6 +10,7 @@ struct dma_map_ops; · 9 unmodified lines
10	struct device_node;	10	struct device_node;
11	#ifdef CONFIG_PPC64	11	#ifdef CONFIG_PPC64
12	struct pci_dn;	12	struct pci_dn;
		13	struct iommu_table;
13	#endif	14	#endif
14		15
15	/*	16	/*
@@ -23,13 +24,15 @@ struct dev_archdata { · 7 unmodified lines
23	struct dma_map_ops *dma_ops;	24	struct dma_map_ops *dma_ops;
24		25
25	/*	26	/*
26	* When an iommu is in use, dma_data is used as a ptr to the base of the	27	* These two used to be a union. However, with the hybrid ops we need
27	* iommu_table. Otherwise, it is a simple numerical offset.	28	* both so here we store both a DMA offset for direct mappings and
		29	* an iommu_table for remapped DMA.
28	*/	30	*/
29	union {	31	dma_addr_t dma_offset;
30	dma_addr_t dma_offset;	32
31	void *iommu_table_base;	33	#ifdef CONFIG_PPC64
32	} dma_data;	34	struct iommu_table *iommu_table_base;
		35	#endif
33		36
34	#ifdef CONFIG_IOMMU_API	37	#ifdef CONFIG_IOMMU_API
35	void *iommu_domain;	38	void *iommu_domain;

arch/powerpc/include/asm/dma-mapping.h+7−7

 #define DMA_ERROR_CODE		(~(dma_addr_t)0x0)
 /* Some dma direct funcs must be visible for use in other dma_ops */
-extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
+extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag,
+					 dma_addr_t *dma_handle, gfp_t flag,
+					 struct dma_attrs *attrs);
+extern void __dma_direct_free_coherent(struct device *dev, size_t size,
+				       void *vaddr, dma_addr_t dma_handle,
 				       struct dma_attrs *attrs);
-extern void dma_direct_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle,
-				     struct dma_attrs *attrs);
 extern int dma_direct_mmap_coherent(struct device *dev,
 				    struct vm_area_struct *vma,
 				    void *cpu_addr, dma_addr_t handle,
 static inline dma_addr_t get_dma_offset(struct device *dev)
 {
 	if (dev)
-		return dev->archdata.dma_data.dma_offset;
+		return dev->archdata.dma_offset;
 	return PCI_DRAM_OFFSET;
 }
 static inline void set_dma_offset(struct device *dev, dma_addr_t off)
 {
 	if (dev)
-		dev->archdata.dma_data.dma_offset = off;
+		dev->archdata.dma_offset = off;
 }
 /* this will be removed soon */

arch/powerpc/include/asm/iommu.h+25−6

  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  * Rewrite, cleanup:
  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 struct scatterlist;
-static inline void set_iommu_table_base(struct device *dev, void *base)
+#ifdef CONFIG_PPC64
+static inline void set_iommu_table_base(struct device *dev,
+					struct iommu_table *base)
 {
-	dev->archdata.dma_data.iommu_table_base = base;
+	dev->archdata.iommu_table_base = base;
 }
 static inline void *get_iommu_table_base(struct device *dev)
 {
-	return dev->archdata.dma_data.iommu_table_base;
+	return dev->archdata.iommu_table_base;
 }
+extern int dma_iommu_dma_supported(struct device *dev, u64 mask);
 /* Frees table for an individual device node */
 extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
 }
 #endif /* !CONFIG_IOMMU_API */
+#else
+static inline void *get_iommu_table_base(struct device *dev)
+{
+	return NULL;
+}
+static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
+{
+	return 0;
+}
+#endif /* CONFIG_PPC64 */
 extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
 			    struct scatterlist *sglist, int nelems,
 			    unsigned long mask,

arch/powerpc/include/asm/machdep.h+1−1

@@ -249,7 +249,7 @@ struct machdep_calls { · 248 unmodified lines
249	#endif	249	#endif
250		250
251	#ifdef CONFIG_ARCH_RANDOM	251	#ifdef CONFIG_ARCH_RANDOM
252	int (get_random_long)(unsigned long v);	252	int (get_random_seed)(unsigned long v);
253	#endif	253	#endif
254	};	254	};
255		255

arch/powerpc/include/asm/opal-api.h+123−1

@@ -154,7 +154,10 @@ · 153 unmodified lines
154	#define OPAL_FLASH_WRITE 111	154	#define OPAL_FLASH_WRITE 111
155	#define OPAL_FLASH_ERASE 112	155	#define OPAL_FLASH_ERASE 112
156	#define OPAL_PRD_MSG 113	156	#define OPAL_PRD_MSG 113
157	#define OPAL_LAST 113	157	#define OPAL_LEDS_GET_INDICATOR 114
		158	#define OPAL_LEDS_SET_INDICATOR 115
		159	#define OPAL_CEC_REBOOT2 116
		160	#define OPAL_LAST 116
158		161
159	/* Device tree flags */	162	/* Device tree flags */
160		163
@@ -340,6 +343,18 @@ enum OpalPciResetState { · 179 unmodified lines
340	OPAL_ASSERT_RESET = 1	343	OPAL_ASSERT_RESET = 1
341	};	344	};
342		345
		346	enum OpalSlotLedType {
		347	OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
		348	OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
		349	OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
		350	OPAL_SLOT_LED_TYPE_MAX = 3
		351	};
		352
		353	enum OpalSlotLedState {
		354	OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
		355	OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
		356	};
		357
343	/*	358	/*
344	* Address cycle types for LPC accesses. These also correspond	359	* Address cycle types for LPC accesses. These also correspond
345	* to the content of the first cell of the "reg" property for	360	* to the content of the first cell of the "reg" property for
@@ -438,6 +453,7 @@ struct OpalMemoryErrorData { · 92 unmodified lines
438	/* HMI interrupt event */	453	/* HMI interrupt event */
439	enum OpalHMI_Version {	454	enum OpalHMI_Version {
440	OpalHMIEvt_V1 = 1,	455	OpalHMIEvt_V1 = 1,
		456	OpalHMIEvt_V2 = 2,
441	};	457	};
442		458
443	enum OpalHMI_Severity {	459	enum OpalHMI_Severity {
@@ -468,6 +484,49 @@ enum OpalHMI_ErrType { · 24 unmodified lines
468	OpalHMI_ERROR_CAPP_RECOVERY,	484	OpalHMI_ERROR_CAPP_RECOVERY,
469	};	485	};
470		486
		487	enum OpalHMI_XstopType {
		488	CHECKSTOP_TYPE_UNKNOWN = 0,
		489	CHECKSTOP_TYPE_CORE = 1,
		490	CHECKSTOP_TYPE_NX = 2,
		491	};
		492
		493	enum OpalHMI_CoreXstopReason {
		494	CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
		495	CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
		496	CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
		497	CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
		498	CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
		499	CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
		500	CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
		501	CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
		502	CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
		503	CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
		504	CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
		505	CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
		506	CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
		507	CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
		508	CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
		509	CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
		510	CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
		511	};
		512
		513	enum OpalHMI_NestAccelXstopReason {
		514	NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
		515	NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
		516	NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
		517	NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
		518	NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
		519	NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
		520	NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
		521	NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
		522	NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
		523	NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
		524	NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
		525	NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
		526	NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
		527	NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
		528	};
		529
471	struct OpalHMIEvent {	530	struct OpalHMIEvent {
472	uint8_t version; /* 0x00 */	531	uint8_t version; /* 0x00 */
473	uint8_t severity; /* 0x01 */	532	uint8_t severity; /* 0x01 */
@@ -478,6 +537,23 @@ struct OpalHMIEvent { · 4 unmodified lines
478	__be64 hmer;	537	__be64 hmer;
479	/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */	538	/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
480	__be64 tfmr;	539	__be64 tfmr;
		540
		541	/* version 2 and later */
		542	union {
		543	/*
		544	* checkstop info (Core/NX).
		545	* Valid for OpalHMI_ERROR_MALFUNC_ALERT.
		546	*/
		547	struct {
		548	uint8_t xstop_type; /* enum OpalHMI_XstopType */
		549	uint8_t reserved_1[3];
		550	__be32 xstop_reason;
		551	union {
		552	__be32 pir; /* for CHECKSTOP_TYPE_CORE */
		553	__be32 chip_id; /* for CHECKSTOP_TYPE_NX */
		554	} u;
		555	} xstop_error;
		556	} u;
481	};	557	};
482		558
483	enum {	559	enum {
@@ -768,6 +844,52 @@ struct opal_i2c_request { · 284 unmodified lines
768	__be64 buffer_ra; /* Buffer real address */	844	__be64 buffer_ra; /* Buffer real address */
769	};	845	};
770		846
		847	/*
		848	* EPOW status sharing (OPAL and the host)
		849	*
		850	* The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
		851	* with individual elements being 16 bits wide to fetch the system
		852	* wide EPOW status. Each element in the buffer will contain the
		853	* EPOW status in it's bit representation for a particular EPOW sub
		854	* class as defiend here. So multiple detailed EPOW status bits
		855	* specific for any sub class can be represented in a single buffer
		856	* element as it's bit representation.
		857	*/
		858
		859	/* System EPOW type */
		860	enum OpalSysEpow {
		861	OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
		862	OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
		863	OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
		864	OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
		865	};
		866
		867	/* Power EPOW */
		868	enum OpalSysPower {
		869	OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
		870	OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
		871	OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
		872	OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
		873	};
		874
		875	/* Temperature EPOW */
		876	enum OpalSysTemp {
		877	OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
		878	OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
		879	OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
		880	};
		881
		882	/* Cooling EPOW */
		883	enum OpalSysCooling {
		884	OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
		885	};
		886
		887	/* Argument to OPAL_CEC_REBOOT2() */
		888	enum {
		889	OPAL_REBOOT_NORMAL = 0,
		890	OPAL_REBOOT_PLATFORM_ERROR = 1,
		891	};
		892
771	#endif /* __ASSEMBLY__ */	893	#endif /* __ASSEMBLY__ */
772		894
773	#endif /* __OPAL_API_H */	895	#endif /* __OPAL_API_H */

arch/powerpc/include/asm/opal.h+7−1

 		       uint32_t hour_min);
 int64_t opal_cec_power_down(uint64_t request);
 int64_t opal_cec_reboot(void);
+int64_t opal_cec_reboot2(uint32_t reboot_type, char *diag);
 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
-int64_t opal_get_epow_status(__be64 *status);
+int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
+int64_t opal_get_dpo_status(__be64 *dpo_timeout);
 int64_t opal_set_system_attention_led(uint8_t led_action);
 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 			    __be16 *pci_error_type, __be16 *severity);
 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
 			 struct opal_i2c_request *oreq);
 int64_t opal_prd_msg(struct opal_prd_msg *msg);
+int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
+			  __be64 *led_value, __be64 *max_led_type);
+int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
+			  const u64 led_value, __be64 *max_led_type);
 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
 		uint64_t size, uint64_t token);

arch/powerpc/include/asm/pci-bridge.h+1−0

@@ -42,6 +42,7 @@ struct pci_controller_ops { · 41 unmodified lines
42	#endif	42	#endif
43		43
44	int (dma_set_mask)(struct pci_dev dev, u64 dma_mask);	44	int (dma_set_mask)(struct pci_dev dev, u64 dma_mask);
		45	u64 (dma_get_required_mask)(struct pci_dev dev);
45		46
46	void (shutdown)(struct pci_controller );	47	void (shutdown)(struct pci_controller );
47	};	48	};

arch/powerpc/include/asm/pgtable-ppc64.h+4−4

 #define pte_iterate_hashed_end() } while(0)
-#ifdef CONFIG_PPC_HAS_HASH_64K
+/*
-#define pte_pagesize_index(mm, addr, pte)	get_slice_psize(mm, addr)
+ * We expect this to be called only for user addresses or kernel virtual
-#else
+ * addresses other than the linear mapping.
+ */
 #define pte_pagesize_index(mm, addr, pte)	MMU_PAGE_4K
-#endif
 #endif /* __real_pte */

arch/powerpc/include/asm/pgtable.h+11−0

@@ -169,6 +169,17 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, · 168 unmodified lines
169	* cases, and 32-bit non-hash with 32-bit PTEs.	169	* cases, and 32-bit non-hash with 32-bit PTEs.
170	*/	170	*/
171	*ptep = pte;	171	*ptep = pte;
		172
		173	#ifdef CONFIG_PPC_BOOK3E_64
		174	/*
		175	* With hardware tablewalk, a sync is needed to ensure that
		176	* subsequent accesses see the PTE we just wrote. Unlike userspace
		177	* mappings, we can't tolerate spurious faults, so make sure
		178	* the new PTE will be seen the first time.
		179	*/
		180	if (is_kernel_addr(addr))
		181	mb();
		182	#endif
172	#endif	183	#endif
173	}	184	}
174		185

arch/powerpc/include/asm/ppc-pci.h+1−0

@@ -61,6 +61,7 @@ int rtas_write_config(struct pci_dn *, int where, int size, u32 val); · 60 unmodified lines
61	int rtas_read_config(struct pci_dn , int where, int size, u32 val);	61	int rtas_read_config(struct pci_dn , int where, int size, u32 val);
62	void eeh_pe_state_mark(struct eeh_pe *pe, int state);	62	void eeh_pe_state_mark(struct eeh_pe *pe, int state);
63	void eeh_pe_state_clear(struct eeh_pe *pe, int state);	63	void eeh_pe_state_clear(struct eeh_pe *pe, int state);
		64	void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state);
64	void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);	65	void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);
65		66
66	void eeh_sysfs_add_device(struct pci_dev *pdev);	67	void eeh_sysfs_add_device(struct pci_dev *pdev);

arch/powerpc/include/asm/processor.h+0−1

@@ -264,7 +264,6 @@ struct thread_struct { · 263 unmodified lines
264	u64 tm_tfhar; /* Transaction fail handler addr */	264	u64 tm_tfhar; /* Transaction fail handler addr */
265	u64 tm_texasr; /* Transaction exception & summary */	265	u64 tm_texasr; /* Transaction exception & summary */
266	u64 tm_tfiar; /* Transaction fail instr address reg */	266	u64 tm_tfiar; /* Transaction fail instr address reg */
267	unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */
268	struct pt_regs ckpt_regs; /* Checkpointed registers */	267	struct pt_regs ckpt_regs; /* Checkpointed registers */
269		268
270	unsigned long tm_tar;	269	unsigned long tm_tar;

arch/powerpc/include/asm/pte-common.h+2−1

  * the processor might need it for DMA coherency.
  */
 #define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
-#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
+#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU) || \
+	defined(CONFIG_PPC_E500MC)
 #define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)
 #else
 #define _PAGE_BASE	(_PAGE_BASE_NC)

arch/powerpc/include/asm/reg.h+10−2

 #ifdef CONFIG_PPC_BOOK3S_64
 #define __mtmsrd(v, l)	asm volatile("mtmsrd %0," __stringify(l) \
 				     : : "r" (v) : "memory")
-#define mtmsrd(v)	__mtmsrd((v), 0)
+#define mtmsr(v)	__mtmsrd((v), 0)
-#define mtmsr(v)	mtmsrd(v)
 #else
 #define mtmsr(v)	asm volatile("mtmsr %0" : \
 				     : "r" ((unsigned long)(v)) \
 extern void ppc_save_regs(struct pt_regs *regs);
+static inline void update_power8_hid0(unsigned long hid0)
+{
+	/*
+	 *  The HID0 update on Power8 should at the very least be
+	 *  preceded by a a SYNC instruction followed by an ISYNC
+	 *  instruction
+	 */
+	asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
+}
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_REG_H */

arch/powerpc/include/asm/rtas.h+1−0

@@ -343,6 +343,7 @@ extern void rtas_power_off(void); · 342 unmodified lines
343	extern void rtas_halt(void);	343	extern void rtas_halt(void);
344	extern void rtas_os_term(char *str);	344	extern void rtas_os_term(char *str);
345	extern int rtas_get_sensor(int sensor, int index, int *state);	345	extern int rtas_get_sensor(int sensor, int index, int *state);
		346	extern int rtas_get_sensor_fast(int sensor, int index, int *state);
346	extern int rtas_get_power_level(int powerdomain, int *level);	347	extern int rtas_get_power_level(int powerdomain, int *level);
347	extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);	348	extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
348	extern bool rtas_indicator_present(int token, int *maxindex);	349	extern bool rtas_indicator_present(int token, int *maxindex);

arch/powerpc/include/asm/spu_csa.h+0−6

  */
 struct spu_state {
 	struct spu_lscsa *lscsa;
-#ifdef CONFIG_SPU_FS_64K_LS
-	int		use_big_pages;
-	/* One struct page per 64k page */
-#define SPU_LSCSA_NUM_BIG_PAGES	(sizeof(struct spu_lscsa) / 0x10000)
-	struct page	*lscsa_pages[SPU_LSCSA_NUM_BIG_PAGES];
-#endif
 	struct spu_problem_collapsed prob;
 	struct spu_priv1_collapsed priv1;
 	struct spu_priv2_collapsed priv2;

arch/powerpc/include/asm/syscall.h+33−21

@@ -22,10 +22,15 @@ · 21 unmodified lines
22	extern const unsigned long sys_call_table[];	22	extern const unsigned long sys_call_table[];
23	#endif /* CONFIG_FTRACE_SYSCALLS */	23	#endif /* CONFIG_FTRACE_SYSCALLS */
24		24
25	static inline long syscall_get_nr(struct task_struct *task,	25	static inline int syscall_get_nr(struct task_struct task, struct pt_regs regs)
26	struct pt_regs *regs)
27	{	26	{
28	return TRAP(regs) == 0xc00 ? regs->gpr[0] : -1L;	27	/*
		28	* Note that we are returning an int here. That means 0xffffffff, ie.
		29	* 32-bit negative 1, will be interpreted as -1 on a 64-bit kernel.
		30	* This is important for seccomp so that compat tasks can set r0 = -1
		31	* to reject the syscall.
		32	*/
		33	return TRAP(regs) == 0xc00 ? regs->gpr[0] : -1;
29	}	34	}
30		35
31	static inline void syscall_rollback(struct task_struct *task,	36	static inline void syscall_rollback(struct task_struct *task,
@@ -34,12 +39,6 @@ static inline void syscall_rollback(struct task_struct *task, · 2 unmodified lines
34	regs->gpr[3] = regs->orig_gpr3;	39	regs->gpr[3] = regs->orig_gpr3;
35	}	40	}
36		41
37	static inline long syscall_get_error(struct task_struct *task,
38	struct pt_regs *regs)
39	{
40	return (regs->ccr & 0x10000000) ? -regs->gpr[3] : 0;
41	}
42
43	static inline long syscall_get_return_value(struct task_struct *task,	42	static inline long syscall_get_return_value(struct task_struct *task,
44	struct pt_regs *regs)	43	struct pt_regs *regs)
45	{	44	{
@@ -50,9 +49,15 @@ static inline void syscall_set_return_value(struct task_struct *task, · 4 unmodified lines
50	struct pt_regs *regs,	49	struct pt_regs *regs,
51	int error, long val)	50	int error, long val)
52	{	51	{
		52	/*
		53	* In the general case it's not obvious that we must deal with CCR
		54	* here, as the syscall exit path will also do that for us. However
		55	* there are some places, eg. the signal code, which check ccr to
		56	* decide if the value in r3 is actually an error.
		57	*/
53	if (error) {	58	if (error) {
54	regs->ccr \|= 0x10000000L;	59	regs->ccr \|= 0x10000000L;
55	regs->gpr[3] = -error;	60	regs->gpr[3] = error;
56	} else {	61	} else {
57	regs->ccr &= ~0x10000000L;	62	regs->ccr &= ~0x10000000L;
58	regs->gpr[3] = val;	63	regs->gpr[3] = val;
@@ -64,19 +69,22 @@ static inline void syscall_get_arguments(struct task_struct *task, · 5 unmodified lines
64	unsigned int i, unsigned int n,	69	unsigned int i, unsigned int n,
65	unsigned long *args)	70	unsigned long *args)
66	{	71	{
		72	unsigned long val, mask = -1UL;
		73
67	BUG_ON(i + n > 6);	74	BUG_ON(i + n > 6);
68	#ifdef CONFIG_PPC64	75
69	if (test_tsk_thread_flag(task, TIF_32BIT)) {	76	#ifdef CONFIG_COMPAT
70	/*	77	if (test_tsk_thread_flag(task, TIF_32BIT))
71	* Zero-extend 32-bit argument values. The high bits are	78	mask = 0xffffffff;
72	* garbage ignored by the actual syscall dispatch.
73	*/
74	while (n-- > 0)
75	args[n] = (u32) regs->gpr[3 + i + n];
76	return;
77	}
78	#endif	79	#endif
79	memcpy(args, &regs->gpr[3 + i], n * sizeof(args[0]));	80	while (n--) {
		81	if (n == 0 && i == 0)
		82	val = regs->orig_gpr3;
		83	else
		84	val = regs->gpr[3 + i + n];
		85
		86	args[n] = val & mask;
		87	}
80	}	88	}
81		89
82	static inline void syscall_set_arguments(struct task_struct *task,	90	static inline void syscall_set_arguments(struct task_struct *task,
@@ -86,6 +94,10 @@ static inline void syscall_set_arguments(struct task_struct *task, · 3 unmodified lines
86	{	94	{
87	BUG_ON(i + n > 6);	95	BUG_ON(i + n > 6);
88	memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));	96	memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));
		97
		98	/* Also copy the first argument into orig_gpr3 */
		99	if (i == 0 && n > 0)
		100	regs->orig_gpr3 = args[0];
89	}	101	}
90		102
91	static inline int syscall_get_arch(void)	103	static inline int syscall_get_arch(void)

arch/powerpc/include/asm/trace_clock.h+19−0

@@ -0,0 +1,19 @@
	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2015 Naveen N. Rao, IBM Corporation
	7	*/
	8
	9	#ifndef _ASM_PPC_TRACE_CLOCK_H
	10	#define _ASM_PPC_TRACE_CLOCK_H
	11
	12	#include <linux/compiler.h>
	13	#include <linux/types.h>
	14
	15	extern u64 notrace trace_clock_ppc_tb(void);
	16
	17	#define ARCH_TRACE_CLOCKS { trace_clock_ppc_tb, "ppc-tb", 0 },
	18
	19	#endif /* _ASM_PPC_TRACE_CLOCK_H */

arch/powerpc/include/uapi/asm/Kbuild+1−0

@@ -6,6 +6,7 @@ header-y += bitsperlong.h · 5 unmodified lines
6	header-y += bootx.h	6	header-y += bootx.h
7	header-y += byteorder.h	7	header-y += byteorder.h
8	header-y += cputable.h	8	header-y += cputable.h
		9	header-y += eeh.h
9	header-y += elf.h	10	header-y += elf.h
10	header-y += epapr_hcalls.h	11	header-y += epapr_hcalls.h
11	header-y += errno.h	12	header-y += errno.h

arch/powerpc/include/uapi/asm/errno.h+0−2

@@ -6,6 +6,4 @@ · 5 unmodified lines
6	#undef EDEADLOCK	6	#undef EDEADLOCK
7	#define EDEADLOCK 58 /* File locking deadlock error */	7	#define EDEADLOCK 58 /* File locking deadlock error */
8		8
9	#define _LAST_ERRNO 516
10
11	#endif /* _ASM_POWERPC_ERRNO_H */	9	#endif /* _ASM_POWERPC_ERRNO_H */

arch/powerpc/include/uapi/asm/sigcontext.h+2−2

@@ -28,7 +28,7 @@ struct sigcontext { · 27 unmodified lines
28	/*	28	/*
29	* To maintain compatibility with current implementations the sigcontext is	29	* To maintain compatibility with current implementations the sigcontext is
30	* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)	30	* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
31	* followed by an unstructured (vmx_reserve) field of 69 doublewords. This	31	* followed by an unstructured (vmx_reserve) field of 101 doublewords. This
32	* allows the array of vector registers to be quadword aligned independent of	32	* allows the array of vector registers to be quadword aligned independent of
33	* the alignment of the containing sigcontext or ucontext. It is the	33	* the alignment of the containing sigcontext or ucontext. It is the
34	* responsibility of the code setting the sigcontext to set this pointer to	34	* responsibility of the code setting the sigcontext to set this pointer to
@@ -80,7 +80,7 @@ struct sigcontext { · 45 unmodified lines
80	* registers and vscr/vrsave.	80	* registers and vscr/vrsave.
81	*/	81	*/
82	elf_vrreg_t __user *v_regs;	82	elf_vrreg_t __user *v_regs;
83	long vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];	83	long vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32];
84	#endif	84	#endif
85	};	85	};
86		86

arch/powerpc/kernel/Makefile+1−0

@@ -118,6 +118,7 @@ obj-$(CONFIG_PPC_IO_WORKAROUNDS) += io-workarounds.o · 117 unmodified lines
118	obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o	118	obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
119	obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o	119	obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
120	obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o	120	obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
		121	obj-$(CONFIG_TRACING) += trace_clock.o
121		122
122	ifneq ($(CONFIG_PPC_INDIRECT_PIO),y)	123	ifneq ($(CONFIG_PPC_INDIRECT_PIO),y)
123	obj-y += iomap.o	124	obj-y += iomap.o

arch/powerpc/kernel/asm-offsets.c+0−1

@@ -213,7 +213,6 @@ int main(void) · 212 unmodified lines
213	offsetof(struct tlb_core_data, esel_max));	213	offsetof(struct tlb_core_data, esel_max));
214	DEFINE(TCD_ESEL_FIRST,	214	DEFINE(TCD_ESEL_FIRST,
215	offsetof(struct tlb_core_data, esel_first));	215	offsetof(struct tlb_core_data, esel_first));
216	DEFINE(TCD_LOCK, offsetof(struct tlb_core_data, lock));
217	#endif /* CONFIG_PPC_BOOK3E */	216	#endif /* CONFIG_PPC_BOOK3E */
218		217
219	#ifdef CONFIG_PPC_STD_MMU_64	218	#ifdef CONFIG_PPC_STD_MMU_64

arch/powerpc/kernel/dma-iommu.c+1−1

@@ -73,7 +73,7 @@ static void dma_iommu_unmap_sg(struct device dev, struct scatterlist sglist, · 72 unmodified lines
73	}	73	}
74		74
75	/* We support DMA to/from any memory page via the iommu */	75	/* We support DMA to/from any memory page via the iommu */
76	static int dma_iommu_dma_supported(struct device *dev, u64 mask)	76	int dma_iommu_dma_supported(struct device *dev, u64 mask)
77	{	77	{
78	struct iommu_table *tbl = get_iommu_table_base(dev);	78	struct iommu_table *tbl = get_iommu_table_base(dev);
79		79

arch/powerpc/kernel/dma-swiotlb.c+2−2

@@ -47,8 +47,8 @@ static u64 swiotlb_powerpc_get_required(struct device *dev) · 46 unmodified lines
47	* for everything else.	47	* for everything else.
48	*/	48	*/
49	struct dma_map_ops swiotlb_dma_ops = {	49	struct dma_map_ops swiotlb_dma_ops = {
50	.alloc = dma_direct_alloc_coherent,	50	.alloc = __dma_direct_alloc_coherent,
51	.free = dma_direct_free_coherent,	51	.free = __dma_direct_free_coherent,
52	.mmap = dma_direct_mmap_coherent,	52	.mmap = dma_direct_mmap_coherent,
53	.map_sg = swiotlb_map_sg_attrs,	53	.map_sg = swiotlb_map_sg_attrs,
54	.unmap_sg = swiotlb_unmap_sg_attrs,	54	.unmap_sg = swiotlb_unmap_sg_attrs,

arch/powerpc/kernel/dma.c+100−18

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	#include <asm/bug.h>	16	#include <asm/bug.h>
17	#include <asm/machdep.h>	17	#include <asm/machdep.h>
18	#include <asm/swiotlb.h>	18	#include <asm/swiotlb.h>
		19	#include <asm/iommu.h>
19		20
20	/*	21	/*
21	* Generic direct DMA implementation	22	* Generic direct DMA implementation
@@ -39,9 +40,31 @@ static u64 __maybe_unused get_pfn_limit(struct device *dev) · 17 unmodified lines
39	return pfn;	40	return pfn;
40	}	41	}
41		42
42	void dma_direct_alloc_coherent(struct device dev, size_t size,	43	static int dma_direct_dma_supported(struct device *dev, u64 mask)
43	dma_addr_t *dma_handle, gfp_t flag,	44	{
44	struct dma_attrs *attrs)	45	#ifdef CONFIG_PPC64
		46	u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
		47
		48	/* Limit fits in the mask, we are good */
		49	if (mask >= limit)
		50	return 1;
		51
		52	#ifdef CONFIG_FSL_SOC
		53	/* Freescale gets another chance via ZONE_DMA/ZONE_DMA32, however
		54	* that will have to be refined if/when they support iommus
		55	*/
		56	return 1;
		57	#endif
		58	/* Sorry ... */
		59	return 0;
		60	#else
		61	return 1;
		62	#endif
		63	}
		64
		65	void __dma_direct_alloc_coherent(struct device dev, size_t size,
		66	dma_addr_t *dma_handle, gfp_t flag,
		67	struct dma_attrs *attrs)
45	{	68	{
46	void *ret;	69	void *ret;
47	#ifdef CONFIG_NOT_COHERENT_CACHE	70	#ifdef CONFIG_NOT_COHERENT_CACHE
@@ -96,9 +119,9 @@ void dma_direct_alloc_coherent(struct device dev, size_t size, · 48 unmodified lines
96	#endif	119	#endif
97	}	120	}
98		121
99	void dma_direct_free_coherent(struct device *dev, size_t size,	122	void __dma_direct_free_coherent(struct device *dev, size_t size,
100	void *vaddr, dma_addr_t dma_handle,	123	void *vaddr, dma_addr_t dma_handle,
101	struct dma_attrs *attrs)	124	struct dma_attrs *attrs)
102	{	125	{
103	#ifdef CONFIG_NOT_COHERENT_CACHE	126	#ifdef CONFIG_NOT_COHERENT_CACHE
104	__dma_free_coherent(size, vaddr);	127	__dma_free_coherent(size, vaddr);
@@ -107,6 +130,51 @@ void dma_direct_free_coherent(struct device *dev, size_t size, · 2 unmodified lines
107	#endif	130	#endif
108	}	131	}
109		132
		133	static void dma_direct_alloc_coherent(struct device dev, size_t size,
		134	dma_addr_t *dma_handle, gfp_t flag,
		135	struct dma_attrs *attrs)
		136	{
		137	struct iommu_table *iommu;
		138
		139	/* The coherent mask may be smaller than the real mask, check if
		140	* we can really use the direct ops
		141	*/
		142	if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
		143	return __dma_direct_alloc_coherent(dev, size, dma_handle,
		144	flag, attrs);
		145
		146	/* Ok we can't ... do we have an iommu ? If not, fail */
		147	iommu = get_iommu_table_base(dev);
		148	if (!iommu)
		149	return NULL;
		150
		151	/* Try to use the iommu */
		152	return iommu_alloc_coherent(dev, iommu, size, dma_handle,
		153	dev->coherent_dma_mask, flag,
		154	dev_to_node(dev));
		155	}
		156
		157	static void dma_direct_free_coherent(struct device *dev, size_t size,
		158	void *vaddr, dma_addr_t dma_handle,
		159	struct dma_attrs *attrs)
		160	{
		161	struct iommu_table *iommu;
		162
		163	/* See comments in dma_direct_alloc_coherent() */
		164	if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
		165	return __dma_direct_free_coherent(dev, size, vaddr, dma_handle,
		166	attrs);
		167	/* Maybe we used an iommu ... */
		168	iommu = get_iommu_table_base(dev);
		169
		170	/* If we hit that we should have never allocated in the first
		171	* place so how come we are freeing ?
		172	*/
		173	if (WARN_ON(!iommu))
		174	return;
		175	iommu_free_coherent(iommu, size, vaddr, dma_handle);
		176	}
		177
110	int dma_direct_mmap_coherent(struct device dev, struct vm_area_struct vma,	178	int dma_direct_mmap_coherent(struct device dev, struct vm_area_struct vma,
111	void *cpu_addr, dma_addr_t handle, size_t size,	179	void *cpu_addr, dma_addr_t handle, size_t size,
112	struct dma_attrs *attrs)	180	struct dma_attrs *attrs)
@@ -147,18 +215,6 @@ static void dma_direct_unmap_sg(struct device dev, struct scatterlist sg, · 34 unmodified lines
147	{	215	{
148	}	216	}
149		217
150	static int dma_direct_dma_supported(struct device *dev, u64 mask)
151	{
152	#ifdef CONFIG_PPC64
153	/* Could be improved so platforms can set the limit in case
154	* they have limited DMA windows
155	*/
156	return mask >= get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
157	#else
158	return 1;
159	#endif
160	}
161
162	static u64 dma_direct_get_required_mask(struct device *dev)	218	static u64 dma_direct_get_required_mask(struct device *dev)
163	{	219	{
164	u64 end, mask;	220	u64 end, mask;
@@ -230,6 +286,25 @@ struct dma_map_ops dma_direct_ops = { · 65 unmodified lines
230	};	286	};
231	EXPORT_SYMBOL(dma_direct_ops);	287	EXPORT_SYMBOL(dma_direct_ops);
232		288
		289	int dma_set_coherent_mask(struct device *dev, u64 mask)
		290	{
		291	if (!dma_supported(dev, mask)) {
		292	/*
		293	* We need to special case the direct DMA ops which can
		294	* support a fallback for coherent allocations. There
		295	* is no dma_op->set_coherent_mask() so we have to do
		296	* things the hard way:
		297	*/
		298	if (get_dma_ops(dev) != &dma_direct_ops \|\|
		299	get_iommu_table_base(dev) == NULL \|\|
		300	!dma_iommu_dma_supported(dev, mask))
		301	return -EIO;
		302	}
		303	dev->coherent_dma_mask = mask;
		304	return 0;
		305	}
		306	EXPORT_SYMBOL_GPL(dma_set_coherent_mask);
		307
233	#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)	308	#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
234		309
235	int __dma_set_mask(struct device *dev, u64 dma_mask)	310	int __dma_set_mask(struct device *dev, u64 dma_mask)
@@ -278,6 +353,13 @@ u64 dma_get_required_mask(struct device *dev) · 42 unmodified lines
278	if (ppc_md.dma_get_required_mask)	353	if (ppc_md.dma_get_required_mask)
279	return ppc_md.dma_get_required_mask(dev);	354	return ppc_md.dma_get_required_mask(dev);
280		355
		356	if (dev_is_pci(dev)) {
		357	struct pci_dev *pdev = to_pci_dev(dev);
		358	struct pci_controller *phb = pci_bus_to_host(pdev->bus);
		359	if (phb->controller_ops.dma_get_required_mask)
		360	return phb->controller_ops.dma_get_required_mask(pdev);
		361	}
		362
281	return __dma_get_required_mask(dev);	363	return __dma_get_required_mask(dev);
282	}	364	}
283	EXPORT_SYMBOL_GPL(dma_get_required_mask);	365	EXPORT_SYMBOL_GPL(dma_get_required_mask);

arch/powerpc/kernel/eeh.c+23−8

 	if (!(pe->type & EEH_PE_PHB)) {
 		if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG))
 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+		/*
+		 * The config space of some PCI devices can't be accessed
+		 * when their PEs are in frozen state. Otherwise, fenced
+		 * PHB might be seen. Those PEs are identified with flag
+		 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
+		 * is set automatically when the PE is put to EEH_PE_ISOLATED.
+		 *
+		 * Restoring BARs possibly triggers PCI config access in
+		 * (OPAL) firmware and then causes fenced PHB. If the
+		 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
+		 * pointless to restore BARs and dump config space.
+		 */
 		eeh_ops->configure_bridge(pe);
-		eeh_pe_restore_bars(pe);
+		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
+			eeh_pe_restore_bars(pe);
-		pci_regs_buf[0] = 0;
+			pci_regs_buf[0] = 0;
-		eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
+			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
+		}
 	}
 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
 		break;
 	case pcie_hot_reset:
-		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
+		eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
 		eeh_ops->reset(pe, EEH_RESET_HOT);
 		break;
 	case pcie_warm_reset:
-		eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
+		eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
 		return;
 	}
-	if (eeh_has_flag(EEH_PROBE_MODE_DEV))
-		eeh_ops->probe(pdn, NULL);
 	/*
 	 * The EEH cache might not be removed correctly because of
 	 * unbalanced kref to the device during unplug time, which
 		dev->dev.archdata.edev = NULL;
 	}
+	if (eeh_has_flag(EEH_PROBE_MODE_DEV))
+		eeh_ops->probe(pdn, NULL);
 	edev->pdev = dev;
 	dev->dev.archdata.edev = edev;

arch/powerpc/kernel/eeh_pe.c+22−0

@@ -657,6 +657,28 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state) · 656 unmodified lines
657	eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);	657	eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
658	}	658	}
659		659
		660	/**
		661	* eeh_pe_state_mark_with_cfg - Mark PE state with unblocked config space
		662	* @pe: PE
		663	* @state: PE state to be set
		664	*
		665	* Set specified flag to PE and its child PEs. The PCI config space
		666	* of some PEs is blocked automatically when EEH_PE_ISOLATED is set,
		667	* which isn't needed in some situations. The function allows to set
		668	* the specified flag to indicated PEs without blocking their PCI
		669	* config space.
		670	*/
		671	void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
		672	{
		673	eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
		674	if (!(state & EEH_PE_ISOLATED))
		675	return;
		676
		677	/* Clear EEH_PE_CFG_BLOCKED, which might be set just now */
		678	state = EEH_PE_CFG_BLOCKED;
		679	eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
		680	}
		681
660	/*	682	/*
661	* Some PCI bridges (e.g. PLX bridges) have primary/secondary	683	* Some PCI bridges (e.g. PLX bridges) have primary/secondary
662	* buses assigned explicitly by firmware, and we probably have	684	* buses assigned explicitly by firmware, and we probably have

arch/powerpc/kernel/entry_32.S+6−1

  */
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sys.h>
 #include <linux/threads.h>
 #include <asm/reg.h>
 	SYNC
 	MTMSRD(r10)
 	lwz	r9,TI_FLAGS(r12)
-	li	r8,-_LAST_ERRNO
+	li	r8,-MAX_ERRNO
 	andi.	r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
 	bne-	syscall_exit_work
 	cmplw	0,r3,r8
 	lwz	r7,GPR7(r1)
 	lwz	r8,GPR8(r1)
 	REST_NVGPRS(r1)
+	cmplwi	r0,NR_syscalls
+	/* Return code is already in r3 thanks to do_syscall_trace_enter() */
+	bge-	ret_from_syscall
 	b	syscall_dotrace_cont
 syscall_exit_work:

arch/powerpc/kernel/entry_64.S+20−8

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	*/	19	*/
20		20
21	#include <linux/errno.h>	21	#include <linux/errno.h>
		22	#include <linux/err.h>
22	#include <asm/unistd.h>	23	#include <asm/unistd.h>
23	#include <asm/processor.h>	24	#include <asm/processor.h>
24	#include <asm/page.h>	25	#include <asm/page.h>
@@ -150,8 +151,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) · 125 unmodified lines
150	CURRENT_THREAD_INFO(r11, r1)	151	CURRENT_THREAD_INFO(r11, r1)
151	ld r10,TI_FLAGS(r11)	152	ld r10,TI_FLAGS(r11)
152	andi. r11,r10,_TIF_SYSCALL_DOTRACE	153	andi. r11,r10,_TIF_SYSCALL_DOTRACE
153	bne syscall_dotrace	154	bne syscall_dotrace /* does not return */
154	.Lsyscall_dotrace_cont:
155	cmpldi 0,r0,NR_syscalls	155	cmpldi 0,r0,NR_syscalls
156	bge- syscall_enosys	156	bge- syscall_enosys
157		157
@@ -207,7 +207,7 @@ system_call: /* label this so stack traces look sane */ · 49 unmodified lines
207	#endif /* CONFIG_PPC_BOOK3E */	207	#endif /* CONFIG_PPC_BOOK3E */
208		208
209	ld r9,TI_FLAGS(r12)	209	ld r9,TI_FLAGS(r12)
210	li r11,-_LAST_ERRNO	210	li r11,-MAX_ERRNO
211	andi. r0,r9,(_TIF_SYSCALL_DOTRACE\|_TIF_SINGLESTEP\|_TIF_USER_WORK_MASK\|_TIF_PERSYSCALL_MASK)	211	andi. r0,r9,(_TIF_SYSCALL_DOTRACE\|_TIF_SINGLESTEP\|_TIF_USER_WORK_MASK\|_TIF_PERSYSCALL_MASK)
212	bne- syscall_exit_work	212	bne- syscall_exit_work
213	cmpld r3,r11	213	cmpld r3,r11
@@ -245,22 +245,34 @@ syscall_dotrace: · 31 unmodified lines
245	bl save_nvgprs	245	bl save_nvgprs
246	addi r3,r1,STACK_FRAME_OVERHEAD	246	addi r3,r1,STACK_FRAME_OVERHEAD
247	bl do_syscall_trace_enter	247	bl do_syscall_trace_enter
		248
248	/*	249	/*
249	* Restore argument registers possibly just changed.	250	* We use the return value of do_syscall_trace_enter() as the syscall
250	* We use the return value of do_syscall_trace_enter	251	* number. If the syscall was rejected for any reason do_syscall_trace_enter()
251	* for the call number to look up in the table (r0).	252	* returns an invalid syscall number and the test below against
		253	* NR_syscalls will fail.
252	*/	254	*/
253	mr r0,r3	255	mr r0,r3
		256
		257	/* Restore argument registers just clobbered and/or possibly changed. */
254	ld r3,GPR3(r1)	258	ld r3,GPR3(r1)
255	ld r4,GPR4(r1)	259	ld r4,GPR4(r1)
256	ld r5,GPR5(r1)	260	ld r5,GPR5(r1)
257	ld r6,GPR6(r1)	261	ld r6,GPR6(r1)
258	ld r7,GPR7(r1)	262	ld r7,GPR7(r1)
259	ld r8,GPR8(r1)	263	ld r8,GPR8(r1)
		264
		265	/* Repopulate r9 and r10 for the system_call path */
260	addi r9,r1,STACK_FRAME_OVERHEAD	266	addi r9,r1,STACK_FRAME_OVERHEAD
261	CURRENT_THREAD_INFO(r10, r1)	267	CURRENT_THREAD_INFO(r10, r1)
262	ld r10,TI_FLAGS(r10)	268	ld r10,TI_FLAGS(r10)
263	b .Lsyscall_dotrace_cont	269
		270	cmpldi r0,NR_syscalls
		271	blt+ system_call
		272
		273	/* Return code is already in r3 thanks to do_syscall_trace_enter() */
		274	b .Lsyscall_exit
		275
264		276
265	syscall_enosys:	277	syscall_enosys:
266	li r3,-ENOSYS	278	li r3,-ENOSYS
@@ -277,7 +289,7 @@ syscall_exit_work: · 10 unmodified lines
277	beq+ 0f	289	beq+ 0f
278	REST_NVGPRS(r1)	290	REST_NVGPRS(r1)
279	b 2f	291	b 2f
280	0: cmpld r3,r11 /* r10 is -LAST_ERRNO */	292	0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
281	blt+ 1f	293	blt+ 1f
282	andi. r0,r9,_TIF_NOERROR	294	andi. r0,r9,_TIF_NOERROR
283	bne- 1f	295	bne- 1f

arch/powerpc/kernel/exceptions-64e.S+8−5

 	sync
 	isync
-/* The mapping only needs to be cache-coherent on SMP */
+/*
-#ifdef CONFIG_SMP
+ * The mapping only needs to be cache-coherent on SMP, except on
-#define M_IF_SMP	MAS2_M
+ * Freescale e500mc derivatives where it's also needed for coherent DMA.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
+#define M_IF_NEEDED	MAS2_M
 #else
-#define M_IF_SMP	0
+#define M_IF_NEEDED	0
 #endif
 /* 6. Setup KERNELBASE mapping in TLB[0]
 	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
 	mtspr	SPRN_MAS1,r6
-	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
+	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED)
 	mtspr	SPRN_MAS2,r6
 	rlwinm	r5,r5,0,0,25

arch/powerpc/kernel/fsl_booke_entry_mapping.S+9−6

 	tlbivax 0,r9
 	TLBSYNC
-/* The mapping only needs to be cache-coherent on SMP */
+/*
-#ifdef CONFIG_SMP
+ * The mapping only needs to be cache-coherent on SMP, except on
-#define M_IF_SMP	MAS2_M
+ * Freescale e500mc derivatives where it's also needed for coherent DMA.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
+#define M_IF_NEEDED	MAS2_M
 #else
-#define M_IF_SMP	0
+#define M_IF_NEEDED	0
 #endif
 #if defined(ENTRY_MAPPING_BOOT_SETUP)
 	lis	r6,(MAS1_VALID|MAS1_IPROT)@h
 	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
 	mtspr	SPRN_MAS1,r6
-	lis	r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
+	lis	r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h
-	ori	r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
+	ori	r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l
 	mtspr	SPRN_MAS2,r6
 	mtspr	SPRN_MAS3,r8
 	tlbwe

arch/powerpc/kernel/kvm.c+0−1

@@ -649,7 +649,6 @@ static void kvm_check_ins(u32 *inst, u32 features) · 648 unmodified lines
649	kvm_patch_ins_mtsrin(inst, inst_rt, inst_rb);	649	kvm_patch_ins_mtsrin(inst, inst_rt, inst_rb);
650	}	650	}
651	break;	651	break;
652	break;
653	#endif	652	#endif
654	}	653	}
655		654

arch/powerpc/kernel/misc_64.S+11−2

@@ -475,9 +475,18 @@ _GLOBAL(kexec_wait) · 474 unmodified lines
475	#ifdef CONFIG_KEXEC /* use no memory without kexec */	475	#ifdef CONFIG_KEXEC /* use no memory without kexec */
476	lwz r4,0(r5)	476	lwz r4,0(r5)
477	cmpwi 0,r4,0	477	cmpwi 0,r4,0
478	bnea 0x60	478	beq 99b
		479	#ifdef CONFIG_PPC_BOOK3S_64
		480	li r10,0x60
		481	mfmsr r11
		482	clrrdi r11,r11,1 /* Clear MSR_LE */
		483	mtsrr0 r10
		484	mtsrr1 r11
		485	rfid
		486	#else
		487	ba 0x60
		488	#endif
479	#endif	489	#endif
480	b 99b
481		490
482	/* this can be in text because we won't change it until we are	491	/* this can be in text because we won't change it until we are
483	* running in real anyways	492	* running in real anyways

arch/powerpc/kernel/nvram_64.c+5−5

 			time->tv_sec = be64_to_cpu(oops_hdr->timestamp);
 			time->tv_nsec = 0;
 		}
-		*buf = kmalloc(length, GFP_KERNEL);
+		*buf = kmemdup(buff + hdr_size, length, GFP_KERNEL);
 		if (*buf == NULL)
 			return -ENOMEM;
-		memcpy(*buf, buff + hdr_size, length);
 		kfree(buff);
 		if (err_type == ERR_TYPE_KERNEL_PANIC_GZ)
 	spin_lock_init(&nvram_pstore_info.buf_lock);
 	rc = pstore_register(&nvram_pstore_info);
-	if (rc != 0)
+	if (rc && (rc != -EPERM))
-		pr_err("nvram: pstore_register() failed, defaults to "
+		/* Print error only when pstore.backend == nvram */
-				"kmsg_dump; returned %d\n", rc);
+		pr_err("nvram: pstore_register() failed, returned %d. "
+				"Defaults to kmsg_dump\n", rc);
 	return rc;
 }

arch/powerpc/kernel/pci-common.c+18−54

 		    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
 			/* Only print message if not re-assigning */
 			if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
-				pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
+				pr_debug("PCI:%s Resource %d %pR is unassigned\n",
-					 "is unassigned\n",
+					 pci_name(dev), i, res);
-					 pci_name(dev), i,
-					 (unsigned long long)res->start,
-					 (unsigned long long)res->end,
-					 (unsigned int)res->flags);
 			res->end -= res->start;
 			res->start = 0;
 			res->flags |= IORESOURCE_UNSET;
 			continue;
 		}
-		pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
+		pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
-			 pci_name(dev), i,
-			 (unsigned long long)res->start,\
-			 (unsigned long long)res->end,
-			 (unsigned int)res->flags);
 	}
 	/* Call machine specific resource fixup */
 			continue;
 		}
-		pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
+		pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
-			 pci_name(dev), i,
-			 (unsigned long long)res->start,\
-			 (unsigned long long)res->end,
-			 (unsigned int)res->flags);
 		/* Try to detect uninitialized P2P bridge resources,
 		 * and clear them out so they get re-assigned later
 	*pp = NULL;
 	for (p = res->child; p != NULL; p = p->sibling) {
 		p->parent = res;
-		pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
+		pr_debug("PCI: Reparented %s %pR under %s\n",
-			 p->name,
+			 p->name, p, res->name);
-			 (unsigned long long)p->start,
-			 (unsigned long long)p->end, res->name);
 	}
 	return 0;
 }
 			}
 		}
-		pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
+		pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
-			 "[0x%x], parent %p (%s)\n",
+			 bus->self ? pci_name(bus->self) : "PHB", bus->number,
-			 bus->self ? pci_name(bus->self) : "PHB",
+			 i, res, pr, (pr && pr->name) ? pr->name : "nil");
-			 bus->number, i,
-			 (unsigned long long)res->start,
-			 (unsigned long long)res->end,
-			 (unsigned int)res->flags,
-			 pr, (pr && pr->name) ? pr->name : "nil");
 		if (pr && !(pr->flags & IORESOURCE_UNSET)) {
 			struct pci_dev *dev = bus->self;
 {
 	struct resource *pr, *r = &dev->resource[idx];
-	pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
+	pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
-		 pci_name(dev), idx,
+		 pci_name(dev), idx, r);
-		 (unsigned long long)r->start,
-		 (unsigned long long)r->end,
-		 (unsigned int)r->flags);
 	pr = pci_find_parent_resource(dev, r);
 	if (!pr || (pr->flags & IORESOURCE_UNSET) ||
 		printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
 		       " of device %s, will remap\n", idx, pci_name(dev));
 		if (pr)
-			pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
+			pr_debug("PCI:  parent is %p: %pR\n", pr, pr);
-				 pr,
-				 (unsigned long long)pr->start,
-				 (unsigned long long)pr->end,
-				 (unsigned int)pr->flags);
 		/* We'll assign a new address later */
 		r->flags |= IORESOURCE_UNSET;
 		r->end -= r->start;
 			if (r->parent || !r->start || !r->flags)
 				continue;
-			pr_debug("PCI: Claiming %s: "
+			pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
-				 "Resource %d: %016llx..%016llx [%x]\n",
+				 pci_name(dev), i, r);
-				 pci_name(dev), i,
-				 (unsigned long long)r->start,
-				 (unsigned long long)r->end,
-				 (unsigned int)r->flags);
 			if (pci_claim_resource(dev, i) == 0)
 				continue;
 	} else {
 		offset = pcibios_io_space_offset(hose);
-		pr_debug("PCI: PHB IO resource    = %08llx-%08llx [%lx] off 0x%08llx\n",
+		pr_debug("PCI: PHB IO resource    = %pR off 0x%08llx\n",
-			 (unsigned long long)res->start,
+			 res, (unsigned long long)offset);
-			 (unsigned long long)res->end,
-			 (unsigned long)res->flags,
-			 (unsigned long long)offset);
 		pci_add_resource_offset(resources, res, offset);
 	}
 		offset = hose->mem_offset[i];
-		pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
+		pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
-			 (unsigned long long)res->start,
+			 res, (unsigned long long)offset);
-			 (unsigned long long)res->end,
-			 (unsigned long)res->flags,
-			 (unsigned long long)offset);
 		pci_add_resource_offset(resources, res, offset);
 	}

arch/powerpc/kernel/process.c+7−7

@@ -86,7 +86,7 @@ void giveup_fpu_maybe_transactional(struct task_struct *tsk) · 85 unmodified lines
86	if (tsk == current && tsk->thread.regs &&	86	if (tsk == current && tsk->thread.regs &&
87	MSR_TM_ACTIVE(tsk->thread.regs->msr) &&	87	MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
88	!test_thread_flag(TIF_RESTORE_TM)) {	88	!test_thread_flag(TIF_RESTORE_TM)) {
89	tsk->thread.tm_orig_msr = tsk->thread.regs->msr;	89	tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
90	set_thread_flag(TIF_RESTORE_TM);	90	set_thread_flag(TIF_RESTORE_TM);
91	}	91	}
92		92
@@ -104,7 +104,7 @@ void giveup_altivec_maybe_transactional(struct task_struct *tsk) · 11 unmodified lines
104	if (tsk == current && tsk->thread.regs &&	104	if (tsk == current && tsk->thread.regs &&
105	MSR_TM_ACTIVE(tsk->thread.regs->msr) &&	105	MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
106	!test_thread_flag(TIF_RESTORE_TM)) {	106	!test_thread_flag(TIF_RESTORE_TM)) {
107	tsk->thread.tm_orig_msr = tsk->thread.regs->msr;	107	tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
108	set_thread_flag(TIF_RESTORE_TM);	108	set_thread_flag(TIF_RESTORE_TM);
109	}	109	}
110		110
@@ -540,7 +540,7 @@ static void tm_reclaim_thread(struct thread_struct *thr, · 429 unmodified lines
540	* the thread will no longer be transactional.	540	* the thread will no longer be transactional.
541	*/	541	*/
542	if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {	542	if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
543	msr_diff = thr->tm_orig_msr & ~thr->regs->msr;	543	msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
544	if (msr_diff & MSR_FP)	544	if (msr_diff & MSR_FP)
545	memcpy(&thr->transact_fp, &thr->fp_state,	545	memcpy(&thr->transact_fp, &thr->fp_state,
546	sizeof(struct thread_fp_state));	546	sizeof(struct thread_fp_state));
@@ -591,10 +591,10 @@ static inline void tm_reclaim_task(struct task_struct *tsk) · 44 unmodified lines
591	/* Stash the original thread MSR, as giveup_fpu et al will	591	/* Stash the original thread MSR, as giveup_fpu et al will
592	* modify it. We hold onto it to see whether the task used	592	* modify it. We hold onto it to see whether the task used
593	* FP & vector regs. If the TIF_RESTORE_TM flag is set,	593	* FP & vector regs. If the TIF_RESTORE_TM flag is set,
594	* tm_orig_msr is already set.	594	* ckpt_regs.msr is already set.
595	*/	595	*/
596	if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))	596	if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
597	thr->tm_orig_msr = thr->regs->msr;	597	thr->ckpt_regs.msr = thr->regs->msr;
598		598
599	TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "	599	TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
600	"ccr=%lx, msr=%lx, trap=%lx)\n",	600	"ccr=%lx, msr=%lx, trap=%lx)\n",
@@ -663,7 +663,7 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new) · 62 unmodified lines
663	tm_restore_sprs(&new->thread);	663	tm_restore_sprs(&new->thread);
664	return;	664	return;
665	}	665	}
666	msr = new->thread.tm_orig_msr;	666	msr = new->thread.ckpt_regs.msr;
667	/* Recheckpoint to restore original checkpointed register state. */	667	/* Recheckpoint to restore original checkpointed register state. */
668	TM_DEBUG("*** tm_recheckpoint of pid %d "	668	TM_DEBUG("*** tm_recheckpoint of pid %d "
669	"(new->msr 0x%lx, new->origmsr 0x%lx)\n",	669	"(new->msr 0x%lx, new->origmsr 0x%lx)\n",
@@ -723,7 +723,7 @@ void restore_tm_state(struct pt_regs *regs) · 53 unmodified lines
723	if (!MSR_TM_ACTIVE(regs->msr))	723	if (!MSR_TM_ACTIVE(regs->msr))
724	return;	724	return;
725		725
726	msr_diff = current->thread.tm_orig_msr & ~regs->msr;	726	msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
727	msr_diff &= MSR_FP \| MSR_VEC \| MSR_VSX;	727	msr_diff &= MSR_FP \| MSR_VEC \| MSR_VSX;
728	if (msr_diff & MSR_FP) {	728	if (msr_diff & MSR_FP) {
729	fp_enable();	729	fp_enable();

arch/powerpc/kernel/prom.c+11−14

@@ -218,22 +218,18 @@ static void __init check_cpu_pa_features(unsigned long node) · 217 unmodified lines
218	}	218	}
219		219
220	#ifdef CONFIG_PPC_STD_MMU_64	220	#ifdef CONFIG_PPC_STD_MMU_64
221	static void __init check_cpu_slb_size(unsigned long node)	221	static void __init init_mmu_slb_size(unsigned long node)
222	{	222	{
223	const __be32 *slb_size_ptr;	223	const __be32 *slb_size_ptr;
224		224
225	slb_size_ptr = of_get_flat_dt_prop(node, "slb-size", NULL);	225	slb_size_ptr = of_get_flat_dt_prop(node, "slb-size", NULL) ? :
226	if (slb_size_ptr != NULL) {	226	of_get_flat_dt_prop(node, "ibm,slb-size", NULL);
227	mmu_slb_size = be32_to_cpup(slb_size_ptr);	227
228	return;	228	if (slb_size_ptr)
229	}
230	slb_size_ptr = of_get_flat_dt_prop(node, "ibm,slb-size", NULL);
231	if (slb_size_ptr != NULL) {
232	mmu_slb_size = be32_to_cpup(slb_size_ptr);	229	mmu_slb_size = be32_to_cpup(slb_size_ptr);
233	}
234	}	230	}
235	#else	231	#else
236	#define check_cpu_slb_size(node) do { } while(0)	232	#define init_mmu_slb_size(node) do { } while(0)
237	#endif	233	#endif
238		234
239	static struct feature_property {	235	static struct feature_property {
@@ -380,7 +376,7 @@ static int __init early_init_dt_scan_cpus(unsigned long node, · 140 unmodified lines
380		376
381	check_cpu_feature_properties(node);	377	check_cpu_feature_properties(node);
382	check_cpu_pa_features(node);	378	check_cpu_pa_features(node);
383	check_cpu_slb_size(node);	379	init_mmu_slb_size(node);
384		380
385	#ifdef CONFIG_PPC64	381	#ifdef CONFIG_PPC64
386	if (nthreads > 1)	382	if (nthreads > 1)
@@ -476,9 +472,10 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node) · 89 unmodified lines
476	flags = of_read_number(&dm[3], 1);	472	flags = of_read_number(&dm[3], 1);
477	/* skip DRC index, pad, assoc. list index, flags */	473	/* skip DRC index, pad, assoc. list index, flags */
478	dm += 4;	474	dm += 4;
479	/* skip this block if the reserved bit is set in flags (0x80)	475	/* skip this block if the reserved bit is set in flags
480	or if the block is not assigned to this partition (0x8) */	476	or if the block is not assigned to this partition */
481	if ((flags & 0x80) \|\| !(flags & 0x8))	477	if ((flags & DRCONF_MEM_RESERVED) \|\|
		478	!(flags & DRCONF_MEM_ASSIGNED))
482	continue;	479	continue;
483	size = memblock_size;	480	size = memblock_size;
484	rngs = 1;	481	rngs = 1;

arch/powerpc/kernel/prom_init.c+17−8

 #define W(x)	((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
 		((x) >> 8) & 0xff, (x) & 0xff
+/* Firmware expects the value to be n - 1, where n is the # of vectors */
+#define NUM_VECTORS(n)		((n) - 1)
+/*
+ * Firmware expects 1 + n - 2, where n is the length of the option vector in
+ * bytes. The 1 accounts for the length byte itself, the - 2 .. ?
+ */
+#define VECTOR_LENGTH(n)	(1 + (n) - 2)
 unsigned char ibm_architecture_vec[] = {
 	W(0xfffe0000), W(0x003a0000),	/* POWER5/POWER5+ */
 	W(0xffff0000), W(0x003e0000),	/* POWER6 */
 	W(0xffffffff), W(0x0f000003),	/* all 2.06-compliant */
 	W(0xffffffff), W(0x0f000002),	/* all 2.05-compliant */
 	W(0xfffffffe), W(0x0f000001),	/* all 2.04-compliant and earlier */
-	6 - 1,				/* 6 option vectors */
+	NUM_VECTORS(6),			/* 6 option vectors */
 	/* option vector 1: processor architectures supported */
-	3 - 2,				/* length */
+	VECTOR_LENGTH(2),		/* length */
 	0,				/* don't ignore, don't halt */
 	OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
 	OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
 	/* option vector 2: Open Firmware options supported */
-	34 - 2,				/* length */
+	VECTOR_LENGTH(33),		/* length */
 	OV2_REAL_MODE,
 	0, 0,
 	W(0xffffffff),			/* real_base */
 	48,				/* max log_2(hash table size) */
 	/* option vector 3: processor options supported */
-	3 - 2,				/* length */
+	VECTOR_LENGTH(2),		/* length */
 	0,				/* don't ignore, don't halt */
 	OV3_FP | OV3_VMX | OV3_DFP,
 	/* option vector 4: IBM PAPR implementation */
-	3 - 2,				/* length */
+	VECTOR_LENGTH(2),		/* length */
 	0,				/* don't halt */
 	OV4_MIN_ENT_CAP,		/* minimum VP entitled capacity */
 	/* option vector 5: PAPR/OF options */
-	19 - 2,				/* length */
+	VECTOR_LENGTH(18),		/* length */
 	0,				/* don't ignore, don't halt */
 	OV5_FEAT(OV5_LPAR) | OV5_FEAT(OV5_SPLPAR) | OV5_FEAT(OV5_LARGE_PAGES) |
 	OV5_FEAT(OV5_DRCONF_MEMORY) | OV5_FEAT(OV5_DONATE_DEDICATE_CPU) |
 	OV5_FEAT(OV5_PFO_HW_RNG) | OV5_FEAT(OV5_PFO_HW_ENCR) |
 	OV5_FEAT(OV5_PFO_HW_842),
 	OV5_FEAT(OV5_SUB_PROCESSORS),
 	/* option vector 6: IBM PAPR hints */
-	4 - 2,				/* length */
+	VECTOR_LENGTH(3),		/* length */
 	0,
 	0,
 	OV6_LINUX,
 };
 /* Old method - ELF header with PT_NOTE sections only works on BE */

arch/powerpc/kernel/ptrace.c+77−12

@@ -1762,26 +1762,81 @@ long arch_ptrace(struct task_struct *child, long request, · 1761 unmodified lines
1762	return ret;	1762	return ret;
1763	}	1763	}
1764		1764
1765	/*	1765	#ifdef CONFIG_SECCOMP
1766	* We must return the syscall number to actually look up in the table.	1766	static int do_seccomp(struct pt_regs *regs)
1767	* This can be -1L to skip running any syscall at all.	1767	{
		1768	if (!test_thread_flag(TIF_SECCOMP))
		1769	return 0;
		1770
		1771	/*
		1772	* The ABI we present to seccomp tracers is that r3 contains
		1773	* the syscall return value and orig_gpr3 contains the first
		1774	* syscall parameter. This is different to the ptrace ABI where
		1775	* both r3 and orig_gpr3 contain the first syscall parameter.
		1776	*/
		1777	regs->gpr[3] = -ENOSYS;
		1778
		1779	/*
		1780	* We use the __ version here because we have already checked
		1781	* TIF_SECCOMP. If this fails, there is nothing left to do, we
		1782	* have already loaded -ENOSYS into r3, or seccomp has put
		1783	* something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
		1784	*/
		1785	if (__secure_computing())
		1786	return -1;
		1787
		1788	/*
		1789	* The syscall was allowed by seccomp, restore the register
		1790	* state to what ptrace and audit expect.
		1791	* Note that we use orig_gpr3, which means a seccomp tracer can
		1792	* modify the first syscall parameter (in orig_gpr3) and also
		1793	* allow the syscall to proceed.
		1794	*/
		1795	regs->gpr[3] = regs->orig_gpr3;
		1796
		1797	return 0;
		1798	}
		1799	#else
		1800	static inline int do_seccomp(struct pt_regs *regs) { return 0; }
		1801	#endif /* CONFIG_SECCOMP */
		1802
		1803	/**
		1804	* do_syscall_trace_enter() - Do syscall tracing on kernel entry.
		1805	* @regs: the pt_regs of the task to trace (current)
		1806	*
		1807	* Performs various types of tracing on syscall entry. This includes seccomp,
		1808	* ptrace, syscall tracepoints and audit.
		1809	*
		1810	* The pt_regs are potentially visible to userspace via ptrace, so their
		1811	* contents is ABI.
		1812	*
		1813	* One or more of the tracers may modify the contents of pt_regs, in particular
		1814	* to modify arguments or even the syscall number itself.
		1815	*
		1816	* It's also possible that a tracer can choose to reject the system call. In
		1817	* that case this function will return an illegal syscall number, and will put
		1818	* an appropriate return value in regs->r3.
		1819	*
		1820	* Return: the (possibly changed) syscall number.
1768	*/	1821	*/
1769	long do_syscall_trace_enter(struct pt_regs *regs)	1822	long do_syscall_trace_enter(struct pt_regs *regs)
1770	{	1823	{
1771	long ret = 0;	1824	bool abort = false;
1772		1825
1773	user_exit();	1826	user_exit();
1774		1827
1775	secure_computing_strict(regs->gpr[0]);	1828	if (do_seccomp(regs))
		1829	return -1;
1776		1830
1777	if (test_thread_flag(TIF_SYSCALL_TRACE) &&	1831	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
1778	tracehook_report_syscall_entry(regs))
1779	/*	1832	/*
1780	* Tracing decided this syscall should not happen.	1833	* The tracer may decide to abort the syscall, if so tracehook
1781	* We'll return a bogus call number to get an ENOSYS	1834	* will return !0. Note that the tracer may also just change
1782	* error, but leave the original number in regs->gpr[0].	1835	* regs->gpr[0] to an invalid syscall number, that is handled
		1836	* below on the exit path.
1783	*/	1837	*/
1784	ret = -1L;	1838	abort = tracehook_report_syscall_entry(regs) != 0;
		1839	}
1785		1840
1786	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))	1841	if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1787	trace_sys_enter(regs, regs->gpr[0]);	1842	trace_sys_enter(regs, regs->gpr[0]);
@@ -1798,7 +1853,17 @@ long do_syscall_trace_enter(struct pt_regs *regs) · 10 unmodified lines
1798	regs->gpr[5] & 0xffffffff,	1853	regs->gpr[5] & 0xffffffff,
1799	regs->gpr[6] & 0xffffffff);	1854	regs->gpr[6] & 0xffffffff);
1800		1855
1801	return ret ?: regs->gpr[0];	1856	if (abort \|\| regs->gpr[0] >= NR_syscalls) {
		1857	/*
		1858	* If we are aborting explicitly, or if the syscall number is
		1859	* now invalid, set the return value to -ENOSYS.
		1860	*/
		1861	regs->gpr[3] = -ENOSYS;
		1862	return -1;
		1863	}
		1864
		1865	/* Return the possibly modified but valid syscall number */
		1866	return regs->gpr[0];
1802	}	1867	}
1803		1868
1804	void do_syscall_trace_leave(struct pt_regs *regs)	1869	void do_syscall_trace_leave(struct pt_regs *regs)

arch/powerpc/kernel/rtas.c+22−3

 	if (status == RTAS_BUSY) {
 		ms = 1;
-	} else if (status >= 9900 && status <= 9905) {
+	} else if (status >= RTAS_EXTENDED_DELAY_MIN &&
-		order = status - 9900;
+		   status <= RTAS_EXTENDED_DELAY_MAX) {
+		order = status - RTAS_EXTENDED_DELAY_MIN;
 		for (ms = 1; order > 0; order--)
 			ms *= 10;
 	}
 }
 EXPORT_SYMBOL(rtas_get_sensor);
+int rtas_get_sensor_fast(int sensor, int index, int *state)
+{
+	int token = rtas_token("get-sensor-state");
+	int rc;
+	if (token == RTAS_UNKNOWN_SERVICE)
+		return -ENOENT;
+	rc = rtas_call(token, 2, 2, state, sensor, index);
+	WARN_ON(rc == RTAS_BUSY || (rc >= RTAS_EXTENDED_DELAY_MIN &&
+				    rc <= RTAS_EXTENDED_DELAY_MAX));
+	if (rc < 0)
+		return rtas_error_rc(rc);
+	return rc;
+}
 bool rtas_indicator_present(int token, int *maxindex)
 {
 	int proplen, count, i;
 	rc = rtas_call(token, 3, 1, NULL, indicator, index, new_value);
-	WARN_ON(rc == -2 || (rc >= 9900 && rc <= 9905));
+	WARN_ON(rc == RTAS_BUSY || (rc >= RTAS_EXTENDED_DELAY_MIN &&
+				    rc <= RTAS_EXTENDED_DELAY_MAX));
 	if (rc < 0)
 		return rtas_error_rc(rc);

arch/powerpc/kernel/signal_32.c+5−0

 		err |= __put_user(s->si_overrun, &d->si_overrun);
 		err |= __put_user(s->si_int, &d->si_int);
 		break;
+	case __SI_SYS >> 16:
+		err |= __put_user(ptr_to_compat(s->si_call_addr), &d->si_call_addr);
+		err |= __put_user(s->si_syscall, &d->si_syscall);
+		err |= __put_user(s->si_arch, &d->si_arch);
+		break;
 	case __SI_RT >> 16: /* This is not generated by the kernel as of now.  */
 	case __SI_MESGQ >> 16:
 		err |= __put_user(s->si_int, &d->si_int);

arch/powerpc/kernel/signal_64.c+16−5

 static const char fmt64[] = KERN_INFO \
 	"%s[%d]: bad frame in %s: %016lx nip %016lx lr %016lx\n";
+/*
+ * This computes a quad word aligned pointer inside the vmx_reserve array
+ * element. For historical reasons sigcontext might not be quad word aligned,
+ * but the location we write the VMX regs to must be. See the comment in
+ * sigcontext for more detail.
+ */
+#ifdef CONFIG_ALTIVEC
+static elf_vrreg_t __user *sigcontext_vmx_regs(struct sigcontext __user *sc)
+{
+	return (elf_vrreg_t __user *) (((unsigned long)sc->vmx_reserve + 15) & ~0xful);
+}
+#endif
 /*
  * Set up the sigcontext for the signal frame.
  */
 	 * v_regs pointer or not
 	 */
 #ifdef CONFIG_ALTIVEC
-	elf_vrreg_t __user *v_regs = (elf_vrreg_t __user *)(((unsigned long)sc->vmx_reserve + 15) & ~0xful);
+	elf_vrreg_t __user *v_regs = sigcontext_vmx_regs(sc);
 #endif
 	unsigned long msr = regs->msr;
 	long err = 0;
 	 * v_regs pointer or not.
 	 */
 #ifdef CONFIG_ALTIVEC
-	elf_vrreg_t __user *v_regs = (elf_vrreg_t __user *)
+	elf_vrreg_t __user *v_regs = sigcontext_vmx_regs(sc);
-		(((unsigned long)sc->vmx_reserve + 15) & ~0xful);
+	elf_vrreg_t __user *tm_v_regs = sigcontext_vmx_regs(tm_sc);
-	elf_vrreg_t __user *tm_v_regs = (elf_vrreg_t __user *)
-		(((unsigned long)tm_sc->vmx_reserve + 15) & ~0xful);
 #endif
 	unsigned long msr = regs->msr;
 	long err = 0;

arch/powerpc/kernel/trace_clock.c+15−0

@@ -0,0 +1,15 @@
	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2015 Naveen N. Rao, IBM Corporation
	7	*/
	8
	9	#include <asm/trace_clock.h>
	10	#include <asm/time.h>
	11
	12	u64 notrace trace_clock_ppc_tb(void)
	13	{
	14	return get_tb();
	15	}

arch/powerpc/lib/checksum_32.S+0−16

@@ -40,22 +40,6 @@ _GLOBAL(ip_fast_csum) · 39 unmodified lines
40	srwi r3,r3,16	40	srwi r3,r3,16
41	blr	41	blr
42		42
43	/*
44	* Compute checksum of TCP or UDP pseudo-header:
45	* csum_tcpudp_magic(saddr, daddr, len, proto, sum)
46	*/
47	_GLOBAL(csum_tcpudp_magic)
48	rlwimi r5,r6,16,0,15 /* put proto in upper half of len */
49	addc r0,r3,r4 /* add 4 32-bit words together */
50	adde r0,r0,r5
51	adde r0,r0,r7
52	addze r0,r0 /* add in final carry */
53	rlwinm r3,r0,16,0,31 /* fold two halves together */
54	add r3,r0,r3
55	not r3,r3
56	srwi r3,r3,16
57	blr
58
59	/*	43	/*
60	* computes the checksum of a memory block at buff, length len,	44	* computes the checksum of a memory block at buff, length len,
61	* and adds in "sum" (32-bit)	45	* and adds in "sum" (32-bit)

arch/powerpc/lib/checksum_64.S+0−21

@@ -44,27 +44,6 @@ _GLOBAL(ip_fast_csum) · 43 unmodified lines
44	srwi r3,r3,16	44	srwi r3,r3,16
45	blr	45	blr
46		46
47	/*
48	* Compute checksum of TCP or UDP pseudo-header:
49	* csum_tcpudp_magic(r3=saddr, r4=daddr, r5=len, r6=proto, r7=sum)
50	* No real gain trying to do this specially for 64 bit, but
51	* the 32 bit addition may spill into the upper bits of
52	* the doubleword so we still must fold it down from 64.
53	*/
54	_GLOBAL(csum_tcpudp_magic)
55	rlwimi r5,r6,16,0,15 /* put proto in upper half of len */
56	addc r0,r3,r4 /* add 4 32-bit words together */
57	adde r0,r0,r5
58	adde r0,r0,r7
59	rldicl r4,r0,32,0 /* fold 64 bit value */
60	add r0,r4,r0
61	srdi r0,r0,32
62	rlwinm r3,r0,16,0,31 /* fold two halves together */
63	add r3,r0,r3
64	not r3,r3
65	srwi r3,r3,16
66	blr
67
68	/*	47	/*
69	* Computes the checksum of a memory block at buff, length len,	48	* Computes the checksum of a memory block at buff, length len,
70	* and adds in "sum" (32-bit).	49	* and adds in "sum" (32-bit).

arch/powerpc/lib/copy_32.S+108−1

@@ -69,9 +69,15 @@ CACHELINE_BYTES = L1_CACHE_BYTES · 68 unmodified lines
69	LG_CACHELINE_BYTES = L1_CACHE_SHIFT	69	LG_CACHELINE_BYTES = L1_CACHE_SHIFT
70	CACHELINE_MASK = (L1_CACHE_BYTES-1)	70	CACHELINE_MASK = (L1_CACHE_BYTES-1)
71		71
		72	/*
		73	* Use dcbz on the complete cache lines in the destination
		74	* to set them to zero. This requires that the destination
		75	* area is cacheable. -- paulus
		76	*/
72	_GLOBAL(memset)	77	_GLOBAL(memset)
73	rlwimi r4,r4,8,16,23	78	rlwimi r4,r4,8,16,23
74	rlwimi r4,r4,16,0,15	79	rlwimi r4,r4,16,0,15
		80
75	addi r6,r3,-4	81	addi r6,r3,-4
76	cmplwi 0,r5,4	82	cmplwi 0,r5,4
77	blt 7f	83	blt 7f
@@ -80,7 +86,29 @@ _GLOBAL(memset) · 2 unmodified lines
80	andi. r0,r6,3	86	andi. r0,r6,3
81	add r5,r0,r5	87	add r5,r0,r5
82	subf r6,r0,r6	88	subf r6,r0,r6
83	srwi r0,r5,2	89	cmplwi 0,r4,0
		90	bne 2f /* Use normal procedure if r4 is not zero */
		91
		92	clrlwi r7,r6,32-LG_CACHELINE_BYTES
		93	add r8,r7,r5
		94	srwi r9,r8,LG_CACHELINE_BYTES
		95	addic. r9,r9,-1 /* total number of complete cachelines */
		96	ble 2f
		97	xori r0,r7,CACHELINE_MASK & ~3
		98	srwi. r0,r0,2
		99	beq 3f
		100	mtctr r0
		101	4: stwu r4,4(r6)
		102	bdnz 4b
		103	3: mtctr r9
		104	li r7,4
		105	10: dcbz r7,r6
		106	addi r6,r6,CACHELINE_BYTES
		107	bdnz 10b
		108	clrlwi r5,r8,32-LG_CACHELINE_BYTES
		109	addi r5,r5,4
		110
		111	2: srwi r0,r5,2
84	mtctr r0	112	mtctr r0
85	bdz 6f	113	bdz 6f
86	1: stwu r4,4(r6)	114	1: stwu r4,4(r6)
@@ -94,12 +122,91 @@ _GLOBAL(memset) · 7 unmodified lines
94	bdnz 8b	122	bdnz 8b
95	blr	123	blr
96		124
		125	/*
		126	* This version uses dcbz on the complete cache lines in the
		127	* destination area to reduce memory traffic. This requires that
		128	* the destination area is cacheable.
		129	* We only use this version if the source and dest don't overlap.
		130	* -- paulus.
		131	*/
97	_GLOBAL(memmove)	132	_GLOBAL(memmove)
98	cmplw 0,r3,r4	133	cmplw 0,r3,r4
99	bgt backwards_memcpy	134	bgt backwards_memcpy
100	/* fall through */	135	/* fall through */
101		136
102	_GLOBAL(memcpy)	137	_GLOBAL(memcpy)
		138	add r7,r3,r5 /* test if the src & dst overlap */
		139	add r8,r4,r5
		140	cmplw 0,r4,r7
		141	cmplw 1,r3,r8
		142	crand 0,0,4 /* cr0.lt &= cr1.lt */
		143	blt generic_memcpy /* if regions overlap */
		144
		145	addi r4,r4,-4
		146	addi r6,r3,-4
		147	neg r0,r3
		148	andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
		149	beq 58f
		150
		151	cmplw 0,r5,r0 /* is this more than total to do? */
		152	blt 63f /* if not much to do */
		153	andi. r8,r0,3 /* get it word-aligned first */
		154	subf r5,r0,r5
		155	mtctr r8
		156	beq+ 61f
		157	70: lbz r9,4(r4) /* do some bytes */
		158	addi r4,r4,1
		159	addi r6,r6,1
		160	stb r9,3(r6)
		161	bdnz 70b
		162	61: srwi. r0,r0,2
		163	mtctr r0
		164	beq 58f
		165	72: lwzu r9,4(r4) /* do some words */
		166	stwu r9,4(r6)
		167	bdnz 72b
		168
		169	58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
		170	clrlwi r5,r5,32-LG_CACHELINE_BYTES
		171	li r11,4
		172	mtctr r0
		173	beq 63f
		174	53:
		175	dcbz r11,r6
		176	COPY_16_BYTES
		177	#if L1_CACHE_BYTES >= 32
		178	COPY_16_BYTES
		179	#if L1_CACHE_BYTES >= 64
		180	COPY_16_BYTES
		181	COPY_16_BYTES
		182	#if L1_CACHE_BYTES >= 128
		183	COPY_16_BYTES
		184	COPY_16_BYTES
		185	COPY_16_BYTES
		186	COPY_16_BYTES
		187	#endif
		188	#endif
		189	#endif
		190	bdnz 53b
		191
		192	63: srwi. r0,r5,2
		193	mtctr r0
		194	beq 64f
		195	30: lwzu r0,4(r4)
		196	stwu r0,4(r6)
		197	bdnz 30b
		198
		199	64: andi. r0,r5,3
		200	mtctr r0
		201	beq+ 65f
		202	addi r4,r4,3
		203	addi r6,r6,3
		204	40: lbzu r0,1(r4)
		205	stbu r0,1(r6)
		206	bdnz 40b
		207	65: blr
		208
		209	_GLOBAL(generic_memcpy)
103	srwi. r7,r5,3	210	srwi. r7,r5,3
104	addi r6,r3,-4	211	addi r6,r3,-4
105	addi r4,r4,-4	212	addi r4,r4,-4

arch/powerpc/mm/fsl_booke_mmu.c+1−1

@@ -112,7 +112,7 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, · 111 unmodified lines
112		112
113	tsize = __ilog2(size) - 10;	113	tsize = __ilog2(size) - 10;
114		114
115	#ifdef CONFIG_SMP	115	#if defined(CONFIG_SMP) \|\| defined(CONFIG_PPC_E500MC)
116	if ((flags & _PAGE_NO_CACHE) == 0)	116	if ((flags & _PAGE_NO_CACHE) == 0)
117	flags \|= _PAGE_COHERENT;	117	flags \|= _PAGE_COHERENT;
118	#endif	118	#endif

arch/powerpc/mm/hash_low_64.S+2−2

@@ -701,7 +701,7 @@ htab_pte_insert_failure: · 700 unmodified lines
701		701
702	#endif /* CONFIG_PPC_64K_PAGES */	702	#endif /* CONFIG_PPC_64K_PAGES */
703		703
704	#ifdef CONFIG_PPC_HAS_HASH_64K	704	#ifdef CONFIG_PPC_64K_PAGES
705		705
706	/*****************************************************************************	706	/*****************************************************************************
707	* *	707	* *
@@ -993,7 +993,7 @@ ht64_pte_insert_failure: · 285 unmodified lines
993	b ht64_bail	993	b ht64_bail
994		994
995		995
996	#endif /* CONFIG_PPC_HAS_HASH_64K */	996	#endif /* CONFIG_PPC_64K_PAGES */
997		997
998		998
999	/*****************************************************************************	999	/*****************************************************************************

arch/powerpc/mm/hash_utils_64.c+6−6

@@ -640,7 +640,7 @@ extern u32 ht64_call_hpte_updatepp[]; · 639 unmodified lines
640		640
641	static void __init htab_finish_init(void)	641	static void __init htab_finish_init(void)
642	{	642	{
643	#ifdef CONFIG_PPC_HAS_HASH_64K	643	#ifdef CONFIG_PPC_64K_PAGES
644	patch_branch(ht64_call_hpte_insert1,	644	patch_branch(ht64_call_hpte_insert1,
645	ppc_function_entry(ppc_md.hpte_insert),	645	ppc_function_entry(ppc_md.hpte_insert),
646	BRANCH_SET_LINK);	646	BRANCH_SET_LINK);
@@ -653,7 +653,7 @@ static void __init htab_finish_init(void) · 6 unmodified lines
653	patch_branch(ht64_call_hpte_updatepp,	653	patch_branch(ht64_call_hpte_updatepp,
654	ppc_function_entry(ppc_md.hpte_updatepp),	654	ppc_function_entry(ppc_md.hpte_updatepp),
655	BRANCH_SET_LINK);	655	BRANCH_SET_LINK);
656	#endif /* CONFIG_PPC_HAS_HASH_64K */	656	#endif /* CONFIG_PPC_64K_PAGES */
657		657
658	patch_branch(htab_call_hpte_insert1,	658	patch_branch(htab_call_hpte_insert1,
659	ppc_function_entry(ppc_md.hpte_insert),	659	ppc_function_entry(ppc_md.hpte_insert),
@@ -1151,12 +1151,12 @@ int hash_page_mm(struct mm_struct *mm, unsigned long ea, · 491 unmodified lines
1151	check_paca_psize(ea, mm, psize, user_region);	1151	check_paca_psize(ea, mm, psize, user_region);
1152	#endif /* CONFIG_PPC_64K_PAGES */	1152	#endif /* CONFIG_PPC_64K_PAGES */
1153		1153
1154	#ifdef CONFIG_PPC_HAS_HASH_64K	1154	#ifdef CONFIG_PPC_64K_PAGES
1155	if (psize == MMU_PAGE_64K)	1155	if (psize == MMU_PAGE_64K)
1156	rc = __hash_page_64K(ea, access, vsid, ptep, trap,	1156	rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1157	flags, ssize);	1157	flags, ssize);
1158	else	1158	else
1159	#endif /* CONFIG_PPC_HAS_HASH_64K */	1159	#endif /* CONFIG_PPC_64K_PAGES */
1160	{	1160	{
1161	int spp = subpage_protection(mm, ea);	1161	int spp = subpage_protection(mm, ea);
1162	if (access & spp)	1162	if (access & spp)
@@ -1264,12 +1264,12 @@ void hash_preload(struct mm_struct *mm, unsigned long ea, · 101 unmodified lines
1264	update_flags \|= HPTE_LOCAL_UPDATE;	1264	update_flags \|= HPTE_LOCAL_UPDATE;
1265		1265
1266	/* Hash it in */	1266	/* Hash it in */
1267	#ifdef CONFIG_PPC_HAS_HASH_64K	1267	#ifdef CONFIG_PPC_64K_PAGES
1268	if (mm->context.user_psize == MMU_PAGE_64K)	1268	if (mm->context.user_psize == MMU_PAGE_64K)
1269	rc = __hash_page_64K(ea, access, vsid, ptep, trap,	1269	rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1270	update_flags, ssize);	1270	update_flags, ssize);
1271	else	1271	else
1272	#endif /* CONFIG_PPC_HAS_HASH_64K */	1272	#endif /* CONFIG_PPC_64K_PAGES */
1273	rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,	1273	rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1274	ssize, subpage_protection(mm, ea));	1274	ssize, subpage_protection(mm, ea));
1275		1275

arch/powerpc/mm/hugetlbpage.c+0−8

@@ -808,14 +808,6 @@ static int __init add_huge_page_size(unsigned long long size) · 807 unmodified lines
808	if ((mmu_psize = shift_to_mmu_psize(shift)) < 0)	808	if ((mmu_psize = shift_to_mmu_psize(shift)) < 0)
809	return -EINVAL;	809	return -EINVAL;
810		810
811	#ifdef CONFIG_SPU_FS_64K_LS
812	/* Disable support for 64K huge pages when 64K SPU local store
813	* support is enabled as the current implementation conflicts.
814	*/
815	if (shift == PAGE_SHIFT_64K)
816	return -EINVAL;
817	#endif /* CONFIG_SPU_FS_64K_LS */
818
819	BUG_ON(mmu_psize_defs[mmu_psize].shift != shift);	811	BUG_ON(mmu_psize_defs[mmu_psize].shift != shift);
820		812
821	/* Return if huge page size has already been setup */	813	/* Return if huge page size has already been setup */

arch/powerpc/mm/mem.c+7−7

 		return;
 	}
 #endif
-#ifdef CONFIG_BOOKE
+#if defined(CONFIG_8xx) || defined(CONFIG_PPC64)
-	{
+	/* On 8xx there is no need to kmap since highmem is not supported */
+	__flush_dcache_icache(page_address(page));
+#else
+	if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
 		void *start = kmap_atomic(page);
 		__flush_dcache_icache(start);
 		kunmap_atomic(start);
+	} else {
+		__flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
 	}
-#elif defined(CONFIG_8xx) || defined(CONFIG_PPC64)
-	/* On 8xx there is no need to kmap since highmem is not supported */
-	__flush_dcache_icache(page_address(page));
-#else
-	__flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
 #endif
 }
 EXPORT_SYMBOL(flush_dcache_icache_page);

arch/powerpc/mm/numa.c+13−3

 	for (i = 0; i < distance_ref_points_depth; i++) {
 		const __be32 *entry;
-		entry = &associativity[be32_to_cpu(distance_ref_points[i])];
+		entry = &associativity[be32_to_cpu(distance_ref_points[i]) - 1];
 		distance_lookup_table[nid][i] = of_read_number(entry, 1);
 	}
 }
 		nid = -1;
 	if (nid > 0 &&
-	    of_read_number(associativity, 1) >= distance_ref_points_depth)
+		of_read_number(associativity, 1) >= distance_ref_points_depth) {
-		initialize_distance_lookup_table(nid, associativity);
+		/*
+		 * Skip the length field and send start of associativity array
+		 */
+		initialize_distance_lookup_table(nid, associativity + 1);
+	}
 out:
 	return nid;
 		if (nid == 0xffff || nid >= MAX_NUMNODES)
 			nid = default_nid;
+		if (nid > 0) {
+			index = drmem->aa_index * aa->array_sz;
+			initialize_distance_lookup_table(nid,
+							&aa->arrays[index]);
+		}
 	}
 	return nid;

arch/powerpc/mm/pgtable_64.c+0−10

@@ -149,17 +149,7 @@ int map_kernel_page(unsigned long ea, unsigned long pa, int flags) · 148 unmodified lines
149	#endif /* !CONFIG_PPC_MMU_NOHASH */	149	#endif /* !CONFIG_PPC_MMU_NOHASH */
150	}	150	}
151		151
152	#ifdef CONFIG_PPC_BOOK3E_64
153	/*
154	* With hardware tablewalk, a sync is needed to ensure that
155	* subsequent accesses see the PTE we just wrote. Unlike userspace
156	* mappings, we can't tolerate spurious faults, so make sure
157	* the new PTE will be seen the first time.
158	*/
159	mb();
160	#else
161	smp_wmb();	152	smp_wmb();
162	#endif
163	return 0;	153	return 0;
164	}	154	}
165		155

arch/powerpc/mm/slb.c+18−6

@@ -41,9 +41,9 @@ static void slb_allocate(unsigned long ea) · 40 unmodified lines
41	(((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)	41	(((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
42		42
43	static inline unsigned long mk_esid_data(unsigned long ea, int ssize,	43	static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
44	unsigned long slot)	44	unsigned long entry)
45	{	45	{
46	return (ea & slb_esid_mask(ssize)) \| SLB_ESID_V \| slot;	46	return (ea & slb_esid_mask(ssize)) \| SLB_ESID_V \| entry;
47	}	47	}
48		48
49	static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,	49	static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
@@ -249,11 +249,24 @@ void switch_slb(struct task_struct tsk, struct mm_struct mm) · 199 unmodified lines
249	static inline void patch_slb_encoding(unsigned int *insn_addr,	249	static inline void patch_slb_encoding(unsigned int *insn_addr,
250	unsigned int immed)	250	unsigned int immed)
251	{	251	{
252	int insn = (*insn_addr & 0xffff0000) \| immed;	252
		253	/*
		254	* This function patches either an li or a cmpldi instruction with
		255	* a new immediate value. This relies on the fact that both li
		256	* (which is actually addi) and cmpldi both take a 16-bit immediate
		257	* value, and it is situated in the same location in the instruction,
		258	* ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
		259	* The signedness of the immediate operand differs between the two
		260	* instructions however this code is only ever patching a small value,
		261	* much less than 1 << 15, so we can get away with it.
		262	* To patch the value we read the existing instruction, clear the
		263	* immediate value, and or in our new value, then write the instruction
		264	* back.
		265	*/
		266	unsigned int insn = (*insn_addr & 0xffff0000) \| immed;
253	patch_instruction(insn_addr, insn);	267	patch_instruction(insn_addr, insn);
254	}	268	}
255		269
256	extern u32 slb_compare_rr_to_size[];
257	extern u32 slb_miss_kernel_load_linear[];	270	extern u32 slb_miss_kernel_load_linear[];
258	extern u32 slb_miss_kernel_load_io[];	271	extern u32 slb_miss_kernel_load_io[];
259	extern u32 slb_compare_rr_to_size[];	272	extern u32 slb_compare_rr_to_size[];
@@ -309,12 +322,11 @@ void slb_initialize(void) · 49 unmodified lines
309	lflags = SLB_VSID_KERNEL \| linear_llp;	322	lflags = SLB_VSID_KERNEL \| linear_llp;
310	vflags = SLB_VSID_KERNEL \| vmalloc_llp;	323	vflags = SLB_VSID_KERNEL \| vmalloc_llp;
311		324
312	/* Invalidate the entire SLB (even slot 0) & all the ERATS */	325	/* Invalidate the entire SLB (even entry 0) & all the ERATS */
313	asm volatile("isync":::"memory");	326	asm volatile("isync":::"memory");
314	asm volatile("slbmte %0,%0"::"r" (0) : "memory");	327	asm volatile("slbmte %0,%0"::"r" (0) : "memory");
315	asm volatile("isync; slbia; isync":::"memory");	328	asm volatile("isync; slbia; isync":::"memory");
316	create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0);	329	create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0);
317
318	create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1);	330	create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
319		331
320	/* For the boot cpu, we're running on the stack in init_thread_union,	332	/* For the boot cpu, we're running on the stack in init_thread_union,

arch/powerpc/mm/tlb_low_64e.S+5−5

 	 *
 	 * MAS6:IND should be already set based on MAS4
 	 */
-1:	lbarx	r15,0,r11
 	lhz	r10,PACAPACAINDEX(r13)
-	cmpdi	r15,0
-	cmpdi	cr1,r15,1	/* set cr1.eq = 0 for non-recursive */
 	addi	r10,r10,1
+	crclr	cr1*4+eq	/* set cr1.eq = 0 for non-recursive */
+1:	lbarx	r15,0,r11
+	cmpdi	r15,0
 	bne	2f
 	stbcx.	r10,0,r11
 	bne	1b
 	.subsection 1
 2:	cmpd	cr1,r15,r10	/* recursive lock due to mcheck/crit/etc? */
 	beq	cr1,3b		/* unlock will happen if cr1.eq = 0 */
-	lbz	r15,0(r11)
+10:	lbz	r15,0(r11)
 	cmpdi	r15,0
-	bne	2b
+	bne	10b
 	b	1b
 	.previous

arch/powerpc/oprofile/op_model_power4.c+2−2

@@ -207,7 +207,7 @@ static int power4_start(struct op_counter_config *ctr) · 206 unmodified lines
207	unsigned int mmcr0;	207	unsigned int mmcr0;
208		208
209	/* set the PMM bit (see comment below) */	209	/* set the PMM bit (see comment below) */
210	mtmsrd(mfmsr() \| MSR_PMM);	210	mtmsr(mfmsr() \| MSR_PMM);
211		211
212	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {	212	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
213	if (ctr[i].enabled) {	213	if (ctr[i].enabled) {
@@ -377,7 +377,7 @@ static void power4_handle_interrupt(struct pt_regs *regs, · 163 unmodified lines
377	is_kernel = get_kernel(pc, mmcra);	377	is_kernel = get_kernel(pc, mmcra);
378		378
379	/* set the PMM bit (see comment below) */	379	/* set the PMM bit (see comment below) */
380	mtmsrd(mfmsr() \| MSR_PMM);	380	mtmsr(mfmsr() \| MSR_PMM);
381		381
382	/* Check that the SIAR valid bit in MMCRA is set to 1. */	382	/* Check that the SIAR valid bit in MMCRA is set to 1. */
383	if ((mmcra & MMCRA_SIAR_VALID_MASK) == MMCRA_SIAR_VALID_MASK)	383	if ((mmcra & MMCRA_SIAR_VALID_MASK) == MMCRA_SIAR_VALID_MASK)

arch/powerpc/perf/core-book3s.c+2−2

 	/* BHRB bits */
 	u64				bhrb_filter;	/* BHRB HW branch filter */
-	int				bhrb_users;
+	unsigned int			bhrb_users;
 	void				*bhrb_context;
 	struct	perf_branch_stack	bhrb_stack;
 	struct	perf_branch_entry	bhrb_entries[BHRB_MAX_ENTRIES];
 	if (!ppmu->bhrb_nr)
 		return;
+	WARN_ON_ONCE(!cpuhw->bhrb_users);
 	cpuhw->bhrb_users--;
-	WARN_ON_ONCE(cpuhw->bhrb_users < 0);
 	perf_sched_cb_dec(event->ctx->pmu);
 	if (!cpuhw->disabled && !cpuhw->bhrb_users) {

arch/powerpc/perf/hv-24x7.c+11−13

 }
 static struct attribute *event_to_desc_attr(struct hv_24x7_event_data *event,
-				int nonce)
+					    int nonce)
 {
 	int nl, dl;
 	char *name = event_name(event, &nl);
 }
 static ssize_t event_data_to_attrs(unsigned ix, struct attribute **attrs,
-		struct hv_24x7_event_data *event, int nonce)
+				   struct hv_24x7_event_data *event, int nonce)
 {
 	unsigned i;
 }
 static int ev_uniq_ord(const void *v1, size_t s1, unsigned d1, const void *v2,
-					size_t s2, unsigned d2)
+		       size_t s2, unsigned d2)
 {
 	int r = memord(v1, s1, v2, s2);
 }
 static int event_uniq_add(struct rb_root *root, const char *name, int nl,
-				unsigned domain)
+			  unsigned domain)
 {
 	struct rb_node **new = &(root->rb_node), *parent = NULL;
 	struct event_uniq *data;
 #define MAX_4K (SIZE_MAX / 4096)
 static int create_events_from_catalog(struct attribute ***events_,
-		struct attribute ***event_descs_,
+				      struct attribute ***event_descs_,
-		struct attribute ***event_long_descs_)
+				      struct attribute ***event_long_descs_)
 {
 	unsigned long hret;
 	size_t catalog_len, catalog_page_len, event_entry_count,
 };
 static void log_24x7_hcall(struct hv_24x7_request_buffer *request_buffer,
-			struct hv_24x7_data_result_buffer *result_buffer,
+			   struct hv_24x7_data_result_buffer *result_buffer,
-			unsigned long ret)
+			   unsigned long ret)
 {
 	struct hv_24x7_request *req;
  * Start the process for a new H_GET_24x7_DATA hcall.
  */
 static void init_24x7_request(struct hv_24x7_request_buffer *request_buffer,
-			struct hv_24x7_data_result_buffer *result_buffer)
+			      struct hv_24x7_data_result_buffer *result_buffer)
 {
 	memset(request_buffer, 0, 4096);
  * by 'init_24x7_request()' and 'add_event_to_24x7_request()'.
  */
 static int make_24x7_request(struct hv_24x7_request_buffer *request_buffer,
-			struct hv_24x7_data_result_buffer *result_buffer)
+			     struct hv_24x7_data_result_buffer *result_buffer)
 {
 	unsigned long ret;
 	unsigned long ret;
 	struct hv_24x7_request_buffer *request_buffer;
 	struct hv_24x7_data_result_buffer *result_buffer;
-	struct hv_24x7_result *resb;
 	BUILD_BUG_ON(sizeof(*request_buffer) > 4096);
 	BUILD_BUG_ON(sizeof(*result_buffer) > 4096);
 	}
 	/* process result from hcall */
-	resb = &result_buffer->results[0];
+	*count = be64_to_cpu(result_buffer->results[0].elements[0].element_data[0]);
-	*count = be64_to_cpu(resb->elements[0].element_data[0]);
 out:
 	put_cpu_var(hv_24x7_reqb);

arch/powerpc/platforms/512x/Kconfig+2−2

@@ -7,8 +7,8 @@ config PPC_MPC512x · 6 unmodified lines
7	select PPC_PCI_CHOICE	7	select PPC_PCI_CHOICE
8	select FSL_PCI if PCI	8	select FSL_PCI if PCI
9	select ARCH_WANT_OPTIONAL_GPIOLIB	9	select ARCH_WANT_OPTIONAL_GPIOLIB
10	select USB_EHCI_BIG_ENDIAN_MMIO	10	select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
11	select USB_EHCI_BIG_ENDIAN_DESC	11	select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
12		12
13	config MPC5121_ADS	13	config MPC5121_ADS
14	bool "Freescale MPC5121E ADS"	14	bool "Freescale MPC5121E ADS"

arch/powerpc/platforms/85xx/c293pcie.c+0−4

 	.probe			= c293_pcie_probe,
 	.setup_arch		= c293_pcie_setup_arch,
 	.init_IRQ		= c293_pcie_pic_init,
-#ifdef CONFIG_PCI
-	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
-	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
-#endif
 	.get_irq		= mpic_get_irq,
 	.restart		= fsl_rstcr_restart,
 	.calibrate_decr		= generic_calibrate_decr,

arch/powerpc/platforms/85xx/corenet_generic.c+2−0

 	"fsl,T1023RDB",
 	"fsl,T1024QDS",
 	"fsl,T1024RDB",
+	"fsl,T1040D4RDB",
+	"fsl,T1042D4RDB",
 	"fsl,T1040QDS",
 	"fsl,T1042QDS",
 	"fsl,T1040RDB",

arch/powerpc/platforms/cell/Kconfig+0−15

@@ -57,21 +57,6 @@ config SPU_FS · 56 unmodified lines
57	Units on machines implementing the Broadband Processor	57	Units on machines implementing the Broadband Processor
58	Architecture.	58	Architecture.
59		59
60	config SPU_FS_64K_LS
61	bool "Use 64K pages to map SPE local store"
62	# we depend on PPC_MM_SLICES for now rather than selecting
63	# it because we depend on hugetlbfs hooks being present. We
64	# will fix that when the generic code has been improved to
65	# not require hijacking hugetlbfs hooks.
66	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
67	default y
68	select PPC_HAS_HASH_64K
69	help
70	This option causes SPE local stores to be mapped in process
71	address spaces using 64K pages while the rest of the kernel
72	uses 4K pages. This can improve performances of applications
73	using multiple SPEs by lowering the TLB pressure on them.
74
75	config SPU_BASE	60	config SPU_BASE
76	bool	61	bool
77	default n	62	default n

arch/powerpc/platforms/cell/spufs/file.c+0−55

@@ -239,23 +239,6 @@ spufs_mem_mmap_fault(struct vm_area_struct vma, struct vm_fault vmf) · 238 unmodified lines
239	unsigned long address = (unsigned long)vmf->virtual_address;	239	unsigned long address = (unsigned long)vmf->virtual_address;
240	unsigned long pfn, offset;	240	unsigned long pfn, offset;
241		241
242	#ifdef CONFIG_SPU_FS_64K_LS
243	struct spu_state *csa = &ctx->csa;
244	int psize;
245
246	/* Check what page size we are using */
247	psize = get_slice_psize(vma->vm_mm, address);
248
249	/* Some sanity checking */
250	BUG_ON(csa->use_big_pages != (psize == MMU_PAGE_64K));
251
252	/* Wow, 64K, cool, we need to align the address though */
253	if (csa->use_big_pages) {
254	BUG_ON(vma->vm_start & 0xffff);
255	address &= ~0xfffful;
256	}
257	#endif /* CONFIG_SPU_FS_64K_LS */
258
259	offset = vmf->pgoff << PAGE_SHIFT;	242	offset = vmf->pgoff << PAGE_SHIFT;
260	if (offset >= LS_SIZE)	243	if (offset >= LS_SIZE)
261	return VM_FAULT_SIGBUS;	244	return VM_FAULT_SIGBUS;
@@ -310,22 +293,6 @@ static const struct vm_operations_struct spufs_mem_mmap_vmops = { · 48 unmodified lines
310		293
311	static int spufs_mem_mmap(struct file file, struct vm_area_struct vma)	294	static int spufs_mem_mmap(struct file file, struct vm_area_struct vma)
312	{	295	{
313	#ifdef CONFIG_SPU_FS_64K_LS
314	struct spu_context *ctx = file->private_data;
315	struct spu_state *csa = &ctx->csa;
316
317	/* Sanity check VMA alignment */
318	if (csa->use_big_pages) {
319	pr_debug("spufs_mem_mmap 64K, start=0x%lx, end=0x%lx,"
320	" pgoff=0x%lx\n", vma->vm_start, vma->vm_end,
321	vma->vm_pgoff);
322	if (vma->vm_start & 0xffff)
323	return -EINVAL;
324	if (vma->vm_pgoff & 0xf)
325	return -EINVAL;
326	}
327	#endif /* CONFIG_SPU_FS_64K_LS */
328
329	if (!(vma->vm_flags & VM_SHARED))	296	if (!(vma->vm_flags & VM_SHARED))
330	return -EINVAL;	297	return -EINVAL;
331		298
@@ -336,25 +303,6 @@ static int spufs_mem_mmap(struct file file, struct vm_area_struct vma) · 4 unmodified lines
336	return 0;	303	return 0;
337	}	304	}
338		305
339	#ifdef CONFIG_SPU_FS_64K_LS
340	static unsigned long spufs_get_unmapped_area(struct file *file,
341	unsigned long addr, unsigned long len, unsigned long pgoff,
342	unsigned long flags)
343	{
344	struct spu_context *ctx = file->private_data;
345	struct spu_state *csa = &ctx->csa;
346
347	/* If not using big pages, fallback to normal MM g_u_a */
348	if (!csa->use_big_pages)
349	return current->mm->get_unmapped_area(file, addr, len,
350	pgoff, flags);
351
352	/* Else, try to obtain a 64K pages slice */
353	return slice_get_unmapped_area(addr, len, flags,
354	MMU_PAGE_64K, 1);
355	}
356	#endif /* CONFIG_SPU_FS_64K_LS */
357
358	static const struct file_operations spufs_mem_fops = {	306	static const struct file_operations spufs_mem_fops = {
359	.open = spufs_mem_open,	307	.open = spufs_mem_open,
360	.release = spufs_mem_release,	308	.release = spufs_mem_release,
@@ -362,9 +310,6 @@ static const struct file_operations spufs_mem_fops = { · 1 unmodified line
362	.write = spufs_mem_write,	310	.write = spufs_mem_write,
363	.llseek = generic_file_llseek,	311	.llseek = generic_file_llseek,
364	.mmap = spufs_mem_mmap,	312	.mmap = spufs_mem_mmap,
365	#ifdef CONFIG_SPU_FS_64K_LS
366	.get_unmapped_area = spufs_get_unmapped_area,
367	#endif
368	};	313	};
369		314
370	static int spufs_ps_fault(struct vm_area_struct *vma,	315	static int spufs_ps_fault(struct vm_area_struct *vma,

arch/powerpc/platforms/cell/spufs/lscsa_alloc.c+2−122

@@ -31,7 +31,7 @@ · 30 unmodified lines
31		31
32	#include "spufs.h"	32	#include "spufs.h"
33		33
34	static int spu_alloc_lscsa_std(struct spu_state *csa)	34	int spu_alloc_lscsa(struct spu_state *csa)
35	{	35	{
36	struct spu_lscsa *lscsa;	36	struct spu_lscsa *lscsa;
37	unsigned char *p;	37	unsigned char *p;
@@ -48,7 +48,7 @@ static int spu_alloc_lscsa_std(struct spu_state *csa) · 10 unmodified lines
48	return 0;	48	return 0;
49	}	49	}
50		50
51	static void spu_free_lscsa_std(struct spu_state *csa)	51	void spu_free_lscsa(struct spu_state *csa)
52	{	52	{
53	/* Clear reserved bit before vfree. */	53	/* Clear reserved bit before vfree. */
54	unsigned char *p;	54	unsigned char *p;
@@ -61,123 +61,3 @@ static void spu_free_lscsa_std(struct spu_state *csa) · 6 unmodified lines
61		61
62	vfree(csa->lscsa);	62	vfree(csa->lscsa);
63	}	63	}
64
65	#ifdef CONFIG_SPU_FS_64K_LS
66
67	#define SPU_64K_PAGE_SHIFT 16
68	#define SPU_64K_PAGE_ORDER (SPU_64K_PAGE_SHIFT - PAGE_SHIFT)
69	#define SPU_64K_PAGE_COUNT (1ul << SPU_64K_PAGE_ORDER)
70
71	int spu_alloc_lscsa(struct spu_state *csa)
72	{
73	struct page **pgarray;
74	unsigned char *p;
75	int i, j, n_4k;
76
77	/* Check availability of 64K pages */
78	if (!spu_64k_pages_available())
79	goto fail;
80
81	csa->use_big_pages = 1;
82
83	pr_debug("spu_alloc_lscsa(csa=0x%p), trying to allocate 64K pages\n",
84	csa);
85
86	/* First try to allocate our 64K pages. We need 5 of them
87	* with the current implementation. In the future, we should try
88	* to separate the lscsa with the actual local store image, thus
89	* allowing us to require only 4 64K pages per context
90	*/
91	for (i = 0; i < SPU_LSCSA_NUM_BIG_PAGES; i++) {
92	/* XXX This is likely to fail, we should use a special pool
93	* similar to what hugetlbfs does.
94	*/
95	csa->lscsa_pages[i] = alloc_pages(GFP_KERNEL,
96	SPU_64K_PAGE_ORDER);
97	if (csa->lscsa_pages[i] == NULL)
98	goto fail;
99	}
100
101	pr_debug(" success ! creating vmap...\n");
102
103	/* Now we need to create a vmalloc mapping of these for the kernel
104	* and SPU context switch code to use. Currently, we stick to a
105	* normal kernel vmalloc mapping, which in our case will be 4K
106	*/
107	n_4k = SPU_64K_PAGE_COUNT * SPU_LSCSA_NUM_BIG_PAGES;
108	pgarray = kmalloc(sizeof(struct page ) n_4k, GFP_KERNEL);
109	if (pgarray == NULL)
110	goto fail;
111	for (i = 0; i < SPU_LSCSA_NUM_BIG_PAGES; i++)
112	for (j = 0; j < SPU_64K_PAGE_COUNT; j++)
113	/* We assume all the struct page's are contiguous
114	* which should be hopefully the case for an order 4
115	* allocation..
116	*/
117	pgarray[i * SPU_64K_PAGE_COUNT + j] =
118	csa->lscsa_pages[i] + j;
119	csa->lscsa = vmap(pgarray, n_4k, VM_USERMAP, PAGE_KERNEL);
120	kfree(pgarray);
121	if (csa->lscsa == NULL)
122	goto fail;
123
124	memset(csa->lscsa, 0, sizeof(struct spu_lscsa));
125
126	/* Set LS pages reserved to allow for user-space mapping.
127	*
128	* XXX isn't that a bit obsolete ? I think we should just
129	* make sure the page count is high enough. Anyway, won't harm
130	* for now
131	*/
132	for (p = csa->lscsa->ls; p < csa->lscsa->ls + LS_SIZE; p += PAGE_SIZE)
133	SetPageReserved(vmalloc_to_page(p));
134
135	pr_debug(" all good !\n");
136
137	return 0;
138	fail:
139	pr_debug("spufs: failed to allocate lscsa 64K pages, falling back\n");
140	spu_free_lscsa(csa);
141	return spu_alloc_lscsa_std(csa);
142	}
143
144	void spu_free_lscsa(struct spu_state *csa)
145	{
146	unsigned char *p;
147	int i;
148
149	if (!csa->use_big_pages) {
150	spu_free_lscsa_std(csa);
151	return;
152	}
153	csa->use_big_pages = 0;
154
155	if (csa->lscsa == NULL)
156	goto free_pages;
157
158	for (p = csa->lscsa->ls; p < csa->lscsa->ls + LS_SIZE; p += PAGE_SIZE)
159	ClearPageReserved(vmalloc_to_page(p));
160
161	vunmap(csa->lscsa);
162	csa->lscsa = NULL;
163
164	free_pages:
165
166	for (i = 0; i < SPU_LSCSA_NUM_BIG_PAGES; i++)
167	if (csa->lscsa_pages[i])
168	__free_pages(csa->lscsa_pages[i], SPU_64K_PAGE_ORDER);
169	}
170
171	#else /* CONFIG_SPU_FS_64K_LS */
172
173	int spu_alloc_lscsa(struct spu_state *csa)
174	{
175	return spu_alloc_lscsa_std(csa);
176	}
177
178	void spu_free_lscsa(struct spu_state *csa)
179	{
180	spu_free_lscsa_std(csa);
181	}
182
183	#endif /* !defined(CONFIG_SPU_FS_64K_LS) */

arch/powerpc/platforms/powernv/eeh-powernv.c+10−2

 			 */
 			if (pnv_eeh_get_pe(hose,
 				be64_to_cpu(frozen_pe_no), pe)) {
-				/* Try best to clear it */
 				pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
-					hose->global_number, frozen_pe_no);
+					hose->global_number, be64_to_cpu(frozen_pe_no));
 				pr_info("EEH: PHB location: %s\n",
 					eeh_pe_loc_get(phb_pe));
+				/* Dump PHB diag-data */
+				rc = opal_pci_get_phb_diag_data2(phb->opal_id,
+					phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
+				if (rc == OPAL_SUCCESS)
+					pnv_pci_dump_phb_diag_data(hose,
+							phb->diag.blob);
+				/* Try best to clear it */
 				opal_pci_eeh_freeze_clear(phb->opal_id,
 					frozen_pe_no,
 					OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);

arch/powerpc/platforms/powernv/opal-hmi.c+175−2

@@ -35,9 +35,134 @@ struct OpalHmiEvtNode { · 34 unmodified lines
35	struct list_head list;	35	struct list_head list;
36	struct OpalHMIEvent hmi_evt;	36	struct OpalHMIEvent hmi_evt;
37	};	37	};
		38
		39	struct xstop_reason {
		40	uint32_t xstop_reason;
		41	const char *unit_failed;
		42	const char *description;
		43	};
		44
38	static LIST_HEAD(opal_hmi_evt_list);	45	static LIST_HEAD(opal_hmi_evt_list);
39	static DEFINE_SPINLOCK(opal_hmi_evt_lock);	46	static DEFINE_SPINLOCK(opal_hmi_evt_lock);
40		47
		48	static void print_core_checkstop_reason(const char *level,
		49	struct OpalHMIEvent *hmi_evt)
		50	{
		51	int i;
		52	static const struct xstop_reason xstop_reason[] = {
		53	{ CORE_CHECKSTOP_IFU_REGFILE, "IFU",
		54	"RegFile core check stop" },
		55	{ CORE_CHECKSTOP_IFU_LOGIC, "IFU", "Logic core check stop" },
		56	{ CORE_CHECKSTOP_PC_DURING_RECOV, "PC",
		57	"Core checkstop during recovery" },
		58	{ CORE_CHECKSTOP_ISU_REGFILE, "ISU",
		59	"RegFile core check stop (mapper error)" },
		60	{ CORE_CHECKSTOP_ISU_LOGIC, "ISU", "Logic core check stop" },
		61	{ CORE_CHECKSTOP_FXU_LOGIC, "FXU", "Logic core check stop" },
		62	{ CORE_CHECKSTOP_VSU_LOGIC, "VSU", "Logic core check stop" },
		63	{ CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE, "PC",
		64	"Recovery in maintenance mode" },
		65	{ CORE_CHECKSTOP_LSU_REGFILE, "LSU",
		66	"RegFile core check stop" },
		67	{ CORE_CHECKSTOP_PC_FWD_PROGRESS, "PC",
		68	"Forward Progress Error" },
		69	{ CORE_CHECKSTOP_LSU_LOGIC, "LSU", "Logic core check stop" },
		70	{ CORE_CHECKSTOP_PC_LOGIC, "PC", "Logic core check stop" },
		71	{ CORE_CHECKSTOP_PC_HYP_RESOURCE, "PC",
		72	"Hypervisor Resource error - core check stop" },
		73	{ CORE_CHECKSTOP_PC_HANG_RECOV_FAILED, "PC",
		74	"Hang Recovery Failed (core check stop)" },
		75	{ CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED, "PC",
		76	"Ambiguous Hang Detected (unknown source)" },
		77	{ CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ, "PC",
		78	"Debug Trigger Error inject" },
		79	{ CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ, "PC",
		80	"Hypervisor check stop via SPRC/SPRD" },
		81	};
		82
		83	/* Validity check */
		84	if (!hmi_evt->u.xstop_error.xstop_reason) {
		85	printk("%s Unknown Core check stop.\n", level);
		86	return;
		87	}
		88
		89	printk("%s CPU PIR: %08x\n", level,
		90	be32_to_cpu(hmi_evt->u.xstop_error.u.pir));
		91	for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
		92	if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
		93	xstop_reason[i].xstop_reason)
		94	printk("%s [Unit: %-3s] %s\n", level,
		95	xstop_reason[i].unit_failed,
		96	xstop_reason[i].description);
		97	}
		98
		99	static void print_nx_checkstop_reason(const char *level,
		100	struct OpalHMIEvent *hmi_evt)
		101	{
		102	int i;
		103	static const struct xstop_reason xstop_reason[] = {
		104	{ NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine",
		105	"SHM invalid state error" },
		106	{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine",
		107	"DMA invalid state error bit 15" },
		108	{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine",
		109	"DMA invalid state error bit 16" },
		110	{ NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine",
		111	"Channel 0 invalid state error" },
		112	{ NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR, "DMA & Engine",
		113	"Channel 1 invalid state error" },
		114	{ NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR, "DMA & Engine",
		115	"Channel 2 invalid state error" },
		116	{ NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR, "DMA & Engine",
		117	"Channel 3 invalid state error" },
		118	{ NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR, "DMA & Engine",
		119	"Channel 4 invalid state error" },
		120	{ NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR, "DMA & Engine",
		121	"Channel 5 invalid state error" },
		122	{ NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR, "DMA & Engine",
		123	"Channel 6 invalid state error" },
		124	{ NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR, "DMA & Engine",
		125	"Channel 7 invalid state error" },
		126	{ NX_CHECKSTOP_DMA_CRB_UE, "DMA & Engine",
		127	"UE error on CRB(CSB address, CCB)" },
		128	{ NX_CHECKSTOP_DMA_CRB_SUE, "DMA & Engine",
		129	"SUE error on CRB(CSB address, CCB)" },
		130	{ NX_CHECKSTOP_PBI_ISN_UE, "PowerBus Interface",
		131	"CRB Kill ISN received while holding ISN with UE error" },
		132	};
		133
		134	/* Validity check */
		135	if (!hmi_evt->u.xstop_error.xstop_reason) {
		136	printk("%s Unknown NX check stop.\n", level);
		137	return;
		138	}
		139
		140	printk("%s NX checkstop on CHIP ID: %x\n", level,
		141	be32_to_cpu(hmi_evt->u.xstop_error.u.chip_id));
		142	for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
		143	if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
		144	xstop_reason[i].xstop_reason)
		145	printk("%s [Unit: %-3s] %s\n", level,
		146	xstop_reason[i].unit_failed,
		147	xstop_reason[i].description);
		148	}
		149
		150	static void print_checkstop_reason(const char *level,
		151	struct OpalHMIEvent *hmi_evt)
		152	{
		153	switch (hmi_evt->u.xstop_error.xstop_type) {
		154	case CHECKSTOP_TYPE_CORE:
		155	print_core_checkstop_reason(level, hmi_evt);
		156	break;
		157	case CHECKSTOP_TYPE_NX:
		158	print_nx_checkstop_reason(level, hmi_evt);
		159	break;
		160	case CHECKSTOP_TYPE_UNKNOWN:
		161	printk("%s Unknown Malfunction Alert.\n", level);
		162	break;
		163	}
		164	}
		165
41	static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)	166	static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
42	{	167	{
43	const char level, sevstr, *error_info;	168	const char level, sevstr, *error_info;
@@ -95,6 +220,13 @@ static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt) · 51 unmodified lines
95	(hmi_evt->type == OpalHMI_ERROR_TFMR_PARITY))	220	(hmi_evt->type == OpalHMI_ERROR_TFMR_PARITY))
96	printk("%s TFMR: %016llx\n", level,	221	printk("%s TFMR: %016llx\n", level,
97	be64_to_cpu(hmi_evt->tfmr));	222	be64_to_cpu(hmi_evt->tfmr));
		223
		224	if (hmi_evt->version < OpalHMIEvt_V2)
		225	return;
		226
		227	/* OpalHMIEvt_V2 and above provides reason for malfunction alert. */
		228	if (hmi_evt->type == OpalHMI_ERROR_MALFUNC_ALERT)
		229	print_checkstop_reason(level, hmi_evt);
98	}	230	}
99		231
100	static void hmi_event_handler(struct work_struct *work)	232	static void hmi_event_handler(struct work_struct *work)
@@ -103,6 +235,8 @@ static void hmi_event_handler(struct work_struct *work) · 2 unmodified lines
103	struct OpalHMIEvent *hmi_evt;	235	struct OpalHMIEvent *hmi_evt;
104	struct OpalHmiEvtNode *msg_node;	236	struct OpalHmiEvtNode *msg_node;
105	uint8_t disposition;	237	uint8_t disposition;
		238	struct opal_msg msg;
		239	int unrecoverable = 0;
106		240
107	spin_lock_irqsave(&opal_hmi_evt_lock, flags);	241	spin_lock_irqsave(&opal_hmi_evt_lock, flags);
108	while (!list_empty(&opal_hmi_evt_list)) {	242	while (!list_empty(&opal_hmi_evt_list)) {
@@ -118,14 +252,53 @@ static void hmi_event_handler(struct work_struct *work) · 9 unmodified lines
118		252
119	/*	253	/*
120	* Check if HMI event has been recovered or not. If not	254	* Check if HMI event has been recovered or not. If not
121	* then we can't continue, invoke panic.	255	* then kernel can't continue, we need to panic.
		256	* But before we do that, display all the HMI event
		257	* available on the list and set unrecoverable flag to 1.
122	*/	258	*/
123	if (disposition != OpalHMI_DISPOSITION_RECOVERED)	259	if (disposition != OpalHMI_DISPOSITION_RECOVERED)
124	panic("Unrecoverable HMI exception");	260	unrecoverable = 1;
125		261
126	spin_lock_irqsave(&opal_hmi_evt_lock, flags);	262	spin_lock_irqsave(&opal_hmi_evt_lock, flags);
127	}	263	}
128	spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);	264	spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);
		265
		266	if (unrecoverable) {
		267	int ret;
		268
		269	/* Pull all HMI events from OPAL before we panic. */
		270	while (opal_get_msg(__pa(&msg), sizeof(msg)) == OPAL_SUCCESS) {
		271	u32 type;
		272
		273	type = be32_to_cpu(msg.msg_type);
		274
		275	/* skip if not HMI event */
		276	if (type != OPAL_MSG_HMI_EVT)
		277	continue;
		278
		279	/* HMI event info starts from param[0] */
		280	hmi_evt = (struct OpalHMIEvent *)&msg.params[0];
		281	print_hmi_event_info(hmi_evt);
		282	}
		283
		284	/*
		285	* Unrecoverable HMI exception. We need to inform BMC/OCC
		286	* about this error so that it can collect relevant data
		287	* for error analysis before rebooting.
		288	*/
		289	ret = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR,
		290	"Unrecoverable HMI exception");
		291	if (ret == OPAL_UNSUPPORTED) {
		292	pr_emerg("Reboot type %d not supported\n",
		293	OPAL_REBOOT_PLATFORM_ERROR);
		294	}
		295
		296	/*
		297	* Fall through and panic if opal_cec_reboot2() returns
		298	* OPAL_UNSUPPORTED.
		299	*/
		300	panic("Unrecoverable HMI exception");
		301	}
129	}	302	}
130		303
131	static DECLARE_WORK(hmi_event_work, hmi_event_handler);	304	static DECLARE_WORK(hmi_event_work, hmi_event_handler);

arch/powerpc/platforms/powernv/opal-power.c+130−17

@@ -9,9 +9,12 @@ · 8 unmodified lines
9	* 2 of the License, or (at your option) any later version.	9	* 2 of the License, or (at your option) any later version.
10	*/	10	*/
11		11
		12	#define pr_fmt(fmt) "opal-power: " fmt
		13
12	#include <linux/kernel.h>	14	#include <linux/kernel.h>
13	#include <linux/reboot.h>	15	#include <linux/reboot.h>
14	#include <linux/notifier.h>	16	#include <linux/notifier.h>
		17	#include <linux/of.h>
15		18
16	#include <asm/opal.h>	19	#include <asm/opal.h>
17	#include <asm/machdep.h>	20	#include <asm/machdep.h>
@@ -19,30 +22,116 @@ · 1 unmodified line
19	#define SOFT_OFF 0x00	22	#define SOFT_OFF 0x00
20	#define SOFT_REBOOT 0x01	23	#define SOFT_REBOOT 0x01
21		24
		25	/* Detect EPOW event */
		26	static bool detect_epow(void)
		27	{
		28	u16 epow;
		29	int i, rc;
		30	__be16 epow_classes;
		31	__be16 opal_epow_status[OPAL_SYSEPOW_MAX] = {0};
		32
		33	/*
		34	* Check for EPOW event. Kernel sends supported EPOW classes info
		35	* to OPAL. OPAL returns EPOW info along with classes present.
		36	*/
		37	epow_classes = cpu_to_be16(OPAL_SYSEPOW_MAX);
		38	rc = opal_get_epow_status(opal_epow_status, &epow_classes);
		39	if (rc != OPAL_SUCCESS) {
		40	pr_err("Failed to get EPOW event information\n");
		41	return false;
		42	}
		43
		44	/* Look for EPOW events present */
		45	for (i = 0; i < be16_to_cpu(epow_classes); i++) {
		46	epow = be16_to_cpu(opal_epow_status[i]);
		47
		48	/* Filter events which do not need shutdown. */
		49	if (i == OPAL_SYSEPOW_POWER)
		50	epow &= ~(OPAL_SYSPOWER_CHNG \| OPAL_SYSPOWER_FAIL \|
		51	OPAL_SYSPOWER_INCL);
		52	if (epow)
		53	return true;
		54	}
		55
		56	return false;
		57	}
		58
		59	/* Check for existing EPOW, DPO events */
		60	static bool poweroff_pending(void)
		61	{
		62	int rc;
		63	__be64 opal_dpo_timeout;
		64
		65	/* Check for DPO event */
		66	rc = opal_get_dpo_status(&opal_dpo_timeout);
		67	if (rc == OPAL_SUCCESS) {
		68	pr_info("Existing DPO event detected.\n");
		69	return true;
		70	}
		71
		72	/* Check for EPOW event */
		73	if (detect_epow()) {
		74	pr_info("Existing EPOW event detected.\n");
		75	return true;
		76	}
		77
		78	return false;
		79	}
		80
		81	/* OPAL power-control events notifier */
22	static int opal_power_control_event(struct notifier_block *nb,	82	static int opal_power_control_event(struct notifier_block *nb,
23	unsigned long msg_type, void *msg)	83	unsigned long msg_type, void *msg)
24	{	84	{
25	struct opal_msg *power_msg = msg;
26	uint64_t type;	85	uint64_t type;
27		86
28	type = be64_to_cpu(power_msg->params[0]);	87	switch (msg_type) {
29		88	case OPAL_MSG_EPOW:
30	switch (type) {	89	if (detect_epow()) {
31	case SOFT_REBOOT:	90	pr_info("EPOW msg received. Powering off system\n");
32	pr_info("OPAL: reboot requested\n");	91	orderly_poweroff(true);
33	orderly_reboot();	92	}
34	break;	93	break;
35	case SOFT_OFF:	94	case OPAL_MSG_DPO:
36	pr_info("OPAL: poweroff requested\n");	95	pr_info("DPO msg received. Powering off system\n");
37	orderly_poweroff(true);	96	orderly_poweroff(true);
38	break;	97	break;
		98	case OPAL_MSG_SHUTDOWN:
		99	type = be64_to_cpu(((struct opal_msg *)msg)->params[0]);
		100	switch (type) {
		101	case SOFT_REBOOT:
		102	pr_info("Reboot requested\n");
		103	orderly_reboot();
		104	break;
		105	case SOFT_OFF:
		106	pr_info("Poweroff requested\n");
		107	orderly_poweroff(true);
		108	break;
		109	default:
		110	pr_err("Unknown power-control type %llu\n", type);
		111	}
		112	break;
39	default:	113	default:
40	pr_err("OPAL: power control type unexpected %016llx\n", type);	114	pr_err("Unknown OPAL message type %lu\n", msg_type);
41	}	115	}
42		116
43	return 0;	117	return 0;
44	}	118	}
45		119
		120	/* OPAL EPOW event notifier block */
		121	static struct notifier_block opal_epow_nb = {
		122	.notifier_call = opal_power_control_event,
		123	.next = NULL,
		124	.priority = 0,
		125	};
		126
		127	/* OPAL DPO event notifier block */
		128	static struct notifier_block opal_dpo_nb = {
		129	.notifier_call = opal_power_control_event,
		130	.next = NULL,
		131	.priority = 0,
		132	};
		133
		134	/* OPAL power-control event notifier block */
46	static struct notifier_block opal_power_control_nb = {	135	static struct notifier_block opal_power_control_nb = {
47	.notifier_call = opal_power_control_event,	136	.notifier_call = opal_power_control_event,
48	.next = NULL,	137	.next = NULL,
@@ -51,16 +140,40 @@ static struct notifier_block opal_power_control_nb = { · 2 unmodified lines
51		140
52	static int __init opal_power_control_init(void)	141	static int __init opal_power_control_init(void)
53	{	142	{
54	int ret;	143	int ret, supported = 0;
		144	struct device_node *np;
55		145
		146	/* Register OPAL power-control events notifier */
56	ret = opal_message_notifier_register(OPAL_MSG_SHUTDOWN,	147	ret = opal_message_notifier_register(OPAL_MSG_SHUTDOWN,
57	&opal_power_control_nb);	148	&opal_power_control_nb);
58	if (ret) {	149	if (ret)
59	pr_err("%s: Can't register OPAL event notifier (%d)\n",	150	pr_err("Failed to register SHUTDOWN notifier, ret = %d\n", ret);
60	__func__, ret);	151
61	return ret;	152	/* Determine OPAL EPOW, DPO support */
		153	np = of_find_node_by_path("/ibm,opal/epow");
		154	if (np) {
		155	supported = of_device_is_compatible(np, "ibm,opal-v3-epow");
		156	of_node_put(np);
62	}	157	}
63		158
		159	if (!supported)
		160	return 0;
		161	pr_info("OPAL EPOW, DPO support detected.\n");
		162
		163	/* Register EPOW event notifier */
		164	ret = opal_message_notifier_register(OPAL_MSG_EPOW, &opal_epow_nb);
		165	if (ret)
		166	pr_err("Failed to register EPOW notifier, ret = %d\n", ret);
		167
		168	/* Register DPO event notifier */
		169	ret = opal_message_notifier_register(OPAL_MSG_DPO, &opal_dpo_nb);
		170	if (ret)
		171	pr_err("Failed to register DPO notifier, ret = %d\n", ret);
		172
		173	/* Check for any pending EPOW or DPO events. */
		174	if (poweroff_pending())
		175	orderly_poweroff(true);
		176
64	return 0;	177	return 0;
65	}	178	}
66	machine_subsys_initcall(powernv, opal_power_control_init);	179	machine_subsys_initcall(powernv, opal_power_control_init);

arch/powerpc/platforms/powernv/opal-wrappers.S+4−0

 OPAL_CALL(opal_rtc_write,			OPAL_RTC_WRITE);
 OPAL_CALL(opal_cec_power_down,			OPAL_CEC_POWER_DOWN);
 OPAL_CALL(opal_cec_reboot,			OPAL_CEC_REBOOT);
+OPAL_CALL(opal_cec_reboot2,			OPAL_CEC_REBOOT2);
 OPAL_CALL(opal_read_nvram,			OPAL_READ_NVRAM);
 OPAL_CALL(opal_write_nvram,			OPAL_WRITE_NVRAM);
 OPAL_CALL(opal_handle_interrupt,		OPAL_HANDLE_INTERRUPT);
 OPAL_CALL(opal_pci_mask_pe_error,		OPAL_PCI_MASK_PE_ERROR);
 OPAL_CALL(opal_set_slot_led_status,		OPAL_SET_SLOT_LED_STATUS);
 OPAL_CALL(opal_get_epow_status,			OPAL_GET_EPOW_STATUS);
+OPAL_CALL(opal_get_dpo_status,			OPAL_GET_DPO_STATUS);
 OPAL_CALL(opal_set_system_attention_led,	OPAL_SET_SYSTEM_ATTENTION_LED);
 OPAL_CALL(opal_pci_next_error,			OPAL_PCI_NEXT_ERROR);
 OPAL_CALL(opal_pci_poll,			OPAL_PCI_POLL);
 OPAL_CALL(opal_flash_write,			OPAL_FLASH_WRITE);
 OPAL_CALL(opal_flash_erase,			OPAL_FLASH_ERASE);
 OPAL_CALL(opal_prd_msg,				OPAL_PRD_MSG);
+OPAL_CALL(opal_leds_get_ind,			OPAL_LEDS_GET_INDICATOR);
+OPAL_CALL(opal_leds_set_ind,			OPAL_LEDS_SET_INDICATOR);

arch/powerpc/platforms/powernv/opal.c+46−1

@@ -441,6 +441,7 @@ static int opal_recover_mce(struct pt_regs *regs, · 440 unmodified lines
441	int opal_machine_check(struct pt_regs *regs)	441	int opal_machine_check(struct pt_regs *regs)
442	{	442	{
443	struct machine_check_event evt;	443	struct machine_check_event evt;
		444	int ret;
444		445
445	if (!get_mce_event(&evt, MCE_EVENT_RELEASE))	446	if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
446	return 0;	447	return 0;
@@ -455,6 +456,40 @@ int opal_machine_check(struct pt_regs *regs) · 8 unmodified lines
455		456
456	if (opal_recover_mce(regs, &evt))	457	if (opal_recover_mce(regs, &evt))
457	return 1;	458	return 1;
		459
		460	/*
		461	* Unrecovered machine check, we are heading to panic path.
		462	*
		463	* We may have hit this MCE in very early stage of kernel
		464	* initialization even before opal-prd has started running. If
		465	* this is the case then this MCE error may go un-noticed or
		466	* un-analyzed if we go down panic path. We need to inform
		467	* BMC/OCC about this error so that they can collect relevant
		468	* data for error analysis before rebooting.
		469	* Use opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR) to do so.
		470	* This function may not return on BMC based system.
		471	*/
		472	ret = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR,
		473	"Unrecoverable Machine Check exception");
		474	if (ret == OPAL_UNSUPPORTED) {
		475	pr_emerg("Reboot type %d not supported\n",
		476	OPAL_REBOOT_PLATFORM_ERROR);
		477	}
		478
		479	/*
		480	* We reached here. There can be three possibilities:
		481	* 1. We are running on a firmware level that do not support
		482	* opal_cec_reboot2()
		483	* 2. We are running on a firmware level that do not support
		484	* OPAL_REBOOT_PLATFORM_ERROR reboot type.
		485	* 3. We are running on FSP based system that does not need opal
		486	* to trigger checkstop explicitly for error analysis. The FSP
		487	* PRD component would have already got notified about this
		488	* error through other channels.
		489	*
		490	* In any case, let us just fall through. We anyway heading
		491	* down to panic path.
		492	*/
458	return 0;	493	return 0;
459	}	494	}
460		495
@@ -648,7 +683,7 @@ static void opal_init_heartbeat(void) · 187 unmodified lines
648		683
649	static int __init opal_init(void)	684	static int __init opal_init(void)
650	{	685	{
651	struct device_node np, consoles;	686	struct device_node np, consoles, *leds;
652	int rc;	687	int rc;
653		688
654	opal_node = of_find_node_by_path("/ibm,opal");	689	opal_node = of_find_node_by_path("/ibm,opal");
@@ -689,6 +724,13 @@ static int __init opal_init(void) · 34 unmodified lines
689	/* Setup a heatbeat thread if requested by OPAL */	724	/* Setup a heatbeat thread if requested by OPAL */
690	opal_init_heartbeat();	725	opal_init_heartbeat();
691		726
		727	/* Create leds platform devices */
		728	leds = of_find_node_by_path("/ibm,opal/leds");
		729	if (leds) {
		730	of_platform_device_create(leds, "opal_leds", NULL);
		731	of_node_put(leds);
		732	}
		733
692	/* Create "opal" kobject under /sys/firmware */	734	/* Create "opal" kobject under /sys/firmware */
693	rc = opal_sysfs_init();	735	rc = opal_sysfs_init();
694	if (rc == 0) {	736	if (rc == 0) {
@@ -841,3 +883,6 @@ EXPORT_SYMBOL_GPL(opal_rtc_write); · 146 unmodified lines
841	EXPORT_SYMBOL_GPL(opal_tpo_read);	883	EXPORT_SYMBOL_GPL(opal_tpo_read);
842	EXPORT_SYMBOL_GPL(opal_tpo_write);	884	EXPORT_SYMBOL_GPL(opal_tpo_write);
843	EXPORT_SYMBOL_GPL(opal_i2c_request);	885	EXPORT_SYMBOL_GPL(opal_i2c_request);
		886	/* Export these symbols for PowerNV LED class driver */
		887	EXPORT_SYMBOL_GPL(opal_leds_get_ind);
		888	EXPORT_SYMBOL_GPL(opal_leds_set_ind);

arch/powerpc/platforms/powernv/pci-ioda.c+59−88

@@ -140,11 +140,9 @@ static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) · 139 unmodified lines
140	return;	140	return;
141	}	141	}
142		142
143	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) {	143	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
144	pr_warn("%s: PE %d was assigned on PHB#%x\n",	144	pr_debug("%s: PE %d was reserved on PHB#%x\n",
145	__func__, pe_no, phb->hose->global_number);	145	__func__, pe_no, phb->hose->global_number);
146	return;
147	}
148		146
149	phb->ioda.pe_array[pe_no].phb = phb;	147	phb->ioda.pe_array[pe_no].phb = phb;
150	phb->ioda.pe_array[pe_no].pe_number = pe_no;	148	phb->ioda.pe_array[pe_no].pe_number = pe_no;
@@ -231,61 +229,60 @@ fail: · 80 unmodified lines
231	return -EIO;	229	return -EIO;
232	}	230	}
233		231
234	static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb)	232	static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
		233	unsigned long *pe_bitmap)
235	{	234	{
236	resource_size_t sgsz = phb->ioda.m64_segsize;	235	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
237	struct pci_dev *pdev;	236	struct pnv_phb *phb = hose->private_data;
238	struct resource *r;	237	struct resource *r;
239	int base, step, i;	238	resource_size_t base, sgsz, start, end;
240		239	int segno, i;
241	/*	240
242	* Root bus always has full M64 range and root port has	241	base = phb->ioda.m64_base;
243	* M64 range used in reality. So we're checking root port	242	sgsz = phb->ioda.m64_segsize;
244	* instead of root bus.	243	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
245	*/	244	r = &pdev->resource[i];
246	list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) {	245	if (!r->parent \|\| !pnv_pci_is_mem_pref_64(r->flags))
247	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {	246	continue;
248	r = &pdev->resource[PCI_BRIDGE_RESOURCES + i];
249	if (!r->parent \|\|
250	!pnv_pci_is_mem_pref_64(r->flags))
251	continue;
252		247
253	base = (r->start - phb->ioda.m64_base) / sgsz;	248	start = _ALIGN_DOWN(r->start - base, sgsz);
254	for (step = 0; step < resource_size(r) / sgsz; step++)	249	end = _ALIGN_UP(r->end - base, sgsz);
255	pnv_ioda_reserve_pe(phb, base + step);	250	for (segno = start / sgsz; segno < end / sgsz; segno++) {
		251	if (pe_bitmap)
		252	set_bit(segno, pe_bitmap);
		253	else
		254	pnv_ioda_reserve_pe(phb, segno);
256	}	255	}
257	}	256	}
258	}	257	}
259		258
260	static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb,	259	static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
261	struct pci_bus *bus, int all)	260	unsigned long *pe_bitmap,
		261	bool all)
262	{	262	{
263	resource_size_t segsz = phb->ioda.m64_segsize;
264	struct pci_dev *pdev;	263	struct pci_dev *pdev;
265	struct resource *r;	264
		265	list_for_each_entry(pdev, &bus->devices, bus_list) {
		266	pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
		267
		268	if (all && pdev->subordinate)
		269	pnv_ioda2_reserve_m64_pe(pdev->subordinate,
		270	pe_bitmap, all);
		271	}
		272	}
		273
		274	static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
		275	{
		276	struct pci_controller *hose = pci_bus_to_host(bus);
		277	struct pnv_phb *phb = hose->private_data;
266	struct pnv_ioda_pe master_pe, pe;	278	struct pnv_ioda_pe master_pe, pe;
267	unsigned long size, *pe_alloc;	279	unsigned long size, *pe_alloc;
268	bool found;	280	int i;
269	int start, i, j;
270		281
271	/* Root bus shouldn't use M64 */	282	/* Root bus shouldn't use M64 */
272	if (pci_is_root_bus(bus))	283	if (pci_is_root_bus(bus))
273	return IODA_INVALID_PE;	284	return IODA_INVALID_PE;
274		285
275	/* We support only one M64 window on each bus */
276	found = false;
277	pci_bus_for_each_resource(bus, r, i) {
278	if (r && r->parent &&
279	pnv_pci_is_mem_pref_64(r->flags)) {
280	found = true;
281	break;
282	}
283	}
284
285	/* No M64 window found ? */
286	if (!found)
287	return IODA_INVALID_PE;
288
289	/* Allocate bitmap */	286	/* Allocate bitmap */
290	size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));	287	size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
291	pe_alloc = kzalloc(size, GFP_KERNEL);	288	pe_alloc = kzalloc(size, GFP_KERNEL);
@@ -295,35 +292,8 @@ static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, · 3 unmodified lines
295	return IODA_INVALID_PE;	292	return IODA_INVALID_PE;
296	}	293	}
297		294
298	/*	295	/* Figure out reserved PE numbers by the PE */
299	* Figure out reserved PE numbers by the PE	296	pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
300	* the its child PEs.
301	*/
302	start = (r->start - phb->ioda.m64_base) / segsz;
303	for (i = 0; i < resource_size(r) / segsz; i++)
304	set_bit(start + i, pe_alloc);
305
306	if (all)
307	goto done;
308
309	/*
310	* If the PE doesn't cover all subordinate buses,
311	* we need subtract from reserved PEs for children.
312	*/
313	list_for_each_entry(pdev, &bus->devices, bus_list) {
314	if (!pdev->subordinate)
315	continue;
316
317	pci_bus_for_each_resource(pdev->subordinate, r, i) {
318	if (!r \|\| !r->parent \|\|
319	!pnv_pci_is_mem_pref_64(r->flags))
320	continue;
321
322	start = (r->start - phb->ioda.m64_base) / segsz;
323	for (j = 0; j < resource_size(r) / segsz ; j++)
324	clear_bit(start + j, pe_alloc);
325	}
326	}
327		297
328	/*	298	/*
329	* the current bus might not own M64 window and that's all	299	* the current bus might not own M64 window and that's all
@@ -339,7 +309,6 @@ static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, · 9 unmodified lines
339	* Figure out the master PE and put all slave PEs to master	309	* Figure out the master PE and put all slave PEs to master
340	* PE's list to form compound PE.	310	* PE's list to form compound PE.
341	*/	311	*/
342	done:
343	master_pe = NULL;	312	master_pe = NULL;
344	i = -1;	313	i = -1;
345	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <	314	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
@@ -653,7 +622,7 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb, · 307 unmodified lines
653	pdev = pe->pdev->bus->self;	622	pdev = pe->pdev->bus->self;
654	#ifdef CONFIG_PCI_IOV	623	#ifdef CONFIG_PCI_IOV
655	else if (pe->flags & PNV_IODA_PE_VF)	624	else if (pe->flags & PNV_IODA_PE_VF)
656	pdev = pe->parent_dev->bus->self;	625	pdev = pe->parent_dev;
657	#endif /* CONFIG_PCI_IOV */	626	#endif /* CONFIG_PCI_IOV */
658	while (pdev) {	627	while (pdev) {
659	struct pci_dn *pdn = pci_get_pdn(pdev);	628	struct pci_dn *pdn = pci_get_pdn(pdev);
@@ -732,7 +701,7 @@ static int pnv_ioda_deconfigure_pe(struct pnv_phb phb, struct pnv_ioda_pe pe) · 72 unmodified lines
732	parent = parent->bus->self;	701	parent = parent->bus->self;
733	}	702	}
734		703
735	opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number,	704	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
736	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);	705	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
737		706
738	/* Disassociate PE in PELT */	707	/* Disassociate PE in PELT */
@@ -946,8 +915,9 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) · 207 unmodified lines
946	res2 = *res;	915	res2 = *res;
947	res->start += size * offset;	916	res->start += size * offset;
948		917
949	dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",	918	dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
950	i, &res2, res, num_vfs, offset);	919	i, &res2, res, (offset > 0) ? "En" : "Dis",
		920	num_vfs, offset);
951	pci_update_resource(dev, i + PCI_IOV_RESOURCES);	921	pci_update_resource(dev, i + PCI_IOV_RESOURCES);
952	}	922	}
953	return 0;	923	return 0;
@@ -1050,7 +1020,7 @@ static void pnv_ioda_setup_same_PE(struct pci_bus bus, struct pnv_ioda_pe pe) · 96 unmodified lines
1050	* subordinate PCI devices and buses. The second type of PE is normally	1020	* subordinate PCI devices and buses. The second type of PE is normally
1051	* orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.	1021	* orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1052	*/	1022	*/
1053	static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)	1023	static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1054	{	1024	{
1055	struct pci_controller *hose = pci_bus_to_host(bus);	1025	struct pci_controller *hose = pci_bus_to_host(bus);
1056	struct pnv_phb *phb = hose->private_data;	1026	struct pnv_phb *phb = hose->private_data;
@@ -1059,7 +1029,7 @@ static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) · 2 unmodified lines
1059		1029
1060	/* Check if PE is determined by M64 */	1030	/* Check if PE is determined by M64 */
1061	if (phb->pick_m64_pe)	1031	if (phb->pick_m64_pe)
1062	pe_num = phb->pick_m64_pe(phb, bus, all);	1032	pe_num = phb->pick_m64_pe(bus, all);
1063		1033
1064	/* The PE number isn't pinned by M64 */	1034	/* The PE number isn't pinned by M64 */
1065	if (pe_num == IODA_INVALID_PE)	1035	if (pe_num == IODA_INVALID_PE)
@@ -1117,12 +1087,12 @@ static void pnv_ioda_setup_PEs(struct pci_bus *bus) · 51 unmodified lines
1117	{	1087	{
1118	struct pci_dev *dev;	1088	struct pci_dev *dev;
1119		1089
1120	pnv_ioda_setup_bus_PE(bus, 0);	1090	pnv_ioda_setup_bus_PE(bus, false);
1121		1091
1122	list_for_each_entry(dev, &bus->devices, bus_list) {	1092	list_for_each_entry(dev, &bus->devices, bus_list) {
1123	if (dev->subordinate) {	1093	if (dev->subordinate) {
1124	if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)	1094	if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1125	pnv_ioda_setup_bus_PE(dev->subordinate, 1);	1095	pnv_ioda_setup_bus_PE(dev->subordinate, true);
1126	else	1096	else
1127	pnv_ioda_setup_PEs(dev->subordinate);	1097	pnv_ioda_setup_PEs(dev->subordinate);
1128	}	1098	}
@@ -1147,7 +1117,7 @@ static void pnv_pci_ioda_setup_PEs(void) · 18 unmodified lines
1147		1117
1148	/* M64 layout might affect PE allocation */	1118	/* M64 layout might affect PE allocation */
1149	if (phb->reserve_m64_pe)	1119	if (phb->reserve_m64_pe)
1150	phb->reserve_m64_pe(phb);	1120	phb->reserve_m64_pe(hose->bus, NULL, true);
1151		1121
1152	pnv_ioda_setup_PEs(hose->bus);	1122	pnv_ioda_setup_PEs(hose->bus);
1153	}	1123	}
@@ -1590,6 +1560,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb phb, struct pci_dev pdev · 436 unmodified lines
1590		1560
1591	pe = &phb->ioda.pe_array[pdn->pe_number];	1561	pe = &phb->ioda.pe_array[pdn->pe_number];
1592	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);	1562	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
		1563	set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1593	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);	1564	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1594	/*	1565	/*
1595	* Note: iommu_add_device() will fail here as	1566	* Note: iommu_add_device() will fail here as
@@ -1620,19 +1591,18 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) · 24 unmodified lines
1620	if (bypass) {	1591	if (bypass) {
1621	dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");	1592	dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1622	set_dma_ops(&pdev->dev, &dma_direct_ops);	1593	set_dma_ops(&pdev->dev, &dma_direct_ops);
1623	set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1624	} else {	1594	} else {
1625	dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");	1595	dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1626	set_dma_ops(&pdev->dev, &dma_iommu_ops);	1596	set_dma_ops(&pdev->dev, &dma_iommu_ops);
1627	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1628	}	1597	}
1629	*pdev->dev.dma_mask = dma_mask;	1598	*pdev->dev.dma_mask = dma_mask;
1630	return 0;	1599	return 0;
1631	}	1600	}
1632		1601
1633	static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb,	1602	static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1634	struct pci_dev *pdev)
1635	{	1603	{
		1604	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
		1605	struct pnv_phb *phb = hose->private_data;
1636	struct pci_dn *pdn = pci_get_pdn(pdev);	1606	struct pci_dn *pdn = pci_get_pdn(pdev);
1637	struct pnv_ioda_pe *pe;	1607	struct pnv_ioda_pe *pe;
1638	u64 end, mask;	1608	u64 end, mask;
@@ -1659,6 +1629,7 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, · 20 unmodified lines
1659		1629
1660	list_for_each_entry(dev, &bus->devices, bus_list) {	1630	list_for_each_entry(dev, &bus->devices, bus_list) {
1661	set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);	1631	set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
		1632	set_dma_offset(&dev->dev, pe->tce_bypass_base);
1662	iommu_add_device(&dev->dev);	1633	iommu_add_device(&dev->dev);
1663		1634
1664	if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)	1635	if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
@@ -3057,6 +3028,7 @@ static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { · 1392 unmodified lines
3057	.window_alignment = pnv_pci_window_alignment,	3028	.window_alignment = pnv_pci_window_alignment,
3058	.reset_secondary_bus = pnv_pci_reset_secondary_bus,	3029	.reset_secondary_bus = pnv_pci_reset_secondary_bus,
3059	.dma_set_mask = pnv_pci_ioda_dma_set_mask,	3030	.dma_set_mask = pnv_pci_ioda_dma_set_mask,
		3031	.dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3060	.shutdown = pnv_pci_ioda_shutdown,	3032	.shutdown = pnv_pci_ioda_shutdown,
3061	};	3033	};
3062		3034
@@ -3203,7 +3175,6 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, · 140 unmodified lines
3203		3175
3204	/* Setup TCEs */	3176	/* Setup TCEs */
3205	phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;	3177	phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3206	phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask;
3207		3178
3208	/* Setup MSI support */	3179	/* Setup MSI support */
3209	pnv_pci_init_ioda_msis(phb);	3180	pnv_pci_init_ioda_msis(phb);

arch/powerpc/platforms/powernv/pci.c+0−11

@@ -761,17 +761,6 @@ void pnv_pci_dma_dev_setup(struct pci_dev *pdev) · 760 unmodified lines
761	phb->dma_dev_setup(phb, pdev);	761	phb->dma_dev_setup(phb, pdev);
762	}	762	}
763		763
764	u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev)
765	{
766	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
767	struct pnv_phb *phb = hose->private_data;
768
769	if (phb && phb->dma_get_required_mask)
770	return phb->dma_get_required_mask(phb, pdev);
771
772	return __dma_get_required_mask(&pdev->dev);
773	}
774
775	void pnv_pci_shutdown(void)	764	void pnv_pci_shutdown(void)
776	{	765	{
777	struct pci_controller *hose;	766	struct pci_controller *hose;

arch/powerpc/platforms/powernv/pci.h+3−4

 			 unsigned int hwirq, unsigned int virq,
 			 unsigned int is_64, struct msi_msg *msg);
 	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
-	u64 (*dma_get_required_mask)(struct pnv_phb *phb,
-				     struct pci_dev *pdev);
 	void (*fixup_phb)(struct pci_controller *hose);
 	u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
 	int (*init_m64)(struct pnv_phb *phb);
-	void (*reserve_m64_pe)(struct pnv_phb *phb);
+	void (*reserve_m64_pe)(struct pci_bus *bus,
-	int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
+			       unsigned long *pe_bitmap, bool all);
+	int (*pick_m64_pe)(struct pci_bus *bus, bool all);
 	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
 	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
 	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

arch/powerpc/platforms/powernv/powernv.h+0−6

 #ifdef CONFIG_PCI
 extern void pnv_pci_init(void);
 extern void pnv_pci_shutdown(void);
-extern u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev);
 #else
 static inline void pnv_pci_init(void) { }
 static inline void pnv_pci_shutdown(void) { }
-static inline u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev)
-{
-	return 0;
-}
 #endif
 extern u32 pnv_get_supported_cpuidle_states(void);

arch/powerpc/platforms/powernv/rng.c+1−1

@@ -128,7 +128,7 @@ static __init int rng_create(struct device_node *dn) · 127 unmodified lines
128		128
129	pr_info_once("Registering arch random hook.\n");	129	pr_info_once("Registering arch random hook.\n");
130		130
131	ppc_md.get_random_long = powernv_get_random_long;	131	ppc_md.get_random_seed = powernv_get_random_long;
132		132
133	return 0;	133	return 0;
134	}	134	}

arch/powerpc/platforms/powernv/setup.c+7−9

 {
 }
-static u64 pnv_dma_get_required_mask(struct device *dev)
-{
-	if (dev_is_pci(dev))
-		return pnv_pci_dma_get_required_mask(to_pci_dev(dev));
-	return __dma_get_required_mask(dev);
-}
 static void pnv_shutdown(void)
 {
 	/* Let the PCI code clear up IODA tables */
 	} else {
 		/* Primary waits for the secondaries to have reached OPAL */
 		pnv_kexec_wait_secondaries_down();
+		/*
+		 * We might be running as little-endian - now that interrupts
+		 * are disabled, reset the HILE bit to big-endian so we don't
+		 * take interrupts in the wrong endian later
+		 */
+		opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
 	}
 }
 #endif /* CONFIG_KEXEC */
 	.machine_shutdown	= pnv_shutdown,
 	.power_save             = power7_idle,
 	.calibrate_decr		= generic_calibrate_decr,
-	.dma_get_required_mask	= pnv_dma_get_required_mask,
 #ifdef CONFIG_KEXEC
 	.kexec_cpu_down		= pnv_kexec_cpu_down,
 #endif

arch/powerpc/platforms/powernv/subcore.c+2−2

@@ -190,7 +190,7 @@ static void unsplit_core(void) · 189 unmodified lines
190		190
191	hid0 = mfspr(SPRN_HID0);	191	hid0 = mfspr(SPRN_HID0);
192	hid0 &= ~HID0_POWER8_DYNLPARDIS;	192	hid0 &= ~HID0_POWER8_DYNLPARDIS;
193	mtspr(SPRN_HID0, hid0);	193	update_power8_hid0(hid0);
194	update_hid_in_slw(hid0);	194	update_hid_in_slw(hid0);
195		195
196	while (mfspr(SPRN_HID0) & mask)	196	while (mfspr(SPRN_HID0) & mask)
@@ -227,7 +227,7 @@ static void split_core(int new_mode) · 30 unmodified lines
227	/* Write new mode */	227	/* Write new mode */
228	hid0 = mfspr(SPRN_HID0);	228	hid0 = mfspr(SPRN_HID0);
229	hid0 \|= HID0_POWER8_DYNLPARDIS \| split_parms[i].value;	229	hid0 \|= HID0_POWER8_DYNLPARDIS \| split_parms[i].value;
230	mtspr(SPRN_HID0, hid0);	230	update_power8_hid0(hid0);
231	update_hid_in_slw(hid0);	231	update_hid_in_slw(hid0);
232		232
233	/* Wait for it to happen */	233	/* Wait for it to happen */

arch/powerpc/platforms/pseries/hotplug-memory.c+1−2

 		return NULL;
 	new_prop->name = kstrdup(prop->name, GFP_KERNEL);
-	new_prop->value = kmalloc(prop->length, GFP_KERNEL);
+	new_prop->value = kmemdup(prop->value, prop->length, GFP_KERNEL);
 	if (!new_prop->name || !new_prop->value) {
 		dlpar_free_drconf_property(new_prop);
 		return NULL;
 	}
-	memcpy(new_prop->value, prop->value, prop->length);
 	new_prop->length = prop->length;
 	/* Convert the property to cpu endian-ness */

arch/powerpc/platforms/pseries/iommu.c+1−2

 		}
 	}
-	/* fall back on iommu ops, restore table pointer with ops */
+	/* fall back on iommu ops */
 	if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
 		dev_info(dev, "Restoring 32-bit DMA via iommu\n");
 		set_dma_ops(dev, &dma_iommu_ops);
-		pci_dma_dev_setup_pSeriesLP(pdev);
 	}
 check_mask:

arch/powerpc/platforms/pseries/ras.c+2−1

@@ -189,7 +189,8 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id) · 188 unmodified lines
189	int state;	189	int state;
190	int critical;	190	int critical;
191		191
192	status = rtas_get_sensor(EPOW_SENSOR_TOKEN, EPOW_SENSOR_INDEX, &state);	192	status = rtas_get_sensor_fast(EPOW_SENSOR_TOKEN, EPOW_SENSOR_INDEX,
		193	&state);
193		194
194	if (state > 3)	195	if (state > 3)
195	critical = 1; /* Time Critical */	196	critical = 1; /* Time Critical */

arch/powerpc/platforms/pseries/rng.c+1−1

@@ -38,7 +38,7 @@ static __init int rng_init(void) · 37 unmodified lines
38		38
39	pr_info("Registering arch random hook.\n");	39	pr_info("Registering arch random hook.\n");
40		40
41	ppc_md.get_random_long = pseries_get_random_long;	41	ppc_md.get_random_seed = pseries_get_random_long;
42		42
43	return 0;	43	return 0;
44	}	44	}

arch/powerpc/platforms/pseries/setup.c+15−8

@@ -254,19 +254,26 @@ static void __init pseries_discover_pic(void) · 253 unmodified lines
254	static int pci_dn_reconfig_notifier(struct notifier_block nb, unsigned long action, void data)	254	static int pci_dn_reconfig_notifier(struct notifier_block nb, unsigned long action, void data)
255	{	255	{
256	struct of_reconfig_data *rd = data;	256	struct of_reconfig_data *rd = data;
257	struct device_node *np = rd->dn;	257	struct device_node parent, np = rd->dn;
258	struct pci_dn *pci = NULL;	258	struct pci_dn *pdn;
259	int err = NOTIFY_OK;	259	int err = NOTIFY_OK;
260		260
261	switch (action) {	261	switch (action) {
262	case OF_RECONFIG_ATTACH_NODE:	262	case OF_RECONFIG_ATTACH_NODE:
263	pci = np->parent->data;	263	parent = of_get_parent(np);
264	if (pci) {	264	pdn = parent ? PCI_DN(parent) : NULL;
265	update_dn_pci_info(np, pci->phb);	265	if (pdn) {
266		266	/* Create pdn and EEH device */
267	/* Create EEH device for the OF node */	267	update_dn_pci_info(np, pdn->phb);
268	eeh_dev_init(PCI_DN(np), pci->phb);	268	eeh_dev_init(PCI_DN(np), pdn->phb);
269	}	269	}
		270
		271	of_node_put(parent);
		272	break;
		273	case OF_RECONFIG_DETACH_NODE:
		274	pdn = PCI_DN(np);
		275	if (pdn)
		276	list_del(&pdn->list);
270	break;	277	break;
271	default:	278	default:
272	err = NOTIFY_DONE;	279	err = NOTIFY_DONE;

arch/powerpc/sysdev/cpm_common.c+1−1

@@ -147,7 +147,7 @@ unsigned long cpm_muram_alloc(unsigned long size, unsigned long align) · 146 unmodified lines
147	spin_lock_irqsave(&cpm_muram_lock, flags);	147	spin_lock_irqsave(&cpm_muram_lock, flags);
148	cpm_muram_info.alignment = align;	148	cpm_muram_info.alignment = align;
149	start = rh_alloc(&cpm_muram_info, size, "commproc");	149	start = rh_alloc(&cpm_muram_info, size, "commproc");
150	memset(cpm_muram_addr(start), 0, size);	150	memset_io(cpm_muram_addr(start), 0, size);
151	spin_unlock_irqrestore(&cpm_muram_lock, flags);	151	spin_unlock_irqrestore(&cpm_muram_lock, flags);
152		152
153	return start;	153	return start;

arch/powerpc/sysdev/dart_iommu.c+3−13

 	set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
 }
-static void dma_dev_setup_dart(struct device *dev)
-{
-	/* We only have one iommu table on the mac for now, which makes
-	 * things simple. Setup all PCI devices to point to this table
-	 */
-	if (get_dma_ops(dev) == &dma_direct_ops)
-		set_dma_offset(dev, DART_U4_BYPASS_BASE);
-	else
-		set_iommu_table_base(dev, &iommu_table_dart);
-}
 static void pci_dma_dev_setup_dart(struct pci_dev *dev)
 {
-	dma_dev_setup_dart(&dev->dev);
+	if (dart_is_u4)
+		set_dma_offset(&dev->dev, DART_U4_BYPASS_BASE);
+	set_iommu_table_base(&dev->dev, &iommu_table_dart);
 }
 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
 		dev_info(dev, "Using 32-bit DMA via iommu\n");
 		set_dma_ops(dev, &dma_iommu_ops);
 	}
-	dma_dev_setup_dart(dev);
 	*dev->dma_mask = dma_mask;
 	return 0;

arch/powerpc/sysdev/ppc4xx_hsta_msi.c+2−2

@@ -132,7 +132,7 @@ static int hsta_msi_probe(struct platform_device *pdev) · 131 unmodified lines
132	struct pci_controller *phb;	132	struct pci_controller *phb;
133		133
134	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);	134	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
135	if (IS_ERR(mem)) {	135	if (!mem) {
136	dev_err(dev, "Unable to get mmio space\n");	136	dev_err(dev, "Unable to get mmio space\n");
137	return -EINVAL;	137	return -EINVAL;
138	}	138	}
@@ -157,7 +157,7 @@ static int hsta_msi_probe(struct platform_device *pdev) · 18 unmodified lines
157	goto out;	157	goto out;
158		158
159	ppc4xx_hsta_msi.irq_map = kmalloc(sizeof(int) * irq_count, GFP_KERNEL);	159	ppc4xx_hsta_msi.irq_map = kmalloc(sizeof(int) * irq_count, GFP_KERNEL);
160	if (IS_ERR(ppc4xx_hsta_msi.irq_map)) {	160	if (!ppc4xx_hsta_msi.irq_map) {
161	ret = -ENOMEM;	161	ret = -ENOMEM;
162	goto out1;	162	goto out1;
163	}	163	}

arch/powerpc/xmon/xmon.c+3−5

 			case '^':
 				adrs -= size;
 				break;
-				break;
 			case '/':
 				if (nslash > 0)
 					adrs -= 1 << nslash;
 void dump_segments(void)
 {
 	int i;
-	unsigned long esid,vsid,valid;
+	unsigned long esid,vsid;
 	unsigned long llp;
 	printf("SLB contents of cpu 0x%x\n", smp_processor_id());
 	for (i = 0; i < mmu_slb_size; i++) {
 		asm volatile("slbmfee  %0,%1" : "=r" (esid) : "r" (i));
 		asm volatile("slbmfev  %0,%1" : "=r" (vsid) : "r" (i));
-		valid = (esid & SLB_ESID_V);
+		if (esid || vsid) {
-		if (valid | esid | vsid) {
 			printf("%02d %016lx %016lx", i, esid, vsid);
-			if (valid) {
+			if (esid & SLB_ESID_V) {
 				llp = vsid & SLB_VSID_LLP;
 				if (vsid & SLB_VSID_B_1T) {
 					printf("  1T  ESID=%9lx  VSID=%13lx LLP:%3lx \n",

drivers/leds/Kconfig+11−0

@@ -565,6 +565,17 @@ config LEDS_BLINKM · 564 unmodified lines
565	This option enables support for the BlinkM RGB LED connected	565	This option enables support for the BlinkM RGB LED connected
566	through I2C. Say Y to enable support for the BlinkM LED.	566	through I2C. Say Y to enable support for the BlinkM LED.
567		567
		568	config LEDS_POWERNV
		569	tristate "LED support for PowerNV Platform"
		570	depends on LEDS_CLASS
		571	depends on PPC_POWERNV
		572	depends on OF
		573	help
		574	This option enables support for the system LEDs present on
		575	PowerNV platforms. Say 'y' to enable this support in kernel.
		576	To compile this driver as a module, choose 'm' here: the module
		577	will be called leds-powernv.
		578
568	config LEDS_SYSCON	579	config LEDS_SYSCON
569	bool "LED support for LEDs on system controllers"	580	bool "LED support for LEDs on system controllers"
570	depends on LEDS_CLASS=y	581	depends on LEDS_CLASS=y

drivers/leds/Makefile+1−0

@@ -65,6 +65,7 @@ obj-$(CONFIG_LEDS_VERSATILE) += leds-versatile.o · 64 unmodified lines
65	obj-$(CONFIG_LEDS_MENF21BMC) += leds-menf21bmc.o	65	obj-$(CONFIG_LEDS_MENF21BMC) += leds-menf21bmc.o
66	obj-$(CONFIG_LEDS_PM8941_WLED) += leds-pm8941-wled.o	66	obj-$(CONFIG_LEDS_PM8941_WLED) += leds-pm8941-wled.o
67	obj-$(CONFIG_LEDS_KTD2692) += leds-ktd2692.o	67	obj-$(CONFIG_LEDS_KTD2692) += leds-ktd2692.o
		68	obj-$(CONFIG_LEDS_POWERNV) += leds-powernv.o
68		69
69	# LED SPI Drivers	70	# LED SPI Drivers
70	obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o	71	obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o

drivers/leds/leds-powernv.c+345−0

@@ -0,0 +1,345 @@
	1	/*
	2	* PowerNV LED Driver
	3	*
	4	* Copyright IBM Corp. 2015
	5	*
	6	* Author: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
	7	* Author: Anshuman Khandual <khandual@linux.vnet.ibm.com>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#include <linux/leds.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/slab.h>
	20	#include <linux/types.h>
	21
	22	#include <asm/opal.h>
	23
	24	/* Map LED type to description. */
	25	struct led_type_map {
	26	const int type;
	27	const char *desc;
	28	};
	29	static const struct led_type_map led_type_map[] = {
	30	{OPAL_SLOT_LED_TYPE_ID, "identify"},
	31	{OPAL_SLOT_LED_TYPE_FAULT, "fault"},
	32	{OPAL_SLOT_LED_TYPE_ATTN, "attention"},
	33	{-1, NULL},
	34	};
	35
	36	struct powernv_led_common {
	37	/*
	38	* By default unload path resets all the LEDs. But on PowerNV
	39	* platform we want to retain LED state across reboot as these
	40	* are controlled by firmware. Also service processor can modify
	41	* the LEDs independent of OS. Hence avoid resetting LEDs in
	42	* unload path.
	43	*/
	44	bool led_disabled;
	45
	46	/* Max supported LED type */
	47	__be64 max_led_type;
	48
	49	/* glabal lock */
	50	struct mutex lock;
	51	};
	52
	53	/* PowerNV LED data */
	54	struct powernv_led_data {
	55	struct led_classdev cdev;
	56	char loc_code; / LED location code */
	57	int led_type; /* OPAL_SLOT_LED_TYPE_* */
	58
	59	struct powernv_led_common *common;
	60	};
	61
	62
	63	/* Returns OPAL_SLOT_LED_TYPE_* for given led type string */
	64	static int powernv_get_led_type(const char *led_type_desc)
	65	{
	66	int i;
	67
	68	for (i = 0; i < ARRAY_SIZE(led_type_map); i++)
	69	if (!strcmp(led_type_map[i].desc, led_type_desc))
	70	return led_type_map[i].type;
	71
	72	return -1;
	73	}
	74
	75	/*
	76	* This commits the state change of the requested LED through an OPAL call.
	77	* This function is called from work queue task context when ever it gets
	78	* scheduled. This function can sleep at opal_async_wait_response call.
	79	*/
	80	static void powernv_led_set(struct powernv_led_data *powernv_led,
	81	enum led_brightness value)
	82	{
	83	int rc, token;
	84	u64 led_mask, led_value = 0;
	85	__be64 max_type;
	86	struct opal_msg msg;
	87	struct device *dev = powernv_led->cdev.dev;
	88	struct powernv_led_common *powernv_led_common = powernv_led->common;
	89
	90	/* Prepare for the OPAL call */
	91	max_type = powernv_led_common->max_led_type;
	92	led_mask = OPAL_SLOT_LED_STATE_ON << powernv_led->led_type;
	93	if (value)
	94	led_value = led_mask;
	95
	96	/* OPAL async call */
	97	token = opal_async_get_token_interruptible();
	98	if (token < 0) {
	99	if (token != -ERESTARTSYS)
	100	dev_err(dev, "%s: Couldn't get OPAL async token\n",
	101	__func__);
	102	return;
	103	}
	104
	105	rc = opal_leds_set_ind(token, powernv_led->loc_code,
	106	led_mask, led_value, &max_type);
	107	if (rc != OPAL_ASYNC_COMPLETION) {
	108	dev_err(dev, "%s: OPAL set LED call failed for %s [rc=%d]\n",
	109	__func__, powernv_led->loc_code, rc);
	110	goto out_token;
	111	}
	112
	113	rc = opal_async_wait_response(token, &msg);
	114	if (rc) {
	115	dev_err(dev,
	116	"%s: Failed to wait for the async response [rc=%d]\n",
	117	__func__, rc);
	118	goto out_token;
	119	}
	120
	121	rc = be64_to_cpu(msg.params[1]);
	122	if (rc != OPAL_SUCCESS)
	123	dev_err(dev, "%s : OAPL async call returned failed [rc=%d]\n",
	124	__func__, rc);
	125
	126	out_token:
	127	opal_async_release_token(token);
	128	}
	129
	130	/*
	131	* This function fetches the LED state for a given LED type for
	132	* mentioned LED classdev structure.
	133	*/
	134	static enum led_brightness powernv_led_get(struct powernv_led_data *powernv_led)
	135	{
	136	int rc;
	137	__be64 mask, value, max_type;
	138	u64 led_mask, led_value;
	139	struct device *dev = powernv_led->cdev.dev;
	140	struct powernv_led_common *powernv_led_common = powernv_led->common;
	141
	142	/* Fetch all LED status */
	143	mask = cpu_to_be64(0);
	144	value = cpu_to_be64(0);
	145	max_type = powernv_led_common->max_led_type;
	146
	147	rc = opal_leds_get_ind(powernv_led->loc_code,
	148	&mask, &value, &max_type);
	149	if (rc != OPAL_SUCCESS && rc != OPAL_PARTIAL) {
	150	dev_err(dev, "%s: OPAL get led call failed [rc=%d]\n",
	151	__func__, rc);
	152	return LED_OFF;
	153	}
	154
	155	led_mask = be64_to_cpu(mask);
	156	led_value = be64_to_cpu(value);
	157
	158	/* LED status available */
	159	if (!((led_mask >> powernv_led->led_type) & OPAL_SLOT_LED_STATE_ON)) {
	160	dev_err(dev, "%s: LED status not available for %s\n",
	161	__func__, powernv_led->cdev.name);
	162	return LED_OFF;
	163	}
	164
	165	/* LED status value */
	166	if ((led_value >> powernv_led->led_type) & OPAL_SLOT_LED_STATE_ON)
	167	return LED_FULL;
	168
	169	return LED_OFF;
	170	}
	171
	172	/*
	173	* LED classdev 'brightness_get' function. This schedules work
	174	* to update LED state.
	175	*/
	176	static void powernv_brightness_set(struct led_classdev *led_cdev,
	177	enum led_brightness value)
	178	{
	179	struct powernv_led_data *powernv_led =
	180	container_of(led_cdev, struct powernv_led_data, cdev);
	181	struct powernv_led_common *powernv_led_common = powernv_led->common;
	182
	183	/* Do not modify LED in unload path */
	184	if (powernv_led_common->led_disabled)
	185	return;
	186
	187	mutex_lock(&powernv_led_common->lock);
	188	powernv_led_set(powernv_led, value);
	189	mutex_unlock(&powernv_led_common->lock);
	190	}
	191
	192	/* LED classdev 'brightness_get' function */
	193	static enum led_brightness powernv_brightness_get(struct led_classdev *led_cdev)
	194	{
	195	struct powernv_led_data *powernv_led =
	196	container_of(led_cdev, struct powernv_led_data, cdev);
	197
	198	return powernv_led_get(powernv_led);
	199	}
	200
	201	/*
	202	* This function registers classdev structure for any given type of LED on
	203	* a given child LED device node.
	204	*/
	205	static int powernv_led_create(struct device *dev,
	206	struct powernv_led_data *powernv_led,
	207	const char *led_type_desc)
	208	{
	209	int rc;
	210
	211	/* Make sure LED type is supported */
	212	powernv_led->led_type = powernv_get_led_type(led_type_desc);
	213	if (powernv_led->led_type == -1) {
	214	dev_warn(dev, "%s: No support for led type : %s\n",
	215	__func__, led_type_desc);
	216	return -EINVAL;
	217	}
	218
	219	/* Create the name for classdev */
	220	powernv_led->cdev.name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
	221	powernv_led->loc_code,
	222	led_type_desc);
	223	if (!powernv_led->cdev.name) {
	224	dev_err(dev,
	225	"%s: Memory allocation failed for classdev name\n",
	226	__func__);
	227	return -ENOMEM;
	228	}
	229
	230	powernv_led->cdev.brightness_set = powernv_brightness_set;
	231	powernv_led->cdev.brightness_get = powernv_brightness_get;
	232	powernv_led->cdev.brightness = LED_OFF;
	233	powernv_led->cdev.max_brightness = LED_FULL;
	234
	235	/* Register the classdev */
	236	rc = devm_led_classdev_register(dev, &powernv_led->cdev);
	237	if (rc) {
	238	dev_err(dev, "%s: Classdev registration failed for %s\n",
	239	__func__, powernv_led->cdev.name);
	240	}
	241
	242	return rc;
	243	}
	244
	245	/* Go through LED device tree node and register LED classdev structure */
	246	static int powernv_led_classdev(struct platform_device *pdev,
	247	struct device_node *led_node,
	248	struct powernv_led_common *powernv_led_common)
	249	{
	250	const char *cur = NULL;
	251	int rc = -1;
	252	struct property *p;
	253	struct device_node *np;
	254	struct powernv_led_data *powernv_led;
	255	struct device *dev = &pdev->dev;
	256
	257	for_each_child_of_node(led_node, np) {
	258	p = of_find_property(np, "led-types", NULL);
	259	if (!p)
	260	continue;
	261
	262	while ((cur = of_prop_next_string(p, cur)) != NULL) {
	263	powernv_led = devm_kzalloc(dev, sizeof(*powernv_led),
	264	GFP_KERNEL);
	265	if (!powernv_led)
	266	return -ENOMEM;
	267
	268	powernv_led->common = powernv_led_common;
	269	powernv_led->loc_code = (char *)np->name;
	270
	271	rc = powernv_led_create(dev, powernv_led, cur);
	272	if (rc)
	273	return rc;
	274	} /* while end */
	275	}
	276
	277	return rc;
	278	}
	279
	280	/* Platform driver probe */
	281	static int powernv_led_probe(struct platform_device *pdev)
	282	{
	283	struct device_node *led_node;
	284	struct powernv_led_common *powernv_led_common;
	285	struct device *dev = &pdev->dev;
	286
	287	led_node = of_find_node_by_path("/ibm,opal/leds");
	288	if (!led_node) {
	289	dev_err(dev, "%s: LED parent device node not found\n",
	290	__func__);
	291	return -EINVAL;
	292	}
	293
	294	powernv_led_common = devm_kzalloc(dev, sizeof(*powernv_led_common),
	295	GFP_KERNEL);
	296	if (!powernv_led_common)
	297	return -ENOMEM;
	298
	299	mutex_init(&powernv_led_common->lock);
	300	powernv_led_common->max_led_type = cpu_to_be64(OPAL_SLOT_LED_TYPE_MAX);
	301
	302	platform_set_drvdata(pdev, powernv_led_common);
	303
	304	return powernv_led_classdev(pdev, led_node, powernv_led_common);
	305	}
	306
	307	/* Platform driver remove */
	308	static int powernv_led_remove(struct platform_device *pdev)
	309	{
	310	struct powernv_led_common *powernv_led_common;
	311
	312	/* Disable LED operation */
	313	powernv_led_common = platform_get_drvdata(pdev);
	314	powernv_led_common->led_disabled = true;
	315
	316	/* Destroy lock */
	317	mutex_destroy(&powernv_led_common->lock);
	318
	319	dev_info(&pdev->dev, "PowerNV led module unregistered\n");
	320	return 0;
	321	}
	322
	323	/* Platform driver property match */
	324	static const struct of_device_id powernv_led_match[] = {
	325	{
	326	.compatible = "ibm,opal-v3-led",
	327	},
	328	{},
	329	};
	330	MODULE_DEVICE_TABLE(of, powernv_led_match);
	331
	332	static struct platform_driver powernv_led_driver = {
	333	.probe = powernv_led_probe,
	334	.remove = powernv_led_remove,
	335	.driver = {
	336	.name = "powernv-led-driver",
	337	.of_match_table = powernv_led_match,
	338	},
	339	};
	340
	341	module_platform_driver(powernv_led_driver);
	342
	343	MODULE_LICENSE("GPL v2");
	344	MODULE_DESCRIPTION("PowerNV LED driver");
	345	MODULE_AUTHOR("Vasant Hegde <hegdevasant@linux.vnet.ibm.com>");

drivers/macintosh/therm_windtunnel.c+2−0

 	{ "therm_adm1030", adm1030 },
 	{ }
 };
+MODULE_DEVICE_TABLE(i2c, therm_windtunnel_id);
 static int
 do_probe(struct i2c_client *cl, const struct i2c_device_id *id)
 	.compatible	= "adm1030"
     }, {}
 };
+MODULE_DEVICE_TABLE(of, therm_of_match);
 static struct platform_driver therm_of_driver = {
 	.driver = {

drivers/macintosh/windfarm.h+0−4

  * the kref and wf_unregister_control will decrement it, thus the
  * object creating/disposing a given control shouldn't assume it
  * still exists after wf_unregister_control has been called.
- * wf_find_control will inc the refcount for you
  */
 extern int wf_register_control(struct wf_control *ct);
 extern void wf_unregister_control(struct wf_control *ct);
-extern struct wf_control * wf_find_control(const char *name);
 extern int wf_get_control(struct wf_control *ct);
 extern void wf_put_control(struct wf_control *ct);
 /* Same lifetime rules as controls */
 extern int wf_register_sensor(struct wf_sensor *sr);
 extern void wf_unregister_sensor(struct wf_sensor *sr);
-extern struct wf_sensor * wf_find_sensor(const char *name);
 extern int wf_get_sensor(struct wf_sensor *sr);
 extern void wf_put_sensor(struct wf_sensor *sr);
 /* Overtemp conditions. Those are refcounted */
 extern void wf_set_overtemp(void);
 extern void wf_clear_overtemp(void);
-extern int wf_is_overtemp(void);
 #define WF_EVENT_NEW_CONTROL	0 /* param is wf_control * */
 #define WF_EVENT_NEW_SENSOR	1 /* param is wf_sensor * */

drivers/macintosh/windfarm_core.c+2−45

@@ -72,7 +72,7 @@ static inline void wf_notify(int event, void *param) · 71 unmodified lines
72	blocking_notifier_call_chain(&wf_client_list, event, param);	72	blocking_notifier_call_chain(&wf_client_list, event, param);
73	}	73	}
74		74
75	int wf_critical_overtemp(void)	75	static int wf_critical_overtemp(void)
76	{	76	{
77	static char * critical_overtemp_path = "/sbin/critical_overtemp";	77	static char * critical_overtemp_path = "/sbin/critical_overtemp";
78	char *argv[] = { critical_overtemp_path, NULL };	78	char *argv[] = { critical_overtemp_path, NULL };
@@ -84,7 +84,6 @@ int wf_critical_overtemp(void) · 5 unmodified lines
84	return call_usermodehelper(critical_overtemp_path,	84	return call_usermodehelper(critical_overtemp_path,
85	argv, envp, UMH_WAIT_EXEC);	85	argv, envp, UMH_WAIT_EXEC);
86	}	86	}
87	EXPORT_SYMBOL_GPL(wf_critical_overtemp);
88		87
89	static int wf_thread_func(void *data)	88	static int wf_thread_func(void *data)
90	{	89	{
@@ -255,24 +254,6 @@ void wf_unregister_control(struct wf_control *ct) · 164 unmodified lines
255	}	254	}
256	EXPORT_SYMBOL_GPL(wf_unregister_control);	255	EXPORT_SYMBOL_GPL(wf_unregister_control);
257		256
258	struct wf_control * wf_find_control(const char *name)
259	{
260	struct wf_control *ct;
261
262	mutex_lock(&wf_lock);
263	list_for_each_entry(ct, &wf_controls, link) {
264	if (!strcmp(ct->name, name)) {
265	if (wf_get_control(ct))
266	ct = NULL;
267	mutex_unlock(&wf_lock);
268	return ct;
269	}
270	}
271	mutex_unlock(&wf_lock);
272	return NULL;
273	}
274	EXPORT_SYMBOL_GPL(wf_find_control);
275
276	int wf_get_control(struct wf_control *ct)	257	int wf_get_control(struct wf_control *ct)
277	{	258	{
278	if (!try_module_get(ct->ops->owner))	259	if (!try_module_get(ct->ops->owner))
@@ -368,24 +349,6 @@ void wf_unregister_sensor(struct wf_sensor *sr) · 89 unmodified lines
368	}	349	}
369	EXPORT_SYMBOL_GPL(wf_unregister_sensor);	350	EXPORT_SYMBOL_GPL(wf_unregister_sensor);
370		351
371	struct wf_sensor * wf_find_sensor(const char *name)
372	{
373	struct wf_sensor *sr;
374
375	mutex_lock(&wf_lock);
376	list_for_each_entry(sr, &wf_sensors, link) {
377	if (!strcmp(sr->name, name)) {
378	if (wf_get_sensor(sr))
379	sr = NULL;
380	mutex_unlock(&wf_lock);
381	return sr;
382	}
383	}
384	mutex_unlock(&wf_lock);
385	return NULL;
386	}
387	EXPORT_SYMBOL_GPL(wf_find_sensor);
388
389	int wf_get_sensor(struct wf_sensor *sr)	352	int wf_get_sensor(struct wf_sensor *sr)
390	{	353	{
391	if (!try_module_get(sr->ops->owner))	354	if (!try_module_get(sr->ops->owner))
@@ -435,7 +398,7 @@ int wf_unregister_client(struct notifier_block *nb) · 43 unmodified lines
435	{	398	{
436	mutex_lock(&wf_lock);	399	mutex_lock(&wf_lock);
437	blocking_notifier_chain_unregister(&wf_client_list, nb);	400	blocking_notifier_chain_unregister(&wf_client_list, nb);
438	wf_client_count++;	401	wf_client_count--;
439	if (wf_client_count == 0)	402	if (wf_client_count == 0)
440	wf_stop_thread();	403	wf_stop_thread();
441	mutex_unlock(&wf_lock);	404	mutex_unlock(&wf_lock);
@@ -474,12 +437,6 @@ void wf_clear_overtemp(void) · 32 unmodified lines
474	}	437	}
475	EXPORT_SYMBOL_GPL(wf_clear_overtemp);	438	EXPORT_SYMBOL_GPL(wf_clear_overtemp);
476		439
477	int wf_is_overtemp(void)
478	{
479	return (wf_overtemp != 0);
480	}
481	EXPORT_SYMBOL_GPL(wf_is_overtemp);
482
483	static int __init windfarm_core_init(void)	440	static int __init windfarm_core_init(void)
484	{	441	{
485	DBG("wf: core loaded\n");	442	DBG("wf: core loaded\n");

drivers/memory/fsl_ifc.c+30−13

 		return -ENODEV;
 	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
-		u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
+		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
 		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
 				convert_ifc_address(addr_base))
 			return i;
 	/*
 	 * Clear all the common status and event registers
 	 */
-	if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
+	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
-		out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
 	/* enable all error and events */
-	out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
+	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
 	/* enable all error and event interrupts */
-	out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
+	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
-	out_be32(&ifc->cm_erattr0, 0x0);
+	ifc_out32(0x0, &ifc->cm_erattr0);
-	out_be32(&ifc->cm_erattr1, 0x0);
+	ifc_out32(0x0, &ifc->cm_erattr1);
 	return 0;
 }
 	spin_lock_irqsave(&nand_irq_lock, flags);
-	stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
+	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 	if (stat) {
-		out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
+		ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
 		ctrl->nand_stat = stat;
 		wake_up(&ctrl->nand_wait);
 	}
 	irqreturn_t ret = IRQ_NONE;
 	/* read for chip select error */
-	cs_err = in_be32(&ifc->cm_evter_stat);
+	cs_err = ifc_in32(&ifc->cm_evter_stat);
 	if (cs_err) {
 		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
 				"any memory bank 0x%08X\n", cs_err);
 		/* clear the chip select error */
-		out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
 		/* read error attribute registers print the error information */
-		status = in_be32(&ifc->cm_erattr0);
+		status = ifc_in32(&ifc->cm_erattr0);
-		err_addr = in_be32(&ifc->cm_erattr1);
+		err_addr = ifc_in32(&ifc->cm_erattr1);
 		if (status & IFC_CM_ERATTR0_ERTYP_READ)
 			dev_err(ctrl->dev, "Read transaction error"
 		goto err;
 	}
+	version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
+			FSL_IFC_VERSION_MASK;
+	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
+	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
+		version >> 24, (version >> 16) & 0xf, banks);
+	fsl_ifc_ctrl_dev->version = version;
+	fsl_ifc_ctrl_dev->banks = banks;
+	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
+		fsl_ifc_ctrl_dev->little_endian = true;
+		dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
+	} else {
+		fsl_ifc_ctrl_dev->little_endian = false;
+		dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
+	}
 	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
 			FSL_IFC_VERSION_MASK;
 	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;

drivers/misc/cxl/Kconfig+6−1

 	bool
 	default n
+config CXL_EEH
+	bool
+	default n
 config CXL
 	tristate "Support for IBM Coherent Accelerators (CXL)"
-	depends on PPC_POWERNV && PCI_MSI
+	depends on PPC_POWERNV && PCI_MSI && EEH
 	select CXL_BASE
 	select CXL_KERNEL_API
+	select CXL_EEH
 	default m
 	help
 	  Select this option to enable driver support for IBM Coherent

drivers/misc/cxl/Makefile+2−0

@@ -1,3 +1,5 @@
		1	ccflags-y := -Werror
		2
1	cxl-y += main.o file.o irq.o fault.o native.o	3	cxl-y += main.o file.o irq.o fault.o native.o
2	cxl-y += context.o sysfs.o debugfs.o pci.o trace.o	4	cxl-y += context.o sysfs.o debugfs.o pci.o trace.o
3	cxl-y += vphb.o api.o	5	cxl-y += vphb.o api.o

drivers/misc/cxl/api.c+49−10

@@ -12,11 +12,13 @@ · 11 unmodified lines
12	#include <linux/anon_inodes.h>	12	#include <linux/anon_inodes.h>
13	#include <linux/file.h>	13	#include <linux/file.h>
14	#include <misc/cxl.h>	14	#include <misc/cxl.h>
		15	#include <linux/fs.h>
15		16
16	#include "cxl.h"	17	#include "cxl.h"
17		18
18	struct cxl_context cxl_dev_context_init(struct pci_dev dev)	19	struct cxl_context cxl_dev_context_init(struct pci_dev dev)
19	{	20	{
		21	struct address_space *mapping;
20	struct cxl_afu *afu;	22	struct cxl_afu *afu;
21	struct cxl_context *ctx;	23	struct cxl_context *ctx;
22	int rc;	24	int rc;
@@ -25,19 +27,42 @@ struct cxl_context cxl_dev_context_init(struct pci_dev dev) · 2 unmodified lines
25		27
26	get_device(&afu->dev);	28	get_device(&afu->dev);
27	ctx = cxl_context_alloc();	29	ctx = cxl_context_alloc();
28	if (IS_ERR(ctx))	30	if (IS_ERR(ctx)) {
29	return ctx;	31	rc = PTR_ERR(ctx);
		32	goto err_dev;
		33	}
30		34
31	/* Make it a slave context. We can promote it later? */	35	ctx->kernelapi = true;
32	rc = cxl_context_init(ctx, afu, false, NULL);	36
33	if (rc) {	37	/*
34	kfree(ctx);	38	* Make our own address space since we won't have one from the
35	put_device(&afu->dev);	39	* filesystem like the user api has, and even if we do associate a file
36	return ERR_PTR(-ENOMEM);	40	* with this context we don't want to use the global anonymous inode's
		41	* address space as that can invalidate unrelated users:
		42	*/
		43	mapping = kmalloc(sizeof(struct address_space), GFP_KERNEL);
		44	if (!mapping) {
		45	rc = -ENOMEM;
		46	goto err_ctx;
37	}	47	}
		48	address_space_init_once(mapping);
		49
		50	/* Make it a slave context. We can promote it later? */
		51	rc = cxl_context_init(ctx, afu, false, mapping);
		52	if (rc)
		53	goto err_mapping;
		54
38	cxl_assign_psn_space(ctx);	55	cxl_assign_psn_space(ctx);
39		56
40	return ctx;	57	return ctx;
		58
		59	err_mapping:
		60	kfree(mapping);
		61	err_ctx:
		62	kfree(ctx);
		63	err_dev:
		64	put_device(&afu->dev);
		65	return ERR_PTR(rc);
41	}	66	}
42	EXPORT_SYMBOL_GPL(cxl_dev_context_init);	67	EXPORT_SYMBOL_GPL(cxl_dev_context_init);
43		68
@@ -59,7 +84,7 @@ EXPORT_SYMBOL_GPL(cxl_get_phys_dev); · 15 unmodified lines
59		84
60	int cxl_release_context(struct cxl_context *ctx)	85	int cxl_release_context(struct cxl_context *ctx)
61	{	86	{
62	if (ctx->status != CLOSED)	87	if (ctx->status >= STARTED)
63	return -EBUSY;	88	return -EBUSY;
64		89
65	put_device(&ctx->afu->dev);	90	put_device(&ctx->afu->dev);
@@ -255,9 +280,16 @@ struct file cxl_get_fd(struct cxl_context ctx, struct file_operations *fops, · 189 unmodified lines
255		280
256	file = anon_inode_getfile("cxl", fops, ctx, flags);	281	file = anon_inode_getfile("cxl", fops, ctx, flags);
257	if (IS_ERR(file))	282	if (IS_ERR(file))
258	put_unused_fd(fdtmp);	283	goto err_fd;
		284
		285	file->f_mapping = ctx->mapping;
		286
259	*fd = fdtmp;	287	*fd = fdtmp;
260	return file;	288	return file;
		289
		290	err_fd:
		291	put_unused_fd(fdtmp);
		292	return NULL;
261	}	293	}
262	EXPORT_SYMBOL_GPL(cxl_get_fd);	294	EXPORT_SYMBOL_GPL(cxl_get_fd);
263		295
@@ -327,3 +359,10 @@ int cxl_afu_reset(struct cxl_context *ctx) · 63 unmodified lines
327	return cxl_afu_check_and_enable(afu);	359	return cxl_afu_check_and_enable(afu);
328	}	360	}
329	EXPORT_SYMBOL_GPL(cxl_afu_reset);	361	EXPORT_SYMBOL_GPL(cxl_afu_reset);
		362
		363	void cxl_perst_reloads_same_image(struct cxl_afu *afu,
		364	bool perst_reloads_same_image)
		365	{
		366	afu->adapter->perst_same_image = perst_reloads_same_image;
		367	}
		368	EXPORT_SYMBOL_GPL(cxl_perst_reloads_same_image);

drivers/misc/cxl/context.c+21−1

 	if (ctx->status != STARTED) {
 		mutex_unlock(&ctx->status_mutex);
 		pr_devel("%s: Context not started, failing problem state access\n", __func__);
+		if (ctx->mmio_err_ff) {
+			if (!ctx->ff_page) {
+				ctx->ff_page = alloc_page(GFP_USER);
+				if (!ctx->ff_page)
+					return VM_FAULT_OOM;
+				memset(page_address(ctx->ff_page), 0xff, PAGE_SIZE);
+			}
+			get_page(ctx->ff_page);
+			vmf->page = ctx->ff_page;
+			vma->vm_page_prot = pgprot_cached(vma->vm_page_prot);
+			return 0;
+		}
 		return VM_FAULT_SIGBUS;
 	}
 	if (status != STARTED)
 		return -EBUSY;
-	WARN_ON(cxl_detach_process(ctx));
+	/* Only warn if we detached while the link was OK.
+	 * If detach fails when hw is down, we don't care.
+	 */
+	WARN_ON(cxl_detach_process(ctx) &&
+		cxl_adapter_link_ok(ctx->afu->adapter));
 	flush_work(&ctx->fault_work); /* Only needed for dedicated process */
 	put_pid(ctx->pid);
 	cxl_ctx_put();
 	struct cxl_context *ctx = container_of(rcu, struct cxl_context, rcu);
 	free_page((u64)ctx->sstp);
+	if (ctx->ff_page)
+		__free_page(ctx->ff_page);
 	ctx->sstp = NULL;
+	if (ctx->kernelapi)
+		kfree(ctx->mapping);
 	kfree(ctx);
 }

drivers/misc/cxl/cxl.h+77−17

  * Bump version each time a user API change is made, whether it is
  * backwards compatible ot not.
  */
-#define CXL_API_VERSION 1
+#define CXL_API_VERSION 2
 #define CXL_API_VERSION_COMPATIBLE 1
 /*
 /* 0x00C0:7EFF Implementation dependent area */
 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
+static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
+static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
 #define CXL_PSL_SPAP_Size_Shift 4
 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
+/****** CXL_PSL_Control ****************************************************/
+#define CXL_PSL_Control_tb 0x0000000000000001ULL
 /****** CXL_PSL_DLCNTL *****************************************************/
 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 	/* Used to unmap any mmaps when force detaching */
 	struct address_space *mapping;
 	struct mutex mapping_lock;
+	struct page *ff_page;
+	bool mmio_err_ff;
+	bool kernelapi;
 	spinlock_t sste_lock; /* Protects segment table entries */
 	struct cxl_sste *sstp;
 	bool user_image_loaded;
 	bool perst_loads_image;
 	bool perst_select_user;
+	bool perst_same_image;
 };
 int cxl_alloc_one_irq(struct cxl *adapter);
 	__be32 software_state;
 } __packed;
+static inline bool cxl_adapter_link_ok(struct cxl *cxl)
+{
+	struct pci_dev *pdev;
+	pdev = to_pci_dev(cxl->dev.parent);
+	return !pci_channel_offline(pdev);
+}
 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 {
 	WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 	return cxl->p1_mmio + cxl_reg_off(reg);
 }
-#define cxl_p1_write(cxl, reg, val) \
+static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
-	out_be64(_cxl_p1_addr(cxl, reg), val)
+{
-#define cxl_p1_read(cxl, reg) \
+	if (likely(cxl_adapter_link_ok(cxl)))
-	in_be64(_cxl_p1_addr(cxl, reg))
+		out_be64(_cxl_p1_addr(cxl, reg), val);
+}
+static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
+{
+	if (likely(cxl_adapter_link_ok(cxl)))
+		return in_be64(_cxl_p1_addr(cxl, reg));
+	else
+		return ~0ULL;
+}
 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 {
 	return afu->p1n_mmio + cxl_reg_off(reg);
 }
-#define cxl_p1n_write(afu, reg, val) \
+static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
-	out_be64(_cxl_p1n_addr(afu, reg), val)
+{
-#define cxl_p1n_read(afu, reg) \
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
-	in_be64(_cxl_p1n_addr(afu, reg))
+		out_be64(_cxl_p1n_addr(afu, reg), val);
+}
+static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
+{
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
+		return in_be64(_cxl_p1n_addr(afu, reg));
+	else
+		return ~0ULL;
+}
 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 {
 	return afu->p2n_mmio + cxl_reg_off(reg);
 }
-#define cxl_p2n_write(afu, reg, val) \
+static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
-	out_be64(_cxl_p2n_addr(afu, reg), val)
+{
-#define cxl_p2n_read(afu, reg) \
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
-	in_be64(_cxl_p2n_addr(afu, reg))
+		out_be64(_cxl_p2n_addr(afu, reg), val);
+}
+static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
+{
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
+		return in_be64(_cxl_p2n_addr(afu, reg));
+	else
+		return ~0ULL;
+}
+static inline u64 cxl_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off)
+{
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
+		return in_le64((afu)->afu_desc_mmio + (afu)->crs_offset +
+			       ((cr) * (afu)->crs_len) + (off));
+	else
+		return ~0ULL;
+}
-#define cxl_afu_cr_read64(afu, cr, off) \
+static inline u32 cxl_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off)
-	in_le64((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off))
+{
-#define cxl_afu_cr_read32(afu, cr, off) \
+	if (likely(cxl_adapter_link_ok(afu->adapter)))
-	in_le32((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off))
+		return in_le32((afu)->afu_desc_mmio + (afu)->crs_offset +
+			       ((cr) * (afu)->crs_len) + (off));
+	else
+		return 0xffffffff;
+}
 u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off);
 u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off);
 int cxl_alloc_adapter_nr(struct cxl *adapter);
 void cxl_remove_adapter_nr(struct cxl *adapter);
+int cxl_alloc_spa(struct cxl_afu *afu);
+void cxl_release_spa(struct cxl_afu *afu);
 int cxl_file_init(void);
 void cxl_file_exit(void);
 int cxl_register_adapter(struct cxl *adapter);
 void cxl_stop_trace(struct cxl *cxl);
 int cxl_pci_vphb_add(struct cxl_afu *afu);
+void cxl_pci_vphb_reconfigure(struct cxl_afu *afu);
 void cxl_pci_vphb_remove(struct cxl_afu *afu);
 extern struct pci_driver cxl_pci_driver;

drivers/misc/cxl/debugfs.c+1−1

@@ -48,7 +48,7 @@ DEFINE_SIMPLE_ATTRIBUTE(fops_io_x64, debugfs_io_u64_get, debugfs_io_u64_set, "0x · 47 unmodified lines
48	static struct dentry debugfs_create_io_x64(const char name, umode_t mode,	48	static struct dentry debugfs_create_io_x64(const char name, umode_t mode,
49	struct dentry parent, u64 __iomem value)	49	struct dentry parent, u64 __iomem value)
50	{	50	{
51	return debugfs_create_file(name, mode, parent, (void *)value, &fops_io_x64);	51	return debugfs_create_file(name, mode, parent, (void __force *)value, &fops_io_x64);
52	}	52	}
53		53
54	int cxl_debugfs_adapter_add(struct cxl *adapter)	54	int cxl_debugfs_adapter_add(struct cxl *adapter)

drivers/misc/cxl/file.c+24−3

 	if (!afu->current_mode)
 		goto err_put_afu;
+	if (!cxl_adapter_link_ok(adapter)) {
+		rc = -EIO;
+		goto err_put_afu;
+	}
 	if (!(ctx = cxl_context_alloc())) {
 		rc = -ENOMEM;
 		goto err_put_afu;
 	if (work.flags & CXL_START_WORK_AMR)
 		amr = work.amr & mfspr(SPRN_UAMOR);
+	ctx->mmio_err_ff = !!(work.flags & CXL_START_WORK_ERR_FF);
 	/*
 	 * We grab the PID here and not in the file open to allow for the case
 	 * where a process (master, some daemon, etc) has opened the chardev on
 	if (ctx->status == CLOSED)
 		return -EIO;
+	if (!cxl_adapter_link_ok(ctx->afu->adapter))
+		return -EIO;
 	pr_devel("afu_ioctl\n");
 	switch (cmd) {
 	case CXL_IOCTL_START_WORK:
 	return -EINVAL;
 }
-long afu_compat_ioctl(struct file *file, unsigned int cmd,
+static long afu_compat_ioctl(struct file *file, unsigned int cmd,
 			     unsigned long arg)
 {
 	return afu_ioctl(file, cmd, arg);
 	if (ctx->status != STARTED)
 		return -EIO;
+	if (!cxl_adapter_link_ok(ctx->afu->adapter))
+		return -EIO;
 	return cxl_context_iomap(ctx, vm);
 }
 	int rc;
 	DEFINE_WAIT(wait);
+	if (!cxl_adapter_link_ok(ctx->afu->adapter))
+		return -EIO;
 	if (count < CXL_READ_MIN_SIZE)
 		return -EINVAL;
 		if (ctx_event_pending(ctx))
 			break;
+		if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
+			rc = -EIO;
+			goto out;
+		}
 		if (file->f_flags & O_NONBLOCK) {
 			rc = -EAGAIN;
 			goto out;
 	.mmap           = afu_mmap,
 };
-const struct file_operations afu_master_fops = {
+static const struct file_operations afu_master_fops = {
 	.owner		= THIS_MODULE,
 	.open           = afu_master_open,
 	.poll		= afu_poll,
 	 * If these change we really need to update API.  Either change some
 	 * flags or update API version number CXL_API_VERSION.
 	 */
-	BUILD_BUG_ON(CXL_API_VERSION != 1);
+	BUILD_BUG_ON(CXL_API_VERSION != 2);
 	BUILD_BUG_ON(sizeof(struct cxl_ioctl_start_work) != 64);
 	BUILD_BUG_ON(sizeof(struct cxl_event_header) != 8);
 	BUILD_BUG_ON(sizeof(struct cxl_event_afu_interrupt) != 8);

drivers/misc/cxl/irq.c+36−20

 	serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
 	afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
-	dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
+	dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
-	dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%.16llx\n", fir1);
+	dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
-	dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%.16llx\n", fir2);
+	dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
-	dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
+	dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
-	dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
+	dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
-	dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
+	dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
 	dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
 	cxl_stop_trace(ctx->afu->adapter);
 	fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
 	errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 	afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
-	dev_crit(&afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
+	dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
-	dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
+	dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
-	dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%.16llx\n", errstat);
+	dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
-	dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
+	dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
 	cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
 	WARN(1, "CXL ERROR interrupt %i\n", irq);
 	err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
-	dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%.16llx\n", err_ivte);
+	dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
 	dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
 	cxl_stop_trace(adapter);
 	fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
 	fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
-	dev_crit(&adapter->dev, "PSL_FIR1: 0x%.16llx\nPSL_FIR2: 0x%.16llx\n", fir1, fir2);
+	dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
 	return IRQ_HANDLED;
 }
 	if (dsisr & CXL_PSL_DSISR_An_PE)
 		return handle_psl_slice_error(ctx, dsisr, irq_info->errstat);
 	if (dsisr & CXL_PSL_DSISR_An_AE) {
-		pr_devel("CXL interrupt: AFU Error %.llx\n", irq_info->afu_err);
+		pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err);
 		if (ctx->pending_afu_err) {
 			/*
 			 * probably best that we log them somewhere:
 			 */
 			dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
-					    "undelivered to pe %i: %.llx\n",
+					    "undelivered to pe %i: 0x%016llx\n",
 					    ctx->pe, irq_info->afu_err);
 		} else {
 			spin_lock(&ctx->lock);
 	}
 	rcu_read_unlock();
-	WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %.16llx DAR"
+	WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
-		" %.16llx\n(Possible AFU HW issue - was a term/remove acked"
+		" %016llx\n(Possible AFU HW issue - was a term/remove acked"
 		" with outstanding transactions?)\n", ph, irq_info.dsisr,
 		irq_info.dar);
 	return fail_psl_irq(afu, &irq_info);
 void cxl_release_psl_err_irq(struct cxl *adapter)
 {
+	if (adapter->err_virq != irq_find_mapping(NULL, adapter->err_hwirq))
+		return;
 	cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
 	cxl_unmap_irq(adapter->err_virq, adapter);
 	cxl_release_one_irq(adapter, adapter->err_hwirq);
 void cxl_release_serr_irq(struct cxl_afu *afu)
 {
+	if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
+		return;
 	cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
 	cxl_unmap_irq(afu->serr_virq, afu);
 	cxl_release_one_irq(afu->adapter, afu->serr_hwirq);
 void cxl_release_psl_irq(struct cxl_afu *afu)
 {
+	if (afu->psl_virq != irq_find_mapping(NULL, afu->psl_hwirq))
+		return;
 	cxl_unmap_irq(afu->psl_virq, afu);
 	cxl_release_one_irq(afu->adapter, afu->psl_hwirq);
 	kfree(afu->psl_irq_name);
 }
-void afu_irq_name_free(struct cxl_context *ctx)
+static void afu_irq_name_free(struct cxl_context *ctx)
 {
 	struct cxl_irq_name *irq_name, *tmp;
 	int rc, r, i, j = 1;
 	struct cxl_irq_name *irq_name;
+	/* Initialize the list head to hold irq names */
+	INIT_LIST_HEAD(&ctx->irq_names);
 	if ((rc = cxl_alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, count)))
 		return rc;
 	ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
 				  sizeof(*ctx->irq_bitmap), GFP_KERNEL);
 	if (!ctx->irq_bitmap)
-		return -ENOMEM;
+		goto out;
 	/*
 	 * Allocate names first.  If any fail, bail out before allocating
 	 * actual hardware IRQs.
 	 */
-	INIT_LIST_HEAD(&ctx->irq_names);
 	for (r = 1; r < CXL_IRQ_RANGES; r++) {
 		for (i = 0; i < ctx->irqs.range[r]; i++) {
 			irq_name = kmalloc(sizeof(struct cxl_irq_name),
 	return 0;
 out:
+	cxl_release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
 	afu_irq_name_free(ctx);
 	return -ENOMEM;
 }
-void afu_register_hwirqs(struct cxl_context *ctx)
+static void afu_register_hwirqs(struct cxl_context *ctx)
 {
 	irq_hw_number_t hwirq;
 	struct cxl_irq_name *irq_name;
 	afu_irq_name_free(ctx);
 	cxl_release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
+	kfree(ctx->irq_bitmap);
+	ctx->irq_bitmap = NULL;
+	ctx->irq_count = 0;
 }

drivers/misc/cxl/main.c+1−0

@@ -222,6 +222,7 @@ static void exit_cxl(void) · 221 unmodified lines
222	cxl_debugfs_exit();	222	cxl_debugfs_exit();
223	cxl_file_exit();	223	cxl_file_exit();
224	unregister_cxl_calls(&cxl_calls);	224	unregister_cxl_calls(&cxl_calls);
		225	idr_destroy(&cxl_adapter_idr);
225	}	226	}
226		227
227	module_init(init_cxl);	228	module_init(init_cxl);

drivers/misc/cxl/native.c+97−22

@@ -41,7 +41,14 @@ static int afu_control(struct cxl_afu *afu, u64 command, · 40 unmodified lines
41	rc = -EBUSY;	41	rc = -EBUSY;
42	goto out;	42	goto out;
43	}	43	}
44	pr_devel_ratelimited("AFU control... (0x%.16llx)\n",	44
		45	if (!cxl_adapter_link_ok(afu->adapter)) {
		46	afu->enabled = enabled;
		47	rc = -EIO;
		48	goto out;
		49	}
		50
		51	pr_devel_ratelimited("AFU control... (0x%016llx)\n",
45	AFU_Cntl \| command);	52	AFU_Cntl \| command);
46	cpu_relax();	53	cpu_relax();
47	AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);	54	AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
@@ -85,6 +92,10 @@ int __cxl_afu_reset(struct cxl_afu *afu) · 37 unmodified lines
85		92
86	int cxl_afu_check_and_enable(struct cxl_afu *afu)	93	int cxl_afu_check_and_enable(struct cxl_afu *afu)
87	{	94	{
		95	if (!cxl_adapter_link_ok(afu->adapter)) {
		96	WARN(1, "Refusing to enable afu while link down!\n");
		97	return -EIO;
		98	}
88	if (afu->enabled)	99	if (afu->enabled)
89	return 0;	100	return 0;
90	return afu_enable(afu);	101	return afu_enable(afu);
@@ -103,6 +114,12 @@ int cxl_psl_purge(struct cxl_afu *afu) · 12 unmodified lines
103		114
104	pr_devel("PSL purge request\n");	115	pr_devel("PSL purge request\n");
105		116
		117	if (!cxl_adapter_link_ok(afu->adapter)) {
		118	dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
		119	rc = -EIO;
		120	goto out;
		121	}
		122
106	if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {	123	if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
107	WARN(1, "psl_purge request while AFU not disabled!\n");	124	WARN(1, "psl_purge request while AFU not disabled!\n");
108	cxl_afu_disable(afu);	125	cxl_afu_disable(afu);
@@ -119,14 +136,19 @@ int cxl_psl_purge(struct cxl_afu *afu) · 10 unmodified lines
119	rc = -EBUSY;	136	rc = -EBUSY;
120	goto out;	137	goto out;
121	}	138	}
		139	if (!cxl_adapter_link_ok(afu->adapter)) {
		140	rc = -EIO;
		141	goto out;
		142	}
		143
122	dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);	144	dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
123	pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%.16llx PSL_DSISR: 0x%.16llx\n", PSL_CNTL, dsisr);	145	pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
124	if (dsisr & CXL_PSL_DSISR_TRANS) {	146	if (dsisr & CXL_PSL_DSISR_TRANS) {
125	dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);	147	dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
126	dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%.16llx, DAR: 0x%.16llx\n", dsisr, dar);	148	dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
127	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);	149	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
128	} else if (dsisr) {	150	} else if (dsisr) {
129	dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%.16llx\n", dsisr);	151	dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
130	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);	152	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
131	} else {	153	} else {
132	cpu_relax();	154	cpu_relax();
@@ -161,10 +183,8 @@ static int spa_max_procs(int spa_size) · 28 unmodified lines
161	return ((spa_size / 8) - 96) / 17;	183	return ((spa_size / 8) - 96) / 17;
162	}	184	}
163		185
164	static int alloc_spa(struct cxl_afu *afu)	186	int cxl_alloc_spa(struct cxl_afu *afu)
165	{	187	{
166	u64 spap;
167
168	/* Work out how many pages to allocate */	188	/* Work out how many pages to allocate */
169	afu->spa_order = 0;	189	afu->spa_order = 0;
170	do {	190	do {
@@ -183,6 +203,13 @@ static int alloc_spa(struct cxl_afu *afu) · 12 unmodified lines
183	pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",	203	pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
184	1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);	204	1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);
185		205
		206	return 0;
		207	}
		208
		209	static void attach_spa(struct cxl_afu *afu)
		210	{
		211	u64 spap;
		212
186	afu->sw_command_status = (__be64 )((char )afu->spa +	213	afu->sw_command_status = (__be64 )((char )afu->spa +
187	((afu->spa_max_procs + 3) * 128));	214	((afu->spa_max_procs + 3) * 128));
188		215
@@ -191,14 +218,19 @@ static int alloc_spa(struct cxl_afu *afu) · 2 unmodified lines
191	spap \|= CXL_PSL_SPAP_V;	218	spap \|= CXL_PSL_SPAP_V;
192	pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);	219	pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);
193	cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);	220	cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
194
195	return 0;
196	}	221	}
197		222
198	static void release_spa(struct cxl_afu *afu)	223	static inline void detach_spa(struct cxl_afu *afu)
199	{	224	{
200	cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);	225	cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
201	free_pages((unsigned long) afu->spa, afu->spa_order);	226	}
		227
		228	void cxl_release_spa(struct cxl_afu *afu)
		229	{
		230	if (afu->spa) {
		231	free_pages((unsigned long) afu->spa, afu->spa_order);
		232	afu->spa = NULL;
		233	}
202	}	234	}
203		235
204	int cxl_tlb_slb_invalidate(struct cxl *adapter)	236	int cxl_tlb_slb_invalidate(struct cxl *adapter)
@@ -215,6 +247,8 @@ int cxl_tlb_slb_invalidate(struct cxl *adapter) · 10 unmodified lines
215	dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");	247	dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
216	return -EBUSY;	248	return -EBUSY;
217	}	249	}
		250	if (!cxl_adapter_link_ok(adapter))
		251	return -EIO;
218	cpu_relax();	252	cpu_relax();
219	}	253	}
220		254
@@ -224,6 +258,8 @@ int cxl_tlb_slb_invalidate(struct cxl *adapter) · 3 unmodified lines
224	dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");	258	dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
225	return -EBUSY;	259	return -EBUSY;
226	}	260	}
		261	if (!cxl_adapter_link_ok(adapter))
		262	return -EIO;
227	cpu_relax();	263	cpu_relax();
228	}	264	}
229	return 0;	265	return 0;
@@ -240,6 +276,11 @@ int cxl_afu_slbia(struct cxl_afu *afu) · 10 unmodified lines
240	dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");	276	dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
241	return -EBUSY;	277	return -EBUSY;
242	}	278	}
		279	/* If the adapter has gone down, we can assume that we
		280	* will PERST it and that will invalidate everything.
		281	*/
		282	if (!cxl_adapter_link_ok(afu->adapter))
		283	return -EIO;
243	cpu_relax();	284	cpu_relax();
244	}	285	}
245	return 0;	286	return 0;
@@ -279,6 +320,8 @@ static void slb_invalid(struct cxl_context *ctx) · 33 unmodified lines
279	cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);	320	cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
280		321
281	while (1) {	322	while (1) {
		323	if (!cxl_adapter_link_ok(adapter))
		324	break;
282	slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);	325	slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
283	if (!(slbia & CXL_TLB_SLB_P))	326	if (!(slbia & CXL_TLB_SLB_P))
284	break;	327	break;
@@ -308,6 +351,11 @@ static int do_process_element_cmd(struct cxl_context *ctx, · 23 unmodified lines
308	rc = -EBUSY;	351	rc = -EBUSY;
309	goto out;	352	goto out;
310	}	353	}
		354	if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
		355	dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
		356	rc = -EIO;
		357	goto out;
		358	}
311	state = be64_to_cpup(ctx->afu->sw_command_status);	359	state = be64_to_cpup(ctx->afu->sw_command_status);
312	if (state == ~0ULL) {	360	if (state == ~0ULL) {
313	pr_err("cxl: Error adding process element to AFU\n");	361	pr_err("cxl: Error adding process element to AFU\n");
@@ -355,8 +403,13 @@ static int terminate_process_element(struct cxl_context *ctx) · 41 unmodified lines
355		403
356	mutex_lock(&ctx->afu->spa_mutex);	404	mutex_lock(&ctx->afu->spa_mutex);
357	pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);	405	pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
358	rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,	406	/* We could be asked to terminate when the hw is down. That
359	CXL_PE_SOFTWARE_STATE_V \| CXL_PE_SOFTWARE_STATE_T);	407	* should always succeed: it's not running if the hw has gone
		408	* away and is being reset.
		409	*/
		410	if (cxl_adapter_link_ok(ctx->afu->adapter))
		411	rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
		412	CXL_PE_SOFTWARE_STATE_V \| CXL_PE_SOFTWARE_STATE_T);
360	ctx->elem->software_state = 0; /* Remove Valid bit */	413	ctx->elem->software_state = 0; /* Remove Valid bit */
361	pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);	414	pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
362	mutex_unlock(&ctx->afu->spa_mutex);	415	mutex_unlock(&ctx->afu->spa_mutex);
@@ -369,7 +422,14 @@ static int remove_process_element(struct cxl_context *ctx) · 6 unmodified lines
369		422
370	mutex_lock(&ctx->afu->spa_mutex);	423	mutex_lock(&ctx->afu->spa_mutex);
371	pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);	424	pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
372	if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0)))	425
		426	/* We could be asked to remove when the hw is down. Again, if
		427	* the hw is down, the PE is gone, so we succeed.
		428	*/
		429	if (cxl_adapter_link_ok(ctx->afu->adapter))
		430	rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
		431
		432	if (!rc)
373	ctx->pe_inserted = false;	433	ctx->pe_inserted = false;
374	slb_invalid(ctx);	434	slb_invalid(ctx);
375	pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);	435	pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
@@ -397,8 +457,11 @@ static int activate_afu_directed(struct cxl_afu *afu) · 21 unmodified lines
397		457
398	dev_info(&afu->dev, "Activating AFU directed mode\n");	458	dev_info(&afu->dev, "Activating AFU directed mode\n");
399		459
400	if (alloc_spa(afu))	460	if (afu->spa == NULL) {
401	return -ENOMEM;	461	if (cxl_alloc_spa(afu))
		462	return -ENOMEM;
		463	}
		464	attach_spa(afu);
402		465
403	cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);	466	cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
404	cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);	467	cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
@@ -492,9 +555,7 @@ static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) · 87 unmodified lines
492	if ((result = cxl_afu_check_and_enable(ctx->afu)))	555	if ((result = cxl_afu_check_and_enable(ctx->afu)))
493	return result;	556	return result;
494		557
495	add_process_element(ctx);	558	return add_process_element(ctx);
496
497	return 0;
498	}	559	}
499		560
500	static int deactivate_afu_directed(struct cxl_afu *afu)	561	static int deactivate_afu_directed(struct cxl_afu *afu)
@@ -511,8 +572,6 @@ static int deactivate_afu_directed(struct cxl_afu *afu) · 10 unmodified lines
511	cxl_afu_disable(afu);	572	cxl_afu_disable(afu);
512	cxl_psl_purge(afu);	573	cxl_psl_purge(afu);
513		574
514	release_spa(afu);
515
516	return 0;	575	return 0;
517	}	576	}
518		577
@@ -614,6 +673,11 @@ int cxl_afu_activate_mode(struct cxl_afu *afu, int mode) · 95 unmodified lines
614	if (!(mode & afu->modes_supported))	673	if (!(mode & afu->modes_supported))
615	return -EINVAL;	674	return -EINVAL;
616		675
		676	if (!cxl_adapter_link_ok(afu->adapter)) {
		677	WARN(1, "Device link is down, refusing to activate!\n");
		678	return -EIO;
		679	}
		680
617	if (mode == CXL_MODE_DIRECTED)	681	if (mode == CXL_MODE_DIRECTED)
618	return activate_afu_directed(afu);	682	return activate_afu_directed(afu);
619	if (mode == CXL_MODE_DEDICATED)	683	if (mode == CXL_MODE_DEDICATED)
@@ -624,6 +688,11 @@ int cxl_afu_activate_mode(struct cxl_afu *afu, int mode) · 4 unmodified lines
624		688
625	int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)	689	int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
626	{	690	{
		691	if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
		692	WARN(1, "Device link is down, refusing to attach process!\n");
		693	return -EIO;
		694	}
		695
627	ctx->kernel = kernel;	696	ctx->kernel = kernel;
628	if (ctx->afu->current_mode == CXL_MODE_DIRECTED)	697	if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
629	return attach_afu_directed(ctx, wed, amr);	698	return attach_afu_directed(ctx, wed, amr);
@@ -668,6 +737,12 @@ int cxl_get_irq(struct cxl_afu afu, struct cxl_irq_info info) · 38 unmodified lines
668	{	737	{
669	u64 pidtid;	738	u64 pidtid;
670		739
		740	/* If the adapter has gone away, we can't get any meaningful
		741	* information.
		742	*/
		743	if (!cxl_adapter_link_ok(afu->adapter))
		744	return -EIO;
		745
671	info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);	746	info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
672	info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);	747	info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
673	info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);	748	info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
@@ -684,7 +759,7 @@ static void recover_psl_err(struct cxl_afu *afu, u64 errstat) · 10 unmodified lines
684	{	759	{
685	u64 dsisr;	760	u64 dsisr;
686		761
687	pr_devel("RECOVERING FROM PSL ERROR... (0x%.16llx)\n", errstat);	762	pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
688		763
689	/* Clear PSL_DSISR[PE] */	764	/* Clear PSL_DSISR[PE] */
690	dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);	765	dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);

drivers/misc/cxl/pci.c+486−125

@@ -24,6 +24,7 @@ · 23 unmodified lines
24	#include <asm/io.h>	24	#include <asm/io.h>
25		25
26	#include "cxl.h"	26	#include "cxl.h"
		27	#include <misc/cxl.h>
27		28
28		29
29	#define CXL_PCI_VSEC_ID 0x1280	30	#define CXL_PCI_VSEC_ID 0x1280
@@ -133,7 +134,7 @@ u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off) · 103 unmodified lines
133	return (val >> ((off & 0x3) * 8)) & 0xff;	134	return (val >> ((off & 0x3) * 8)) & 0xff;
134	}	135	}
135		136
136	static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = {	137	static const struct pci_device_id cxl_pci_tbl[] = {
137	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },	138	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
138	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },	139	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
139	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },	140	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
@@ -369,6 +370,55 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev · 229 unmodified lines
369	return 0;	370	return 0;
370	}	371	}
371		372
		373	#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
		374	#define _2048_250MHZ_CYCLES 1
		375
		376	static int cxl_setup_psl_timebase(struct cxl adapter, struct pci_dev dev)
		377	{
		378	u64 psl_tb;
		379	int delta;
		380	unsigned int retry = 0;
		381	struct device_node *np;
		382
		383	if (!(np = pnv_pci_get_phb_node(dev)))
		384	return -ENODEV;
		385
		386	/* Do not fail when CAPP timebase sync is not supported by OPAL */
		387	of_node_get(np);
		388	if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
		389	of_node_put(np);
		390	pr_err("PSL: Timebase sync: OPAL support missing\n");
		391	return 0;
		392	}
		393	of_node_put(np);
		394
		395	/*
		396	* Setup PSL Timebase Control and Status register
		397	* with the recommended Timebase Sync Count value
		398	*/
		399	cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
		400	TBSYNC_CNT(2 * _2048_250MHZ_CYCLES));
		401
		402	/* Enable PSL Timebase */
		403	cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
		404	cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
		405
		406	/* Wait until CORE TB and PSL TB difference <= 16usecs */
		407	do {
		408	msleep(1);
		409	if (retry++ > 5) {
		410	pr_err("PSL: Timebase sync: giving up!\n");
		411	return -EIO;
		412	}
		413	psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase);
		414	delta = mftb() - psl_tb;
		415	if (delta < 0)
		416	delta = -delta;
		417	} while (cputime_to_usecs(delta) > 16);
		418
		419	return 0;
		420	}
		421
372	static int init_implementation_afu_regs(struct cxl_afu *afu)	422	static int init_implementation_afu_regs(struct cxl_afu *afu)
373	{	423	{
374	/* read/write masks for this slice */	424	/* read/write masks for this slice */
@@ -539,10 +589,18 @@ err: · 164 unmodified lines
539		589
540	static void cxl_unmap_slice_regs(struct cxl_afu *afu)	590	static void cxl_unmap_slice_regs(struct cxl_afu *afu)
541	{	591	{
542	if (afu->p2n_mmio)	592	if (afu->p2n_mmio) {
543	iounmap(afu->p2n_mmio);	593	iounmap(afu->p2n_mmio);
544	if (afu->p1n_mmio)	594	afu->p2n_mmio = NULL;
		595	}
		596	if (afu->p1n_mmio) {
545	iounmap(afu->p1n_mmio);	597	iounmap(afu->p1n_mmio);
		598	afu->p1n_mmio = NULL;
		599	}
		600	if (afu->afu_desc_mmio) {
		601	iounmap(afu->afu_desc_mmio);
		602	afu->afu_desc_mmio = NULL;
		603	}
546	}	604	}
547		605
548	static void cxl_release_afu(struct device *dev)	606	static void cxl_release_afu(struct device *dev)
@@ -551,6 +609,9 @@ static void cxl_release_afu(struct device *dev) · 2 unmodified lines
551		609
552	pr_devel("cxl_release_afu\n");	610	pr_devel("cxl_release_afu\n");
553		611
		612	idr_destroy(&afu->contexts_idr);
		613	cxl_release_spa(afu);
		614
554	kfree(afu);	615	kfree(afu);
555	}	616	}
556		617
@@ -656,7 +717,7 @@ static int sanitise_afu_regs(struct cxl_afu *afu) · 99 unmodified lines
656	*/	717	*/
657	reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);	718	reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
658	if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {	719	if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
659	dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg);	720	dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
660	if (__cxl_afu_reset(afu))	721	if (__cxl_afu_reset(afu))
661	return -EIO;	722	return -EIO;
662	if (cxl_afu_disable(afu))	723	if (cxl_afu_disable(afu))
@@ -677,7 +738,7 @@ static int sanitise_afu_regs(struct cxl_afu *afu) · 14 unmodified lines
677	cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);	738	cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
678	reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);	739	reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
679	if (reg) {	740	if (reg) {
680	dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg);	741	dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
681	if (reg & CXL_PSL_DSISR_TRANS)	742	if (reg & CXL_PSL_DSISR_TRANS)
682	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);	743	cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
683	else	744	else
@@ -686,12 +747,12 @@ static int sanitise_afu_regs(struct cxl_afu *afu) · 2 unmodified lines
686	reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);	747	reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
687	if (reg) {	748	if (reg) {
688	if (reg & ~0xffff)	749	if (reg & ~0xffff)
689	dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg);	750	dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
690	cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);	751	cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
691	}	752	}
692	reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);	753	reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
693	if (reg) {	754	if (reg) {
694	dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg);	755	dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
695	cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);	756	cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
696	}	757	}
697		758
@@ -742,45 +803,70 @@ ssize_t cxl_afu_read_err_buffer(struct cxl_afu afu, char buf, · 44 unmodified lines
742	return count;	803	return count;
743	}	804	}
744		805
745	static int cxl_init_afu(struct cxl adapter, int slice, struct pci_dev dev)	806	static int cxl_configure_afu(struct cxl_afu afu, struct cxl adapter, struct pci_dev *dev)
746	{	807	{
747	struct cxl_afu *afu;
748	bool free = true;
749	int rc;	808	int rc;
750		809
751	if (!(afu = cxl_alloc_afu(adapter, slice)))
752	return -ENOMEM;
753
754	if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice)))
755	goto err1;
756
757	if ((rc = cxl_map_slice_regs(afu, adapter, dev)))	810	if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
758	goto err1;	811	return rc;
759		812
760	if ((rc = sanitise_afu_regs(afu)))	813	if ((rc = sanitise_afu_regs(afu)))
761	goto err2;	814	goto err1;
762		815
763	/* We need to reset the AFU before we can read the AFU descriptor */	816	/* We need to reset the AFU before we can read the AFU descriptor */
764	if ((rc = __cxl_afu_reset(afu)))	817	if ((rc = __cxl_afu_reset(afu)))
765	goto err2;	818	goto err1;
766		819
767	if (cxl_verbose)	820	if (cxl_verbose)
768	dump_afu_descriptor(afu);	821	dump_afu_descriptor(afu);
769		822
770	if ((rc = cxl_read_afu_descriptor(afu)))	823	if ((rc = cxl_read_afu_descriptor(afu)))
771	goto err2;	824	goto err1;
772		825
773	if ((rc = cxl_afu_descriptor_looks_ok(afu)))	826	if ((rc = cxl_afu_descriptor_looks_ok(afu)))
774	goto err2;	827	goto err1;
775		828
776	if ((rc = init_implementation_afu_regs(afu)))	829	if ((rc = init_implementation_afu_regs(afu)))
777	goto err2;	830	goto err1;
778		831
779	if ((rc = cxl_register_serr_irq(afu)))	832	if ((rc = cxl_register_serr_irq(afu)))
780	goto err2;	833	goto err1;
781		834
782	if ((rc = cxl_register_psl_irq(afu)))	835	if ((rc = cxl_register_psl_irq(afu)))
783	goto err3;	836	goto err2;
		837
		838	return 0;
		839
		840	err2:
		841	cxl_release_serr_irq(afu);
		842	err1:
		843	cxl_unmap_slice_regs(afu);
		844	return rc;
		845	}
		846
		847	static void cxl_deconfigure_afu(struct cxl_afu *afu)
		848	{
		849	cxl_release_psl_irq(afu);
		850	cxl_release_serr_irq(afu);
		851	cxl_unmap_slice_regs(afu);
		852	}
		853
		854	static int cxl_init_afu(struct cxl adapter, int slice, struct pci_dev dev)
		855	{
		856	struct cxl_afu *afu;
		857	int rc;
		858
		859	afu = cxl_alloc_afu(adapter, slice);
		860	if (!afu)
		861	return -ENOMEM;
		862
		863	rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
		864	if (rc)
		865	goto err_free;
		866
		867	rc = cxl_configure_afu(afu, adapter, dev);
		868	if (rc)
		869	goto err_free;
784		870
785	/* Don't care if this fails */	871	/* Don't care if this fails */
786	cxl_debugfs_afu_add(afu);	872	cxl_debugfs_afu_add(afu);
@@ -795,10 +881,6 @@ static int cxl_init_afu(struct cxl adapter, int slice, struct pci_dev dev) · 8 unmodified lines
795	if ((rc = cxl_sysfs_afu_add(afu)))	881	if ((rc = cxl_sysfs_afu_add(afu)))
796	goto err_put1;	882	goto err_put1;
797		883
798
799	if ((rc = cxl_afu_select_best_mode(afu)))
800	goto err_put2;
801
802	adapter->afu[afu->slice] = afu;	884	adapter->afu[afu->slice] = afu;
803		885
804	if ((rc = cxl_pci_vphb_add(afu)))	886	if ((rc = cxl_pci_vphb_add(afu)))
@@ -806,21 +888,16 @@ static int cxl_init_afu(struct cxl adapter, int slice, struct pci_dev dev) · 1 unmodified line
806		888
807	return 0;	889	return 0;
808		890
809	err_put2:
810	cxl_sysfs_afu_remove(afu);
811	err_put1:	891	err_put1:
812	device_unregister(&afu->dev);	892	cxl_deconfigure_afu(afu);
813	free = false;
814	cxl_debugfs_afu_remove(afu);	893	cxl_debugfs_afu_remove(afu);
815	cxl_release_psl_irq(afu);	894	device_unregister(&afu->dev);
816	err3:	895	return rc;
817	cxl_release_serr_irq(afu);	896
818	err2:	897	err_free:
819	cxl_unmap_slice_regs(afu);	898	kfree(afu);
820	err1:
821	if (free)
822	kfree(afu);
823	return rc;	899	return rc;
		900
824	}	901	}
825		902
826	static void cxl_remove_afu(struct cxl_afu *afu)	903	static void cxl_remove_afu(struct cxl_afu *afu)
@@ -840,10 +917,7 @@ static void cxl_remove_afu(struct cxl_afu *afu) · 13 unmodified lines
840	cxl_context_detach_all(afu);	917	cxl_context_detach_all(afu);
841	cxl_afu_deactivate_mode(afu);	918	cxl_afu_deactivate_mode(afu);
842		919
843	cxl_release_psl_irq(afu);	920	cxl_deconfigure_afu(afu);
844	cxl_release_serr_irq(afu);
845	cxl_unmap_slice_regs(afu);
846
847	device_unregister(&afu->dev);	921	device_unregister(&afu->dev);
848	}	922	}
849		923
@@ -851,16 +925,15 @@ int cxl_reset(struct cxl *adapter) · 1 unmodified line
851	{	925	{
852	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);	926	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
853	int rc;	927	int rc;
854	int i;
855	u32 val;
856
857	dev_info(&dev->dev, "CXL reset\n");
858		928
859	for (i = 0; i < adapter->slices; i++) {	929	if (adapter->perst_same_image) {
860	cxl_pci_vphb_remove(adapter->afu[i]);	930	dev_warn(&dev->dev,
861	cxl_remove_afu(adapter->afu[i]);	931	"cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
		932	return -EINVAL;
862	}	933	}
863		934
		935	dev_info(&dev->dev, "CXL reset\n");
		936
864	/* pcie_warm_reset requests a fundamental pci reset which includes a	937	/* pcie_warm_reset requests a fundamental pci reset which includes a
865	* PERST assert/deassert. PERST triggers a loading of the image	938	* PERST assert/deassert. PERST triggers a loading of the image
866	* if "user" or "factory" is selected in sysfs */	939	* if "user" or "factory" is selected in sysfs */
@@ -869,20 +942,6 @@ int cxl_reset(struct cxl *adapter) · 2 unmodified lines
869	return rc;	942	return rc;
870	}	943	}
871		944
872	/* the PERST done above fences the PHB. So, reset depends on EEH
873	* to unbind the driver, tell Sapphire to reinit the PHB, and rebind
874	* the driver. Do an mmio read explictly to ensure EEH notices the
875	* fenced PHB. Retry for a few seconds before giving up. */
876	i = 0;
877	while (((val = mmio_read32be(adapter->p1_mmio)) != 0xffffffff) &&
878	(i < 5)) {
879	msleep(500);
880	i++;
881	}
882
883	if (val != 0xffffffff)
884	dev_err(&dev->dev, "cxl: PERST failed to trigger EEH\n");
885
886	return rc;	945	return rc;
887	}	946	}
888		947
@@ -893,7 +952,7 @@ static int cxl_map_adapter_regs(struct cxl adapter, struct pci_dev dev) · 4 unmodified lines
893	if (pci_request_region(dev, 0, "priv 1 regs"))	952	if (pci_request_region(dev, 0, "priv 1 regs"))
894	goto err2;	953	goto err2;
895		954
896	pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",	955	pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
897	p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));	956	p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
898		957
899	if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))	958	if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
@@ -917,10 +976,16 @@ err1: · 17 unmodified lines
917		976
918	static void cxl_unmap_adapter_regs(struct cxl *adapter)	977	static void cxl_unmap_adapter_regs(struct cxl *adapter)
919	{	978	{
920	if (adapter->p1_mmio)	979	if (adapter->p1_mmio) {
921	iounmap(adapter->p1_mmio);	980	iounmap(adapter->p1_mmio);
922	if (adapter->p2_mmio)	981	adapter->p1_mmio = NULL;
		982	pci_release_region(to_pci_dev(adapter->dev.parent), 2);
		983	}
		984	if (adapter->p2_mmio) {
923	iounmap(adapter->p2_mmio);	985	iounmap(adapter->p2_mmio);
		986	adapter->p2_mmio = NULL;
		987	pci_release_region(to_pci_dev(adapter->dev.parent), 0);
		988	}
924	}	989	}
925		990
926	static int cxl_read_vsec(struct cxl adapter, struct pci_dev dev)	991	static int cxl_read_vsec(struct cxl adapter, struct pci_dev dev)
@@ -949,7 +1014,6 @@ static int cxl_read_vsec(struct cxl adapter, struct pci_dev dev) · 22 unmodified lines
949	CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);	1014	CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
950	CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);	1015	CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
951	adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);	1016	adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
952	adapter->perst_loads_image = true;
953	adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);	1017	adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
954		1018
955	CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);	1019	CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
@@ -1009,81 +1073,138 @@ static void cxl_release_adapter(struct device *dev) · 53 unmodified lines
1009		1073
1010	pr_devel("cxl_release_adapter\n");	1074	pr_devel("cxl_release_adapter\n");
1011		1075
		1076	cxl_remove_adapter_nr(adapter);
		1077
1012	kfree(adapter);	1078	kfree(adapter);
1013	}	1079	}
1014		1080
1015	static struct cxl cxl_alloc_adapter(struct pci_dev dev)	1081	static struct cxl *cxl_alloc_adapter(void)
1016	{	1082	{
1017	struct cxl *adapter;	1083	struct cxl *adapter;
1018		1084
1019	if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))	1085	if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
1020	return NULL;	1086	return NULL;
1021		1087
1022	adapter->dev.parent = &dev->dev;
1023	adapter->dev.release = cxl_release_adapter;
1024	pci_set_drvdata(dev, adapter);
1025	spin_lock_init(&adapter->afu_list_lock);	1088	spin_lock_init(&adapter->afu_list_lock);
1026		1089
		1090	if (cxl_alloc_adapter_nr(adapter))
		1091	goto err1;
		1092
		1093	if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
		1094	goto err2;
		1095
1027	return adapter;	1096	return adapter;
		1097
		1098	err2:
		1099	cxl_remove_adapter_nr(adapter);
		1100	err1:
		1101	kfree(adapter);
		1102	return NULL;
1028	}	1103	}
1029		1104
		1105	#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
		1106
1030	static int sanitise_adapter_regs(struct cxl *adapter)	1107	static int sanitise_adapter_regs(struct cxl *adapter)
1031	{	1108	{
1032	cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);	1109	/* Clear PSL tberror bit by writing 1 to it */
		1110	cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1033	return cxl_tlb_slb_invalidate(adapter);	1111	return cxl_tlb_slb_invalidate(adapter);
1034	}	1112	}
1035		1113
1036	static struct cxl cxl_init_adapter(struct pci_dev dev)	1114	/* This should contain only operations that can safely be done in
		1115	* both creation and recovery.
		1116	*/
		1117	static int cxl_configure_adapter(struct cxl adapter, struct pci_dev dev)
1037	{	1118	{
1038	struct cxl *adapter;
1039	bool free = true;
1040	int rc;	1119	int rc;
1041		1120
		1121	adapter->dev.parent = &dev->dev;
		1122	adapter->dev.release = cxl_release_adapter;
		1123	pci_set_drvdata(dev, adapter);
1042		1124
1043	if (!(adapter = cxl_alloc_adapter(dev)))	1125	rc = pci_enable_device(dev);
1044	return ERR_PTR(-ENOMEM);	1126	if (rc) {
		1127	dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
		1128	return rc;
		1129	}
1045		1130
1046	if ((rc = cxl_read_vsec(adapter, dev)))	1131	if ((rc = cxl_read_vsec(adapter, dev)))
1047	goto err1;	1132	return rc;
1048		1133
1049	if ((rc = cxl_vsec_looks_ok(adapter, dev)))	1134	if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1050	goto err1;	1135	return rc;
1051		1136
1052	if ((rc = setup_cxl_bars(dev)))	1137	if ((rc = setup_cxl_bars(dev)))
1053	goto err1;	1138	return rc;
1054		1139
1055	if ((rc = switch_card_to_cxl(dev)))	1140	if ((rc = switch_card_to_cxl(dev)))
1056	goto err1;	1141	return rc;
1057
1058	if ((rc = cxl_alloc_adapter_nr(adapter)))
1059	goto err1;
1060
1061	if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)))
1062	goto err2;
1063		1142
1064	if ((rc = cxl_update_image_control(adapter)))	1143	if ((rc = cxl_update_image_control(adapter)))
1065	goto err2;	1144	return rc;
1066		1145
1067	if ((rc = cxl_map_adapter_regs(adapter, dev)))	1146	if ((rc = cxl_map_adapter_regs(adapter, dev)))
1068	goto err2;	1147	return rc;
1069		1148
1070	if ((rc = sanitise_adapter_regs(adapter)))	1149	if ((rc = sanitise_adapter_regs(adapter)))
1071	goto err2;	1150	goto err;
1072		1151
1073	if ((rc = init_implementation_adapter_regs(adapter, dev)))	1152	if ((rc = init_implementation_adapter_regs(adapter, dev)))
1074	goto err3;	1153	goto err;
1075		1154
1076	if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))	1155	if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
1077	goto err3;	1156	goto err;
1078		1157
1079	/* If recovery happened, the last step is to turn on snooping.	1158	/* If recovery happened, the last step is to turn on snooping.
1080	* In the non-recovery case this has no effect */	1159	* In the non-recovery case this has no effect */
1081	if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {	1160	if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1082	goto err3;	1161	goto err;
1083	}	1162
		1163	if ((rc = cxl_setup_psl_timebase(adapter, dev)))
		1164	goto err;
1084		1165
1085	if ((rc = cxl_register_psl_err_irq(adapter)))	1166	if ((rc = cxl_register_psl_err_irq(adapter)))
1086	goto err3;	1167	goto err;
		1168
		1169	return 0;
		1170
		1171	err:
		1172	cxl_unmap_adapter_regs(adapter);
		1173	return rc;
		1174
		1175	}
		1176
		1177	static void cxl_deconfigure_adapter(struct cxl *adapter)
		1178	{
		1179	struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
		1180
		1181	cxl_release_psl_err_irq(adapter);
		1182	cxl_unmap_adapter_regs(adapter);
		1183
		1184	pci_disable_device(pdev);
		1185	}
		1186
		1187	static struct cxl cxl_init_adapter(struct pci_dev dev)
		1188	{
		1189	struct cxl *adapter;
		1190	int rc;
		1191
		1192	adapter = cxl_alloc_adapter();
		1193	if (!adapter)
		1194	return ERR_PTR(-ENOMEM);
		1195
		1196	/* Set defaults for parameters which need to persist over
		1197	* configure/reconfigure
		1198	*/
		1199	adapter->perst_loads_image = true;
		1200	adapter->perst_same_image = false;
		1201
		1202	rc = cxl_configure_adapter(adapter, dev);
		1203	if (rc) {
		1204	pci_disable_device(dev);
		1205	cxl_release_adapter(&adapter->dev);
		1206	return ERR_PTR(rc);
		1207	}
1087		1208
1088	/* Don't care if this one fails: */	1209	/* Don't care if this one fails: */
1089	cxl_debugfs_adapter_add(adapter);	1210	cxl_debugfs_adapter_add(adapter);
@@ -1101,37 +1222,25 @@ static struct cxl cxl_init_adapter(struct pci_dev dev) · 11 unmodified lines
1101	return adapter;	1222	return adapter;
1102		1223
1103	err_put1:	1224	err_put1:
1104	device_unregister(&adapter->dev);	1225	/* This should mirror cxl_remove_adapter, except without the
1105	free = false;	1226	* sysfs parts
		1227	*/
1106	cxl_debugfs_adapter_remove(adapter);	1228	cxl_debugfs_adapter_remove(adapter);
1107	cxl_release_psl_err_irq(adapter);	1229	cxl_deconfigure_adapter(adapter);
1108	err3:	1230	device_unregister(&adapter->dev);
1109	cxl_unmap_adapter_regs(adapter);
1110	err2:
1111	cxl_remove_adapter_nr(adapter);
1112	err1:
1113	if (free)
1114	kfree(adapter);
1115	return ERR_PTR(rc);	1231	return ERR_PTR(rc);
1116	}	1232	}
1117		1233
1118	static void cxl_remove_adapter(struct cxl *adapter)	1234	static void cxl_remove_adapter(struct cxl *adapter)
1119	{	1235	{
1120	struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);	1236	pr_devel("cxl_remove_adapter\n");
1121
1122	pr_devel("cxl_release_adapter\n");
1123		1237
1124	cxl_sysfs_adapter_remove(adapter);	1238	cxl_sysfs_adapter_remove(adapter);
1125	cxl_debugfs_adapter_remove(adapter);	1239	cxl_debugfs_adapter_remove(adapter);
1126	cxl_release_psl_err_irq(adapter);
1127	cxl_unmap_adapter_regs(adapter);
1128	cxl_remove_adapter_nr(adapter);
1129		1240
1130	device_unregister(&adapter->dev);	1241	cxl_deconfigure_adapter(adapter);
1131		1242
1132	pci_release_region(pdev, 0);	1243	device_unregister(&adapter->dev);
1133	pci_release_region(pdev, 2);
1134	pci_disable_device(pdev);
1135	}	1244	}
1136		1245
1137	static int cxl_probe(struct pci_dev dev, const struct pci_device_id id)	1246	static int cxl_probe(struct pci_dev dev, const struct pci_device_id id)
@@ -1145,21 +1254,21 @@ static int cxl_probe(struct pci_dev dev, const struct pci_device_id id) · 7 unmodified lines
1145	if (cxl_verbose)	1254	if (cxl_verbose)
1146	dump_cxl_config_space(dev);	1255	dump_cxl_config_space(dev);
1147		1256
1148	if ((rc = pci_enable_device(dev))) {
1149	dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1150	return rc;
1151	}
1152
1153	adapter = cxl_init_adapter(dev);	1257	adapter = cxl_init_adapter(dev);
1154	if (IS_ERR(adapter)) {	1258	if (IS_ERR(adapter)) {
1155	dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));	1259	dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1156	pci_disable_device(dev);
1157	return PTR_ERR(adapter);	1260	return PTR_ERR(adapter);
1158	}	1261	}
1159		1262
1160	for (slice = 0; slice < adapter->slices; slice++) {	1263	for (slice = 0; slice < adapter->slices; slice++) {
1161	if ((rc = cxl_init_afu(adapter, slice, dev)))	1264	if ((rc = cxl_init_afu(adapter, slice, dev))) {
1162	dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);	1265	dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
		1266	continue;
		1267	}
		1268
		1269	rc = cxl_afu_select_best_mode(adapter->afu[slice]);
		1270	if (rc)
		1271	dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1163	}	1272	}
1164		1273
1165	return 0;	1274	return 0;
@@ -1183,10 +1292,262 @@ static void cxl_remove(struct pci_dev *dev) · 17 unmodified lines
1183	cxl_remove_adapter(adapter);	1292	cxl_remove_adapter(adapter);
1184	}	1293	}
1185		1294
		1295	static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
		1296	pci_channel_state_t state)
		1297	{
		1298	struct pci_dev *afu_dev;
		1299	pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
		1300	pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
		1301
		1302	/* There should only be one entry, but go through the list
		1303	* anyway
		1304	*/
		1305	list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
		1306	if (!afu_dev->driver)
		1307	continue;
		1308
		1309	afu_dev->error_state = state;
		1310
		1311	if (afu_dev->driver->err_handler)
		1312	afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
		1313	state);
		1314	/* Disconnect trumps all, NONE trumps NEED_RESET */
		1315	if (afu_result == PCI_ERS_RESULT_DISCONNECT)
		1316	result = PCI_ERS_RESULT_DISCONNECT;
		1317	else if ((afu_result == PCI_ERS_RESULT_NONE) &&
		1318	(result == PCI_ERS_RESULT_NEED_RESET))
		1319	result = PCI_ERS_RESULT_NONE;
		1320	}
		1321	return result;
		1322	}
		1323
		1324	static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
		1325	pci_channel_state_t state)
		1326	{
		1327	struct cxl *adapter = pci_get_drvdata(pdev);
		1328	struct cxl_afu *afu;
		1329	pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
		1330	int i;
		1331
		1332	/* At this point, we could still have an interrupt pending.
		1333	* Let's try to get them out of the way before they do
		1334	* anything we don't like.
		1335	*/
		1336	schedule();
		1337
		1338	/* If we're permanently dead, give up. */
		1339	if (state == pci_channel_io_perm_failure) {
		1340	/* Tell the AFU drivers; but we don't care what they
		1341	* say, we're going away.
		1342	*/
		1343	for (i = 0; i < adapter->slices; i++) {
		1344	afu = adapter->afu[i];
		1345	cxl_vphb_error_detected(afu, state);
		1346	}
		1347	return PCI_ERS_RESULT_DISCONNECT;
		1348	}
		1349
		1350	/* Are we reflashing?
		1351	*
		1352	* If we reflash, we could come back as something entirely
		1353	* different, including a non-CAPI card. As such, by default
		1354	* we don't participate in the process. We'll be unbound and
		1355	* the slot re-probed. (TODO: check EEH doesn't blindly rebind
		1356	* us!)
		1357	*
		1358	* However, this isn't the entire story: for reliablity
		1359	* reasons, we usually want to reflash the FPGA on PERST in
		1360	* order to get back to a more reliable known-good state.
		1361	*
		1362	* This causes us a bit of a problem: if we reflash we can't
		1363	* trust that we'll come back the same - we could have a new
		1364	* image and been PERSTed in order to load that
		1365	* image. However, most of the time we actually will come
		1366	* back the same - for example a regular EEH event.
		1367	*
		1368	* Therefore, we allow the user to assert that the image is
		1369	* indeed the same and that we should continue on into EEH
		1370	* anyway.
		1371	*/
		1372	if (adapter->perst_loads_image && !adapter->perst_same_image) {
		1373	/* TODO take the PHB out of CXL mode */
		1374	dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
		1375	return PCI_ERS_RESULT_NONE;
		1376	}
		1377
		1378	/*
		1379	* At this point, we want to try to recover. We'll always
		1380	* need a complete slot reset: we don't trust any other reset.
		1381	*
		1382	* Now, we go through each AFU:
		1383	* - We send the driver, if bound, an error_detected callback.
		1384	* We expect it to clean up, but it can also tell us to give
		1385	* up and permanently detach the card. To simplify things, if
		1386	* any bound AFU driver doesn't support EEH, we give up on EEH.
		1387	*
		1388	* - We detach all contexts associated with the AFU. This
		1389	* does not free them, but puts them into a CLOSED state
		1390	* which causes any the associated files to return useful
		1391	* errors to userland. It also unmaps, but does not free,
		1392	* any IRQs.
		1393	*
		1394	* - We clean up our side: releasing and unmapping resources we hold
		1395	* so we can wire them up again when the hardware comes back up.
		1396	*
		1397	* Driver authors should note:
		1398	*
		1399	* - Any contexts you create in your kernel driver (except
		1400	* those associated with anonymous file descriptors) are
		1401	* your responsibility to free and recreate. Likewise with
		1402	* any attached resources.
		1403	*
		1404	* - We will take responsibility for re-initialising the
		1405	* device context (the one set up for you in
		1406	* cxl_pci_enable_device_hook and accessed through
		1407	* cxl_get_context). If you've attached IRQs or other
		1408	* resources to it, they remains yours to free.
		1409	*
		1410	* You can call the same functions to release resources as you
		1411	* normally would: we make sure that these functions continue
		1412	* to work when the hardware is down.
		1413	*
		1414	* Two examples:
		1415	*
		1416	* 1) If you normally free all your resources at the end of
		1417	* each request, or if you use anonymous FDs, your
		1418	* error_detected callback can simply set a flag to tell
		1419	* your driver not to start any new calls. You can then
		1420	* clear the flag in the resume callback.
		1421	*
		1422	* 2) If you normally allocate your resources on startup:
		1423	* * Set a flag in error_detected as above.
		1424	* * Let CXL detach your contexts.
		1425	* * In slot_reset, free the old resources and allocate new ones.
		1426	* * In resume, clear the flag to allow things to start.
		1427	*/
		1428	for (i = 0; i < adapter->slices; i++) {
		1429	afu = adapter->afu[i];
		1430
		1431	result = cxl_vphb_error_detected(afu, state);
		1432
		1433	/* Only continue if everyone agrees on NEED_RESET */
		1434	if (result != PCI_ERS_RESULT_NEED_RESET)
		1435	return result;
		1436
		1437	cxl_context_detach_all(afu);
		1438	cxl_afu_deactivate_mode(afu);
		1439	cxl_deconfigure_afu(afu);
		1440	}
		1441	cxl_deconfigure_adapter(adapter);
		1442
		1443	return result;
		1444	}
		1445
		1446	static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
		1447	{
		1448	struct cxl *adapter = pci_get_drvdata(pdev);
		1449	struct cxl_afu *afu;
		1450	struct cxl_context *ctx;
		1451	struct pci_dev *afu_dev;
		1452	pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
		1453	pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
		1454	int i;
		1455
		1456	if (cxl_configure_adapter(adapter, pdev))
		1457	goto err;
		1458
		1459	for (i = 0; i < adapter->slices; i++) {
		1460	afu = adapter->afu[i];
		1461
		1462	if (cxl_configure_afu(afu, adapter, pdev))
		1463	goto err;
		1464
		1465	if (cxl_afu_select_best_mode(afu))
		1466	goto err;
		1467
		1468	cxl_pci_vphb_reconfigure(afu);
		1469
		1470	list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
		1471	/* Reset the device context.
		1472	* TODO: make this less disruptive
		1473	*/
		1474	ctx = cxl_get_context(afu_dev);
		1475
		1476	if (ctx && cxl_release_context(ctx))
		1477	goto err;
		1478
		1479	ctx = cxl_dev_context_init(afu_dev);
		1480	if (!ctx)
		1481	goto err;
		1482
		1483	afu_dev->dev.archdata.cxl_ctx = ctx;
		1484
		1485	if (cxl_afu_check_and_enable(afu))
		1486	goto err;
		1487
		1488	afu_dev->error_state = pci_channel_io_normal;
		1489
		1490	/* If there's a driver attached, allow it to
		1491	* chime in on recovery. Drivers should check
		1492	* if everything has come back OK, but
		1493	* shouldn't start new work until we call
		1494	* their resume function.
		1495	*/
		1496	if (!afu_dev->driver)
		1497	continue;
		1498
		1499	if (afu_dev->driver->err_handler &&
		1500	afu_dev->driver->err_handler->slot_reset)
		1501	afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
		1502
		1503	if (afu_result == PCI_ERS_RESULT_DISCONNECT)
		1504	result = PCI_ERS_RESULT_DISCONNECT;
		1505	}
		1506	}
		1507	return result;
		1508
		1509	err:
		1510	/* All the bits that happen in both error_detected and cxl_remove
		1511	* should be idempotent, so we don't need to worry about leaving a mix
		1512	* of unconfigured and reconfigured resources.
		1513	*/
		1514	dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
		1515	return PCI_ERS_RESULT_DISCONNECT;
		1516	}
		1517
		1518	static void cxl_pci_resume(struct pci_dev *pdev)
		1519	{
		1520	struct cxl *adapter = pci_get_drvdata(pdev);
		1521	struct cxl_afu *afu;
		1522	struct pci_dev *afu_dev;
		1523	int i;
		1524
		1525	/* Everything is back now. Drivers should restart work now.
		1526	* This is not the place to be checking if everything came back up
		1527	* properly, because there's no return value: do that in slot_reset.
		1528	*/
		1529	for (i = 0; i < adapter->slices; i++) {
		1530	afu = adapter->afu[i];
		1531
		1532	list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
		1533	if (afu_dev->driver && afu_dev->driver->err_handler &&
		1534	afu_dev->driver->err_handler->resume)
		1535	afu_dev->driver->err_handler->resume(afu_dev);
		1536	}
		1537	}
		1538	}
		1539
		1540	static const struct pci_error_handlers cxl_err_handler = {
		1541	.error_detected = cxl_pci_error_detected,
		1542	.slot_reset = cxl_pci_slot_reset,
		1543	.resume = cxl_pci_resume,
		1544	};
		1545
1186	struct pci_driver cxl_pci_driver = {	1546	struct pci_driver cxl_pci_driver = {
1187	.name = "cxl-pci",	1547	.name = "cxl-pci",
1188	.id_table = cxl_pci_tbl,	1548	.id_table = cxl_pci_tbl,
1189	.probe = cxl_probe,	1549	.probe = cxl_probe,
1190	.remove = cxl_remove,	1550	.remove = cxl_remove,
1191	.shutdown = cxl_remove,	1551	.shutdown = cxl_remove,
		1552	.err_handler = &cxl_err_handler,
1192	};	1553	};

drivers/misc/cxl/sysfs.c+26−0

@@ -112,12 +112,38 @@ static ssize_t load_image_on_perst_store(struct device *device, · 111 unmodified lines
112	return count;	112	return count;
113	}	113	}
114		114
		115	static ssize_t perst_reloads_same_image_show(struct device *device,
		116	struct device_attribute *attr,
		117	char *buf)
		118	{
		119	struct cxl *adapter = to_cxl_adapter(device);
		120
		121	return scnprintf(buf, PAGE_SIZE, "%i\n", adapter->perst_same_image);
		122	}
		123
		124	static ssize_t perst_reloads_same_image_store(struct device *device,
		125	struct device_attribute *attr,
		126	const char *buf, size_t count)
		127	{
		128	struct cxl *adapter = to_cxl_adapter(device);
		129	int rc;
		130	int val;
		131
		132	rc = sscanf(buf, "%i", &val);
		133	if ((rc != 1) \|\| !(val == 1 \|\| val == 0))
		134	return -EINVAL;
		135
		136	adapter->perst_same_image = (val == 1 ? true : false);
		137	return count;
		138	}
		139
115	static struct device_attribute adapter_attrs[] = {	140	static struct device_attribute adapter_attrs[] = {
116	__ATTR_RO(caia_version),	141	__ATTR_RO(caia_version),
117	__ATTR_RO(psl_revision),	142	__ATTR_RO(psl_revision),
118	__ATTR_RO(base_image),	143	__ATTR_RO(base_image),
119	__ATTR_RO(image_loaded),	144	__ATTR_RO(image_loaded),
120	__ATTR_RW(load_image_on_perst),	145	__ATTR_RW(load_image_on_perst),
		146	__ATTR_RW(perst_reloads_same_image),
121	__ATTR(reset, S_IWUSR, NULL, reset_adapter_store),	147	__ATTR(reset, S_IWUSR, NULL, reset_adapter_store),
122	};	148	};
123		149

drivers/misc/cxl/trace.h+5−5

@@ -105,7 +105,7 @@ TRACE_EVENT(cxl_attach, · 104 unmodified lines
105	__entry->num_interrupts = num_interrupts;	105	__entry->num_interrupts = num_interrupts;
106	),	106	),
107		107
108	TP_printk("afu%i.%i pid=%i pe=%i wed=0x%.16llx irqs=%i amr=0x%llx",	108	TP_printk("afu%i.%i pid=%i pe=%i wed=0x%016llx irqs=%i amr=0x%llx",
109	__entry->card,	109	__entry->card,
110	__entry->afu,	110	__entry->afu,
111	__entry->pid,	111	__entry->pid,
@@ -177,7 +177,7 @@ TRACE_EVENT(cxl_psl_irq, · 65 unmodified lines
177	__entry->dar = dar;	177	__entry->dar = dar;
178	),	178	),
179		179
180	TP_printk("afu%i.%i pe=%i irq=%i dsisr=%s dar=0x%.16llx",	180	TP_printk("afu%i.%i pe=%i irq=%i dsisr=%s dar=0x%016llx",
181	__entry->card,	181	__entry->card,
182	__entry->afu,	182	__entry->afu,
183	__entry->pe,	183	__entry->pe,
@@ -233,7 +233,7 @@ TRACE_EVENT(cxl_ste_miss, · 49 unmodified lines
233	__entry->dar = dar;	233	__entry->dar = dar;
234	),	234	),
235		235
236	TP_printk("afu%i.%i pe=%i dar=0x%.16llx",	236	TP_printk("afu%i.%i pe=%i dar=0x%016llx",
237	__entry->card,	237	__entry->card,
238	__entry->afu,	238	__entry->afu,
239	__entry->pe,	239	__entry->pe,
@@ -264,7 +264,7 @@ TRACE_EVENT(cxl_ste_write, · 24 unmodified lines
264	__entry->v = v;	264	__entry->v = v;
265	),	265	),
266		266
267	TP_printk("afu%i.%i pe=%i SSTE[%i] E=0x%.16llx V=0x%.16llx",	267	TP_printk("afu%i.%i pe=%i SSTE[%i] E=0x%016llx V=0x%016llx",
268	__entry->card,	268	__entry->card,
269	__entry->afu,	269	__entry->afu,
270	__entry->pe,	270	__entry->pe,
@@ -295,7 +295,7 @@ TRACE_EVENT(cxl_pte_miss, · 24 unmodified lines
295	__entry->dar = dar;	295	__entry->dar = dar;
296	),	296	),
297		297
298	TP_printk("afu%i.%i pe=%i dsisr=%s dar=0x%.16llx",	298	TP_printk("afu%i.%i pe=%i dsisr=%s dar=0x%016llx",
299	__entry->card,	299	__entry->card,
300	__entry->afu,	300	__entry->afu,
301	__entry->pe,	301	__entry->pe,

drivers/misc/cxl/vphb.c+34−0

@@ -138,6 +138,26 @@ static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn, · 137 unmodified lines
138	return 0;	138	return 0;
139	}	139	}
140		140
		141
		142	static inline bool cxl_config_link_ok(struct pci_bus *bus)
		143	{
		144	struct pci_controller *phb;
		145	struct cxl_afu *afu;
		146
		147	/* Config space IO is based on phb->cfg_addr, which is based on
		148	* afu_desc_mmio. This isn't safe to read/write when the link
		149	* goes down, as EEH tears down MMIO space.
		150	*
		151	* Check if the link is OK before proceeding.
		152	*/
		153
		154	phb = pci_bus_to_host(bus);
		155	if (phb == NULL)
		156	return false;
		157	afu = (struct cxl_afu *)phb->private_data;
		158	return cxl_adapter_link_ok(afu->adapter);
		159	}
		160
141	static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,	161	static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
142	int offset, int len, u32 *val)	162	int offset, int len, u32 *val)
143	{	163	{
@@ -150,6 +170,9 @@ static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn, · 6 unmodified lines
150	if (rc)	170	if (rc)
151	return rc;	171	return rc;
152		172
		173	if (!cxl_config_link_ok(bus))
		174	return PCIBIOS_DEVICE_NOT_FOUND;
		175
153	/* Can only read 32 bits */	176	/* Can only read 32 bits */
154	*val = (in_le32(ioaddr) >> shift) & mask;	177	*val = (in_le32(ioaddr) >> shift) & mask;
155	return PCIBIOS_SUCCESSFUL;	178	return PCIBIOS_SUCCESSFUL;
@@ -167,6 +190,9 @@ static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn, · 11 unmodified lines
167	if (rc)	190	if (rc)
168	return rc;	191	return rc;
169		192
		193	if (!cxl_config_link_ok(bus))
		194	return PCIBIOS_DEVICE_NOT_FOUND;
		195
170	/* Can only write 32 bits so do read-modify-write */	196	/* Can only write 32 bits so do read-modify-write */
171	mask <<= shift;	197	mask <<= shift;
172	val <<= shift;	198	val <<= shift;
@@ -240,6 +266,14 @@ int cxl_pci_vphb_add(struct cxl_afu *afu) · 67 unmodified lines
240	return 0;	266	return 0;
241	}	267	}
242		268
		269	void cxl_pci_vphb_reconfigure(struct cxl_afu *afu)
		270	{
		271	/* When we are reconfigured, the AFU's MMIO space is unmapped
		272	* and remapped. We need to reflect this in the PHB's view of
		273	* the world.
		274	*/
		275	afu->phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
		276	}
243		277
244	void cxl_pci_vphb_remove(struct cxl_afu *afu)	278	void cxl_pci_vphb_remove(struct cxl_afu *afu)
245	{	279	{

drivers/mtd/nand/fsl_ifc_nand.c+130−128

@@ -238,8 +238,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) · 237 unmodified lines
238		238
239	ifc_nand_ctrl->page = page_addr;	239	ifc_nand_ctrl->page = page_addr;
240	/* Program ROW0/COL0 */	240	/* Program ROW0/COL0 */
241	iowrite32be(page_addr, &ifc->ifc_nand.row0);	241	ifc_out32(page_addr, &ifc->ifc_nand.row0);
242	iowrite32be((oob ? IFC_NAND_COL_MS : 0) \| column, &ifc->ifc_nand.col0);	242	ifc_out32((oob ? IFC_NAND_COL_MS : 0) \| column, &ifc->ifc_nand.col0);
243		243
244	buf_num = page_addr & priv->bufnum_mask;	244	buf_num = page_addr & priv->bufnum_mask;
245		245
@@ -301,19 +301,19 @@ static void fsl_ifc_run_command(struct mtd_info *mtd) · 55 unmodified lines
301	int i;	301	int i;
302		302
303	/* set the chip select for NAND Transaction */	303	/* set the chip select for NAND Transaction */
304	iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,	304	ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
305	&ifc->ifc_nand.nand_csel);	305	&ifc->ifc_nand.nand_csel);
306		306
307	dev_vdbg(priv->dev,	307	dev_vdbg(priv->dev,
308	"%s: fir0=%08x fcr0=%08x\n",	308	"%s: fir0=%08x fcr0=%08x\n",
309	__func__,	309	__func__,
310	ioread32be(&ifc->ifc_nand.nand_fir0),	310	ifc_in32(&ifc->ifc_nand.nand_fir0),
311	ioread32be(&ifc->ifc_nand.nand_fcr0));	311	ifc_in32(&ifc->ifc_nand.nand_fcr0));
312		312
313	ctrl->nand_stat = 0;	313	ctrl->nand_stat = 0;
314		314
315	/* start read/write seq */	315	/* start read/write seq */
316	iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);	316	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
317		317
318	/* wait for command complete flag or timeout */	318	/* wait for command complete flag or timeout */
319	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,	319	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
@@ -336,7 +336,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd) · 16 unmodified lines
336	int sector_end = sector + chip->ecc.steps - 1;	336	int sector_end = sector + chip->ecc.steps - 1;
337		337
338	for (i = sector / 4; i <= sector_end / 4; i++)	338	for (i = sector / 4; i <= sector_end / 4; i++)
339	eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);	339	eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
340		340
341	for (i = sector; i <= sector_end; i++) {	341	for (i = sector; i <= sector_end; i++) {
342	errors = check_read_ecc(mtd, ctrl, eccstat, i);	342	errors = check_read_ecc(mtd, ctrl, eccstat, i);
@@ -376,33 +376,33 @@ static void fsl_ifc_do_read(struct nand_chip *chip, · 33 unmodified lines
376		376
377	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */	377	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
378	if (mtd->writesize > 512) {	378	if (mtd->writesize > 512) {
379	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	379	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
380	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|	380	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
381	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|	381	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
382	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|	382	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|
383	(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),	383	(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
384	&ifc->ifc_nand.nand_fir0);	384	&ifc->ifc_nand.nand_fir0);
385	iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);	385	ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
386		386
387	iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|	387	ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|
388	(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),	388	(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
389	&ifc->ifc_nand.nand_fcr0);	389	&ifc->ifc_nand.nand_fcr0);
390	} else {	390	} else {
391	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	391	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
392	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|	392	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
393	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|	393	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
394	(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),	394	(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
395	&ifc->ifc_nand.nand_fir0);	395	&ifc->ifc_nand.nand_fir0);
396	iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);	396	ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
397		397
398	if (oob)	398	if (oob)
399	iowrite32be(NAND_CMD_READOOB <<	399	ifc_out32(NAND_CMD_READOOB <<
400	IFC_NAND_FCR0_CMD0_SHIFT,	400	IFC_NAND_FCR0_CMD0_SHIFT,
401	&ifc->ifc_nand.nand_fcr0);	401	&ifc->ifc_nand.nand_fcr0);
402	else	402	else
403	iowrite32be(NAND_CMD_READ0 <<	403	ifc_out32(NAND_CMD_READ0 <<
404	IFC_NAND_FCR0_CMD0_SHIFT,	404	IFC_NAND_FCR0_CMD0_SHIFT,
405	&ifc->ifc_nand.nand_fcr0);	405	&ifc->ifc_nand.nand_fcr0);
406	}	406	}
407	}	407	}
408		408
@@ -422,7 +422,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 13 unmodified lines
422	switch (command) {	422	switch (command) {
423	/* READ0 read the entire buffer to use hardware ECC. */	423	/* READ0 read the entire buffer to use hardware ECC. */
424	case NAND_CMD_READ0:	424	case NAND_CMD_READ0:
425	iowrite32be(0, &ifc->ifc_nand.nand_fbcr);	425	ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
426	set_addr(mtd, 0, page_addr, 0);	426	set_addr(mtd, 0, page_addr, 0);
427		427
428	ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;	428	ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -437,7 +437,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 8 unmodified lines
437		437
438	/* READOOB reads only the OOB because no ECC is performed. */	438	/* READOOB reads only the OOB because no ECC is performed. */
439	case NAND_CMD_READOOB:	439	case NAND_CMD_READOOB:
440	iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);	440	ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
441	set_addr(mtd, column, page_addr, 1);	441	set_addr(mtd, column, page_addr, 1);
442		442
443	ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;	443	ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -453,19 +453,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 9 unmodified lines
453	if (command == NAND_CMD_PARAM)	453	if (command == NAND_CMD_PARAM)
454	timing = IFC_FIR_OP_RBCD;	454	timing = IFC_FIR_OP_RBCD;
455		455
456	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	456	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
457	(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|	457	(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
458	(timing << IFC_NAND_FIR0_OP2_SHIFT),	458	(timing << IFC_NAND_FIR0_OP2_SHIFT),
459	&ifc->ifc_nand.nand_fir0);	459	&ifc->ifc_nand.nand_fir0);
460	iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,	460	ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
461	&ifc->ifc_nand.nand_fcr0);	461	&ifc->ifc_nand.nand_fcr0);
462	iowrite32be(column, &ifc->ifc_nand.row3);	462	ifc_out32(column, &ifc->ifc_nand.row3);
463		463
464	/*	464	/*
465	* although currently it's 8 bytes for READID, we always read	465	* although currently it's 8 bytes for READID, we always read
466	* the maximum 256 bytes(for PARAM)	466	* the maximum 256 bytes(for PARAM)
467	*/	467	*/
468	iowrite32be(256, &ifc->ifc_nand.nand_fbcr);	468	ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
469	ifc_nand_ctrl->read_bytes = 256;	469	ifc_nand_ctrl->read_bytes = 256;
470		470
471	set_addr(mtd, 0, 0, 0);	471	set_addr(mtd, 0, 0, 0);
@@ -480,16 +480,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 8 unmodified lines
480		480
481	/* ERASE2 uses the block and page address from ERASE1 */	481	/* ERASE2 uses the block and page address from ERASE1 */
482	case NAND_CMD_ERASE2:	482	case NAND_CMD_ERASE2:
483	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	483	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
484	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) \|	484	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
485	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),	485	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
486	&ifc->ifc_nand.nand_fir0);	486	&ifc->ifc_nand.nand_fir0);
487		487
488	iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) \|	488	ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) \|
489	(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),	489	(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
490	&ifc->ifc_nand.nand_fcr0);	490	&ifc->ifc_nand.nand_fcr0);
491		491
492	iowrite32be(0, &ifc->ifc_nand.nand_fbcr);	492	ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
493	ifc_nand_ctrl->read_bytes = 0;	493	ifc_nand_ctrl->read_bytes = 0;
494	fsl_ifc_run_command(mtd);	494	fsl_ifc_run_command(mtd);
495	return;	495	return;
@@ -506,19 +506,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 10 unmodified lines
506	(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) \|	506	(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) \|
507	(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);	507	(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
508		508
509	iowrite32be(	509	ifc_out32(
510	(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	510	(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
511	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|	511	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
512	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|	512	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
513	(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) \|	513	(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) \|
514	(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),	514	(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
515	&ifc->ifc_nand.nand_fir0);	515	&ifc->ifc_nand.nand_fir0);
516	iowrite32be(	516	ifc_out32(
517	(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) \|	517	(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) \|
518	(IFC_FIR_OP_RDSTAT <<	518	(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) \|
519	IFC_NAND_FIR1_OP6_SHIFT) \|	519	(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
520	(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),	520	&ifc->ifc_nand.nand_fir1);
521	&ifc->ifc_nand.nand_fir1);
522	} else {	521	} else {
523	nand_fcr0 = ((NAND_CMD_PAGEPROG <<	522	nand_fcr0 = ((NAND_CMD_PAGEPROG <<
524	IFC_NAND_FCR0_CMD1_SHIFT) \|	523	IFC_NAND_FCR0_CMD1_SHIFT) \|
@@ -527,20 +526,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 2 unmodified lines
527	(NAND_CMD_STATUS <<	526	(NAND_CMD_STATUS <<
528	IFC_NAND_FCR0_CMD3_SHIFT));	527	IFC_NAND_FCR0_CMD3_SHIFT));
529		528
530	iowrite32be(	529	ifc_out32(
531	(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	530	(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
532	(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) \|	531	(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) \|
533	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) \|	532	(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
534	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) \|	533	(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) \|
535	(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),	534	(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
536	&ifc->ifc_nand.nand_fir0);	535	&ifc->ifc_nand.nand_fir0);
537	iowrite32be(	536	ifc_out32(
538	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) \|	537	(IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) \|
539	(IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) \|	538	(IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) \|
540	(IFC_FIR_OP_RDSTAT <<	539	(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) \|
541	IFC_NAND_FIR1_OP7_SHIFT) \|	540	(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
542	(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),	541	&ifc->ifc_nand.nand_fir1);
543	&ifc->ifc_nand.nand_fir1);
544		542
545	if (column >= mtd->writesize)	543	if (column >= mtd->writesize)
546	nand_fcr0 \|=	544	nand_fcr0 \|=
@@ -555,7 +553,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 8 unmodified lines
555	column -= mtd->writesize;	553	column -= mtd->writesize;
556	ifc_nand_ctrl->oob = 1;	554	ifc_nand_ctrl->oob = 1;
557	}	555	}
558	iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);	556	ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
559	set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);	557	set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
560	return;	558	return;
561	}	559	}
@@ -563,24 +561,26 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 1 unmodified line
563	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */	561	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
564	case NAND_CMD_PAGEPROG: {	562	case NAND_CMD_PAGEPROG: {
565	if (ifc_nand_ctrl->oob) {	563	if (ifc_nand_ctrl->oob) {
566	iowrite32be(ifc_nand_ctrl->index -	564	ifc_out32(ifc_nand_ctrl->index -
567	ifc_nand_ctrl->column,	565	ifc_nand_ctrl->column,
568	&ifc->ifc_nand.nand_fbcr);	566	&ifc->ifc_nand.nand_fbcr);
569	} else {	567	} else {
570	iowrite32be(0, &ifc->ifc_nand.nand_fbcr);	568	ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
571	}	569	}
572		570
573	fsl_ifc_run_command(mtd);	571	fsl_ifc_run_command(mtd);
574	return;	572	return;
575	}	573	}
576		574
577	case NAND_CMD_STATUS:	575	case NAND_CMD_STATUS: {
578	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	576	void __iomem *addr;
579	(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),	577
580	&ifc->ifc_nand.nand_fir0);	578	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
581	iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,	579	(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
582	&ifc->ifc_nand.nand_fcr0);	580	&ifc->ifc_nand.nand_fir0);
583	iowrite32be(1, &ifc->ifc_nand.nand_fbcr);	581	ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
		582	&ifc->ifc_nand.nand_fcr0);
		583	ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
584	set_addr(mtd, 0, 0, 0);	584	set_addr(mtd, 0, 0, 0);
585	ifc_nand_ctrl->read_bytes = 1;	585	ifc_nand_ctrl->read_bytes = 1;
586		586
@@ -590,17 +590,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, · 3 unmodified lines
590	* The chip always seems to report that it is	590	* The chip always seems to report that it is
591	* write-protected, even when it is not.	591	* write-protected, even when it is not.
592	*/	592	*/
		593	addr = ifc_nand_ctrl->addr;
593	if (chip->options & NAND_BUSWIDTH_16)	594	if (chip->options & NAND_BUSWIDTH_16)
594	setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP);	595	ifc_out16(ifc_in16(addr) \| (NAND_STATUS_WP), addr);
595	else	596	else
596	setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);	597	ifc_out8(ifc_in8(addr) \| (NAND_STATUS_WP), addr);
597	return;	598	return;
		599	}
598		600
599	case NAND_CMD_RESET:	601	case NAND_CMD_RESET:
600	iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,	602	ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
601	&ifc->ifc_nand.nand_fir0);	603	&ifc->ifc_nand.nand_fir0);
602	iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,	604	ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
603	&ifc->ifc_nand.nand_fcr0);	605	&ifc->ifc_nand.nand_fcr0);
604	fsl_ifc_run_command(mtd);	606	fsl_ifc_run_command(mtd);
605	return;	607	return;
606		608
@@ -658,7 +660,7 @@ static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) · 51 unmodified lines
658	*/	660	*/
659	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {	661	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
660	offset = ifc_nand_ctrl->index++;	662	offset = ifc_nand_ctrl->index++;
661	return in_8(ifc_nand_ctrl->addr + offset);	663	return ifc_in8(ifc_nand_ctrl->addr + offset);
662	}	664	}
663		665
664	dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);	666	dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
@@ -680,7 +682,7 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) · 15 unmodified lines
680	* next byte.	682	* next byte.
681	*/	683	*/
682	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {	684	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
683	data = in_be16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);	685	data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
684	ifc_nand_ctrl->index += 2;	686	ifc_nand_ctrl->index += 2;
685	return (uint8_t) data;	687	return (uint8_t) data;
686	}	688	}
@@ -726,18 +728,18 @@ static int fsl_ifc_wait(struct mtd_info mtd, struct nand_chip chip) · 39 unmodified lines
726	u32 nand_fsr;	728	u32 nand_fsr;
727		729
728	/* Use READ_STATUS command, but wait for the device to be ready */	730	/* Use READ_STATUS command, but wait for the device to be ready */
729	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	731	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
730	(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),	732	(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
731	&ifc->ifc_nand.nand_fir0);	733	&ifc->ifc_nand.nand_fir0);
732	iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,	734	ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
733	&ifc->ifc_nand.nand_fcr0);	735	&ifc->ifc_nand.nand_fcr0);
734	iowrite32be(1, &ifc->ifc_nand.nand_fbcr);	736	ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
735	set_addr(mtd, 0, 0, 0);	737	set_addr(mtd, 0, 0, 0);
736	ifc_nand_ctrl->read_bytes = 1;	738	ifc_nand_ctrl->read_bytes = 1;
737		739
738	fsl_ifc_run_command(mtd);	740	fsl_ifc_run_command(mtd);
739		741
740	nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);	742	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
741		743
742	/*	744	/*
743	* The chip always seems to report that it is	745	* The chip always seems to report that it is
@@ -829,34 +831,34 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) · 85 unmodified lines
829	uint32_t cs = priv->bank;	831	uint32_t cs = priv->bank;
830		832
831	/* Save CSOR and CSOR_ext */	833	/* Save CSOR and CSOR_ext */
832	csor = ioread32be(&ifc->csor_cs[cs].csor);	834	csor = ifc_in32(&ifc->csor_cs[cs].csor);
833	csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);	835	csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
834		836
835	/* chage PageSize 8K and SpareSize 1K*/	837	/* chage PageSize 8K and SpareSize 1K*/
836	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) \| 0x0018C000;	838	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) \| 0x0018C000;
837	iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);	839	ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
838	iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);	840	ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
839		841
840	/* READID */	842	/* READID */
841	iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|	843	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
842	(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|	844	(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
843	(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),	845	(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
844	&ifc->ifc_nand.nand_fir0);	846	&ifc->ifc_nand.nand_fir0);
845	iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,	847	ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
846	&ifc->ifc_nand.nand_fcr0);	848	&ifc->ifc_nand.nand_fcr0);
847	iowrite32be(0x0, &ifc->ifc_nand.row3);	849	ifc_out32(0x0, &ifc->ifc_nand.row3);
848		850
849	iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);	851	ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
850		852
851	/* Program ROW0/COL0 */	853	/* Program ROW0/COL0 */
852	iowrite32be(0x0, &ifc->ifc_nand.row0);	854	ifc_out32(0x0, &ifc->ifc_nand.row0);
853	iowrite32be(0x0, &ifc->ifc_nand.col0);	855	ifc_out32(0x0, &ifc->ifc_nand.col0);
854		856
855	/* set the chip select for NAND Transaction */	857	/* set the chip select for NAND Transaction */
856	iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);	858	ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
857		859
858	/* start read seq */	860	/* start read seq */
859	iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);	861	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
860		862
861	/* wait for command complete flag or timeout */	863	/* wait for command complete flag or timeout */
862	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,	864	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
@@ -866,8 +868,8 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) · 3 unmodified lines
866	printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");	868	printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
867		869
868	/* Restore CSOR and CSOR_ext */	870	/* Restore CSOR and CSOR_ext */
869	iowrite32be(csor, &ifc->csor_cs[cs].csor);	871	ifc_out32(csor, &ifc->csor_cs[cs].csor);
870	iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);	872	ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
871	}	873	}
872		874
873	static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)	875	static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
@@ -884,7 +886,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) · 10 unmodified lines
884		886
885	/* fill in nand_chip structure */	887	/* fill in nand_chip structure */
886	/* set up function call table */	888	/* set up function call table */
887	if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)	889	if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
888	chip->read_byte = fsl_ifc_read_byte16;	890	chip->read_byte = fsl_ifc_read_byte16;
889	else	891	else
890	chip->read_byte = fsl_ifc_read_byte;	892	chip->read_byte = fsl_ifc_read_byte;
@@ -898,13 +900,13 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) · 7 unmodified lines
898	chip->bbt_td = &bbt_main_descr;	900	chip->bbt_td = &bbt_main_descr;
899	chip->bbt_md = &bbt_mirror_descr;	901	chip->bbt_md = &bbt_mirror_descr;
900		902
901	iowrite32be(0x0, &ifc->ifc_nand.ncfgr);	903	ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
902		904
903	/* set up nand options */	905	/* set up nand options */
904	chip->bbt_options = NAND_BBT_USE_FLASH;	906	chip->bbt_options = NAND_BBT_USE_FLASH;
905	chip->options = NAND_NO_SUBPAGE_WRITE;	907	chip->options = NAND_NO_SUBPAGE_WRITE;
906		908
907	if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {	909	if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
908	chip->read_byte = fsl_ifc_read_byte16;	910	chip->read_byte = fsl_ifc_read_byte16;
909	chip->options \|= NAND_BUSWIDTH_16;	911	chip->options \|= NAND_BUSWIDTH_16;
910	} else {	912	} else {
@@ -917,7 +919,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) · 6 unmodified lines
917	chip->ecc.read_page = fsl_ifc_read_page;	919	chip->ecc.read_page = fsl_ifc_read_page;
918	chip->ecc.write_page = fsl_ifc_write_page;	920	chip->ecc.write_page = fsl_ifc_write_page;
919		921
920	csor = ioread32be(&ifc->csor_cs[priv->bank].csor);	922	csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
921		923
922	/* Hardware generates ECC per 512 Bytes */	924	/* Hardware generates ECC per 512 Bytes */
923	chip->ecc.size = 512;	925	chip->ecc.size = 512;
@@ -1006,7 +1008,7 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) · 82 unmodified lines
1006	static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,	1008	static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1007	phys_addr_t addr)	1009	phys_addr_t addr)
1008	{	1010	{
1009	u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);	1011	u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
1010		1012
1011	if (!(cspr & CSPR_V))	1013	if (!(cspr & CSPR_V))
1012	return 0;	1014	return 0;
@@ -1092,16 +1094,16 @@ static int fsl_ifc_nand_probe(struct platform_device *dev) · 79 unmodified lines
1092		1094
1093	dev_set_drvdata(priv->dev, priv);	1095	dev_set_drvdata(priv->dev, priv);
1094		1096
1095	iowrite32be(IFC_NAND_EVTER_EN_OPC_EN \|	1097	ifc_out32(IFC_NAND_EVTER_EN_OPC_EN \|
1096	IFC_NAND_EVTER_EN_FTOER_EN \|	1098	IFC_NAND_EVTER_EN_FTOER_EN \|
1097	IFC_NAND_EVTER_EN_WPER_EN,	1099	IFC_NAND_EVTER_EN_WPER_EN,
1098	&ifc->ifc_nand.nand_evter_en);	1100	&ifc->ifc_nand.nand_evter_en);
1099		1101
1100	/* enable NAND Machine Interrupts */	1102	/* enable NAND Machine Interrupts */
1101	iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN \|	1103	ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN \|
1102	IFC_NAND_EVTER_INTR_FTOERIR_EN \|	1104	IFC_NAND_EVTER_INTR_FTOERIR_EN \|
1103	IFC_NAND_EVTER_INTR_WPERIR_EN,	1105	IFC_NAND_EVTER_INTR_WPERIR_EN,
1104	&ifc->ifc_nand.nand_evter_intr_en);	1106	&ifc->ifc_nand.nand_evter_intr_en);
1105	priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);	1107	priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1106	if (!priv->mtd.name) {	1108	if (!priv->mtd.name) {
1107	ret = -ENOMEM;	1109	ret = -ENOMEM;

drivers/tty/hvc/hvsi.c+24−22

 {
 	struct hvsi_control *header = (struct hvsi_control *)packet;
-	switch (header->verb) {
+	switch (be16_to_cpu(header->verb)) {
 		case VSV_MODEM_CTL_UPDATE:
-			if ((header->word & HVSI_TSCD) == 0) {
+			if ((be32_to_cpu(header->word) & HVSI_TSCD) == 0) {
 				/* CD went away; no more connection */
 				pr_debug("hvsi%i: CD dropped\n", hp->index);
 				hp->mctrl &= TIOCM_CD;
 static void hvsi_recv_response(struct hvsi_struct *hp, uint8_t *packet)
 {
 	struct hvsi_query_response *resp = (struct hvsi_query_response *)packet;
+	uint32_t mctrl_word;
 	switch (hp->state) {
 		case HVSI_WAIT_FOR_VER_RESPONSE:
 			break;
 		case HVSI_WAIT_FOR_MCTRL_RESPONSE:
 			hp->mctrl = 0;
-			if (resp->u.mctrl_word & HVSI_TSDTR)
+			mctrl_word = be32_to_cpu(resp->u.mctrl_word);
+			if (mctrl_word & HVSI_TSDTR)
 				hp->mctrl |= TIOCM_DTR;
-			if (resp->u.mctrl_word & HVSI_TSCD)
+			if (mctrl_word & HVSI_TSCD)
 				hp->mctrl |= TIOCM_CD;
 			__set_state(hp, HVSI_OPEN);
 			break;
 	packet.hdr.type = VS_QUERY_RESPONSE_PACKET_HEADER;
 	packet.hdr.len = sizeof(struct hvsi_query_response);
-	packet.hdr.seqno = atomic_inc_return(&hp->seqno);
+	packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
-	packet.verb = VSV_SEND_VERSION_NUMBER;
+	packet.verb = cpu_to_be16(VSV_SEND_VERSION_NUMBER);
 	packet.u.version = HVSI_VERSION;
-	packet.query_seqno = query_seqno+1;
+	packet.query_seqno = cpu_to_be16(query_seqno+1);
 	pr_debug("%s: sending %i bytes\n", __func__, packet.hdr.len);
 	dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);
 	switch (hp->state) {
 		case HVSI_WAIT_FOR_VER_QUERY:
-			hvsi_version_respond(hp, query->hdr.seqno);
+			hvsi_version_respond(hp, be16_to_cpu(query->hdr.seqno));
 			__set_state(hp, HVSI_OPEN);
 			break;
 		default:
 	packet.hdr.type = VS_QUERY_PACKET_HEADER;
 	packet.hdr.len = sizeof(struct hvsi_query);
-	packet.hdr.seqno = atomic_inc_return(&hp->seqno);
+	packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
-	packet.verb = verb;
+	packet.verb = cpu_to_be16(verb);
 	pr_debug("%s: sending %i bytes\n", __func__, packet.hdr.len);
 	dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);
 	struct hvsi_control packet __ALIGNED__;
 	int wrote;
-	packet.hdr.type = VS_CONTROL_PACKET_HEADER,
+	packet.hdr.type = VS_CONTROL_PACKET_HEADER;
-	packet.hdr.seqno = atomic_inc_return(&hp->seqno);
+	packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
 	packet.hdr.len = sizeof(struct hvsi_control);
-	packet.verb = VSV_SET_MODEM_CTL;
+	packet.verb = cpu_to_be16(VSV_SET_MODEM_CTL);
-	packet.mask = HVSI_TSDTR;
+	packet.mask = cpu_to_be32(HVSI_TSDTR);
 	if (mctrl & TIOCM_DTR)
-		packet.word = HVSI_TSDTR;
+		packet.word = cpu_to_be32(HVSI_TSDTR);
 	pr_debug("%s: sending %i bytes\n", __func__, packet.hdr.len);
 	dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);
 	BUG_ON(count > HVSI_MAX_OUTGOING_DATA);
 	packet.hdr.type = VS_DATA_PACKET_HEADER;
-	packet.hdr.seqno = atomic_inc_return(&hp->seqno);
+	packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
 	packet.hdr.len = count + sizeof(struct hvsi_header);
 	memcpy(&packet.data, buf, count);
 	struct hvsi_control packet __ALIGNED__;
 	packet.hdr.type = VS_CONTROL_PACKET_HEADER;
-	packet.hdr.seqno = atomic_inc_return(&hp->seqno);
+	packet.hdr.seqno = cpu_to_be16(atomic_inc_return(&hp->seqno));
 	packet.hdr.len = 6;
-	packet.verb = VSV_CLOSE_PROTOCOL;
+	packet.verb = cpu_to_be16(VSV_CLOSE_PROTOCOL);
 	pr_debug("%s: sending %i bytes\n", __func__, packet.hdr.len);
 	dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);
 	/* search device tree for vty nodes */
 	for_each_compatible_node(vty, "serial", "hvterm-protocol") {
 		struct hvsi_struct *hp;
-		const uint32_t *vtermno, *irq;
+		const __be32 *vtermno, *irq;
 		vtermno = of_get_property(vty, "reg", NULL);
 		irq = of_get_property(vty, "interrupts", NULL);
 		hp->index = hvsi_count;
 		hp->inbuf_end = hp->inbuf;
 		hp->state = HVSI_CLOSED;
-		hp->vtermno = *vtermno;
+		hp->vtermno = be32_to_cpup(vtermno);
-		hp->virq = irq_create_mapping(NULL, irq[0]);
+		hp->virq = irq_create_mapping(NULL, be32_to_cpup(irq));
 		if (hp->virq == 0) {
 			printk(KERN_ERR "%s: couldn't create irq mapping for 0x%x\n",
-				__func__, irq[0]);
+			       __func__, be32_to_cpup(irq));
 			tty_port_destroy(&hp->port);
 			continue;
 		}

include/linux/fsl_ifc.h+50−0

@@ -841,9 +841,59 @@ struct fsl_ifc_ctrl { · 840 unmodified lines
841		841
842	u32 nand_stat;	842	u32 nand_stat;
843	wait_queue_head_t nand_wait;	843	wait_queue_head_t nand_wait;
		844	bool little_endian;
844	};	845	};
845		846
846	extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;	847	extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
847		848
		849	static inline u32 ifc_in32(void __iomem *addr)
		850	{
		851	u32 val;
		852
		853	if (fsl_ifc_ctrl_dev->little_endian)
		854	val = ioread32(addr);
		855	else
		856	val = ioread32be(addr);
		857
		858	return val;
		859	}
		860
		861	static inline u16 ifc_in16(void __iomem *addr)
		862	{
		863	u16 val;
		864
		865	if (fsl_ifc_ctrl_dev->little_endian)
		866	val = ioread16(addr);
		867	else
		868	val = ioread16be(addr);
		869
		870	return val;
		871	}
		872
		873	static inline u8 ifc_in8(void __iomem *addr)
		874	{
		875	return ioread8(addr);
		876	}
		877
		878	static inline void ifc_out32(u32 val, void __iomem *addr)
		879	{
		880	if (fsl_ifc_ctrl_dev->little_endian)
		881	iowrite32(val, addr);
		882	else
		883	iowrite32be(val, addr);
		884	}
		885
		886	static inline void ifc_out16(u16 val, void __iomem *addr)
		887	{
		888	if (fsl_ifc_ctrl_dev->little_endian)
		889	iowrite16(val, addr);
		890	else
		891	iowrite16be(val, addr);
		892	}
		893
		894	static inline void ifc_out8(u8 val, void __iomem *addr)
		895	{
		896	iowrite8(val, addr);
		897	}
848		898
849	#endif /* __ASM_FSL_IFC_H */	899	#endif /* __ASM_FSL_IFC_H */

include/misc/cxl.h+10−0

@@ -200,4 +200,14 @@ unsigned int cxl_fd_poll(struct file file, struct poll_table_struct poll); · 199 unmodified lines
200	ssize_t cxl_fd_read(struct file file, char __user buf, size_t count,	200	ssize_t cxl_fd_read(struct file file, char __user buf, size_t count,
201	loff_t *off);	201	loff_t *off);
202		202
		203	/*
		204	* For EEH, a driver may want to assert a PERST will reload the same image
		205	* from flash into the FPGA.
		206	*
		207	* This is a property of the entire adapter, not a single AFU, so drivers
		208	* should set this property with care!
		209	*/
		210	void cxl_perst_reloads_same_image(struct cxl_afu *afu,
		211	bool perst_reloads_same_image);
		212
203	#endif /* _MISC_CXL_H */	213	#endif /* _MISC_CXL_H */

include/uapi/misc/cxl.h+3−1

@@ -29,8 +29,10 @@ struct cxl_ioctl_start_work { · 28 unmodified lines
29		29
30	#define CXL_START_WORK_AMR 0x0000000000000001ULL	30	#define CXL_START_WORK_AMR 0x0000000000000001ULL
31	#define CXL_START_WORK_NUM_IRQS 0x0000000000000002ULL	31	#define CXL_START_WORK_NUM_IRQS 0x0000000000000002ULL
		32	#define CXL_START_WORK_ERR_FF 0x0000000000000004ULL
32	#define CXL_START_WORK_ALL (CXL_START_WORK_AMR \|\	33	#define CXL_START_WORK_ALL (CXL_START_WORK_AMR \|\
33	CXL_START_WORK_NUM_IRQS)	34	CXL_START_WORK_NUM_IRQS \|\
		35	CXL_START_WORK_ERR_FF)
34		36
35		37
36	/* Possible modes that an afu can be in */	38	/* Possible modes that an afu can be in */

tools/testing/selftests/powerpc/mm/Makefile+2−1

@@ -2,8 +2,9 @@ noarg: · 1 unmodified line
2	$(MAKE) -C ../	2	$(MAKE) -C ../
3		3
4	TEST_PROGS := hugetlb_vs_thp_test subpage_prot	4	TEST_PROGS := hugetlb_vs_thp_test subpage_prot
		5	TEST_FILES := tempfile
5		6
6	all: $(TEST_PROGS) tempfile	7	all: $(TEST_PROGS) $(TEST_FILES)
7		8
8	$(TEST_PROGS): ../harness.c	9	$(TEST_PROGS): ../harness.c
9		10

tools/testing/selftests/seccomp/seccomp_bpf.c+14−1

 #include <linux/filter.h>
 #include <sys/prctl.h>
 #include <sys/ptrace.h>
+#include <sys/types.h>
 #include <sys/user.h>
 #include <linux/prctl.h>
 #include <linux/ptrace.h>
 };
 #endif
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 #define syscall_arg(_n) (offsetof(struct seccomp_data, args[_n]))
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define syscall_arg(_n) (offsetof(struct seccomp_data, args[_n]) + sizeof(__u32))
+#else
+#error "wut? Unknown __BYTE_ORDER?!"
+#endif
 #define SIBLING_EXIT_UNKILLED	0xbadbeef
 #define SIBLING_EXIT_FAILURE	0xbadface
 # define ARCH_REGS	struct user_pt_regs
 # define SYSCALL_NUM	regs[8]
 # define SYSCALL_RET	regs[0]
+#elif defined(__powerpc__)
+# define ARCH_REGS	struct pt_regs
+# define SYSCALL_NUM	gpr[0]
+# define SYSCALL_RET	gpr[3]
 #else
 # error "Do not know how to find your architecture's registers and syscalls"
 #endif
 	ret = ptrace(PTRACE_GETREGSET, tracee, NT_PRSTATUS, &iov);
 	EXPECT_EQ(0, ret);
-#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__)
+#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__) || defined(__powerpc__)
 	{
 		regs.SYSCALL_NUM = syscall;
 	}
 #  define __NR_seccomp 383
 # elif defined(__aarch64__)
 #  define __NR_seccomp 277
+# elif defined(__powerpc__)
+#  define __NR_seccomp 358
 # else
 #  warning "seccomp syscall number unknown for this architecture"
 #  define __NR_seccomp 0xffff