History

Merge tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "No core changes this time. Just new driver code and improvements! New drivers: - New driver for the Broadcom BCM4908 SoC. - New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative of the Samsung Exynos pin control driver. - New driver for the Amlogic Meson S4 SoC. - New driver for the Sunplus SP7021 SoC. - New driver for the Microsemi Ocelot family ServalT SoC. - New subdriver for Intel Alder Lake-M SoC. - New subdriver for Intel Ice Lake-N SoC, including PCH support. - New subdriver for Renesas R8A779F0 SoC. - New subdriver for Mediatek MT8186 SoC. - New subdriver for NXP Freescale i.MX93 SoC. - New driver for Nuvoton WPCM450 SoC. - New driver for Qualcomm SC8280XP SoC. Improvements: - Wakeup support on Samsung Exynos850 and ExynosAutov9. - Serious and voluminous maintenance cleanup and refactoring in the Renesas drivers. Mainly sharing similar data between the different SoC subdrivers. - Qualcomm SM8450 EGPIO support. - Drive strength support on the Mediatek MT8195. - Add some missing groups and functions to the Ralink RT2880" * tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits) pinctrl: mediatek: common-v1: fix semicolon.cocci warnings pinctrl: nuvoton: wpcm450: Fix build error without OF pinctrl: qcom-pmic-gpio: Add support for pm8450 dt-bindings: pinctrl: aspeed: Update gfx node in example dt-bindings: pinctrl: rt2880: add missing pin groups and functions pinctrl: ingenic: Fix regmap on X series SoCs pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register() pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register() pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS pinctrl: nuvoton: Fix sparse warning pinctrl: mediatek: mt8186: Account for probe refactoring pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback pinctrl: mediatek: common-v1: Commonize spec_pupd callback pinctrl: mediatek: common-v1: Use common probe function pinctrl: mediatek: common-v1: Add common probe function pinctrl: mediatek: paris: Unify probe function by using OF match data pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe pinctrl: berlin: fix error return code of berlin_pinctrl_build_state() pinctrl: qcom: Introduce sc8280xp TLMM driver ...

Linus Torvalds committed 4 years ago

Commit ff61bc82 parents 901c728 4a6d014135 files · +19104 −3941Browse files

Unified · Split

135 files
  1. Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +16 −0
  2. Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +1 −1
  3. Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml +72 −0
  4. Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml +85 −0
  5. Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +1 −0
  6. Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +1 −1
  7. Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +2 −2
  8. Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml +160 −0
  9. Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +297 −0
  10. Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +51 −14
  11. Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +2 −0
  12. Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +1 −0
  13. Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +1 −0
  14. Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml +151 −0
  15. Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +0 −1
  16. Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +6 −5
  17. Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +1 −0
  18. Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +12 −4
  19. Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +1 −0
  20. Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml +374 −0
  21. MAINTAINERS +19 −0
  22. drivers/pinctrl/Kconfig +1 −0
  23. drivers/pinctrl/Makefile +2 −1
  24. drivers/pinctrl/bcm/Kconfig +14 −0
  25. drivers/pinctrl/bcm/Makefile +1 −0
  26. drivers/pinctrl/bcm/pinctrl-bcm4908.c +563 −0
  27. drivers/pinctrl/berlin/berlin.c +2 −0
  28. drivers/pinctrl/freescale/Kconfig +7 −0
  29. drivers/pinctrl/freescale/Makefile +1 −0
  30. drivers/pinctrl/freescale/pinctrl-imx.c +1 −1
  31. drivers/pinctrl/freescale/pinctrl-imx93.c +272 −0
  32. drivers/pinctrl/intel/pinctrl-alderlake.c +316 −1
  33. drivers/pinctrl/intel/pinctrl-baytrail.c +53 −2
  34. drivers/pinctrl/intel/pinctrl-icelake.c +283 −8
  35. drivers/pinctrl/mediatek/Kconfig +7 −0
  36. drivers/pinctrl/mediatek/Makefile +1 −0
  37. drivers/pinctrl/mediatek/pinctrl-moore.c +9 −16
  38. drivers/pinctrl/mediatek/pinctrl-mt2701.c +11 −29
  39. drivers/pinctrl/mediatek/pinctrl-mt2712.c +10 −34
  40. drivers/pinctrl/mediatek/pinctrl-mt6765.c +2 −7
  41. drivers/pinctrl/mediatek/pinctrl-mt6779.c +2 −7
  42. drivers/pinctrl/mediatek/pinctrl-mt6797.c +2 −7
  43. drivers/pinctrl/mediatek/pinctrl-mt8127.c +10 −29
  44. drivers/pinctrl/mediatek/pinctrl-mt8135.c +6 −11
  45. drivers/pinctrl/mediatek/pinctrl-mt8167.c +10 −30
  46. drivers/pinctrl/mediatek/pinctrl-mt8173.c +8 −21
  47. drivers/pinctrl/mediatek/pinctrl-mt8183.c +2 −7
  48. drivers/pinctrl/mediatek/pinctrl-mt8186.c +1267 −0
  49. drivers/pinctrl/mediatek/pinctrl-mt8192.c +2 −7
  50. drivers/pinctrl/mediatek/pinctrl-mt8195.c +2 −7
  51. drivers/pinctrl/mediatek/pinctrl-mt8365.c +10 −30
  52. drivers/pinctrl/mediatek/pinctrl-mt8516.c +10 −30
  53. drivers/pinctrl/mediatek/pinctrl-mtk-common.c +59 −29
  54. drivers/pinctrl/mediatek/pinctrl-mtk-common.h +24 −9
  55. drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h +2186 −0
  56. drivers/pinctrl/mediatek/pinctrl-paris.c +184 −117
  57. drivers/pinctrl/mediatek/pinctrl-paris.h +1 −2
  58. drivers/pinctrl/meson/Kconfig +6 −0
  59. drivers/pinctrl/meson/Makefile +1 −0
  60. drivers/pinctrl/meson/pinctrl-meson-g12a.c +5 −1
  61. drivers/pinctrl/meson/pinctrl-meson-s4.c +1232 −0
  62. drivers/pinctrl/nomadik/pinctrl-nomadik.c +3 −1
  63. drivers/pinctrl/nuvoton/Kconfig +20 −0
  64. drivers/pinctrl/nuvoton/Makefile +1 −0
  65. drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +84 −84
  66. drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +1151 −0
  67. drivers/pinctrl/pinconf-generic.c +3 −3
  68. drivers/pinctrl/pinctrl-at91-pio4.c +7 −9
  69. drivers/pinctrl/pinctrl-ingenic.c +45 −1
  70. drivers/pinctrl/pinctrl-microchip-sgpio.c +97 −15
  71. drivers/pinctrl/pinctrl-ocelot.c +106 −3
  72. drivers/pinctrl/pinctrl-rockchip.c +2 −0
  73. drivers/pinctrl/pinctrl-starfive.c +1 −1
  74. drivers/pinctrl/pinctrl-zynq.c +2 −5
  75. drivers/pinctrl/pxa/pinctrl-pxa27x.c +2 −3
  76. drivers/pinctrl/qcom/Kconfig +9 −0
  77. drivers/pinctrl/qcom/Makefile +1 −0
  78. drivers/pinctrl/qcom/pinctrl-msm.c +11 −2
  79. drivers/pinctrl/qcom/pinctrl-qcm2290.c +12 −0
  80. drivers/pinctrl/qcom/pinctrl-sc8180x.c +2 −2
  81. drivers/pinctrl/qcom/pinctrl-sc8280xp.c +1953 −0
  82. drivers/pinctrl/qcom/pinctrl-sm6125.c +1 −1
  83. drivers/pinctrl/qcom/pinctrl-sm8450.c +61 −45
  84. drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +1 −0
  85. drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +1 −0
  86. drivers/pinctrl/renesas/Kconfig +9 −2
  87. drivers/pinctrl/renesas/Makefile +1 −0
  88. drivers/pinctrl/renesas/core.c +199 −20
  89. drivers/pinctrl/renesas/pfc-emev2.c +17 −54
  90. drivers/pinctrl/renesas/pfc-r8a73a4.c +24 −73
  91. drivers/pinctrl/renesas/pfc-r8a7740.c +48 −234
  92. drivers/pinctrl/renesas/pfc-r8a77470.c +82 −158
  93. drivers/pinctrl/renesas/pfc-r8a7778.c +25 −44
  94. drivers/pinctrl/renesas/pfc-r8a7779.c +30 −88
  95. drivers/pinctrl/renesas/pfc-r8a7790.c +208 −322
  96. drivers/pinctrl/renesas/pfc-r8a7791.c +126 −196
  97. drivers/pinctrl/renesas/pfc-r8a7792.c +202 −244
  98. drivers/pinctrl/renesas/pfc-r8a7794.c +83 −131
  99. drivers/pinctrl/renesas/pfc-r8a77950.c +29 −90
  100. drivers/pinctrl/renesas/pfc-r8a77951.c +108 −205
  101. drivers/pinctrl/renesas/pfc-r8a7796.c +109 −206
  102. drivers/pinctrl/renesas/pfc-r8a77965.c +110 −223
  103. drivers/pinctrl/renesas/pfc-r8a77970.c +51 −114
  104. drivers/pinctrl/renesas/pfc-r8a77980.c +65 −128
  105. drivers/pinctrl/renesas/pfc-r8a77990.c +129 −204
  106. drivers/pinctrl/renesas/pfc-r8a77995.c +97 −103
  107. drivers/pinctrl/renesas/pfc-r8a779a0.c +37 −68
  108. drivers/pinctrl/renesas/pfc-r8a779f0.c +2126 −0
  109. drivers/pinctrl/renesas/pfc-sh7203.c +0 −1
  110. drivers/pinctrl/renesas/pfc-sh7264.c +0 −1
  111. drivers/pinctrl/renesas/pfc-sh7269.c +0 −1
  112. drivers/pinctrl/renesas/pfc-sh73a0.c +46 −223
  113. drivers/pinctrl/renesas/pfc-sh7720.c +0 −1
  114. drivers/pinctrl/renesas/pfc-sh7722.c +0 −1
  115. drivers/pinctrl/renesas/pinctrl-rzg2l.c +2 −2
  116. drivers/pinctrl/renesas/pinctrl.c +14 −12
  117. drivers/pinctrl/renesas/sh_pfc.h +79 −97
  118. drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +71 −0
  119. drivers/pinctrl/samsung/pinctrl-exynos.c +2 −1
  120. drivers/pinctrl/samsung/pinctrl-samsung.c +2 −0
  121. drivers/pinctrl/samsung/pinctrl-samsung.h +1 −0
  122. drivers/pinctrl/sunplus/Kconfig +22 −0
  123. drivers/pinctrl/sunplus/Makefile +6 −0
  124. drivers/pinctrl/sunplus/sppctl.c +1118 −0
  125. drivers/pinctrl/sunplus/sppctl.h +170 −0
  126. drivers/pinctrl/sunplus/sppctl_sp7021.c +583 −0
  127. drivers/pinctrl/sunxi/pinctrl-sunxi.c +4 −5
  128. drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +20 −6
  129. drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +50 −14
  130. drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +53 −9
  131. drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +48 −14
  132. include/dt-bindings/gpio/meson-s4-gpio.h +99 −0
  133. include/dt-bindings/pinctrl/mt8186-pinfunc.h +1174 −0
  134. include/dt-bindings/pinctrl/sppctl-sp7021.h +179 −0
  135. include/dt-bindings/pinctrl/sppctl.h +31 −0
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+16−0
@@ -75,6 +75,7 @@ additionalProperties: false · 74 unmodified lines
7575
7676 examples:
7777 - |
78+ #include <dt-bindings/clock/aspeed-clock.h>
7879 apb {
7980 compatible = "simple-bus";
8081 #address-cells = <1>;
@@ -84,6 +85,8 @@ examples: · 3 unmodified lines
8485 syscon: scu@1e6e2000 {
8586 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
8687 reg = <0x1e6e2000 0x1a8>;
88+ #clock-cells = <1>;
89+ #reset-cells = <1>;
8790
8891 pinctrl: pinctrl {
8992 compatible = "aspeed,ast2500-pinctrl";
@@ -104,6 +107,12 @@ examples: · 14 unmodified lines
104107 gfx: display@1e6e6000 {
105108 compatible = "aspeed,ast2500-gfx", "syscon";
106109 reg = <0x1e6e6000 0x1000>;
110+ reg-io-width = <4>;
111+ clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
112+ resets = <&syscon ASPEED_RESET_CRT1>;
113+ interrupts = <0x19>;
114+ syscon = <&syscon>;
115+ memory-region = <&gfx_memory>;
107116 };
108117 };
109118
@@ -130,3 +139,10 @@ examples: · 20 unmodified lines
130139 };
131140 };
132141 };
142+
143+ gfx_memory: framebuffer {
144+ size = <0x01000000>;
145+ alignment = <0x01000000>;
146+ compatible = "shared-dma-pool";
147+ reusable;
148+ };
Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt+1−1
@@ -85,7 +85,7 @@ Optional Properties (for I2C pins): · 84 unmodified lines
8585 - function: String. Specifies the pin mux selection. Values
8686 must be one of: "alt1", "alt2", "alt3", "alt4"
8787 - bias-pull-up: Integer. Pull up strength in Ohm. There are 3
88− pull-up resisitors (1.2k, 1.8k, 2.7k) available
88+ pull-up resistors (1.2k, 1.8k, 2.7k) available
8989 in parallel for I2C pins, so the valid values
9090 are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
9191 - bias-disable: No arguments. Disable pin bias.
Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml+72−0
@@ -0,0 +1,72 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Broadcom BCM4908 pin controller
8+
9+maintainers:
10+ - Rafał Miłecki <rafal@milecki.pl>
11+
12+description:
13+ Binding for pin controller present on BCM4908 family SoCs.
14+
15+properties:
16+ compatible:
17+ const: brcm,bcm4908-pinctrl
18+
19+ reg:
20+ maxItems: 1
21+
22+patternProperties:
23+ '-pins$':
24+ type: object
25+ $ref: pinmux-node.yaml#
26+
27+ properties:
28+ function:
29+ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
30+ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
31+ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
32+ led_25, led_26, led_27, led_28, led_29, led_30, led_31,
33+ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
34+ usb1_pwr ]
35+
36+ groups:
37+ minItems: 1
38+ maxItems: 2
39+ items:
40+ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
41+ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
42+ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
43+ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
44+ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
45+ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
46+ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
47+ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
48+ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
49+ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
50+ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
51+ usb1_pwr_grp ]
52+
53+allOf:
54+ - $ref: pinctrl.yaml#
55+
56+required:
57+ - compatible
58+ - reg
59+
60+unevaluatedProperties: false
61+
62+examples:
63+ - |
64+ pinctrl@ff800560 {
65+ compatible = "brcm,bcm4908-pinctrl";
66+ reg = <0xff800560 0x10>;
67+
68+ led_0-a-pins {
69+ function = "led_0";
70+ groups = "led_0_grp_a";
71+ };
72+ };
Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml+85−0
@@ -0,0 +1,85 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Freescale IMX93 IOMUX Controller
8+
9+maintainers:
10+ - Peng Fan <peng.fan@nxp.com>
11+
12+description:
13+ Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14+ for common binding part and usage.
15+
16+allOf:
17+ - $ref: "pinctrl.yaml#"
18+
19+properties:
20+ compatible:
21+ const: fsl,imx93-iomuxc
22+
23+ reg:
24+ maxItems: 1
25+
26+# Client device subnode's properties
27+patternProperties:
28+ 'grp$':
29+ type: object
30+ description:
31+ Pinctrl node's client devices use subnodes for desired pin configuration.
32+ Client device subnodes use below standard properties.
33+
34+ properties:
35+ fsl,pins:
36+ description:
37+ each entry consists of 6 integers and represents the mux and config
38+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
39+ mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
40+ be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
41+ integer CONFIG is the pad setting value like pull-up on this pin. Please
42+ refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
43+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
44+ items:
45+ items:
46+ - description: |
47+ "mux_reg" indicates the offset of mux register.
48+ - description: |
49+ "conf_reg" indicates the offset of pad configuration register.
50+ - description: |
51+ "input_reg" indicates the offset of select input register.
52+ - description: |
53+ "mux_val" indicates the mux value to be applied.
54+ - description: |
55+ "input_val" indicates the select input value to be applied.
56+ - description: |
57+ "pad_setting" indicates the pad configuration value to be applied.
58+
59+
60+ required:
61+ - fsl,pins
62+
63+ additionalProperties: false
64+
65+required:
66+ - compatible
67+ - reg
68+
69+additionalProperties: false
70+
71+examples:
72+ # Pinmux controller node
73+ - |
74+ iomuxc: pinctrl@443c0000 {
75+ compatible = "fsl,imx93-iomuxc";
76+ reg = <0x30330000 0x10000>;
77+
78+ pinctrl_uart3: uart3grp {
79+ fsl,pins =
80+ <0x48 0x1f8 0x41c 0x1 0x0 0x49>,
81+ <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
82+ };
83+ };
84+
85+...
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt+1−0
@@ -16,6 +16,7 @@ Required properties for the root node: · 15 unmodified lines
1616 "amlogic,meson-g12a-periphs-pinctrl"
1717 "amlogic,meson-g12a-aobus-pinctrl"
1818 "amlogic,meson-a1-periphs-pinctrl"
19+ "amlogic,meson-s4-periphs-pinctrl"
1920 - reg: address and size of registers controlling irq functionality
2021
2122 === GPIO sub-nodes ===
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml+1−1
@@ -145,7 +145,7 @@ examples: · 144 unmodified lines
145145 clocks = <&sys_clk>;
146146 pinctrl-0 = <&sgpio2_pins>;
147147 pinctrl-names = "default";
148− reg = <0x1101059c 0x100>;
148+ reg = <0x1101059c 0x118>;
149149 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
150150 bus-frequency = <25000000>;
151151 sgpio_in2: gpio@0 {
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt+2−2
@@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings · 3 unmodified lines
44 Required properties:
55 - compatible : Should be "mscc,ocelot-pinctrl",
66 "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
7− "mscc,luton-pinctrl", "mscc,serval-pinctrl" or
8− "microchip,lan966x-pinctrl"
7+ "mscc,luton-pinctrl", "mscc,serval-pinctrl",
8+ "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
99 - reg : Address and length of the register set for the device
1010 - gpio-controller : Indicates this device is a GPIO controller
1111 - #gpio-cells : Must be 2.
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml+160−0
@@ -0,0 +1,160 @@
1+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Nuvoton WPCM450 pin control and GPIO
8+
9+maintainers:
10+ - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11+
12+properties:
13+ compatible:
14+ const: nuvoton,wpcm450-pinctrl
15+
16+ reg:
17+ maxItems: 1
18+
19+ '#address-cells':
20+ const: 1
21+
22+ '#size-cells':
23+ const: 0
24+
25+patternProperties:
26+ # There are three kinds of subnodes:
27+ # 1. a GPIO controller node for each GPIO bank
28+ # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
29+ # 3. a pinconf node configures properties of a single pin
30+
31+ "^gpio@[0-7]$":
32+ type: object
33+
34+ description:
35+ Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
36+ GPIOs. Some GPIOs support interrupts.
37+
38+ properties:
39+ reg:
40+ minimum: 0
41+ maximum: 7
42+
43+ gpio-controller: true
44+
45+ "#gpio-cells":
46+ const: 2
47+
48+ interrupt-controller: true
49+
50+ "#interrupt-cells":
51+ const: 2
52+
53+ interrupts:
54+ maxItems: 3
55+ description:
56+ The interrupts associated with this GPIO bank
57+
58+ required:
59+ - reg
60+ - gpio-controller
61+ - '#gpio-cells'
62+
63+ "^mux-":
64+ $ref: pinmux-node.yaml#
65+
66+ properties:
67+ groups:
68+ description:
69+ One or more groups of pins to mux to a certain function
70+ items:
71+ enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
72+ hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
73+ clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
74+ fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
75+ fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
76+ pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
77+ function:
78+ description:
79+ The function that a group of pins is muxed to
80+ enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
81+ hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
82+ dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
83+ gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
84+ fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
85+ pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
86+ hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
87+
88+ dependencies:
89+ groups: [ function ]
90+ function: [ groups ]
91+
92+ additionalProperties: false
93+
94+ "^cfg-":
95+ $ref: pincfg-node.yaml#
96+
97+ properties:
98+ pins:
99+ description:
100+ A list of pins to configure in certain ways, such as enabling
101+ debouncing
102+ items:
103+ pattern: "^gpio1?[0-9]{1,2}$"
104+
105+ input-debounce: true
106+
107+ additionalProperties: false
108+
109+required:
110+ - compatible
111+ - reg
112+
113+additionalProperties: false
114+
115+examples:
116+ - |
117+ #include <dt-bindings/interrupt-controller/irq.h>
118+ #include <dt-bindings/gpio/gpio.h>
119+ pinctrl: pinctrl@b8003000 {
120+ compatible = "nuvoton,wpcm450-pinctrl";
121+ reg = <0xb8003000 0x1000>;
122+ #address-cells = <1>;
123+ #size-cells = <0>;
124+
125+ gpio0: gpio@0 {
126+ reg = <0>;
127+ gpio-controller;
128+ #gpio-cells = <2>;
129+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
130+ <3 IRQ_TYPE_LEVEL_HIGH>,
131+ <4 IRQ_TYPE_LEVEL_HIGH>;
132+ };
133+
134+ mux-rmii2 {
135+ groups = "rmii2";
136+ function = "rmii2";
137+ };
138+
139+ pinmux_uid: mux-uid {
140+ groups = "gspi", "sspi";
141+ function = "gpio";
142+ };
143+
144+ pinctrl_uid: cfg-uid {
145+ pins = "gpio14";
146+ input-debounce = <1>;
147+ };
148+ };
149+
150+ gpio-keys {
151+ compatible = "gpio-keys";
152+ pinctrl-names = "default";
153+ pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
154+
155+ uid {
156+ label = "UID";
157+ linux,code = <102>;
158+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
159+ };
160+ };
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml+297−0
@@ -0,0 +1,297 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Mediatek MT8186 Pin Controller
8+
9+maintainers:
10+ - Sean Wang <sean.wang@mediatek.com>
11+
12+description: |
13+ The Mediatek's Pin controller is used to control SoC pins.
14+
15+properties:
16+ compatible:
17+ const: mediatek,mt8186-pinctrl
18+
19+ gpio-controller: true
20+
21+ '#gpio-cells':
22+ description: |
23+ Number of cells in GPIO specifier. Since the generic GPIO binding is used,
24+ the amount of cells must be specified as 2. See the below
25+ mentioned gpio binding representation for description of particular cells.
26+ const: 2
27+
28+ gpio-ranges:
29+ maxItems: 1
30+
31+ reg:
32+ description: |
33+ Physical address base for gpio base registers. There are 8 different GPIO
34+ physical address base in mt8186.
35+ maxItems: 8
36+
37+ reg-names:
38+ description: |
39+ Gpio base register names.
40+ items:
41+ - const: iocfg0
42+ - const: iocfg_bm
43+ - const: iocfg_bl
44+ - const: iocfg_br
45+ - const: iocfg_lm
46+ - const: iocfg_rb
47+ - const: iocfg_tl
48+ - const: eint
49+
50+ interrupt-controller: true
51+
52+ '#interrupt-cells':
53+ const: 2
54+
55+ interrupts:
56+ description: The interrupt outputs to sysirq
57+ maxItems: 1
58+
59+ mediatek,rsel-resistance-in-si-unit:
60+ type: boolean
61+ description: |
62+ Identifying i2c pins pull up/down type which is RSEL. It can support
63+ RSEL define or si unit value(ohm) to set different resistance.
64+
65+# PIN CONFIGURATION NODES
66+patternProperties:
67+ '-pins$':
68+ type: object
69+ additionalProperties: false
70+ patternProperties:
71+ '^pins':
72+ type: object
73+ additionalProperties: false
74+ description: |
75+ A pinctrl node should contain at least one subnodes representing the
76+ pinctrl groups available on the machine. Each subnode will list the
77+ pins it needs, and how they should be configured, with regard to muxer
78+ configuration, pullups, drive strength, input enable/disable and
79+ input schmitt.
80+ An example of using macro:
81+ pincontroller {
82+ /* GPIO0 set as multifunction GPIO0 */
83+ gpio-pins {
84+ pins {
85+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
86+ }
87+ };
88+ /* GPIO128 set as multifunction SDA0 */
89+ i2c0-pins {
90+ pins {
91+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
92+ }
93+ };
94+ };
95+ $ref: "pinmux-node.yaml"
96+
97+ properties:
98+ pinmux:
99+ description: |
100+ Integer array, represents gpio pin number and mux setting.
101+ Supported pin number and mux varies for different SoCs, and are
102+ defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
103+ directly.
104+
105+ drive-strength:
106+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
107+
108+ mediatek,drive-strength-adv:
109+ description: |
110+ Describe the specific driving setup property.
111+ For I2C pins, the existing generic driving setup can only support
112+ 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
113+ can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
114+ driving setup, the existing generic setup will be disabled.
115+ The specific driving setup is controlled by E1E0EN.
116+ When E1=0/E0=0, the strength is 0.125mA.
117+ When E1=0/E0=1, the strength is 0.25mA.
118+ When E1=1/E0=0, the strength is 0.5mA.
119+ When E1=1/E0=1, the strength is 1mA.
120+ EN is used to enable or disable the specific driving setup.
121+ Valid arguments are described as below:
122+ 0: (E1, E0, EN) = (0, 0, 0)
123+ 1: (E1, E0, EN) = (0, 0, 1)
124+ 2: (E1, E0, EN) = (0, 1, 0)
125+ 3: (E1, E0, EN) = (0, 1, 1)
126+ 4: (E1, E0, EN) = (1, 0, 0)
127+ 5: (E1, E0, EN) = (1, 0, 1)
128+ 6: (E1, E0, EN) = (1, 1, 0)
129+ 7: (E1, E0, EN) = (1, 1, 1)
130+ So the valid arguments are from 0 to 7.
131+ $ref: /schemas/types.yaml#/definitions/uint32
132+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
133+
134+ bias-pull-down:
135+ oneOf:
136+ - type: boolean
137+ - enum: [100, 101, 102, 103]
138+ description: mt8186 pull down PUPD/R0/R1 type define value.
139+ - enum: [200, 201, 202, 203]
140+ description: mt8186 pull down RSEL type define value.
141+ - enum: [75000, 5000]
142+ description: mt8186 pull down RSEL type si unit value(ohm).
143+ description: |
144+ For pull down type is normal, it don't need add RSEL & R1R0 define
145+ and resistance value.
146+ For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
147+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
148+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
149+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
150+ For pull down type is RSEL, it can add RSEL define & resistance
151+ value(ohm) to set different resistance by identifying property
152+ "mediatek,rsel-resistance-in-si-unit".
153+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
154+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
155+ define in mt8186. It can also support resistance value(ohm)
156+ "75000" & "5000" in mt8186.
157+ An example of using RSEL define:
158+ pincontroller {
159+ i2c0_pin {
160+ pins {
161+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
162+ bias-pull-down = <MTK_PULL_SET_RSEL_001>;
163+ }
164+ };
165+ };
166+ An example of using si unit resistance value(ohm):
167+ &pio {
168+ mediatek,rsel-resistance-in-si-unit;
169+ }
170+ pincontroller {
171+ i2c0_pin {
172+ pins {
173+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
174+ bias-pull-down = <75000>;
175+ }
176+ };
177+ };
178+
179+ bias-pull-up:
180+ oneOf:
181+ - type: boolean
182+ - enum: [100, 101, 102, 103]
183+ description: mt8186 pull up PUPD/R0/R1 type define value.
184+ - enum: [200, 201, 202, 203]
185+ description: mt8186 pull up RSEL type define value.
186+ - enum: [1000, 5000, 10000, 75000]
187+ description: mt8186 pull up RSEL type si unit value(ohm).
188+ description: |
189+ For pull up type is normal, it don't need add RSEL & R1R0 define
190+ and resistance value.
191+ For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
192+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
193+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
194+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
195+ For pull up type is RSEL, it can add RSEL define & resistance
196+ value(ohm) to set different resistance by identifying property
197+ "mediatek,rsel-resistance-in-si-unit".
198+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
199+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
200+ define in mt8186. It can also support resistance value(ohm)
201+ "1000" & "5000" & "10000" & "75000" in mt8186.
202+ An example of using si unit resistance value(ohm):
203+ &pio {
204+ mediatek,rsel-resistance-in-si-unit;
205+ }
206+ pincontroller {
207+ i2c0-pins {
208+ pins {
209+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
210+ bias-pull-up = <1000>;
211+ }
212+ };
213+ };
214+
215+ bias-disable: true
216+
217+ output-high: true
218+
219+ output-low: true
220+
221+ input-enable: true
222+
223+ input-disable: true
224+
225+ input-schmitt-enable: true
226+
227+ input-schmitt-disable: true
228+
229+ required:
230+ - pinmux
231+
232+required:
233+ - compatible
234+ - reg
235+ - interrupts
236+ - interrupt-controller
237+ - '#interrupt-cells'
238+ - gpio-controller
239+ - '#gpio-cells'
240+ - gpio-ranges
241+
242+additionalProperties: false
243+
244+examples:
245+ - |
246+ #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
247+ #include <dt-bindings/interrupt-controller/arm-gic.h>
248+
249+ pio: pinctrl@10005000 {
250+ compatible = "mediatek,mt8186-pinctrl";
251+ reg = <0x10005000 0x1000>,
252+ <0x10002000 0x0200>,
253+ <0x10002200 0x0200>,
254+ <0x10002400 0x0200>,
255+ <0x10002600 0x0200>,
256+ <0x10002A00 0x0200>,
257+ <0x10002c00 0x0200>,
258+ <0x1000b000 0x1000>;
259+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
260+ "iocfg_br", "iocfg_lm", "iocfg_rb",
261+ "iocfg_tl", "eint";
262+ gpio-controller;
263+ #gpio-cells = <2>;
264+ gpio-ranges = <&pio 0 0 185>;
265+ interrupt-controller;
266+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
267+ #interrupt-cells = <2>;
268+
269+ pio-pins {
270+ pins {
271+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
272+ output-low;
273+ };
274+ };
275+
276+ spi0-pins {
277+ pins-spi {
278+ pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
279+ <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
280+ <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
281+ bias-disable;
282+ };
283+ pins-spi-mi {
284+ pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
285+ bias-pull-down;
286+ };
287+ };
288+
289+ i2c0-pins {
290+ pins {
291+ pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
292+ <PINMUX_GPIO128__FUNC_SDA0>;
293+ bias-pull-up = <MTK_PULL_SET_RSEL_001>;
294+ mediatek,drive-strength-adv = <7>;
295+ };
296+ };
297+ };
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml+51−14
@@ -98,7 +98,41 @@ patternProperties: · 97 unmodified lines
9898 drive-strength:
9999 enum: [2, 4, 6, 8, 10, 12, 14, 16]
100100
101+ mediatek,drive-strength-adv:
102+ description: |
103+ Describe the specific driving setup property.
104+ For I2C pins, the existing generic driving setup can only support
105+ 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
106+ can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
107+ driving setup, the existing generic setup will be disabled.
108+ The specific driving setup is controlled by E1E0EN.
109+ When E1=0/E0=0, the strength is 0.125mA.
110+ When E1=0/E0=1, the strength is 0.25mA.
111+ When E1=1/E0=0, the strength is 0.5mA.
112+ When E1=1/E0=1, the strength is 1mA.
113+ EN is used to enable or disable the specific driving setup.
114+ Valid arguments are described as below:
115+ 0: (E1, E0, EN) = (0, 0, 0)
116+ 1: (E1, E0, EN) = (0, 0, 1)
117+ 2: (E1, E0, EN) = (0, 1, 0)
118+ 3: (E1, E0, EN) = (0, 1, 1)
119+ 4: (E1, E0, EN) = (1, 0, 0)
120+ 5: (E1, E0, EN) = (1, 0, 1)
121+ 6: (E1, E0, EN) = (1, 1, 0)
122+ 7: (E1, E0, EN) = (1, 1, 1)
123+ So the valid arguments are from 0 to 7.
124+ $ref: /schemas/types.yaml#/definitions/uint32
125+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
126+
101127 bias-pull-down:
128+ oneOf:
129+ - type: boolean
130+ - enum: [100, 101, 102, 103]
131+ description: mt8195 pull down PUPD/R0/R1 type define value.
132+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
133+ description: mt8195 pull down RSEL type define value.
134+ - enum: [75000, 5000]
135+ description: mt8195 pull down RSEL type si unit value(ohm).
102136 description: |
103137 For pull down type is normal, it don't need add RSEL & R1R0 define
104138 and resistance value.
@@ -115,13 +149,6 @@ patternProperties: · 10 unmodified lines
115149 & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
116150 define in mt8195. It can also support resistance value(ohm)
117151 "75000" & "5000" in mt8195.
118− oneOf:
119− - enum: [100, 101, 102, 103]
120− - description: mt8195 pull down PUPD/R0/R1 type define value.
121− - enum: [200, 201, 202, 203, 204, 205, 206, 207]
122− - description: mt8195 pull down RSEL type define value.
123− - enum: [75000, 5000]
124− - description: mt8195 pull down RSEL type si unit value(ohm).
125152
126153 An example of using RSEL define:
127154 pincontroller {
@@ -146,6 +173,14 @@ patternProperties: · 18 unmodified lines
146173 };
147174
148175 bias-pull-up:
176+ oneOf:
177+ - type: boolean
178+ - enum: [100, 101, 102, 103]
179+ description: mt8195 pull up PUPD/R0/R1 type define value.
180+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
181+ description: mt8195 pull up RSEL type define value.
182+ - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
183+ description: mt8195 pull up RSEL type si unit value(ohm).
149184 description: |
150185 For pull up type is normal, it don't need add RSEL & R1R0 define
151186 and resistance value.
@@ -163,13 +198,6 @@ patternProperties: · 11 unmodified lines
163198 define in mt8195. It can also support resistance value(ohm)
164199 "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
165200 "75000" in mt8195.
166− oneOf:
167− - enum: [100, 101, 102, 103]
168− - description: mt8195 pull up PUPD/R0/R1 type define value.
169− - enum: [200, 201, 202, 203, 204, 205, 206, 207]
170− - description: mt8195 pull up RSEL type define value.
171− - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
172− - description: mt8195 pull up RSEL type si unit value(ohm).
173201 An example of using RSEL define:
174202 pincontroller {
175203 i2c0-pins {
@@ -268,4 +296,13 @@ examples: · 92 unmodified lines
268296 bias-pull-down;
269297 };
270298 };
299+
300+ i2c0-pins {
301+ pins {
302+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
303+ <PINMUX_GPIO9__FUNC_SCL0>;
304+ bias-disable;
305+ mediatek,drive-strength-adv = <7>;
306+ };
307+ };
271308 };
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml+2−0
@@ -34,6 +34,8 @@ properties: · 33 unmodified lines
3434
3535 gpio-controller: true
3636
37+ gpio-reserved-ranges: true
38+
3739 '#gpio-cells':
3840 description: Specifying the pin number and flags, as defined in
3941 include/dt-bindings/gpio/gpio.h
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml+1−0
@@ -36,6 +36,7 @@ properties: · 35 unmodified lines
3636 - qcom,pm8350-gpio
3737 - qcom,pm8350b-gpio
3838 - qcom,pm8350c-gpio
39+ - qcom,pm8450-gpio
3940 - qcom,pm8916-gpio
4041 - qcom,pm8917-gpio
4142 - qcom,pm8921-gpio
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml+1−0
@@ -21,6 +21,7 @@ properties: · 20 unmodified lines
2121 - qcom,pm8019-mpp
2222 - qcom,pm8038-mpp
2323 - qcom,pm8058-mpp
24+ - qcom,pm8226-mpp
2425 - qcom,pm8821-mpp
2526 - qcom,pm8841-mpp
2627 - qcom,pm8916-mpp
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml+151−0
@@ -0,0 +1,151 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Technologies, Inc. SC8280XP TLMM block
8+
9+maintainers:
10+ - Bjorn Andersson <bjorn.andersson@linaro.org>
11+
12+description: |
13+ This binding describes the Top Level Mode Multiplexer block found in the
14+ SC8280XP platform.
15+
16+allOf:
17+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18+
19+properties:
20+ compatible:
21+ const: qcom,sc8280xp-tlmm
22+
23+ reg:
24+ maxItems: 1
25+
26+ interrupts: true
27+ interrupt-controller: true
28+ '#interrupt-cells': true
29+ gpio-controller: true
30+ gpio-reserved-ranges: true
31+ '#gpio-cells': true
32+ gpio-ranges: true
33+ wakeup-parent: true
34+
35+required:
36+ - compatible
37+ - reg
38+
39+additionalProperties: false
40+
41+patternProperties:
42+ '-state$':
43+ oneOf:
44+ - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
45+ - patternProperties:
46+ ".*":
47+ $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
48+
49+'$defs':
50+ qcom-sc8280xp-tlmm-state:
51+ type: object
52+ description:
53+ Pinctrl node's client devices use subnodes for desired pin configuration.
54+ Client device subnodes use below standard properties.
55+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
56+
57+ properties:
58+ pins:
59+ description:
60+ List of gpio pins affected by the properties specified in this
61+ subnode.
62+ items:
63+ oneOf:
64+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
65+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
66+ minItems: 1
67+ maxItems: 16
68+
69+ function:
70+ description:
71+ Specify the alternative function to be configured for the specified
72+ pins.
73+
74+ enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
75+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
76+ cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
77+ cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
78+ ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
79+ ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
80+ edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
81+ emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
82+ emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
83+ emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
84+ gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
85+ jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
86+ mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
87+ mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
88+ mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
89+ mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
90+ mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
91+ mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
92+ mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
93+ pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
94+ phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
95+ prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
96+ qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
97+ qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
98+ qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
99+ sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
100+ tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
101+ usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
102+ usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
103+ vsense_trigger ]
104+
105+ bias-disable: true
106+ bias-pull-down: true
107+ bias-pull-up: true
108+ drive-strength: true
109+ input-enable: true
110+ output-high: true
111+ output-low: true
112+
113+ required:
114+ - pins
115+ - function
116+
117+ additionalProperties: false
118+
119+examples:
120+ - |
121+ #include <dt-bindings/interrupt-controller/arm-gic.h>
122+ pinctrl@f100000 {
123+ compatible = "qcom,sc8280xp-tlmm";
124+ reg = <0x0f100000 0x300000>;
125+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126+ gpio-controller;
127+ #gpio-cells = <2>;
128+ interrupt-controller;
129+ #interrupt-cells = <2>;
130+ gpio-ranges = <&tlmm 0 0 230>;
131+
132+ gpio-wo-subnode-state {
133+ pins = "gpio1";
134+ function = "gpio";
135+ };
136+
137+ uart-w-subnodes-state {
138+ rx {
139+ pins = "gpio4";
140+ function = "qup14";
141+ bias-pull-up;
142+ };
143+
144+ tx {
145+ pins = "gpio5";
146+ function = "qup14";
147+ bias-disable;
148+ };
149+ };
150+ };
151+...
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml+0−1
@@ -73,7 +73,6 @@ $defs: · 72 unmodified lines
7373 properties:
7474 drive-strength:
7575 enum: [2, 4, 6, 8, 10, 12, 14, 16]
76− default: 2
7776 description:
7877 Selects the drive strength for the specified pins, in mA.
7978
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml+6−5
@@ -10,7 +10,7 @@ maintainers: · 9 unmodified lines
1010 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
1111
1212 description:
13− The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
13+ The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
1414 is not supported. There is no pinconf support.
1515
1616 properties:
@@ -29,12 +29,13 @@ patternProperties: · 12 unmodified lines
2929 properties:
3030 groups:
3131 description: Name of the pin group to use for the functions.
32− enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
33− pcie, sdhci]
32+ enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
33+ uart1, uart2, uart3, wdt]
3434 function:
3535 description: The mux function to select
36− enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
37− mdio, nand1, nand2, sdhci]
36+ enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
37+ pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
38+ spi, uart1, uart2, uart3, wdt refclk, wdt rst]
3839
3940 required:
4041 - groups
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml+1−0
@@ -44,6 +44,7 @@ properties: · 43 unmodified lines
4444 - renesas,pfc-r8a77990 # R-Car E3
4545 - renesas,pfc-r8a77995 # R-Car D3
4646 - renesas,pfc-r8a779a0 # R-Car V3U
47+ - renesas,pfc-r8a779f0 # R-Car S4-8
4748 - renesas,pfc-sh73a0 # SH-Mobile AG5
4849
4950 reg:
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml+12−4
@@ -4,14 +4,14 @@ · 3 unmodified lines
44 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
55 $schema: http://devicetree.org/meta-schemas/core.yaml#
66
7−title: Renesas RZ/G2L combined Pin and GPIO controller
7+title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
88
99 maintainers:
1010 - Geert Uytterhoeven <geert+renesas@glider.be>
1111 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
1212
1313 description:
14− The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
14+ The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
1515 controller.
1616 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
1717 Each port features up to 8 pins, each of them configurable for GPIO function
@@ -20,8 +20,15 @@ description: · 2 unmodified lines
2020
2121 properties:
2222 compatible:
23− enum:
24− - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
23+ oneOf:
24+ - items:
25+ - enum:
26+ - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
27+
28+ - items:
29+ - enum:
30+ - renesas,r9a07g054-pinctrl # RZ/V2L
31+ - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
2532
2633 reg:
2734 maxItems: 1
@@ -76,6 +83,7 @@ additionalProperties: · 48 unmodified lines
7683 output-impedance-ohms:
7784 enum: [ 33, 50, 66, 100 ]
7885 power-source:
86+ description: I/O voltage in millivolt.
7987 enum: [ 1800, 2500, 3300 ]
8088 slew-rate: true
8189 gpio-hog: true
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml+1−0
@@ -56,6 +56,7 @@ properties: · 55 unmodified lines
5656 - samsung,exynos7885-pinctrl
5757 - samsung,exynos850-pinctrl
5858 - samsung,exynosautov9-pinctrl
59+ - tesla,fsd-pinctrl
5960
6061 interrupts:
6162 description:
Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml+374−0
@@ -0,0 +1,374 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+# Copyright (C) Sunplus Co., Ltd.
3+%YAML 1.2
4+---
5+$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6+$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+title: Sunplus SP7021 Pin Controller Device Tree Bindings
9+
10+maintainers:
11+ - Dvorkin Dmitry <dvorkin@tibbo.com>
12+ - Wells Lu <wellslutw@gmail.com>
13+
14+description: |
15+ The Sunplus SP7021 pin controller is used to control SoC pins. Please
16+ refer to pinctrl-bindings.txt in this directory for details of the common
17+ pinctrl bindings used by client devices.
18+
19+ SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20+ are multiplexed with some special function pins. SP7021 has 3 types of
21+ special function pins:
22+
23+ (1) function-group pins:
24+ Ex 1 (SPI-NOR flash):
25+ If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
26+ will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
27+ and 81 will be pins of SPI-NOR flash.
28+
29+ Ex 2 (UART_0):
30+ If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
31+ RX pins of UART_0 (UART channel 0).
32+
33+ Ex 3 (eMMC):
34+ If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
35+ 78, 79, 80, 81 will be pins of an eMMC device.
36+
37+ Properties "function" and "groups" are used to select function-group
38+ pins.
39+
40+ (2) fully pin-mux (like phone exchange mux) pins:
41+ GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
42+ SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
43+ can be routed to any pins of fully pin-mux pins.
44+
45+ Ex 1 (UART channel 1):
46+ If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
47+ routed to GPIO 10 (3 - 1 + 8 = 10).
48+ If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
49+ routed to GPIO 11 (4 - 1 + 8 = 11).
50+ If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
51+ be routed to GPIO 12 (5 - 1 + 8 = 12).
52+ If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
53+ be routed to GPIO 13 (6 - 1 + 8 = 13).
54+
55+ Ex 2 (I2C channel 0):
56+ If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
57+ be routed to GPIO 27 (20 - 1 + 8 = 27).
58+ If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
59+ will be routed to GPIO 28 (21 - 1 + 9 = 28).
60+
61+ Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
62+ routed to any of 64 'fully pin-mux' pins.
63+
64+ (3) I/O processor pins
65+ SP7021 has a built-in I/O processor.
66+ Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.
67+
68+ Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
69+ "I/O processor pins" and "digital GPIO" pins.
70+
71+ The device node of pin controller of Sunplus SP7021 has following
72+ properties.
73+
74+properties:
75+ compatible:
76+ const: sunplus,sp7021-pctl
77+
78+ gpio-controller: true
79+
80+ '#gpio-cells':
81+ const: 2
82+
83+ reg:
84+ items:
85+ - description: the MOON2 registers
86+ - description: the GPIOXT registers
87+ - description: the FIRST registers
88+ - description: the MOON1 registers
89+
90+ reg-names:
91+ items:
92+ - const: moon2
93+ - const: gpioxt
94+ - const: first
95+ - const: moon1
96+
97+ clocks:
98+ maxItems: 1
99+
100+ resets:
101+ maxItems: 1
102+
103+patternProperties:
104+ '-pins$':
105+ type: object
106+ description: |
107+ A pinctrl node should contain at least one subnodes representing the
108+ pins or function-pins group available on the machine. Each subnode
109+ will list the pins it needs, and how they should be configured.
110+
111+ Pinctrl node's client devices use subnodes for desired pin
112+ configuration. Client device subnodes use below standard properties.
113+ $ref: pinmux-node.yaml#
114+
115+ properties:
116+ sunplus,pins:
117+ description: |
118+ Define 'sunplus,pins' which are used by pinctrl node's client
119+ device.
120+
121+ It consists of one or more integers which represents the config
122+ setting for corresponding pin. Each integer defines a individual
123+ pin in which:
124+
125+ Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
126+ Bit 23~16: defines types: (1) fully pin-mux pins
127+ (2) IO processor pins
128+ (3) digital GPIO pins
129+ Bit 15~8: defines pins of peripherals (which are defined in
130+ 'include/dt-binging/pinctrl/sppctl.h').
131+ Bit 7~0: defines types or initial-state of digital GPIO pins.
132+
133+ Please use macro SPPCTL_IOPAD to define the integers for pins.
134+
135+ $ref: /schemas/types.yaml#/definitions/uint32-array
136+
137+ function:
138+ description: |
139+ Define pin-function which is used by pinctrl node's client device.
140+ The name should be one of string in the following enumeration.
141+ $ref: "/schemas/types.yaml#/definitions/string"
142+ enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
143+ UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]
144+
145+ groups:
146+ description: |
147+ Define pin-group in a specified pin-function.
148+ The name should be one of string in the following enumeration.
149+ $ref: "/schemas/types.yaml#/definitions/string"
150+ enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
151+ SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
152+ HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]
153+
154+ sunplus,zerofunc:
155+ description: |
156+ This is a vendor specific property. It is used to disable pins
157+ which are not used by pinctrl node's client device.
158+ Some pins may be enabled by boot-loader. We can use this
159+ property to disable them.
160+ $ref: /schemas/types.yaml#/definitions/uint32-array
161+
162+ additionalProperties: false
163+
164+ allOf:
165+ - if:
166+ properties:
167+ function:
168+ enum:
169+ - SPI_FLASH
170+ then:
171+ properties:
172+ groups:
173+ enum:
174+ - SPI_FLASH1
175+ - SPI_FLASH2
176+ - if:
177+ properties:
178+ function:
179+ enum:
180+ - SPI_FLASH_4BIT
181+ then:
182+ properties:
183+ groups:
184+ enum:
185+ - SPI_FLASH_4BIT1
186+ - SPI_FLASH_4BIT2
187+ - if:
188+ properties:
189+ function:
190+ enum:
191+ - SPI_NAND
192+ then:
193+ properties:
194+ groups:
195+ enum:
196+ - SPI_NAND
197+ - if:
198+ properties:
199+ function:
200+ enum:
201+ - CARD0_EMMC
202+ then:
203+ properties:
204+ groups:
205+ enum:
206+ - CARD0_EMMC
207+ - if:
208+ properties:
209+ function:
210+ enum:
211+ - SD_CARD
212+ then:
213+ properties:
214+ groups:
215+ enum:
216+ - SD_CARD
217+ - if:
218+ properties:
219+ function:
220+ enum:
221+ - UA0
222+ then:
223+ properties:
224+ groups:
225+ enum:
226+ - UA0
227+ - if:
228+ properties:
229+ function:
230+ enum:
231+ - FPGA_IFX
232+ then:
233+ properties:
234+ groups:
235+ enum:
236+ - FPGA_IFX
237+ - if:
238+ properties:
239+ function:
240+ enum:
241+ - HDMI_TX
242+ then:
243+ properties:
244+ groups:
245+ enum:
246+ - HDMI_TX1
247+ - HDMI_TX2
248+ - HDMI_TX3
249+ - if:
250+ properties:
251+ function:
252+ enum:
253+ - LCDIF
254+ then:
255+ properties:
256+ groups:
257+ enum:
258+ - LCDIF
259+ - if:
260+ properties:
261+ function:
262+ enum:
263+ - USB0_OTG
264+ then:
265+ properties:
266+ groups:
267+ enum:
268+ - USB0_OTG
269+ - if:
270+ properties:
271+ function:
272+ enum:
273+ - USB1_OTG
274+ then:
275+ properties:
276+ groups:
277+ enum:
278+ - USB1_OTG
279+
280+required:
281+ - compatible
282+ - reg
283+ - reg-names
284+ - "#gpio-cells"
285+ - gpio-controller
286+ - clocks
287+ - resets
288+
289+additionalProperties: false
290+
291+examples:
292+ - |
293+ #include <dt-bindings/pinctrl/sppctl-sp7021.h>
294+
295+ pinctl@9c000100 {
296+ compatible = "sunplus,sp7021-pctl";
297+ reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
298+ <0x9c0032e4 0x1c>, <0x9c000080 0x20>;
299+ reg-names = "moon2", "gpioxt", "first", "moon1";
300+ gpio-controller;
301+ #gpio-cells = <2>;
302+ clocks = <&clkc 0x83>;
303+ resets = <&rstc 0x73>;
304+
305+ uart0-pins {
306+ function = "UA0";
307+ groups = "UA0";
308+ };
309+
310+ spinand0-pins {
311+ function = "SPI_NAND";
312+ groups = "SPI_NAND";
313+ };
314+
315+ uart1-pins {
316+ sunplus,pins = <
317+ SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
318+ SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
319+ >;
320+ };
321+
322+ uart2-pins {
323+ sunplus,pins = <
324+ SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
325+ SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
326+ SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
327+ SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
328+ >;
329+ };
330+
331+ emmc-pins {
332+ function = "CARD0_EMMC";
333+ groups = "CARD0_EMMC";
334+ };
335+
336+ sdcard-pins {
337+ function = "SD_CARD";
338+ groups = "SD_CARD";
339+ sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
340+ };
341+
342+ hdmi_A_tx1-pins {
343+ function = "HDMI_TX";
344+ groups = "HDMI_TX1";
345+ };
346+ hdmi_A_tx2-pins {
347+ function = "HDMI_TX";
348+ groups = "HDMI_TX2";
349+ };
350+ hdmi_A_tx3-pins {
351+ function = "HDMI_TX";
352+ groups = "HDMI_TX3";
353+ };
354+
355+ ethernet-pins {
356+ sunplus,pins = <
357+ SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
358+ SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
359+ SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
360+ SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
361+ SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
362+ SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
363+ SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
364+ SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
365+ SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
366+ >;
367+ sunplus,zerofunc = <
368+ MUXF_L2SW_LED_FLASH0
369+ MUXF_L2SW_LED_ON0
370+ MUXF_L2SW_P0_MAC_RMII_RXER
371+ >;
372+ };
373+ };
374+...
MAINTAINERS+19−0
@@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki · 2382 unmodified lines
23832383 F: Documentation/devicetree/bindings/*/*wpcm*
23842384 F: arch/arm/boot/dts/nuvoton-wpcm450*
23852385 F: arch/arm/mach-npcm/wpcm450.c
2386+F: drivers/*/*/*wpcm*
23862387 F: drivers/*/*wpcm*
23872388
23882389 ARM/NXP S32G ARCHITECTURE
@@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml · 1327 unmodified lines
37163717 F: drivers/net/ethernet/broadcom/bcm4908_enet.*
37173718 F: drivers/net/ethernet/broadcom/unimac.h
37183719
3720+BROADCOM BCM4908 PINMUX DRIVER
3721+M: Rafał Miłecki <rafal@milecki.pl>
3722+M: bcm-kernel-feedback-list@broadcom.com
3723+L: linux-gpio@vger.kernel.org
3724+S: Maintained
3725+F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
3726+F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
3727+
37193728 BROADCOM BCM5301X ARM ARCHITECTURE
37203729 M: Florian Fainelli <f.fainelli@gmail.com>
37213730 M: Hauke Mehrtens <hauke@hauke-m.de>
@@ -15478,6 +15487,16 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> · 11756 unmodified lines
1547815487 S: Supported
1547915488 F: drivers/pinctrl/pinctrl-thunderbay.c
1548015489
15490+PIN CONTROLLER - SUNPLUS / TIBBO
15491+M: Dvorkin Dmitry <dvorkin@tibbo.com>
15492+M: Wells Lu <wellslutw@gmail.com>
15493+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
15494+S: Maintained
15495+W: https://sunplus.atlassian.net/wiki/spaces/doc/overview
15496+F: Documentation/devicetree/bindings/pinctrl/sunplus,*
15497+F: drivers/pinctrl/sunplus/
15498+F: include/dt-bindings/pinctrl/sppctl*.h
15499+
1548115500 PKTCDVD DRIVER
1548215501 M: linux-block@vger.kernel.org
1548315502 S: Orphan
drivers/pinctrl/Kconfig+1−0
@@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig" · 526 unmodified lines
527527 source "drivers/pinctrl/spear/Kconfig"
528528 source "drivers/pinctrl/sprd/Kconfig"
529529 source "drivers/pinctrl/stm32/Kconfig"
530+source "drivers/pinctrl/sunplus/Kconfig"
530531 source "drivers/pinctrl/sunxi/Kconfig"
531532 source "drivers/pinctrl/tegra/Kconfig"
532533 source "drivers/pinctrl/ti/Kconfig"
drivers/pinctrl/Makefile+2−1
@@ -62,7 +62,7 @@ obj-y += mediatek/ · 61 unmodified lines
6262 obj-$(CONFIG_PINCTRL_MESON) += meson/
6363 obj-y += mvebu/
6464 obj-y += nomadik/
65−obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
65+obj-y += nuvoton/
6666 obj-$(CONFIG_PINCTRL_PXA) += pxa/
6767 obj-$(CONFIG_ARCH_QCOM) += qcom/
6868 obj-$(CONFIG_PINCTRL_RALINK) += ralink/
@@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ · 2 unmodified lines
7171 obj-$(CONFIG_PINCTRL_SPEAR) += spear/
7272 obj-y += sprd/
7373 obj-$(CONFIG_PINCTRL_STM32) += stm32/
74+obj-y += sunplus/
7475 obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
7576 obj-$(CONFIG_ARCH_TEGRA) += tegra/
7677 obj-y += ti/
drivers/pinctrl/bcm/Kconfig+14−0
@@ -29,6 +29,20 @@ config PINCTRL_BCM2835 · 28 unmodified lines
2929 help
3030 Say Y here to enable the Broadcom BCM2835 GPIO driver.
3131
32+config PINCTRL_BCM4908
33+ tristate "Broadcom BCM4908 pinmux driver"
34+ depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
35+ select PINMUX
36+ select PINCONF
37+ select GENERIC_PINCONF
38+ select GENERIC_PINCTRL_GROUPS
39+ select GENERIC_PINMUX_FUNCTIONS
40+ default ARCH_BCM4908
41+ help
42+ Driver for BCM4908 family SoCs with integrated pin controller.
43+
44+ If compiled as module it will be called pinctrl-bcm4908.
45+
3246 config PINCTRL_BCM63XX
3347 bool
3448 select PINMUX
drivers/pinctrl/bcm/Makefile+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
33
44 obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
55 obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
6+obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
67 obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
78 obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
89 obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
drivers/pinctrl/bcm/pinctrl-bcm4908.c+563−0
@@ -0,0 +1,563 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
3+
4+#include <linux/err.h>
5+#include <linux/io.h>
6+#include <linux/mod_devicetable.h>
7+#include <linux/module.h>
8+#include <linux/pinctrl/pinconf-generic.h>
9+#include <linux/pinctrl/pinctrl.h>
10+#include <linux/pinctrl/pinmux.h>
11+#include <linux/platform_device.h>
12+#include <linux/slab.h>
13+#include <linux/string_helpers.h>
14+
15+#include "../core.h"
16+#include "../pinmux.h"
17+
18+#define BCM4908_NUM_PINS 86
19+
20+#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
21+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
22+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
23+#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
24+#define BCM4908_TEST_PORT_COMMAND 0x0c
25+#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
26+
27+struct bcm4908_pinctrl {
28+ struct device *dev;
29+ void __iomem *base;
30+ struct mutex mutex;
31+ struct pinctrl_dev *pctldev;
32+ struct pinctrl_desc pctldesc;
33+};
34+
35+/*
36+ * Groups
37+ */
38+
39+struct bcm4908_pinctrl_pin_setup {
40+ unsigned int number;
41+ unsigned int function;
42+};
43+
44+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
45+ { 0, 3 },
46+};
47+
48+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
49+ { 1, 3 },
50+};
51+
52+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
53+ { 2, 3 },
54+};
55+
56+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
57+ { 3, 3 },
58+};
59+
60+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
61+ { 4, 3 },
62+};
63+
64+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
65+ { 5, 3 },
66+};
67+
68+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
69+ { 6, 3 },
70+};
71+
72+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
73+ { 7, 3 },
74+};
75+
76+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
77+ { 8, 3 },
78+};
79+
80+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
81+ { 9, 3 },
82+};
83+
84+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
85+ { 10, 3 },
86+};
87+
88+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
89+ { 11, 3 },
90+};
91+
92+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
93+ { 12, 3 },
94+};
95+
96+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
97+ { 13, 3 },
98+};
99+
100+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
101+ { 14, 3 },
102+};
103+
104+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
105+ { 15, 3 },
106+};
107+
108+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
109+ { 16, 3 },
110+};
111+
112+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
113+ { 17, 3 },
114+};
115+
116+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
117+ { 18, 3 },
118+};
119+
120+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
121+ { 19, 3 },
122+};
123+
124+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
125+ { 20, 3 },
126+};
127+
128+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
129+ { 21, 3 },
130+};
131+
132+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
133+ { 22, 3 },
134+};
135+
136+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
137+ { 23, 3 },
138+};
139+
140+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
141+ { 24, 3 },
142+};
143+
144+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
145+ { 25, 3 },
146+};
147+
148+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
149+ { 26, 3 },
150+};
151+
152+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
153+ { 27, 3 },
154+};
155+
156+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
157+ { 28, 3 },
158+};
159+
160+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
161+ { 29, 3 },
162+};
163+
164+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
165+ { 30, 3 },
166+};
167+
168+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
169+ { 31, 3 },
170+};
171+
172+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
173+ { 8, 2 },
174+};
175+
176+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
177+ { 9, 2 },
178+};
179+
180+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
181+ { 0, 2 },
182+};
183+
184+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
185+ { 1, 2 },
186+};
187+
188+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
189+ { 30, 2 },
190+};
191+
192+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
193+ { 10, 0 }, /* CTS */
194+ { 11, 0 }, /* RTS */
195+ { 12, 0 }, /* RXD */
196+ { 13, 0 }, /* TXD */
197+};
198+
199+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
200+ { 18, 0 }, /* SDA */
201+ { 19, 0 }, /* SCL */
202+};
203+
204+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
205+ { 22, 0 }, /* SDA */
206+ { 23, 0 }, /* SCL */
207+};
208+
209+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
210+ { 27, 0 }, /* MCLK */
211+ { 28, 0 }, /* LRCK */
212+ { 29, 0 }, /* SDATA */
213+ { 30, 0 }, /* SCLK */
214+};
215+
216+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
217+ { 32, 0 },
218+ { 33, 0 },
219+ { 34, 0 },
220+ { 43, 0 },
221+ { 44, 0 },
222+ { 45, 0 },
223+ { 56, 1 },
224+};
225+
226+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
227+ { 35, 0 },
228+ { 36, 0 },
229+ { 37, 0 },
230+ { 38, 0 },
231+ { 39, 0 },
232+ { 40, 0 },
233+ { 41, 0 },
234+ { 42, 0 },
235+};
236+
237+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
238+ { 46, 0 },
239+ { 47, 0 },
240+};
241+
242+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
243+ { 63, 0 },
244+ { 64, 0 },
245+};
246+
247+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
248+ { 66, 0 },
249+ { 67, 0 },
250+};
251+
252+struct bcm4908_pinctrl_grp {
253+ const char *name;
254+ const struct bcm4908_pinctrl_pin_setup *pins;
255+ const unsigned int num_pins;
256+};
257+
258+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
259+ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
260+ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
261+ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
262+ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
263+ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
264+ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
265+ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
266+ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
267+ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
268+ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
269+ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
270+ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
271+ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
272+ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
273+ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
274+ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
275+ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
276+ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
277+ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
278+ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
279+ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
280+ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
281+ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
282+ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
283+ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
284+ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
285+ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
286+ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
287+ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
288+ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
289+ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
290+ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
291+ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
292+ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
293+ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
294+ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
295+ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
296+ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
297+ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
298+ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
299+ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
300+ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
301+ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
302+ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
303+ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
304+ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
305+};
306+
307+/*
308+ * Functions
309+ */
310+
311+struct bcm4908_pinctrl_function {
312+ const char *name;
313+ const char * const *groups;
314+ const unsigned int num_groups;
315+};
316+
317+static const char * const led_0_groups[] = { "led_0_grp_a" };
318+static const char * const led_1_groups[] = { "led_1_grp_a" };
319+static const char * const led_2_groups[] = { "led_2_grp_a" };
320+static const char * const led_3_groups[] = { "led_3_grp_a" };
321+static const char * const led_4_groups[] = { "led_4_grp_a" };
322+static const char * const led_5_groups[] = { "led_5_grp_a" };
323+static const char * const led_6_groups[] = { "led_6_grp_a" };
324+static const char * const led_7_groups[] = { "led_7_grp_a" };
325+static const char * const led_8_groups[] = { "led_8_grp_a" };
326+static const char * const led_9_groups[] = { "led_9_grp_a" };
327+static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
328+static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
329+static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
330+static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
331+static const char * const led_14_groups[] = { "led_14_grp_a" };
332+static const char * const led_15_groups[] = { "led_15_grp_a" };
333+static const char * const led_16_groups[] = { "led_16_grp_a" };
334+static const char * const led_17_groups[] = { "led_17_grp_a" };
335+static const char * const led_18_groups[] = { "led_18_grp_a" };
336+static const char * const led_19_groups[] = { "led_19_grp_a" };
337+static const char * const led_20_groups[] = { "led_20_grp_a" };
338+static const char * const led_21_groups[] = { "led_21_grp_a" };
339+static const char * const led_22_groups[] = { "led_22_grp_a" };
340+static const char * const led_23_groups[] = { "led_23_grp_a" };
341+static const char * const led_24_groups[] = { "led_24_grp_a" };
342+static const char * const led_25_groups[] = { "led_25_grp_a" };
343+static const char * const led_26_groups[] = { "led_26_grp_a" };
344+static const char * const led_27_groups[] = { "led_27_grp_a" };
345+static const char * const led_28_groups[] = { "led_28_grp_a" };
346+static const char * const led_29_groups[] = { "led_29_grp_a" };
347+static const char * const led_30_groups[] = { "led_30_grp_a" };
348+static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
349+static const char * const hs_uart_groups[] = { "hs_uart_grp" };
350+static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
351+static const char * const i2s_groups[] = { "i2s_grp" };
352+static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
353+static const char * const nand_data_groups[] = { "nand_data_grp" };
354+static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
355+static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
356+static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
357+
358+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
359+ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
360+ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
361+ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
362+ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
363+ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
364+ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
365+ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
366+ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
367+ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
368+ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
369+ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
370+ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
371+ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
372+ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
373+ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
374+ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
375+ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
376+ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
377+ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
378+ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
379+ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
380+ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
381+ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
382+ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
383+ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
384+ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
385+ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
386+ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
387+ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
388+ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
389+ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
390+ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
391+ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
392+ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
393+ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
394+ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
395+ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
396+ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
397+ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
398+ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
399+};
400+
401+/*
402+ * Groups code
403+ */
404+
405+static const struct pinctrl_ops bcm4908_pinctrl_ops = {
406+ .get_groups_count = pinctrl_generic_get_group_count,
407+ .get_group_name = pinctrl_generic_get_group_name,
408+ .get_group_pins = pinctrl_generic_get_group_pins,
409+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
410+ .dt_free_map = pinconf_generic_dt_free_map,
411+};
412+
413+/*
414+ * Functions code
415+ */
416+
417+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
418+ unsigned int func_selector,
419+ unsigned int group_selector)
420+{
421+ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
422+ const struct bcm4908_pinctrl_grp *group;
423+ struct group_desc *group_desc;
424+ int i;
425+
426+ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
427+ if (!group_desc)
428+ return -EINVAL;
429+ group = group_desc->data;
430+
431+ mutex_lock(&bcm4908_pinctrl->mutex);
432+ for (i = 0; i < group->num_pins; i++) {
433+ u32 lsb = 0;
434+
435+ lsb |= group->pins[i].number;
436+ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
437+
438+ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
439+ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
440+ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
441+ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
442+ }
443+ mutex_unlock(&bcm4908_pinctrl->mutex);
444+
445+ return 0;
446+}
447+
448+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
449+ .get_functions_count = pinmux_generic_get_function_count,
450+ .get_function_name = pinmux_generic_get_function_name,
451+ .get_function_groups = pinmux_generic_get_function_groups,
452+ .set_mux = bcm4908_pinctrl_set_mux,
453+};
454+
455+/*
456+ * Controller code
457+ */
458+
459+static struct pinctrl_desc bcm4908_pinctrl_desc = {
460+ .name = "bcm4908-pinctrl",
461+ .pctlops = &bcm4908_pinctrl_ops,
462+ .pmxops = &bcm4908_pinctrl_pmxops,
463+};
464+
465+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
466+ { .compatible = "brcm,bcm4908-pinctrl", },
467+ { }
468+};
469+
470+static int bcm4908_pinctrl_probe(struct platform_device *pdev)
471+{
472+ struct device *dev = &pdev->dev;
473+ struct bcm4908_pinctrl *bcm4908_pinctrl;
474+ struct pinctrl_desc *pctldesc;
475+ struct pinctrl_pin_desc *pins;
476+ char **pin_names;
477+ int i;
478+
479+ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
480+ if (!bcm4908_pinctrl)
481+ return -ENOMEM;
482+ pctldesc = &bcm4908_pinctrl->pctldesc;
483+ platform_set_drvdata(pdev, bcm4908_pinctrl);
484+
485+ /* Set basic properties */
486+
487+ bcm4908_pinctrl->dev = dev;
488+
489+ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
490+ if (IS_ERR(bcm4908_pinctrl->base))
491+ return PTR_ERR(bcm4908_pinctrl->base);
492+
493+ mutex_init(&bcm4908_pinctrl->mutex);
494+
495+ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
496+
497+ /* Set pinctrl properties */
498+
499+ pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS);
500+ if (IS_ERR(pin_names))
501+ return PTR_ERR(pin_names);
502+
503+ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
504+ if (!pins)
505+ return -ENOMEM;
506+ for (i = 0; i < BCM4908_NUM_PINS; i++) {
507+ pins[i].number = i;
508+ pins[i].name = pin_names[i];
509+ }
510+ pctldesc->pins = pins;
511+ pctldesc->npins = BCM4908_NUM_PINS;
512+
513+ /* Register */
514+
515+ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
516+ if (IS_ERR(bcm4908_pinctrl->pctldev))
517+ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
518+ "Failed to register pinctrl\n");
519+
520+ /* Groups */
521+
522+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
523+ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
524+ int *pins;
525+ int j;
526+
527+ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
528+ if (!pins)
529+ return -ENOMEM;
530+ for (j = 0; j < group->num_pins; j++)
531+ pins[j] = group->pins[j].number;
532+
533+ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
534+ pins, group->num_pins, (void *)group);
535+ }
536+
537+ /* Functions */
538+
539+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
540+ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
541+
542+ pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
543+ function->name,
544+ function->groups,
545+ function->num_groups, NULL);
546+ }
547+
548+ return 0;
549+}
550+
551+static struct platform_driver bcm4908_pinctrl_driver = {
552+ .probe = bcm4908_pinctrl_probe,
553+ .driver = {
554+ .name = "bcm4908-pinctrl",
555+ .of_match_table = bcm4908_pinctrl_of_match_table,
556+ },
557+};
558+
559+module_platform_driver(bcm4908_pinctrl_driver);
560+
561+MODULE_AUTHOR("Rafał Miłecki");
562+MODULE_LICENSE("GPL v2");
563+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
drivers/pinctrl/berlin/berlin.c+2−0
@@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) · 232 unmodified lines
233233 pctrl->functions = krealloc(pctrl->functions,
234234 pctrl->nfunctions * sizeof(*pctrl->functions),
235235 GFP_KERNEL);
236+ if (!pctrl->functions)
237+ return -ENOMEM;
236238
237239 /* map functions to theirs groups */
238240 for (i = 0; i < pctrl->desc->ngroups; i++) {
drivers/pinctrl/freescale/Kconfig+7−0
@@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050 · 179 unmodified lines
180180 help
181181 Say Y here to enable the imxrt1050 pinctrl driver
182182
183+config PINCTRL_IMX93
184+ tristate "IMX93 pinctrl driver"
185+ depends on ARCH_MXC
186+ select PINCTRL_IMX
187+ help
188+ Say Y here to enable the imx93 pinctrl driver
189+
183190 config PINCTRL_VF610
184191 bool "Freescale Vybrid VF610 pinctrl driver"
185192 depends on SOC_VF610
drivers/pinctrl/freescale/Makefile+1−0
@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o · 24 unmodified lines
2525 obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
2626 obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
2727 obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
28+obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
2829 obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
2930 obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
3031 obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
drivers/pinctrl/freescale/pinctrl-imx.c+1−1
@@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, · 660 unmodified lines
661661 func->name = np->name;
662662 func->num_group_names = of_get_child_count(np);
663663 if (func->num_group_names == 0) {
664− dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
664+ dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
665665 return -EINVAL;
666666 }
667667
drivers/pinctrl/freescale/pinctrl-imx93.c+272−0
@@ -0,0 +1,272 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright 2021 NXP
4+ */
5+
6+#include <linux/err.h>
7+#include <linux/init.h>
8+#include <linux/io.h>
9+#include <linux/module.h>
10+#include <linux/of.h>
11+#include <linux/of_device.h>
12+#include <linux/pinctrl/pinctrl.h>
13+
14+#include "pinctrl-imx.h"
15+
16+enum imx93_pads {
17+ IMX93_IOMUXC_DAP_TDI = 0,
18+ IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
19+ IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
20+ IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
21+ IMX93_IOMUXC_GPIO_IO00 = 4,
22+ IMX93_IOMUXC_GPIO_IO01 = 5,
23+ IMX93_IOMUXC_GPIO_IO02 = 6,
24+ IMX93_IOMUXC_GPIO_IO03 = 7,
25+ IMX93_IOMUXC_GPIO_IO04 = 8,
26+ IMX93_IOMUXC_GPIO_IO05 = 9,
27+ IMX93_IOMUXC_GPIO_IO06 = 10,
28+ IMX93_IOMUXC_GPIO_IO07 = 11,
29+ IMX93_IOMUXC_GPIO_IO08 = 12,
30+ IMX93_IOMUXC_GPIO_IO09 = 13,
31+ IMX93_IOMUXC_GPIO_IO10 = 14,
32+ IMX93_IOMUXC_GPIO_IO11 = 15,
33+ IMX93_IOMUXC_GPIO_IO12 = 16,
34+ IMX93_IOMUXC_GPIO_IO13 = 17,
35+ IMX93_IOMUXC_GPIO_IO14 = 18,
36+ IMX93_IOMUXC_GPIO_IO15 = 19,
37+ IMX93_IOMUXC_GPIO_IO16 = 20,
38+ IMX93_IOMUXC_GPIO_IO17 = 21,
39+ IMX93_IOMUXC_GPIO_IO18 = 22,
40+ IMX93_IOMUXC_GPIO_IO19 = 23,
41+ IMX93_IOMUXC_GPIO_IO20 = 24,
42+ IMX93_IOMUXC_GPIO_IO21 = 25,
43+ IMX93_IOMUXC_GPIO_IO22 = 26,
44+ IMX93_IOMUXC_GPIO_IO23 = 27,
45+ IMX93_IOMUXC_GPIO_IO24 = 28,
46+ IMX93_IOMUXC_GPIO_IO25 = 29,
47+ IMX93_IOMUXC_GPIO_IO26 = 30,
48+ IMX93_IOMUXC_GPIO_IO27 = 31,
49+ IMX93_IOMUXC_GPIO_IO28 = 32,
50+ IMX93_IOMUXC_GPIO_IO29 = 33,
51+ IMX93_IOMUXC_CCM_CLKO1 = 34,
52+ IMX93_IOMUXC_CCM_CLKO2 = 35,
53+ IMX93_IOMUXC_CCM_CLKO3 = 36,
54+ IMX93_IOMUXC_CCM_CLKO4 = 37,
55+ IMX93_IOMUXC_ENET1_MDC = 38,
56+ IMX93_IOMUXC_ENET1_MDIO = 39,
57+ IMX93_IOMUXC_ENET1_TD3 = 40,
58+ IMX93_IOMUXC_ENET1_TD2 = 41,
59+ IMX93_IOMUXC_ENET1_TD1 = 42,
60+ IMX93_IOMUXC_ENET1_TD0 = 43,
61+ IMX93_IOMUXC_ENET1_TX_CTL = 44,
62+ IMX93_IOMUXC_ENET1_TXC = 45,
63+ IMX93_IOMUXC_ENET1_RX_CTL = 46,
64+ IMX93_IOMUXC_ENET1_RXC = 47,
65+ IMX93_IOMUXC_ENET1_RD0 = 48,
66+ IMX93_IOMUXC_ENET1_RD1 = 49,
67+ IMX93_IOMUXC_ENET1_RD2 = 50,
68+ IMX93_IOMUXC_ENET1_RD3 = 51,
69+ IMX93_IOMUXC_ENET2_MDC = 52,
70+ IMX93_IOMUXC_ENET2_MDIO = 53,
71+ IMX93_IOMUXC_ENET2_TD3 = 54,
72+ IMX93_IOMUXC_ENET2_TD2 = 55,
73+ IMX93_IOMUXC_ENET2_TD1 = 56,
74+ IMX93_IOMUXC_ENET2_TD0 = 57,
75+ IMX93_IOMUXC_ENET2_TX_CTL = 58,
76+ IMX93_IOMUXC_ENET2_TXC = 59,
77+ IMX93_IOMUXC_ENET2_RX_CTL = 60,
78+ IMX93_IOMUXC_ENET2_RXC = 61,
79+ IMX93_IOMUXC_ENET2_RD0 = 62,
80+ IMX93_IOMUXC_ENET2_RD1 = 63,
81+ IMX93_IOMUXC_ENET2_RD2 = 64,
82+ IMX93_IOMUXC_ENET2_RD3 = 65,
83+ IMX93_IOMUXC_SD1_CLK = 66,
84+ IMX93_IOMUXC_SD1_CMD = 67,
85+ IMX93_IOMUXC_SD1_DATA0 = 68,
86+ IMX93_IOMUXC_SD1_DATA1 = 69,
87+ IMX93_IOMUXC_SD1_DATA2 = 70,
88+ IMX93_IOMUXC_SD1_DATA3 = 71,
89+ IMX93_IOMUXC_SD1_DATA4 = 72,
90+ IMX93_IOMUXC_SD1_DATA5 = 73,
91+ IMX93_IOMUXC_SD1_DATA6 = 74,
92+ IMX93_IOMUXC_SD1_DATA7 = 75,
93+ IMX93_IOMUXC_SD1_STROBE = 76,
94+ IMX93_IOMUXC_SD2_VSELECT = 77,
95+ IMX93_IOMUXC_SD3_CLK = 78,
96+ IMX93_IOMUXC_SD3_CMD = 79,
97+ IMX93_IOMUXC_SD3_DATA0 = 80,
98+ IMX93_IOMUXC_SD3_DATA1 = 81,
99+ IMX93_IOMUXC_SD3_DATA2 = 82,
100+ IMX93_IOMUXC_SD3_DATA3 = 83,
101+ IMX93_IOMUXC_SD2_CD_B = 84,
102+ IMX93_IOMUXC_SD2_CLK = 85,
103+ IMX93_IOMUXC_SD2_CMD = 86,
104+ IMX93_IOMUXC_SD2_DATA0 = 87,
105+ IMX93_IOMUXC_SD2_DATA1 = 88,
106+ IMX93_IOMUXC_SD2_DATA2 = 89,
107+ IMX93_IOMUXC_SD2_DATA3 = 90,
108+ IMX93_IOMUXC_SD2_RESET_B = 91,
109+ IMX93_IOMUXC_I2C1_SCL = 92,
110+ IMX93_IOMUXC_I2C1_SDA = 93,
111+ IMX93_IOMUXC_I2C2_SCL = 94,
112+ IMX93_IOMUXC_I2C2_SDA = 95,
113+ IMX93_IOMUXC_UART1_RXD = 96,
114+ IMX93_IOMUXC_UART1_TXD = 97,
115+ IMX93_IOMUXC_UART2_RXD = 98,
116+ IMX93_IOMUXC_UART2_TXD = 99,
117+ IMX93_IOMUXC_PDM_CLK = 100,
118+ IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
119+ IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
120+ IMX93_IOMUXC_SAI1_TXFS = 103,
121+ IMX93_IOMUXC_SAI1_TXC = 104,
122+ IMX93_IOMUXC_SAI1_TXD0 = 105,
123+ IMX93_IOMUXC_SAI1_RXD0 = 106,
124+ IMX93_IOMUXC_WDOG_ANY = 107,
125+};
126+
127+/* Pad names for the pinmux subsystem */
128+static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
129+ IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
130+ IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
131+ IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
132+ IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
133+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
134+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
135+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
136+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
137+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
138+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
139+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
140+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
141+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
142+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
143+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
144+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
145+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
146+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
147+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
148+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
149+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
150+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
151+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
152+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
153+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
154+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
155+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
156+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
157+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
158+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
159+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
160+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
161+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
162+ IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
163+ IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
164+ IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
165+ IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
166+ IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
167+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
168+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
169+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
170+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
171+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
172+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
173+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
174+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
175+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
176+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
177+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
178+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
179+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
180+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
181+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
182+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
183+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
184+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
185+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
186+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
187+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
188+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
189+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
190+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
191+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
192+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
193+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
194+ IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
195+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
196+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
197+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
198+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
199+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
200+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
201+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
202+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
203+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
204+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
205+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
206+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
207+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
208+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
209+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
210+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
211+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
212+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
213+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
214+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
215+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
216+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
217+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
218+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
219+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
220+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
221+ IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
222+ IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
223+ IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
224+ IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
225+ IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
226+ IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
227+ IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
228+ IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
229+ IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
230+ IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
231+ IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
232+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
233+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
234+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
235+ IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
236+ IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
237+};
238+
239+static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
240+ .pins = imx93_pinctrl_pads,
241+ .npins = ARRAY_SIZE(imx93_pinctrl_pads),
242+ .gpr_compatible = "fsl,imx93-iomuxc-gpr",
243+};
244+
245+static const struct of_device_id imx93_pinctrl_of_match[] = {
246+ { .compatible = "fsl,imx93-iomuxc", },
247+ { /* sentinel */ }
248+};
249+
250+static int imx93_pinctrl_probe(struct platform_device *pdev)
251+{
252+ return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
253+}
254+
255+static struct platform_driver imx93_pinctrl_driver = {
256+ .driver = {
257+ .name = "imx93-pinctrl",
258+ .of_match_table = imx93_pinctrl_of_match,
259+ .suppress_bind_attrs = true,
260+ },
261+ .probe = imx93_pinctrl_probe,
262+};
263+
264+static int __init imx93_pinctrl_init(void)
265+{
266+ return platform_driver_register(&imx93_pinctrl_driver);
267+}
268+arch_initcall(imx93_pinctrl_init);
269+
270+MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
271+MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
272+MODULE_LICENSE("GPL v2");
drivers/pinctrl/intel/pinctrl-alderlake.c+316−1
@@ -2,7 +2,7 @@ · 1 unmodified line
22 /*
33 * Intel Alder Lake PCH pinctrl/GPIO driver
44 *
5− * Copyright (C) 2020, Intel Corporation
5+ * Copyright (C) 2020, 2022 Intel Corporation
66 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
77 */
88
@@ -42,6 +42,319 @@ · 33 unmodified lines
4242 .ngpps = ARRAY_SIZE(g), \
4343 }
4444
45+/* Alder Lake-N */
46+static const struct pinctrl_pin_desc adln_pins[] = {
47+ /* GPP_B */
48+ PINCTRL_PIN(0, "CORE_VID_0"),
49+ PINCTRL_PIN(1, "CORE_VID_1"),
50+ PINCTRL_PIN(2, "GPPC_B_2"),
51+ PINCTRL_PIN(3, "GPPC_B_3"),
52+ PINCTRL_PIN(4, "GPPC_B_4"),
53+ PINCTRL_PIN(5, "GPPC_B_5"),
54+ PINCTRL_PIN(6, "GPPC_B_6"),
55+ PINCTRL_PIN(7, "GPPC_B_7"),
56+ PINCTRL_PIN(8, "GPPC_B_8"),
57+ PINCTRL_PIN(9, "GPPC_B_9"),
58+ PINCTRL_PIN(10, "GPPC_B_10"),
59+ PINCTRL_PIN(11, "GPPC_B_11"),
60+ PINCTRL_PIN(12, "SLP_S0B"),
61+ PINCTRL_PIN(13, "PLTRSTB"),
62+ PINCTRL_PIN(14, "GPPC_B_14"),
63+ PINCTRL_PIN(15, "GPPC_B_15"),
64+ PINCTRL_PIN(16, "GPPC_B_16"),
65+ PINCTRL_PIN(17, "GPPC_B_17"),
66+ PINCTRL_PIN(18, "GPPC_B_18"),
67+ PINCTRL_PIN(19, "GPPC_B_19"),
68+ PINCTRL_PIN(20, "GPPC_B_20"),
69+ PINCTRL_PIN(21, "GPPC_B_21"),
70+ PINCTRL_PIN(22, "GPPC_B_22"),
71+ PINCTRL_PIN(23, "GPPC_B_23"),
72+ PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
73+ PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
74+ /* GPP_T */
75+ PINCTRL_PIN(26, "GPPC_T_0"),
76+ PINCTRL_PIN(27, "GPPC_T_1"),
77+ PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"),
78+ PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"),
79+ PINCTRL_PIN(30, "GPPC_T_4"),
80+ PINCTRL_PIN(31, "GPPC_T_5"),
81+ PINCTRL_PIN(32, "GPPC_T_6"),
82+ PINCTRL_PIN(33, "GPPC_T_7"),
83+ PINCTRL_PIN(34, "GPPC_T_8"),
84+ PINCTRL_PIN(35, "GPPC_T_9"),
85+ PINCTRL_PIN(36, "GPPC_T_10"),
86+ PINCTRL_PIN(37, "GPPC_T_11"),
87+ PINCTRL_PIN(38, "GPPC_T_12"),
88+ PINCTRL_PIN(39, "GPPC_T_13"),
89+ PINCTRL_PIN(40, "GPPC_T_14"),
90+ PINCTRL_PIN(41, "GPPC_T_15"),
91+ /* GPP_A */
92+ PINCTRL_PIN(42, "ESPI_IO_0"),
93+ PINCTRL_PIN(43, "ESPI_IO_1"),
94+ PINCTRL_PIN(44, "ESPI_IO_2"),
95+ PINCTRL_PIN(45, "ESPI_IO_3"),
96+ PINCTRL_PIN(46, "ESPI_CS0B"),
97+ PINCTRL_PIN(47, "ESPI_ALERT0B"),
98+ PINCTRL_PIN(48, "ESPI_ALERT1B"),
99+ PINCTRL_PIN(49, "GPPC_A_7"),
100+ PINCTRL_PIN(50, "GPPC_A_8"),
101+ PINCTRL_PIN(51, "ESPI_CLK"),
102+ PINCTRL_PIN(52, "ESPI_RESETB"),
103+ PINCTRL_PIN(53, "GPPC_A_11"),
104+ PINCTRL_PIN(54, "GPPC_A_12"),
105+ PINCTRL_PIN(55, "GPPC_A_13"),
106+ PINCTRL_PIN(56, "GPPC_A_14"),
107+ PINCTRL_PIN(57, "GPPC_A_15"),
108+ PINCTRL_PIN(58, "GPPC_A_16"),
109+ PINCTRL_PIN(59, "GPPC_A_17"),
110+ PINCTRL_PIN(60, "GPPC_A_18"),
111+ PINCTRL_PIN(61, "GPPC_A_19"),
112+ PINCTRL_PIN(62, "GPPC_A_20"),
113+ PINCTRL_PIN(63, "GPPC_A_21"),
114+ PINCTRL_PIN(64, "GPPC_A_22"),
115+ PINCTRL_PIN(65, "ESPI_CS1B"),
116+ PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
117+ /* GPP_S */
118+ PINCTRL_PIN(67, "GPP_S_0"),
119+ PINCTRL_PIN(68, "GPP_S_1"),
120+ PINCTRL_PIN(69, "GPP_S_2"),
121+ PINCTRL_PIN(70, "GPP_S_3"),
122+ PINCTRL_PIN(71, "GPP_S_4"),
123+ PINCTRL_PIN(72, "GPP_S_5"),
124+ PINCTRL_PIN(73, "GPP_S_6"),
125+ PINCTRL_PIN(74, "GPP_S_7"),
126+ /* GPP_I */
127+ PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"),
128+ PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"),
129+ PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"),
130+ PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"),
131+ PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"),
132+ PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"),
133+ PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"),
134+ PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"),
135+ PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"),
136+ PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"),
137+ PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"),
138+ PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"),
139+ PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"),
140+ PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"),
141+ PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"),
142+ PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"),
143+ PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"),
144+ PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"),
145+ PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"),
146+ PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"),
147+ /* GPP_H */
148+ PINCTRL_PIN(95, "GPPC_H_0"),
149+ PINCTRL_PIN(96, "GPPC_H_1"),
150+ PINCTRL_PIN(97, "GPPC_H_2"),
151+ PINCTRL_PIN(98, "GPPC_H_3"),
152+ PINCTRL_PIN(99, "GPPC_H_4"),
153+ PINCTRL_PIN(100, "GPPC_H_5"),
154+ PINCTRL_PIN(101, "GPPC_H_6"),
155+ PINCTRL_PIN(102, "GPPC_H_7"),
156+ PINCTRL_PIN(103, "GPPC_H_8"),
157+ PINCTRL_PIN(104, "GPPC_H_9"),
158+ PINCTRL_PIN(105, "GPPC_H_10"),
159+ PINCTRL_PIN(106, "GPPC_H_11"),
160+ PINCTRL_PIN(107, "I2C7_SDA"),
161+ PINCTRL_PIN(108, "I2C7_SCL"),
162+ PINCTRL_PIN(109, "GPPC_H_14"),
163+ PINCTRL_PIN(110, "GPPC_H_15"),
164+ PINCTRL_PIN(111, "GPPC_H_16"),
165+ PINCTRL_PIN(112, "GPPC_H_17"),
166+ PINCTRL_PIN(113, "CPU_C10_GATEB"),
167+ PINCTRL_PIN(114, "GPPC_H_19"),
168+ PINCTRL_PIN(115, "GPPC_H_20"),
169+ PINCTRL_PIN(116, "GPPC_H_21"),
170+ PINCTRL_PIN(117, "GPPC_H_22"),
171+ PINCTRL_PIN(118, "GPPC_H_23"),
172+ /* GPP_D */
173+ PINCTRL_PIN(119, "GPPC_D_0"),
174+ PINCTRL_PIN(120, "GPPC_D_1"),
175+ PINCTRL_PIN(121, "GPPC_D_2"),
176+ PINCTRL_PIN(122, "GPPC_D_3"),
177+ PINCTRL_PIN(123, "GPPC_D_4"),
178+ PINCTRL_PIN(124, "GPPC_D_5"),
179+ PINCTRL_PIN(125, "GPPC_D_6"),
180+ PINCTRL_PIN(126, "GPPC_D_7"),
181+ PINCTRL_PIN(127, "GPPC_D_8"),
182+ PINCTRL_PIN(128, "BSSB_LS2_RX"),
183+ PINCTRL_PIN(129, "BSSB_LS2_TX"),
184+ PINCTRL_PIN(130, "BSSB_LS3_RX"),
185+ PINCTRL_PIN(131, "BSSB_LS3_TX"),
186+ PINCTRL_PIN(132, "GPPC_D_13"),
187+ PINCTRL_PIN(133, "GPPC_D_14"),
188+ PINCTRL_PIN(134, "GPPC_D_15"),
189+ PINCTRL_PIN(135, "GPPC_D_16"),
190+ PINCTRL_PIN(136, "GPPC_D_17"),
191+ PINCTRL_PIN(137, "GPPC_D_18"),
192+ PINCTRL_PIN(138, "GPPC_D_19"),
193+ PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"),
194+ /* vGPIO */
195+ PINCTRL_PIN(140, "CNV_BTEN"),
196+ PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"),
197+ PINCTRL_PIN(142, "CNV_BT_IF_SELECT"),
198+ PINCTRL_PIN(143, "vCNV_BT_UART_TXD"),
199+ PINCTRL_PIN(144, "vCNV_BT_UART_RXD"),
200+ PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"),
201+ PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"),
202+ PINCTRL_PIN(147, "vCNV_MFUART1_TXD"),
203+ PINCTRL_PIN(148, "vCNV_MFUART1_RXD"),
204+ PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"),
205+ PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"),
206+ PINCTRL_PIN(151, "vUART0_TXD"),
207+ PINCTRL_PIN(152, "vUART0_RXD"),
208+ PINCTRL_PIN(153, "vUART0_CTS_B"),
209+ PINCTRL_PIN(154, "vUART0_RTS_B"),
210+ PINCTRL_PIN(155, "vISH_UART0_TXD"),
211+ PINCTRL_PIN(156, "vISH_UART0_RXD"),
212+ PINCTRL_PIN(157, "vISH_UART0_CTS_B"),
213+ PINCTRL_PIN(158, "vISH_UART0_RTS_B"),
214+ PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"),
215+ PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"),
216+ PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"),
217+ PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"),
218+ PINCTRL_PIN(163, "vI2S2_SCLK"),
219+ PINCTRL_PIN(164, "vI2S2_SFRM"),
220+ PINCTRL_PIN(165, "vI2S2_TXD"),
221+ PINCTRL_PIN(166, "vI2S2_RXD"),
222+ PINCTRL_PIN(167, "THC0_WOT_INT"),
223+ PINCTRL_PIN(168, "THC1_WOT_INT"),
224+ /* GPP_C */
225+ PINCTRL_PIN(169, "SMBCLK"),
226+ PINCTRL_PIN(170, "SMBDATA"),
227+ PINCTRL_PIN(171, "SMBALERTB"),
228+ PINCTRL_PIN(172, "SML0CLK"),
229+ PINCTRL_PIN(173, "SML0DATA"),
230+ PINCTRL_PIN(174, "GPPC_C_5"),
231+ PINCTRL_PIN(175, "GPPC_C_6"),
232+ PINCTRL_PIN(176, "GPPC_C_7"),
233+ PINCTRL_PIN(177, "GPPC_C_8"),
234+ PINCTRL_PIN(178, "GPPC_C_9"),
235+ PINCTRL_PIN(179, "GPPC_C_10"),
236+ PINCTRL_PIN(180, "GPPC_C_11"),
237+ PINCTRL_PIN(181, "GPPC_C_12"),
238+ PINCTRL_PIN(182, "GPPC_C_13"),
239+ PINCTRL_PIN(183, "GPPC_C_14"),
240+ PINCTRL_PIN(184, "GPPC_C_15"),
241+ PINCTRL_PIN(185, "GPPC_C_16"),
242+ PINCTRL_PIN(186, "GPPC_C_17"),
243+ PINCTRL_PIN(187, "GPPC_C_18"),
244+ PINCTRL_PIN(188, "GPPC_C_19"),
245+ PINCTRL_PIN(189, "GPPC_C_20"),
246+ PINCTRL_PIN(190, "GPPC_C_21"),
247+ PINCTRL_PIN(191, "GPPC_C_22"),
248+ PINCTRL_PIN(192, "GPPC_C_23"),
249+ /* GPP_F */
250+ PINCTRL_PIN(193, "CNV_BRI_DT"),
251+ PINCTRL_PIN(194, "CNV_BRI_RSP"),
252+ PINCTRL_PIN(195, "CNV_RGI_DT"),
253+ PINCTRL_PIN(196, "CNV_RGI_RSP"),
254+ PINCTRL_PIN(197, "CNV_RF_RESET_B"),
255+ PINCTRL_PIN(198, "MODEM_CLKREQ"),
256+ PINCTRL_PIN(199, "GPPC_F_6"),
257+ PINCTRL_PIN(200, "GPPC_F_7"),
258+ PINCTRL_PIN(201, "GPPC_F_8"),
259+ PINCTRL_PIN(202, "BOOTMPC"),
260+ PINCTRL_PIN(203, "GPPC_F_10"),
261+ PINCTRL_PIN(204, "GPPC_F_11"),
262+ PINCTRL_PIN(205, "GPPC_F_12"),
263+ PINCTRL_PIN(206, "GPPC_F_13"),
264+ PINCTRL_PIN(207, "GPPC_F_14"),
265+ PINCTRL_PIN(208, "GPPC_F_15"),
266+ PINCTRL_PIN(209, "GPPC_F_16"),
267+ PINCTRL_PIN(210, "GPPC_F_17"),
268+ PINCTRL_PIN(211, "GPPC_F_18"),
269+ PINCTRL_PIN(212, "GPPC_F_19"),
270+ PINCTRL_PIN(213, "EXT_PWR_GATEB"),
271+ PINCTRL_PIN(214, "EXT_PWR_GATE2B"),
272+ PINCTRL_PIN(215, "GPPC_F_22"),
273+ PINCTRL_PIN(216, "GPPC_F_23"),
274+ PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"),
275+ /* HVCMOS */
276+ PINCTRL_PIN(218, "L_BKLTEN"),
277+ PINCTRL_PIN(219, "L_BKLTCTL"),
278+ PINCTRL_PIN(220, "L_VDDEN"),
279+ PINCTRL_PIN(221, "SYS_PWROK"),
280+ PINCTRL_PIN(222, "SYS_RESETB"),
281+ PINCTRL_PIN(223, "MLK_RSTB"),
282+ /* GPP_E */
283+ PINCTRL_PIN(224, "GPPC_E_0"),
284+ PINCTRL_PIN(225, "GPPC_E_1"),
285+ PINCTRL_PIN(226, "GPPC_E_2"),
286+ PINCTRL_PIN(227, "GPPC_E_3"),
287+ PINCTRL_PIN(228, "GPPC_E_4"),
288+ PINCTRL_PIN(229, "GPPC_E_5"),
289+ PINCTRL_PIN(230, "GPPC_E_6"),
290+ PINCTRL_PIN(231, "GPPC_E_7"),
291+ PINCTRL_PIN(232, "GPPC_E_8"),
292+ PINCTRL_PIN(233, "GPPC_E_9"),
293+ PINCTRL_PIN(234, "GPPC_E_10"),
294+ PINCTRL_PIN(235, "GPPC_E_11"),
295+ PINCTRL_PIN(236, "GPPC_E_12"),
296+ PINCTRL_PIN(237, "GPPC_E_13"),
297+ PINCTRL_PIN(238, "GPPC_E_14"),
298+ PINCTRL_PIN(239, "FIVR_DIGPB_0"),
299+ PINCTRL_PIN(240, "FIVR_DIGPB_1"),
300+ PINCTRL_PIN(241, "GPPC_E_17"),
301+ PINCTRL_PIN(242, "BSSB_LS0_RX"),
302+ PINCTRL_PIN(243, "BSSB_LS0_TX"),
303+ PINCTRL_PIN(244, "BSSB_LS1_RX"),
304+ PINCTRL_PIN(245, "BSSB_LS1_TX"),
305+ PINCTRL_PIN(246, "DNX_FORCE_RELOAD"),
306+ PINCTRL_PIN(247, "GPPC_E_23"),
307+ PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"),
308+ /* GPP_R */
309+ PINCTRL_PIN(249, "HDA_BCLK"),
310+ PINCTRL_PIN(250, "HDA_SYNC"),
311+ PINCTRL_PIN(251, "HDA_SDO"),
312+ PINCTRL_PIN(252, "HDA_SDI_0"),
313+ PINCTRL_PIN(253, "HDA_RSTB"),
314+ PINCTRL_PIN(254, "GPP_R_5"),
315+ PINCTRL_PIN(255, "GPP_R_6"),
316+ PINCTRL_PIN(256, "GPP_R_7"),
317+};
318+
319+static const struct intel_padgroup adln_community0_gpps[] = {
320+ ADL_GPP(0, 0, 25, 0), /* GPP_B */
321+ ADL_GPP(1, 26, 41, 32), /* GPP_T */
322+ ADL_GPP(2, 42, 66, 64), /* GPP_A */
323+};
324+
325+static const struct intel_padgroup adln_community1_gpps[] = {
326+ ADL_GPP(0, 67, 74, 96), /* GPP_S */
327+ ADL_GPP(1, 75, 94, 128), /* GPP_I */
328+ ADL_GPP(2, 95, 118, 160), /* GPP_H */
329+ ADL_GPP(3, 119, 139, 192), /* GPP_D */
330+ ADL_GPP(4, 140, 168, 224), /* vGPIO */
331+};
332+
333+static const struct intel_padgroup adln_community4_gpps[] = {
334+ ADL_GPP(0, 169, 192, 256), /* GPP_C */
335+ ADL_GPP(1, 193, 217, 288), /* GPP_F */
336+ ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
337+ ADL_GPP(3, 224, 248, 320), /* GPP_E */
338+};
339+
340+static const struct intel_padgroup adln_community5_gpps[] = {
341+ ADL_GPP(0, 249, 256, 352), /* GPP_R */
342+};
343+
344+static const struct intel_community adln_communities[] = {
345+ ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
346+ ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
347+ ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
348+ ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
349+};
350+
351+static const struct intel_pinctrl_soc_data adln_soc_data = {
352+ .pins = adln_pins,
353+ .npins = ARRAY_SIZE(adln_pins),
354+ .communities = adln_communities,
355+ .ncommunities = ARRAY_SIZE(adln_communities),
356+};
357+
45358 /* Alder Lake-S */
46359 static const struct pinctrl_pin_desc adls_pins[] = {
47360 /* GPP_I */
@@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = { · 368 unmodified lines
416729
417730 static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
418731 { "INTC1056", (kernel_ulong_t)&adls_soc_data },
732+ { "INTC1057", (kernel_ulong_t)&adln_soc_data },
733+ { "INTC1085", (kernel_ulong_t)&adls_soc_data },
419734 { }
420735 };
421736 MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
drivers/pinctrl/intel/pinctrl-baytrail.c+53−2
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #define BYT_VAL_REG 0x008
3333 #define BYT_DFT_REG 0x00c
3434 #define BYT_INT_STAT_REG 0x800
35+#define BYT_DIRECT_IRQ_REG 0x980
3536 #define BYT_DEBOUNCE_REG 0x9d0
3637
3738 /* BYT_CONF0_REG register bits */
@@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) · 1437 unmodified lines
14751476 chip->irq_eoi(data);
14761477 }
14771478
1479+static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1480+{
1481+ int direct_irq, ioapic_direct_irq_base;
1482+ u8 *match, direct_irq_mux[16];
1483+ u32 trig;
1484+
1485+ memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1486+ sizeof(direct_irq_mux));
1487+ match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1488+ if (!match) {
1489+ dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
1490+ return false;
1491+ }
1492+
1493+ direct_irq = match - direct_irq_mux;
1494+ /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1495+ ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1496+ dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1497+ direct_irq, direct_irq + ioapic_direct_irq_base);
1498+
1499+ /*
1500+ * Testing has shown that the way direct IRQs work is that the combination of the
1501+ * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1502+ * trigger block, which normally sets the status flag in the IRQ status reg at
1503+ * 0x800, to one of the IO-APIC pins according to the mux registers.
1504+ *
1505+ * This means that:
1506+ * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1507+ * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1508+ * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1509+ * selecting edge mode operation then on the first edge the IO-APIC pin goes
1510+ * high, but since no write-to-clear write will be done to the IRQ status reg
1511+ * at 0x800, the detected edge condition will never get cleared.
1512+ */
1513+ trig = conf0 & BYT_TRIG_MASK;
1514+ if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1515+ trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1516+ dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
1517+ pin, conf0);
1518+ return false;
1519+ }
1520+
1521+ return true;
1522+}
1523+
14781524 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
14791525 unsigned long *valid_mask,
14801526 unsigned int ngpios)
@@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, · 21 unmodified lines
15021548
15031549 value = readl(reg);
15041550 if (value & BYT_DIRECT_IRQ_EN) {
1505− clear_bit(i, valid_mask);
1506− dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
1551+ if (byt_direct_irq_sanity_check(vg, i, value)) {
1552+ clear_bit(i, valid_mask);
1553+ } else {
1554+ value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1555+ BYT_TRIG_NEG | BYT_TRIG_LVL);
1556+ writel(value, reg);
1557+ }
15071558 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
15081559 byt_gpio_clear_triggering(vg, i);
15091560 dev_dbg(vg->dev, "disabling GPIO %d\n", i);
drivers/pinctrl/intel/pinctrl-icelake.c+283−8
@@ -2,7 +2,7 @@ · 1 unmodified line
22 /*
33 * Intel Ice Lake PCH pinctrl/GPIO driver
44 *
5− * Copyright (C) 2018, Intel Corporation
5+ * Copyright (C) 2018, 2022 Intel Corporation
66 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
77 * Mika Westerberg <mika.westerberg@linux.intel.com>
88 */
@@ -19,7 +19,8 @@ · 10 unmodified lines
1919 #define ICL_PADCFGLOCK 0x080
2020 #define ICL_HOSTSW_OWN 0x0b0
2121 #define ICL_GPI_IS 0x100
22−#define ICL_GPI_IE 0x110
22+#define ICL_LP_GPI_IE 0x110
23+#define ICL_N_GPI_IE 0x120
2324
2425 #define ICL_GPP(r, s, e, g) \
2526 { \
@@ -29,20 +30,26 @@ · 3 unmodified lines
2930 .gpio_base = (g), \
3031 }
3132
32−#define ICL_COMMUNITY(b, s, e, g) \
33+#define ICL_COMMUNITY(b, s, e, ie, g) \
3334 { \
3435 .barno = (b), \
3536 .padown_offset = ICL_PAD_OWN, \
3637 .padcfglock_offset = ICL_PADCFGLOCK, \
3738 .hostown_offset = ICL_HOSTSW_OWN, \
3839 .is_offset = ICL_GPI_IS, \
39− .ie_offset = ICL_GPI_IE, \
40+ .ie_offset = (ie), \
4041 .pin_base = (s), \
4142 .npins = ((e) - (s) + 1), \
4243 .gpps = (g), \
4344 .ngpps = ARRAY_SIZE(g), \
4445 }
4546
47+#define ICL_LP_COMMUNITY(b, s, e, g) \
48+ ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
49+
50+#define ICL_N_COMMUNITY(b, s, e, g) \
51+ ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
52+
4653 /* Ice Lake-LP */
4754 static const struct pinctrl_pin_desc icllp_pins[] = {
4855 /* GPP_G */
@@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = { · 280 unmodified lines
329336 };
330337
331338 static const struct intel_community icllp_communities[] = {
332− ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
333− ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
334− ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
335− ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
339+ ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
340+ ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
341+ ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
342+ ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
336343 };
337344
338345 static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
@@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = { · 64 unmodified lines
403410 .ncommunities = ARRAY_SIZE(icllp_communities),
404411 };
405412
413+/* Ice Lake-N */
414+static const struct pinctrl_pin_desc icln_pins[] = {
415+ /* SPI */
416+ PINCTRL_PIN(0, "SPI0_IO_2"),
417+ PINCTRL_PIN(1, "SPI0_IO_3"),
418+ PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
419+ PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
420+ PINCTRL_PIN(4, "SPI0_TPM_CSB"),
421+ PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
422+ PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
423+ PINCTRL_PIN(7, "SPI0_CLK"),
424+ PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
425+ /* GPP_B */
426+ PINCTRL_PIN(9, "CORE_VID_0"),
427+ PINCTRL_PIN(10, "CORE_VID_1"),
428+ PINCTRL_PIN(11, "VRALERTB"),
429+ PINCTRL_PIN(12, "CPU_GP_2"),
430+ PINCTRL_PIN(13, "CPU_GP_3"),
431+ PINCTRL_PIN(14, "SRCCLKREQB_0"),
432+ PINCTRL_PIN(15, "SRCCLKREQB_1"),
433+ PINCTRL_PIN(16, "SRCCLKREQB_2"),
434+ PINCTRL_PIN(17, "SRCCLKREQB_3"),
435+ PINCTRL_PIN(18, "SRCCLKREQB_4"),
436+ PINCTRL_PIN(19, "SRCCLKREQB_5"),
437+ PINCTRL_PIN(20, "EXT_PWR_GATEB"),
438+ PINCTRL_PIN(21, "SLP_S0B"),
439+ PINCTRL_PIN(22, "PLTRSTB"),
440+ PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
441+ PINCTRL_PIN(24, "GSPI0_CS0B"),
442+ PINCTRL_PIN(25, "GSPI0_CLK"),
443+ PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
444+ PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
445+ PINCTRL_PIN(28, "GSPI1_CS0B"),
446+ PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
447+ PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
448+ PINCTRL_PIN(31, "GSPI1_MOSI"),
449+ PINCTRL_PIN(32, "GSPI1_CS1B"),
450+ PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
451+ PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
452+ /* GPP_A */
453+ PINCTRL_PIN(35, "ESPI_IO_0"),
454+ PINCTRL_PIN(36, "ESPI_IO_1"),
455+ PINCTRL_PIN(37, "ESPI_IO_2"),
456+ PINCTRL_PIN(38, "ESPI_IO_3"),
457+ PINCTRL_PIN(39, "ESPI_CSB"),
458+ PINCTRL_PIN(40, "ESPI_CLK"),
459+ PINCTRL_PIN(41, "ESPI_RESETB"),
460+ PINCTRL_PIN(42, "SMBCLK"),
461+ PINCTRL_PIN(43, "SMBDATA"),
462+ PINCTRL_PIN(44, "SMBALERTB"),
463+ PINCTRL_PIN(45, "CPU_GP_0"),
464+ PINCTRL_PIN(46, "CPU_GP_1"),
465+ PINCTRL_PIN(47, "USB2_OCB_1"),
466+ PINCTRL_PIN(48, "USB2_OCB_2"),
467+ PINCTRL_PIN(49, "USB2_OCB_3"),
468+ PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
469+ PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
470+ PINCTRL_PIN(52, "DDSP_HPD_C"),
471+ PINCTRL_PIN(53, "USB2_OCB_0"),
472+ PINCTRL_PIN(54, "PCHHOTB"),
473+ PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
474+ /* GPP_S */
475+ PINCTRL_PIN(56, "SNDW1_CLK"),
476+ PINCTRL_PIN(57, "SNDW1_DATA"),
477+ PINCTRL_PIN(58, "SNDW2_CLK"),
478+ PINCTRL_PIN(59, "SNDW2_DATA"),
479+ PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
480+ PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
481+ PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
482+ PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
483+ /* GPP_R */
484+ PINCTRL_PIN(64, "HDA_BCLK"),
485+ PINCTRL_PIN(65, "HDA_SYNC"),
486+ PINCTRL_PIN(66, "HDA_SDO"),
487+ PINCTRL_PIN(67, "HDA_SDI_0"),
488+ PINCTRL_PIN(68, "HDA_RSTB"),
489+ PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
490+ PINCTRL_PIN(70, "I2S1_SFRM"),
491+ PINCTRL_PIN(71, "I2S1_TXD"),
492+ /* GPP_H */
493+ PINCTRL_PIN(72, "GPPC_H_0"),
494+ PINCTRL_PIN(73, "CNV_RF_RESET_B"),
495+ PINCTRL_PIN(74, "MODEM_CLKREQ"),
496+ PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
497+ PINCTRL_PIN(76, "I2C2_SDA"),
498+ PINCTRL_PIN(77, "I2C2_SCL"),
499+ PINCTRL_PIN(78, "I2C3_SDA"),
500+ PINCTRL_PIN(79, "I2C3_SCL"),
501+ PINCTRL_PIN(80, "I2C4_SDA"),
502+ PINCTRL_PIN(81, "I2C4_SCL"),
503+ PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
504+ PINCTRL_PIN(83, "I2S2_SCLK"),
505+ PINCTRL_PIN(84, "CNV_RF_RESET_B"),
506+ PINCTRL_PIN(85, "MODEM_CLKREQ"),
507+ PINCTRL_PIN(86, "I2S2_RXD"),
508+ PINCTRL_PIN(87, "I2S1_SCLK"),
509+ PINCTRL_PIN(88, "GPPC_H_16"),
510+ PINCTRL_PIN(89, "GPPC_H_17"),
511+ PINCTRL_PIN(90, "GPPC_H_18"),
512+ PINCTRL_PIN(91, "GPPC_H_19"),
513+ PINCTRL_PIN(92, "GPPC_H_20"),
514+ PINCTRL_PIN(93, "GPPC_H_21"),
515+ PINCTRL_PIN(94, "GPPC_H_22"),
516+ PINCTRL_PIN(95, "GPPC_H_23"),
517+ /* GPP_D */
518+ PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
519+ PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
520+ PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
521+ PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
522+ PINCTRL_PIN(100, "ISH_I2C0_SDA"),
523+ PINCTRL_PIN(101, "ISH_I2C0_SCL"),
524+ PINCTRL_PIN(102, "ISH_I2C1_SDA"),
525+ PINCTRL_PIN(103, "ISH_I2C1_SCL"),
526+ PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
527+ PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
528+ PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
529+ PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
530+ PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
531+ PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
532+ PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
533+ PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
534+ PINCTRL_PIN(112, "SPI1_IO_2"),
535+ PINCTRL_PIN(113, "SPI1_IO_3"),
536+ PINCTRL_PIN(114, "I2S_MCLK"),
537+ PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
538+ PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
539+ PINCTRL_PIN(117, "CNV_PA_BLANKING"),
540+ PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
541+ PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
542+ PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
543+ PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
544+ /* vGPIO */
545+ PINCTRL_PIN(122, "CNV_BTEN"),
546+ PINCTRL_PIN(123, "CNV_WCEN"),
547+ PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
548+ PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
549+ PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
550+ PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
551+ PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
552+ PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
553+ PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
554+ PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
555+ PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
556+ PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
557+ PINCTRL_PIN(134, "vUART0_TXD"),
558+ PINCTRL_PIN(135, "vUART0_RXD"),
559+ PINCTRL_PIN(136, "vUART0_CTS_B"),
560+ PINCTRL_PIN(137, "vUART0_RTS_B"),
561+ PINCTRL_PIN(138, "vISH_UART0_TXD"),
562+ PINCTRL_PIN(139, "vISH_UART0_RXD"),
563+ PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
564+ PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
565+ PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
566+ PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
567+ PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
568+ PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
569+ PINCTRL_PIN(146, "vI2S2_SCLK"),
570+ PINCTRL_PIN(147, "vI2S2_SFRM"),
571+ PINCTRL_PIN(148, "vI2S2_TXD"),
572+ PINCTRL_PIN(149, "vI2S2_RXD"),
573+ PINCTRL_PIN(150, "vSD3_CD_B"),
574+ /* GPP_C */
575+ PINCTRL_PIN(151, "GPPC_C_0"),
576+ PINCTRL_PIN(152, "GPPC_C_1"),
577+ PINCTRL_PIN(153, "GPPC_C_2"),
578+ PINCTRL_PIN(154, "GPPC_C_3"),
579+ PINCTRL_PIN(155, "GPPC_C_4"),
580+ PINCTRL_PIN(156, "GPPC_C_5"),
581+ PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
582+ PINCTRL_PIN(158, "SUSACKB"),
583+ PINCTRL_PIN(159, "UART0_RXD"),
584+ PINCTRL_PIN(160, "UART0_TXD"),
585+ PINCTRL_PIN(161, "UART0_RTSB"),
586+ PINCTRL_PIN(162, "UART0_CTSB"),
587+ PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
588+ PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
589+ PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
590+ PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
591+ PINCTRL_PIN(167, "I2C0_SDA"),
592+ PINCTRL_PIN(168, "I2C0_SCL"),
593+ PINCTRL_PIN(169, "I2C1_SDA"),
594+ PINCTRL_PIN(170, "I2C1_SCL"),
595+ PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
596+ PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
597+ PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
598+ PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
599+ /* HVCMOS */
600+ PINCTRL_PIN(175, "L_BKLTEN"),
601+ PINCTRL_PIN(176, "L_BKLTCTL"),
602+ PINCTRL_PIN(177, "L_VDDEN"),
603+ PINCTRL_PIN(178, "SYS_PWROK"),
604+ PINCTRL_PIN(179, "SYS_RESETB"),
605+ PINCTRL_PIN(180, "MLK_RSTB"),
606+ /* GPP_E */
607+ PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
608+ PINCTRL_PIN(182, "ISH_GP_1"),
609+ PINCTRL_PIN(183, "IMGCLKOUT_1"),
610+ PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
611+ PINCTRL_PIN(185, "IMGCLKOUT_2"),
612+ PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
613+ PINCTRL_PIN(187, "IMGCLKOUT_3"),
614+ PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
615+ PINCTRL_PIN(189, "FIVR_DIGPB_0"),
616+ PINCTRL_PIN(190, "SML0CLK"),
617+ PINCTRL_PIN(191, "SML0DATA"),
618+ PINCTRL_PIN(192, "BSSB_LS3_RX"),
619+ PINCTRL_PIN(193, "BSSB_LS3_TX"),
620+ PINCTRL_PIN(194, "BSSB_LS0_RX"),
621+ PINCTRL_PIN(195, "BSSB_LS0_TX"),
622+ PINCTRL_PIN(196, "BSSB_LS1_RX"),
623+ PINCTRL_PIN(197, "BSSB_LS1_TX"),
624+ PINCTRL_PIN(198, "BSSB_LS2_RX"),
625+ PINCTRL_PIN(199, "BSSB_LS2_TX"),
626+ PINCTRL_PIN(200, "FIVR_DIGPB_1"),
627+ PINCTRL_PIN(201, "CNV_BRI_DT"),
628+ PINCTRL_PIN(202, "CNV_BRI_RSP"),
629+ PINCTRL_PIN(203, "CNV_RGI_DT"),
630+ PINCTRL_PIN(204, "CNV_RGI_RSP"),
631+ /* GPP_G */
632+ PINCTRL_PIN(205, "SD3_CMD"),
633+ PINCTRL_PIN(206, "SD3_D0"),
634+ PINCTRL_PIN(207, "SD3_D1"),
635+ PINCTRL_PIN(208, "SD3_D2"),
636+ PINCTRL_PIN(209, "SD3_D3"),
637+ PINCTRL_PIN(210, "SD3_CDB"),
638+ PINCTRL_PIN(211, "SD3_CLK"),
639+ PINCTRL_PIN(212, "SD3_WP"),
640+};
641+
642+static const struct intel_padgroup icln_community0_gpps[] = {
643+ ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
644+ ICL_GPP(1, 9, 34, 32), /* GPP_B */
645+ ICL_GPP(2, 35, 55, 64), /* GPP_A */
646+ ICL_GPP(3, 56, 63, 96), /* GPP_S */
647+ ICL_GPP(4, 64, 71, 128), /* GPP_R */
648+};
649+
650+static const struct intel_padgroup icln_community1_gpps[] = {
651+ ICL_GPP(0, 72, 95, 160), /* GPP_H */
652+ ICL_GPP(1, 96, 121, 192), /* GPP_D */
653+ ICL_GPP(2, 122, 150, 224), /* vGPIO */
654+ ICL_GPP(3, 151, 174, 256), /* GPP_C */
655+};
656+
657+static const struct intel_padgroup icln_community4_gpps[] = {
658+ ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
659+ ICL_GPP(1, 181, 204, 288), /* GPP_E */
660+};
661+
662+static const struct intel_padgroup icln_community5_gpps[] = {
663+ ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
664+};
665+
666+static const struct intel_community icln_communities[] = {
667+ ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
668+ ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
669+ ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
670+ ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
671+};
672+
673+static const struct intel_pinctrl_soc_data icln_soc_data = {
674+ .pins = icln_pins,
675+ .npins = ARRAY_SIZE(icln_pins),
676+ .communities = icln_communities,
677+ .ncommunities = ARRAY_SIZE(icln_communities),
678+};
679+
406680 static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
407681
408682 static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
409683 { "INT3455", (kernel_ulong_t)&icllp_soc_data },
684+ { "INT34C3", (kernel_ulong_t)&icln_soc_data },
410685 { }
411686 };
412687 MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
drivers/pinctrl/mediatek/Kconfig+7−0
@@ -147,6 +147,13 @@ config PINCTRL_MT8183 · 146 unmodified lines
147147 default ARM64 && ARCH_MEDIATEK
148148 select PINCTRL_MTK_PARIS
149149
150+config PINCTRL_MT8186
151+ bool "Mediatek MT8186 pin control"
152+ depends on OF
153+ depends on ARM64 || COMPILE_TEST
154+ default ARM64 && ARCH_MEDIATEK
155+ select PINCTRL_MTK_PARIS
156+
150157 config PINCTRL_MT8192
151158 bool "Mediatek MT8192 pin control"
152159 depends on OF
drivers/pinctrl/mediatek/Makefile+1−0
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o · 20 unmodified lines
2121 obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
2222 obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
2323 obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
24+obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
2425 obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
2526 obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
2627 obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
drivers/pinctrl/mediatek/pinctrl-moore.c+9−16
@@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw) · 604 unmodified lines
605605 int mtk_moore_pinctrl_probe(struct platform_device *pdev,
606606 const struct mtk_pin_soc *soc)
607607 {
608+ struct device *dev = &pdev->dev;
608609 struct pinctrl_pin_desc *pins;
609610 struct mtk_pinctrl *hw;
610611 int err, i;
@@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, · 5 unmodified lines
616617 hw->soc = soc;
617618 hw->dev = &pdev->dev;
618619
619− if (!hw->soc->nbase_names) {
620− dev_err(&pdev->dev,
620+ if (!hw->soc->nbase_names)
621+ return dev_err_probe(dev, -EINVAL,
621622 "SoC should be assigned at least one register base\n");
622− return -EINVAL;
623− }
624623
625624 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
626625 sizeof(*hw->base), GFP_KERNEL);
@@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, · 38 unmodified lines
665664
666665 /* Setup groups descriptions per SoC types */
667666 err = mtk_build_groups(hw);
668− if (err) {
669− dev_err(&pdev->dev, "Failed to build groups\n");
670− return err;
671− }
667+ if (err)
668+ return dev_err_probe(dev, err, "Failed to build groups\n");
672669
673670 /* Setup functions descriptions per SoC types */
674671 err = mtk_build_functions(hw);
675− if (err) {
676− dev_err(&pdev->dev, "Failed to build functions\n");
677− return err;
678− }
672+ if (err)
673+ return dev_err_probe(dev, err, "Failed to build functions\n");
679674
680675 /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
681676 * until all groups and functions are being added one.
@@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, · 9 unmodified lines
691686
692687 /* Build gpiochip should be after pinctrl_enable is done */
693688 err = mtk_build_gpiochip(hw);
694− if (err) {
695− dev_err(&pdev->dev, "Failed to add gpio_chip\n");
696− return err;
697− }
689+ if (err)
690+ return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
698691
699692 platform_set_drvdata(pdev, hw);
700693
drivers/pinctrl/mediatek/pinctrl-mt2701.c+11−29
@@ -270,13 +270,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = { · 269 unmodified lines
270270 MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
271271 };
272272
273−static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
274− unsigned char align, bool isup, unsigned int r1r0)
275−{
276− return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
277− ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
278−}
279−
280273 static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
281274 MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
282275 MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
@@ -436,18 +429,6 @@ static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = { · 153 unmodified lines
436429 MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
437430 };
438431
439−static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
440− unsigned char align, int value, enum pin_config_param arg)
441−{
442− if (arg == PIN_CONFIG_INPUT_ENABLE)
443− return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
444− ARRAY_SIZE(mt2701_ies_set), pin, align, value);
445− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
446− return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
447− ARRAY_SIZE(mt2701_smt_set), pin, align, value);
448− return -EINVAL;
449−}
450−
451432 static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
452433 MTK_PINMUX_SPEC(22, 0xb10, 3),
453434 MTK_PINMUX_SPEC(23, 0xb10, 4),
@@ -508,8 +489,14 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { · 54 unmodified lines
508489 .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
509490 .pin_drv_grp = mt2701_pin_drv,
510491 .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
511− .spec_pull_set = mt2701_spec_pull_set,
512− .spec_ies_smt_set = mt2701_ies_smt_set,
492+ .spec_ies = mt2701_ies_set,
493+ .n_spec_ies = ARRAY_SIZE(mt2701_ies_set),
494+ .spec_pupd = mt2701_spec_pupd,
495+ .n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd),
496+ .spec_smt = mt2701_smt_set,
497+ .n_spec_smt = ARRAY_SIZE(mt2701_smt_set),
498+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
499+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
513500 .spec_pinmux_set = mt2701_spec_pinmux_set,
514501 .spec_dir_set = mt2701_spec_dir_set,
515502 .dir_offset = 0x0000,
@@ -534,20 +521,15 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { · 18 unmodified lines
534521 },
535522 };
536523
537−static int mt2701_pinctrl_probe(struct platform_device *pdev)
538−{
539− return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
540−}
541−
542524 static const struct of_device_id mt2701_pctrl_match[] = {
543− { .compatible = "mediatek,mt2701-pinctrl", },
544− { .compatible = "mediatek,mt7623-pinctrl", },
525+ { .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data },
526+ { .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data },
545527 {}
546528 };
547529 MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
548530
549531 static struct platform_driver mtk_pinctrl_driver = {
550− .probe = mt2701_pinctrl_probe,
532+ .probe = mtk_pctrl_common_probe,
551533 .driver = {
552534 .name = "mediatek-mt2701-pinctrl",
553535 .of_match_table = mt2701_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt2712.c+10−34
@@ -81,16 +81,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = { · 80 unmodified lines
8181 MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
8282 };
8383
84−static int mt2712_spec_pull_set(struct regmap *regmap,
85− unsigned int pin,
86− unsigned char align,
87− bool isup,
88− unsigned int r1r0)
89−{
90− return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
91− ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
92−}
93−
9484 static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
9585 MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
9686 MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
@@ -285,19 +275,6 @@ static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = { · 188 unmodified lines
285275 MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
286276 };
287277
288−static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
289− unsigned char align,
290− int value, enum pin_config_param arg)
291−{
292− if (arg == PIN_CONFIG_INPUT_ENABLE)
293− return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
294− ARRAY_SIZE(mt2712_ies_set), pin, align, value);
295− if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
296− return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
297− ARRAY_SIZE(mt2712_smt_set), pin, align, value);
298− return -EINVAL;
299−}
300−
301278 static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
302279 /* 0E4E8SR 4/8/12/16 */
303280 MTK_DRV_GRP(4, 16, 1, 2, 4),
@@ -563,8 +540,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { · 259 unmodified lines
563540 .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
564541 .pin_drv_grp = mt2712_pin_drv,
565542 .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
566− .spec_pull_set = mt2712_spec_pull_set,
567− .spec_ies_smt_set = mt2712_ies_smt_set,
543+ .spec_ies = mt2712_ies_set,
544+ .n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
545+ .spec_pupd = mt2712_spec_pupd,
546+ .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
547+ .spec_smt = mt2712_smt_set,
548+ .n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
549+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
550+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
568551 .dir_offset = 0x0000,
569552 .pullen_offset = 0x0100,
570553 .pullsel_offset = 0x0200,
@@ -587,21 +570,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { · 16 unmodified lines
587570 },
588571 };
589572
590−static int mt2712_pinctrl_probe(struct platform_device *pdev)
591−{
592− return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
593−}
594−
595573 static const struct of_device_id mt2712_pctrl_match[] = {
596− {
597− .compatible = "mediatek,mt2712-pinctrl",
598− },
574+ { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
599575 { }
600576 };
601577 MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
602578
603579 static struct platform_driver mtk_pinctrl_driver = {
604− .probe = mt2712_pinctrl_probe,
580+ .probe = mtk_pctrl_common_probe,
605581 .driver = {
606582 .name = "mediatek-mt2712-pinctrl",
607583 .of_match_table = mt2712_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt6765.c+2−7
@@ -1082,21 +1082,16 @@ static const struct mtk_pin_soc mt6765_data = { · 1081 unmodified lines
10821082 };
10831083
10841084 static const struct of_device_id mt6765_pinctrl_of_match[] = {
1085− { .compatible = "mediatek,mt6765-pinctrl", },
1085+ { .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data },
10861086 { }
10871087 };
10881088
1089−static int mt6765_pinctrl_probe(struct platform_device *pdev)
1090−{
1091− return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
1092−}
1093−
10941089 static struct platform_driver mt6765_pinctrl_driver = {
10951090 .driver = {
10961091 .name = "mt6765-pinctrl",
10971092 .of_match_table = mt6765_pinctrl_of_match,
10981093 },
1099− .probe = mt6765_pinctrl_probe,
1094+ .probe = mtk_paris_pinctrl_probe,
11001095 };
11011096
11021097 static int __init mt6765_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt6779.c+2−7
@@ -758,21 +758,16 @@ static const struct mtk_pin_soc mt6779_data = { · 757 unmodified lines
758758 };
759759
760760 static const struct of_device_id mt6779_pinctrl_of_match[] = {
761− { .compatible = "mediatek,mt6779-pinctrl", },
761+ { .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data },
762762 { }
763763 };
764764
765−static int mt6779_pinctrl_probe(struct platform_device *pdev)
766−{
767− return mtk_paris_pinctrl_probe(pdev, &mt6779_data);
768−}
769−
770765 static struct platform_driver mt6779_pinctrl_driver = {
771766 .driver = {
772767 .name = "mt6779-pinctrl",
773768 .of_match_table = mt6779_pinctrl_of_match,
774769 },
775− .probe = mt6779_pinctrl_probe,
770+ .probe = mtk_paris_pinctrl_probe,
776771 };
777772
778773 static int __init mt6779_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt6797.c+2−7
@@ -58,21 +58,16 @@ static const struct mtk_pin_soc mt6797_data = { · 57 unmodified lines
5858 };
5959
6060 static const struct of_device_id mt6797_pinctrl_of_match[] = {
61− { .compatible = "mediatek,mt6797-pinctrl", },
61+ { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data },
6262 { }
6363 };
6464
65−static int mt6797_pinctrl_probe(struct platform_device *pdev)
66−{
67− return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
68−}
69−
7065 static struct platform_driver mt6797_pinctrl_driver = {
7166 .driver = {
7267 .name = "mt6797-pinctrl",
7368 .of_match_table = mt6797_pinctrl_of_match,
7469 },
75− .probe = mt6797_pinctrl_probe,
70+ .probe = mtk_paris_pinctrl_probe,
7671 };
7772
7873 static int __init mt6797_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt8127.c+10−29
@@ -172,13 +172,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { · 171 unmodified lines
172172 MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
173173 };
174174
175−static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
176− unsigned char align, bool isup, unsigned int r1r0)
177−{
178− return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
179− ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
180−}
181−
182175 static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
183176 MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
184177 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
@@ -259,19 +252,6 @@ static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { · 74 unmodified lines
259252 MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
260253 };
261254
262−static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
263− unsigned char align, int value, enum pin_config_param arg)
264−{
265− if (arg == PIN_CONFIG_INPUT_ENABLE)
266− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
267− ARRAY_SIZE(mt8127_ies_set), pin, align, value);
268− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
269− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
270− ARRAY_SIZE(mt8127_smt_set), pin, align, value);
271− return -EINVAL;
272−}
273−
274−
275255 static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
276256 .pins = mtk_pins_mt8127,
277257 .npins = ARRAY_SIZE(mtk_pins_mt8127),
@@ -279,8 +259,14 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { · 1 unmodified line
279259 .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
280260 .pin_drv_grp = mt8127_pin_drv,
281261 .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
282− .spec_pull_set = mt8127_spec_pull_set,
283− .spec_ies_smt_set = mt8127_ies_smt_set,
262+ .spec_ies = mt8127_ies_set,
263+ .n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
264+ .spec_pupd = mt8127_spec_pupd,
265+ .n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
266+ .spec_smt = mt8127_smt_set,
267+ .n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
268+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
269+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
284270 .dir_offset = 0x0000,
285271 .pullen_offset = 0x0100,
286272 .pullsel_offset = 0x0200,
@@ -303,18 +289,13 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { · 16 unmodified lines
303289 },
304290 };
305291
306−static int mt8127_pinctrl_probe(struct platform_device *pdev)
307−{
308− return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
309−}
310−
311292 static const struct of_device_id mt8127_pctrl_match[] = {
312− { .compatible = "mediatek,mt8127-pinctrl", },
293+ { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
313294 { }
314295 };
315296
316297 static struct platform_driver mtk_pinctrl_driver = {
317− .probe = mt8127_pinctrl_probe,
298+ .probe = mtk_pctrl_common_probe,
318299 .driver = {
319300 .name = "mediatek-mt8127-pinctrl",
320301 .of_match_table = mt8127_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt8135.c+6−11
@@ -230,12 +230,14 @@ static const struct mtk_spec_pull_set spec_pupd[] = { · 229 unmodified lines
230230 SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
231231 };
232232
233−static int spec_pull_set(struct regmap *regmap, unsigned int pin,
234− unsigned char align, bool isup, unsigned int r1r0)
233+static int spec_pull_set(struct regmap *regmap,
234+ const struct mtk_pinctrl_devdata *devdata,
235+ unsigned int pin, bool isup, unsigned int r1r0)
235236 {
236237 unsigned int i;
237238 unsigned int reg_pupd, reg_set_r0, reg_set_r1;
238239 unsigned int reg_rst_r0, reg_rst_r1;
240+ unsigned char align = devdata->port_align;
239241 bool find = false;
240242
241243 for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
@@ -316,20 +318,13 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { · 74 unmodified lines
316318 },
317319 };
318320
319−static int mt8135_pinctrl_probe(struct platform_device *pdev)
320−{
321− return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
322−}
323−
324321 static const struct of_device_id mt8135_pctrl_match[] = {
325− {
326− .compatible = "mediatek,mt8135-pinctrl",
327− },
322+ { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
328323 { }
329324 };
330325
331326 static struct platform_driver mtk_pinctrl_driver = {
332− .probe = mt8135_pinctrl_probe,
327+ .probe = mtk_pctrl_common_probe,
333328 .driver = {
334329 .name = "mediatek-mt8135-pinctrl",
335330 .of_match_table = mt8135_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt8167.c+10−30
@@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = { · 185 unmodified lines
186186 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
187187 };
188188
189−static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
190− unsigned char align, bool isup, unsigned int r1r0)
191−{
192− return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
193− ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
194−}
195−
196189 static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
197190 MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
198191 MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
@@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { · 93 unmodified lines
292285 MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
293286 };
294287
295−static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
296− unsigned char align, int value, enum pin_config_param arg)
297−{
298− if (arg == PIN_CONFIG_INPUT_ENABLE)
299− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
300− ARRAY_SIZE(mt8167_ies_set), pin, align, value);
301− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
302− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
303− ARRAY_SIZE(mt8167_smt_set), pin, align, value);
304− return -EINVAL;
305−}
306−
307288 static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
308289 .pins = mtk_pins_mt8167,
309290 .npins = ARRAY_SIZE(mtk_pins_mt8167),
@@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { · 1 unmodified line
311292 .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
312293 .pin_drv_grp = mt8167_pin_drv,
313294 .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
314− .spec_pull_set = mt8167_spec_pull_set,
315− .spec_ies_smt_set = mt8167_ies_smt_set,
295+ .spec_ies = mt8167_ies_set,
296+ .n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
297+ .spec_pupd = mt8167_spec_pupd,
298+ .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
299+ .spec_smt = mt8167_smt_set,
300+ .n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
301+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
302+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
316303 .dir_offset = 0x0000,
317304 .pullen_offset = 0x0500,
318305 .pullsel_offset = 0x0600,
@@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { · 16 unmodified lines
335322 },
336323 };
337324
338−static int mt8167_pinctrl_probe(struct platform_device *pdev)
339−{
340− return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
341−}
342−
343325 static const struct of_device_id mt8167_pctrl_match[] = {
344− {
345− .compatible = "mediatek,mt8167-pinctrl",
346− },
326+ { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
347327 {}
348328 };
349329
350330 MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
351331
352332 static struct platform_driver mtk_pinctrl_driver = {
353− .probe = mt8167_pinctrl_probe,
333+ .probe = mtk_pctrl_common_probe,
354334 .driver = {
355335 .name = "mediatek-mt8167-pinctrl",
356336 .of_match_table = mt8167_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt8173.c+8−21
@@ -61,13 +61,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { · 60 unmodified lines
6161 MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
6262 };
6363
64−static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
65− unsigned char align, bool isup, unsigned int r1r0)
66−{
67− return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
68− ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
69−}
70−
7164 static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
7265 MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
7366 MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
@@ -174,18 +167,6 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { · 100 unmodified lines
174167 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
175168 };
176169
177−static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
178− unsigned char align, int value, enum pin_config_param arg)
179−{
180− if (arg == PIN_CONFIG_INPUT_ENABLE)
181− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
182− ARRAY_SIZE(mt8173_ies_set), pin, align, value);
183− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
184− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
185− ARRAY_SIZE(mt8173_smt_set), pin, align, value);
186− return -EINVAL;
187−}
188−
189170 static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
190171 /* 0E4E8SR 4/8/12/16 */
191172 MTK_DRV_GRP(4, 16, 1, 2, 4),
@@ -319,8 +300,14 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { · 127 unmodified lines
319300 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
320301 .pin_drv_grp = mt8173_pin_drv,
321302 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
322− .spec_pull_set = mt8173_spec_pull_set,
323− .spec_ies_smt_set = mt8173_ies_smt_set,
303+ .spec_ies = mt8173_ies_set,
304+ .n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
305+ .spec_pupd = mt8173_spec_pupd,
306+ .n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
307+ .spec_smt = mt8173_smt_set,
308+ .n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
309+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
310+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
324311 .dir_offset = 0x0000,
325312 .pullen_offset = 0x0100,
326313 .pullsel_offset = 0x0200,
drivers/pinctrl/mediatek/pinctrl-mt8183.c+2−7
@@ -567,22 +567,17 @@ static const struct mtk_pin_soc mt8183_data = { · 566 unmodified lines
567567 };
568568
569569 static const struct of_device_id mt8183_pinctrl_of_match[] = {
570− { .compatible = "mediatek,mt8183-pinctrl", },
570+ { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data },
571571 { }
572572 };
573573
574−static int mt8183_pinctrl_probe(struct platform_device *pdev)
575−{
576− return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
577−}
578−
579574 static struct platform_driver mt8183_pinctrl_driver = {
580575 .driver = {
581576 .name = "mt8183-pinctrl",
582577 .of_match_table = mt8183_pinctrl_of_match,
583578 .pm = &mtk_paris_pinctrl_pm_ops,
584579 },
585− .probe = mt8183_pinctrl_probe,
580+ .probe = mtk_paris_pinctrl_probe,
586581 };
587582
588583 static int __init mt8183_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt8186.c+1267−0
@@ -0,0 +1,1267 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (C) 2021 MediaTek Inc.
4+ *
5+ * Author: Guodong Liu <guodong.liu@mediatek.com>
6+ *
7+ */
8+
9+#include "pinctrl-mtk-mt8186.h"
10+#include "pinctrl-paris.h"
11+
12+/* MT8186 have multiple bases to program pin configuration listed as the below:
13+ * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
14+ * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
15+ * iocfg[6]:0x10002C00.
16+ * _i_based could be used to indicate what base the pin should be mapped into.
17+ */
18+
19+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
20+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
21+
22+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
23+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1)
24+
25+static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = {
26+ PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
27+};
28+
29+static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = {
30+ PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
31+};
32+
33+static const struct mtk_pin_field_calc mt8186_pin_di_range[] = {
34+ PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
35+};
36+
37+static const struct mtk_pin_field_calc mt8186_pin_do_range[] = {
38+ PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
39+};
40+
41+static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = {
42+ PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
43+ PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
44+ PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1),
45+ PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1),
46+ PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1),
47+ PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1),
48+ PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1),
49+ PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1),
50+ PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1),
51+ PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1),
52+ PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1),
53+ PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1),
54+ PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1),
55+ PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1),
56+ PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1),
57+ PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1),
58+ PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1),
59+ PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1),
60+ PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1),
61+ PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1),
62+ PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1),
63+ PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1),
64+ PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1),
65+ PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1),
66+ PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1),
67+ PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1),
68+ PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1),
69+ PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1),
70+ PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1),
71+ PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1),
72+ PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1),
73+ PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1),
74+ PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1),
75+ PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1),
76+ PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1),
77+ PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1),
78+ PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1),
79+ PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1),
80+ PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1),
81+ PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1),
82+ PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1),
83+ PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1),
84+ PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1),
85+ PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1),
86+ PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1),
87+ PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1),
88+ PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1),
89+ PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1),
90+ PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1),
91+ PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1),
92+ PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1),
93+ PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1),
94+ PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1),
95+ PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1),
96+ PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1),
97+ PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1),
98+ PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1),
99+ PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1),
100+ PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1),
101+ PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1),
102+ PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1),
103+ PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1),
104+ PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1),
105+ PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1),
106+ PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1),
107+ PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1),
108+ PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1),
109+ PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1),
110+ PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1),
111+ PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1),
112+ PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1),
113+ PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1),
114+ PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1),
115+ PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1),
116+ PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1),
117+ PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1),
118+ PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1),
119+ PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1),
120+ PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1),
121+ PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1),
122+ PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1),
123+ PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1),
124+ PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1),
125+ PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1),
126+ PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1),
127+ PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1),
128+ PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1),
129+ PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1),
130+ PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1),
131+ PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1),
132+ PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1),
133+ PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1),
134+ PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1),
135+ PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1),
136+ PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1),
137+ PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1),
138+ PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1),
139+ PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1),
140+ PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1),
141+ PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1),
142+ PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1),
143+ PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1),
144+ PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1),
145+ PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1),
146+ PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1),
147+ PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1),
148+ PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1),
149+ PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1),
150+ PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1),
151+ PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1),
152+ PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1),
153+ PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1),
154+ PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1),
155+ PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1),
156+ PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1),
157+ PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1),
158+ PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1),
159+ PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1),
160+ PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1),
161+ PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1),
162+ PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1),
163+ PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1),
164+ PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1),
165+ PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1),
166+ PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1),
167+ PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1),
168+ PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1),
169+ PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1),
170+ PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1),
171+ PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1),
172+ PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1),
173+ PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1),
174+ PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1),
175+ PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1),
176+ PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1),
177+ PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1),
178+ PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1),
179+ PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1),
180+ PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1),
181+ PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1),
182+ PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1),
183+ PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1),
184+ PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1),
185+ PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1),
186+ PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1),
187+ PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1),
188+ PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1),
189+ PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1),
190+ PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1),
191+ PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1),
192+ PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1),
193+ PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1),
194+ PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1),
195+ PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1),
196+ PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1),
197+ PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1),
198+ PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1),
199+ PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1),
200+ PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1),
201+ PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1),
202+ PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1),
203+ PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1),
204+ PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1),
205+ PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1),
206+ PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1),
207+ PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1),
208+ PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1),
209+ PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1),
210+ PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1),
211+ PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1),
212+ PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1),
213+ PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1),
214+ PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1),
215+ PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1),
216+ PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1),
217+ PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1),
218+ PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1),
219+ PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1),
220+ PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1),
221+ PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1),
222+ PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1),
223+ PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1),
224+ PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1),
225+ PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1),
226+ PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1),
227+};
228+
229+static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = {
230+ PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1),
231+ PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1),
232+ PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1),
233+ PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1),
234+ PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1),
235+ PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1),
236+ PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1),
237+ PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1),
238+ PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1),
239+ PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1),
240+ PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1),
241+ PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1),
242+ PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1),
243+ PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1),
244+ PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1),
245+ PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1),
246+ PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1),
247+ PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1),
248+ PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1),
249+ PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1),
250+ PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1),
251+ PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1),
252+ PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1),
253+ PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1),
254+ PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1),
255+ PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1),
256+ PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1),
257+ PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1),
258+ PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1),
259+ PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1),
260+ PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
261+ PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1),
262+ PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1),
263+ PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1),
264+ PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1),
265+ PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1),
266+ PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1),
267+ PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1),
268+ PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1),
269+ PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1),
270+ PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1),
271+ PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1),
272+ PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1),
273+ PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1),
274+ PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1),
275+ PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1),
276+ PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1),
277+ PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1),
278+ PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1),
279+ PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1),
280+ PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1),
281+ PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1),
282+ PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1),
283+ PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1),
284+ PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1),
285+ PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1),
286+ PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1),
287+ PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1),
288+ PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1),
289+ PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1),
290+ PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1),
291+ PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
292+ PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1),
293+ PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1),
294+ PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1),
295+ PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1),
296+ PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1),
297+ PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1),
298+ PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1),
299+ PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
300+ PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1),
301+ PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1),
302+ PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1),
303+ PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1),
304+ PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1),
305+ PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1),
306+ PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1),
307+ PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1),
308+ PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1),
309+ PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1),
310+ PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1),
311+ PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1),
312+ PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1),
313+ PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1),
314+ PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1),
315+ PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1),
316+ PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1),
317+ PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1),
318+ PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1),
319+ PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1),
320+ PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1),
321+ PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1),
322+ PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1),
323+ PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1),
324+ PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1),
325+ PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1),
326+ PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1),
327+ PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1),
328+ PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1),
329+ PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1),
330+ PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1),
331+ PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1),
332+ PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1),
333+ PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1),
334+ PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1),
335+ PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1),
336+ PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1),
337+ PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1),
338+ PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1),
339+ PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1),
340+ PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1),
341+ PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1),
342+ PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1),
343+ PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1),
344+ PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1),
345+ PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1),
346+ PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1),
347+ PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1),
348+ PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1),
349+ PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1),
350+ PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1),
351+ PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1),
352+ PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1),
353+ PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1),
354+ PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1),
355+ PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1),
356+ PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1),
357+ PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1),
358+ PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1),
359+ PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1),
360+ PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1),
361+ PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1),
362+ PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1),
363+ PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1),
364+ PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1),
365+ PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1),
366+ PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1),
367+ PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1),
368+ PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1),
369+ PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1),
370+ PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1),
371+ PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1),
372+ PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1),
373+ PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1),
374+ PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1),
375+ PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1),
376+ PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1),
377+ PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1),
378+ PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1),
379+ PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1),
380+ PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1),
381+ PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1),
382+ PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1),
383+ PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1),
384+ PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1),
385+ PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1),
386+ PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1),
387+ PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1),
388+ PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1),
389+ PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1),
390+ PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1),
391+ PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1),
392+ PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1),
393+ PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1),
394+ PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1),
395+ PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1),
396+ PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1),
397+ PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1),
398+ PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1),
399+ PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1),
400+ PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1),
401+ PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1),
402+ PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1),
403+ PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1),
404+ PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
405+ PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1),
406+ PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1),
407+ PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1),
408+ PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1),
409+ PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1),
410+ PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1),
411+ PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1),
412+ PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1),
413+ PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1),
414+ PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1),
415+};
416+
417+static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = {
418+ PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1),
419+ PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1),
420+ PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1),
421+ PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1),
422+ PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1),
423+ PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1),
424+ PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1),
425+ PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1),
426+ PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1),
427+ PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1),
428+ PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1),
429+ PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1),
430+ PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1),
431+ PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1),
432+ PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1),
433+ PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1),
434+ PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1),
435+ PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1),
436+ PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1),
437+ PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1),
438+ PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1),
439+ PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1),
440+ PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1),
441+ PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1),
442+ PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1),
443+ PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1),
444+ PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1),
445+ PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1),
446+ PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1),
447+ PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
448+ PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
449+ PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1),
450+ PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1),
451+ PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1),
452+ PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1),
453+ PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1),
454+ PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1),
455+ PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1),
456+ PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1),
457+ PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1),
458+ PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1),
459+ PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1),
460+ PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1),
461+ PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1),
462+ PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1),
463+ PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1),
464+ PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1),
465+ PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1),
466+ PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1),
467+ PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1),
468+ PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1),
469+ PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1),
470+ PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1),
471+ PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1),
472+ PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1),
473+ PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1),
474+ PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1),
475+ PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1),
476+ PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1),
477+ PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1),
478+ PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1),
479+ PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1),
480+ PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1),
481+ PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1),
482+ PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1),
483+ PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1),
484+ PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1),
485+ PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1),
486+ PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1),
487+ PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1),
488+ PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1),
489+ PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1),
490+ PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1),
491+ PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1),
492+ PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1),
493+ PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1),
494+ PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1),
495+ PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1),
496+ PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1),
497+ PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1),
498+ PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1),
499+ PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1),
500+ PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1),
501+ PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1),
502+ PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1),
503+ PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1),
504+ PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1),
505+ PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1),
506+ PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1),
507+ PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1),
508+ PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1),
509+ PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1),
510+ PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1),
511+ PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1),
512+ PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1),
513+ PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1),
514+ PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1),
515+ PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1),
516+ PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1),
517+ PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1),
518+ PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1),
519+ PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1),
520+ PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1),
521+ PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1),
522+ PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1),
523+ PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1),
524+ PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1),
525+ PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1),
526+ PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1),
527+ PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1),
528+ PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1),
529+ PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1),
530+ PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
531+ PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1),
532+ PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1),
533+ PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1),
534+ PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1),
535+ PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1),
536+ PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1),
537+ PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1),
538+ PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1),
539+ PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1),
540+ PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1),
541+ PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1),
542+ PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1),
543+ PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1),
544+ PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1),
545+ PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1),
546+ PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1),
547+ PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1),
548+ PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1),
549+ PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1),
550+ PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1),
551+ PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1),
552+ PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1),
553+ PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1),
554+ PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1),
555+ PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1),
556+ PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1),
557+ PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1),
558+ PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1),
559+ PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1),
560+ PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1),
561+ PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1),
562+ PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1),
563+ PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1),
564+ PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1),
565+ PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1),
566+ PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1),
567+ PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1),
568+ PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1),
569+ PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1),
570+ PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1),
571+ PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1),
572+ PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1),
573+ PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1),
574+ PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1),
575+ PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1),
576+ PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1),
577+ PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1),
578+ PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1),
579+ PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1),
580+ PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1),
581+};
582+
583+static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = {
584+ PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1),
585+ PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1),
586+ PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1),
587+ PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1),
588+ PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1),
589+ PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1),
590+ PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1),
591+ PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1),
592+ PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1),
593+ PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1),
594+ PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1),
595+ PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1),
596+ PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1),
597+ PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1),
598+ PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1),
599+ PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
600+ PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1),
601+ PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1),
602+ PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1),
603+ PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1),
604+ PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1),
605+ PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1),
606+ PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1),
607+ PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1),
608+ PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1),
609+ PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1),
610+ PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1),
611+ PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1),
612+ PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1),
613+ PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1),
614+ PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1),
615+ PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1),
616+ PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1),
617+ PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1),
618+ PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1),
619+ PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1),
620+ PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1),
621+ PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1),
622+ PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1),
623+ PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1),
624+ PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1),
625+ PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1),
626+ PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1),
627+ PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1),
628+ PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1),
629+ PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1),
630+ PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1),
631+ PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1),
632+ PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1),
633+ PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1),
634+ PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1),
635+ PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1),
636+ PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1),
637+ PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1),
638+ PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1),
639+ PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1),
640+ PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1),
641+ PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1),
642+ PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1),
643+ PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1),
644+ PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1),
645+ PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1),
646+ PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1),
647+ PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1),
648+ PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1),
649+ PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1),
650+ PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1),
651+ PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1),
652+ PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1),
653+ PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1),
654+ PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1),
655+ PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1),
656+ PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1),
657+ PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1),
658+ PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1),
659+ PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1),
660+ PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1),
661+ PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1),
662+ PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1),
663+ PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1),
664+ PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1),
665+ PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1),
666+ PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1),
667+ PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1),
668+ PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1),
669+ PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1),
670+ PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1),
671+ PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1),
672+ PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1),
673+ PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1),
674+ PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1),
675+ PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1),
676+ PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1),
677+ PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1),
678+ PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1),
679+ PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1),
680+ PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1),
681+ PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1),
682+ PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1),
683+ PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1),
684+ PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1),
685+ PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1),
686+ PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1),
687+ PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1),
688+ PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1),
689+ PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1),
690+ PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1),
691+ PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1),
692+ PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1),
693+ PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1),
694+ PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1),
695+ PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1),
696+ PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1),
697+ PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1),
698+ PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1),
699+ PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1),
700+ PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1),
701+ PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1),
702+ PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1),
703+ PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1),
704+ PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1),
705+ PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1),
706+ PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1),
707+ PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1),
708+ PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1),
709+ PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1),
710+ PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1),
711+ PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1),
712+ PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1),
713+ PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1),
714+ PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1),
715+ PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1),
716+ PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1),
717+ PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1),
718+ PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1),
719+ PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1),
720+ PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1),
721+ PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1),
722+ PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1),
723+ PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1),
724+ PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1),
725+ PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1),
726+ PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1),
727+ PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1),
728+ PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1),
729+ PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1),
730+ PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1),
731+ PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1),
732+ PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1),
733+ PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1),
734+ PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1),
735+ PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1),
736+ PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1),
737+ PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1),
738+ PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1),
739+ PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1),
740+ PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1),
741+ PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1),
742+ PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1),
743+ PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1),
744+ PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1),
745+ PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1),
746+ PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1),
747+};
748+
749+static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = {
750+ PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1),
751+ PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1),
752+ PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1),
753+ PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1),
754+ PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1),
755+ PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1),
756+ PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1),
757+ PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1),
758+ PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1),
759+ PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1),
760+ PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1),
761+ PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1),
762+ PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1),
763+ PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1),
764+ PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1),
765+ PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1),
766+ PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1),
767+ PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1),
768+ PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1),
769+ PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1),
770+ PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1),
771+ PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1),
772+};
773+
774+static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = {
775+ PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1),
776+ PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1),
777+ PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1),
778+ PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1),
779+ PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1),
780+ PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1),
781+ PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1),
782+ PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1),
783+ PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1),
784+ PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1),
785+ PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1),
786+ PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1),
787+ PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1),
788+ PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1),
789+ PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1),
790+ PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1),
791+ PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1),
792+ PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1),
793+ PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1),
794+ PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
795+ PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
796+ PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
797+};
798+
799+static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = {
800+ PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1),
801+ PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1),
802+ PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1),
803+ PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1),
804+ PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1),
805+ PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1),
806+ PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1),
807+ PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1),
808+ PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1),
809+ PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1),
810+ PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1),
811+ PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1),
812+ PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1),
813+ PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1),
814+ PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1),
815+ PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1),
816+ PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1),
817+ PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1),
818+ PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1),
819+ PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1),
820+ PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1),
821+ PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1),
822+};
823+
824+static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = {
825+ PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3),
826+ PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3),
827+ PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3),
828+ PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3),
829+ PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3),
830+ PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3),
831+ PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3),
832+ PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3),
833+ PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3),
834+ PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3),
835+ PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3),
836+ PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3),
837+ PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3),
838+ PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3),
839+ PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3),
840+ PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3),
841+ PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3),
842+ PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3),
843+ PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3),
844+ PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3),
845+ PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3),
846+ PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3),
847+ PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3),
848+ PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3),
849+ PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3),
850+ PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3),
851+ PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3),
852+ PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3),
853+ PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3),
854+ PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
855+ PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3),
856+ PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
857+ PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3),
858+ PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3),
859+ PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3),
860+ PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3),
861+ PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3),
862+ PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3),
863+ PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3),
864+ PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3),
865+ PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3),
866+ PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3),
867+ PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3),
868+ PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
869+ PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3),
870+ PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3),
871+ PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3),
872+ PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3),
873+ PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3),
874+ PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3),
875+ PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3),
876+ PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3),
877+ PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3),
878+ PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3),
879+ PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3),
880+ PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3),
881+ PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3),
882+ PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3),
883+ PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3),
884+ PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3),
885+ PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3),
886+ PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3),
887+ PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3),
888+ PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3),
889+ PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3),
890+ PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3),
891+ PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3),
892+ PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3),
893+ PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3),
894+ PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3),
895+ PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3),
896+ PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3),
897+ PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3),
898+ PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3),
899+ PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3),
900+ PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3),
901+ PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3),
902+ PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3),
903+ PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3),
904+ PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3),
905+ PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3),
906+ PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3),
907+ PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3),
908+ PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3),
909+ PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3),
910+ PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3),
911+ PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3),
912+ PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3),
913+ PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3),
914+ PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3),
915+ PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3),
916+ PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3),
917+ PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3),
918+ PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3),
919+ PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3),
920+ PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3),
921+ PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3),
922+ PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3),
923+ PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3),
924+ PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3),
925+ PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3),
926+ PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3),
927+ PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3),
928+ PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3),
929+ PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3),
930+ PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3),
931+ PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3),
932+ PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3),
933+ PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3),
934+ PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3),
935+ PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3),
936+ PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3),
937+ PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3),
938+ PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3),
939+ PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3),
940+ PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3),
941+ PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3),
942+ PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3),
943+ PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3),
944+ PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3),
945+ PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3),
946+ PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3),
947+ PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3),
948+ PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3),
949+ PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3),
950+ PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3),
951+ PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3),
952+ PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3),
953+ PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3),
954+ PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3),
955+ PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3),
956+ PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3),
957+ PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3),
958+ PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3),
959+ PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3),
960+ PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3),
961+ PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3),
962+ PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3),
963+ PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3),
964+ PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3),
965+ PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3),
966+ PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3),
967+ PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3),
968+ PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3),
969+ PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3),
970+ PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3),
971+ PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3),
972+ PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3),
973+ PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3),
974+ PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3),
975+ PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3),
976+ PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3),
977+ PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3),
978+ PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3),
979+ PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3),
980+ PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3),
981+ PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3),
982+ PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3),
983+ PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3),
984+ PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3),
985+ PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3),
986+ PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3),
987+ PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3),
988+ PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3),
989+ PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3),
990+ PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3),
991+ PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3),
992+ PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3),
993+ PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3),
994+ PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3),
995+ PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3),
996+ PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3),
997+ PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3),
998+ PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
999+ PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
1000+ PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3),
1001+ PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3),
1002+ PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3),
1003+ PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3),
1004+ PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3),
1005+ PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3),
1006+ PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3),
1007+ PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3),
1008+ PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3),
1009+};
1010+
1011+static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = {
1012+ PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3),
1013+ PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3),
1014+ PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3),
1015+ PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3),
1016+ PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3),
1017+ PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3),
1018+ PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3),
1019+ PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3),
1020+ PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3),
1021+ PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3),
1022+ PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3),
1023+ PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3),
1024+ PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3),
1025+ PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3),
1026+ PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3),
1027+ PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3),
1028+ PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3),
1029+ PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3),
1030+ PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3),
1031+ PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3),
1032+};
1033+
1034+static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = {
1035+ PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2),
1036+ PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2),
1037+ PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2),
1038+ PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2),
1039+ PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2),
1040+ PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2),
1041+ PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2),
1042+ PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2),
1043+ PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2),
1044+ PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2),
1045+ PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2),
1046+ PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2),
1047+ PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2),
1048+ PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2),
1049+ PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2),
1050+ PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2),
1051+ PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2),
1052+ PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2),
1053+ PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2),
1054+ PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2),
1055+};
1056+
1057+static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = {
1058+ PIN_RSEL(127, 128, 0x0, 75000, 75000),
1059+ PIN_RSEL(127, 128, 0x1, 10000, 75000),
1060+ PIN_RSEL(127, 128, 0x2, 5000, 5000),
1061+ PIN_RSEL(127, 128, 0x3, 1000, 5000),
1062+ PIN_RSEL(129, 130, 0x0, 75000, 75000),
1063+ PIN_RSEL(129, 130, 0x1, 10000, 75000),
1064+ PIN_RSEL(129, 130, 0x2, 5000, 5000),
1065+ PIN_RSEL(129, 130, 0x3, 1000, 5000),
1066+ PIN_RSEL(131, 132, 0x0, 75000, 75000),
1067+ PIN_RSEL(131, 132, 0x1, 10000, 75000),
1068+ PIN_RSEL(131, 132, 0x2, 5000, 5000),
1069+ PIN_RSEL(131, 132, 0x3, 1000, 5000),
1070+ PIN_RSEL(133, 134, 0x0, 75000, 75000),
1071+ PIN_RSEL(133, 134, 0x1, 10000, 75000),
1072+ PIN_RSEL(133, 134, 0x2, 5000, 5000),
1073+ PIN_RSEL(133, 134, 0x3, 1000, 5000),
1074+ PIN_RSEL(135, 136, 0x0, 75000, 75000),
1075+ PIN_RSEL(135, 136, 0x1, 10000, 75000),
1076+ PIN_RSEL(135, 136, 0x2, 5000, 5000),
1077+ PIN_RSEL(135, 136, 0x3, 1000, 5000),
1078+ PIN_RSEL(137, 138, 0x0, 75000, 75000),
1079+ PIN_RSEL(137, 138, 0x1, 10000, 75000),
1080+ PIN_RSEL(137, 138, 0x2, 5000, 5000),
1081+ PIN_RSEL(137, 138, 0x3, 1000, 5000),
1082+ PIN_RSEL(139, 140, 0x0, 75000, 75000),
1083+ PIN_RSEL(139, 140, 0x1, 10000, 75000),
1084+ PIN_RSEL(139, 140, 0x2, 5000, 5000),
1085+ PIN_RSEL(139, 140, 0x3, 1000, 5000),
1086+ PIN_RSEL(141, 142, 0x0, 75000, 75000),
1087+ PIN_RSEL(141, 142, 0x1, 10000, 75000),
1088+ PIN_RSEL(141, 142, 0x2, 5000, 5000),
1089+ PIN_RSEL(141, 142, 0x3, 1000, 5000),
1090+ PIN_RSEL(143, 144, 0x0, 75000, 75000),
1091+ PIN_RSEL(143, 144, 0x1, 10000, 75000),
1092+ PIN_RSEL(143, 144, 0x2, 5000, 5000),
1093+ PIN_RSEL(143, 144, 0x3, 1000, 5000),
1094+ PIN_RSEL(145, 146, 0x0, 75000, 75000),
1095+ PIN_RSEL(145, 146, 0x1, 10000, 75000),
1096+ PIN_RSEL(145, 146, 0x2, 5000, 5000),
1097+ PIN_RSEL(145, 146, 0x3, 1000, 5000),
1098+};
1099+
1100+static const unsigned int mt8186_pull_type[] = {
1101+ MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/
1102+ MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/
1103+ MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/
1104+ MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/
1105+ MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/
1106+ MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/
1107+ MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/
1108+ MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/
1109+ MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/
1110+ MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/
1111+ MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/
1112+ MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/
1113+ MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/
1114+ MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/
1115+ MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/
1116+ MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/
1117+ MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
1118+ MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
1119+ MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
1120+ MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/
1121+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
1122+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
1123+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
1124+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
1125+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
1126+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
1127+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
1128+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
1129+ MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/
1130+ MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/
1131+ MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/
1132+ MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/
1133+ MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/
1134+ MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
1135+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
1136+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
1137+ MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
1138+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
1139+ MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
1140+ MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
1141+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
1142+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
1143+ MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
1144+ MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
1145+ MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
1146+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
1147+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
1148+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
1149+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
1150+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
1151+ MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/
1152+ MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/
1153+ MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/
1154+ MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/
1155+ MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/
1156+ MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/
1157+ MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/
1158+ MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/
1159+ MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/
1160+ MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/
1161+ MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/
1162+ MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/
1163+ MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/
1164+ MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/
1165+ MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/
1166+ MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/
1167+ MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/
1168+ MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/
1169+ MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/
1170+ MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/
1171+ MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/
1172+ MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/
1173+ MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/
1174+ MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/
1175+ MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/
1176+ MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/
1177+ MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/
1178+ MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/
1179+ MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/
1180+ MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/
1181+ MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/
1182+ MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/
1183+ MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/
1184+ MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/
1185+ MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/
1186+ MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/
1187+ MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/
1188+ MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/
1189+ MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/
1190+ MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/
1191+ MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/
1192+ MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/
1193+ MTK_PULL_PU_PD_TYPE,/*184*/
1194+};
1195+
1196+static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = {
1197+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range),
1198+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range),
1199+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range),
1200+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range),
1201+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range),
1202+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range),
1203+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range),
1204+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range),
1205+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range),
1206+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range),
1207+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range),
1208+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range),
1209+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range),
1210+ [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range),
1211+ [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range),
1212+
1213+};
1214+
1215+static const char * const mt8186_pinctrl_register_base_names[] = {
1216+ "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl",
1217+ "iocfg_rb", "iocfg_rt",
1218+};
1219+
1220+static const struct mtk_eint_hw mt8186_eint_hw = {
1221+ .port_mask = 0xf,
1222+ .ports = 7,
1223+ .ap_num = 217,
1224+ .db_cnt = 32,
1225+};
1226+
1227+static const struct mtk_pin_soc mt8186_data = {
1228+ .reg_cal = mt8186_reg_cals,
1229+ .pins = mtk_pins_mt8186,
1230+ .npins = ARRAY_SIZE(mtk_pins_mt8186),
1231+ .ngrps = ARRAY_SIZE(mtk_pins_mt8186),
1232+ .nfuncs = 8,
1233+ .gpio_m = 0,
1234+ .eint_hw = &mt8186_eint_hw,
1235+ .base_names = mt8186_pinctrl_register_base_names,
1236+ .nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names),
1237+ .pull_type = mt8186_pull_type,
1238+ .pin_rsel = mt8186_pin_rsel_val_range,
1239+ .npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range),
1240+ .bias_set_combo = mtk_pinconf_bias_set_combo,
1241+ .bias_get_combo = mtk_pinconf_bias_get_combo,
1242+ .drive_set = mtk_pinconf_drive_set_rev1,
1243+ .drive_get = mtk_pinconf_drive_get_rev1,
1244+ .adv_drive_get = mtk_pinconf_adv_drive_get_raw,
1245+ .adv_drive_set = mtk_pinconf_adv_drive_set_raw,
1246+};
1247+
1248+static const struct of_device_id mt8186_pinctrl_of_match[] = {
1249+ { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data },
1250+ { }
1251+};
1252+
1253+static struct platform_driver mt8186_pinctrl_driver = {
1254+ .driver = {
1255+ .name = "mt8186-pinctrl",
1256+ .of_match_table = mt8186_pinctrl_of_match,
1257+ .pm = &mtk_paris_pinctrl_pm_ops,
1258+ },
1259+ .probe = mtk_paris_pinctrl_probe,
1260+};
1261+
1262+static int __init mt8186_pinctrl_init(void)
1263+{
1264+ return platform_driver_register(&mt8186_pinctrl_driver);
1265+}
1266+
1267+arch_initcall(mt8186_pinctrl_init);
drivers/pinctrl/mediatek/pinctrl-mt8192.c+2−7
@@ -1381,22 +1381,17 @@ static const struct mtk_pin_soc mt8192_data = { · 1380 unmodified lines
13811381 };
13821382
13831383 static const struct of_device_id mt8192_pinctrl_of_match[] = {
1384− { .compatible = "mediatek,mt8192-pinctrl", },
1384+ { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data },
13851385 { }
13861386 };
13871387
1388−static int mt8192_pinctrl_probe(struct platform_device *pdev)
1389−{
1390− return mtk_paris_pinctrl_probe(pdev, &mt8192_data);
1391−}
1392−
13931388 static struct platform_driver mt8192_pinctrl_driver = {
13941389 .driver = {
13951390 .name = "mt8192-pinctrl",
13961391 .of_match_table = mt8192_pinctrl_of_match,
13971392 .pm = &mtk_paris_pinctrl_pm_ops,
13981393 },
1399− .probe = mt8192_pinctrl_probe,
1394+ .probe = mtk_paris_pinctrl_probe,
14001395 };
14011396
14021397 static int __init mt8192_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt8195.c+2−7
@@ -959,22 +959,17 @@ static const struct mtk_pin_soc mt8195_data = { · 958 unmodified lines
959959 };
960960
961961 static const struct of_device_id mt8195_pinctrl_of_match[] = {
962− { .compatible = "mediatek,mt8195-pinctrl", },
962+ { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data },
963963 { }
964964 };
965965
966−static int mt8195_pinctrl_probe(struct platform_device *pdev)
967−{
968− return mtk_paris_pinctrl_probe(pdev, &mt8195_data);
969−}
970−
971966 static struct platform_driver mt8195_pinctrl_driver = {
972967 .driver = {
973968 .name = "mt8195-pinctrl",
974969 .of_match_table = mt8195_pinctrl_of_match,
975970 .pm = &mtk_paris_pinctrl_pm_ops,
976971 },
977− .probe = mt8195_pinctrl_probe,
972+ .probe = mtk_paris_pinctrl_probe,
978973 };
979974
980975 static int __init mt8195_pinctrl_init(void)
drivers/pinctrl/mediatek/pinctrl-mt8365.c+10−30
@@ -416,25 +416,6 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { · 415 unmodified lines
416416 MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22),
417417 };
418418
419−static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin,
420− unsigned char align, bool isup, unsigned int r1r0)
421−{
422− return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd,
423− ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0);
424−}
425−
426−static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin,
427− unsigned char align, int value, enum pin_config_param arg)
428−{
429− if (arg == PIN_CONFIG_INPUT_ENABLE)
430− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set,
431− ARRAY_SIZE(mt8365_ies_set), pin, align, value);
432− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
433− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set,
434− ARRAY_SIZE(mt8365_smt_set), pin, align, value);
435− return -EINVAL;
436−}
437−
438419 static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
439420 .pins = mtk_pins_mt8365,
440421 .npins = ARRAY_SIZE(mtk_pins_mt8365),
@@ -442,8 +423,14 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { · 1 unmodified line
442423 .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp),
443424 .pin_drv_grp = mt8365_pin_drv,
444425 .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv),
445− .spec_pull_set = mt8365_spec_pull_set,
446− .spec_ies_smt_set = mt8365_ies_smt_set,
426+ .spec_ies = mt8365_ies_set,
427+ .n_spec_ies = ARRAY_SIZE(mt8365_ies_set),
428+ .spec_smt = mt8365_smt_set,
429+ .n_spec_smt = ARRAY_SIZE(mt8365_smt_set),
430+ .spec_pupd = mt8365_spec_pupd,
431+ .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd),
432+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
433+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
447434 .dir_offset = 0x0140,
448435 .dout_offset = 0x00A0,
449436 .din_offset = 0x0000,
@@ -469,20 +456,13 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { · 19 unmodified lines
469456 },
470457 };
471458
472−static int mtk_pinctrl_probe(struct platform_device *pdev)
473−{
474− return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL);
475−}
476−
477459 static const struct of_device_id mt8365_pctrl_match[] = {
478− {
479− .compatible = "mediatek,mt8365-pinctrl",
480− },
460+ { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data },
481461 {}
482462 };
483463
484464 static struct platform_driver mtk_pinctrl_driver = {
485− .probe = mtk_pinctrl_probe,
465+ .probe = mtk_pctrl_common_probe,
486466 .driver = {
487467 .name = "mediatek-mt8365-pinctrl",
488468 .of_match_table = mt8365_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mt8516.c+10−30
@@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = { · 185 unmodified lines
186186 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
187187 };
188188
189−static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
190− unsigned char align, bool isup, unsigned int r1r0)
191−{
192− return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
193− ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
194−}
195−
196189 static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
197190 MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
198191 MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
@@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { · 93 unmodified lines
292285 MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
293286 };
294287
295−static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
296− unsigned char align, int value, enum pin_config_param arg)
297−{
298− if (arg == PIN_CONFIG_INPUT_ENABLE)
299− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
300− ARRAY_SIZE(mt8516_ies_set), pin, align, value);
301− else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
302− return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
303− ARRAY_SIZE(mt8516_smt_set), pin, align, value);
304− return -EINVAL;
305−}
306−
307288 static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
308289 .pins = mtk_pins_mt8516,
309290 .npins = ARRAY_SIZE(mtk_pins_mt8516),
@@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { · 1 unmodified line
311292 .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
312293 .pin_drv_grp = mt8516_pin_drv,
313294 .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
314− .spec_pull_set = mt8516_spec_pull_set,
315− .spec_ies_smt_set = mt8516_ies_smt_set,
295+ .spec_ies = mt8516_ies_set,
296+ .n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
297+ .spec_pupd = mt8516_spec_pupd,
298+ .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
299+ .spec_smt = mt8516_smt_set,
300+ .n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
301+ .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
302+ .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
316303 .dir_offset = 0x0000,
317304 .pullen_offset = 0x0500,
318305 .pullsel_offset = 0x0600,
@@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { · 16 unmodified lines
335322 },
336323 };
337324
338−static int mt8516_pinctrl_probe(struct platform_device *pdev)
339−{
340− return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
341−}
342−
343325 static const struct of_device_id mt8516_pctrl_match[] = {
344− {
345− .compatible = "mediatek,mt8516-pinctrl",
346− },
326+ { .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
347327 {}
348328 };
349329
350330 MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
351331
352332 static struct platform_driver mtk_pinctrl_driver = {
353− .probe = mt8516_pinctrl_probe,
333+ .probe = mtk_pctrl_common_probe,
354334 .driver = {
355335 .name = "mediatek-mt8516-pinctrl",
356336 .of_match_table = mt8516_pctrl_match,
drivers/pinctrl/mediatek/pinctrl-mtk-common.c+59−29
@@ -131,7 +131,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, · 130 unmodified lines
131131 */
132132 if (pctl->devdata->spec_ies_smt_set) {
133133 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
134− pin, pctl->devdata->port_align, value, arg);
134+ pctl->devdata, pin, value, arg);
135135 }
136136
137137 if (arg == PIN_CONFIG_INPUT_ENABLE)
@@ -151,10 +151,27 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, · 13 unmodified lines
151151 }
152152
153153 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
154− const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
155− unsigned int pin, unsigned char align, int value)
154+ const struct mtk_pinctrl_devdata *devdata,
155+ unsigned int pin, int value, enum pin_config_param arg)
156156 {
157− unsigned int i, reg_addr, bit;
157+ const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
158+ unsigned int i, info_num, reg_addr, bit;
159+
160+ switch (arg) {
161+ case PIN_CONFIG_INPUT_ENABLE:
162+ ies_smt_infos = devdata->spec_ies;
163+ info_num = devdata->n_spec_ies;
164+ break;
165+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
166+ ies_smt_infos = devdata->spec_smt;
167+ info_num = devdata->n_spec_smt;
168+ break;
169+ default:
170+ break;
171+ }
172+
173+ if (!ies_smt_infos)
174+ return -EINVAL;
158175
159176 for (i = 0; i < info_num; i++) {
160177 if (pin >= ies_smt_infos[i].start &&
@@ -167,9 +184,9 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, · 6 unmodified lines
167184 return -EINVAL;
168185
169186 if (value)
170− reg_addr = ies_smt_infos[i].offset + align;
187+ reg_addr = ies_smt_infos[i].offset + devdata->port_align;
171188 else
172− reg_addr = ies_smt_infos[i].offset + (align << 1);
189+ reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
173190
174191 bit = BIT(ies_smt_infos[i].bit);
175192 regmap_write(regmap, reg_addr, bit);
@@ -222,9 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, · 46 unmodified lines
222239 }
223240
224241 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
225− const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
226− unsigned int info_num, unsigned int pin,
227− unsigned char align, bool isup, unsigned int r1r0)
242+ const struct mtk_pinctrl_devdata *devdata,
243+ unsigned int pin, bool isup, unsigned int r1r0)
228244 {
229245 unsigned int i;
230246 unsigned int reg_pupd, reg_set, reg_rst;
@@ -232,8 +248,11 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, · 1 unmodified line
232248 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
233249 bool find = false;
234250
235− for (i = 0; i < info_num; i++) {
236− if (pin == pupd_infos[i].pin) {
251+ if (!devdata->spec_pupd)
252+ return -EINVAL;
253+
254+ for (i = 0; i < devdata->n_spec_pupd; i++) {
255+ if (pin == devdata->spec_pupd[i].pin) {
237256 find = true;
238257 break;
239258 }
@@ -242,9 +261,9 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, · 2 unmodified lines
242261 if (!find)
243262 return -EINVAL;
244263
245− spec_pupd_pin = pupd_infos + i;
246− reg_set = spec_pupd_pin->offset + align;
247− reg_rst = spec_pupd_pin->offset + (align << 1);
264+ spec_pupd_pin = devdata->spec_pupd + i;
265+ reg_set = spec_pupd_pin->offset + devdata->port_align;
266+ reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
248267
249268 if (isup)
250269 reg_pupd = reg_rst;
@@ -298,7 +317,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, · 47 unmodified lines
298317 */
299318 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
300319 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
301− pin, pctl->devdata->port_align, isup, r1r0);
320+ pctl->devdata, pin, isup,
321+ r1r0);
302322 if (!ret)
303323 return 0;
304324 }
@@ -1013,10 +1033,12 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) · 708 unmodified lines
10131033 return mtk_eint_do_init(pctl->eint);
10141034 }
10151035
1036+/* This is used as a common probe function */
10161037 int mtk_pctrl_init(struct platform_device *pdev,
10171038 const struct mtk_pinctrl_devdata *data,
10181039 struct regmap *regmap)
10191040 {
1041+ struct device *dev = &pdev->dev;
10201042 struct pinctrl_pin_desc *pins;
10211043 struct mtk_pinctrl *pctl;
10221044 struct device_node *np = pdev->dev.of_node, *node;
@@ -1030,37 +1052,35 @@ int mtk_pctrl_init(struct platform_device *pdev, · 7 unmodified lines
10301052 platform_set_drvdata(pdev, pctl);
10311053
10321054 prop = of_find_property(np, "pins-are-numbered", NULL);
1033− if (!prop) {
1034− dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1035− return -EINVAL;
1036− }
1055+ if (!prop)
1056+ return dev_err_probe(dev, -EINVAL,
1057+ "only support pins-are-numbered format\n");
10371058
10381059 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
10391060 if (node) {
10401061 pctl->regmap1 = syscon_node_to_regmap(node);
1062+ of_node_put(node);
10411063 if (IS_ERR(pctl->regmap1))
10421064 return PTR_ERR(pctl->regmap1);
10431065 } else if (regmap) {
10441066 pctl->regmap1 = regmap;
10451067 } else {
1046− dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1047− return -EINVAL;
1068+ return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
10481069 }
10491070
10501071 /* Only 8135 has two base addr, other SoCs have only one. */
10511072 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
10521073 if (node) {
10531074 pctl->regmap2 = syscon_node_to_regmap(node);
1075+ of_node_put(node);
10541076 if (IS_ERR(pctl->regmap2))
10551077 return PTR_ERR(pctl->regmap2);
10561078 }
10571079
10581080 pctl->devdata = data;
10591081 ret = mtk_pctrl_build_state(pdev);
1060− if (ret) {
1061− dev_err(&pdev->dev, "build state failed: %d\n", ret);
1062− return -EINVAL;
1063− }
1082+ if (ret)
1083+ return dev_err_probe(dev, ret, "build state failed\n");
10641084
10651085 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
10661086 GFP_KERNEL);
@@ -1081,10 +1101,9 @@ int mtk_pctrl_init(struct platform_device *pdev, · 14 unmodified lines
10811101
10821102 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
10831103 pctl);
1084− if (IS_ERR(pctl->pctl_dev)) {
1085− dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1086− return PTR_ERR(pctl->pctl_dev);
1087− }
1104+ if (IS_ERR(pctl->pctl_dev))
1105+ return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
1106+ "Couldn't register pinctrl driver\n");
10881107
10891108 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
10901109 if (!pctl->chip)
@@ -1118,3 +1137,14 @@ chip_error: · 27 unmodified lines
11181137 gpiochip_remove(pctl->chip);
11191138 return ret;
11201139 }
1140+
1141+int mtk_pctrl_common_probe(struct platform_device *pdev)
1142+{
1143+ struct device *dev = &pdev->dev;
1144+ const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
1145+
1146+ if (!data)
1147+ return -ENODEV;
1148+
1149+ return mtk_pctrl_init(pdev, data, NULL);
1150+}
drivers/pinctrl/mediatek/pinctrl-mtk-common.h+24−9
@@ -193,6 +193,12 @@ struct mtk_eint_offsets { · 192 unmodified lines
193193 *
194194 * @grp_desc: The driving group info.
195195 * @pin_drv_grp: The driving group for all pins.
196+ * @spec_ies: Special pin setting for input enable
197+ * @n_spec_ies: Number of entries in spec_ies
198+ * @spec_pupd: Special pull up/down setting
199+ * @n_spec_pupd: Number of entries in spec_pupd
200+ * @spec_smt: Special pin setting for schmitt
201+ * @n_spec_smt: Number of entries in spec_smt
196202 * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
197203 * these pins' pull setting are very different, they have separate pull
198204 * up/down bit, R0 and R1 resistor bit, so they need special pull setting.
@@ -231,10 +237,18 @@ struct mtk_pinctrl_devdata { · 32 unmodified lines
231237 unsigned int n_grp_cls;
232238 const struct mtk_pin_drv_grp *pin_drv_grp;
233239 unsigned int n_pin_drv_grps;
234− int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
235− unsigned char align, bool isup, unsigned int arg);
236− int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
237− unsigned char align, int value, enum pin_config_param arg);
240+ const struct mtk_pin_ies_smt_set *spec_ies;
241+ unsigned int n_spec_ies;
242+ const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
243+ unsigned int n_spec_pupd;
244+ const struct mtk_pin_ies_smt_set *spec_smt;
245+ unsigned int n_spec_smt;
246+ int (*spec_pull_set)(struct regmap *regmap,
247+ const struct mtk_pinctrl_devdata *devdata,
248+ unsigned int pin, bool isup, unsigned int r1r0);
249+ int (*spec_ies_smt_set)(struct regmap *reg,
250+ const struct mtk_pinctrl_devdata *devdata,
251+ unsigned int pin, int value, enum pin_config_param arg);
238252 void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
239253 unsigned int mode);
240254 void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
@@ -277,14 +291,15 @@ int mtk_pctrl_init(struct platform_device *pdev, · 36 unmodified lines
277291 const struct mtk_pinctrl_devdata *data,
278292 struct regmap *regmap);
279293
294+int mtk_pctrl_common_probe(struct platform_device *pdev);
295+
280296 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
281− const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
282− unsigned int info_num, unsigned int pin,
283− unsigned char align, bool isup, unsigned int r1r0);
297+ const struct mtk_pinctrl_devdata *devdata,
298+ unsigned int pin, bool isup, unsigned int r1r0);
284299
285300 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
286− const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
287− unsigned int pin, unsigned char align, int value);
301+ const struct mtk_pinctrl_devdata *devdata,
302+ unsigned int pin, int value, enum pin_config_param arg);
288303
289304 extern const struct dev_pm_ops mtk_eint_pm_ops;
290305
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h+2186−0
@@ -0,0 +1,2186 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (C) 2021 MediaTek Inc.
4+ *
5+ * Author: Guodong Liu <guodong.liu@mediatek.com>
6+ *
7+ */
8+
9+#ifndef __PINCTRL_MTK_MT8186_H
10+#define __PINCTRL_MTK_MT8186_H
11+
12+#include "pinctrl-paris.h"
13+
14+static const struct mtk_pin_desc mtk_pins_mt8186[] = {
15+ MTK_PIN(
16+ 0, "GPIO0",
17+ MTK_EINT_FUNCTION(0, 0),
18+ DRV_GRP4,
19+ MTK_FUNCTION(0, "GPIO0"),
20+ MTK_FUNCTION(1, "I2S0_MCK"),
21+ MTK_FUNCTION(2, "SPI0_CLK_B"),
22+ MTK_FUNCTION(3, "I2S2_MCK"),
23+ MTK_FUNCTION(4, "CMFLASH0"),
24+ MTK_FUNCTION(5, "SCP_SPI0_CK"),
25+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
26+ MTK_FUNCTION(7, "dbg_mon_a0")
27+ ),
28+
29+ MTK_PIN(
30+ 1, "GPIO1",
31+ MTK_EINT_FUNCTION(0, 1),
32+ DRV_GRP4,
33+ MTK_FUNCTION(0, "GPIO1"),
34+ MTK_FUNCTION(1, "I2S0_BCK"),
35+ MTK_FUNCTION(2, "SPI0_CSB_B"),
36+ MTK_FUNCTION(3, "I2S2_BCK"),
37+ MTK_FUNCTION(4, "CMFLASH1"),
38+ MTK_FUNCTION(5, "SCP_SPI0_CS"),
39+ MTK_FUNCTION(6, "TP_GPIO1_AO")
40+ ),
41+
42+ MTK_PIN(
43+ 2, "GPIO2",
44+ MTK_EINT_FUNCTION(0, 2),
45+ DRV_GRP4,
46+ MTK_FUNCTION(0, "GPIO2"),
47+ MTK_FUNCTION(1, "I2S0_LRCK"),
48+ MTK_FUNCTION(2, "SPI0_MO_B"),
49+ MTK_FUNCTION(3, "I2S2_LRCK"),
50+ MTK_FUNCTION(4, "CMFLASH2"),
51+ MTK_FUNCTION(5, "SCP_SPI0_MO"),
52+ MTK_FUNCTION(6, "TP_GPIO2_AO")
53+ ),
54+
55+ MTK_PIN(
56+ 3, "GPIO3",
57+ MTK_EINT_FUNCTION(0, 3),
58+ DRV_GRP4,
59+ MTK_FUNCTION(0, "GPIO3"),
60+ MTK_FUNCTION(1, "I2S0_DI"),
61+ MTK_FUNCTION(2, "SPI0_MI_B"),
62+ MTK_FUNCTION(3, "I2S2_DI"),
63+ MTK_FUNCTION(4, "SRCLKENAI1"),
64+ MTK_FUNCTION(5, "SCP_SPI0_MI"),
65+ MTK_FUNCTION(6, "TP_GPIO3_AO")
66+ ),
67+
68+ MTK_PIN(
69+ 4, "GPIO4",
70+ MTK_EINT_FUNCTION(0, 4),
71+ DRV_GRP4,
72+ MTK_FUNCTION(0, "GPIO4"),
73+ MTK_FUNCTION(1, "I2S3_DO"),
74+ MTK_FUNCTION(3, "I2S1_DO"),
75+ MTK_FUNCTION(6, "TP_GPIO4_AO")
76+ ),
77+
78+ MTK_PIN(
79+ 5, "GPIO5",
80+ MTK_EINT_FUNCTION(0, 5),
81+ DRV_GRP4,
82+ MTK_FUNCTION(0, "GPIO5"),
83+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
84+ MTK_FUNCTION(6, "TP_GPIO5_AO")
85+ ),
86+
87+ MTK_PIN(
88+ 6, "GPIO6",
89+ MTK_EINT_FUNCTION(0, 6),
90+ DRV_GRP4,
91+ MTK_FUNCTION(0, "GPIO6"),
92+ MTK_FUNCTION(1, "I2S3_MCK"),
93+ MTK_FUNCTION(2, "SPI1_CLK_B"),
94+ MTK_FUNCTION(3, "I2S1_MCK"),
95+ MTK_FUNCTION(4, "DPI_DATA22"),
96+ MTK_FUNCTION(6, "TP_GPIO6_AO")
97+ ),
98+
99+ MTK_PIN(
100+ 7, "GPIO7",
101+ MTK_EINT_FUNCTION(0, 7),
102+ DRV_GRP4,
103+ MTK_FUNCTION(0, "GPIO7"),
104+ MTK_FUNCTION(1, "I2S3_BCK"),
105+ MTK_FUNCTION(2, "SPI1_CSB_B"),
106+ MTK_FUNCTION(3, "I2S1_BCK"),
107+ MTK_FUNCTION(4, "DPI_DATA23"),
108+ MTK_FUNCTION(6, "TP_GPIO7_AO")
109+ ),
110+
111+ MTK_PIN(
112+ 8, "GPIO8",
113+ MTK_EINT_FUNCTION(0, 8),
114+ DRV_GRP4,
115+ MTK_FUNCTION(0, "GPIO8"),
116+ MTK_FUNCTION(1, "I2S3_LRCK"),
117+ MTK_FUNCTION(2, "SPI1_MO_B"),
118+ MTK_FUNCTION(3, "I2S1_LRCK"),
119+ MTK_FUNCTION(4, "CONN_UART0_RXD"),
120+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
121+ MTK_FUNCTION(6, "ADSP_UART_RX"),
122+ MTK_FUNCTION(7, "CONN_MCU_DBGACK_N")
123+ ),
124+
125+ MTK_PIN(
126+ 9, "GPIO9",
127+ MTK_EINT_FUNCTION(0, 9),
128+ DRV_GRP4,
129+ MTK_FUNCTION(0, "GPIO9"),
130+ MTK_FUNCTION(1, "I2S3_DO"),
131+ MTK_FUNCTION(2, "SPI1_MI_B"),
132+ MTK_FUNCTION(3, "I2S1_DO"),
133+ MTK_FUNCTION(4, "CONN_UART0_TXD"),
134+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
135+ MTK_FUNCTION(6, "ADSP_UART_TX"),
136+ MTK_FUNCTION(7, "CONN_MCU_DBGI_N")
137+ ),
138+
139+ MTK_PIN(
140+ 10, "GPIO10",
141+ MTK_EINT_FUNCTION(0, 10),
142+ DRV_GRP4,
143+ MTK_FUNCTION(0, "GPIO10"),
144+ MTK_FUNCTION(1, "I2S0_MCK"),
145+ MTK_FUNCTION(2, "SPI4_CLK_A"),
146+ MTK_FUNCTION(3, "I2S2_MCK"),
147+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
148+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
149+ MTK_FUNCTION(6, "ADSP_JTAG_TDI"),
150+ MTK_FUNCTION(7, "CONN_MCU_TDI")
151+ ),
152+
153+ MTK_PIN(
154+ 11, "GPIO11",
155+ MTK_EINT_FUNCTION(0, 11),
156+ DRV_GRP4,
157+ MTK_FUNCTION(0, "GPIO11"),
158+ MTK_FUNCTION(1, "I2S0_BCK"),
159+ MTK_FUNCTION(2, "SPI4_CSB_A"),
160+ MTK_FUNCTION(3, "I2S2_BCK"),
161+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
162+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
163+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"),
164+ MTK_FUNCTION(7, "CONN_MCU_TRST_B")
165+ ),
166+
167+ MTK_PIN(
168+ 12, "GPIO12",
169+ MTK_EINT_FUNCTION(0, 12),
170+ DRV_GRP4,
171+ MTK_FUNCTION(0, "GPIO12"),
172+ MTK_FUNCTION(1, "I2S0_LRCK"),
173+ MTK_FUNCTION(2, "SPI4_MO_A"),
174+ MTK_FUNCTION(3, "I2S2_LRCK"),
175+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
176+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
177+ MTK_FUNCTION(6, "ADSP_JTAG_TCK"),
178+ MTK_FUNCTION(7, "CONN_MCU_TCK")
179+ ),
180+
181+ MTK_PIN(
182+ 13, "GPIO13",
183+ MTK_EINT_FUNCTION(0, 13),
184+ DRV_GRP4,
185+ MTK_FUNCTION(0, "GPIO13"),
186+ MTK_FUNCTION(1, "I2S0_DI"),
187+ MTK_FUNCTION(2, "SPI4_MI_A"),
188+ MTK_FUNCTION(3, "I2S2_DI"),
189+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
190+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
191+ MTK_FUNCTION(6, "ADSP_JTAG_TDO"),
192+ MTK_FUNCTION(7, "CONN_MCU_TDO")
193+ ),
194+
195+ MTK_PIN(
196+ 14, "GPIO14",
197+ MTK_EINT_FUNCTION(0, 14),
198+ DRV_GRP4,
199+ MTK_FUNCTION(0, "GPIO14"),
200+ MTK_FUNCTION(3, "CLKM0"),
201+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
202+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
203+ MTK_FUNCTION(6, "ADSP_JTAG_TMS"),
204+ MTK_FUNCTION(7, "CONN_MCU_TMS")
205+ ),
206+
207+ MTK_PIN(
208+ 15, "GPIO15",
209+ MTK_EINT_FUNCTION(0, 15),
210+ DRV_GRP4,
211+ MTK_FUNCTION(0, "GPIO15"),
212+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
213+ MTK_FUNCTION(2, "SRCLKENAI1"),
214+ MTK_FUNCTION(3, "CLKM1"),
215+ MTK_FUNCTION(4, "PWM0")
216+ ),
217+
218+ MTK_PIN(
219+ 16, "GPIO16",
220+ MTK_EINT_FUNCTION(0, 16),
221+ DRV_GRP4,
222+ MTK_FUNCTION(0, "GPIO16"),
223+ MTK_FUNCTION(1, "CONN_WIFI_TXD"),
224+ MTK_FUNCTION(2, "SRCLKENAI0"),
225+ MTK_FUNCTION(3, "CLKM2"),
226+ MTK_FUNCTION(4, "PWM1")
227+ ),
228+
229+ MTK_PIN(
230+ 17, "GPIO17",
231+ MTK_EINT_FUNCTION(0, 17),
232+ DRV_GRP4,
233+ MTK_FUNCTION(0, "GPIO17"),
234+ MTK_FUNCTION(3, "CLKM3"),
235+ MTK_FUNCTION(4, "PWM2"),
236+ MTK_FUNCTION(7, "dbg_mon_a32")
237+ ),
238+
239+ MTK_PIN(
240+ 18, "GPIO18",
241+ MTK_EINT_FUNCTION(0, 18),
242+ DRV_GRP4,
243+ MTK_FUNCTION(0, "GPIO18"),
244+ MTK_FUNCTION(2, "CMVREF0"),
245+ MTK_FUNCTION(6, "SPI2_CLK_B"),
246+ MTK_FUNCTION(7, "dbg_mon_a26")
247+ ),
248+
249+ MTK_PIN(
250+ 19, "GPIO19",
251+ MTK_EINT_FUNCTION(0, 19),
252+ DRV_GRP4,
253+ MTK_FUNCTION(0, "GPIO19"),
254+ MTK_FUNCTION(2, "CMVREF1"),
255+ MTK_FUNCTION(5, "ANT_SEL3"),
256+ MTK_FUNCTION(6, "SPI2_CSB_B"),
257+ MTK_FUNCTION(7, "dbg_mon_a2")
258+ ),
259+
260+ MTK_PIN(
261+ 20, "GPIO20",
262+ MTK_EINT_FUNCTION(0, 20),
263+ DRV_GRP4,
264+ MTK_FUNCTION(0, "GPIO20"),
265+ MTK_FUNCTION(2, "CMVREF2"),
266+ MTK_FUNCTION(5, "ANT_SEL4"),
267+ MTK_FUNCTION(6, "SPI2_MO_B"),
268+ MTK_FUNCTION(7, "dbg_mon_a3")
269+ ),
270+
271+ MTK_PIN(
272+ 21, "GPIO21",
273+ MTK_EINT_FUNCTION(0, 21),
274+ DRV_GRP4,
275+ MTK_FUNCTION(0, "GPIO21"),
276+ MTK_FUNCTION(1, "I2S0_MCK"),
277+ MTK_FUNCTION(2, "I2S1_MCK"),
278+ MTK_FUNCTION(3, "I2S3_MCK"),
279+ MTK_FUNCTION(5, "ANT_SEL5"),
280+ MTK_FUNCTION(6, "SPI2_MI_B"),
281+ MTK_FUNCTION(7, "dbg_mon_a4")
282+ ),
283+
284+ MTK_PIN(
285+ 22, "GPIO22",
286+ MTK_EINT_FUNCTION(0, 22),
287+ DRV_GRP4,
288+ MTK_FUNCTION(0, "GPIO22"),
289+ MTK_FUNCTION(1, "I2S0_BCK"),
290+ MTK_FUNCTION(2, "I2S1_BCK"),
291+ MTK_FUNCTION(3, "I2S3_BCK"),
292+ MTK_FUNCTION(4, "TDM_RX_LRCK"),
293+ MTK_FUNCTION(5, "ANT_SEL6"),
294+ MTK_FUNCTION(7, "dbg_mon_a5")
295+ ),
296+
297+ MTK_PIN(
298+ 23, "GPIO23",
299+ MTK_EINT_FUNCTION(0, 23),
300+ DRV_GRP4,
301+ MTK_FUNCTION(0, "GPIO23"),
302+ MTK_FUNCTION(1, "I2S0_LRCK"),
303+ MTK_FUNCTION(2, "I2S1_LRCK"),
304+ MTK_FUNCTION(3, "I2S3_LRCK"),
305+ MTK_FUNCTION(4, "TDM_RX_BCK"),
306+ MTK_FUNCTION(5, "ANT_SEL7"),
307+ MTK_FUNCTION(7, "dbg_mon_a6")
308+ ),
309+
310+ MTK_PIN(
311+ 24, "GPIO24",
312+ MTK_EINT_FUNCTION(0, 24),
313+ DRV_GRP4,
314+ MTK_FUNCTION(0, "GPIO24"),
315+ MTK_FUNCTION(1, "I2S0_DI"),
316+ MTK_FUNCTION(2, "I2S1_DO"),
317+ MTK_FUNCTION(3, "I2S3_DO"),
318+ MTK_FUNCTION(4, "TDM_RX_MCK"),
319+ MTK_FUNCTION(7, "dbg_mon_a7")
320+ ),
321+
322+ MTK_PIN(
323+ 25, "GPIO25",
324+ MTK_EINT_FUNCTION(0, 25),
325+ DRV_GRP4,
326+ MTK_FUNCTION(0, "GPIO25"),
327+ MTK_FUNCTION(1, "I2S2_MCK"),
328+ MTK_FUNCTION(2, "PCM_CLK"),
329+ MTK_FUNCTION(3, "SPI4_CLK_B"),
330+ MTK_FUNCTION(4, "TDM_RX_DATA0"),
331+ MTK_FUNCTION(7, "dbg_mon_a8")
332+ ),
333+
334+ MTK_PIN(
335+ 26, "GPIO26",
336+ MTK_EINT_FUNCTION(0, 26),
337+ DRV_GRP4,
338+ MTK_FUNCTION(0, "GPIO26"),
339+ MTK_FUNCTION(1, "I2S2_BCK"),
340+ MTK_FUNCTION(2, "PCM_SYNC"),
341+ MTK_FUNCTION(3, "SPI4_CSB_B"),
342+ MTK_FUNCTION(4, "TDM_RX_DATA1"),
343+ MTK_FUNCTION(7, "dbg_mon_a9")
344+ ),
345+
346+ MTK_PIN(
347+ 27, "GPIO27",
348+ MTK_EINT_FUNCTION(0, 27),
349+ DRV_GRP4,
350+ MTK_FUNCTION(0, "GPIO27"),
351+ MTK_FUNCTION(1, "I2S2_LRCK"),
352+ MTK_FUNCTION(2, "PCM_DI"),
353+ MTK_FUNCTION(3, "SPI4_MO_B"),
354+ MTK_FUNCTION(4, "TDM_RX_DATA2"),
355+ MTK_FUNCTION(7, "dbg_mon_a10")
356+ ),
357+
358+ MTK_PIN(
359+ 28, "GPIO28",
360+ MTK_EINT_FUNCTION(0, 28),
361+ DRV_GRP4,
362+ MTK_FUNCTION(0, "GPIO28"),
363+ MTK_FUNCTION(1, "I2S2_DI"),
364+ MTK_FUNCTION(2, "PCM_DO"),
365+ MTK_FUNCTION(3, "SPI4_MI_B"),
366+ MTK_FUNCTION(4, "TDM_RX_DATA3")
367+ ),
368+
369+ MTK_PIN(
370+ 29, "GPIO29",
371+ MTK_EINT_FUNCTION(0, 29),
372+ DRV_GRP4,
373+ MTK_FUNCTION(0, "GPIO29"),
374+ MTK_FUNCTION(1, "ANT_SEL0"),
375+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN")
376+ ),
377+
378+ MTK_PIN(
379+ 30, "GPIO30",
380+ MTK_EINT_FUNCTION(0, 30),
381+ DRV_GRP4,
382+ MTK_FUNCTION(0, "GPIO30"),
383+ MTK_FUNCTION(1, "ANT_SEL1")
384+ ),
385+
386+ MTK_PIN(
387+ 31, "GPIO31",
388+ MTK_EINT_FUNCTION(0, 31),
389+ DRV_GRP4,
390+ MTK_FUNCTION(0, "GPIO31"),
391+ MTK_FUNCTION(1, "ANT_SEL2"),
392+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
393+ MTK_FUNCTION(3, "SRCLKENAI1")
394+ ),
395+
396+ MTK_PIN(
397+ 32, "GPIO32",
398+ MTK_EINT_FUNCTION(0, 32),
399+ DRV_GRP4,
400+ MTK_FUNCTION(0, "GPIO32"),
401+ MTK_FUNCTION(1, "URXD0"),
402+ MTK_FUNCTION(2, "UTXD0"),
403+ MTK_FUNCTION(3, "ADSP_UART_RX"),
404+ MTK_FUNCTION(4, "TP_URXD1_AO")
405+ ),
406+
407+ MTK_PIN(
408+ 33, "GPIO33",
409+ MTK_EINT_FUNCTION(0, 33),
410+ DRV_GRP4,
411+ MTK_FUNCTION(0, "GPIO33"),
412+ MTK_FUNCTION(1, "UTXD0"),
413+ MTK_FUNCTION(2, "URXD0"),
414+ MTK_FUNCTION(3, "ADSP_UART_TX"),
415+ MTK_FUNCTION(4, "TP_UTXD1_AO")
416+ ),
417+
418+ MTK_PIN(
419+ 34, "GPIO34",
420+ MTK_EINT_FUNCTION(0, 34),
421+ DRV_GRP4,
422+ MTK_FUNCTION(0, "GPIO34"),
423+ MTK_FUNCTION(1, "URXD1"),
424+ MTK_FUNCTION(2, "TP_URXD2_AO"),
425+ MTK_FUNCTION(3, "SSPM_URXD_AO"),
426+ MTK_FUNCTION(4, "ADSP_UART_RX"),
427+ MTK_FUNCTION(5, "CONN_UART0_RXD")
428+ ),
429+
430+ MTK_PIN(
431+ 35, "GPIO35",
432+ MTK_EINT_FUNCTION(0, 35),
433+ DRV_GRP4,
434+ MTK_FUNCTION(0, "GPIO35"),
435+ MTK_FUNCTION(1, "UTXD1"),
436+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
437+ MTK_FUNCTION(3, "SSPM_UTXD_AO"),
438+ MTK_FUNCTION(4, "ADSP_UART_TX"),
439+ MTK_FUNCTION(5, "CONN_UART0_TXD"),
440+ MTK_FUNCTION(6, "CONN_WIFI_TXD")
441+ ),
442+
443+ MTK_PIN(
444+ 36, "GPIO36",
445+ MTK_EINT_FUNCTION(0, 36),
446+ DRV_GRP4,
447+ MTK_FUNCTION(0, "GPIO36"),
448+ MTK_FUNCTION(1, "SPI0_CLK_A"),
449+ MTK_FUNCTION(2, "CLKM0"),
450+ MTK_FUNCTION(4, "SCP_SPI0_CK"),
451+ MTK_FUNCTION(5, "SPINOR_CK"),
452+ MTK_FUNCTION(7, "dbg_mon_a11")
453+ ),
454+
455+ MTK_PIN(
456+ 37, "GPIO37",
457+ MTK_EINT_FUNCTION(0, 37),
458+ DRV_GRP4,
459+ MTK_FUNCTION(0, "GPIO37"),
460+ MTK_FUNCTION(1, "SPI0_CSB_A"),
461+ MTK_FUNCTION(2, "CLKM1"),
462+ MTK_FUNCTION(3, "PWM0"),
463+ MTK_FUNCTION(4, "SCP_SPI0_CS"),
464+ MTK_FUNCTION(5, "SPINOR_CS"),
465+ MTK_FUNCTION(7, "dbg_mon_a12")
466+ ),
467+
468+ MTK_PIN(
469+ 38, "GPIO38",
470+ MTK_EINT_FUNCTION(0, 38),
471+ DRV_GRP4,
472+ MTK_FUNCTION(0, "GPIO38"),
473+ MTK_FUNCTION(1, "SPI0_MO_A"),
474+ MTK_FUNCTION(2, "CLKM2"),
475+ MTK_FUNCTION(3, "PWM1"),
476+ MTK_FUNCTION(4, "SCP_SPI0_MO"),
477+ MTK_FUNCTION(5, "SPINOR_IO0"),
478+ MTK_FUNCTION(7, "dbg_mon_a13")
479+ ),
480+
481+ MTK_PIN(
482+ 39, "GPIO39",
483+ MTK_EINT_FUNCTION(0, 39),
484+ DRV_GRP4,
485+ MTK_FUNCTION(0, "GPIO39"),
486+ MTK_FUNCTION(1, "SPI0_MI_A"),
487+ MTK_FUNCTION(2, "CLKM3"),
488+ MTK_FUNCTION(3, "PWM2"),
489+ MTK_FUNCTION(4, "SCP_SPI0_MI"),
490+ MTK_FUNCTION(5, "SPINOR_IO1"),
491+ MTK_FUNCTION(7, "dbg_mon_a14")
492+ ),
493+
494+ MTK_PIN(
495+ 40, "GPIO40",
496+ MTK_EINT_FUNCTION(0, 40),
497+ DRV_GRP4,
498+ MTK_FUNCTION(0, "GPIO40"),
499+ MTK_FUNCTION(1, "SPI1_CLK_A"),
500+ MTK_FUNCTION(2, "SCP_SPI1_CK"),
501+ MTK_FUNCTION(4, "UCTS0"),
502+ MTK_FUNCTION(5, "SPINOR_IO2"),
503+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
504+ MTK_FUNCTION(7, "dbg_mon_a15")
505+ ),
506+
507+ MTK_PIN(
508+ 41, "GPIO41",
509+ MTK_EINT_FUNCTION(0, 41),
510+ DRV_GRP4,
511+ MTK_FUNCTION(0, "GPIO41"),
512+ MTK_FUNCTION(1, "SPI1_CSB_A"),
513+ MTK_FUNCTION(2, "SCP_SPI1_CS"),
514+ MTK_FUNCTION(3, "PWM0"),
515+ MTK_FUNCTION(4, "URTS0"),
516+ MTK_FUNCTION(5, "SPINOR_IO3"),
517+ MTK_FUNCTION(6, "TP_URTS1_AO"),
518+ MTK_FUNCTION(7, "dbg_mon_a16")
519+ ),
520+
521+ MTK_PIN(
522+ 42, "GPIO42",
523+ MTK_EINT_FUNCTION(0, 42),
524+ DRV_GRP4,
525+ MTK_FUNCTION(0, "GPIO42"),
526+ MTK_FUNCTION(1, "SPI1_MO_A"),
527+ MTK_FUNCTION(2, "SCP_SPI1_MO"),
528+ MTK_FUNCTION(3, "PWM1"),
529+ MTK_FUNCTION(4, "UCTS1"),
530+ MTK_FUNCTION(6, "TP_UCTS2_AO"),
531+ MTK_FUNCTION(7, "dbg_mon_a17")
532+ ),
533+
534+ MTK_PIN(
535+ 43, "GPIO43",
536+ MTK_EINT_FUNCTION(0, 43),
537+ DRV_GRP4,
538+ MTK_FUNCTION(0, "GPIO43"),
539+ MTK_FUNCTION(1, "SPI1_MI_A"),
540+ MTK_FUNCTION(2, "SCP_SPI1_MI"),
541+ MTK_FUNCTION(3, "PWM2"),
542+ MTK_FUNCTION(4, "URTS1"),
543+ MTK_FUNCTION(6, "TP_URTS2_AO"),
544+ MTK_FUNCTION(7, "dbg_mon_a18")
545+ ),
546+
547+ MTK_PIN(
548+ 44, "GPIO44",
549+ MTK_EINT_FUNCTION(0, 44),
550+ DRV_GRP4,
551+ MTK_FUNCTION(0, "GPIO44"),
552+ MTK_FUNCTION(1, "SPI2_CLK_A"),
553+ MTK_FUNCTION(2, "SCP_SPI0_CK"),
554+ MTK_FUNCTION(7, "dbg_mon_a19")
555+ ),
556+
557+ MTK_PIN(
558+ 45, "GPIO45",
559+ MTK_EINT_FUNCTION(0, 45),
560+ DRV_GRP4,
561+ MTK_FUNCTION(0, "GPIO45"),
562+ MTK_FUNCTION(1, "SPI2_CSB_A"),
563+ MTK_FUNCTION(2, "SCP_SPI0_CS"),
564+ MTK_FUNCTION(7, "dbg_mon_a20")
565+ ),
566+
567+ MTK_PIN(
568+ 46, "GPIO46",
569+ MTK_EINT_FUNCTION(0, 46),
570+ DRV_GRP4,
571+ MTK_FUNCTION(0, "GPIO46"),
572+ MTK_FUNCTION(1, "SPI2_MO_A"),
573+ MTK_FUNCTION(2, "SCP_SPI0_MO"),
574+ MTK_FUNCTION(7, "dbg_mon_a21")
575+ ),
576+
577+ MTK_PIN(
578+ 47, "GPIO47",
579+ MTK_EINT_FUNCTION(0, 47),
580+ DRV_GRP4,
581+ MTK_FUNCTION(0, "GPIO47"),
582+ MTK_FUNCTION(1, "SPI2_MI_A"),
583+ MTK_FUNCTION(2, "SCP_SPI0_MI"),
584+ MTK_FUNCTION(7, "dbg_mon_a22")
585+ ),
586+
587+ MTK_PIN(
588+ 48, "GPIO48",
589+ MTK_EINT_FUNCTION(0, 48),
590+ DRV_GRP4,
591+ MTK_FUNCTION(0, "GPIO48"),
592+ MTK_FUNCTION(1, "SPI3_CLK"),
593+ MTK_FUNCTION(2, "TP_URXD1_AO"),
594+ MTK_FUNCTION(3, "TP_URXD2_AO"),
595+ MTK_FUNCTION(4, "URXD1"),
596+ MTK_FUNCTION(5, "I2S2_MCK"),
597+ MTK_FUNCTION(6, "SCP_SPI0_CK")
598+ ),
599+
600+ MTK_PIN(
601+ 49, "GPIO49",
602+ MTK_EINT_FUNCTION(0, 49),
603+ DRV_GRP4,
604+ MTK_FUNCTION(0, "GPIO49"),
605+ MTK_FUNCTION(1, "SPI3_CSB"),
606+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
607+ MTK_FUNCTION(3, "TP_UTXD2_AO"),
608+ MTK_FUNCTION(4, "UTXD1"),
609+ MTK_FUNCTION(5, "I2S2_BCK"),
610+ MTK_FUNCTION(6, "SCP_SPI0_CS")
611+ ),
612+
613+ MTK_PIN(
614+ 50, "GPIO50",
615+ MTK_EINT_FUNCTION(0, 50),
616+ DRV_GRP4,
617+ MTK_FUNCTION(0, "GPIO50"),
618+ MTK_FUNCTION(1, "SPI3_MO"),
619+ MTK_FUNCTION(5, "I2S2_LRCK"),
620+ MTK_FUNCTION(6, "SCP_SPI0_MO")
621+ ),
622+
623+ MTK_PIN(
624+ 51, "GPIO51",
625+ MTK_EINT_FUNCTION(0, 51),
626+ DRV_GRP4,
627+ MTK_FUNCTION(0, "GPIO51"),
628+ MTK_FUNCTION(1, "SPI3_MI"),
629+ MTK_FUNCTION(5, "I2S2_DI"),
630+ MTK_FUNCTION(6, "SCP_SPI0_MI")
631+ ),
632+
633+ MTK_PIN(
634+ 52, "GPIO52",
635+ MTK_EINT_FUNCTION(0, 52),
636+ DRV_GRP4,
637+ MTK_FUNCTION(0, "GPIO52"),
638+ MTK_FUNCTION(1, "SPI5_CLK"),
639+ MTK_FUNCTION(2, "I2S2_MCK"),
640+ MTK_FUNCTION(3, "I2S1_MCK"),
641+ MTK_FUNCTION(4, "SCP_SPI1_CK"),
642+ MTK_FUNCTION(5, "LVTS_26M"),
643+ MTK_FUNCTION(6, "DFD_TCK_XI"),
644+ MTK_FUNCTION(7, "dbg_mon_b30")
645+ ),
646+
647+ MTK_PIN(
648+ 53, "GPIO53",
649+ MTK_EINT_FUNCTION(0, 53),
650+ DRV_GRP4,
651+ MTK_FUNCTION(0, "GPIO53"),
652+ MTK_FUNCTION(1, "SPI5_CSB"),
653+ MTK_FUNCTION(2, "I2S2_BCK"),
654+ MTK_FUNCTION(3, "I2S1_BCK"),
655+ MTK_FUNCTION(4, "SCP_SPI1_CS"),
656+ MTK_FUNCTION(5, "LVTS_FOUT"),
657+ MTK_FUNCTION(6, "DFD_TDI"),
658+ MTK_FUNCTION(7, "dbg_mon_b31")
659+ ),
660+
661+ MTK_PIN(
662+ 54, "GPIO54",
663+ MTK_EINT_FUNCTION(0, 54),
664+ DRV_GRP4,
665+ MTK_FUNCTION(0, "GPIO54"),
666+ MTK_FUNCTION(1, "SPI5_MO"),
667+ MTK_FUNCTION(2, "I2S2_LRCK"),
668+ MTK_FUNCTION(3, "I2S1_LRCK"),
669+ MTK_FUNCTION(4, "SCP_SPI1_MO"),
670+ MTK_FUNCTION(5, "LVTS_SCK"),
671+ MTK_FUNCTION(6, "DFD_TDO"),
672+ MTK_FUNCTION(7, "dbg_mon_a1")
673+ ),
674+
675+ MTK_PIN(
676+ 55, "GPIO55",
677+ MTK_EINT_FUNCTION(0, 55),
678+ DRV_GRP4,
679+ MTK_FUNCTION(0, "GPIO55"),
680+ MTK_FUNCTION(1, "SPI5_MI"),
681+ MTK_FUNCTION(2, "I2S2_DI"),
682+ MTK_FUNCTION(3, "I2S1_DO"),
683+ MTK_FUNCTION(4, "SCP_SPI1_MI"),
684+ MTK_FUNCTION(5, "LVTS_SDO"),
685+ MTK_FUNCTION(6, "DFD_TMS"),
686+ MTK_FUNCTION(7, "dbg_mon_b32")
687+ ),
688+
689+ MTK_PIN(
690+ 56, "GPIO56",
691+ MTK_EINT_FUNCTION(0, 56),
692+ DRV_GRP4,
693+ MTK_FUNCTION(0, "GPIO56"),
694+ MTK_FUNCTION(1, "I2S1_DO"),
695+ MTK_FUNCTION(2, "I2S3_DO"),
696+ MTK_FUNCTION(7, "dbg_mon_a23")
697+ ),
698+
699+ MTK_PIN(
700+ 57, "GPIO57",
701+ MTK_EINT_FUNCTION(0, 57),
702+ DRV_GRP4,
703+ MTK_FUNCTION(0, "GPIO57"),
704+ MTK_FUNCTION(1, "I2S1_BCK"),
705+ MTK_FUNCTION(2, "I2S3_BCK"),
706+ MTK_FUNCTION(7, "dbg_mon_a24")
707+ ),
708+
709+ MTK_PIN(
710+ 58, "GPIO58",
711+ MTK_EINT_FUNCTION(0, 58),
712+ DRV_GRP4,
713+ MTK_FUNCTION(0, "GPIO58"),
714+ MTK_FUNCTION(1, "I2S1_LRCK"),
715+ MTK_FUNCTION(2, "I2S3_LRCK"),
716+ MTK_FUNCTION(7, "dbg_mon_a25")
717+ ),
718+
719+ MTK_PIN(
720+ 59, "GPIO59",
721+ MTK_EINT_FUNCTION(0, 59),
722+ DRV_GRP4,
723+ MTK_FUNCTION(0, "GPIO59"),
724+ MTK_FUNCTION(1, "I2S1_MCK"),
725+ MTK_FUNCTION(2, "I2S3_MCK"),
726+ MTK_FUNCTION(7, "dbg_mon_a27")
727+ ),
728+
729+ MTK_PIN(
730+ 60, "GPIO60",
731+ MTK_EINT_FUNCTION(0, 60),
732+ DRV_GRP4,
733+ MTK_FUNCTION(0, "GPIO60"),
734+ MTK_FUNCTION(1, "TDM_RX_LRCK"),
735+ MTK_FUNCTION(2, "ANT_SEL3"),
736+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N")
737+ ),
738+
739+ MTK_PIN(
740+ 61, "GPIO61",
741+ MTK_EINT_FUNCTION(0, 61),
742+ DRV_GRP4,
743+ MTK_FUNCTION(0, "GPIO61"),
744+ MTK_FUNCTION(1, "TDM_RX_BCK"),
745+ MTK_FUNCTION(2, "ANT_SEL4"),
746+ MTK_FUNCTION(4, "SPINOR_CK"),
747+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N")
748+ ),
749+
750+ MTK_PIN(
751+ 62, "GPIO62",
752+ MTK_EINT_FUNCTION(0, 62),
753+ DRV_GRP4,
754+ MTK_FUNCTION(0, "GPIO62"),
755+ MTK_FUNCTION(1, "TDM_RX_MCK"),
756+ MTK_FUNCTION(2, "ANT_SEL5"),
757+ MTK_FUNCTION(4, "SPINOR_CS"),
758+ MTK_FUNCTION(5, "CONN_MCU_TDI")
759+ ),
760+
761+ MTK_PIN(
762+ 63, "GPIO63",
763+ MTK_EINT_FUNCTION(0, 63),
764+ DRV_GRP4,
765+ MTK_FUNCTION(0, "GPIO63"),
766+ MTK_FUNCTION(1, "TDM_RX_DATA0"),
767+ MTK_FUNCTION(2, "ANT_SEL6"),
768+ MTK_FUNCTION(4, "SPINOR_IO0"),
769+ MTK_FUNCTION(5, "CONN_MCU_TRST_B")
770+ ),
771+
772+ MTK_PIN(
773+ 64, "GPIO64",
774+ MTK_EINT_FUNCTION(0, 64),
775+ DRV_GRP4,
776+ MTK_FUNCTION(0, "GPIO64"),
777+ MTK_FUNCTION(1, "TDM_RX_DATA1"),
778+ MTK_FUNCTION(2, "ANT_SEL7"),
779+ MTK_FUNCTION(3, "PWM0"),
780+ MTK_FUNCTION(4, "SPINOR_IO1"),
781+ MTK_FUNCTION(5, "CONN_MCU_TCK")
782+ ),
783+
784+ MTK_PIN(
785+ 65, "GPIO65",
786+ MTK_EINT_FUNCTION(0, 65),
787+ DRV_GRP4,
788+ MTK_FUNCTION(0, "GPIO65"),
789+ MTK_FUNCTION(1, "TDM_RX_DATA2"),
790+ MTK_FUNCTION(2, "UCTS0"),
791+ MTK_FUNCTION(3, "PWM1"),
792+ MTK_FUNCTION(4, "SPINOR_IO2"),
793+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
794+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
795+ MTK_FUNCTION(7, "TP_UCTS2_AO")
796+ ),
797+
798+ MTK_PIN(
799+ 66, "GPIO66",
800+ MTK_EINT_FUNCTION(0, 66),
801+ DRV_GRP4,
802+ MTK_FUNCTION(0, "GPIO66"),
803+ MTK_FUNCTION(1, "TDM_RX_DATA3"),
804+ MTK_FUNCTION(2, "URTS0"),
805+ MTK_FUNCTION(3, "PWM2"),
806+ MTK_FUNCTION(4, "SPINOR_IO3"),
807+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
808+ MTK_FUNCTION(6, "TP_URTS1_AO"),
809+ MTK_FUNCTION(7, "TP_URTS2_AO")
810+ ),
811+
812+ MTK_PIN(
813+ 67, "GPIO67",
814+ MTK_EINT_FUNCTION(0, 67),
815+ DRV_GRP4,
816+ MTK_FUNCTION(0, "GPIO67"),
817+ MTK_FUNCTION(1, "MSDC0_DSL")
818+ ),
819+
820+ MTK_PIN(
821+ 68, "GPIO68",
822+ MTK_EINT_FUNCTION(0, 68),
823+ DRV_GRP4,
824+ MTK_FUNCTION(0, "GPIO68"),
825+ MTK_FUNCTION(1, "MSDC0_CLK")
826+ ),
827+
828+ MTK_PIN(
829+ 69, "GPIO69",
830+ MTK_EINT_FUNCTION(0, 69),
831+ DRV_GRP4,
832+ MTK_FUNCTION(0, "GPIO69"),
833+ MTK_FUNCTION(1, "MSDC0_CMD")
834+ ),
835+
836+ MTK_PIN(
837+ 70, "GPIO70",
838+ MTK_EINT_FUNCTION(0, 70),
839+ DRV_GRP4,
840+ MTK_FUNCTION(0, "GPIO70"),
841+ MTK_FUNCTION(1, "MSDC0_RSTB")
842+ ),
843+
844+ MTK_PIN(
845+ 71, "GPIO71",
846+ MTK_EINT_FUNCTION(0, 71),
847+ DRV_GRP4,
848+ MTK_FUNCTION(0, "GPIO71"),
849+ MTK_FUNCTION(1, "MSDC0_DAT0")
850+ ),
851+
852+ MTK_PIN(
853+ 72, "GPIO72",
854+ MTK_EINT_FUNCTION(0, 72),
855+ DRV_GRP4,
856+ MTK_FUNCTION(0, "GPIO72"),
857+ MTK_FUNCTION(1, "MSDC0_DAT1")
858+ ),
859+
860+ MTK_PIN(
861+ 73, "GPIO73",
862+ MTK_EINT_FUNCTION(0, 73),
863+ DRV_GRP4,
864+ MTK_FUNCTION(0, "GPIO73"),
865+ MTK_FUNCTION(1, "MSDC0_DAT2")
866+ ),
867+
868+ MTK_PIN(
869+ 74, "GPIO74",
870+ MTK_EINT_FUNCTION(0, 74),
871+ DRV_GRP4,
872+ MTK_FUNCTION(0, "GPIO74"),
873+ MTK_FUNCTION(1, "MSDC0_DAT3")
874+ ),
875+
876+ MTK_PIN(
877+ 75, "GPIO75",
878+ MTK_EINT_FUNCTION(0, 75),
879+ DRV_GRP4,
880+ MTK_FUNCTION(0, "GPIO75"),
881+ MTK_FUNCTION(1, "MSDC0_DAT4")
882+ ),
883+
884+ MTK_PIN(
885+ 76, "GPIO76",
886+ MTK_EINT_FUNCTION(0, 76),
887+ DRV_GRP4,
888+ MTK_FUNCTION(0, "GPIO76"),
889+ MTK_FUNCTION(1, "MSDC0_DAT5")
890+ ),
891+
892+ MTK_PIN(
893+ 77, "GPIO77",
894+ MTK_EINT_FUNCTION(0, 77),
895+ DRV_GRP4,
896+ MTK_FUNCTION(0, "GPIO77"),
897+ MTK_FUNCTION(1, "MSDC0_DAT6")
898+ ),
899+
900+ MTK_PIN(
901+ 78, "GPIO78",
902+ MTK_EINT_FUNCTION(0, 78),
903+ DRV_GRP4,
904+ MTK_FUNCTION(0, "GPIO78"),
905+ MTK_FUNCTION(1, "MSDC0_DAT7")
906+ ),
907+
908+ MTK_PIN(
909+ 79, "GPIO79",
910+ MTK_EINT_FUNCTION(0, 79),
911+ DRV_GRP4,
912+ MTK_FUNCTION(0, "GPIO79"),
913+ MTK_FUNCTION(1, "KPCOL0")
914+ ),
915+
916+ MTK_PIN(
917+ 80, "GPIO80",
918+ MTK_EINT_FUNCTION(0, 80),
919+ DRV_GRP4,
920+ MTK_FUNCTION(0, "GPIO80"),
921+ MTK_FUNCTION(1, "KPCOL1"),
922+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
923+ MTK_FUNCTION(3, "PWM0"),
924+ MTK_FUNCTION(4, "CLKM0")
925+ ),
926+
927+ MTK_PIN(
928+ 81, "GPIO81",
929+ MTK_EINT_FUNCTION(0, 81),
930+ DRV_GRP4,
931+ MTK_FUNCTION(0, "GPIO81"),
932+ MTK_FUNCTION(1, "KPROW0"),
933+ MTK_FUNCTION(3, "PWM1"),
934+ MTK_FUNCTION(4, "CLKM1")
935+ ),
936+
937+ MTK_PIN(
938+ 82, "GPIO82",
939+ MTK_EINT_FUNCTION(0, 82),
940+ DRV_GRP4,
941+ MTK_FUNCTION(0, "GPIO82"),
942+ MTK_FUNCTION(1, "KPROW1"),
943+ MTK_FUNCTION(3, "PWM2"),
944+ MTK_FUNCTION(4, "CLKM2")
945+ ),
946+
947+ MTK_PIN(
948+ 83, "GPIO83",
949+ MTK_EINT_FUNCTION(0, 83),
950+ DRV_GRP4,
951+ MTK_FUNCTION(0, "GPIO83"),
952+ MTK_FUNCTION(1, "AP_GOOD"),
953+ MTK_FUNCTION(2, "GPS_PPS"),
954+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
955+ MTK_FUNCTION(7, "dbg_mon_a28")
956+ ),
957+
958+ MTK_PIN(
959+ 84, "GPIO84",
960+ MTK_EINT_FUNCTION(0, 84),
961+ DRV_GRP4,
962+ MTK_FUNCTION(0, "GPIO84"),
963+ MTK_FUNCTION(1, "MSDC1_CLK"),
964+ MTK_FUNCTION(2, "ADSP_JTAG_TCK"),
965+ MTK_FUNCTION(4, "UDI_TCK"),
966+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
967+ MTK_FUNCTION(6, "SSPM_JTAG_TCK"),
968+ MTK_FUNCTION(7, "DFD_TCK_XI")
969+ ),
970+
971+ MTK_PIN(
972+ 85, "GPIO85",
973+ MTK_EINT_FUNCTION(0, 85),
974+ DRV_GRP4,
975+ MTK_FUNCTION(0, "GPIO85"),
976+ MTK_FUNCTION(1, "MSDC1_CMD"),
977+ MTK_FUNCTION(2, "ADSP_JTAG_TMS"),
978+ MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
979+ MTK_FUNCTION(4, "UDI_TMS"),
980+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
981+ MTK_FUNCTION(6, "SSPM_JTAG_TMS"),
982+ MTK_FUNCTION(7, "DFD_TMS")
983+ ),
984+
985+ MTK_PIN(
986+ 86, "GPIO86",
987+ MTK_EINT_FUNCTION(0, 86),
988+ DRV_GRP4,
989+ MTK_FUNCTION(0, "GPIO86"),
990+ MTK_FUNCTION(1, "MSDC1_DAT0"),
991+ MTK_FUNCTION(2, "ADSP_JTAG_TDI"),
992+ MTK_FUNCTION(4, "UDI_TDI"),
993+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
994+ MTK_FUNCTION(6, "SSPM_JTAG_TDI"),
995+ MTK_FUNCTION(7, "DFD_TDI")
996+ ),
997+
998+ MTK_PIN(
999+ 87, "GPIO87",
1000+ MTK_EINT_FUNCTION(0, 87),
1001+ DRV_GRP4,
1002+ MTK_FUNCTION(0, "GPIO87"),
1003+ MTK_FUNCTION(1, "MSDC1_DAT1"),
1004+ MTK_FUNCTION(2, "ADSP_JTAG_TDO"),
1005+ MTK_FUNCTION(4, "UDI_TDO"),
1006+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
1007+ MTK_FUNCTION(6, "SSPM_JTAG_TDO"),
1008+ MTK_FUNCTION(7, "DFD_TDO")
1009+ ),
1010+
1011+ MTK_PIN(
1012+ 88, "GPIO88",
1013+ MTK_EINT_FUNCTION(0, 88),
1014+ DRV_GRP4,
1015+ MTK_FUNCTION(0, "GPIO88"),
1016+ MTK_FUNCTION(1, "MSDC1_DAT2"),
1017+ MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"),
1018+ MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"),
1019+ MTK_FUNCTION(4, "UDI_NTRST"),
1020+ MTK_FUNCTION(5, "CONN_WIFI_TXD"),
1021+ MTK_FUNCTION(6, "SSPM_JTAG_TRSTN")
1022+ ),
1023+
1024+ MTK_PIN(
1025+ 89, "GPIO89",
1026+ MTK_EINT_FUNCTION(0, 89),
1027+ DRV_GRP4,
1028+ MTK_FUNCTION(0, "GPIO89"),
1029+ MTK_FUNCTION(1, "MSDC1_DAT3"),
1030+ MTK_FUNCTION(5, "CONN_DSP_JINTP")
1031+ ),
1032+
1033+ MTK_PIN(
1034+ 90, "GPIO90",
1035+ MTK_EINT_FUNCTION(0, 90),
1036+ DRV_GRP4,
1037+ MTK_FUNCTION(0, "GPIO90"),
1038+ MTK_FUNCTION(1, "IDDIG_P0"),
1039+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"),
1040+ MTK_FUNCTION(5, "GDU_SUM_TROOP2_2")
1041+ ),
1042+
1043+ MTK_PIN(
1044+ 91, "GPIO91",
1045+ MTK_EINT_FUNCTION(0, 91),
1046+ DRV_GRP4,
1047+ MTK_FUNCTION(0, "GPIO91"),
1048+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
1049+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"),
1050+ MTK_FUNCTION(5, "GDU_TROOPS_DET0")
1051+ ),
1052+
1053+ MTK_PIN(
1054+ 92, "GPIO92",
1055+ MTK_EINT_FUNCTION(0, 92),
1056+ DRV_GRP4,
1057+ MTK_FUNCTION(0, "GPIO92"),
1058+ MTK_FUNCTION(1, "VBUS_VALID_P0"),
1059+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"),
1060+ MTK_FUNCTION(5, "GDU_TROOPS_DET1")
1061+ ),
1062+
1063+ MTK_PIN(
1064+ 93, "GPIO93",
1065+ MTK_EINT_FUNCTION(0, 93),
1066+ DRV_GRP4,
1067+ MTK_FUNCTION(0, "GPIO93"),
1068+ MTK_FUNCTION(1, "IDDIG_P1"),
1069+ MTK_FUNCTION(2, "PWM0"),
1070+ MTK_FUNCTION(3, "CLKM0"),
1071+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"),
1072+ MTK_FUNCTION(5, "GDU_TROOPS_DET2")
1073+ ),
1074+
1075+ MTK_PIN(
1076+ 94, "GPIO94",
1077+ MTK_EINT_FUNCTION(0, 94),
1078+ DRV_GRP4,
1079+ MTK_FUNCTION(0, "GPIO94"),
1080+ MTK_FUNCTION(1, "USB_DRVVBUS_P1"),
1081+ MTK_FUNCTION(2, "PWM1"),
1082+ MTK_FUNCTION(3, "CLKM1"),
1083+ MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET")
1084+ ),
1085+
1086+ MTK_PIN(
1087+ 95, "GPIO95",
1088+ MTK_EINT_FUNCTION(0, 95),
1089+ DRV_GRP4,
1090+ MTK_FUNCTION(0, "GPIO95"),
1091+ MTK_FUNCTION(1, "VBUS_VALID_P1"),
1092+ MTK_FUNCTION(2, "PWM2"),
1093+ MTK_FUNCTION(3, "CLKM2"),
1094+ MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB")
1095+ ),
1096+
1097+ MTK_PIN(
1098+ 96, "GPIO96",
1099+ MTK_EINT_FUNCTION(0, 96),
1100+ DRV_GRP4,
1101+ MTK_FUNCTION(0, "GPIO96"),
1102+ MTK_FUNCTION(1, "DSI_TE"),
1103+ MTK_FUNCTION(7, "dbg_mon_a29")
1104+ ),
1105+
1106+ MTK_PIN(
1107+ 97, "GPIO97",
1108+ MTK_EINT_FUNCTION(0, 97),
1109+ DRV_GRP4,
1110+ MTK_FUNCTION(0, "GPIO97"),
1111+ MTK_FUNCTION(1, "DISP_PWM"),
1112+ MTK_FUNCTION(7, "dbg_mon_a30")
1113+ ),
1114+
1115+ MTK_PIN(
1116+ 98, "GPIO98",
1117+ MTK_EINT_FUNCTION(0, 98),
1118+ DRV_GRP4,
1119+ MTK_FUNCTION(0, "GPIO98"),
1120+ MTK_FUNCTION(1, "LCM_RST")
1121+ ),
1122+
1123+ MTK_PIN(
1124+ 99, "GPIO99",
1125+ MTK_EINT_FUNCTION(0, 99),
1126+ DRV_GRP4,
1127+ MTK_FUNCTION(0, "GPIO99"),
1128+ MTK_FUNCTION(1, "DPI_PCLK"),
1129+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
1130+ MTK_FUNCTION(3, "SSPM_JTAG_TCK"),
1131+ MTK_FUNCTION(5, "ANT_SEL0"),
1132+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
1133+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR0")
1134+ ),
1135+
1136+ MTK_PIN(
1137+ 100, "GPIO100",
1138+ MTK_EINT_FUNCTION(0, 100),
1139+ DRV_GRP4,
1140+ MTK_FUNCTION(0, "GPIO100"),
1141+ MTK_FUNCTION(1, "DPI_VSYNC"),
1142+ MTK_FUNCTION(2, "KPCOL2"),
1143+ MTK_FUNCTION(3, "SSPM_JTAG_TMS"),
1144+ MTK_FUNCTION(5, "ANT_SEL1"),
1145+ MTK_FUNCTION(6, "TP_GPIO1_AO"),
1146+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR1")
1147+ ),
1148+
1149+ MTK_PIN(
1150+ 101, "GPIO101",
1151+ MTK_EINT_FUNCTION(0, 101),
1152+ DRV_GRP4,
1153+ MTK_FUNCTION(0, "GPIO101"),
1154+ MTK_FUNCTION(1, "DPI_HSYNC"),
1155+ MTK_FUNCTION(2, "KPROW2"),
1156+ MTK_FUNCTION(3, "SSPM_JTAG_TDI"),
1157+ MTK_FUNCTION(5, "ANT_SEL2"),
1158+ MTK_FUNCTION(6, "TP_GPIO2_AO"),
1159+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR2")
1160+ ),
1161+
1162+ MTK_PIN(
1163+ 102, "GPIO102",
1164+ MTK_EINT_FUNCTION(0, 102),
1165+ DRV_GRP4,
1166+ MTK_FUNCTION(0, "GPIO102"),
1167+ MTK_FUNCTION(1, "DPI_DE"),
1168+ MTK_FUNCTION(3, "SSPM_JTAG_TDO"),
1169+ MTK_FUNCTION(5, "ANT_SEL3"),
1170+ MTK_FUNCTION(6, "TP_GPIO3_AO"),
1171+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR3")
1172+ ),
1173+
1174+ MTK_PIN(
1175+ 103, "GPIO103",
1176+ MTK_EINT_FUNCTION(0, 103),
1177+ DRV_GRP4,
1178+ MTK_FUNCTION(0, "GPIO103"),
1179+ MTK_FUNCTION(1, "DPI_DATA0"),
1180+ MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"),
1181+ MTK_FUNCTION(4, "CLKM0"),
1182+ MTK_FUNCTION(5, "ANT_SEL4"),
1183+ MTK_FUNCTION(6, "TP_GPIO4_AO"),
1184+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR4")
1185+ ),
1186+
1187+ MTK_PIN(
1188+ 104, "GPIO104",
1189+ MTK_EINT_FUNCTION(0, 104),
1190+ DRV_GRP4,
1191+ MTK_FUNCTION(0, "GPIO104"),
1192+ MTK_FUNCTION(1, "DPI_DATA1"),
1193+ MTK_FUNCTION(2, "GPS_PPS"),
1194+ MTK_FUNCTION(3, "UCTS2"),
1195+ MTK_FUNCTION(4, "CLKM1"),
1196+ MTK_FUNCTION(5, "ANT_SEL5"),
1197+ MTK_FUNCTION(6, "TP_GPIO5_AO"),
1198+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR5")
1199+ ),
1200+
1201+ MTK_PIN(
1202+ 105, "GPIO105",
1203+ MTK_EINT_FUNCTION(0, 105),
1204+ DRV_GRP4,
1205+ MTK_FUNCTION(0, "GPIO105"),
1206+ MTK_FUNCTION(1, "DPI_DATA2"),
1207+ MTK_FUNCTION(2, "CONN_TCXOENA_REQ"),
1208+ MTK_FUNCTION(3, "URTS2"),
1209+ MTK_FUNCTION(4, "CLKM2"),
1210+ MTK_FUNCTION(5, "ANT_SEL6"),
1211+ MTK_FUNCTION(6, "TP_GPIO6_AO"),
1212+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR0")
1213+ ),
1214+
1215+ MTK_PIN(
1216+ 106, "GPIO106",
1217+ MTK_EINT_FUNCTION(0, 106),
1218+ DRV_GRP4,
1219+ MTK_FUNCTION(0, "GPIO106"),
1220+ MTK_FUNCTION(1, "DPI_DATA3"),
1221+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
1222+ MTK_FUNCTION(3, "UTXD2"),
1223+ MTK_FUNCTION(4, "PWM0"),
1224+ MTK_FUNCTION(5, "ANT_SEL7"),
1225+ MTK_FUNCTION(6, "TP_GPIO7_AO"),
1226+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR1")
1227+ ),
1228+
1229+ MTK_PIN(
1230+ 107, "GPIO107",
1231+ MTK_EINT_FUNCTION(0, 107),
1232+ DRV_GRP4,
1233+ MTK_FUNCTION(0, "GPIO107"),
1234+ MTK_FUNCTION(1, "DPI_DATA4"),
1235+ MTK_FUNCTION(2, "TP_URXD1_AO"),
1236+ MTK_FUNCTION(3, "URXD2"),
1237+ MTK_FUNCTION(4, "PWM1"),
1238+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"),
1239+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR2")
1240+ ),
1241+
1242+ MTK_PIN(
1243+ 108, "GPIO108",
1244+ MTK_EINT_FUNCTION(0, 108),
1245+ DRV_GRP4,
1246+ MTK_FUNCTION(0, "GPIO108"),
1247+ MTK_FUNCTION(1, "DPI_DATA5"),
1248+ MTK_FUNCTION(2, "TP_UCTS1_AO"),
1249+ MTK_FUNCTION(3, "UCTS0"),
1250+ MTK_FUNCTION(4, "PWM2"),
1251+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"),
1252+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR3")
1253+ ),
1254+
1255+ MTK_PIN(
1256+ 109, "GPIO109",
1257+ MTK_EINT_FUNCTION(0, 109),
1258+ DRV_GRP4,
1259+ MTK_FUNCTION(0, "GPIO109"),
1260+ MTK_FUNCTION(1, "DPI_DATA6"),
1261+ MTK_FUNCTION(2, "TP_URTS1_AO"),
1262+ MTK_FUNCTION(3, "URTS0"),
1263+ MTK_FUNCTION(4, "I2S0_DI"),
1264+ MTK_FUNCTION(5, "I2S2_DI"),
1265+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"),
1266+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR4")
1267+ ),
1268+
1269+ MTK_PIN(
1270+ 110, "GPIO110",
1271+ MTK_EINT_FUNCTION(0, 110),
1272+ DRV_GRP4,
1273+ MTK_FUNCTION(0, "GPIO110"),
1274+ MTK_FUNCTION(1, "DPI_DATA7"),
1275+ MTK_FUNCTION(2, "TP_UCTS2_AO"),
1276+ MTK_FUNCTION(3, "UCTS1"),
1277+ MTK_FUNCTION(4, "I2S3_BCK"),
1278+ MTK_FUNCTION(5, "I2S1_BCK"),
1279+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"),
1280+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR5")
1281+ ),
1282+
1283+ MTK_PIN(
1284+ 111, "GPIO111",
1285+ MTK_EINT_FUNCTION(0, 111),
1286+ DRV_GRP4,
1287+ MTK_FUNCTION(0, "GPIO111"),
1288+ MTK_FUNCTION(1, "DPI_DATA8"),
1289+ MTK_FUNCTION(2, "TP_URTS2_AO"),
1290+ MTK_FUNCTION(3, "URTS1"),
1291+ MTK_FUNCTION(4, "I2S3_MCK"),
1292+ MTK_FUNCTION(5, "I2S1_MCK"),
1293+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"),
1294+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR0")
1295+ ),
1296+
1297+ MTK_PIN(
1298+ 112, "GPIO112",
1299+ MTK_EINT_FUNCTION(0, 112),
1300+ DRV_GRP4,
1301+ MTK_FUNCTION(0, "GPIO112"),
1302+ MTK_FUNCTION(1, "DPI_DATA9"),
1303+ MTK_FUNCTION(2, "TP_URXD2_AO"),
1304+ MTK_FUNCTION(3, "URXD1"),
1305+ MTK_FUNCTION(4, "I2S3_LRCK"),
1306+ MTK_FUNCTION(5, "I2S1_LRCK"),
1307+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"),
1308+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR1")
1309+ ),
1310+
1311+ MTK_PIN(
1312+ 113, "GPIO113",
1313+ MTK_EINT_FUNCTION(0, 113),
1314+ DRV_GRP4,
1315+ MTK_FUNCTION(0, "GPIO113"),
1316+ MTK_FUNCTION(1, "DPI_DATA10"),
1317+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
1318+ MTK_FUNCTION(3, "UTXD1"),
1319+ MTK_FUNCTION(4, "I2S3_DO"),
1320+ MTK_FUNCTION(5, "I2S1_DO"),
1321+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"),
1322+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR2")
1323+ ),
1324+
1325+ MTK_PIN(
1326+ 114, "GPIO114",
1327+ MTK_EINT_FUNCTION(0, 114),
1328+ DRV_GRP4,
1329+ MTK_FUNCTION(0, "GPIO114"),
1330+ MTK_FUNCTION(1, "DPI_DATA11"),
1331+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"),
1332+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR3")
1333+ ),
1334+
1335+ MTK_PIN(
1336+ 115, "GPIO115",
1337+ MTK_EINT_FUNCTION(0, 115),
1338+ DRV_GRP4,
1339+ MTK_FUNCTION(0, "GPIO115"),
1340+ MTK_FUNCTION(1, "PCM_CLK"),
1341+ MTK_FUNCTION(2, "I2S0_BCK"),
1342+ MTK_FUNCTION(3, "I2S2_BCK")
1343+ ),
1344+
1345+ MTK_PIN(
1346+ 116, "GPIO116",
1347+ MTK_EINT_FUNCTION(0, 116),
1348+ DRV_GRP4,
1349+ MTK_FUNCTION(0, "GPIO116"),
1350+ MTK_FUNCTION(1, "PCM_SYNC"),
1351+ MTK_FUNCTION(2, "I2S0_LRCK"),
1352+ MTK_FUNCTION(3, "I2S2_LRCK")
1353+ ),
1354+
1355+ MTK_PIN(
1356+ 117, "GPIO117",
1357+ MTK_EINT_FUNCTION(0, 117),
1358+ DRV_GRP4,
1359+ MTK_FUNCTION(0, "GPIO117"),
1360+ MTK_FUNCTION(1, "PCM_DI"),
1361+ MTK_FUNCTION(2, "I2S0_DI"),
1362+ MTK_FUNCTION(3, "I2S2_DI")
1363+ ),
1364+
1365+ MTK_PIN(
1366+ 118, "GPIO118",
1367+ MTK_EINT_FUNCTION(0, 118),
1368+ DRV_GRP4,
1369+ MTK_FUNCTION(0, "GPIO118"),
1370+ MTK_FUNCTION(1, "PCM_DO"),
1371+ MTK_FUNCTION(2, "I2S0_MCK"),
1372+ MTK_FUNCTION(3, "I2S2_MCK"),
1373+ MTK_FUNCTION(4, "I2S3_DO"),
1374+ MTK_FUNCTION(5, "I2S1_DO")
1375+ ),
1376+
1377+ MTK_PIN(
1378+ 119, "GPIO119",
1379+ MTK_EINT_FUNCTION(0, 119),
1380+ DRV_GRP4,
1381+ MTK_FUNCTION(0, "GPIO119"),
1382+ MTK_FUNCTION(1, "JTMS_SEL1"),
1383+ MTK_FUNCTION(2, "UDI_TMS"),
1384+ MTK_FUNCTION(3, "DFD_TMS"),
1385+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
1386+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
1387+ MTK_FUNCTION(6, "ADSP_JTAG_TMS")
1388+ ),
1389+
1390+ MTK_PIN(
1391+ 120, "GPIO120",
1392+ MTK_EINT_FUNCTION(0, 120),
1393+ DRV_GRP4,
1394+ MTK_FUNCTION(0, "GPIO120"),
1395+ MTK_FUNCTION(1, "JTCK_SEL1"),
1396+ MTK_FUNCTION(2, "UDI_TCK"),
1397+ MTK_FUNCTION(3, "DFD_TCK_XI"),
1398+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
1399+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
1400+ MTK_FUNCTION(6, "ADSP_JTAG_TCK")
1401+ ),
1402+
1403+ MTK_PIN(
1404+ 121, "GPIO121",
1405+ MTK_EINT_FUNCTION(0, 121),
1406+ DRV_GRP4,
1407+ MTK_FUNCTION(0, "GPIO121"),
1408+ MTK_FUNCTION(1, "JTDI_SEL1"),
1409+ MTK_FUNCTION(2, "UDI_TDI"),
1410+ MTK_FUNCTION(3, "DFD_TDI"),
1411+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
1412+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
1413+ MTK_FUNCTION(6, "ADSP_JTAG_TDI")
1414+ ),
1415+
1416+ MTK_PIN(
1417+ 122, "GPIO122",
1418+ MTK_EINT_FUNCTION(0, 122),
1419+ DRV_GRP4,
1420+ MTK_FUNCTION(0, "GPIO122"),
1421+ MTK_FUNCTION(1, "JTDO_SEL1"),
1422+ MTK_FUNCTION(2, "UDI_TDO"),
1423+ MTK_FUNCTION(3, "DFD_TDO"),
1424+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
1425+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
1426+ MTK_FUNCTION(6, "ADSP_JTAG_TDO")
1427+ ),
1428+
1429+ MTK_PIN(
1430+ 123, "GPIO123",
1431+ MTK_EINT_FUNCTION(0, 123),
1432+ DRV_GRP4,
1433+ MTK_FUNCTION(0, "GPIO123"),
1434+ MTK_FUNCTION(1, "JTRSTN_SEL1"),
1435+ MTK_FUNCTION(2, "UDI_NTRST"),
1436+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
1437+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
1438+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN")
1439+ ),
1440+
1441+ MTK_PIN(
1442+ 124, "GPIO124",
1443+ MTK_EINT_FUNCTION(0, 124),
1444+ DRV_GRP4,
1445+ MTK_FUNCTION(0, "GPIO124"),
1446+ MTK_FUNCTION(1, "CMMCLK0"),
1447+ MTK_FUNCTION(2, "CLKM0"),
1448+ MTK_FUNCTION(3, "PWM0")
1449+ ),
1450+
1451+ MTK_PIN(
1452+ 125, "GPIO125",
1453+ MTK_EINT_FUNCTION(0, 125),
1454+ DRV_GRP4,
1455+ MTK_FUNCTION(0, "GPIO125"),
1456+ MTK_FUNCTION(1, "CMMCLK1"),
1457+ MTK_FUNCTION(2, "CLKM1"),
1458+ MTK_FUNCTION(3, "PWM1"),
1459+ MTK_FUNCTION(7, "dbg_mon_b0")
1460+ ),
1461+
1462+ MTK_PIN(
1463+ 126, "GPIO126",
1464+ MTK_EINT_FUNCTION(0, 126),
1465+ DRV_GRP4,
1466+ MTK_FUNCTION(0, "GPIO126"),
1467+ MTK_FUNCTION(1, "CMMCLK2"),
1468+ MTK_FUNCTION(2, "CLKM2"),
1469+ MTK_FUNCTION(3, "PWM2"),
1470+ MTK_FUNCTION(7, "dbg_mon_b1")
1471+ ),
1472+
1473+ MTK_PIN(
1474+ 127, "GPIO127",
1475+ MTK_EINT_FUNCTION(0, 127),
1476+ DRV_GRP4,
1477+ MTK_FUNCTION(0, "GPIO127"),
1478+ MTK_FUNCTION(1, "SCL0"),
1479+ MTK_FUNCTION(4, "SCP_SCL0"),
1480+ MTK_FUNCTION(5, "SCP_SCL1")
1481+ ),
1482+
1483+ MTK_PIN(
1484+ 128, "GPIO128",
1485+ MTK_EINT_FUNCTION(0, 128),
1486+ DRV_GRP4,
1487+ MTK_FUNCTION(0, "GPIO128"),
1488+ MTK_FUNCTION(1, "SDA0"),
1489+ MTK_FUNCTION(4, "SCP_SDA0"),
1490+ MTK_FUNCTION(5, "SCP_SDA1")
1491+ ),
1492+
1493+ MTK_PIN(
1494+ 129, "GPIO129",
1495+ MTK_EINT_FUNCTION(0, 129),
1496+ DRV_GRP4,
1497+ MTK_FUNCTION(0, "GPIO129"),
1498+ MTK_FUNCTION(1, "SCL1"),
1499+ MTK_FUNCTION(4, "SCP_SCL0"),
1500+ MTK_FUNCTION(5, "SCP_SCL1"),
1501+ MTK_FUNCTION(7, "dbg_mon_b4")
1502+ ),
1503+
1504+ MTK_PIN(
1505+ 130, "GPIO130",
1506+ MTK_EINT_FUNCTION(0, 130),
1507+ DRV_GRP4,
1508+ MTK_FUNCTION(0, "GPIO130"),
1509+ MTK_FUNCTION(1, "SDA1"),
1510+ MTK_FUNCTION(4, "SCP_SDA0"),
1511+ MTK_FUNCTION(5, "SCP_SDA1"),
1512+ MTK_FUNCTION(7, "dbg_mon_b5")
1513+ ),
1514+
1515+ MTK_PIN(
1516+ 131, "GPIO131",
1517+ MTK_EINT_FUNCTION(0, 131),
1518+ DRV_GRP4,
1519+ MTK_FUNCTION(0, "GPIO131"),
1520+ MTK_FUNCTION(1, "SCL2"),
1521+ MTK_FUNCTION(2, "SSPM_UTXD_AO"),
1522+ MTK_FUNCTION(3, "CONN_UART0_TXD"),
1523+ MTK_FUNCTION(4, "SCP_SCL0"),
1524+ MTK_FUNCTION(5, "SCP_SCL1"),
1525+ MTK_FUNCTION(7, "dbg_mon_b6")
1526+ ),
1527+
1528+ MTK_PIN(
1529+ 132, "GPIO132",
1530+ MTK_EINT_FUNCTION(0, 132),
1531+ DRV_GRP4,
1532+ MTK_FUNCTION(0, "GPIO132"),
1533+ MTK_FUNCTION(1, "SDA2"),
1534+ MTK_FUNCTION(2, "SSPM_URXD_AO"),
1535+ MTK_FUNCTION(3, "CONN_UART0_RXD"),
1536+ MTK_FUNCTION(4, "SCP_SDA0"),
1537+ MTK_FUNCTION(5, "SCP_SDA1"),
1538+ MTK_FUNCTION(7, "dbg_mon_b7")
1539+ ),
1540+
1541+ MTK_PIN(
1542+ 133, "GPIO133",
1543+ MTK_EINT_FUNCTION(0, 133),
1544+ DRV_GRP4,
1545+ MTK_FUNCTION(0, "GPIO133"),
1546+ MTK_FUNCTION(1, "SCL3"),
1547+ MTK_FUNCTION(4, "SCP_SCL0"),
1548+ MTK_FUNCTION(5, "SCP_SCL1"),
1549+ MTK_FUNCTION(7, "dbg_mon_b8")
1550+ ),
1551+
1552+ MTK_PIN(
1553+ 134, "GPIO134",
1554+ MTK_EINT_FUNCTION(0, 134),
1555+ DRV_GRP4,
1556+ MTK_FUNCTION(0, "GPIO134"),
1557+ MTK_FUNCTION(1, "SDA3"),
1558+ MTK_FUNCTION(3, "GPS_PPS"),
1559+ MTK_FUNCTION(4, "SCP_SDA0"),
1560+ MTK_FUNCTION(5, "SCP_SDA1"),
1561+ MTK_FUNCTION(7, "dbg_mon_b9")
1562+ ),
1563+
1564+ MTK_PIN(
1565+ 135, "GPIO135",
1566+ MTK_EINT_FUNCTION(0, 135),
1567+ DRV_GRP4,
1568+ MTK_FUNCTION(0, "GPIO135"),
1569+ MTK_FUNCTION(1, "SCL4"),
1570+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
1571+ MTK_FUNCTION(3, "UTXD1"),
1572+ MTK_FUNCTION(4, "SCP_SCL0"),
1573+ MTK_FUNCTION(5, "SCP_SCL1"),
1574+ MTK_FUNCTION(7, "dbg_mon_b10")
1575+ ),
1576+
1577+ MTK_PIN(
1578+ 136, "GPIO136",
1579+ MTK_EINT_FUNCTION(0, 136),
1580+ DRV_GRP4,
1581+ MTK_FUNCTION(0, "GPIO136"),
1582+ MTK_FUNCTION(1, "SDA4"),
1583+ MTK_FUNCTION(2, "TP_URXD1_AO"),
1584+ MTK_FUNCTION(3, "URXD1"),
1585+ MTK_FUNCTION(4, "SCP_SDA0"),
1586+ MTK_FUNCTION(5, "SCP_SDA1"),
1587+ MTK_FUNCTION(7, "dbg_mon_b11")
1588+ ),
1589+
1590+ MTK_PIN(
1591+ 137, "GPIO137",
1592+ MTK_EINT_FUNCTION(0, 137),
1593+ DRV_GRP4,
1594+ MTK_FUNCTION(0, "GPIO137"),
1595+ MTK_FUNCTION(1, "SCL5"),
1596+ MTK_FUNCTION(2, "UTXD2"),
1597+ MTK_FUNCTION(3, "UCTS1"),
1598+ MTK_FUNCTION(4, "SCP_SCL0"),
1599+ MTK_FUNCTION(5, "SCP_SCL1")
1600+ ),
1601+
1602+ MTK_PIN(
1603+ 138, "GPIO138",
1604+ MTK_EINT_FUNCTION(0, 138),
1605+ DRV_GRP4,
1606+ MTK_FUNCTION(0, "GPIO138"),
1607+ MTK_FUNCTION(1, "SDA5"),
1608+ MTK_FUNCTION(2, "URXD2"),
1609+ MTK_FUNCTION(3, "URTS1"),
1610+ MTK_FUNCTION(4, "SCP_SDA0"),
1611+ MTK_FUNCTION(5, "SCP_SDA1")
1612+ ),
1613+
1614+ MTK_PIN(
1615+ 139, "GPIO139",
1616+ MTK_EINT_FUNCTION(0, 139),
1617+ DRV_GRP4,
1618+ MTK_FUNCTION(0, "GPIO139"),
1619+ MTK_FUNCTION(1, "SCL6"),
1620+ MTK_FUNCTION(2, "UTXD1"),
1621+ MTK_FUNCTION(3, "TP_UTXD1_AO"),
1622+ MTK_FUNCTION(4, "SCP_SCL0"),
1623+ MTK_FUNCTION(5, "SCP_SCL1"),
1624+ MTK_FUNCTION(7, "dbg_mon_b12")
1625+ ),
1626+
1627+ MTK_PIN(
1628+ 140, "GPIO140",
1629+ MTK_EINT_FUNCTION(0, 140),
1630+ DRV_GRP4,
1631+ MTK_FUNCTION(0, "GPIO140"),
1632+ MTK_FUNCTION(1, "SDA6"),
1633+ MTK_FUNCTION(2, "URXD1"),
1634+ MTK_FUNCTION(3, "TP_URXD1_AO"),
1635+ MTK_FUNCTION(4, "SCP_SDA0"),
1636+ MTK_FUNCTION(5, "SCP_SDA1"),
1637+ MTK_FUNCTION(7, "dbg_mon_b13")
1638+ ),
1639+
1640+ MTK_PIN(
1641+ 141, "GPIO141",
1642+ MTK_EINT_FUNCTION(0, 141),
1643+ DRV_GRP4,
1644+ MTK_FUNCTION(0, "GPIO141"),
1645+ MTK_FUNCTION(1, "SCL7"),
1646+ MTK_FUNCTION(2, "URTS0"),
1647+ MTK_FUNCTION(3, "TP_URTS1_AO"),
1648+ MTK_FUNCTION(4, "SCP_SCL0"),
1649+ MTK_FUNCTION(5, "SCP_SCL1"),
1650+ MTK_FUNCTION(6, "UDI_TCK"),
1651+ MTK_FUNCTION(7, "dbg_mon_b14")
1652+ ),
1653+
1654+ MTK_PIN(
1655+ 142, "GPIO142",
1656+ MTK_EINT_FUNCTION(0, 142),
1657+ DRV_GRP4,
1658+ MTK_FUNCTION(0, "GPIO142"),
1659+ MTK_FUNCTION(1, "SDA7"),
1660+ MTK_FUNCTION(2, "UCTS0"),
1661+ MTK_FUNCTION(3, "TP_UCTS1_AO"),
1662+ MTK_FUNCTION(4, "SCP_SDA0"),
1663+ MTK_FUNCTION(5, "SCP_SDA1")
1664+ ),
1665+
1666+ MTK_PIN(
1667+ 143, "GPIO143",
1668+ MTK_EINT_FUNCTION(0, 143),
1669+ DRV_GRP4,
1670+ MTK_FUNCTION(0, "GPIO143"),
1671+ MTK_FUNCTION(1, "SCL8"),
1672+ MTK_FUNCTION(4, "SCP_SCL0"),
1673+ MTK_FUNCTION(5, "SCP_SCL1"),
1674+ MTK_FUNCTION(7, "dbg_mon_b16")
1675+ ),
1676+
1677+ MTK_PIN(
1678+ 144, "GPIO144",
1679+ MTK_EINT_FUNCTION(0, 144),
1680+ DRV_GRP4,
1681+ MTK_FUNCTION(0, "GPIO144"),
1682+ MTK_FUNCTION(1, "SDA8"),
1683+ MTK_FUNCTION(4, "SCP_SDA0"),
1684+ MTK_FUNCTION(5, "SCP_SDA1"),
1685+ MTK_FUNCTION(7, "dbg_mon_b17")
1686+ ),
1687+
1688+ MTK_PIN(
1689+ 145, "GPIO145",
1690+ MTK_EINT_FUNCTION(0, 145),
1691+ DRV_GRP4,
1692+ MTK_FUNCTION(0, "GPIO145"),
1693+ MTK_FUNCTION(1, "SCL9"),
1694+ MTK_FUNCTION(2, "CMVREF1"),
1695+ MTK_FUNCTION(3, "GPS_PPS"),
1696+ MTK_FUNCTION(4, "SCP_SCL0"),
1697+ MTK_FUNCTION(5, "SCP_SCL1"),
1698+ MTK_FUNCTION(7, "dbg_mon_b18")
1699+ ),
1700+
1701+ MTK_PIN(
1702+ 146, "GPIO146",
1703+ MTK_EINT_FUNCTION(0, 146),
1704+ DRV_GRP4,
1705+ MTK_FUNCTION(0, "GPIO146"),
1706+ MTK_FUNCTION(1, "SDA9"),
1707+ MTK_FUNCTION(2, "CMVREF0"),
1708+ MTK_FUNCTION(4, "SCP_SDA0"),
1709+ MTK_FUNCTION(5, "SCP_SDA1"),
1710+ MTK_FUNCTION(7, "dbg_mon_b19")
1711+ ),
1712+
1713+ MTK_PIN(
1714+ 147, "GPIO147",
1715+ MTK_EINT_FUNCTION(0, 147),
1716+ DRV_GRP4,
1717+ MTK_FUNCTION(0, "GPIO147"),
1718+ MTK_FUNCTION(1, "CMFLASH0"),
1719+ MTK_FUNCTION(2, "LVTS_SDI"),
1720+ MTK_FUNCTION(3, "DPI_DATA12"),
1721+ MTK_FUNCTION(4, "TP_GPIO0_AO"),
1722+ MTK_FUNCTION(5, "ANT_SEL3"),
1723+ MTK_FUNCTION(6, "DFD_TCK_XI"),
1724+ MTK_FUNCTION(7, "dbg_mon_b20")
1725+ ),
1726+
1727+ MTK_PIN(
1728+ 148, "GPIO148",
1729+ MTK_EINT_FUNCTION(0, 148),
1730+ DRV_GRP4,
1731+ MTK_FUNCTION(0, "GPIO148"),
1732+ MTK_FUNCTION(1, "CMFLASH1"),
1733+ MTK_FUNCTION(2, "LVTS_SCF"),
1734+ MTK_FUNCTION(3, "DPI_DATA13"),
1735+ MTK_FUNCTION(4, "TP_GPIO1_AO"),
1736+ MTK_FUNCTION(5, "ANT_SEL4"),
1737+ MTK_FUNCTION(6, "DFD_TMS"),
1738+ MTK_FUNCTION(7, "dbg_mon_b21")
1739+ ),
1740+
1741+ MTK_PIN(
1742+ 149, "GPIO149",
1743+ MTK_EINT_FUNCTION(0, 149),
1744+ DRV_GRP4,
1745+ MTK_FUNCTION(0, "GPIO149"),
1746+ MTK_FUNCTION(1, "CMFLASH2"),
1747+ MTK_FUNCTION(2, "CLKM0"),
1748+ MTK_FUNCTION(3, "DPI_DATA14"),
1749+ MTK_FUNCTION(4, "TP_GPIO2_AO"),
1750+ MTK_FUNCTION(5, "ANT_SEL5"),
1751+ MTK_FUNCTION(6, "DFD_TDI"),
1752+ MTK_FUNCTION(7, "dbg_mon_b22")
1753+ ),
1754+
1755+ MTK_PIN(
1756+ 150, "GPIO150",
1757+ MTK_EINT_FUNCTION(0, 150),
1758+ DRV_GRP4,
1759+ MTK_FUNCTION(0, "GPIO150"),
1760+ MTK_FUNCTION(2, "CLKM1"),
1761+ MTK_FUNCTION(3, "DPI_DATA15"),
1762+ MTK_FUNCTION(4, "TP_GPIO3_AO"),
1763+ MTK_FUNCTION(5, "ANT_SEL6"),
1764+ MTK_FUNCTION(6, "DFD_TDO"),
1765+ MTK_FUNCTION(7, "dbg_mon_b23")
1766+ ),
1767+
1768+ MTK_PIN(
1769+ 151, "GPIO151",
1770+ MTK_EINT_FUNCTION(0, 151),
1771+ DRV_GRP4,
1772+ MTK_FUNCTION(0, "GPIO151"),
1773+ MTK_FUNCTION(1, "GPS_L1_ELNA_EN"),
1774+ MTK_FUNCTION(2, "CLKM2"),
1775+ MTK_FUNCTION(3, "DPI_DATA16"),
1776+ MTK_FUNCTION(4, "TP_GPIO4_AO"),
1777+ MTK_FUNCTION(5, "ANT_SEL7"),
1778+ MTK_FUNCTION(6, "UDI_TMS"),
1779+ MTK_FUNCTION(7, "dbg_mon_b24")
1780+ ),
1781+
1782+ MTK_PIN(
1783+ 152, "GPIO152",
1784+ MTK_EINT_FUNCTION(0, 152),
1785+ DRV_GRP4,
1786+ MTK_FUNCTION(0, "GPIO152"),
1787+ MTK_FUNCTION(2, "CLKM3"),
1788+ MTK_FUNCTION(3, "DPI_DATA17"),
1789+ MTK_FUNCTION(4, "TP_GPIO5_AO")
1790+ ),
1791+
1792+ MTK_PIN(
1793+ 153, "GPIO153",
1794+ MTK_EINT_FUNCTION(0, 153),
1795+ DRV_GRP4,
1796+ MTK_FUNCTION(0, "GPIO153"),
1797+ MTK_FUNCTION(1, "CONN_TCXOENA_REQ"),
1798+ MTK_FUNCTION(3, "DPI_DATA18"),
1799+ MTK_FUNCTION(4, "TP_GPIO6_AO"),
1800+ MTK_FUNCTION(6, "UDI_TDI"),
1801+ MTK_FUNCTION(7, "dbg_mon_b26")
1802+ ),
1803+
1804+ MTK_PIN(
1805+ 154, "GPIO154",
1806+ MTK_EINT_FUNCTION(0, 154),
1807+ DRV_GRP4,
1808+ MTK_FUNCTION(0, "GPIO154"),
1809+ MTK_FUNCTION(1, "PWM0"),
1810+ MTK_FUNCTION(2, "CMVREF2"),
1811+ MTK_FUNCTION(3, "DPI_DATA19"),
1812+ MTK_FUNCTION(4, "TP_GPIO7_AO"),
1813+ MTK_FUNCTION(6, "UDI_TDO"),
1814+ MTK_FUNCTION(7, "dbg_mon_b27")
1815+ ),
1816+
1817+ MTK_PIN(
1818+ 155, "GPIO155",
1819+ MTK_EINT_FUNCTION(0, 155),
1820+ DRV_GRP4,
1821+ MTK_FUNCTION(0, "GPIO155"),
1822+ MTK_FUNCTION(1, "PWM1"),
1823+ MTK_FUNCTION(2, "CMVREF1"),
1824+ MTK_FUNCTION(3, "DPI_DATA20"),
1825+ MTK_FUNCTION(6, "UDI_NTRST"),
1826+ MTK_FUNCTION(7, "dbg_mon_b28")
1827+ ),
1828+
1829+ MTK_PIN(
1830+ 156, "GPIO156",
1831+ MTK_EINT_FUNCTION(0, 156),
1832+ DRV_GRP4,
1833+ MTK_FUNCTION(0, "GPIO156"),
1834+ MTK_FUNCTION(1, "PWM2"),
1835+ MTK_FUNCTION(2, "CMVREF0"),
1836+ MTK_FUNCTION(3, "DPI_DATA21")
1837+ ),
1838+
1839+ MTK_PIN(
1840+ 157, "GPIO157",
1841+ MTK_EINT_FUNCTION(0, 157),
1842+ DRV_GRP4,
1843+ MTK_FUNCTION(0, "GPIO157"),
1844+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
1845+ ),
1846+
1847+ MTK_PIN(
1848+ 158, "GPIO158",
1849+ MTK_EINT_FUNCTION(0, 158),
1850+ DRV_GRP4,
1851+ MTK_FUNCTION(0, "GPIO158"),
1852+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
1853+ ),
1854+
1855+ MTK_PIN(
1856+ 159, "GPIO159",
1857+ MTK_EINT_FUNCTION(0, 159),
1858+ DRV_GRP4,
1859+ MTK_FUNCTION(0, "GPIO159"),
1860+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
1861+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
1862+ ),
1863+
1864+ MTK_PIN(
1865+ 160, "GPIO160",
1866+ MTK_EINT_FUNCTION(0, 160),
1867+ DRV_GRP4,
1868+ MTK_FUNCTION(0, "GPIO160"),
1869+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
1870+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
1871+ ),
1872+
1873+ MTK_PIN(
1874+ 161, "GPIO161",
1875+ MTK_EINT_FUNCTION(0, 161),
1876+ DRV_GRP4,
1877+ MTK_FUNCTION(0, "GPIO161"),
1878+ MTK_FUNCTION(1, "SRCLKENA0")
1879+ ),
1880+
1881+ MTK_PIN(
1882+ 162, "GPIO162",
1883+ MTK_EINT_FUNCTION(0, 162),
1884+ DRV_GRP4,
1885+ MTK_FUNCTION(0, "GPIO162"),
1886+ MTK_FUNCTION(1, "SRCLKENA1"),
1887+ MTK_FUNCTION(7, "dbg_mon_a31")
1888+ ),
1889+
1890+ MTK_PIN(
1891+ 163, "GPIO163",
1892+ MTK_EINT_FUNCTION(0, 163),
1893+ DRV_GRP4,
1894+ MTK_FUNCTION(0, "GPIO163"),
1895+ MTK_FUNCTION(1, "SCP_VREQ_VAO"),
1896+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ")
1897+ ),
1898+
1899+ MTK_PIN(
1900+ 164, "GPIO164",
1901+ MTK_EINT_FUNCTION(0, 164),
1902+ DRV_GRP4,
1903+ MTK_FUNCTION(0, "GPIO164"),
1904+ MTK_FUNCTION(1, "RTC32K_CK")
1905+ ),
1906+
1907+ MTK_PIN(
1908+ 165, "GPIO165",
1909+ MTK_EINT_FUNCTION(0, 165),
1910+ DRV_GRP4,
1911+ MTK_FUNCTION(0, "GPIO165"),
1912+ MTK_FUNCTION(1, "WATCHDOG")
1913+ ),
1914+
1915+ MTK_PIN(
1916+ 166, "GPIO166",
1917+ MTK_EINT_FUNCTION(0, 166),
1918+ DRV_GRP4,
1919+ MTK_FUNCTION(0, "GPIO166"),
1920+ MTK_FUNCTION(1, "AUD_CLK_MOSI"),
1921+ MTK_FUNCTION(2, "AUD_CLK_MISO"),
1922+ MTK_FUNCTION(3, "I2S1_MCK")
1923+ ),
1924+
1925+ MTK_PIN(
1926+ 167, "GPIO167",
1927+ MTK_EINT_FUNCTION(0, 167),
1928+ DRV_GRP4,
1929+ MTK_FUNCTION(0, "GPIO167"),
1930+ MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
1931+ MTK_FUNCTION(2, "AUD_SYNC_MISO"),
1932+ MTK_FUNCTION(3, "I2S1_BCK")
1933+ ),
1934+
1935+ MTK_PIN(
1936+ 168, "GPIO168",
1937+ MTK_EINT_FUNCTION(0, 168),
1938+ DRV_GRP4,
1939+ MTK_FUNCTION(0, "GPIO168"),
1940+ MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
1941+ MTK_FUNCTION(2, "AUD_DAT_MISO0"),
1942+ MTK_FUNCTION(3, "I2S1_LRCK")
1943+ ),
1944+
1945+ MTK_PIN(
1946+ 169, "GPIO169",
1947+ MTK_EINT_FUNCTION(0, 169),
1948+ DRV_GRP4,
1949+ MTK_FUNCTION(0, "GPIO169"),
1950+ MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
1951+ MTK_FUNCTION(2, "AUD_DAT_MISO1"),
1952+ MTK_FUNCTION(3, "I2S1_DO")
1953+ ),
1954+
1955+ MTK_PIN(
1956+ 170, "GPIO170",
1957+ MTK_EINT_FUNCTION(0, 170),
1958+ DRV_GRP4,
1959+ MTK_FUNCTION(0, "GPIO170"),
1960+ MTK_FUNCTION(1, "AUD_CLK_MISO"),
1961+ MTK_FUNCTION(2, "AUD_CLK_MOSI"),
1962+ MTK_FUNCTION(3, "I2S2_MCK")
1963+ ),
1964+
1965+ MTK_PIN(
1966+ 171, "GPIO171",
1967+ MTK_EINT_FUNCTION(0, 171),
1968+ DRV_GRP4,
1969+ MTK_FUNCTION(0, "GPIO171"),
1970+ MTK_FUNCTION(1, "AUD_SYNC_MISO"),
1971+ MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
1972+ MTK_FUNCTION(3, "I2S2_BCK")
1973+ ),
1974+
1975+ MTK_PIN(
1976+ 172, "GPIO172",
1977+ MTK_EINT_FUNCTION(0, 172),
1978+ DRV_GRP4,
1979+ MTK_FUNCTION(0, "GPIO172"),
1980+ MTK_FUNCTION(1, "AUD_DAT_MISO0"),
1981+ MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
1982+ MTK_FUNCTION(3, "I2S2_LRCK"),
1983+ MTK_FUNCTION(4, "VOW_DAT_MISO")
1984+ ),
1985+
1986+ MTK_PIN(
1987+ 173, "GPIO173",
1988+ MTK_EINT_FUNCTION(0, 173),
1989+ DRV_GRP4,
1990+ MTK_FUNCTION(0, "GPIO173"),
1991+ MTK_FUNCTION(1, "AUD_DAT_MISO1"),
1992+ MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
1993+ MTK_FUNCTION(3, "I2S2_DI"),
1994+ MTK_FUNCTION(4, "VOW_CLK_MISO")
1995+ ),
1996+
1997+ MTK_PIN(
1998+ 174, "GPIO174",
1999+ MTK_EINT_FUNCTION(0, 174),
2000+ DRV_GRP4,
2001+ MTK_FUNCTION(0, "GPIO174"),
2002+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
2003+ MTK_FUNCTION(2, "AUXIF_CLK"),
2004+ MTK_FUNCTION(3, "DFD_TCK_XI"),
2005+ MTK_FUNCTION(7, "dbg_mon_b3")
2006+ ),
2007+
2008+ MTK_PIN(
2009+ 175, "GPIO175",
2010+ MTK_EINT_FUNCTION(0, 175),
2011+ DRV_GRP4,
2012+ MTK_FUNCTION(0, "GPIO175"),
2013+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
2014+ MTK_FUNCTION(2, "AUXIF_ST"),
2015+ MTK_FUNCTION(3, "DFD_TMS"),
2016+ MTK_FUNCTION(7, "dbg_mon_b15")
2017+ ),
2018+
2019+ MTK_PIN(
2020+ 176, "GPIO176",
2021+ MTK_EINT_FUNCTION(0, 176),
2022+ DRV_GRP4,
2023+ MTK_FUNCTION(0, "GPIO176"),
2024+ MTK_FUNCTION(1, "CONN_BT_CLK"),
2025+ MTK_FUNCTION(3, "DFD_TDI"),
2026+ MTK_FUNCTION(7, "dbg_mon_b2")
2027+ ),
2028+
2029+ MTK_PIN(
2030+ 177, "GPIO177",
2031+ MTK_EINT_FUNCTION(0, 177),
2032+ DRV_GRP4,
2033+ MTK_FUNCTION(0, "GPIO177"),
2034+ MTK_FUNCTION(1, "CONN_BT_DATA"),
2035+ MTK_FUNCTION(3, "DFD_TDO")
2036+ ),
2037+
2038+ MTK_PIN(
2039+ 178, "GPIO178",
2040+ MTK_EINT_FUNCTION(0, 178),
2041+ DRV_GRP4,
2042+ MTK_FUNCTION(0, "GPIO178"),
2043+ MTK_FUNCTION(1, "CONN_HRST_B"),
2044+ MTK_FUNCTION(3, "UDI_TMS"),
2045+ MTK_FUNCTION(7, "dbg_mon_b25")
2046+ ),
2047+
2048+ MTK_PIN(
2049+ 179, "GPIO179",
2050+ MTK_EINT_FUNCTION(0, 179),
2051+ DRV_GRP4,
2052+ MTK_FUNCTION(0, "GPIO179"),
2053+ MTK_FUNCTION(1, "CONN_WB_PTA"),
2054+ MTK_FUNCTION(3, "UDI_TCK"),
2055+ MTK_FUNCTION(7, "dbg_mon_b29")
2056+ ),
2057+
2058+ MTK_PIN(
2059+ 180, "GPIO180",
2060+ MTK_EINT_FUNCTION(0, 180),
2061+ DRV_GRP4,
2062+ MTK_FUNCTION(0, "GPIO180"),
2063+ MTK_FUNCTION(1, "CONN_WF_CTRL0"),
2064+ MTK_FUNCTION(3, "UDI_TDI")
2065+ ),
2066+
2067+ MTK_PIN(
2068+ 181, "GPIO181",
2069+ MTK_EINT_FUNCTION(0, 181),
2070+ DRV_GRP4,
2071+ MTK_FUNCTION(0, "GPIO181"),
2072+ MTK_FUNCTION(1, "CONN_WF_CTRL1"),
2073+ MTK_FUNCTION(3, "UDI_TDO")
2074+ ),
2075+
2076+ MTK_PIN(
2077+ 182, "GPIO182",
2078+ MTK_EINT_FUNCTION(0, 182),
2079+ DRV_GRP4,
2080+ MTK_FUNCTION(0, "GPIO182"),
2081+ MTK_FUNCTION(1, "CONN_WF_CTRL2"),
2082+ MTK_FUNCTION(3, "UDI_NTRST")
2083+ ),
2084+
2085+ MTK_PIN(
2086+ 183, "GPIO183",
2087+ MTK_EINT_FUNCTION(0, 183),
2088+ DRV_GRP4,
2089+ MTK_FUNCTION(0, "GPIO183"),
2090+ MTK_FUNCTION(1, "SPMI_SCL")
2091+ ),
2092+
2093+ MTK_PIN(
2094+ 184, "GPIO184",
2095+ MTK_EINT_FUNCTION(0, 184),
2096+ DRV_GRP4,
2097+ MTK_FUNCTION(0, "GPIO184"),
2098+ MTK_FUNCTION(1, "SPMI_SDA")
2099+ ),
2100+
2101+ MTK_PIN(
2102+ 185, "GPIO185",
2103+ MTK_EINT_FUNCTION(0, 197),
2104+ DRV_FIXED,
2105+ MTK_FUNCTION(0, NULL)
2106+ ),
2107+
2108+ MTK_PIN(
2109+ 186, "GPIO186",
2110+ MTK_EINT_FUNCTION(0, 198),
2111+ DRV_FIXED,
2112+ MTK_FUNCTION(0, NULL)
2113+ ),
2114+
2115+ MTK_PIN(
2116+ 187, "GPIO187",
2117+ MTK_EINT_FUNCTION(0, 199),
2118+ DRV_FIXED,
2119+ MTK_FUNCTION(0, NULL)
2120+ ),
2121+
2122+ MTK_PIN(
2123+ 188, "GPIO188",
2124+ MTK_EINT_FUNCTION(0, 200),
2125+ DRV_FIXED,
2126+ MTK_FUNCTION(0, NULL)
2127+ ),
2128+
2129+ MTK_PIN(
2130+ 189, "GPIO189",
2131+ MTK_EINT_FUNCTION(0, 201),
2132+ DRV_FIXED,
2133+ MTK_FUNCTION(0, NULL)
2134+ ),
2135+
2136+ MTK_PIN(
2137+ 190, "GPIO190",
2138+ MTK_EINT_FUNCTION(0, 202),
2139+ DRV_FIXED,
2140+ MTK_FUNCTION(0, NULL)
2141+ ),
2142+
2143+ MTK_PIN(
2144+ 191, "GPIO191",
2145+ MTK_EINT_FUNCTION(0, 203),
2146+ DRV_FIXED,
2147+ MTK_FUNCTION(0, NULL)
2148+ ),
2149+
2150+ MTK_PIN(
2151+ 192, "GPIO192",
2152+ MTK_EINT_FUNCTION(0, 204),
2153+ DRV_FIXED,
2154+ MTK_FUNCTION(0, NULL)
2155+ ),
2156+
2157+ MTK_PIN(
2158+ 193, "GPIO193",
2159+ MTK_EINT_FUNCTION(0, 205),
2160+ DRV_FIXED,
2161+ MTK_FUNCTION(0, NULL)
2162+ ),
2163+
2164+ MTK_PIN(
2165+ 194, "GPIO194",
2166+ MTK_EINT_FUNCTION(0, 206),
2167+ DRV_FIXED,
2168+ MTK_FUNCTION(0, NULL)
2169+ ),
2170+
2171+ MTK_PIN(
2172+ 195, "GPIO195",
2173+ MTK_EINT_FUNCTION(0, 207),
2174+ DRV_FIXED,
2175+ MTK_FUNCTION(0, NULL)
2176+ ),
2177+
2178+ MTK_PIN(
2179+ 196, "GPIO196",
2180+ MTK_EINT_FUNCTION(0, 208),
2181+ DRV_FIXED,
2182+ MTK_FUNCTION(0, NULL)
2183+ )
2184+};
2185+
2186+#endif /* __PINCTRL_MTK_MT8186_H */
drivers/pinctrl/mediatek/pinctrl-paris.c+184−117
@@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] = { · 47 unmodified lines
4848 "func12", "func13", "func14", "func15",
4949 };
5050
51+/*
52+ * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
53+ * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
54+ *
55+ * The custom value encodes three hardware bits as follows:
56+ *
57+ * | Bits |
58+ * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
59+ * ------------------------------------------------
60+ * | x | x | 0 | disabled, use standard drive strength
61+ * -------------------------------------
62+ * | 0 | 0 | 1 | 125 uA
63+ * | 0 | 1 | 1 | 250 uA
64+ * | 1 | 0 | 1 | 500 uA
65+ * | 1 | 1 | 1 | 1000 uA
66+ */
67+static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
68+
69+static int mtk_drv_adv_to_uA(int val)
70+{
71+ /* This should never happen. */
72+ if (WARN_ON_ONCE(val < 0 || val > 7))
73+ return -EINVAL;
74+
75+ /* Bit 0 simply enables this hardware part */
76+ if (!(val & BIT(0)))
77+ return -EINVAL;
78+
79+ return mtk_drv_adv_uA[(val >> 1)];
80+}
81+
82+static int mtk_drv_uA_to_adv(int val)
83+{
84+ switch (val) {
85+ case 125:
86+ return 0x1;
87+ case 250:
88+ return 0x3;
89+ case 500:
90+ return 0x5;
91+ case 1000:
92+ return 0x7;
93+ }
94+
95+ return -EINVAL;
96+}
97+
5198 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
5299 struct pinctrl_gpio_range *range,
53100 unsigned int pin)
@@ -79,41 +126,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 25 unmodified lines
79126 {
80127 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
81128 u32 param = pinconf_to_config_param(*config);
82− int pullup, err, reg, ret = 1;
129+ int pullup, reg, err = -ENOTSUPP, ret = 1;
83130 const struct mtk_pin_desc *desc;
84131
85− if (pin >= hw->soc->npins) {
86− err = -EINVAL;
87− goto out;
88− }
132+ if (pin >= hw->soc->npins)
133+ return -EINVAL;
134+
89135 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
90136
91137 switch (param) {
92138 case PIN_CONFIG_BIAS_DISABLE:
93139 case PIN_CONFIG_BIAS_PULL_UP:
94140 case PIN_CONFIG_BIAS_PULL_DOWN:
95− if (hw->soc->bias_get_combo) {
96− err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
97− if (err)
98− goto out;
99− if (param == PIN_CONFIG_BIAS_DISABLE) {
100− if (ret == MTK_PUPD_SET_R1R0_00)
101− ret = MTK_DISABLE;
102− } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
103− /* When desire to get pull-up value, return
104− * error if current setting is pull-down
105− */
106− if (!pullup)
107− err = -EINVAL;
108− } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
109− /* When desire to get pull-down value, return
110− * error if current setting is pull-up
111− */
112− if (pullup)
113− err = -EINVAL;
114− }
115− } else {
116− err = -ENOTSUPP;
141+ if (!hw->soc->bias_get_combo)
142+ break;
143+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
144+ if (err)
145+ break;
146+ if (ret == MTK_PUPD_SET_R1R0_00)
147+ ret = MTK_DISABLE;
148+ if (param == PIN_CONFIG_BIAS_DISABLE) {
149+ if (ret != MTK_DISABLE)
150+ err = -EINVAL;
151+ } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
152+ if (!pullup || ret == MTK_DISABLE)
153+ err = -EINVAL;
154+ } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
155+ if (pullup || ret == MTK_DISABLE)
156+ err = -EINVAL;
117157 }
118158 break;
119159 case PIN_CONFIG_SLEW_RATE:
@@ -123,7 +163,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 3 unmodified lines
123163 case PIN_CONFIG_OUTPUT_ENABLE:
124164 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
125165 if (err)
126− goto out;
166+ break;
127167 /* CONFIG Current direction return value
128168 * ------------- ----------------- ----------------------
129169 * OUTPUT_ENABLE output 1 (= HW value)
@@ -138,23 +178,48 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 8 unmodified lines
138178 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
139179 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
140180 if (err)
141− goto out;
181+ break;
142182 /* return error when in output mode
143183 * because schmitt trigger only work in input mode
144184 */
145185 if (ret) {
146186 err = -EINVAL;
147− goto out;
187+ break;
148188 }
149189
150190 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
151−
152191 break;
153192 case PIN_CONFIG_DRIVE_STRENGTH:
154− if (hw->soc->drive_get)
155− err = hw->soc->drive_get(hw, desc, &ret);
156− else
157− err = -ENOTSUPP;
193+ if (!hw->soc->drive_get)
194+ break;
195+
196+ if (hw->soc->adv_drive_get) {
197+ err = hw->soc->adv_drive_get(hw, desc, &ret);
198+ if (!err) {
199+ err = mtk_drv_adv_to_uA(ret);
200+ if (err > 0) {
201+ /* PIN_CONFIG_DRIVE_STRENGTH_UA used */
202+ err = -EINVAL;
203+ break;
204+ }
205+ }
206+ }
207+
208+ err = hw->soc->drive_get(hw, desc, &ret);
209+ break;
210+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
211+ if (!hw->soc->adv_drive_get)
212+ break;
213+
214+ err = hw->soc->adv_drive_get(hw, desc, &ret);
215+ if (err)
216+ break;
217+ err = mtk_drv_adv_to_uA(ret);
218+ if (err < 0)
219+ break;
220+
221+ ret = err;
222+ err = 0;
158223 break;
159224 case MTK_PIN_CONFIG_TDSEL:
160225 case MTK_PIN_CONFIG_RDSEL:
@@ -164,23 +229,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, · 3 unmodified lines
164229 break;
165230 case MTK_PIN_CONFIG_PU_ADV:
166231 case MTK_PIN_CONFIG_PD_ADV:
167− if (hw->soc->adv_pull_get) {
168− pullup = param == MTK_PIN_CONFIG_PU_ADV;
169− err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
170− } else
171− err = -ENOTSUPP;
232+ if (!hw->soc->adv_pull_get)
233+ break;
234+ pullup = param == MTK_PIN_CONFIG_PU_ADV;
235+ err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
172236 break;
173237 case MTK_PIN_CONFIG_DRV_ADV:
174− if (hw->soc->adv_drive_get)
175− err = hw->soc->adv_drive_get(hw, desc, &ret);
176− else
177− err = -ENOTSUPP;
238+ if (!hw->soc->adv_drive_get)
239+ break;
240+ err = hw->soc->adv_drive_get(hw, desc, &ret);
178241 break;
179− default:
180− err = -ENOTSUPP;
181242 }
182243
183−out:
184244 if (!err)
185245 *config = pinconf_to_config_packed(param, ret);
186246
@@ -188,38 +248,33 @@ out: · 1 unmodified line
188248 }
189249
190250 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
191− enum pin_config_param param,
192− enum pin_config_param arg)
251+ enum pin_config_param param, u32 arg)
193252 {
194253 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
195254 const struct mtk_pin_desc *desc;
196− int err = 0;
255+ int err = -ENOTSUPP;
197256 u32 reg;
198257
199− if (pin >= hw->soc->npins) {
200− err = -EINVAL;
201− goto err;
202− }
258+ if (pin >= hw->soc->npins)
259+ return -EINVAL;
260+
203261 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
204262
205263 switch ((u32)param) {
206264 case PIN_CONFIG_BIAS_DISABLE:
207− if (hw->soc->bias_set_combo)
208− err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
209− else
210− err = -ENOTSUPP;
265+ if (!hw->soc->bias_set_combo)
266+ break;
267+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
211268 break;
212269 case PIN_CONFIG_BIAS_PULL_UP:
213− if (hw->soc->bias_set_combo)
214− err = hw->soc->bias_set_combo(hw, desc, 1, arg);
215− else
216− err = -ENOTSUPP;
270+ if (!hw->soc->bias_set_combo)
271+ break;
272+ err = hw->soc->bias_set_combo(hw, desc, 1, arg);
217273 break;
218274 case PIN_CONFIG_BIAS_PULL_DOWN:
219− if (hw->soc->bias_set_combo)
220− err = hw->soc->bias_set_combo(hw, desc, 0, arg);
221− else
222− err = -ENOTSUPP;
275+ if (!hw->soc->bias_set_combo)
276+ break;
277+ err = hw->soc->bias_set_combo(hw, desc, 0, arg);
223278 break;
224279 case PIN_CONFIG_OUTPUT_ENABLE:
225280 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
@@ -228,7 +283,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 2 unmodified lines
228283 * does not have SMT control
229284 */
230285 if (err != -ENOTSUPP)
231− goto err;
286+ break;
232287
233288 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
234289 MTK_OUTPUT);
@@ -237,7 +292,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 2 unmodified lines
237292 /* regard all non-zero value as enable */
238293 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
239294 if (err)
240− goto err;
295+ break;
241296
242297 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
243298 MTK_INPUT);
@@ -250,7 +305,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 6 unmodified lines
250305 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
251306 arg);
252307 if (err)
253− goto err;
308+ break;
254309
255310 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
256311 MTK_OUTPUT);
@@ -262,15 +317,23 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 5 unmodified lines
262317 */
263318 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
264319 if (err)
265− goto err;
320+ break;
266321
267322 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
268323 break;
269324 case PIN_CONFIG_DRIVE_STRENGTH:
270− if (hw->soc->drive_set)
271− err = hw->soc->drive_set(hw, desc, arg);
272− else
273− err = -ENOTSUPP;
325+ if (!hw->soc->drive_set)
326+ break;
327+ err = hw->soc->drive_set(hw, desc, arg);
328+ break;
329+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
330+ if (!hw->soc->adv_drive_set)
331+ break;
332+
333+ err = mtk_drv_uA_to_adv(arg);
334+ if (err < 0)
335+ break;
336+ err = hw->soc->adv_drive_set(hw, desc, err);
274337 break;
275338 case MTK_PIN_CONFIG_TDSEL:
276339 case MTK_PIN_CONFIG_RDSEL:
@@ -280,26 +343,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 3 unmodified lines
280343 break;
281344 case MTK_PIN_CONFIG_PU_ADV:
282345 case MTK_PIN_CONFIG_PD_ADV:
283− if (hw->soc->adv_pull_set) {
284− bool pullup;
285−
286− pullup = param == MTK_PIN_CONFIG_PU_ADV;
287− err = hw->soc->adv_pull_set(hw, desc, pullup,
288− arg);
289− } else
290− err = -ENOTSUPP;
346+ if (!hw->soc->adv_pull_set)
347+ break;
348+ err = hw->soc->adv_pull_set(hw, desc,
349+ (param == MTK_PIN_CONFIG_PU_ADV),
350+ arg);
291351 break;
292352 case MTK_PIN_CONFIG_DRV_ADV:
293− if (hw->soc->adv_drive_set)
294− err = hw->soc->adv_drive_set(hw, desc, arg);
295− else
296− err = -ENOTSUPP;
353+ if (!hw->soc->adv_drive_set)
354+ break;
355+ err = hw->soc->adv_drive_set(hw, desc, arg);
297356 break;
298− default:
299− err = -ENOTSUPP;
300357 }
301358
302−err:
303359 return err;
304360 }
305361
@@ -586,6 +642,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, · 280 unmodified lines
586642 if (gpio >= hw->soc->npins)
587643 return -EINVAL;
588644
645+ if (mtk_is_virt_gpio(hw, gpio))
646+ return -EINVAL;
647+
589648 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
590649 pinmux = mtk_pctrl_get_pinmux(hw, gpio);
591650 if (pinmux >= hw->soc->nfuncs)
@@ -639,14 +698,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, · 47 unmodified lines
639698 pullen,
640699 pullup);
641700
642− if (r1 != -1) {
643− len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",
644− r1, r0);
645− } else if (rsel != -1) {
646− len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
647− } else {
648− len += scnprintf(buf + len, buf_len - len, "\n");
649− }
701+ if (r1 != -1)
702+ len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
703+ else if (rsel != -1)
704+ len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
650705
651706 return len;
652707 }
@@ -737,10 +792,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, · 84 unmodified lines
737792 unsigned long *config)
738793 {
739794 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
795+ struct mtk_pinctrl_group *grp = &hw->groups[group];
740796
741− *config = hw->groups[group].config;
742−
743− return 0;
797+ /* One pin per group only */
798+ return mtk_pinconf_get(pctldev, grp->pin, config);
744799 }
745800
746801 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
@@ -748,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, · 1 unmodified line
748803 {
749804 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
750805 struct mtk_pinctrl_group *grp = &hw->groups[group];
806+ bool drive_strength_uA_found = false;
807+ bool adv_drve_strength_found = false;
751808 int i, ret;
752809
753810 for (i = 0; i < num_configs; i++) {
@@ -757,9 +814,21 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, · 3 unmodified lines
757814 if (ret < 0)
758815 return ret;
759816
760− grp->config = configs[i];
817+ if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
818+ drive_strength_uA_found = true;
819+ if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
820+ adv_drve_strength_found = true;
761821 }
762822
823+ /*
824+ * Disable advanced drive strength mode if drive-strength-microamp
825+ * is not set. However, mediatek,drive-strength-adv takes precedence
826+ * as its value can explicitly request the mode be enabled or not.
827+ */
828+ if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
829+ !adv_drve_strength_found)
830+ hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
831+
763832 return 0;
764833 }
765834
@@ -952,9 +1021,9 @@ static int mtk_pctrl_build_state(struct platform_device *pdev) · 186 unmodified lines
9521021 return 0;
9531022 }
9541023
955−int mtk_paris_pinctrl_probe(struct platform_device *pdev,
956− const struct mtk_pin_soc *soc)
1024+int mtk_paris_pinctrl_probe(struct platform_device *pdev)
9571025 {
1026+ struct device *dev = &pdev->dev;
9581027 struct pinctrl_pin_desc *pins;
9591028 struct mtk_pinctrl *hw;
9601029 int err, i;
@@ -964,14 +1033,16 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 3 unmodified lines
9641033 return -ENOMEM;
9651034
9661035 platform_set_drvdata(pdev, hw);
967− hw->soc = soc;
1036+
1037+ hw->soc = device_get_match_data(dev);
1038+ if (!hw->soc)
1039+ return -ENOENT;
1040+
9681041 hw->dev = &pdev->dev;
9691042
970− if (!hw->soc->nbase_names) {
971− dev_err(&pdev->dev,
1043+ if (!hw->soc->nbase_names)
1044+ return dev_err_probe(dev, -EINVAL,
9721045 "SoC should be assigned at least one register base\n");
973− return -EINVAL;
974− }
9751046
9761047 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
9771048 sizeof(*hw->base), GFP_KERNEL);
@@ -988,7 +1059,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 10 unmodified lines
9881059 hw->nbase = hw->soc->nbase_names;
9891060
9901061 if (of_find_property(hw->dev->of_node,
991− "mediatek,rsel_resistance_in_si_unit", NULL))
1062+ "mediatek,rsel-resistance-in-si-unit", NULL))
9921063 hw->rsel_si_unit = true;
9931064 else
9941065 hw->rsel_si_unit = false;
@@ -996,10 +1067,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 1 unmodified line
9961067 spin_lock_init(&hw->lock);
9971068
9981069 err = mtk_pctrl_build_state(pdev);
999− if (err) {
1000− dev_err(&pdev->dev, "build state failed: %d\n", err);
1001− return -EINVAL;
1002− }
1070+ if (err)
1071+ return dev_err_probe(dev, err, "build state failed\n");
10031072
10041073 /* Copy from internal struct mtk_pin_desc to register to the core */
10051074 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
@@ -1037,10 +1106,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 31 unmodified lines
10371106
10381107 /* Build gpiochip should be after pinctrl_enable is done */
10391108 err = mtk_build_gpiochip(hw);
1040− if (err) {
1041− dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1042− return err;
1043− }
1109+ if (err)
1110+ return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
10441111
10451112 platform_set_drvdata(pdev, hw);
10461113
drivers/pinctrl/mediatek/pinctrl-paris.h+1−2
@@ -57,8 +57,7 @@ · 56 unmodified lines
5757 id##_funcs, \
5858 }
5959
60−int mtk_paris_pinctrl_probe(struct platform_device *pdev,
61− const struct mtk_pin_soc *soc);
60+int mtk_paris_pinctrl_probe(struct platform_device *pdev);
6261
6362 ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
6463 unsigned int gpio, char *buf, unsigned int bufLen);
drivers/pinctrl/meson/Kconfig+6−0
@@ -61,4 +61,10 @@ config PINCTRL_MESON_A1 · 60 unmodified lines
6161 select PINCTRL_MESON_AXG_PMX
6262 default y
6363
64+config PINCTRL_MESON_S4
65+ tristate "Meson s4 Soc pinctrl driver"
66+ depends on ARM64
67+ select PINCTRL_MESON_AXG_PMX
68+ default y
69+
6470 endif
drivers/pinctrl/meson/Makefile+1−0
@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o · 8 unmodified lines
99 obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
1010 obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
1111 obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
12+obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o
drivers/pinctrl/meson/pinctrl-meson-g12a.c+5−1
@@ -283,6 +283,8 @@ static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; · 282 unmodified lines
283283 static const unsigned int pwm_e_pins[] = { GPIOX_16 };
284284
285285 /* pwm_f */
286+static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 };
287+static const unsigned int pwm_f_a_pins[] = { GPIOA_11 };
286288 static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
287289 static const unsigned int pwm_f_h_pins[] = { GPIOH_5 };
288290
@@ -618,6 +620,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { · 329 unmodified lines
618620 GROUP(tdm_c_dout2_z, 4),
619621 GROUP(tdm_c_dout3_z, 4),
620622 GROUP(mclk1_z, 4),
623+ GROUP(pwm_f_z, 5),
621624
622625 /* bank GPIOX */
623626 GROUP(sdio_d0, 1),
@@ -768,6 +771,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { · 144 unmodified lines
768771 GROUP(tdm_c_dout3_a, 2),
769772 GROUP(mclk0_a, 1),
770773 GROUP(mclk1_a, 2),
774+ GROUP(pwm_f_a, 3),
771775 };
772776
773777 /* uart_ao_a */
@@ -1069,7 +1073,7 @@ static const char * const pwm_e_groups[] = { · 295 unmodified lines
10691073 };
10701074
10711075 static const char * const pwm_f_groups[] = {
1072− "pwm_f_x", "pwm_f_h",
1076+ "pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h",
10731077 };
10741078
10751079 static const char * const cec_ao_a_h_groups[] = {
drivers/pinctrl/meson/pinctrl-meson-s4.c+1232−0
@@ -0,0 +1,1232 @@
1+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+/*
3+ * Pin controller and GPIO driver for Amlogic Meson S4 SoC.
4+ *
5+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
6+ * Author: Qianggui Song <qianggui.song@amlogic.com>
7+ */
8+
9+#include <dt-bindings/gpio/meson-s4-gpio.h>
10+#include "pinctrl-meson.h"
11+#include "pinctrl-meson-axg-pmx.h"
12+
13+static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = {
14+ MESON_PIN(GPIOE_0),
15+ MESON_PIN(GPIOE_1),
16+
17+ MESON_PIN(GPIOB_0),
18+ MESON_PIN(GPIOB_1),
19+ MESON_PIN(GPIOB_2),
20+ MESON_PIN(GPIOB_3),
21+ MESON_PIN(GPIOB_4),
22+ MESON_PIN(GPIOB_5),
23+ MESON_PIN(GPIOB_6),
24+ MESON_PIN(GPIOB_7),
25+ MESON_PIN(GPIOB_8),
26+ MESON_PIN(GPIOB_9),
27+ MESON_PIN(GPIOB_10),
28+ MESON_PIN(GPIOB_11),
29+ MESON_PIN(GPIOB_12),
30+ MESON_PIN(GPIOB_13),
31+
32+ MESON_PIN(GPIOC_0),
33+ MESON_PIN(GPIOC_1),
34+ MESON_PIN(GPIOC_2),
35+ MESON_PIN(GPIOC_3),
36+ MESON_PIN(GPIOC_4),
37+ MESON_PIN(GPIOC_5),
38+ MESON_PIN(GPIOC_6),
39+ MESON_PIN(GPIOC_7),
40+
41+ MESON_PIN(GPIOD_0),
42+ MESON_PIN(GPIOD_1),
43+ MESON_PIN(GPIOD_2),
44+ MESON_PIN(GPIOD_3),
45+ MESON_PIN(GPIOD_4),
46+ MESON_PIN(GPIOD_5),
47+ MESON_PIN(GPIOD_6),
48+ MESON_PIN(GPIOD_7),
49+ MESON_PIN(GPIOD_8),
50+ MESON_PIN(GPIOD_9),
51+ MESON_PIN(GPIOD_10),
52+ MESON_PIN(GPIOD_11),
53+
54+ MESON_PIN(GPIOH_0),
55+ MESON_PIN(GPIOH_1),
56+ MESON_PIN(GPIOH_2),
57+ MESON_PIN(GPIOH_3),
58+ MESON_PIN(GPIOH_4),
59+ MESON_PIN(GPIOH_5),
60+ MESON_PIN(GPIOH_6),
61+ MESON_PIN(GPIOH_7),
62+ MESON_PIN(GPIOH_8),
63+ MESON_PIN(GPIOH_9),
64+ MESON_PIN(GPIOH_10),
65+ MESON_PIN(GPIOH_11),
66+
67+ MESON_PIN(GPIOX_0),
68+ MESON_PIN(GPIOX_1),
69+ MESON_PIN(GPIOX_2),
70+ MESON_PIN(GPIOX_3),
71+ MESON_PIN(GPIOX_4),
72+ MESON_PIN(GPIOX_5),
73+ MESON_PIN(GPIOX_6),
74+ MESON_PIN(GPIOX_7),
75+ MESON_PIN(GPIOX_8),
76+ MESON_PIN(GPIOX_9),
77+ MESON_PIN(GPIOX_10),
78+ MESON_PIN(GPIOX_11),
79+ MESON_PIN(GPIOX_12),
80+ MESON_PIN(GPIOX_13),
81+ MESON_PIN(GPIOX_14),
82+ MESON_PIN(GPIOX_15),
83+ MESON_PIN(GPIOX_16),
84+ MESON_PIN(GPIOX_17),
85+ MESON_PIN(GPIOX_18),
86+ MESON_PIN(GPIOX_19),
87+
88+ MESON_PIN(GPIOZ_0),
89+ MESON_PIN(GPIOZ_1),
90+ MESON_PIN(GPIOZ_2),
91+ MESON_PIN(GPIOZ_3),
92+ MESON_PIN(GPIOZ_4),
93+ MESON_PIN(GPIOZ_5),
94+ MESON_PIN(GPIOZ_6),
95+ MESON_PIN(GPIOZ_7),
96+ MESON_PIN(GPIOZ_8),
97+ MESON_PIN(GPIOZ_9),
98+ MESON_PIN(GPIOZ_10),
99+ MESON_PIN(GPIOZ_11),
100+ MESON_PIN(GPIOZ_12),
101+
102+ MESON_PIN(GPIO_TEST_N),
103+};
104+
105+/* BANK E func1 */
106+static const unsigned int i2c0_sda_pins[] = { GPIOE_0 };
107+static const unsigned int i2c0_scl_pins[] = { GPIOE_1 };
108+
109+/* BANK E func2 */
110+static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 };
111+static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 };
112+
113+/* BANK E func3 */
114+static const unsigned int pwm_h_pins[] = { GPIOE_0 };
115+static const unsigned int pwm_j_pins[] = { GPIOE_1 };
116+
117+/* BANK B func1 */
118+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
119+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
120+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
121+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
122+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
123+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
124+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
125+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
126+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
127+static const unsigned int emmc_rst_pins[] = { GPIOB_9 };
128+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
129+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
130+
131+/* Bank B func2 */
132+static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
133+static const unsigned int nand_ale_pins[] = { GPIOB_9 };
134+static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
135+static const unsigned int nand_cle_pins[] = { GPIOB_11 };
136+static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
137+
138+/* Bank B func3 */
139+static const unsigned int spif_hold_pins[] = { GPIOB_3 };
140+static const unsigned int spif_mo_pins[] = { GPIOB_4 };
141+static const unsigned int spif_mi_pins[] = { GPIOB_5 };
142+static const unsigned int spif_clk_pins[] = { GPIOB_6 };
143+static const unsigned int spif_wp_pins[] = { GPIOB_7 };
144+static const unsigned int spif_cs_pins[] = { GPIOB_13 };
145+
146+/* Bank C func1 */
147+static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
148+static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
149+static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
150+static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
151+static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
152+static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
153+static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
154+
155+/* Bank C func2 */
156+static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 };
157+static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 };
158+static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
159+static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
160+static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 };
161+static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 };
162+static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 };
163+static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 };
164+
165+/* Bank C func3 */
166+static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 };
167+static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 };
168+static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 };
169+static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 };
170+static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
171+static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
172+static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
173+
174+/* Bank C func4 */
175+static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 };
176+static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 };
177+static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 };
178+static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 };
179+static const unsigned int mclk_1_c_pins[] = { GPIOC_4 };
180+static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 };
181+static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 };
182+
183+/* Bank D func1 */
184+static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
185+static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
186+static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 };
187+static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 };
188+static const unsigned int remote_out_pins[] = { GPIOD_4 };
189+static const unsigned int remote_in_pins[] = { GPIOD_5 };
190+static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 };
191+static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 };
192+static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 };
193+static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 };
194+static const unsigned int clk12_24_pins[] = { GPIOD_10 };
195+static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 };
196+
197+/* Bank D func2 */
198+static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 };
199+static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 };
200+static const unsigned int mclk_1_d_pins[] = { GPIOD_4 };
201+static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 };
202+static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 };
203+static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 };
204+static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 };
205+static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 };
206+static const unsigned int pwm_g_d_pins[] = { GPIOD_11 };
207+
208+/* Bank D func3 */
209+static const unsigned int uart_c_tx_pins[] = { GPIOD_2 };
210+static const unsigned int uart_c_rx_pins[] = { GPIOD_3 };
211+static const unsigned int pwm_b_d_pins[] = { GPIOD_4 };
212+static const unsigned int pwm_a_d_pins[] = { GPIOD_6 };
213+static const unsigned int pwm_c_d_pins[] = { GPIOD_7 };
214+static const unsigned int pwm_d_d_pins[] = { GPIOD_8 };
215+static const unsigned int pwm_i_d_pins[] = { GPIOD_9 };
216+
217+/* Bank D func4 */
218+static const unsigned int clk_32k_in_pins[] = { GPIOD_2 };
219+static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 };
220+static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 };
221+static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 };
222+static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 };
223+static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 };
224+static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 };
225+
226+/* Bank D func5 */
227+static const unsigned int mic_mute_en_pins[] = { GPIOD_2 };
228+static const unsigned int mic_mute_key_pins[] = { GPIOD_3 };
229+static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 };
230+static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 };
231+static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 };
232+static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 };
233+
234+/* Bank D func6 */
235+static const unsigned int gen_clk_d_pins[] = { GPIOD_10 };
236+static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 };
237+static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 };
238+static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 };
239+static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 };
240+
241+/* Bank H func1 */
242+static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
243+static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 };
244+static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
245+static const unsigned int ao_cec_a_pins[] = { GPIOH_3 };
246+static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
247+static const unsigned int spdif_in_pins[] = { GPIOH_5 };
248+static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 };
249+static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 };
250+static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 };
251+static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 };
252+static const unsigned int eth_link_led_pins[] = { GPIOH_10 };
253+static const unsigned int eth_act_led_pins[] = { GPIOH_11 };
254+
255+/* Bank H func2 */
256+static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 };
257+static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 };
258+static const unsigned int ao_cec_b_pins[] = { GPIOH_3 };
259+static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 };
260+static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 };
261+static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 };
262+static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 };
263+static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 };
264+static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 };
265+static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 };
266+static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 };
267+
268+/* Bank H func3 */
269+static const unsigned int pwm_d_h_pins[] = { GPIOH_6 };
270+static const unsigned int pwm_i_h_pins[] = { GPIOH_7 };
271+static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 };
272+static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 };
273+static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 };
274+
275+/* Bank H func4 */
276+static const unsigned int mclk_1_h_pins[] = { GPIOH_4 };
277+static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 };
278+static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 };
279+static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 };
280+static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 };
281+static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 };
282+
283+/* Bank H func5 */
284+static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 };
285+static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 };
286+static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 };
287+static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 };
288+
289+/* Bank H func6 */
290+static const unsigned int gen_clk_h_pins[] = { GPIOH_11 };
291+static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 };
292+static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 };
293+static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 };
294+static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 };
295+
296+/* Bank X func1 */
297+static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
298+static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
299+static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
300+static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
301+static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
302+static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
303+static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
304+static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
305+static const unsigned int tdm_d1_pins[] = { GPIOX_8 };
306+static const unsigned int tdm_d0_pins[] = { GPIOX_9 };
307+static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
308+static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
309+static const unsigned int uart_a_tx_pins[] = { GPIOX_12 };
310+static const unsigned int uart_a_rx_pins[] = { GPIOX_13 };
311+static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
312+static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
313+static const unsigned int pwm_e_x_pins[] = { GPIOX_16 };
314+static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 };
315+static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 };
316+static const unsigned int pwm_b_x_pins[] = { GPIOX_19 };
317+
318+/* Bank X func2 */
319+static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 };
320+static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 };
321+static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 };
322+
323+/* Bank X func3 */
324+static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 };
325+static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 };
326+static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 };
327+static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 };
328+
329+/* Bank X func4 */
330+static const unsigned int pwm_c_x_pins[] = { GPIOX_8 };
331+static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 };
332+static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 };
333+
334+/* Bank X func5 */
335+static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 };
336+static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 };
337+
338+/* Bank Z func1 */
339+static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 };
340+static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 };
341+static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 };
342+static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 };
343+static const unsigned int tdm_d6_pins[] = { GPIOZ_4 };
344+static const unsigned int tdm_d7_pins[] = { GPIOZ_5 };
345+static const unsigned int mclk_2_pins[] = { GPIOZ_6 };
346+static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 };
347+static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 };
348+static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 };
349+static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 };
350+
351+/* Bank Z func2 */
352+static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 };
353+static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 };
354+static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 };
355+static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 };
356+static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 };
357+static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 };
358+static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 };
359+static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 };
360+static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 };
361+static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 };
362+
363+/* Bank Z func3 */
364+static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 };
365+static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 };
366+static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 };
367+static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 };
368+static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 };
369+static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 };
370+static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 };
371+static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 };
372+static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 };
373+static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 };
374+static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 };
375+
376+/* Bank Z func4 */
377+static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 };
378+static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 };
379+static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 };
380+static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 };
381+static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 };
382+static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 };
383+static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 };
384+static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 };
385+
386+/* Bank Z func5 */
387+static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 };
388+static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 };
389+static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 };
390+static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 };
391+static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 };
392+static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 };
393+static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 };
394+static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 };
395+static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 };
396+static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 };
397+static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 };
398+
399+/* Bank Z func6 */
400+static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 };
401+static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 };
402+static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 };
403+static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 };
404+static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 };
405+static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 };
406+static const unsigned int diseqc_out_pins[] = { GPIOZ_7 };
407+static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 };
408+static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 };
409+
410+/* Bank Z func7 */
411+static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
412+static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
413+
414+static struct meson_pmx_group meson_s4_periphs_groups[] = {
415+ GPIO_GROUP(GPIOE_0),
416+ GPIO_GROUP(GPIOE_1),
417+
418+ GPIO_GROUP(GPIOB_0),
419+ GPIO_GROUP(GPIOB_1),
420+ GPIO_GROUP(GPIOB_2),
421+ GPIO_GROUP(GPIOB_3),
422+ GPIO_GROUP(GPIOB_4),
423+ GPIO_GROUP(GPIOB_5),
424+ GPIO_GROUP(GPIOB_6),
425+ GPIO_GROUP(GPIOB_7),
426+ GPIO_GROUP(GPIOB_8),
427+ GPIO_GROUP(GPIOB_9),
428+ GPIO_GROUP(GPIOB_10),
429+ GPIO_GROUP(GPIOB_11),
430+ GPIO_GROUP(GPIOB_12),
431+ GPIO_GROUP(GPIOB_13),
432+
433+ GPIO_GROUP(GPIOC_0),
434+ GPIO_GROUP(GPIOC_1),
435+ GPIO_GROUP(GPIOC_2),
436+ GPIO_GROUP(GPIOC_3),
437+ GPIO_GROUP(GPIOC_4),
438+ GPIO_GROUP(GPIOC_5),
439+ GPIO_GROUP(GPIOC_6),
440+ GPIO_GROUP(GPIOC_7),
441+
442+ GPIO_GROUP(GPIOD_0),
443+ GPIO_GROUP(GPIOD_1),
444+ GPIO_GROUP(GPIOD_2),
445+ GPIO_GROUP(GPIOD_3),
446+ GPIO_GROUP(GPIOD_4),
447+ GPIO_GROUP(GPIOD_5),
448+ GPIO_GROUP(GPIOD_6),
449+ GPIO_GROUP(GPIOD_7),
450+ GPIO_GROUP(GPIOD_8),
451+ GPIO_GROUP(GPIOD_9),
452+ GPIO_GROUP(GPIOD_10),
453+ GPIO_GROUP(GPIOD_11),
454+
455+ GPIO_GROUP(GPIOH_0),
456+ GPIO_GROUP(GPIOH_1),
457+ GPIO_GROUP(GPIOH_2),
458+ GPIO_GROUP(GPIOH_3),
459+ GPIO_GROUP(GPIOH_4),
460+ GPIO_GROUP(GPIOH_5),
461+ GPIO_GROUP(GPIOH_6),
462+ GPIO_GROUP(GPIOH_7),
463+ GPIO_GROUP(GPIOH_8),
464+ GPIO_GROUP(GPIOH_9),
465+ GPIO_GROUP(GPIOH_10),
466+ GPIO_GROUP(GPIOH_11),
467+
468+ GPIO_GROUP(GPIOX_0),
469+ GPIO_GROUP(GPIOX_1),
470+ GPIO_GROUP(GPIOX_2),
471+ GPIO_GROUP(GPIOX_3),
472+ GPIO_GROUP(GPIOX_4),
473+ GPIO_GROUP(GPIOX_5),
474+ GPIO_GROUP(GPIOX_6),
475+ GPIO_GROUP(GPIOX_7),
476+ GPIO_GROUP(GPIOX_8),
477+ GPIO_GROUP(GPIOX_9),
478+ GPIO_GROUP(GPIOX_10),
479+ GPIO_GROUP(GPIOX_11),
480+ GPIO_GROUP(GPIOX_12),
481+ GPIO_GROUP(GPIOX_13),
482+ GPIO_GROUP(GPIOX_14),
483+ GPIO_GROUP(GPIOX_15),
484+ GPIO_GROUP(GPIOX_16),
485+ GPIO_GROUP(GPIOX_17),
486+ GPIO_GROUP(GPIOX_18),
487+ GPIO_GROUP(GPIOX_19),
488+
489+ GPIO_GROUP(GPIOZ_0),
490+ GPIO_GROUP(GPIOZ_1),
491+ GPIO_GROUP(GPIOZ_2),
492+ GPIO_GROUP(GPIOZ_3),
493+ GPIO_GROUP(GPIOZ_4),
494+ GPIO_GROUP(GPIOZ_5),
495+ GPIO_GROUP(GPIOZ_6),
496+ GPIO_GROUP(GPIOZ_7),
497+ GPIO_GROUP(GPIOZ_8),
498+ GPIO_GROUP(GPIOZ_9),
499+ GPIO_GROUP(GPIOZ_10),
500+ GPIO_GROUP(GPIOZ_11),
501+ GPIO_GROUP(GPIOZ_12),
502+
503+ GPIO_GROUP(GPIO_TEST_N),
504+
505+ /* BANK E func1 */
506+ GROUP(i2c0_sda, 1),
507+ GROUP(i2c0_scl, 1),
508+
509+ /* BANK E func2 */
510+ GROUP(uart_b_tx_e, 2),
511+ GROUP(uart_b_rx_e, 2),
512+
513+ /* BANK E func3 */
514+ GROUP(pwm_h, 3),
515+ GROUP(pwm_j, 3),
516+
517+ /* BANK B func1 */
518+ GROUP(emmc_nand_d0, 1),
519+ GROUP(emmc_nand_d1, 1),
520+ GROUP(emmc_nand_d2, 1),
521+ GROUP(emmc_nand_d3, 1),
522+ GROUP(emmc_nand_d4, 1),
523+ GROUP(emmc_nand_d5, 1),
524+ GROUP(emmc_nand_d6, 1),
525+ GROUP(emmc_nand_d7, 1),
526+ GROUP(emmc_clk, 1),
527+ GROUP(emmc_rst, 1),
528+ GROUP(emmc_cmd, 1),
529+ GROUP(emmc_nand_ds, 1),
530+
531+ /* Bank B func2 */
532+ GROUP(nand_wen_clk, 2),
533+ GROUP(nand_ale, 2),
534+ GROUP(nand_ren_wr, 2),
535+ GROUP(nand_cle, 2),
536+ GROUP(nand_ce0, 2),
537+
538+ /* Bank B func3 */
539+ GROUP(spif_hold, 3),
540+ GROUP(spif_mo, 3),
541+ GROUP(spif_mi, 3),
542+ GROUP(spif_clk, 3),
543+ GROUP(spif_wp, 3),
544+ GROUP(spif_cs, 3),
545+
546+ /* Bank C func1 */
547+ GROUP(sdcard_d0_c, 1),
548+ GROUP(sdcard_d1_c, 1),
549+ GROUP(sdcard_d2_c, 1),
550+ GROUP(sdcard_d3_c, 1),
551+ GROUP(sdcard_clk_c, 1),
552+ GROUP(sdcard_cmd_c, 1),
553+ GROUP(sdcard_cd, 1),
554+
555+ /* Bank C func2 */
556+ GROUP(jtag_2_tdo, 2),
557+ GROUP(jtag_2_tdi, 2),
558+ GROUP(uart_b_rx_c, 2),
559+ GROUP(uart_b_tx_c, 2),
560+ GROUP(jtag_2_clk, 2),
561+ GROUP(jtag_2_tms, 2),
562+ GROUP(i2c1_sda_c, 2),
563+ GROUP(i2c1_scl_c, 2),
564+
565+ /* Bank C func3 */
566+ GROUP(pdm_din1_c, 3),
567+ GROUP(pdm_din0_c, 3),
568+ GROUP(i2c4_sda_c, 3),
569+ GROUP(i2c4_scl_c, 3),
570+ GROUP(pdm_dclk_c, 3),
571+ GROUP(iso7816_clk_c, 3),
572+ GROUP(iso7816_data_c, 3),
573+
574+ /* Bank C func4 */
575+ GROUP(tdm_d2_c, 4),
576+ GROUP(tdm_d3_c, 4),
577+ GROUP(tdm_fs1_c, 4),
578+ GROUP(mclk_1_c, 4),
579+ GROUP(tdm_d4_c, 4),
580+ GROUP(tdm_d5_c, 4),
581+
582+ /* Bank D func1 */
583+ GROUP(uart_b_tx_d, 1),
584+ GROUP(uart_b_rx_d, 1),
585+ GROUP(uart_b_cts_d, 1),
586+ GROUP(uart_b_rts_d, 1),
587+ GROUP(remote_out, 1),
588+ GROUP(remote_in, 1),
589+ GROUP(jtag_1_clk, 1),
590+ GROUP(jtag_1_tms, 1),
591+ GROUP(jtag_1_tdi, 1),
592+ GROUP(jtag_1_tdo, 1),
593+ GROUP(clk12_24, 1),
594+ GROUP(pwm_g_hiz, 1),
595+
596+ /* Bank D func2 */
597+ GROUP(i2c4_sda_d, 2),
598+ GROUP(i2c4_scl_d, 2),
599+ GROUP(mclk_1_d, 2),
600+ GROUP(tdm_sclk1_d, 2),
601+ GROUP(tdm_fs1_d, 2),
602+ GROUP(tdm_d4_d, 2),
603+ GROUP(tdm_d3_d, 2),
604+ GROUP(tdm_d2_d, 2),
605+ GROUP(pwm_g_d, 2),
606+
607+ /* Bank D func3 */
608+ GROUP(uart_c_tx, 3),
609+ GROUP(uart_c_rx, 3),
610+ GROUP(pwm_b_d, 3),
611+ GROUP(pwm_a_d, 3),
612+ GROUP(pwm_c_d, 3),
613+ GROUP(pwm_d_d, 3),
614+ GROUP(pwm_i_d, 3),
615+
616+ /* Bank D func4 */
617+ GROUP(clk_32k_in, 4),
618+ GROUP(pwm_b_hiz, 4),
619+ GROUP(pwm_a_hiz, 4),
620+ GROUP(pwm_c_hiz, 4),
621+ GROUP(pdm_dclk_d, 4),
622+ GROUP(pdm_din0_d, 4),
623+ GROUP(pdm_din1_d, 4),
624+
625+ /* Bank D func5 */
626+ GROUP(mic_mute_en, 5),
627+ GROUP(mic_mute_key, 5),
628+ GROUP(i2c1_sda_d, 5),
629+ GROUP(i2c1_scl_d, 5),
630+ GROUP(i2c2_sda_d, 5),
631+ GROUP(i2c2_scl_d, 5),
632+
633+ /* Bank D func6 */
634+ GROUP(gen_clk_d, 6),
635+ GROUP(tsin_b_clk_c, 6),
636+ GROUP(tsin_b_sop_c, 6),
637+ GROUP(tsin_b_valid_c, 6),
638+ GROUP(tsin_b_d0_c, 6),
639+
640+ /* Bank H func1 */
641+ GROUP(hdmitx_sda, 1),
642+ GROUP(hdmitx_sck, 1),
643+ GROUP(hdmitx_hpd_in, 1),
644+ GROUP(ao_cec_a, 1),
645+ GROUP(spdif_out_h, 1),
646+ GROUP(spdif_in, 1),
647+ GROUP(i2c1_sda_h, 1),
648+ GROUP(i2c1_scl_h, 1),
649+ GROUP(i2c2_sda_h8, 1),
650+ GROUP(i2c2_scl_h9, 1),
651+ GROUP(eth_link_led, 1),
652+ GROUP(eth_act_led, 1),
653+
654+ /* Bank H func2 */
655+ GROUP(i2c2_sda_h0, 2),
656+ GROUP(i2c2_scl_h1, 2),
657+ GROUP(ao_cec_b, 2),
658+ GROUP(uart_d_tx_h, 2),
659+ GROUP(uart_d_rx_h, 2),
660+ GROUP(uart_d_cts_h, 2),
661+ GROUP(uart_d_rts_h, 2),
662+ GROUP(iso7816_clk_h, 2),
663+ GROUP(iso7816_data_h, 2),
664+ GROUP(uart_e_tx_h, 2),
665+ GROUP(uart_e_rx_h, 2),
666+
667+ /* Bank H func3 */
668+ GROUP(pwm_d_h, 3),
669+ GROUP(pwm_i_h, 3),
670+ GROUP(pdm_dclk_h, 3),
671+ GROUP(pdm_din0_h, 3),
672+ GROUP(pdm_din1_h, 3),
673+
674+ /* Bank H func4 */
675+ GROUP(mclk_1_h, 4),
676+ GROUP(tdm_sclk1_h, 4),
677+ GROUP(tdm_fs1_h, 4),
678+ GROUP(tdm_d2_h, 4),
679+ GROUP(tdm_d3_h, 4),
680+ GROUP(tdm_d4_h, 4),
681+
682+ /* Bank H func5 */
683+ GROUP(spi_a_miso_h, 5),
684+ GROUP(spi_a_mosi_h, 5),
685+ GROUP(spi_a_clk_h, 5),
686+ GROUP(spi_a_ss0_h, 5),
687+
688+ /* Bank H func6 */
689+ GROUP(gen_clk_h, 6),
690+ GROUP(tsin_b1_clk, 6),
691+ GROUP(tsin_b1_sop, 6),
692+ GROUP(tsin_b1_valid, 6),
693+ GROUP(tsin_b1_d0, 6),
694+
695+ /* Bank X func1 */
696+ GROUP(sdio_d0, 1),
697+ GROUP(sdio_d1, 1),
698+ GROUP(sdio_d2, 1),
699+ GROUP(sdio_d3, 1),
700+ GROUP(sdio_clk, 1),
701+ GROUP(sdio_cmd, 1),
702+ GROUP(pwm_a_x, 1),
703+ GROUP(pwm_f_x, 1),
704+ GROUP(tdm_d1, 1),
705+ GROUP(tdm_d0, 1),
706+ GROUP(tdm_fs0, 1),
707+ GROUP(tdm_sclk0, 1),
708+ GROUP(uart_a_tx, 1),
709+ GROUP(uart_a_rx, 1),
710+ GROUP(uart_a_cts, 1),
711+ GROUP(uart_a_rts, 1),
712+ GROUP(pwm_e_x, 1),
713+ GROUP(i2c1_sda_x, 1),
714+ GROUP(i2c1_scl_x, 1),
715+ GROUP(pwm_b_x, 1),
716+
717+ /* Bank X func2 */
718+ GROUP(pdm_din0_x, 2),
719+ GROUP(pdm_din1_x, 2),
720+ GROUP(pdm_dclk_x, 2),
721+
722+ /* Bank X func3 */
723+ GROUP(spi_a_mosi_x, 3),
724+ GROUP(spi_a_miso_x, 3),
725+ GROUP(spi_a_ss0_x, 3),
726+ GROUP(spi_a_clk_x, 3),
727+
728+ /* Bank X func4 */
729+ GROUP(pwm_c_x, 4),
730+ GROUP(i2c_slave_scl, 4),
731+ GROUP(i2c_slave_sda, 4),
732+
733+ /* Bank X func5 */
734+ GROUP(i2c3_sda_x, 5),
735+ GROUP(i2c3_scl_x, 5),
736+
737+ /* Bank Z func1 */
738+ GROUP(tdm_fs2, 1),
739+ GROUP(tdm_sclk2, 1),
740+ GROUP(tdm_d4_z, 1),
741+ GROUP(tdm_d5_z, 1),
742+ GROUP(tdm_d6, 1),
743+ GROUP(tdm_d7, 1),
744+ GROUP(mclk_2, 1),
745+ GROUP(spdif_out_z, 1),
746+ GROUP(dtv_a_if_agc_z10, 1),
747+ GROUP(uart_e_tx_z11, 1),
748+ GROUP(uart_e_rx_z12, 1),
749+
750+ /* Bank Z func2 */
751+ GROUP(tsin_a_clk, 2),
752+ GROUP(tsin_a_sop, 2),
753+ GROUP(tsin_a_valid, 2),
754+ GROUP(tsin_a_din0, 2),
755+ GROUP(dtv_a_if_agc_z6, 2),
756+ GROUP(dtv_b_if_agc, 2),
757+ GROUP(i2c3_sda_z, 2),
758+ GROUP(i2c3_scl_z, 2),
759+ GROUP(dtv_a_rf_agc, 2),
760+ GROUP(dtv_b_rf_agc, 2),
761+
762+ /* Bank Z func3 */
763+ GROUP(sdcard_d0_z, 3),
764+ GROUP(sdcard_d1_z, 3),
765+ GROUP(sdcard_d2_z, 3),
766+ GROUP(sdcard_d3_z, 3),
767+ GROUP(sdcard_clk_z, 3),
768+ GROUP(sdcard_cmd_z, 3),
769+ GROUP(uart_e_tx_z8, 3),
770+ GROUP(uart_e_rx_z9, 3),
771+ GROUP(pdm_din1_z, 3),
772+ GROUP(pdm_din0_z, 3),
773+ GROUP(pdm_dclk_z, 3),
774+
775+ /* Bank Z func4 */
776+ GROUP(spi_a_miso_z, 4),
777+ GROUP(spi_a_mosi_z, 4),
778+ GROUP(spi_a_clk_z, 4),
779+ GROUP(spi_a_ss0_z, 4),
780+ GROUP(spi_a_ss1_z, 4),
781+ GROUP(spi_a_ss2_z, 4),
782+ GROUP(i2c4_scl_z, 4),
783+ GROUP(i2c4_sda_z, 4),
784+
785+ /* Bank Z func5 */
786+ GROUP(uart_d_tx_z, 5),
787+ GROUP(uart_d_rx_z, 5),
788+ GROUP(uart_d_cts_z, 5),
789+ GROUP(uart_d_rts_z, 5),
790+ GROUP(pwm_g_z, 5),
791+ GROUP(pwm_f_z, 5),
792+ GROUP(pwm_e_z, 5),
793+ GROUP(tsin_b_clk_z, 5),
794+ GROUP(tsin_b_sop_z, 5),
795+ GROUP(tsin_b_valid_z, 5),
796+ GROUP(tsin_b_d0_z, 5),
797+
798+ /* Bank Z func6 */
799+ GROUP(s2_demod_gpio7, 6),
800+ GROUP(s2_demod_gpio6, 6),
801+ GROUP(s2_demod_gpio5, 6),
802+ GROUP(s2_demod_gpio4, 6),
803+ GROUP(s2_demod_gpio3, 6),
804+ GROUP(s2_demod_gpio2, 6),
805+ GROUP(diseqc_out, 6),
806+ GROUP(s2_demod_gpio1, 6),
807+ GROUP(s2_demod_gpio0, 6),
808+
809+ /* Bank Z func7 */
810+ GROUP(gen_clk_z9, 7),
811+ GROUP(gen_clk_z12, 7),
812+};
813+
814+static const char * const gpio_periphs_groups[] = {
815+ "GPIOE_0", "GPIOE_1",
816+
817+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
818+ "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11",
819+ "GPIOB_12", "GPIOB_13",
820+
821+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
822+ "GPIOC_6", "GPIOC_7",
823+
824+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
825+ "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
826+
827+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
828+ "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11",
829+
830+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
831+ "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
832+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
833+ "GPIOX_18", "GPIOX_19",
834+
835+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
836+ "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10",
837+ "GPIOZ_11", "GPIOZ_12",
838+
839+ "GPIO_TEST_N",
840+};
841+
842+static const char * const i2c0_groups[] = {
843+ "i2c0_sda", "i2c0_scl",
844+};
845+
846+static const char * const i2c1_groups[] = {
847+ "i2c1_sda_c", "i2c1_scl_c",
848+ "i2c1_sda_d", "i2c1_scl_d",
849+ "i2c1_sda_h", "i2c1_scl_h",
850+ "i2c1_sda_x", "i2c1_scl_x",
851+};
852+
853+static const char * const i2c2_groups[] = {
854+ "i2c2_sda_d", "i2c2_scl_d",
855+ "i2c2_sda_h8", "i2c2_scl_h9",
856+ "i2c2_sda_h0", "i2c2_scl_h1l,"
857+};
858+
859+static const char * const i2c3_groups[] = {
860+ "i2c3_sda_x", "i2c3_scl_x",
861+ "i2c3_sda_z", "i2c3_scl_z",
862+};
863+
864+static const char * const i2c4_groups[] = {
865+ "i2c4_sda_c", "i2c4_scl_c",
866+ "i2c4_sda_d", "i2c4_scl_d",
867+ "i2c4_scl_z", "i2c4_sda_z",
868+};
869+
870+static const char * const uart_a_groups[] = {
871+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
872+};
873+
874+static const char * const uart_b_groups[] = {
875+ "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c",
876+ "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d",
877+};
878+
879+static const char * const uart_c_groups[] = {
880+ "uart_c_tx", "uart_c_rx",
881+};
882+
883+static const char * const uart_d_groups[] = {
884+ "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h",
885+ "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z",
886+};
887+
888+static const char * const uart_e_groups[] = {
889+ "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12",
890+ "uart_e_tx_z8", "uart_e_rx_z9",
891+};
892+
893+static const char * const emmc_groups[] = {
894+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
895+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
896+ "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds",
897+};
898+
899+static const char * const nand_groups[] = {
900+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
901+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
902+ "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0",
903+};
904+
905+static const char * const spif_groups[] = {
906+ "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp",
907+ "spif_cs",
908+};
909+
910+static const char * const sdcard_groups[] = {
911+ "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
912+ "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd",
913+ "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
914+ "sdcard_clk_z", "sdcard_cmd_z",
915+};
916+
917+static const char * const jtag_1_groups[] = {
918+ "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo",
919+};
920+
921+static const char * const jtag_2_groups[] = {
922+ "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms",
923+};
924+
925+static const char * const pdm_groups[] = {
926+ "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c",
927+ "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d",
928+ "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h",
929+ "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x",
930+ "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z",
931+};
932+
933+static const char * const iso7816_groups[] = {
934+ "iso7816_clk_c", "iso7816_data_c",
935+ "iso7816_clk_h", "iso7816_data_h",
936+};
937+
938+static const char * const tdm_groups[] = {
939+ "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c",
940+ "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d",
941+ "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h",
942+ "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2",
943+ "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7",
944+};
945+
946+static const char * const mclk_1_groups[] = {
947+ "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2",
948+};
949+
950+static const char * const mclk_2_groups[] = {
951+ "mclk_2",
952+};
953+
954+static const char * const remote_out_groups[] = {
955+ "remote_out",
956+};
957+
958+static const char * const remote_in_groups[] = {
959+ "remote_in",
960+};
961+
962+static const char * const clk12_24_groups[] = {
963+ "clk12_24",
964+};
965+
966+static const char * const clk_32k_in_groups[] = {
967+ "clk_32k_in",
968+};
969+
970+static const char * const pwm_a_hiz_groups[] = {
971+ "pwm_a_hiz",
972+};
973+
974+static const char * const pwm_b_hiz_groups[] = {
975+ "pwm_b_hiz",
976+};
977+
978+static const char * const pwm_c_hiz_groups[] = {
979+ "pwm_c_hiz",
980+};
981+
982+static const char * const pwm_g_hiz_groups[] = {
983+ "pwm_g_hiz",
984+};
985+
986+static const char * const pwm_a_groups[] = {
987+ "pwm_a_d",
988+};
989+
990+static const char * const pwm_b_groups[] = {
991+ "pwm_b_d", "pwm_b_x",
992+};
993+
994+static const char * const pwm_c_groups[] = {
995+ "pwm_c_d", "pwm_c_x",
996+};
997+
998+static const char * const pwm_d_groups[] = {
999+ "pwm_d_d", "pwm_d_h",
1000+};
1001+
1002+static const char * const pwm_e_groups[] = {
1003+ "pwm_e_x", "pwm_e_z",
1004+};
1005+
1006+static const char * const pwm_f_groups[] = {
1007+ "pwm_f_x", "pwm_f_z",
1008+};
1009+
1010+static const char * const pwm_g_groups[] = {
1011+ "pwm_g_d", "pwm_g_z",
1012+};
1013+
1014+static const char * const pwm_h_groups[] = {
1015+ "pwm_h",
1016+};
1017+
1018+static const char * const pwm_i_groups[] = {
1019+ "pwm_i_d", "pwm_i_h"
1020+};
1021+
1022+static const char * const pwm_j_groups[] = {
1023+ "pwm_j",
1024+};
1025+
1026+static const char * const mic_mute_groups[] = {
1027+ "mic_mute_en", "mic_mute_key",
1028+};
1029+
1030+static const char * const hdmitx_groups[] = {
1031+ "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in",
1032+};
1033+
1034+static const char * const ao_cec_a_groups[] = {
1035+ "ao_cec_a",
1036+};
1037+
1038+static const char * const ao_cec_b_groups[] = {
1039+ "ao_cec_b",
1040+};
1041+
1042+static const char * const spdif_out_groups[] = {
1043+ "spdif_out_h", "spdif_out_z",
1044+};
1045+
1046+static const char * const spdif_in_groups[] = {
1047+ "spdif_in",
1048+};
1049+
1050+static const char * const eth_groups[] = {
1051+ "eth_link_led", "eth_act_led",
1052+};
1053+
1054+static const char * const spi_a_groups[] = {
1055+ "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h",
1056+
1057+ "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x",
1058+
1059+ "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z",
1060+ "spi_a_ss1_z", "spi_a_ss2_z",
1061+};
1062+
1063+static const char * const gen_clk_groups[] = {
1064+ "gen_clk_h", "gen_clk_z9", "gen_clk_z12",
1065+};
1066+
1067+static const char * const sdio_groups[] = {
1068+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd",
1069+};
1070+
1071+static const char * const i2c_slave_groups[] = {
1072+ "i2c_slave_scl", "i2c_slave_sda",
1073+};
1074+
1075+static const char * const dtv_groups[] = {
1076+ "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc",
1077+ "dtv_a_rf_agc", "dtv_b_rf_agc",
1078+};
1079+
1080+static const char * const tsin_a_groups[] = {
1081+ "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0",
1082+};
1083+
1084+static const char * const tsin_b_groups[] = {
1085+ "tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c",
1086+ "tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z",
1087+};
1088+
1089+static const char * const tsin_b1_groups[] = {
1090+ "tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0",
1091+};
1092+
1093+static const char * const diseqc_out_groups[] = {
1094+ "diseqc_out",
1095+};
1096+
1097+static const char * const s2_demod_groups[] = {
1098+ "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4",
1099+ "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0",
1100+};
1101+
1102+static struct meson_pmx_func meson_s4_periphs_functions[] = {
1103+ FUNCTION(gpio_periphs),
1104+ FUNCTION(i2c0),
1105+ FUNCTION(i2c1),
1106+ FUNCTION(i2c2),
1107+ FUNCTION(i2c3),
1108+ FUNCTION(i2c4),
1109+ FUNCTION(uart_a),
1110+ FUNCTION(uart_b),
1111+ FUNCTION(uart_c),
1112+ FUNCTION(uart_d),
1113+ FUNCTION(uart_e),
1114+ FUNCTION(emmc),
1115+ FUNCTION(nand),
1116+ FUNCTION(spif),
1117+ FUNCTION(sdcard),
1118+ FUNCTION(jtag_1),
1119+ FUNCTION(jtag_2),
1120+ FUNCTION(pdm),
1121+ FUNCTION(iso7816),
1122+ FUNCTION(tdm),
1123+ FUNCTION(mclk_1),
1124+ FUNCTION(mclk_2),
1125+ FUNCTION(remote_out),
1126+ FUNCTION(remote_in),
1127+ FUNCTION(clk12_24),
1128+ FUNCTION(clk_32k_in),
1129+ FUNCTION(pwm_a_hiz),
1130+ FUNCTION(pwm_b_hiz),
1131+ FUNCTION(pwm_c_hiz),
1132+ FUNCTION(pwm_g_hiz),
1133+ FUNCTION(pwm_a),
1134+ FUNCTION(pwm_b),
1135+ FUNCTION(pwm_c),
1136+ FUNCTION(pwm_d),
1137+ FUNCTION(pwm_e),
1138+ FUNCTION(pwm_f),
1139+ FUNCTION(pwm_g),
1140+ FUNCTION(pwm_h),
1141+ FUNCTION(pwm_i),
1142+ FUNCTION(pwm_j),
1143+ FUNCTION(mic_mute),
1144+ FUNCTION(hdmitx),
1145+ FUNCTION(ao_cec_a),
1146+ FUNCTION(ao_cec_b),
1147+ FUNCTION(spdif_out),
1148+ FUNCTION(spdif_in),
1149+ FUNCTION(eth),
1150+ FUNCTION(spi_a),
1151+ FUNCTION(gen_clk),
1152+ FUNCTION(sdio),
1153+ FUNCTION(i2c_slave),
1154+ FUNCTION(dtv),
1155+ FUNCTION(tsin_a),
1156+ FUNCTION(tsin_b),
1157+ FUNCTION(tsin_b1),
1158+ FUNCTION(diseqc_out),
1159+ FUNCTION(s2_demod),
1160+};
1161+
1162+static struct meson_bank meson_s4_periphs_banks[] = {
1163+ /* name first last irq pullen pull dir out in */
1164+ BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13,
1165+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
1166+ BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21,
1167+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0),
1168+ BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23,
1169+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0),
1170+ BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35,
1171+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0),
1172+ BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47,
1173+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0),
1174+ BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67,
1175+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0),
1176+ BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80,
1177+ 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
1178+ BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1,
1179+ 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
1180+};
1181+
1182+static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
1183+ /*name first lask reg offset*/
1184+ BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
1185+ BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
1186+ BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0),
1187+ BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0),
1188+ BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0),
1189+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
1190+ BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0),
1191+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
1192+};
1193+
1194+static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
1195+ .pmx_banks = meson_s4_periphs_pmx_banks,
1196+ .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
1197+};
1198+
1199+static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
1200+ .name = "periphs-banks",
1201+ .pins = meson_s4_periphs_pins,
1202+ .groups = meson_s4_periphs_groups,
1203+ .funcs = meson_s4_periphs_functions,
1204+ .banks = meson_s4_periphs_banks,
1205+ .num_pins = ARRAY_SIZE(meson_s4_periphs_pins),
1206+ .num_groups = ARRAY_SIZE(meson_s4_periphs_groups),
1207+ .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions),
1208+ .num_banks = ARRAY_SIZE(meson_s4_periphs_banks),
1209+ .pmx_ops = &meson_axg_pmx_ops,
1210+ .pmx_data = &meson_s4_periphs_pmx_banks_data,
1211+ .parse_dt = &meson_a1_parse_dt_extra,
1212+};
1213+
1214+static const struct of_device_id meson_s4_pinctrl_dt_match[] = {
1215+ {
1216+ .compatible = "amlogic,meson-s4-periphs-pinctrl",
1217+ .data = &meson_s4_periphs_pinctrl_data,
1218+ },
1219+ { }
1220+};
1221+MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match);
1222+
1223+static struct platform_driver meson_s4_pinctrl_driver = {
1224+ .probe = meson_pinctrl_probe,
1225+ .driver = {
1226+ .name = "meson-s4-pinctrl",
1227+ .of_match_table = meson_s4_pinctrl_dt_match,
1228+ },
1229+};
1230+module_platform_driver(meson_s4_pinctrl_driver);
1231+
1232+MODULE_LICENSE("Dual BSD/GPL");
drivers/pinctrl/nomadik/pinctrl-nomadik.c+3−1
@@ -1883,8 +1883,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) · 1882 unmodified lines
18831883 }
18841884
18851885 prcm_np = of_parse_phandle(np, "prcm", 0);
1886− if (prcm_np)
1886+ if (prcm_np) {
18871887 npct->prcm_base = of_iomap(prcm_np, 0);
1888+ of_node_put(prcm_np);
1889+ }
18881890 if (!npct->prcm_base) {
18891891 if (version == PINCTRL_NMK_STN8815) {
18901892 dev_info(&pdev->dev,
drivers/pinctrl/nuvoton/Kconfig+20−0
@@ -1,4 +1,24 @@
11 # SPDX-License-Identifier: GPL-2.0-only
2+
3+config PINCTRL_WPCM450
4+ tristate "Pinctrl and GPIO driver for Nuvoton WPCM450"
5+ depends on ARCH_WPCM450 || COMPILE_TEST
6+ depends on OF
7+ select PINMUX
8+ select PINCONF
9+ select GENERIC_PINCONF
10+ select GENERIC_PINCTRL_GROUPS
11+ select GPIOLIB
12+ select GPIO_GENERIC
13+ select GPIOLIB_IRQCHIP
14+ help
15+ Say Y or M here to enable pin controller and GPIO support for
16+ the Nuvoton WPCM450 SoC. This is strongly recommended when
17+ building a kernel that will run on this chip.
18+
19+ If this driver is compiled as a module, it will be named
20+ pinctrl-wpcm450.
21+
222 config PINCTRL_NPCM7XX
323 bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
424 depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF
drivers/pinctrl/nuvoton/Makefile+1−0
@@ -1,4 +1,5 @@
11 # SPDX-License-Identifier: GPL-2.0
22 # Nuvoton pinctrl support
33
4+obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
45 obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+84−84
@@ -216,7 +216,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) · 215 unmodified lines
216216 struct gpio_chip *gc;
217217 struct irq_chip *chip;
218218 struct npcm7xx_gpio *bank;
219− u32 sts, en, bit;
219+ unsigned long sts, en, bit;
220220
221221 gc = irq_desc_get_handler_data(desc);
222222 bank = gpiochip_get_data(gc);
@@ -225,11 +225,11 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) · 2 unmodified lines
225225 chained_irq_enter(chip, desc);
226226 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
227227 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
228− dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts,
228+ dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
229229 en);
230230
231231 sts &= en;
232− for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
232+ for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
233233 generic_handle_domain_irq(gc->irq.domain, bit);
234234 chained_irq_exit(chip, desc);
235235 }
@@ -894,7 +894,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { · 658 unmodified lines
894894 };
895895
896896 #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
897− [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
897+ [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
898898 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
899899 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
900900 .flag = k }
@@ -904,7 +904,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { · 3 unmodified lines
904904 #define DRIVE_STRENGTH_HI_SHIFT 12
905905 #define DRIVE_STRENGTH_MASK 0x0000FF00
906906
907−#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
907+#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
908908 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
909909 #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
910910 #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
@@ -924,31 +924,31 @@ struct npcm7xx_pincfg { · 13 unmodified lines
924924 static const struct npcm7xx_pincfg pincfg[] = {
925925 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
926926 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
927− NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
928− NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
927+ NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
928+ NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
929929 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
930930 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
931931 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
932932 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
933933 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
934− NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)),
935− NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)),
936− NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
937− NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
934+ NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
935+ NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
936+ NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
937+ NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
938938 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
939939 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
940940 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
941941 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
942− NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
943− NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)),
944− NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
945− NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
942+ NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
943+ NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
944+ NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
945+ NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
946946 NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
947947 NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
948948 NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
949949 NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
950− NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
951− NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
950+ NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
951+ NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
952952 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
953953 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
954954 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
@@ -964,12 +964,12 @@ static const struct npcm7xx_pincfg pincfg[] = { · 9 unmodified lines
964964 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
965965 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
966966 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
967− NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO),
967+ NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
968968 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
969969 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
970970 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
971− NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
972− NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
971+ NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
972+ NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
973973 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
974974 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
975975 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
@@ -979,8 +979,8 @@ static const struct npcm7xx_pincfg pincfg[] = { · 3 unmodified lines
979979 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
980980 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
981981 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
982− NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
983− NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
982+ NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
983+ NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
984984 NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
985985 NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
986986 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
@@ -1003,19 +1003,19 @@ static const struct npcm7xx_pincfg pincfg[] = { · 16 unmodified lines
10031003 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
10041004 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
10051005 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
1006− NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1007− NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1008− NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1009− NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1010− NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1011− NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1012− NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1006+ NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1007+ NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1008+ NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1009+ NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1010+ NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1011+ NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1012+ NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
10131013 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
10141014 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
10151015 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
10161016 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
1017− NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
1018− NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
1017+ NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1018+ NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
10191019 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
10201020 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
10211021 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
@@ -1061,34 +1061,34 @@ static const struct npcm7xx_pincfg pincfg[] = { · 39 unmodified lines
10611061 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
10621062 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
10631063 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
1064− NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1065− NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1066− NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1067− NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1068− NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1064+ NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1065+ NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1066+ NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1067+ NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1068+ NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
10691069 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
1070− NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1070+ NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
10711071 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
1072− NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1073− NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1074− NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1075− NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1076− NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1077− NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1078− NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1079− NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1080− NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1072+ NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1073+ NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1074+ NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1075+ NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1076+ NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1077+ NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1078+ NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1079+ NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1080+ NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
10811081 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
1082− NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1082+ NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
10831083 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
1084− NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1085− NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1086− NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1087− NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1088−
1089− NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1090− NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)),
1091− NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)),
1084+ NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1085+ NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1086+ NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1087+ NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1088+
1089+ NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1090+ NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
1091+ NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
10921092 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
10931093 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
10941094 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
@@ -1101,25 +1101,25 @@ static const struct npcm7xx_pincfg pincfg[] = { · 6 unmodified lines
11011101 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
11021102 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
11031103 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
1104− NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
1105− NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
1106− NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
1107− NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1108− NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1109− NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1104+ NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1105+ NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1106+ NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1107+ NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1108+ NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1109+ NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
11101110 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
11111111 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
1112− NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1113− NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
1114− NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
1115− NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)),
1116− NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
1117− NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW),
1118− NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW),
1119− NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)),
1120− NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
1121−
1122− NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
1112+ NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1113+ NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1114+ NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1115+ NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1116+ NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1117+ NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
1118+ NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
1119+ NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1120+ NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
1121+
1122+ NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
11231123 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
11241124 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
11251125 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
@@ -1130,11 +1130,11 @@ static const struct npcm7xx_pincfg pincfg[] = { · 4 unmodified lines
11301130 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
11311131 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
11321132 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
1133− NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)),
1133+ NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
11341134 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
11351135 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
1136− NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
1137− NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
1136+ NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
1137+ NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
11381138 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
11391139 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
11401140 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
@@ -1146,20 +1146,20 @@ static const struct npcm7xx_pincfg pincfg[] = { · 5 unmodified lines
11461146 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
11471147 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
11481148 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
1149− NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
1149+ NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
11501150 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
11511151 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
11521152 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
11531153 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
11541154
11551155 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
1156− NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
1157− NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
1158− NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1159− NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1160− NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1161− NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
1162− NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)),
1156+ NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1157+ NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1158+ NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1159+ NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1160+ NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1161+ NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1162+ NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
11631163 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
11641164 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
11651165 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
@@ -1560,7 +1560,7 @@ static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) · 394 unmodified lines
15601560 {
15611561 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
15621562
1563− dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups));
1563+ dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
15641564 return ARRAY_SIZE(npcm7xx_groups);
15651565 }
15661566
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c+1151−0
@@ -0,0 +1,1151 @@
1+// SPDX-License-Identifier: GPL-2.0
2+// Copyright (c) 2016-2018 Nuvoton Technology corporation.
3+// Copyright (c) 2016, Dell Inc
4+// Copyright (c) 2021-2022 Jonathan Neuschäfer
5+//
6+// This driver uses the following registers:
7+// - Pin mux registers, in the GCR (general control registers) block
8+// - GPIO registers, specific to each GPIO bank
9+// - GPIO event (interrupt) registers, located centrally in the GPIO register
10+// block, shared between all GPIO banks
11+
12+#include <linux/device.h>
13+#include <linux/fwnode.h>
14+#include <linux/gpio/driver.h>
15+#include <linux/interrupt.h>
16+#include <linux/irq.h>
17+#include <linux/mfd/syscon.h>
18+#include <linux/module.h>
19+#include <linux/mod_devicetable.h>
20+#include <linux/platform_device.h>
21+#include <linux/regmap.h>
22+
23+#include <linux/pinctrl/pinconf.h>
24+#include <linux/pinctrl/pinconf-generic.h>
25+#include <linux/pinctrl/pinctrl.h>
26+#include <linux/pinctrl/pinmux.h>
27+
28+#include "../core.h"
29+
30+/* GCR registers */
31+#define WPCM450_GCR_MFSEL1 0x0c
32+#define WPCM450_GCR_MFSEL2 0x10
33+#define WPCM450_GCR_NONE 0
34+
35+/* GPIO event (interrupt) registers */
36+#define WPCM450_GPEVTYPE 0x00
37+#define WPCM450_GPEVPOL 0x04
38+#define WPCM450_GPEVDBNC 0x08
39+#define WPCM450_GPEVEN 0x0c
40+#define WPCM450_GPEVST 0x10
41+
42+#define WPCM450_NUM_BANKS 8
43+#define WPCM450_NUM_GPIOS 128
44+#define WPCM450_NUM_GPIO_IRQS 4
45+
46+struct wpcm450_pinctrl;
47+struct wpcm450_bank;
48+
49+struct wpcm450_gpio {
50+ struct gpio_chip gc;
51+ struct wpcm450_pinctrl *pctrl;
52+ struct irq_chip irqc;
53+ const struct wpcm450_bank *bank;
54+};
55+
56+struct wpcm450_pinctrl {
57+ struct pinctrl_dev *pctldev;
58+ struct device *dev;
59+ struct irq_domain *domain;
60+ struct regmap *gcr_regmap;
61+ void __iomem *gpio_base;
62+ struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS];
63+ unsigned long both_edges;
64+
65+ /*
66+ * This spin lock protects registers and struct wpcm450_pinctrl fields
67+ * against concurrent access.
68+ */
69+ raw_spinlock_t lock;
70+};
71+
72+struct wpcm450_bank {
73+ /* Range of GPIOs in this port */
74+ u8 base;
75+ u8 length;
76+
77+ /* Register offsets (0 = register doesn't exist in this port) */
78+ u8 cfg0, cfg1, cfg2;
79+ u8 blink;
80+ u8 dataout, datain;
81+
82+ /* Interrupt bit mapping */
83+ u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */
84+ u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */
85+ u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */
86+};
87+
88+static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = {
89+ /* range cfg0 cfg1 cfg2 blink out in IRQ map */
90+ { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 },
91+ { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 },
92+ { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 },
93+ { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 },
94+ { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 },
95+ { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 },
96+ { 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 },
97+ { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 },
98+};
99+
100+static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d)
101+{
102+ const struct wpcm450_bank *bank = gpio->bank;
103+ int hwirq = irqd_to_hwirq(d);
104+
105+ if (hwirq < bank->first_irq_gpio)
106+ return -EINVAL;
107+
108+ if (hwirq - bank->first_irq_gpio >= bank->num_irqs)
109+ return -EINVAL;
110+
111+ return hwirq - bank->first_irq_gpio + bank->first_irq_bit;
112+}
113+
114+static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum)
115+{
116+ const struct wpcm450_bank *bank = gpio->bank;
117+
118+ if (bitnum < bank->first_irq_bit)
119+ return -EINVAL;
120+
121+ if (bitnum - bank->first_irq_bit > bank->num_irqs)
122+ return -EINVAL;
123+
124+ return bitnum - bank->first_irq_bit + bank->first_irq_gpio;
125+}
126+
127+static void wpcm450_gpio_irq_ack(struct irq_data *d)
128+{
129+ struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
130+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
131+ unsigned long flags;
132+ int bit;
133+
134+ bit = wpcm450_gpio_irq_bitnum(gpio, d);
135+ if (bit < 0)
136+ return;
137+
138+ raw_spin_lock_irqsave(&pctrl->lock, flags);
139+ iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
140+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
141+}
142+
143+static void wpcm450_gpio_irq_mask(struct irq_data *d)
144+{
145+ struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
146+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
147+ unsigned long flags;
148+ unsigned long even;
149+ int bit;
150+
151+ bit = wpcm450_gpio_irq_bitnum(gpio, d);
152+ if (bit < 0)
153+ return;
154+
155+ raw_spin_lock_irqsave(&pctrl->lock, flags);
156+ even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
157+ __assign_bit(bit, &even, 0);
158+ iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
159+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
160+}
161+
162+static void wpcm450_gpio_irq_unmask(struct irq_data *d)
163+{
164+ struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
165+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
166+ unsigned long flags;
167+ unsigned long even;
168+ int bit;
169+
170+ bit = wpcm450_gpio_irq_bitnum(gpio, d);
171+ if (bit < 0)
172+ return;
173+
174+ raw_spin_lock_irqsave(&pctrl->lock, flags);
175+ even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
176+ __assign_bit(bit, &even, 1);
177+ iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
178+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
179+}
180+
181+/*
182+ * This is an implementation of the gpio_chip->get() function, for use in
183+ * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided
184+ * implementation there, because it would require taking gpio_chip->bgpio_lock,
185+ * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where
186+ * a raw spin lock is held.
187+ */
188+static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset)
189+{
190+ void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
191+ unsigned long flags;
192+ u32 level;
193+
194+ raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
195+ level = !!(ioread32(reg) & BIT(offset));
196+ raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
197+
198+ return level;
199+}
200+
201+/*
202+ * Since the GPIO controller does not support dual-edge triggered interrupts
203+ * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered
204+ * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the
205+ * specified emulated dual-edge triggered interrupts, so that the next edge can
206+ * be detected.
207+ */
208+static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all)
209+{
210+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
211+ unsigned int bit;
212+
213+ for_each_set_bit(bit, &all, 32) {
214+ int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
215+ unsigned long evpol;
216+ unsigned long flags;
217+ int level;
218+
219+ do {
220+ level = wpcm450_gpio_get(gpio, offset);
221+
222+ /* Switch event polarity to the opposite of the current level */
223+ raw_spin_lock_irqsave(&pctrl->lock, flags);
224+ evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
225+ __assign_bit(bit, &evpol, !level);
226+ iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
227+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
228+
229+ } while (wpcm450_gpio_get(gpio, offset) != level);
230+ }
231+}
232+
233+static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type)
234+{
235+ struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
236+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
237+ unsigned long evtype, evpol;
238+ unsigned long flags;
239+ int ret = 0;
240+ int bit;
241+
242+ bit = wpcm450_gpio_irq_bitnum(gpio, d);
243+ if (bit < 0)
244+ return bit;
245+
246+ irq_set_handler_locked(d, handle_level_irq);
247+
248+ raw_spin_lock_irqsave(&pctrl->lock, flags);
249+ evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
250+ evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
251+ __assign_bit(bit, &pctrl->both_edges, 0);
252+ switch (flow_type) {
253+ case IRQ_TYPE_LEVEL_LOW:
254+ __assign_bit(bit, &evtype, 1);
255+ __assign_bit(bit, &evpol, 0);
256+ break;
257+ case IRQ_TYPE_LEVEL_HIGH:
258+ __assign_bit(bit, &evtype, 1);
259+ __assign_bit(bit, &evpol, 1);
260+ break;
261+ case IRQ_TYPE_EDGE_FALLING:
262+ __assign_bit(bit, &evtype, 0);
263+ __assign_bit(bit, &evpol, 0);
264+ break;
265+ case IRQ_TYPE_EDGE_RISING:
266+ __assign_bit(bit, &evtype, 0);
267+ __assign_bit(bit, &evpol, 1);
268+ break;
269+ case IRQ_TYPE_EDGE_BOTH:
270+ __assign_bit(bit, &evtype, 0);
271+ __assign_bit(bit, &pctrl->both_edges, 1);
272+ break;
273+ default:
274+ ret = -EINVAL;
275+ }
276+ iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
277+ iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
278+
279+ /* clear the event status for good measure */
280+ iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
281+
282+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
283+
284+ /* fix event polarity after clearing event status */
285+ wpcm450_gpio_fix_evpol(gpio, BIT(bit));
286+
287+ return ret;
288+}
289+
290+static const struct irq_chip wpcm450_gpio_irqchip = {
291+ .name = "WPCM450-GPIO-IRQ",
292+ .irq_ack = wpcm450_gpio_irq_ack,
293+ .irq_unmask = wpcm450_gpio_irq_unmask,
294+ .irq_mask = wpcm450_gpio_irq_mask,
295+ .irq_set_type = wpcm450_gpio_set_irq_type,
296+};
297+
298+static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
299+{
300+ struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc));
301+ struct wpcm450_pinctrl *pctrl = gpio->pctrl;
302+ struct irq_chip *chip = irq_desc_get_chip(desc);
303+ unsigned long pending;
304+ unsigned long flags;
305+ unsigned long ours;
306+ unsigned int bit;
307+
308+ ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;
309+
310+ raw_spin_lock_irqsave(&pctrl->lock, flags);
311+
312+ pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
313+ pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
314+ pending &= ours;
315+
316+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
317+
318+ if (pending & pctrl->both_edges)
319+ wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
320+
321+ chained_irq_enter(chip, desc);
322+ for_each_set_bit(bit, &pending, 32) {
323+ int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
324+
325+ generic_handle_domain_irq(gpio->gc.irq.domain, offset);
326+ }
327+ chained_irq_exit(chip, desc);
328+}
329+
330+static int smb0_pins[] = { 115, 114 };
331+static int smb1_pins[] = { 117, 116 };
332+static int smb2_pins[] = { 119, 118 };
333+static int smb3_pins[] = { 30, 31 };
334+static int smb4_pins[] = { 28, 29 };
335+static int smb5_pins[] = { 26, 27 };
336+
337+static int scs1_pins[] = { 32 };
338+static int scs2_pins[] = { 33 };
339+static int scs3_pins[] = { 34 };
340+
341+static int bsp_pins[] = { 41, 42 };
342+static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
343+static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
344+
345+static int r1err_pins[] = { 56 };
346+static int r1md_pins[] = { 57, 58 };
347+static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 };
348+static int r2err_pins[] = { 90 };
349+static int r2md_pins[] = { 91, 92 };
350+
351+static int kbcc_pins[] = { 94, 93 };
352+static int clko_pins[] = { 96 };
353+static int smi_pins[] = { 97 };
354+static int uinc_pins[] = { 19 };
355+static int mben_pins[] = {};
356+
357+static int gspi_pins[] = { 12, 13, 14, 15 };
358+static int sspi_pins[] = { 12, 13, 14, 15 };
359+
360+static int xcs1_pins[] = { 35 };
361+static int xcs2_pins[] = { 36 };
362+
363+static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 };
364+
365+static int fi0_pins[] = { 64 };
366+static int fi1_pins[] = { 65 };
367+static int fi2_pins[] = { 66 };
368+static int fi3_pins[] = { 67 };
369+static int fi4_pins[] = { 68 };
370+static int fi5_pins[] = { 69 };
371+static int fi6_pins[] = { 70 };
372+static int fi7_pins[] = { 71 };
373+static int fi8_pins[] = { 72 };
374+static int fi9_pins[] = { 73 };
375+static int fi10_pins[] = { 74 };
376+static int fi11_pins[] = { 75 };
377+static int fi12_pins[] = { 76 };
378+static int fi13_pins[] = { 77 };
379+static int fi14_pins[] = { 78 };
380+static int fi15_pins[] = { 79 };
381+
382+static int pwm0_pins[] = { 80 };
383+static int pwm1_pins[] = { 81 };
384+static int pwm2_pins[] = { 82 };
385+static int pwm3_pins[] = { 83 };
386+static int pwm4_pins[] = { 20 };
387+static int pwm5_pins[] = { 21 };
388+static int pwm6_pins[] = { 16 };
389+static int pwm7_pins[] = { 17 };
390+
391+static int hg0_pins[] = { 20 };
392+static int hg1_pins[] = { 21 };
393+static int hg2_pins[] = { 22 };
394+static int hg3_pins[] = { 23 };
395+static int hg4_pins[] = { 24 };
396+static int hg5_pins[] = { 25 };
397+static int hg6_pins[] = { 59 };
398+static int hg7_pins[] = { 60 };
399+
400+#define WPCM450_GRPS \
401+ WPCM450_GRP(smb3), \
402+ WPCM450_GRP(smb4), \
403+ WPCM450_GRP(smb5), \
404+ WPCM450_GRP(scs1), \
405+ WPCM450_GRP(scs2), \
406+ WPCM450_GRP(scs3), \
407+ WPCM450_GRP(smb0), \
408+ WPCM450_GRP(smb1), \
409+ WPCM450_GRP(smb2), \
410+ WPCM450_GRP(bsp), \
411+ WPCM450_GRP(hsp1), \
412+ WPCM450_GRP(hsp2), \
413+ WPCM450_GRP(r1err), \
414+ WPCM450_GRP(r1md), \
415+ WPCM450_GRP(rmii2), \
416+ WPCM450_GRP(r2err), \
417+ WPCM450_GRP(r2md), \
418+ WPCM450_GRP(kbcc), \
419+ WPCM450_GRP(clko), \
420+ WPCM450_GRP(smi), \
421+ WPCM450_GRP(uinc), \
422+ WPCM450_GRP(gspi), \
423+ WPCM450_GRP(mben), \
424+ WPCM450_GRP(xcs2), \
425+ WPCM450_GRP(xcs1), \
426+ WPCM450_GRP(sdio), \
427+ WPCM450_GRP(sspi), \
428+ WPCM450_GRP(fi0), \
429+ WPCM450_GRP(fi1), \
430+ WPCM450_GRP(fi2), \
431+ WPCM450_GRP(fi3), \
432+ WPCM450_GRP(fi4), \
433+ WPCM450_GRP(fi5), \
434+ WPCM450_GRP(fi6), \
435+ WPCM450_GRP(fi7), \
436+ WPCM450_GRP(fi8), \
437+ WPCM450_GRP(fi9), \
438+ WPCM450_GRP(fi10), \
439+ WPCM450_GRP(fi11), \
440+ WPCM450_GRP(fi12), \
441+ WPCM450_GRP(fi13), \
442+ WPCM450_GRP(fi14), \
443+ WPCM450_GRP(fi15), \
444+ WPCM450_GRP(pwm0), \
445+ WPCM450_GRP(pwm1), \
446+ WPCM450_GRP(pwm2), \
447+ WPCM450_GRP(pwm3), \
448+ WPCM450_GRP(pwm4), \
449+ WPCM450_GRP(pwm5), \
450+ WPCM450_GRP(pwm6), \
451+ WPCM450_GRP(pwm7), \
452+ WPCM450_GRP(hg0), \
453+ WPCM450_GRP(hg1), \
454+ WPCM450_GRP(hg2), \
455+ WPCM450_GRP(hg3), \
456+ WPCM450_GRP(hg4), \
457+ WPCM450_GRP(hg5), \
458+ WPCM450_GRP(hg6), \
459+ WPCM450_GRP(hg7), \
460+
461+enum {
462+#define WPCM450_GRP(x) fn_ ## x
463+ WPCM450_GRPS
464+ /* add placeholder for none/gpio */
465+ WPCM450_GRP(gpio),
466+ WPCM450_GRP(none),
467+#undef WPCM450_GRP
468+};
469+
470+static struct group_desc wpcm450_groups[] = {
471+#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
472+ .num_pins = ARRAY_SIZE(x ## _pins) }
473+ WPCM450_GRPS
474+#undef WPCM450_GRP
475+};
476+
477+#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a)
478+#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b }
479+#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
480+ .groups = nm ## _grp }
481+struct wpcm450_func {
482+ const char *name;
483+ const unsigned int ngroups;
484+ const char *const *groups;
485+};
486+
487+WPCM450_SFUNC(smb3);
488+WPCM450_SFUNC(smb4);
489+WPCM450_SFUNC(smb5);
490+WPCM450_SFUNC(scs1);
491+WPCM450_SFUNC(scs2);
492+WPCM450_SFUNC(scs3);
493+WPCM450_SFUNC(smb0);
494+WPCM450_SFUNC(smb1);
495+WPCM450_SFUNC(smb2);
496+WPCM450_SFUNC(bsp);
497+WPCM450_SFUNC(hsp1);
498+WPCM450_SFUNC(hsp2);
499+WPCM450_SFUNC(r1err);
500+WPCM450_SFUNC(r1md);
501+WPCM450_SFUNC(rmii2);
502+WPCM450_SFUNC(r2err);
503+WPCM450_SFUNC(r2md);
504+WPCM450_SFUNC(kbcc);
505+WPCM450_SFUNC(clko);
506+WPCM450_SFUNC(smi);
507+WPCM450_SFUNC(uinc);
508+WPCM450_SFUNC(gspi);
509+WPCM450_SFUNC(mben);
510+WPCM450_SFUNC(xcs2);
511+WPCM450_SFUNC(xcs1);
512+WPCM450_SFUNC(sdio);
513+WPCM450_SFUNC(sspi);
514+WPCM450_SFUNC(fi0);
515+WPCM450_SFUNC(fi1);
516+WPCM450_SFUNC(fi2);
517+WPCM450_SFUNC(fi3);
518+WPCM450_SFUNC(fi4);
519+WPCM450_SFUNC(fi5);
520+WPCM450_SFUNC(fi6);
521+WPCM450_SFUNC(fi7);
522+WPCM450_SFUNC(fi8);
523+WPCM450_SFUNC(fi9);
524+WPCM450_SFUNC(fi10);
525+WPCM450_SFUNC(fi11);
526+WPCM450_SFUNC(fi12);
527+WPCM450_SFUNC(fi13);
528+WPCM450_SFUNC(fi14);
529+WPCM450_SFUNC(fi15);
530+WPCM450_SFUNC(pwm0);
531+WPCM450_SFUNC(pwm1);
532+WPCM450_SFUNC(pwm2);
533+WPCM450_SFUNC(pwm3);
534+WPCM450_SFUNC(pwm4);
535+WPCM450_SFUNC(pwm5);
536+WPCM450_SFUNC(pwm6);
537+WPCM450_SFUNC(pwm7);
538+WPCM450_SFUNC(hg0);
539+WPCM450_SFUNC(hg1);
540+WPCM450_SFUNC(hg2);
541+WPCM450_SFUNC(hg3);
542+WPCM450_SFUNC(hg4);
543+WPCM450_SFUNC(hg5);
544+WPCM450_SFUNC(hg6);
545+WPCM450_SFUNC(hg7);
546+
547+#define WPCM450_GRP(x) #x
548+WPCM450_FUNC(gpio, WPCM450_GRPS);
549+#undef WPCM450_GRP
550+
551+/* Function names */
552+static struct wpcm450_func wpcm450_funcs[] = {
553+ WPCM450_MKFUNC(smb3),
554+ WPCM450_MKFUNC(smb4),
555+ WPCM450_MKFUNC(smb5),
556+ WPCM450_MKFUNC(scs1),
557+ WPCM450_MKFUNC(scs2),
558+ WPCM450_MKFUNC(scs3),
559+ WPCM450_MKFUNC(smb0),
560+ WPCM450_MKFUNC(smb1),
561+ WPCM450_MKFUNC(smb2),
562+ WPCM450_MKFUNC(bsp),
563+ WPCM450_MKFUNC(hsp1),
564+ WPCM450_MKFUNC(hsp2),
565+ WPCM450_MKFUNC(r1err),
566+ WPCM450_MKFUNC(r1md),
567+ WPCM450_MKFUNC(rmii2),
568+ WPCM450_MKFUNC(r2err),
569+ WPCM450_MKFUNC(r2md),
570+ WPCM450_MKFUNC(kbcc),
571+ WPCM450_MKFUNC(clko),
572+ WPCM450_MKFUNC(smi),
573+ WPCM450_MKFUNC(uinc),
574+ WPCM450_MKFUNC(gspi),
575+ WPCM450_MKFUNC(mben),
576+ WPCM450_MKFUNC(xcs2),
577+ WPCM450_MKFUNC(xcs1),
578+ WPCM450_MKFUNC(sdio),
579+ WPCM450_MKFUNC(sspi),
580+ WPCM450_MKFUNC(fi0),
581+ WPCM450_MKFUNC(fi1),
582+ WPCM450_MKFUNC(fi2),
583+ WPCM450_MKFUNC(fi3),
584+ WPCM450_MKFUNC(fi4),
585+ WPCM450_MKFUNC(fi5),
586+ WPCM450_MKFUNC(fi6),
587+ WPCM450_MKFUNC(fi7),
588+ WPCM450_MKFUNC(fi8),
589+ WPCM450_MKFUNC(fi9),
590+ WPCM450_MKFUNC(fi10),
591+ WPCM450_MKFUNC(fi11),
592+ WPCM450_MKFUNC(fi12),
593+ WPCM450_MKFUNC(fi13),
594+ WPCM450_MKFUNC(fi14),
595+ WPCM450_MKFUNC(fi15),
596+ WPCM450_MKFUNC(pwm0),
597+ WPCM450_MKFUNC(pwm1),
598+ WPCM450_MKFUNC(pwm2),
599+ WPCM450_MKFUNC(pwm3),
600+ WPCM450_MKFUNC(pwm4),
601+ WPCM450_MKFUNC(pwm5),
602+ WPCM450_MKFUNC(pwm6),
603+ WPCM450_MKFUNC(pwm7),
604+ WPCM450_MKFUNC(hg0),
605+ WPCM450_MKFUNC(hg1),
606+ WPCM450_MKFUNC(hg2),
607+ WPCM450_MKFUNC(hg3),
608+ WPCM450_MKFUNC(hg4),
609+ WPCM450_MKFUNC(hg5),
610+ WPCM450_MKFUNC(hg6),
611+ WPCM450_MKFUNC(hg7),
612+ WPCM450_MKFUNC(gpio),
613+};
614+
615+#define WPCM450_PINCFG(a, b, c, d, e, f, g) \
616+ [a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \
617+ .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g }
618+
619+struct wpcm450_pincfg {
620+ int fn0, reg0, bit0;
621+ int fn1, reg1, bit1;
622+};
623+
624+static const struct wpcm450_pincfg pincfg[] = {
625+ /* PIN FUNCTION 1 FUNCTION 2 */
626+ WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0),
627+ WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0),
628+ WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0),
629+ WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0),
630+ WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0),
631+ WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0),
632+ WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0),
633+ WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30),
634+ WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0),
635+ WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0),
636+ WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0),
637+ WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0),
638+ WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
639+ WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
640+ WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
641+ WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
642+ WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22),
643+ WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23),
644+ WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0),
645+ WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0),
646+ WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20),
647+ WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21),
648+ WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0),
649+ WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0),
650+ WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0),
651+ WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0),
652+ WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0),
653+ WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0),
654+ WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0),
655+ WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0),
656+ WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0),
657+ WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0),
658+
659+ WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0),
660+ WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0),
661+ WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0),
662+ WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0),
663+ WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0),
664+ WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */
665+ WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */
666+ WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */
667+ WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */
668+ WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0),
669+ WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0),
670+ WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
671+ WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
672+ WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
673+ WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
674+ WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
675+ WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0),
676+ WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0),
677+ WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0),
678+ WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0),
679+ WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0),
680+ WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0),
681+ WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0),
682+ WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0),
683+ WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0),
684+ WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0),
685+ WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0),
686+ WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0),
687+ WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30),
688+ WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0),
689+ WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0),
690+ WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0),
691+
692+ WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0),
693+ WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0),
694+ WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0),
695+ WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0),
696+ WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0),
697+ WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0),
698+ WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0),
699+ WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0),
700+ WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0),
701+ WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0),
702+ WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0),
703+ WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0),
704+ WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0),
705+ WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0),
706+ WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0),
707+ WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0),
708+ WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0),
709+ WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0),
710+ WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0),
711+ WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0),
712+ WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0),
713+ WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0),
714+ WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0),
715+ WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0),
716+ WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0),
717+ WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0),
718+ WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0),
719+ WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0),
720+ WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0),
721+ WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0),
722+ WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0),
723+ WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0),
724+
725+ WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0),
726+ WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0),
727+ WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0),
728+ WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0),
729+ WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0),
730+ WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0),
731+ WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0),
732+ WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0),
733+ WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0),
734+ WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0),
735+ WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0),
736+ WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0),
737+ WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */
738+ WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */
739+ WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */
740+ WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */
741+ WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */
742+ WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */
743+ WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0),
744+ WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0),
745+ WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0),
746+ WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0),
747+ WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0),
748+ WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0),
749+ WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */
750+ WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */
751+ WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */
752+ WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */
753+ WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */
754+ WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */
755+ WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */
756+ WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */
757+};
758+
759+#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n)
760+
761+static const struct pinctrl_pin_desc wpcm450_pins[] = {
762+ WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3),
763+ WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7),
764+ WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11),
765+ WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15),
766+ WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19),
767+ WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23),
768+ WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27),
769+ WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31),
770+ WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35),
771+ WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39),
772+ WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43),
773+ WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47),
774+ WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51),
775+ WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55),
776+ WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59),
777+ WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63),
778+ WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67),
779+ WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71),
780+ WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75),
781+ WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79),
782+ WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83),
783+ WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87),
784+ WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91),
785+ WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95),
786+ WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99),
787+ WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103),
788+ WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107),
789+ WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111),
790+ WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115),
791+ WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119),
792+ WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123),
793+ WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
794+};
795+
796+/* Enable mode in pin group */
797+static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
798+ int npins, int func)
799+{
800+ const struct wpcm450_pincfg *cfg;
801+ int i;
802+
803+ for (i = 0; i < npins; i++) {
804+ cfg = &pincfg[pin[i]];
805+ if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) {
806+ if (cfg->reg0)
807+ regmap_update_bits(gcr_regmap, cfg->reg0,
808+ BIT(cfg->bit0),
809+ (cfg->fn0 == func) ? BIT(cfg->bit0) : 0);
810+ if (cfg->reg1)
811+ regmap_update_bits(gcr_regmap, cfg->reg1,
812+ BIT(cfg->bit1),
813+ (cfg->fn1 == func) ? BIT(cfg->bit1) : 0);
814+ }
815+ }
816+}
817+
818+static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev)
819+{
820+ return ARRAY_SIZE(wpcm450_groups);
821+}
822+
823+static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev,
824+ unsigned int selector)
825+{
826+ return wpcm450_groups[selector].name;
827+}
828+
829+static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
830+ unsigned int selector,
831+ const unsigned int **pins,
832+ unsigned int *npins)
833+{
834+ *npins = wpcm450_groups[selector].num_pins;
835+ *pins = wpcm450_groups[selector].pins;
836+
837+ return 0;
838+}
839+
840+static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
841+ struct device_node *np_config,
842+ struct pinctrl_map **map,
843+ u32 *num_maps)
844+{
845+ return pinconf_generic_dt_node_to_map(pctldev, np_config,
846+ map, num_maps,
847+ PIN_MAP_TYPE_INVALID);
848+}
849+
850+static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
851+ struct pinctrl_map *map, u32 num_maps)
852+{
853+ kfree(map);
854+}
855+
856+static const struct pinctrl_ops wpcm450_pinctrl_ops = {
857+ .get_groups_count = wpcm450_get_groups_count,
858+ .get_group_name = wpcm450_get_group_name,
859+ .get_group_pins = wpcm450_get_group_pins,
860+ .dt_node_to_map = wpcm450_dt_node_to_map,
861+ .dt_free_map = wpcm450_dt_free_map,
862+};
863+
864+static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev)
865+{
866+ return ARRAY_SIZE(wpcm450_funcs);
867+}
868+
869+static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev,
870+ unsigned int function)
871+{
872+ return wpcm450_funcs[function].name;
873+}
874+
875+static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev,
876+ unsigned int function,
877+ const char * const **groups,
878+ unsigned int * const ngroups)
879+{
880+ *ngroups = wpcm450_funcs[function].ngroups;
881+ *groups = wpcm450_funcs[function].groups;
882+
883+ return 0;
884+}
885+
886+static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
887+ unsigned int function,
888+ unsigned int group)
889+{
890+ struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
891+
892+ wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
893+ wpcm450_groups[group].num_pins, function);
894+
895+ return 0;
896+}
897+
898+static const struct pinmux_ops wpcm450_pinmux_ops = {
899+ .get_functions_count = wpcm450_get_functions_count,
900+ .get_function_name = wpcm450_get_function_name,
901+ .get_function_groups = wpcm450_get_function_groups,
902+ .set_mux = wpcm450_pinmux_set_mux,
903+};
904+
905+static int debounce_bitnum(int gpio)
906+{
907+ if (gpio >= 0 && gpio < 16)
908+ return gpio;
909+ return -EINVAL;
910+}
911+
912+static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
913+ unsigned long *config)
914+{
915+ struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
916+ enum pin_config_param param = pinconf_to_config_param(*config);
917+ unsigned long flags;
918+ int bit;
919+ u32 reg;
920+
921+ switch (param) {
922+ case PIN_CONFIG_INPUT_DEBOUNCE:
923+ bit = debounce_bitnum(pin);
924+ if (bit < 0)
925+ return bit;
926+
927+ raw_spin_lock_irqsave(&pctrl->lock, flags);
928+ reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
929+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
930+
931+ *config = pinconf_to_config_packed(param, !!(reg & BIT(bit)));
932+ return 0;
933+ default:
934+ return -ENOTSUPP;
935+ }
936+}
937+
938+static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
939+ unsigned int pin, unsigned long config)
940+{
941+ enum pin_config_param param = pinconf_to_config_param(config);
942+ unsigned long flags;
943+ unsigned long reg;
944+ int bit;
945+ int arg;
946+
947+ switch (param) {
948+ case PIN_CONFIG_INPUT_DEBOUNCE:
949+ bit = debounce_bitnum(pin);
950+ if (bit < 0)
951+ return bit;
952+
953+ arg = pinconf_to_config_argument(config);
954+
955+ raw_spin_lock_irqsave(&pctrl->lock, flags);
956+ reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
957+ __assign_bit(bit, &reg, arg);
958+ iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
959+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
960+ return 0;
961+ default:
962+ return -ENOTSUPP;
963+ }
964+}
965+
966+static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
967+ unsigned long *configs, unsigned int num_configs)
968+{
969+ struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
970+ int ret;
971+
972+ while (num_configs--) {
973+ ret = wpcm450_config_set_one(pctrl, pin, *configs++);
974+ if (ret)
975+ return ret;
976+ }
977+
978+ return 0;
979+}
980+
981+static const struct pinconf_ops wpcm450_pinconf_ops = {
982+ .is_generic = true,
983+ .pin_config_get = wpcm450_config_get,
984+ .pin_config_set = wpcm450_config_set,
985+};
986+
987+static struct pinctrl_desc wpcm450_pinctrl_desc = {
988+ .name = "wpcm450-pinctrl",
989+ .pins = wpcm450_pins,
990+ .npins = ARRAY_SIZE(wpcm450_pins),
991+ .pctlops = &wpcm450_pinctrl_ops,
992+ .pmxops = &wpcm450_pinmux_ops,
993+ .confops = &wpcm450_pinconf_ops,
994+ .owner = THIS_MODULE,
995+};
996+
997+static int wpcm450_gpio_set_config(struct gpio_chip *chip,
998+ unsigned int offset, unsigned long config)
999+{
1000+ struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1001+
1002+ return wpcm450_config_set_one(gpio->pctrl, offset, config);
1003+}
1004+
1005+static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip)
1006+{
1007+ struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1008+ const struct wpcm450_bank *bank = gpio->bank;
1009+
1010+ return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
1011+ 0, bank->base, bank->length);
1012+}
1013+
1014+static int wpcm450_gpio_register(struct platform_device *pdev,
1015+ struct wpcm450_pinctrl *pctrl)
1016+{
1017+ struct device *dev = &pdev->dev;
1018+ struct fwnode_handle *child;
1019+ int ret;
1020+
1021+ pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
1022+ if (IS_ERR(pctrl->gpio_base))
1023+ return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
1024+ "Resource fail for GPIO controller\n");
1025+
1026+ device_for_each_child_node(dev, child) {
1027+ void __iomem *dat = NULL;
1028+ void __iomem *set = NULL;
1029+ void __iomem *dirout = NULL;
1030+ unsigned long flags = 0;
1031+ const struct wpcm450_bank *bank;
1032+ struct wpcm450_gpio *gpio;
1033+ struct gpio_irq_chip *girq;
1034+ u32 reg;
1035+ int i;
1036+
1037+ if (!fwnode_property_read_bool(child, "gpio-controller"))
1038+ continue;
1039+
1040+ ret = fwnode_property_read_u32(child, "reg", &reg);
1041+ if (ret < 0)
1042+ return ret;
1043+
1044+ gpio = &pctrl->gpio_bank[reg];
1045+ gpio->pctrl = pctrl;
1046+
1047+ if (reg >= WPCM450_NUM_BANKS)
1048+ return dev_err_probe(dev, -EINVAL,
1049+ "GPIO index %d out of range!\n", reg);
1050+
1051+ bank = &wpcm450_banks[reg];
1052+ gpio->bank = bank;
1053+
1054+ dat = pctrl->gpio_base + bank->datain;
1055+ if (bank->dataout) {
1056+ set = pctrl->gpio_base + bank->dataout;
1057+ dirout = pctrl->gpio_base + bank->cfg0;
1058+ } else {
1059+ flags = BGPIOF_NO_OUTPUT;
1060+ }
1061+ ret = bgpio_init(&gpio->gc, dev, 4,
1062+ dat, set, NULL, dirout, NULL, flags);
1063+ if (ret < 0)
1064+ return dev_err_probe(dev, ret, "GPIO initialization failed\n");
1065+
1066+ gpio->gc.ngpio = bank->length;
1067+ gpio->gc.set_config = wpcm450_gpio_set_config;
1068+ gpio->gc.fwnode = child;
1069+ gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
1070+
1071+ gpio->irqc = wpcm450_gpio_irqchip;
1072+ girq = &gpio->gc.irq;
1073+ girq->chip = &gpio->irqc;
1074+ girq->parent_handler = wpcm450_gpio_irqhandler;
1075+ girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
1076+ sizeof(*girq->parents), GFP_KERNEL);
1077+ if (!girq->parents)
1078+ return -ENOMEM;
1079+ girq->default_type = IRQ_TYPE_NONE;
1080+ girq->handler = handle_bad_irq;
1081+
1082+ girq->num_parents = 0;
1083+ for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
1084+ int irq = fwnode_irq_get(child, i);
1085+
1086+ if (irq < 0)
1087+ break;
1088+
1089+ girq->parents[i] = irq;
1090+ girq->num_parents++;
1091+ }
1092+
1093+ ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
1094+ if (ret)
1095+ return dev_err_probe(dev, ret, "Failed to add GPIO chip\n");
1096+ }
1097+
1098+ return 0;
1099+}
1100+
1101+static int wpcm450_pinctrl_probe(struct platform_device *pdev)
1102+{
1103+ struct device *dev = &pdev->dev;
1104+ struct wpcm450_pinctrl *pctrl;
1105+ int ret;
1106+
1107+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1108+ if (!pctrl)
1109+ return -ENOMEM;
1110+
1111+ pctrl->dev = &pdev->dev;
1112+ raw_spin_lock_init(&pctrl->lock);
1113+ dev_set_drvdata(dev, pctrl);
1114+
1115+ pctrl->gcr_regmap =
1116+ syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
1117+ if (IS_ERR(pctrl->gcr_regmap))
1118+ return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
1119+ "Failed to find nuvoton,wpcm450-gcr\n");
1120+
1121+ pctrl->pctldev = devm_pinctrl_register(dev,
1122+ &wpcm450_pinctrl_desc, pctrl);
1123+ if (IS_ERR(pctrl->pctldev))
1124+ return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
1125+ "Failed to register pinctrl device\n");
1126+
1127+ ret = wpcm450_gpio_register(pdev, pctrl);
1128+ if (ret < 0)
1129+ return ret;
1130+
1131+ return 0;
1132+}
1133+
1134+static const struct of_device_id wpcm450_pinctrl_match[] = {
1135+ { .compatible = "nuvoton,wpcm450-pinctrl" },
1136+ { }
1137+};
1138+MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match);
1139+
1140+static struct platform_driver wpcm450_pinctrl_driver = {
1141+ .probe = wpcm450_pinctrl_probe,
1142+ .driver = {
1143+ .name = "wpcm450-pinctrl",
1144+ .of_match_table = wpcm450_pinctrl_match,
1145+ },
1146+};
1147+module_platform_driver(wpcm450_pinctrl_driver);
1148+
1149+MODULE_LICENSE("GPL v2");
1150+MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
1151+MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver");
drivers/pinctrl/pinconf-generic.c+3−3
@@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] = { · 29 unmodified lines
3030 PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
3131 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
3232 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
33− PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),
33+ PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true),
3434 PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
35− "input bias pull to pin specific state", NULL, false),
36− PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
35+ "input bias pull to pin specific state", "ohms", true),
36+ PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true),
3737 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
3838 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
3939 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
drivers/pinctrl/pinctrl-at91-pio4.c+7−9
@@ -1045,7 +1045,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) · 1044 unmodified lines
10451045 const char **group_names;
10461046 const struct of_device_id *match;
10471047 int i, ret;
1048− struct resource *res;
10491048 struct atmel_pioctrl *atmel_pioctrl;
10501049 const struct atmel_pioctrl_data *atmel_pioctrl_data;
10511050
@@ -1164,16 +1163,15 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) · 112 unmodified lines
11641163
11651164 /* There is one controller but each bank has its own irq line. */
11661165 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1167− res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1168− if (!res) {
1169− dev_err(dev, "missing irq resource for group %c\n",
1166+ ret = platform_get_irq(pdev, i);
1167+ if (ret < 0) {
1168+ dev_dbg(dev, "missing irq resource for group %c\n",
11701169 'A' + i);
1171− return -EINVAL;
1170+ return ret;
11721171 }
1173− atmel_pioctrl->irqs[i] = res->start;
1174− irq_set_chained_handler_and_data(res->start,
1175− atmel_gpio_irq_handler, atmel_pioctrl);
1176− dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1172+ atmel_pioctrl->irqs[i] = ret;
1173+ irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
1174+ dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
11771175 }
11781176
11791177 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
drivers/pinctrl/pinctrl-ingenic.c+45−1
@@ -119,6 +119,8 @@ struct ingenic_chip_info { · 118 unmodified lines
119119 unsigned int num_functions;
120120
121121 const u32 *pull_ups, *pull_downs;
122+
123+ const struct regmap_access_table *access_table;
122124 };
123125
124126 struct ingenic_pinctrl {
@@ -2179,6 +2181,17 @@ static const struct function_desc x1000_functions[] = { · 2054 unmodified lines
21792181 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
21802182 };
21812183
2184+static const struct regmap_range x1000_access_ranges[] = {
2185+ regmap_reg_range(0x000, 0x400 - 4),
2186+ regmap_reg_range(0x700, 0x800 - 4),
2187+};
2188+
2189+/* shared with X1500 */
2190+static const struct regmap_access_table x1000_access_table = {
2191+ .yes_ranges = x1000_access_ranges,
2192+ .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
2193+};
2194+
21822195 static const struct ingenic_chip_info x1000_chip_info = {
21832196 .num_chips = 4,
21842197 .reg_offset = 0x100,
@@ -2189,6 +2202,7 @@ static const struct ingenic_chip_info x1000_chip_info = { · 4 unmodified lines
21892202 .num_functions = ARRAY_SIZE(x1000_functions),
21902203 .pull_ups = x1000_pull_ups,
21912204 .pull_downs = x1000_pull_downs,
2205+ .access_table = &x1000_access_table,
21922206 };
21932207
21942208 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
@@ -2300,6 +2314,7 @@ static const struct ingenic_chip_info x1500_chip_info = { · 105 unmodified lines
23002314 .num_functions = ARRAY_SIZE(x1500_functions),
23012315 .pull_ups = x1000_pull_ups,
23022316 .pull_downs = x1000_pull_downs,
2317+ .access_table = &x1000_access_table,
23032318 };
23042319
23052320 static const u32 x1830_pull_ups[4] = {
@@ -2506,6 +2521,16 @@ static const struct function_desc x1830_functions[] = { · 200 unmodified lines
25062521 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
25072522 };
25082523
2524+static const struct regmap_range x1830_access_ranges[] = {
2525+ regmap_reg_range(0x0000, 0x4000 - 4),
2526+ regmap_reg_range(0x7000, 0x8000 - 4),
2527+};
2528+
2529+static const struct regmap_access_table x1830_access_table = {
2530+ .yes_ranges = x1830_access_ranges,
2531+ .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
2532+};
2533+
25092534 static const struct ingenic_chip_info x1830_chip_info = {
25102535 .num_chips = 4,
25112536 .reg_offset = 0x1000,
@@ -2516,6 +2541,7 @@ static const struct ingenic_chip_info x1830_chip_info = { · 4 unmodified lines
25162541 .num_functions = ARRAY_SIZE(x1830_functions),
25172542 .pull_ups = x1830_pull_ups,
25182543 .pull_downs = x1830_pull_downs,
2544+ .access_table = &x1830_access_table,
25192545 };
25202546
25212547 static const u32 x2000_pull_ups[5] = {
@@ -2969,6 +2995,17 @@ static const struct function_desc x2000_functions[] = { · 447 unmodified lines
29692995 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
29702996 };
29712997
2998+static const struct regmap_range x2000_access_ranges[] = {
2999+ regmap_reg_range(0x000, 0x500 - 4),
3000+ regmap_reg_range(0x700, 0x800 - 4),
3001+};
3002+
3003+/* shared with X2100 */
3004+static const struct regmap_access_table x2000_access_table = {
3005+ .yes_ranges = x2000_access_ranges,
3006+ .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
3007+};
3008+
29723009 static const struct ingenic_chip_info x2000_chip_info = {
29733010 .num_chips = 5,
29743011 .reg_offset = 0x100,
@@ -2979,6 +3016,7 @@ static const struct ingenic_chip_info x2000_chip_info = { · 4 unmodified lines
29793016 .num_functions = ARRAY_SIZE(x2000_functions),
29803017 .pull_ups = x2000_pull_ups,
29813018 .pull_downs = x2000_pull_downs,
3019+ .access_table = &x2000_access_table,
29823020 };
29833021
29843022 static const u32 x2100_pull_ups[5] = {
@@ -3189,6 +3227,7 @@ static const struct ingenic_chip_info x2100_chip_info = { · 204 unmodified lines
31893227 .num_functions = ARRAY_SIZE(x2100_functions),
31903228 .pull_ups = x2100_pull_ups,
31913229 .pull_downs = x2100_pull_downs,
3230+ .access_table = &x2000_access_table,
31923231 };
31933232
31943233 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
@@ -4168,7 +4207,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 973 unmodified lines
41684207 return PTR_ERR(base);
41694208
41704209 regmap_config = ingenic_pinctrl_regmap_config;
4171− regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset;
4210+ if (chip_info->access_table) {
4211+ regmap_config.rd_table = chip_info->access_table;
4212+ regmap_config.wr_table = chip_info->access_table;
4213+ } else {
4214+ regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
4215+ }
41724216
41734217 jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
41744218 if (IS_ERR(jzpc->map)) {
drivers/pinctrl/pinctrl-microchip-sgpio.c+97−15
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 #include <linux/property.h>
2020 #include <linux/regmap.h>
2121 #include <linux/reset.h>
22+#include <linux/spinlock.h>
2223
2324 #include "core.h"
2425 #include "pinconf.h"
@@ -63,11 +64,13 @@ struct sgpio_properties { · 38 unmodified lines
6364 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
6465
6566 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
67+#define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
6668 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
6769 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
6870 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
6971
7072 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
73+#define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
7174 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
7275 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
7376 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
@@ -116,6 +119,9 @@ struct sgpio_priv { · 42 unmodified lines
116119 u32 clock;
117120 struct regmap *regs;
118121 const struct sgpio_properties *properties;
122+ spinlock_t lock;
123+ /* protects the config register and single shot mode */
124+ struct mutex poll_lock;
119125 };
120126
121127 struct sgpio_port_addr {
@@ -166,12 +172,11 @@ static void sgpio_writel(struct sgpio_priv *priv, · 44 unmodified lines
166172 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
167173 u32 rno, u32 off, u32 clear, u32 set)
168174 {
169− u32 val = sgpio_readl(priv, rno, off);
170−
171− val &= ~clear;
172− val |= set;
175+ u32 addr = sgpio_get_addr(priv, rno, off);
176+ int ret;
173177
174− sgpio_writel(priv, val, rno, off);
178+ ret = regmap_update_bits(priv->regs, addr, clear | set, set);
179+ WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
175180 }
176181
177182 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
@@ -224,12 +229,64 @@ static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) · 46 unmodified lines
224229 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
225230 }
226231
227−static void sgpio_output_set(struct sgpio_priv *priv,
228− struct sgpio_port_addr *addr,
229− int value)
232+static int sgpio_single_shot(struct sgpio_priv *priv)
233+{
234+ u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
235+ int ret, ret2;
236+ u32 ctrl;
237+ unsigned int single_shot;
238+ unsigned int auto_repeat;
239+
240+ switch (priv->properties->arch) {
241+ case SGPIO_ARCH_LUTON:
242+ /* not supported for now */
243+ return 0;
244+ case SGPIO_ARCH_OCELOT:
245+ single_shot = SGPIO_OCELOT_SINGLE_SHOT;
246+ auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
247+ break;
248+ case SGPIO_ARCH_SPARX5:
249+ single_shot = SGPIO_SPARX5_SINGLE_SHOT;
250+ auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
251+ break;
252+ default:
253+ return -EINVAL;
254+ }
255+
256+ /*
257+ * Trigger immediate burst. This only works when auto repeat is turned
258+ * off. Otherwise, the single shot bit will never be cleared by the
259+ * hardware. Measurements showed that an update might take as long as
260+ * the burst gap. On a LAN9668 this is about 50ms for the largest
261+ * setting.
262+ * After the manual burst, reenable the auto repeat mode again.
263+ */
264+ mutex_lock(&priv->poll_lock);
265+ ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
266+ single_shot);
267+ if (ret)
268+ goto out;
269+
270+ ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
271+ !(ctrl & single_shot), 100, 60000);
272+
273+ /* reenable auto repeat mode even if there was an error */
274+ ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
275+out:
276+ mutex_unlock(&priv->poll_lock);
277+
278+ return ret ?: ret2;
279+}
280+
281+static int sgpio_output_set(struct sgpio_priv *priv,
282+ struct sgpio_port_addr *addr,
283+ int value)
230284 {
231285 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
286+ u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
287+ bool changed;
232288 u32 clr, set;
289+ int ret;
233290
234291 switch (priv->properties->arch) {
235292 case SGPIO_ARCH_LUTON:
@@ -245,9 +302,21 @@ static void sgpio_output_set(struct sgpio_priv *priv, · 9 unmodified lines
245302 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
246303 break;
247304 default:
248− return;
305+ return -EINVAL;
249306 }
250− sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
307+
308+ ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
309+ &changed);
310+ if (ret)
311+ return ret;
312+
313+ if (changed) {
314+ ret = sgpio_single_shot(priv);
315+ if (ret)
316+ return ret;
317+ }
318+
319+ return 0;
251320 }
252321
253322 static int sgpio_output_get(struct sgpio_priv *priv,
@@ -333,7 +402,7 @@ static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 79 unmodified lines
333402 case PIN_CONFIG_OUTPUT:
334403 if (bank->is_input)
335404 return -EINVAL;
336− sgpio_output_set(priv, &addr, arg);
405+ err = sgpio_output_set(priv, &addr, arg);
337406 break;
338407
339408 default:
@@ -473,9 +542,7 @@ static int microchip_sgpio_direction_output(struct gpio_chip *gc, · 133 unmodified lines
473542
474543 sgpio_pin_to_addr(priv, gpio, &addr);
475544
476− sgpio_output_set(priv, &addr, value);
477−
478− return 0;
545+ return sgpio_output_set(priv, &addr, value);
479546 }
480547
481548 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
@@ -575,10 +642,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, · 93 unmodified lines
575642 struct sgpio_bank *bank = gpiochip_get_data(chip);
576643 unsigned int gpio = irqd_to_hwirq(data);
577644 struct sgpio_port_addr addr;
645+ unsigned long flags;
578646 u32 ena;
579647
580648 sgpio_pin_to_addr(bank->priv, gpio, &addr);
581649
650+ spin_lock_irqsave(&bank->priv->lock, flags);
651+
582652 /* Disable interrupt while changing type */
583653 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
584654 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
@@ -595,6 +665,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, · 10 unmodified lines
595665
596666 /* Possibly re-enable interrupts */
597667 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
668+
669+ spin_unlock_irqrestore(&bank->priv->lock, flags);
598670 }
599671
600672 static void microchip_sgpio_irq_setreg(struct irq_data *data,
@@ -626,7 +698,14 @@ static void microchip_sgpio_irq_unmask(struct irq_data *data) · 25 unmodified lines
626698
627699 static void microchip_sgpio_irq_ack(struct irq_data *data)
628700 {
629− microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
701+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
702+ struct sgpio_bank *bank = gpiochip_get_data(chip);
703+ unsigned int gpio = irqd_to_hwirq(data);
704+ struct sgpio_port_addr addr;
705+
706+ sgpio_pin_to_addr(bank->priv, gpio, &addr);
707+
708+ sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
630709 }
631710
632711 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
@@ -774,6 +853,7 @@ static int microchip_sgpio_register_bank(struct device *dev, · 141 unmodified lines
774853 gc->of_gpio_n_cells = 3;
775854 gc->base = -1;
776855 gc->ngpio = ngpios;
856+ gc->can_sleep = !bank->is_input;
777857
778858 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
779859 int irq = fwnode_irq_get(fwnode, 0);
@@ -833,6 +913,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev) · 53 unmodified lines
833913 return -ENOMEM;
834914
835915 priv->dev = dev;
916+ spin_lock_init(&priv->lock);
917+ mutex_init(&priv->poll_lock);
836918
837919 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
838920 if (IS_ERR(reset))
drivers/pinctrl/pinctrl-ocelot.c+106−3
@@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { · 694 unmodified lines
695695 JAGUAR2_PIN(63),
696696 };
697697
698+#define SERVALT_P(p, f0, f1, f2) \
699+static struct ocelot_pin_caps servalt_pin_##p = { \
700+ .pin = p, \
701+ .functions = { \
702+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
703+ }, \
704+}
705+
706+SERVALT_P(0, SG0, NONE, NONE);
707+SERVALT_P(1, SG0, NONE, NONE);
708+SERVALT_P(2, SG0, NONE, NONE);
709+SERVALT_P(3, SG0, NONE, NONE);
710+SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
711+SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
712+SERVALT_P(6, UART, NONE, NONE);
713+SERVALT_P(7, UART, NONE, NONE);
714+SERVALT_P(8, SI, SFP, TWI_SCL_M);
715+SERVALT_P(9, PCI_WAKE, SFP, SI);
716+SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
717+SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
718+SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
719+SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
720+SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
721+SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
722+SERVALT_P(16, TACHO, SFP, SI);
723+SERVALT_P(17, PWM, NONE, TWI_SCL_M);
724+SERVALT_P(18, PTP2, SFP, SI);
725+SERVALT_P(19, PTP3, SFP, SI);
726+SERVALT_P(20, UART2, SFP, SI);
727+SERVALT_P(21, UART2, NONE, NONE);
728+SERVALT_P(22, MIIM, SFP, TWI2);
729+SERVALT_P(23, MIIM, SFP, TWI2);
730+SERVALT_P(24, TWI, NONE, NONE);
731+SERVALT_P(25, TWI, SFP, TWI_SCL_M);
732+SERVALT_P(26, TWI_SCL_M, SFP, SI);
733+SERVALT_P(27, TWI_SCL_M, SFP, SI);
734+SERVALT_P(28, TWI_SCL_M, SFP, SI);
735+SERVALT_P(29, TWI_SCL_M, NONE, NONE);
736+SERVALT_P(30, TWI_SCL_M, NONE, NONE);
737+SERVALT_P(31, TWI_SCL_M, NONE, NONE);
738+SERVALT_P(32, TWI_SCL_M, NONE, NONE);
739+SERVALT_P(33, RCVRD_CLK, NONE, NONE);
740+SERVALT_P(34, RCVRD_CLK, NONE, NONE);
741+SERVALT_P(35, RCVRD_CLK, NONE, NONE);
742+SERVALT_P(36, RCVRD_CLK, NONE, NONE);
743+
744+#define SERVALT_PIN(n) { \
745+ .number = n, \
746+ .name = "GPIO_"#n, \
747+ .drv_data = &servalt_pin_##n \
748+}
749+
750+static const struct pinctrl_pin_desc servalt_pins[] = {
751+ SERVALT_PIN(0),
752+ SERVALT_PIN(1),
753+ SERVALT_PIN(2),
754+ SERVALT_PIN(3),
755+ SERVALT_PIN(4),
756+ SERVALT_PIN(5),
757+ SERVALT_PIN(6),
758+ SERVALT_PIN(7),
759+ SERVALT_PIN(8),
760+ SERVALT_PIN(9),
761+ SERVALT_PIN(10),
762+ SERVALT_PIN(11),
763+ SERVALT_PIN(12),
764+ SERVALT_PIN(13),
765+ SERVALT_PIN(14),
766+ SERVALT_PIN(15),
767+ SERVALT_PIN(16),
768+ SERVALT_PIN(17),
769+ SERVALT_PIN(18),
770+ SERVALT_PIN(19),
771+ SERVALT_PIN(20),
772+ SERVALT_PIN(21),
773+ SERVALT_PIN(22),
774+ SERVALT_PIN(23),
775+ SERVALT_PIN(24),
776+ SERVALT_PIN(25),
777+ SERVALT_PIN(26),
778+ SERVALT_PIN(27),
779+ SERVALT_PIN(28),
780+ SERVALT_PIN(29),
781+ SERVALT_PIN(30),
782+ SERVALT_PIN(31),
783+ SERVALT_PIN(32),
784+ SERVALT_PIN(33),
785+ SERVALT_PIN(34),
786+ SERVALT_PIN(35),
787+ SERVALT_PIN(36),
788+};
789+
698790 #define SPARX5_P(p, f0, f1, f2) \
699791 static struct ocelot_pin_caps sparx5_pin_##p = { \
700792 .pin = p, \
@@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { · 796 unmodified lines
14971589 .owner = THIS_MODULE,
14981590 };
14991591
1592+static struct pinctrl_desc servalt_desc = {
1593+ .name = "servalt-pinctrl",
1594+ .pins = servalt_pins,
1595+ .npins = ARRAY_SIZE(servalt_pins),
1596+ .pctlops = &ocelot_pctl_ops,
1597+ .pmxops = &ocelot_pmx_ops,
1598+ .owner = THIS_MODULE,
1599+};
1600+
15001601 static struct pinctrl_desc sparx5_desc = {
15011602 .name = "sparx5-pinctrl",
15021603 .pins = sparx5_pins,
@@ -1750,8 +1851,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, · 247 unmodified lines
17501851 gc->base = -1;
17511852 gc->label = "ocelot-gpio";
17521853
1753− irq = irq_of_parse_and_map(gc->of_node, 0);
1754− if (irq) {
1854+ irq = platform_get_irq_optional(pdev, 0);
1855+ if (irq > 0) {
17551856 girq = &gc->irq;
17561857 girq->chip = &ocelot_irqchip;
17571858 girq->parent_handler = ocelot_irq_handler;
@@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { · 16 unmodified lines
17741875 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
17751876 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
17761877 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1878+ { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
17771879 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
17781880 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
17791881 {},
@@ -1788,9 +1890,10 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) · 8 unmodified lines
17881890 .val_bits = 32,
17891891 .reg_stride = 4,
17901892 .max_register = 32,
1893+ .name = "pincfg",
17911894 };
17921895
1793− base = devm_platform_ioremap_resource(pdev, 0);
1896+ base = devm_platform_ioremap_resource(pdev, 1);
17941897 if (IS_ERR(base)) {
17951898 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
17961899 return NULL;
drivers/pinctrl/pinctrl-rockchip.c+2−0
@@ -2693,6 +2693,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) · 2692 unmodified lines
26932693 node = of_parse_phandle(np, "rockchip,grf", 0);
26942694 if (node) {
26952695 info->regmap_base = syscon_node_to_regmap(node);
2696+ of_node_put(node);
26962697 if (IS_ERR(info->regmap_base))
26972698 return PTR_ERR(info->regmap_base);
26982699 } else {
@@ -2725,6 +2726,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) · 26 unmodified lines
27252726 node = of_parse_phandle(np, "rockchip,pmu", 0);
27262727 if (node) {
27272728 info->regmap_pmu = syscon_node_to_regmap(node);
2729+ of_node_put(node);
27282730 if (IS_ERR(info->regmap_pmu))
27292731 return PTR_ERR(info->regmap_pmu);
27302732 }
drivers/pinctrl/pinctrl-starfive.c+1−1
@@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, · 1025 unmodified lines
10261026 break;
10271027 default:
10281028 return -ENOTSUPP;
1029− };
1029+ }
10301030
10311031 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
10321032 return 0;
drivers/pinctrl/pinctrl-zynq.c+2−5
@@ -8,6 +8,7 @@ · 7 unmodified lines
88 */
99 #include <linux/io.h>
1010 #include <linux/mfd/syscon.h>
11+#include <linux/module.h>
1112 #include <linux/init.h>
1213 #include <linux/of.h>
1314 #include <linux/platform_device.h>
@@ -1210,8 +1211,4 @@ static struct platform_driver zynq_pinctrl_driver = { · 1196 unmodified lines
12101211 .probe = zynq_pinctrl_probe,
12111212 };
12121213
1213−static int __init zynq_pinctrl_init(void)
1214−{
1215− return platform_driver_register(&zynq_pinctrl_driver);
1216−}
1217−arch_initcall(zynq_pinctrl_init);
1214+module_platform_driver(zynq_pinctrl_driver);
drivers/pinctrl/pxa/pinctrl-pxa27x.c+2−3
@@ -504,7 +504,7 @@ static const struct pxa_desc_pin pxa27x_pins[] = { · 503 unmodified lines
504504
505505 static int pxa27x_pinctrl_probe(struct platform_device *pdev)
506506 {
507− int ret, i;
507+ int i;
508508 void __iomem *base_af[8];
509509 void __iomem *base_dir[4];
510510 void __iomem *base_sleep[4];
@@ -532,9 +532,8 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev) · 21 unmodified lines
532532 for (i = 0; i < ARRAY_SIZE(base_sleep); i++)
533533 base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i;
534534
535− ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
535+ return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
536536 base_af, base_dir, base_sleep);
537− return ret;
538537 }
539538
540539 static const struct of_device_id pxa27x_pinctrl_match[] = {
drivers/pinctrl/qcom/Kconfig+9−0
@@ -248,6 +248,15 @@ config PINCTRL_SC8180X · 247 unmodified lines
248248 Qualcomm Technologies Inc TLMM block found on the Qualcomm
249249 Technologies Inc SC8180x platform.
250250
251+config PINCTRL_SC8280XP
252+ tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
253+ depends on OF
254+ depends on PINCTRL_MSM
255+ help
256+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
257+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
258+ Technologies Inc SC8280xp platform.
259+
251260 config PINCTRL_SDM660
252261 tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
253262 depends on OF
drivers/pinctrl/qcom/Makefile+1−0
@@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o · 28 unmodified lines
2929 obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
3030 obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
3131 obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
32+obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
3233 obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
3334 obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
3435 obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
drivers/pinctrl/qcom/pinctrl-msm.c+11−2
@@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, · 614 unmodified lines
615615 int drive;
616616 int pull;
617617 int val;
618+ int egpio_enable;
618619 u32 ctl_reg, io_reg;
619620
620621 static const char * const pulls_keeper[] = {
@@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, · 20 unmodified lines
641642 func = (ctl_reg >> g->mux_bit) & 7;
642643 drive = (ctl_reg >> g->drv_bit) & 7;
643644 pull = (ctl_reg >> g->pull_bit) & 3;
645+ egpio_enable = 0;
646+ if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
647+ egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
644648
645649 if (is_out)
646650 val = !!(io_reg & BIT(g->out_bit));
647651 else
648652 val = !!(io_reg & BIT(g->in_bit));
649653
654+ if (egpio_enable) {
655+ seq_printf(s, " %-8s: egpio\n", g->name);
656+ return;
657+ }
658+
650659 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
651660 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
652661 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
@@ -1168,7 +1177,7 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, · 515 unmodified lines
11681177 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
11691178 return irq_chip_set_affinity_parent(d, dest, force);
11701179
1171− return 0;
1180+ return -EINVAL;
11721181 }
11731182
11741183 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
@@ -1179,7 +1188,7 @@ static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) · 4 unmodified lines
11791188 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
11801189 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
11811190
1182− return 0;
1191+ return -EINVAL;
11831192 }
11841193
11851194 static void msm_gpio_irq_handler(struct irq_desc *desc)
drivers/pinctrl/qcom/pinctrl-qcm2290.c+12−0
@@ -1083,6 +1083,16 @@ static const struct msm_pingroup qcm2290_groups[] = { · 1082 unmodified lines
10831083 [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
10841084 };
10851085
1086+static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = {
1087+ { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },
1088+ { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 },
1089+ { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 },
1090+ { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 },
1091+ { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 },
1092+ { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
1093+ { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
1094+};
1095+
10861096 static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
10871097 .pins = qcm2290_pins,
10881098 .npins = ARRAY_SIZE(qcm2290_pins),
@@ -1091,6 +1101,8 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { · 2 unmodified lines
10911101 .groups = qcm2290_groups,
10921102 .ngroups = ARRAY_SIZE(qcm2290_groups),
10931103 .ngpios = 127,
1104+ .wakeirq_map = qcm2290_mpm_map,
1105+ .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
10941106 };
10951107
10961108 static int qcm2290_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/qcom/pinctrl-sc8180x.c+2−2
@@ -1622,8 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { · 1621 unmodified lines
16221622 };
16231623
16241624 /*
1625− * ACPI DSDT has one single memory resource for TLMM, which voilates the
1626− * hardware layout of 3 sepearte tiles. Let's split the memory resource into
1625+ * ACPI DSDT has one single memory resource for TLMM, which violates the
1626+ * hardware layout of 3 separate tiles. Let's split the memory resource into
16271627 * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the
16281628 * same way as for DT probe.
16291629 */
drivers/pinctrl/qcom/pinctrl-sc8280xp.c+1953−0
@@ -0,0 +1,1953 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4+ * Copyright (c) 2022, Linaro Ltd.
5+ */
6+
7+#include <linux/module.h>
8+#include <linux/of.h>
9+#include <linux/platform_device.h>
10+#include <linux/pinctrl/pinctrl.h>
11+
12+#include "pinctrl-msm.h"
13+
14+#define FUNCTION(fname) \
15+ [msm_mux_##fname] = { \
16+ .name = #fname, \
17+ .groups = fname##_groups, \
18+ .ngroups = ARRAY_SIZE(fname##_groups), \
19+ }
20+
21+#define REG_SIZE 0x1000
22+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
23+ { \
24+ .name = "gpio" #id, \
25+ .pins = gpio##id##_pins, \
26+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
27+ .funcs = (int[]){ \
28+ msm_mux_gpio, /* gpio mode */ \
29+ msm_mux_##f1, \
30+ msm_mux_##f2, \
31+ msm_mux_##f3, \
32+ msm_mux_##f4, \
33+ msm_mux_##f5, \
34+ msm_mux_##f6, \
35+ msm_mux_##f7, \
36+ }, \
37+ .nfuncs = 8, \
38+ .ctl_reg = REG_SIZE * id, \
39+ .io_reg = 0x4 + REG_SIZE * id, \
40+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
41+ .intr_status_reg = 0xc + REG_SIZE * id, \
42+ .intr_target_reg = 0x8 + REG_SIZE * id, \
43+ .mux_bit = 2, \
44+ .pull_bit = 0, \
45+ .drv_bit = 6, \
46+ .oe_bit = 9, \
47+ .in_bit = 0, \
48+ .out_bit = 1, \
49+ .egpio_enable = 12, \
50+ .egpio_present = 11, \
51+ .intr_enable_bit = 0, \
52+ .intr_status_bit = 0, \
53+ .intr_target_bit = 5, \
54+ .intr_target_kpss_val = 3, \
55+ .intr_raw_status_bit = 4, \
56+ .intr_polarity_bit = 1, \
57+ .intr_detection_bit = 2, \
58+ .intr_detection_width = 2, \
59+ }
60+
61+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
62+ { \
63+ .name = #pg_name, \
64+ .pins = pg_name##_pins, \
65+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
66+ .ctl_reg = ctl, \
67+ .io_reg = 0, \
68+ .intr_cfg_reg = 0, \
69+ .intr_status_reg = 0, \
70+ .intr_target_reg = 0, \
71+ .mux_bit = -1, \
72+ .pull_bit = pull, \
73+ .drv_bit = drv, \
74+ .oe_bit = -1, \
75+ .in_bit = -1, \
76+ .out_bit = -1, \
77+ .intr_enable_bit = -1, \
78+ .intr_status_bit = -1, \
79+ .intr_target_bit = -1, \
80+ .intr_raw_status_bit = -1, \
81+ .intr_polarity_bit = -1, \
82+ .intr_detection_bit = -1, \
83+ .intr_detection_width = -1, \
84+ }
85+
86+#define UFS_RESET(pg_name, offset) \
87+ { \
88+ .name = #pg_name, \
89+ .pins = pg_name##_pins, \
90+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
91+ .ctl_reg = offset, \
92+ .io_reg = offset + 0x4, \
93+ .intr_cfg_reg = 0, \
94+ .intr_status_reg = 0, \
95+ .intr_target_reg = 0, \
96+ .mux_bit = -1, \
97+ .pull_bit = 3, \
98+ .drv_bit = 0, \
99+ .oe_bit = -1, \
100+ .in_bit = -1, \
101+ .out_bit = 0, \
102+ .intr_enable_bit = -1, \
103+ .intr_status_bit = -1, \
104+ .intr_target_bit = -1, \
105+ .intr_raw_status_bit = -1, \
106+ .intr_polarity_bit = -1, \
107+ .intr_detection_bit = -1, \
108+ .intr_detection_width = -1, \
109+ }
110+static const struct pinctrl_pin_desc sc8280xp_pins[] = {
111+ PINCTRL_PIN(0, "GPIO_0"),
112+ PINCTRL_PIN(1, "GPIO_1"),
113+ PINCTRL_PIN(2, "GPIO_2"),
114+ PINCTRL_PIN(3, "GPIO_3"),
115+ PINCTRL_PIN(4, "GPIO_4"),
116+ PINCTRL_PIN(5, "GPIO_5"),
117+ PINCTRL_PIN(6, "GPIO_6"),
118+ PINCTRL_PIN(7, "GPIO_7"),
119+ PINCTRL_PIN(8, "GPIO_8"),
120+ PINCTRL_PIN(9, "GPIO_9"),
121+ PINCTRL_PIN(10, "GPIO_10"),
122+ PINCTRL_PIN(11, "GPIO_11"),
123+ PINCTRL_PIN(12, "GPIO_12"),
124+ PINCTRL_PIN(13, "GPIO_13"),
125+ PINCTRL_PIN(14, "GPIO_14"),
126+ PINCTRL_PIN(15, "GPIO_15"),
127+ PINCTRL_PIN(16, "GPIO_16"),
128+ PINCTRL_PIN(17, "GPIO_17"),
129+ PINCTRL_PIN(18, "GPIO_18"),
130+ PINCTRL_PIN(19, "GPIO_19"),
131+ PINCTRL_PIN(20, "GPIO_20"),
132+ PINCTRL_PIN(21, "GPIO_21"),
133+ PINCTRL_PIN(22, "GPIO_22"),
134+ PINCTRL_PIN(23, "GPIO_23"),
135+ PINCTRL_PIN(24, "GPIO_24"),
136+ PINCTRL_PIN(25, "GPIO_25"),
137+ PINCTRL_PIN(26, "GPIO_26"),
138+ PINCTRL_PIN(27, "GPIO_27"),
139+ PINCTRL_PIN(28, "GPIO_28"),
140+ PINCTRL_PIN(29, "GPIO_29"),
141+ PINCTRL_PIN(30, "GPIO_30"),
142+ PINCTRL_PIN(31, "GPIO_31"),
143+ PINCTRL_PIN(32, "GPIO_32"),
144+ PINCTRL_PIN(33, "GPIO_33"),
145+ PINCTRL_PIN(34, "GPIO_34"),
146+ PINCTRL_PIN(35, "GPIO_35"),
147+ PINCTRL_PIN(36, "GPIO_36"),
148+ PINCTRL_PIN(37, "GPIO_37"),
149+ PINCTRL_PIN(38, "GPIO_38"),
150+ PINCTRL_PIN(39, "GPIO_39"),
151+ PINCTRL_PIN(40, "GPIO_40"),
152+ PINCTRL_PIN(41, "GPIO_41"),
153+ PINCTRL_PIN(42, "GPIO_42"),
154+ PINCTRL_PIN(43, "GPIO_43"),
155+ PINCTRL_PIN(44, "GPIO_44"),
156+ PINCTRL_PIN(45, "GPIO_45"),
157+ PINCTRL_PIN(46, "GPIO_46"),
158+ PINCTRL_PIN(47, "GPIO_47"),
159+ PINCTRL_PIN(48, "GPIO_48"),
160+ PINCTRL_PIN(49, "GPIO_49"),
161+ PINCTRL_PIN(50, "GPIO_50"),
162+ PINCTRL_PIN(51, "GPIO_51"),
163+ PINCTRL_PIN(52, "GPIO_52"),
164+ PINCTRL_PIN(53, "GPIO_53"),
165+ PINCTRL_PIN(54, "GPIO_54"),
166+ PINCTRL_PIN(55, "GPIO_55"),
167+ PINCTRL_PIN(56, "GPIO_56"),
168+ PINCTRL_PIN(57, "GPIO_57"),
169+ PINCTRL_PIN(58, "GPIO_58"),
170+ PINCTRL_PIN(59, "GPIO_59"),
171+ PINCTRL_PIN(60, "GPIO_60"),
172+ PINCTRL_PIN(61, "GPIO_61"),
173+ PINCTRL_PIN(62, "GPIO_62"),
174+ PINCTRL_PIN(63, "GPIO_63"),
175+ PINCTRL_PIN(64, "GPIO_64"),
176+ PINCTRL_PIN(65, "GPIO_65"),
177+ PINCTRL_PIN(66, "GPIO_66"),
178+ PINCTRL_PIN(67, "GPIO_67"),
179+ PINCTRL_PIN(68, "GPIO_68"),
180+ PINCTRL_PIN(69, "GPIO_69"),
181+ PINCTRL_PIN(70, "GPIO_70"),
182+ PINCTRL_PIN(71, "GPIO_71"),
183+ PINCTRL_PIN(72, "GPIO_72"),
184+ PINCTRL_PIN(73, "GPIO_73"),
185+ PINCTRL_PIN(74, "GPIO_74"),
186+ PINCTRL_PIN(75, "GPIO_75"),
187+ PINCTRL_PIN(76, "GPIO_76"),
188+ PINCTRL_PIN(77, "GPIO_77"),
189+ PINCTRL_PIN(78, "GPIO_78"),
190+ PINCTRL_PIN(79, "GPIO_79"),
191+ PINCTRL_PIN(80, "GPIO_80"),
192+ PINCTRL_PIN(81, "GPIO_81"),
193+ PINCTRL_PIN(82, "GPIO_82"),
194+ PINCTRL_PIN(83, "GPIO_83"),
195+ PINCTRL_PIN(84, "GPIO_84"),
196+ PINCTRL_PIN(85, "GPIO_85"),
197+ PINCTRL_PIN(86, "GPIO_86"),
198+ PINCTRL_PIN(87, "GPIO_87"),
199+ PINCTRL_PIN(88, "GPIO_88"),
200+ PINCTRL_PIN(89, "GPIO_89"),
201+ PINCTRL_PIN(90, "GPIO_90"),
202+ PINCTRL_PIN(91, "GPIO_91"),
203+ PINCTRL_PIN(92, "GPIO_92"),
204+ PINCTRL_PIN(93, "GPIO_93"),
205+ PINCTRL_PIN(94, "GPIO_94"),
206+ PINCTRL_PIN(95, "GPIO_95"),
207+ PINCTRL_PIN(96, "GPIO_96"),
208+ PINCTRL_PIN(97, "GPIO_97"),
209+ PINCTRL_PIN(98, "GPIO_98"),
210+ PINCTRL_PIN(99, "GPIO_99"),
211+ PINCTRL_PIN(100, "GPIO_100"),
212+ PINCTRL_PIN(101, "GPIO_101"),
213+ PINCTRL_PIN(102, "GPIO_102"),
214+ PINCTRL_PIN(103, "GPIO_103"),
215+ PINCTRL_PIN(104, "GPIO_104"),
216+ PINCTRL_PIN(105, "GPIO_105"),
217+ PINCTRL_PIN(106, "GPIO_106"),
218+ PINCTRL_PIN(107, "GPIO_107"),
219+ PINCTRL_PIN(108, "GPIO_108"),
220+ PINCTRL_PIN(109, "GPIO_109"),
221+ PINCTRL_PIN(110, "GPIO_110"),
222+ PINCTRL_PIN(111, "GPIO_111"),
223+ PINCTRL_PIN(112, "GPIO_112"),
224+ PINCTRL_PIN(113, "GPIO_113"),
225+ PINCTRL_PIN(114, "GPIO_114"),
226+ PINCTRL_PIN(115, "GPIO_115"),
227+ PINCTRL_PIN(116, "GPIO_116"),
228+ PINCTRL_PIN(117, "GPIO_117"),
229+ PINCTRL_PIN(118, "GPIO_118"),
230+ PINCTRL_PIN(119, "GPIO_119"),
231+ PINCTRL_PIN(120, "GPIO_120"),
232+ PINCTRL_PIN(121, "GPIO_121"),
233+ PINCTRL_PIN(122, "GPIO_122"),
234+ PINCTRL_PIN(123, "GPIO_123"),
235+ PINCTRL_PIN(124, "GPIO_124"),
236+ PINCTRL_PIN(125, "GPIO_125"),
237+ PINCTRL_PIN(126, "GPIO_126"),
238+ PINCTRL_PIN(127, "GPIO_127"),
239+ PINCTRL_PIN(128, "GPIO_128"),
240+ PINCTRL_PIN(129, "GPIO_129"),
241+ PINCTRL_PIN(130, "GPIO_130"),
242+ PINCTRL_PIN(131, "GPIO_131"),
243+ PINCTRL_PIN(132, "GPIO_132"),
244+ PINCTRL_PIN(133, "GPIO_133"),
245+ PINCTRL_PIN(134, "GPIO_134"),
246+ PINCTRL_PIN(135, "GPIO_135"),
247+ PINCTRL_PIN(136, "GPIO_136"),
248+ PINCTRL_PIN(137, "GPIO_137"),
249+ PINCTRL_PIN(138, "GPIO_138"),
250+ PINCTRL_PIN(139, "GPIO_139"),
251+ PINCTRL_PIN(140, "GPIO_140"),
252+ PINCTRL_PIN(141, "GPIO_141"),
253+ PINCTRL_PIN(142, "GPIO_142"),
254+ PINCTRL_PIN(143, "GPIO_143"),
255+ PINCTRL_PIN(144, "GPIO_144"),
256+ PINCTRL_PIN(145, "GPIO_145"),
257+ PINCTRL_PIN(146, "GPIO_146"),
258+ PINCTRL_PIN(147, "GPIO_147"),
259+ PINCTRL_PIN(148, "GPIO_148"),
260+ PINCTRL_PIN(149, "GPIO_149"),
261+ PINCTRL_PIN(150, "GPIO_150"),
262+ PINCTRL_PIN(151, "GPIO_151"),
263+ PINCTRL_PIN(152, "GPIO_152"),
264+ PINCTRL_PIN(153, "GPIO_153"),
265+ PINCTRL_PIN(154, "GPIO_154"),
266+ PINCTRL_PIN(155, "GPIO_155"),
267+ PINCTRL_PIN(156, "GPIO_156"),
268+ PINCTRL_PIN(157, "GPIO_157"),
269+ PINCTRL_PIN(158, "GPIO_158"),
270+ PINCTRL_PIN(159, "GPIO_159"),
271+ PINCTRL_PIN(160, "GPIO_160"),
272+ PINCTRL_PIN(161, "GPIO_161"),
273+ PINCTRL_PIN(162, "GPIO_162"),
274+ PINCTRL_PIN(163, "GPIO_163"),
275+ PINCTRL_PIN(164, "GPIO_164"),
276+ PINCTRL_PIN(165, "GPIO_165"),
277+ PINCTRL_PIN(166, "GPIO_166"),
278+ PINCTRL_PIN(167, "GPIO_167"),
279+ PINCTRL_PIN(168, "GPIO_168"),
280+ PINCTRL_PIN(169, "GPIO_169"),
281+ PINCTRL_PIN(170, "GPIO_170"),
282+ PINCTRL_PIN(171, "GPIO_171"),
283+ PINCTRL_PIN(172, "GPIO_172"),
284+ PINCTRL_PIN(173, "GPIO_173"),
285+ PINCTRL_PIN(174, "GPIO_174"),
286+ PINCTRL_PIN(175, "GPIO_175"),
287+ PINCTRL_PIN(176, "GPIO_176"),
288+ PINCTRL_PIN(177, "GPIO_177"),
289+ PINCTRL_PIN(178, "GPIO_178"),
290+ PINCTRL_PIN(179, "GPIO_179"),
291+ PINCTRL_PIN(180, "GPIO_180"),
292+ PINCTRL_PIN(181, "GPIO_181"),
293+ PINCTRL_PIN(182, "GPIO_182"),
294+ PINCTRL_PIN(183, "GPIO_183"),
295+ PINCTRL_PIN(184, "GPIO_184"),
296+ PINCTRL_PIN(185, "GPIO_185"),
297+ PINCTRL_PIN(186, "GPIO_186"),
298+ PINCTRL_PIN(187, "GPIO_187"),
299+ PINCTRL_PIN(188, "GPIO_188"),
300+ PINCTRL_PIN(189, "GPIO_189"),
301+ PINCTRL_PIN(190, "GPIO_190"),
302+ PINCTRL_PIN(191, "GPIO_191"),
303+ PINCTRL_PIN(192, "GPIO_192"),
304+ PINCTRL_PIN(193, "GPIO_193"),
305+ PINCTRL_PIN(194, "GPIO_194"),
306+ PINCTRL_PIN(195, "GPIO_195"),
307+ PINCTRL_PIN(196, "GPIO_196"),
308+ PINCTRL_PIN(197, "GPIO_197"),
309+ PINCTRL_PIN(198, "GPIO_198"),
310+ PINCTRL_PIN(199, "GPIO_199"),
311+ PINCTRL_PIN(200, "GPIO_200"),
312+ PINCTRL_PIN(201, "GPIO_201"),
313+ PINCTRL_PIN(202, "GPIO_202"),
314+ PINCTRL_PIN(203, "GPIO_203"),
315+ PINCTRL_PIN(204, "GPIO_204"),
316+ PINCTRL_PIN(205, "GPIO_205"),
317+ PINCTRL_PIN(206, "GPIO_206"),
318+ PINCTRL_PIN(207, "GPIO_207"),
319+ PINCTRL_PIN(208, "GPIO_208"),
320+ PINCTRL_PIN(209, "GPIO_209"),
321+ PINCTRL_PIN(210, "GPIO_210"),
322+ PINCTRL_PIN(211, "GPIO_211"),
323+ PINCTRL_PIN(212, "GPIO_212"),
324+ PINCTRL_PIN(213, "GPIO_213"),
325+ PINCTRL_PIN(214, "GPIO_214"),
326+ PINCTRL_PIN(215, "GPIO_215"),
327+ PINCTRL_PIN(216, "GPIO_216"),
328+ PINCTRL_PIN(217, "GPIO_217"),
329+ PINCTRL_PIN(218, "GPIO_218"),
330+ PINCTRL_PIN(219, "GPIO_219"),
331+ PINCTRL_PIN(220, "GPIO_220"),
332+ PINCTRL_PIN(221, "GPIO_221"),
333+ PINCTRL_PIN(222, "GPIO_222"),
334+ PINCTRL_PIN(223, "GPIO_223"),
335+ PINCTRL_PIN(224, "GPIO_224"),
336+ PINCTRL_PIN(225, "GPIO_225"),
337+ PINCTRL_PIN(226, "GPIO_226"),
338+ PINCTRL_PIN(227, "GPIO_227"),
339+ PINCTRL_PIN(228, "UFS_RESET"),
340+ PINCTRL_PIN(229, "UFS1_RESET"),
341+ PINCTRL_PIN(230, "SDC2_CLK"),
342+ PINCTRL_PIN(231, "SDC2_CMD"),
343+ PINCTRL_PIN(232, "SDC2_DATA"),
344+};
345+
346+#define DECLARE_MSM_GPIO_PINS(pin) \
347+ static const unsigned int gpio##pin##_pins[] = { pin }
348+DECLARE_MSM_GPIO_PINS(0);
349+DECLARE_MSM_GPIO_PINS(1);
350+DECLARE_MSM_GPIO_PINS(2);
351+DECLARE_MSM_GPIO_PINS(3);
352+DECLARE_MSM_GPIO_PINS(4);
353+DECLARE_MSM_GPIO_PINS(5);
354+DECLARE_MSM_GPIO_PINS(6);
355+DECLARE_MSM_GPIO_PINS(7);
356+DECLARE_MSM_GPIO_PINS(8);
357+DECLARE_MSM_GPIO_PINS(9);
358+DECLARE_MSM_GPIO_PINS(10);
359+DECLARE_MSM_GPIO_PINS(11);
360+DECLARE_MSM_GPIO_PINS(12);
361+DECLARE_MSM_GPIO_PINS(13);
362+DECLARE_MSM_GPIO_PINS(14);
363+DECLARE_MSM_GPIO_PINS(15);
364+DECLARE_MSM_GPIO_PINS(16);
365+DECLARE_MSM_GPIO_PINS(17);
366+DECLARE_MSM_GPIO_PINS(18);
367+DECLARE_MSM_GPIO_PINS(19);
368+DECLARE_MSM_GPIO_PINS(20);
369+DECLARE_MSM_GPIO_PINS(21);
370+DECLARE_MSM_GPIO_PINS(22);
371+DECLARE_MSM_GPIO_PINS(23);
372+DECLARE_MSM_GPIO_PINS(24);
373+DECLARE_MSM_GPIO_PINS(25);
374+DECLARE_MSM_GPIO_PINS(26);
375+DECLARE_MSM_GPIO_PINS(27);
376+DECLARE_MSM_GPIO_PINS(28);
377+DECLARE_MSM_GPIO_PINS(29);
378+DECLARE_MSM_GPIO_PINS(30);
379+DECLARE_MSM_GPIO_PINS(31);
380+DECLARE_MSM_GPIO_PINS(32);
381+DECLARE_MSM_GPIO_PINS(33);
382+DECLARE_MSM_GPIO_PINS(34);
383+DECLARE_MSM_GPIO_PINS(35);
384+DECLARE_MSM_GPIO_PINS(36);
385+DECLARE_MSM_GPIO_PINS(37);
386+DECLARE_MSM_GPIO_PINS(38);
387+DECLARE_MSM_GPIO_PINS(39);
388+DECLARE_MSM_GPIO_PINS(40);
389+DECLARE_MSM_GPIO_PINS(41);
390+DECLARE_MSM_GPIO_PINS(42);
391+DECLARE_MSM_GPIO_PINS(43);
392+DECLARE_MSM_GPIO_PINS(44);
393+DECLARE_MSM_GPIO_PINS(45);
394+DECLARE_MSM_GPIO_PINS(46);
395+DECLARE_MSM_GPIO_PINS(47);
396+DECLARE_MSM_GPIO_PINS(48);
397+DECLARE_MSM_GPIO_PINS(49);
398+DECLARE_MSM_GPIO_PINS(50);
399+DECLARE_MSM_GPIO_PINS(51);
400+DECLARE_MSM_GPIO_PINS(52);
401+DECLARE_MSM_GPIO_PINS(53);
402+DECLARE_MSM_GPIO_PINS(54);
403+DECLARE_MSM_GPIO_PINS(55);
404+DECLARE_MSM_GPIO_PINS(56);
405+DECLARE_MSM_GPIO_PINS(57);
406+DECLARE_MSM_GPIO_PINS(58);
407+DECLARE_MSM_GPIO_PINS(59);
408+DECLARE_MSM_GPIO_PINS(60);
409+DECLARE_MSM_GPIO_PINS(61);
410+DECLARE_MSM_GPIO_PINS(62);
411+DECLARE_MSM_GPIO_PINS(63);
412+DECLARE_MSM_GPIO_PINS(64);
413+DECLARE_MSM_GPIO_PINS(65);
414+DECLARE_MSM_GPIO_PINS(66);
415+DECLARE_MSM_GPIO_PINS(67);
416+DECLARE_MSM_GPIO_PINS(68);
417+DECLARE_MSM_GPIO_PINS(69);
418+DECLARE_MSM_GPIO_PINS(70);
419+DECLARE_MSM_GPIO_PINS(71);
420+DECLARE_MSM_GPIO_PINS(72);
421+DECLARE_MSM_GPIO_PINS(73);
422+DECLARE_MSM_GPIO_PINS(74);
423+DECLARE_MSM_GPIO_PINS(75);
424+DECLARE_MSM_GPIO_PINS(76);
425+DECLARE_MSM_GPIO_PINS(77);
426+DECLARE_MSM_GPIO_PINS(78);
427+DECLARE_MSM_GPIO_PINS(79);
428+DECLARE_MSM_GPIO_PINS(80);
429+DECLARE_MSM_GPIO_PINS(81);
430+DECLARE_MSM_GPIO_PINS(82);
431+DECLARE_MSM_GPIO_PINS(83);
432+DECLARE_MSM_GPIO_PINS(84);
433+DECLARE_MSM_GPIO_PINS(85);
434+DECLARE_MSM_GPIO_PINS(86);
435+DECLARE_MSM_GPIO_PINS(87);
436+DECLARE_MSM_GPIO_PINS(88);
437+DECLARE_MSM_GPIO_PINS(89);
438+DECLARE_MSM_GPIO_PINS(90);
439+DECLARE_MSM_GPIO_PINS(91);
440+DECLARE_MSM_GPIO_PINS(92);
441+DECLARE_MSM_GPIO_PINS(93);
442+DECLARE_MSM_GPIO_PINS(94);
443+DECLARE_MSM_GPIO_PINS(95);
444+DECLARE_MSM_GPIO_PINS(96);
445+DECLARE_MSM_GPIO_PINS(97);
446+DECLARE_MSM_GPIO_PINS(98);
447+DECLARE_MSM_GPIO_PINS(99);
448+DECLARE_MSM_GPIO_PINS(100);
449+DECLARE_MSM_GPIO_PINS(101);
450+DECLARE_MSM_GPIO_PINS(102);
451+DECLARE_MSM_GPIO_PINS(103);
452+DECLARE_MSM_GPIO_PINS(104);
453+DECLARE_MSM_GPIO_PINS(105);
454+DECLARE_MSM_GPIO_PINS(106);
455+DECLARE_MSM_GPIO_PINS(107);
456+DECLARE_MSM_GPIO_PINS(108);
457+DECLARE_MSM_GPIO_PINS(109);
458+DECLARE_MSM_GPIO_PINS(110);
459+DECLARE_MSM_GPIO_PINS(111);
460+DECLARE_MSM_GPIO_PINS(112);
461+DECLARE_MSM_GPIO_PINS(113);
462+DECLARE_MSM_GPIO_PINS(114);
463+DECLARE_MSM_GPIO_PINS(115);
464+DECLARE_MSM_GPIO_PINS(116);
465+DECLARE_MSM_GPIO_PINS(117);
466+DECLARE_MSM_GPIO_PINS(118);
467+DECLARE_MSM_GPIO_PINS(119);
468+DECLARE_MSM_GPIO_PINS(120);
469+DECLARE_MSM_GPIO_PINS(121);
470+DECLARE_MSM_GPIO_PINS(122);
471+DECLARE_MSM_GPIO_PINS(123);
472+DECLARE_MSM_GPIO_PINS(124);
473+DECLARE_MSM_GPIO_PINS(125);
474+DECLARE_MSM_GPIO_PINS(126);
475+DECLARE_MSM_GPIO_PINS(127);
476+DECLARE_MSM_GPIO_PINS(128);
477+DECLARE_MSM_GPIO_PINS(129);
478+DECLARE_MSM_GPIO_PINS(130);
479+DECLARE_MSM_GPIO_PINS(131);
480+DECLARE_MSM_GPIO_PINS(132);
481+DECLARE_MSM_GPIO_PINS(133);
482+DECLARE_MSM_GPIO_PINS(134);
483+DECLARE_MSM_GPIO_PINS(135);
484+DECLARE_MSM_GPIO_PINS(136);
485+DECLARE_MSM_GPIO_PINS(137);
486+DECLARE_MSM_GPIO_PINS(138);
487+DECLARE_MSM_GPIO_PINS(139);
488+DECLARE_MSM_GPIO_PINS(140);
489+DECLARE_MSM_GPIO_PINS(141);
490+DECLARE_MSM_GPIO_PINS(142);
491+DECLARE_MSM_GPIO_PINS(143);
492+DECLARE_MSM_GPIO_PINS(144);
493+DECLARE_MSM_GPIO_PINS(145);
494+DECLARE_MSM_GPIO_PINS(146);
495+DECLARE_MSM_GPIO_PINS(147);
496+DECLARE_MSM_GPIO_PINS(148);
497+DECLARE_MSM_GPIO_PINS(149);
498+DECLARE_MSM_GPIO_PINS(150);
499+DECLARE_MSM_GPIO_PINS(151);
500+DECLARE_MSM_GPIO_PINS(152);
501+DECLARE_MSM_GPIO_PINS(153);
502+DECLARE_MSM_GPIO_PINS(154);
503+DECLARE_MSM_GPIO_PINS(155);
504+DECLARE_MSM_GPIO_PINS(156);
505+DECLARE_MSM_GPIO_PINS(157);
506+DECLARE_MSM_GPIO_PINS(158);
507+DECLARE_MSM_GPIO_PINS(159);
508+DECLARE_MSM_GPIO_PINS(160);
509+DECLARE_MSM_GPIO_PINS(161);
510+DECLARE_MSM_GPIO_PINS(162);
511+DECLARE_MSM_GPIO_PINS(163);
512+DECLARE_MSM_GPIO_PINS(164);
513+DECLARE_MSM_GPIO_PINS(165);
514+DECLARE_MSM_GPIO_PINS(166);
515+DECLARE_MSM_GPIO_PINS(167);
516+DECLARE_MSM_GPIO_PINS(168);
517+DECLARE_MSM_GPIO_PINS(169);
518+DECLARE_MSM_GPIO_PINS(170);
519+DECLARE_MSM_GPIO_PINS(171);
520+DECLARE_MSM_GPIO_PINS(172);
521+DECLARE_MSM_GPIO_PINS(173);
522+DECLARE_MSM_GPIO_PINS(174);
523+DECLARE_MSM_GPIO_PINS(175);
524+DECLARE_MSM_GPIO_PINS(176);
525+DECLARE_MSM_GPIO_PINS(177);
526+DECLARE_MSM_GPIO_PINS(178);
527+DECLARE_MSM_GPIO_PINS(179);
528+DECLARE_MSM_GPIO_PINS(180);
529+DECLARE_MSM_GPIO_PINS(181);
530+DECLARE_MSM_GPIO_PINS(182);
531+DECLARE_MSM_GPIO_PINS(183);
532+DECLARE_MSM_GPIO_PINS(184);
533+DECLARE_MSM_GPIO_PINS(185);
534+DECLARE_MSM_GPIO_PINS(186);
535+DECLARE_MSM_GPIO_PINS(187);
536+DECLARE_MSM_GPIO_PINS(188);
537+DECLARE_MSM_GPIO_PINS(189);
538+DECLARE_MSM_GPIO_PINS(190);
539+DECLARE_MSM_GPIO_PINS(191);
540+DECLARE_MSM_GPIO_PINS(192);
541+DECLARE_MSM_GPIO_PINS(193);
542+DECLARE_MSM_GPIO_PINS(194);
543+DECLARE_MSM_GPIO_PINS(195);
544+DECLARE_MSM_GPIO_PINS(196);
545+DECLARE_MSM_GPIO_PINS(197);
546+DECLARE_MSM_GPIO_PINS(198);
547+DECLARE_MSM_GPIO_PINS(199);
548+DECLARE_MSM_GPIO_PINS(200);
549+DECLARE_MSM_GPIO_PINS(201);
550+DECLARE_MSM_GPIO_PINS(202);
551+DECLARE_MSM_GPIO_PINS(203);
552+DECLARE_MSM_GPIO_PINS(204);
553+DECLARE_MSM_GPIO_PINS(205);
554+DECLARE_MSM_GPIO_PINS(206);
555+DECLARE_MSM_GPIO_PINS(207);
556+DECLARE_MSM_GPIO_PINS(208);
557+DECLARE_MSM_GPIO_PINS(209);
558+DECLARE_MSM_GPIO_PINS(210);
559+DECLARE_MSM_GPIO_PINS(211);
560+DECLARE_MSM_GPIO_PINS(212);
561+DECLARE_MSM_GPIO_PINS(213);
562+DECLARE_MSM_GPIO_PINS(214);
563+DECLARE_MSM_GPIO_PINS(215);
564+DECLARE_MSM_GPIO_PINS(216);
565+DECLARE_MSM_GPIO_PINS(217);
566+DECLARE_MSM_GPIO_PINS(218);
567+DECLARE_MSM_GPIO_PINS(219);
568+DECLARE_MSM_GPIO_PINS(220);
569+DECLARE_MSM_GPIO_PINS(221);
570+DECLARE_MSM_GPIO_PINS(222);
571+DECLARE_MSM_GPIO_PINS(223);
572+DECLARE_MSM_GPIO_PINS(224);
573+DECLARE_MSM_GPIO_PINS(225);
574+DECLARE_MSM_GPIO_PINS(226);
575+DECLARE_MSM_GPIO_PINS(227);
576+
577+static const unsigned int ufs_reset_pins[] = { 228 };
578+static const unsigned int ufs1_reset_pins[] = { 229 };
579+static const unsigned int sdc2_clk_pins[] = { 230 };
580+static const unsigned int sdc2_cmd_pins[] = { 231 };
581+static const unsigned int sdc2_data_pins[] = { 232 };
582+
583+enum sc8280xp_functions {
584+ msm_mux_atest_char,
585+ msm_mux_atest_usb,
586+ msm_mux_audio_ref,
587+ msm_mux_cam_mclk,
588+ msm_mux_cci_async,
589+ msm_mux_cci_i2c,
590+ msm_mux_cci_timer0,
591+ msm_mux_cci_timer1,
592+ msm_mux_cci_timer2,
593+ msm_mux_cci_timer3,
594+ msm_mux_cci_timer4,
595+ msm_mux_cci_timer5,
596+ msm_mux_cci_timer6,
597+ msm_mux_cci_timer7,
598+ msm_mux_cci_timer8,
599+ msm_mux_cci_timer9,
600+ msm_mux_cmu_rng,
601+ msm_mux_cri_trng,
602+ msm_mux_cri_trng0,
603+ msm_mux_cri_trng1,
604+ msm_mux_dbg_out,
605+ msm_mux_ddr_bist,
606+ msm_mux_ddr_pxi0,
607+ msm_mux_ddr_pxi1,
608+ msm_mux_ddr_pxi2,
609+ msm_mux_ddr_pxi3,
610+ msm_mux_ddr_pxi4,
611+ msm_mux_ddr_pxi5,
612+ msm_mux_ddr_pxi6,
613+ msm_mux_ddr_pxi7,
614+ msm_mux_dp2_hot,
615+ msm_mux_dp3_hot,
616+ msm_mux_edp0_lcd,
617+ msm_mux_edp1_lcd,
618+ msm_mux_edp2_lcd,
619+ msm_mux_edp3_lcd,
620+ msm_mux_edp_hot,
621+ msm_mux_egpio,
622+ msm_mux_emac0_dll,
623+ msm_mux_emac0_mcg0,
624+ msm_mux_emac0_mcg1,
625+ msm_mux_emac0_mcg2,
626+ msm_mux_emac0_mcg3,
627+ msm_mux_emac0_phy,
628+ msm_mux_emac0_ptp,
629+ msm_mux_emac1_dll0,
630+ msm_mux_emac1_dll1,
631+ msm_mux_emac1_mcg0,
632+ msm_mux_emac1_mcg1,
633+ msm_mux_emac1_mcg2,
634+ msm_mux_emac1_mcg3,
635+ msm_mux_emac1_phy,
636+ msm_mux_emac1_ptp,
637+ msm_mux_gcc_gp1,
638+ msm_mux_gcc_gp2,
639+ msm_mux_gcc_gp3,
640+ msm_mux_gcc_gp4,
641+ msm_mux_gcc_gp5,
642+ msm_mux_gpio,
643+ msm_mux_hs1_mi2s,
644+ msm_mux_hs2_mi2s,
645+ msm_mux_hs3_mi2s,
646+ msm_mux_ibi_i3c,
647+ msm_mux_jitter_bist,
648+ msm_mux_lpass_slimbus,
649+ msm_mux_mdp0_vsync0,
650+ msm_mux_mdp0_vsync1,
651+ msm_mux_mdp0_vsync2,
652+ msm_mux_mdp0_vsync3,
653+ msm_mux_mdp0_vsync4,
654+ msm_mux_mdp0_vsync5,
655+ msm_mux_mdp0_vsync6,
656+ msm_mux_mdp0_vsync7,
657+ msm_mux_mdp0_vsync8,
658+ msm_mux_mdp1_vsync0,
659+ msm_mux_mdp1_vsync1,
660+ msm_mux_mdp1_vsync2,
661+ msm_mux_mdp1_vsync3,
662+ msm_mux_mdp1_vsync4,
663+ msm_mux_mdp1_vsync5,
664+ msm_mux_mdp1_vsync6,
665+ msm_mux_mdp1_vsync7,
666+ msm_mux_mdp1_vsync8,
667+ msm_mux_mdp_vsync,
668+ msm_mux_mi2s0_data0,
669+ msm_mux_mi2s0_data1,
670+ msm_mux_mi2s0_sck,
671+ msm_mux_mi2s0_ws,
672+ msm_mux_mi2s1_data0,
673+ msm_mux_mi2s1_data1,
674+ msm_mux_mi2s1_sck,
675+ msm_mux_mi2s1_ws,
676+ msm_mux_mi2s2_data0,
677+ msm_mux_mi2s2_data1,
678+ msm_mux_mi2s2_sck,
679+ msm_mux_mi2s2_ws,
680+ msm_mux_mi2s_mclk1,
681+ msm_mux_mi2s_mclk2,
682+ msm_mux_pcie2a_clkreq,
683+ msm_mux_pcie2b_clkreq,
684+ msm_mux_pcie3a_clkreq,
685+ msm_mux_pcie3b_clkreq,
686+ msm_mux_pcie4_clkreq,
687+ msm_mux_phase_flag,
688+ msm_mux_pll_bist,
689+ msm_mux_pll_clk,
690+ msm_mux_prng_rosc0,
691+ msm_mux_prng_rosc1,
692+ msm_mux_prng_rosc2,
693+ msm_mux_prng_rosc3,
694+ msm_mux_qdss_cti,
695+ msm_mux_qdss_gpio,
696+ msm_mux_qspi,
697+ msm_mux_qspi_clk,
698+ msm_mux_qspi_cs,
699+ msm_mux_qup0,
700+ msm_mux_qup1,
701+ msm_mux_qup10,
702+ msm_mux_qup11,
703+ msm_mux_qup12,
704+ msm_mux_qup13,
705+ msm_mux_qup14,
706+ msm_mux_qup15,
707+ msm_mux_qup16,
708+ msm_mux_qup17,
709+ msm_mux_qup18,
710+ msm_mux_qup19,
711+ msm_mux_qup2,
712+ msm_mux_qup20,
713+ msm_mux_qup21,
714+ msm_mux_qup22,
715+ msm_mux_qup23,
716+ msm_mux_qup3,
717+ msm_mux_qup4,
718+ msm_mux_qup5,
719+ msm_mux_qup6,
720+ msm_mux_qup7,
721+ msm_mux_qup8,
722+ msm_mux_qup9,
723+ msm_mux_rgmii_0,
724+ msm_mux_rgmii_1,
725+ msm_mux_sd_write,
726+ msm_mux_sdc40,
727+ msm_mux_sdc42,
728+ msm_mux_sdc43,
729+ msm_mux_sdc4_clk,
730+ msm_mux_sdc4_cmd,
731+ msm_mux_tb_trig,
732+ msm_mux_tgu,
733+ msm_mux_tsense_pwm1,
734+ msm_mux_tsense_pwm2,
735+ msm_mux_tsense_pwm3,
736+ msm_mux_tsense_pwm4,
737+ msm_mux_usb0_dp,
738+ msm_mux_usb0_phy,
739+ msm_mux_usb0_sbrx,
740+ msm_mux_usb0_sbtx,
741+ msm_mux_usb0_usb4,
742+ msm_mux_usb1_dp,
743+ msm_mux_usb1_phy,
744+ msm_mux_usb1_sbrx,
745+ msm_mux_usb1_sbtx,
746+ msm_mux_usb1_usb4,
747+ msm_mux_usb2phy_ac,
748+ msm_mux_vsense_trigger,
749+ msm_mux__,
750+};
751+
752+static const char * const gpio_groups[] = {
753+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
754+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
755+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
756+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
757+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
758+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
759+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
760+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
761+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
762+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
763+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78",
764+ "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85",
765+ "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92",
766+ "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99",
767+ "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
768+ "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111",
769+ "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117",
770+ "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123",
771+ "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129",
772+ "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
773+ "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
774+ "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147",
775+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153",
776+ "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
777+ "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165",
778+ "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171",
779+ "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
780+ "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", "gpio183",
781+ "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", "gpio189",
782+ "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195",
783+ "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201",
784+ "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", "gpio207",
785+ "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", "gpio213",
786+ "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", "gpio219",
787+ "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", "gpio225",
788+ "gpio226", "gpio227",
789+};
790+
791+static const char * const atest_char_groups[] = {
792+ "gpio134", "gpio139", "gpio140", "gpio142", "gpio143",
793+};
794+
795+static const char * const atest_usb_groups[] = {
796+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78",
797+ "gpio79", "gpio97", "gpio98", "gpio101", "gpio102", "gpio103",
798+ "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113",
799+ "gpio114", "gpio121", "gpio122", "gpio130", "gpio131", "gpio135",
800+ "gpio137", "gpio138", "gpio148", "gpio149",
801+};
802+
803+static const char * const audio_ref_groups[] = {
804+ "gpio80",
805+};
806+
807+static const char * const cam_mclk_groups[] = {
808+ "gpio6", "gpio7", "gpio16", "gpio17", "gpio33", "gpio34", "gpio119",
809+ "gpio120",
810+};
811+
812+static const char * const cci_async_groups[] = {
813+ "gpio15", "gpio119", "gpio120", "gpio160", "gpio161", "gpio167",
814+};
815+
816+static const char * const cci_i2c_groups[] = {
817+ "gpio10", "gpio11", "gpio12", "gpio13", "gpio113", "gpio114",
818+ "gpio115", "gpio116", "gpio117", "gpio118", "gpio123", "gpio124",
819+ "gpio145", "gpio146", "gpio164", "gpio165",
820+};
821+
822+static const char * const cci_timer0_groups[] = {
823+ "gpio119",
824+};
825+
826+static const char * const cci_timer1_groups[] = {
827+ "gpio120",
828+};
829+
830+static const char * const cci_timer2_groups[] = {
831+ "gpio14",
832+};
833+
834+static const char * const cci_timer3_groups[] = {
835+ "gpio15",
836+};
837+
838+static const char * const cci_timer4_groups[] = {
839+ "gpio161",
840+};
841+
842+static const char * const cci_timer5_groups[] = {
843+ "gpio139",
844+};
845+
846+static const char * const cci_timer6_groups[] = {
847+ "gpio162",
848+};
849+
850+static const char * const cci_timer7_groups[] = {
851+ "gpio163",
852+};
853+
854+static const char * const cci_timer8_groups[] = {
855+ "gpio167",
856+};
857+
858+static const char * const cci_timer9_groups[] = {
859+ "gpio160",
860+};
861+
862+static const char * const cmu_rng_groups[] = {
863+ "gpio123", "gpio124", "gpio126", "gpio136",
864+};
865+
866+static const char * const cri_trng0_groups[] = {
867+ "gpio187",
868+};
869+
870+static const char * const cri_trng1_groups[] = {
871+ "gpio188",
872+};
873+
874+static const char * const cri_trng_groups[] = {
875+ "gpio190",
876+};
877+
878+static const char * const dbg_out_groups[] = {
879+ "gpio125",
880+};
881+
882+static const char * const ddr_bist_groups[] = {
883+ "gpio42", "gpio45", "gpio46", "gpio47",
884+};
885+
886+static const char * const ddr_pxi0_groups[] = {
887+ "gpio121", "gpio126",
888+};
889+
890+static const char * const ddr_pxi1_groups[] = {
891+ "gpio124", "gpio125",
892+};
893+
894+static const char * const ddr_pxi2_groups[] = {
895+ "gpio123", "gpio138",
896+};
897+
898+static const char * const ddr_pxi3_groups[] = {
899+ "gpio120", "gpio137",
900+};
901+
902+static const char * const ddr_pxi4_groups[] = {
903+ "gpio216", "gpio217",
904+};
905+
906+static const char * const ddr_pxi5_groups[] = {
907+ "gpio214", "gpio215",
908+};
909+
910+static const char * const ddr_pxi6_groups[] = {
911+ "gpio79", "gpio218",
912+};
913+
914+static const char * const ddr_pxi7_groups[] = {
915+ "gpio135", "gpio136",
916+};
917+
918+static const char * const dp2_hot_groups[] = {
919+ "gpio20",
920+};
921+
922+static const char * const dp3_hot_groups[] = {
923+ "gpio45",
924+};
925+
926+static const char * const edp0_lcd_groups[] = {
927+ "gpio26",
928+};
929+
930+static const char * const edp1_lcd_groups[] = {
931+ "gpio27",
932+};
933+
934+static const char * const edp2_lcd_groups[] = {
935+ "gpio28",
936+};
937+
938+static const char * const edp3_lcd_groups[] = {
939+ "gpio29",
940+};
941+
942+static const char * const edp_hot_groups[] = {
943+ "gpio2", "gpio3", "gpio6", "gpio7",
944+};
945+
946+static const char * const egpio_groups[] = {
947+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
948+ "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
949+ "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
950+ "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212",
951+ "gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218",
952+ "gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224",
953+ "gpio225", "gpio226", "gpio227",
954+};
955+
956+static const char * const emac0_dll_groups[] = {
957+ "gpio216", "gpio217",
958+};
959+
960+static const char * const emac0_mcg0_groups[] = {
961+ "gpio160",
962+};
963+
964+static const char * const emac0_mcg1_groups[] = {
965+ "gpio161",
966+};
967+
968+static const char * const emac0_mcg2_groups[] = {
969+ "gpio162",
970+};
971+
972+static const char * const emac0_mcg3_groups[] = {
973+ "gpio163",
974+};
975+
976+static const char * const emac0_phy_groups[] = {
977+ "gpio127",
978+};
979+
980+static const char * const emac0_ptp_groups[] = {
981+ "gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156",
982+ "gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159",
983+};
984+
985+static const char * const emac1_dll0_groups[] = {
986+ "gpio215",
987+};
988+
989+static const char * const emac1_dll1_groups[] = {
990+ "gpio218",
991+};
992+
993+static const char * const emac1_mcg0_groups[] = {
994+ "gpio57",
995+};
996+
997+static const char * const emac1_mcg1_groups[] = {
998+ "gpio58",
999+};
1000+
1001+static const char * const emac1_mcg2_groups[] = {
1002+ "gpio68",
1003+};
1004+
1005+static const char * const emac1_mcg3_groups[] = {
1006+ "gpio69",
1007+};
1008+
1009+static const char * const emac1_phy_groups[] = {
1010+ "gpio54",
1011+};
1012+
1013+static const char * const emac1_ptp_groups[] = {
1014+ "gpio55", "gpio55", "gpio56", "gpio56", "gpio93", "gpio93", "gpio94",
1015+ "gpio94", "gpio95", "gpio95", "gpio96", "gpio96",
1016+};
1017+
1018+static const char * const gcc_gp1_groups[] = {
1019+ "gpio119", "gpio149",
1020+};
1021+
1022+static const char * const gcc_gp2_groups[] = {
1023+ "gpio114", "gpio120",
1024+};
1025+
1026+static const char * const gcc_gp3_groups[] = {
1027+ "gpio115", "gpio139",
1028+};
1029+
1030+static const char * const gcc_gp4_groups[] = {
1031+ "gpio160", "gpio162",
1032+};
1033+
1034+static const char * const gcc_gp5_groups[] = {
1035+ "gpio167", "gpio168",
1036+};
1037+
1038+static const char * const hs1_mi2s_groups[] = {
1039+ "gpio208", "gpio209", "gpio210", "gpio211",
1040+};
1041+
1042+static const char * const hs2_mi2s_groups[] = {
1043+ "gpio91", "gpio92", "gpio218", "gpio219",
1044+};
1045+
1046+static const char * const hs3_mi2s_groups[] = {
1047+ "gpio224", "gpio225", "gpio226", "gpio227",
1048+};
1049+
1050+static const char * const ibi_i3c_groups[] = {
1051+ "gpio4", "gpio5", "gpio36", "gpio37", "gpio128", "gpio129", "gpio154",
1052+ "gpio155",
1053+};
1054+
1055+static const char * const jitter_bist_groups[] = {
1056+ "gpio140",
1057+};
1058+
1059+static const char * const lpass_slimbus_groups[] = {
1060+ "gpio220", "gpio221",
1061+};
1062+
1063+static const char * const mdp0_vsync0_groups[] = {
1064+ "gpio1",
1065+};
1066+
1067+static const char * const mdp0_vsync1_groups[] = {
1068+ "gpio2",
1069+};
1070+
1071+static const char * const mdp0_vsync2_groups[] = {
1072+ "gpio8",
1073+};
1074+
1075+static const char * const mdp0_vsync3_groups[] = {
1076+ "gpio9",
1077+};
1078+
1079+static const char * const mdp0_vsync4_groups[] = {
1080+ "gpio10",
1081+};
1082+
1083+static const char * const mdp0_vsync5_groups[] = {
1084+ "gpio11",
1085+};
1086+
1087+static const char * const mdp0_vsync6_groups[] = {
1088+ "gpio12",
1089+};
1090+
1091+static const char * const mdp0_vsync7_groups[] = {
1092+ "gpio13",
1093+};
1094+
1095+static const char * const mdp0_vsync8_groups[] = {
1096+ "gpio16",
1097+};
1098+
1099+static const char * const mdp1_vsync0_groups[] = {
1100+ "gpio17",
1101+};
1102+
1103+static const char * const mdp1_vsync1_groups[] = {
1104+ "gpio18",
1105+};
1106+
1107+static const char * const mdp1_vsync2_groups[] = {
1108+ "gpio19",
1109+};
1110+
1111+static const char * const mdp1_vsync3_groups[] = {
1112+ "gpio20",
1113+};
1114+
1115+static const char * const mdp1_vsync4_groups[] = {
1116+ "gpio36",
1117+};
1118+
1119+static const char * const mdp1_vsync5_groups[] = {
1120+ "gpio37",
1121+};
1122+
1123+static const char * const mdp1_vsync6_groups[] = {
1124+ "gpio38",
1125+};
1126+
1127+static const char * const mdp1_vsync7_groups[] = {
1128+ "gpio39",
1129+};
1130+
1131+static const char * const mdp1_vsync8_groups[] = {
1132+ "gpio40",
1133+};
1134+
1135+static const char * const mdp_vsync_groups[] = {
1136+ "gpio8", "gpio100", "gpio101",
1137+};
1138+
1139+static const char * const mi2s0_data0_groups[] = {
1140+ "gpio95",
1141+};
1142+
1143+static const char * const mi2s0_data1_groups[] = {
1144+ "gpio96",
1145+};
1146+
1147+static const char * const mi2s0_sck_groups[] = {
1148+ "gpio93",
1149+};
1150+
1151+static const char * const mi2s0_ws_groups[] = {
1152+ "gpio94",
1153+};
1154+
1155+static const char * const mi2s1_data0_groups[] = {
1156+ "gpio222",
1157+};
1158+
1159+static const char * const mi2s1_data1_groups[] = {
1160+ "gpio223",
1161+};
1162+
1163+static const char * const mi2s1_sck_groups[] = {
1164+ "gpio220",
1165+};
1166+
1167+static const char * const mi2s1_ws_groups[] = {
1168+ "gpio221",
1169+};
1170+
1171+static const char * const mi2s2_data0_groups[] = {
1172+ "gpio214",
1173+};
1174+
1175+static const char * const mi2s2_data1_groups[] = {
1176+ "gpio215",
1177+};
1178+
1179+static const char * const mi2s2_sck_groups[] = {
1180+ "gpio212",
1181+};
1182+
1183+static const char * const mi2s2_ws_groups[] = {
1184+ "gpio213",
1185+};
1186+
1187+static const char * const mi2s_mclk1_groups[] = {
1188+ "gpio80", "gpio216",
1189+};
1190+
1191+static const char * const mi2s_mclk2_groups[] = {
1192+ "gpio217",
1193+};
1194+
1195+static const char * const pcie2a_clkreq_groups[] = {
1196+ "gpio142",
1197+};
1198+
1199+static const char * const pcie2b_clkreq_groups[] = {
1200+ "gpio144",
1201+};
1202+
1203+static const char * const pcie3a_clkreq_groups[] = {
1204+ "gpio150",
1205+};
1206+
1207+static const char * const pcie3b_clkreq_groups[] = {
1208+ "gpio152",
1209+};
1210+
1211+static const char * const pcie4_clkreq_groups[] = {
1212+ "gpio140",
1213+};
1214+
1215+static const char * const phase_flag_groups[] = {
1216+ "gpio80", "gpio81", "gpio82", "gpio83", "gpio87", "gpio88", "gpio89",
1217+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio132",
1218+ "gpio144", "gpio145", "gpio146", "gpio147", "gpio195", "gpio196",
1219+ "gpio197", "gpio198", "gpio202", "gpio219", "gpio220", "gpio221",
1220+ "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227",
1221+};
1222+
1223+static const char * const pll_bist_groups[] = {
1224+ "gpio84",
1225+};
1226+
1227+static const char * const pll_clk_groups[] = {
1228+ "gpio84", "gpio86",
1229+};
1230+
1231+static const char * const prng_rosc0_groups[] = {
1232+ "gpio189",
1233+};
1234+
1235+static const char * const prng_rosc1_groups[] = {
1236+ "gpio191",
1237+};
1238+
1239+static const char * const prng_rosc2_groups[] = {
1240+ "gpio193",
1241+};
1242+
1243+static const char * const prng_rosc3_groups[] = {
1244+ "gpio194",
1245+};
1246+
1247+static const char * const qdss_cti_groups[] = {
1248+ "gpio3", "gpio4", "gpio7", "gpio21", "gpio30", "gpio30", "gpio31",
1249+ "gpio31",
1250+};
1251+
1252+static const char * const qdss_gpio_groups[] = {
1253+ "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
1254+ "gpio17", "gpio80", "gpio96", "gpio115", "gpio116", "gpio117",
1255+ "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio161",
1256+ "gpio162", "gpio195", "gpio196", "gpio197", "gpio198", "gpio201",
1257+ "gpio202", "gpio206", "gpio207", "gpio212", "gpio213", "gpio214",
1258+ "gpio215", "gpio216", "gpio217", "gpio222", "gpio223",
1259+};
1260+
1261+static const char * const qspi_clk_groups[] = {
1262+ "gpio74",
1263+};
1264+
1265+static const char * const qspi_cs_groups[] = {
1266+ "gpio75", "gpio81",
1267+};
1268+
1269+static const char * const qspi_groups[] = {
1270+ "gpio76", "gpio78", "gpio79",
1271+};
1272+
1273+static const char * const qup0_groups[] = {
1274+ "gpio135", "gpio136", "gpio137", "gpio138",
1275+};
1276+
1277+static const char * const qup10_groups[] = {
1278+ "gpio22", "gpio23", "gpio24", "gpio25",
1279+};
1280+
1281+static const char * const qup11_groups[] = {
1282+ "gpio18", "gpio19", "gpio20", "gpio21",
1283+};
1284+
1285+static const char * const qup12_groups[] = {
1286+ "gpio0", "gpio1", "gpio2", "gpio3",
1287+};
1288+
1289+static const char * const qup13_groups[] = {
1290+ "gpio26", "gpio27", "gpio28", "gpio29",
1291+};
1292+
1293+static const char * const qup14_groups[] = {
1294+ "gpio4", "gpio5", "gpio6", "gpio7",
1295+};
1296+
1297+static const char * const qup15_groups[] = {
1298+ "gpio36", "gpio37", "gpio38", "gpio39",
1299+};
1300+
1301+static const char * const qup16_groups[] = {
1302+ "gpio70", "gpio71", "gpio72", "gpio73",
1303+};
1304+
1305+static const char * const qup17_groups[] = {
1306+ "gpio61", "gpio62", "gpio63", "gpio64",
1307+};
1308+
1309+static const char * const qup18_groups[] = {
1310+ "gpio66", "gpio67", "gpio68", "gpio69",
1311+};
1312+
1313+static const char * const qup19_groups[] = {
1314+ "gpio55", "gpio56", "gpio57", "gpio58",
1315+};
1316+
1317+static const char * const qup1_groups[] = {
1318+ "gpio158", "gpio159", "gpio160", "gpio161",
1319+};
1320+
1321+static const char * const qup20_groups[] = {
1322+ "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio110",
1323+};
1324+
1325+static const char * const qup21_groups[] = {
1326+ "gpio81", "gpio82", "gpio83", "gpio84",
1327+};
1328+
1329+static const char * const qup22_groups[] = {
1330+ "gpio83", "gpio84", "gpio85", "gpio86",
1331+};
1332+
1333+static const char * const qup23_groups[] = {
1334+ "gpio59", "gpio60", "gpio61", "gpio62",
1335+};
1336+
1337+static const char * const qup2_groups[] = {
1338+ "gpio121", "gpio122", "gpio123", "gpio124",
1339+};
1340+
1341+static const char * const qup3_groups[] = {
1342+ "gpio135", "gpio136", "gpio137", "gpio138",
1343+};
1344+
1345+static const char * const qup4_groups[] = {
1346+ "gpio111", "gpio112", "gpio171", "gpio172", "gpio173", "gpio174",
1347+ "gpio175",
1348+};
1349+
1350+static const char * const qup5_groups[] = {
1351+ "gpio111", "gpio112", "gpio145", "gpio146",
1352+};
1353+
1354+static const char * const qup6_groups[] = {
1355+ "gpio154", "gpio155", "gpio156", "gpio157",
1356+};
1357+
1358+static const char * const qup7_groups[] = {
1359+ "gpio125", "gpio126", "gpio128", "gpio129",
1360+};
1361+
1362+static const char * const qup8_groups[] = {
1363+ "gpio43", "gpio44", "gpio45", "gpio46",
1364+};
1365+
1366+static const char * const qup9_groups[] = {
1367+ "gpio41", "gpio42", "gpio43", "gpio44",
1368+};
1369+
1370+static const char * const rgmii_0_groups[] = {
1371+ "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180",
1372+ "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
1373+ "gpio187", "gpio188",
1374+};
1375+
1376+static const char * const rgmii_1_groups[] = {
1377+ "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102",
1378+ "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108",
1379+ "gpio109", "gpio110",
1380+};
1381+
1382+static const char * const sd_write_groups[] = {
1383+ "gpio130",
1384+};
1385+
1386+static const char * const sdc40_groups[] = {
1387+ "gpio76",
1388+};
1389+
1390+static const char * const sdc42_groups[] = {
1391+ "gpio78",
1392+};
1393+
1394+static const char * const sdc43_groups[] = {
1395+ "gpio79",
1396+};
1397+
1398+static const char * const sdc4_clk_groups[] = {
1399+ "gpio74",
1400+};
1401+
1402+static const char * const sdc4_cmd_groups[] = {
1403+ "gpio75",
1404+};
1405+
1406+static const char * const tb_trig_groups[] = {
1407+ "gpio153", "gpio157",
1408+};
1409+
1410+static const char * const tgu_groups[] = {
1411+ "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
1412+ "gpio107", "gpio108",
1413+};
1414+
1415+static const char * const tsense_pwm1_groups[] = {
1416+ "gpio70",
1417+};
1418+
1419+static const char * const tsense_pwm2_groups[] = {
1420+ "gpio69",
1421+};
1422+
1423+static const char * const tsense_pwm3_groups[] = {
1424+ "gpio67",
1425+};
1426+
1427+static const char * const tsense_pwm4_groups[] = {
1428+ "gpio65",
1429+};
1430+
1431+static const char * const usb0_dp_groups[] = {
1432+ "gpio21",
1433+};
1434+
1435+static const char * const usb0_phy_groups[] = {
1436+ "gpio166",
1437+};
1438+
1439+static const char * const usb0_sbrx_groups[] = {
1440+ "gpio170",
1441+};
1442+
1443+static const char * const usb0_sbtx_groups[] = {
1444+ "gpio168", "gpio169",
1445+};
1446+
1447+static const char * const usb0_usb4_groups[] = {
1448+ "gpio132",
1449+};
1450+
1451+static const char * const usb1_dp_groups[] = {
1452+ "gpio9",
1453+};
1454+
1455+static const char * const usb1_phy_groups[] = {
1456+ "gpio49",
1457+};
1458+
1459+static const char * const usb1_sbrx_groups[] = {
1460+ "gpio53",
1461+};
1462+
1463+static const char * const usb1_sbtx_groups[] = {
1464+ "gpio51", "gpio52",
1465+};
1466+
1467+static const char * const usb1_usb4_groups[] = {
1468+ "gpio32",
1469+};
1470+
1471+static const char * const usb2phy_ac_groups[] = {
1472+ "gpio24", "gpio25", "gpio133", "gpio134", "gpio148", "gpio149",
1473+};
1474+
1475+static const char * const vsense_trigger_groups[] = {
1476+ "gpio81",
1477+};
1478+
1479+static const struct msm_function sc8280xp_functions[] = {
1480+ FUNCTION(atest_char),
1481+ FUNCTION(atest_usb),
1482+ FUNCTION(audio_ref),
1483+ FUNCTION(cam_mclk),
1484+ FUNCTION(cci_async),
1485+ FUNCTION(cci_i2c),
1486+ FUNCTION(cci_timer0),
1487+ FUNCTION(cci_timer1),
1488+ FUNCTION(cci_timer2),
1489+ FUNCTION(cci_timer3),
1490+ FUNCTION(cci_timer4),
1491+ FUNCTION(cci_timer5),
1492+ FUNCTION(cci_timer6),
1493+ FUNCTION(cci_timer7),
1494+ FUNCTION(cci_timer8),
1495+ FUNCTION(cci_timer9),
1496+ FUNCTION(cmu_rng),
1497+ FUNCTION(cri_trng),
1498+ FUNCTION(cri_trng0),
1499+ FUNCTION(cri_trng1),
1500+ FUNCTION(dbg_out),
1501+ FUNCTION(ddr_bist),
1502+ FUNCTION(ddr_pxi0),
1503+ FUNCTION(ddr_pxi1),
1504+ FUNCTION(ddr_pxi2),
1505+ FUNCTION(ddr_pxi3),
1506+ FUNCTION(ddr_pxi4),
1507+ FUNCTION(ddr_pxi5),
1508+ FUNCTION(ddr_pxi6),
1509+ FUNCTION(ddr_pxi7),
1510+ FUNCTION(dp2_hot),
1511+ FUNCTION(dp3_hot),
1512+ FUNCTION(edp0_lcd),
1513+ FUNCTION(edp1_lcd),
1514+ FUNCTION(edp2_lcd),
1515+ FUNCTION(edp3_lcd),
1516+ FUNCTION(edp_hot),
1517+ FUNCTION(egpio),
1518+ FUNCTION(emac0_dll),
1519+ FUNCTION(emac0_mcg0),
1520+ FUNCTION(emac0_mcg1),
1521+ FUNCTION(emac0_mcg2),
1522+ FUNCTION(emac0_mcg3),
1523+ FUNCTION(emac0_phy),
1524+ FUNCTION(emac0_ptp),
1525+ FUNCTION(emac1_dll0),
1526+ FUNCTION(emac1_dll1),
1527+ FUNCTION(emac1_mcg0),
1528+ FUNCTION(emac1_mcg1),
1529+ FUNCTION(emac1_mcg2),
1530+ FUNCTION(emac1_mcg3),
1531+ FUNCTION(emac1_phy),
1532+ FUNCTION(emac1_ptp),
1533+ FUNCTION(gcc_gp1),
1534+ FUNCTION(gcc_gp2),
1535+ FUNCTION(gcc_gp3),
1536+ FUNCTION(gcc_gp4),
1537+ FUNCTION(gcc_gp5),
1538+ FUNCTION(gpio),
1539+ FUNCTION(hs1_mi2s),
1540+ FUNCTION(hs2_mi2s),
1541+ FUNCTION(hs3_mi2s),
1542+ FUNCTION(ibi_i3c),
1543+ FUNCTION(jitter_bist),
1544+ FUNCTION(lpass_slimbus),
1545+ FUNCTION(mdp0_vsync0),
1546+ FUNCTION(mdp0_vsync1),
1547+ FUNCTION(mdp0_vsync2),
1548+ FUNCTION(mdp0_vsync3),
1549+ FUNCTION(mdp0_vsync4),
1550+ FUNCTION(mdp0_vsync5),
1551+ FUNCTION(mdp0_vsync6),
1552+ FUNCTION(mdp0_vsync7),
1553+ FUNCTION(mdp0_vsync8),
1554+ FUNCTION(mdp1_vsync0),
1555+ FUNCTION(mdp1_vsync1),
1556+ FUNCTION(mdp1_vsync2),
1557+ FUNCTION(mdp1_vsync3),
1558+ FUNCTION(mdp1_vsync4),
1559+ FUNCTION(mdp1_vsync5),
1560+ FUNCTION(mdp1_vsync6),
1561+ FUNCTION(mdp1_vsync7),
1562+ FUNCTION(mdp1_vsync8),
1563+ FUNCTION(mdp_vsync),
1564+ FUNCTION(mi2s0_data0),
1565+ FUNCTION(mi2s0_data1),
1566+ FUNCTION(mi2s0_sck),
1567+ FUNCTION(mi2s0_ws),
1568+ FUNCTION(mi2s1_data0),
1569+ FUNCTION(mi2s1_data1),
1570+ FUNCTION(mi2s1_sck),
1571+ FUNCTION(mi2s1_ws),
1572+ FUNCTION(mi2s2_data0),
1573+ FUNCTION(mi2s2_data1),
1574+ FUNCTION(mi2s2_sck),
1575+ FUNCTION(mi2s2_ws),
1576+ FUNCTION(mi2s_mclk1),
1577+ FUNCTION(mi2s_mclk2),
1578+ FUNCTION(pcie2a_clkreq),
1579+ FUNCTION(pcie2b_clkreq),
1580+ FUNCTION(pcie3a_clkreq),
1581+ FUNCTION(pcie3b_clkreq),
1582+ FUNCTION(pcie4_clkreq),
1583+ FUNCTION(phase_flag),
1584+ FUNCTION(pll_bist),
1585+ FUNCTION(pll_clk),
1586+ FUNCTION(prng_rosc0),
1587+ FUNCTION(prng_rosc1),
1588+ FUNCTION(prng_rosc2),
1589+ FUNCTION(prng_rosc3),
1590+ FUNCTION(qdss_cti),
1591+ FUNCTION(qdss_gpio),
1592+ FUNCTION(qspi),
1593+ FUNCTION(qspi_clk),
1594+ FUNCTION(qspi_cs),
1595+ FUNCTION(qup0),
1596+ FUNCTION(qup1),
1597+ FUNCTION(qup2),
1598+ FUNCTION(qup3),
1599+ FUNCTION(qup4),
1600+ FUNCTION(qup5),
1601+ FUNCTION(qup6),
1602+ FUNCTION(qup7),
1603+ FUNCTION(qup8),
1604+ FUNCTION(qup9),
1605+ FUNCTION(qup10),
1606+ FUNCTION(qup11),
1607+ FUNCTION(qup12),
1608+ FUNCTION(qup13),
1609+ FUNCTION(qup14),
1610+ FUNCTION(qup15),
1611+ FUNCTION(qup16),
1612+ FUNCTION(qup17),
1613+ FUNCTION(qup18),
1614+ FUNCTION(qup19),
1615+ FUNCTION(qup20),
1616+ FUNCTION(qup21),
1617+ FUNCTION(qup22),
1618+ FUNCTION(qup23),
1619+ FUNCTION(rgmii_0),
1620+ FUNCTION(rgmii_1),
1621+ FUNCTION(sd_write),
1622+ FUNCTION(sdc40),
1623+ FUNCTION(sdc42),
1624+ FUNCTION(sdc43),
1625+ FUNCTION(sdc4_clk),
1626+ FUNCTION(sdc4_cmd),
1627+ FUNCTION(tb_trig),
1628+ FUNCTION(tgu),
1629+ FUNCTION(tsense_pwm1),
1630+ FUNCTION(tsense_pwm2),
1631+ FUNCTION(tsense_pwm3),
1632+ FUNCTION(tsense_pwm4),
1633+ FUNCTION(usb0_dp),
1634+ FUNCTION(usb0_phy),
1635+ FUNCTION(usb0_sbrx),
1636+ FUNCTION(usb0_sbtx),
1637+ FUNCTION(usb0_usb4),
1638+ FUNCTION(usb1_dp),
1639+ FUNCTION(usb1_phy),
1640+ FUNCTION(usb1_sbrx),
1641+ FUNCTION(usb1_sbtx),
1642+ FUNCTION(usb1_usb4),
1643+ FUNCTION(usb2phy_ac),
1644+ FUNCTION(vsense_trigger),
1645+};
1646+
1647+static const struct msm_pingroup sc8280xp_groups[] = {
1648+ [0] = PINGROUP(0, qup12, _, _, _, _, _, _),
1649+ [1] = PINGROUP(1, qup12, mdp0_vsync0, _, _, _, _, _),
1650+ [2] = PINGROUP(2, edp_hot, qup12, mdp0_vsync1, _, _, _, _),
1651+ [3] = PINGROUP(3, edp_hot, qup12, qdss_cti, _, _, _, _),
1652+ [4] = PINGROUP(4, qup14, ibi_i3c, qdss_cti, _, _, _, _),
1653+ [5] = PINGROUP(5, qup14, ibi_i3c, _, _, _, _, _),
1654+ [6] = PINGROUP(6, edp_hot, qup14, cam_mclk, _, _, _, _),
1655+ [7] = PINGROUP(7, edp_hot, qup14, qdss_cti, cam_mclk, _, _, _),
1656+ [8] = PINGROUP(8, mdp_vsync, mdp0_vsync2, _, _, _, _, _),
1657+ [9] = PINGROUP(9, usb1_dp, mdp0_vsync3, _, _, _, _, _),
1658+ [10] = PINGROUP(10, cci_i2c, mdp0_vsync4, _, qdss_gpio, _, _, _),
1659+ [11] = PINGROUP(11, cci_i2c, mdp0_vsync5, _, qdss_gpio, _, _, _),
1660+ [12] = PINGROUP(12, cci_i2c, mdp0_vsync6, _, qdss_gpio, _, _, _),
1661+ [13] = PINGROUP(13, cci_i2c, mdp0_vsync7, _, qdss_gpio, _, _, _),
1662+ [14] = PINGROUP(14, cci_timer2, qdss_gpio, _, _, _, _, _),
1663+ [15] = PINGROUP(15, cci_timer3, cci_async, _, qdss_gpio, _, _, _),
1664+ [16] = PINGROUP(16, cam_mclk, mdp0_vsync8, _, qdss_gpio, _, _, _),
1665+ [17] = PINGROUP(17, cam_mclk, mdp1_vsync0, _, qdss_gpio, _, _, _),
1666+ [18] = PINGROUP(18, qup11, mdp1_vsync1, _, _, _, _, _),
1667+ [19] = PINGROUP(19, qup11, mdp1_vsync2, _, _, _, _, _),
1668+ [20] = PINGROUP(20, qup11, dp2_hot, mdp1_vsync3, _, _, _, _),
1669+ [21] = PINGROUP(21, qup11, usb0_dp, qdss_cti, _, _, _, _),
1670+ [22] = PINGROUP(22, qup10, _, _, _, _, _, _),
1671+ [23] = PINGROUP(23, qup10, _, _, _, _, _, _),
1672+ [24] = PINGROUP(24, qup10, usb2phy_ac, _, _, _, _, _),
1673+ [25] = PINGROUP(25, qup10, usb2phy_ac, _, _, _, _, _),
1674+ [26] = PINGROUP(26, qup13, edp0_lcd, _, _, _, _, _),
1675+ [27] = PINGROUP(27, qup13, edp1_lcd, _, _, _, _, _),
1676+ [28] = PINGROUP(28, qup13, edp2_lcd, _, _, _, _, _),
1677+ [29] = PINGROUP(29, qup13, edp3_lcd, _, _, _, _, _),
1678+ [30] = PINGROUP(30, qdss_cti, qdss_cti, _, _, _, _, _),
1679+ [31] = PINGROUP(31, qdss_cti, qdss_cti, _, _, _, _, _),
1680+ [32] = PINGROUP(32, usb1_usb4, _, _, _, _, _, _),
1681+ [33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _),
1682+ [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _),
1683+ [35] = PINGROUP(35, _, _, _, _, _, _, _),
1684+ [36] = PINGROUP(36, qup15, ibi_i3c, mdp1_vsync4, _, _, _, _),
1685+ [37] = PINGROUP(37, qup15, ibi_i3c, mdp1_vsync5, _, _, _, _),
1686+ [38] = PINGROUP(38, qup15, mdp1_vsync6, _, _, _, _, _),
1687+ [39] = PINGROUP(39, qup15, mdp1_vsync7, _, _, _, _, _),
1688+ [40] = PINGROUP(40, mdp1_vsync8, _, _, _, _, _, _),
1689+ [41] = PINGROUP(41, qup9, _, _, _, _, _, _),
1690+ [42] = PINGROUP(42, qup9, ddr_bist, _, _, _, _, _),
1691+ [43] = PINGROUP(43, qup8, qup9, _, _, _, _, _),
1692+ [44] = PINGROUP(44, qup8, qup9, _, _, _, _, _),
1693+ [45] = PINGROUP(45, qup8, dp3_hot, ddr_bist, _, _, _, _),
1694+ [46] = PINGROUP(46, qup8, ddr_bist, _, _, _, _, _),
1695+ [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _),
1696+ [48] = PINGROUP(48, _, _, _, _, _, _, _),
1697+ [49] = PINGROUP(49, usb1_phy, _, _, _, _, _, _),
1698+ [50] = PINGROUP(50, _, _, _, _, _, _, _),
1699+ [51] = PINGROUP(51, usb1_sbtx, _, _, _, _, _, _),
1700+ [52] = PINGROUP(52, usb1_sbtx, _, _, _, _, _, _),
1701+ [53] = PINGROUP(53, usb1_sbrx, _, _, _, _, _, _),
1702+ [54] = PINGROUP(54, emac1_phy, _, _, _, _, _, _),
1703+ [55] = PINGROUP(55, emac1_ptp, emac1_ptp, qup19, _, _, _, _),
1704+ [56] = PINGROUP(56, emac1_ptp, emac1_ptp, qup19, _, _, _, _),
1705+ [57] = PINGROUP(57, qup19, emac1_mcg0, _, _, _, _, _),
1706+ [58] = PINGROUP(58, qup19, emac1_mcg1, _, _, _, _, _),
1707+ [59] = PINGROUP(59, qup23, _, _, _, _, _, _),
1708+ [60] = PINGROUP(60, qup23, _, _, _, _, _, _),
1709+ [61] = PINGROUP(61, qup23, qup17, _, _, _, _, _),
1710+ [62] = PINGROUP(62, qup23, qup17, _, _, _, _, _),
1711+ [63] = PINGROUP(63, qup17, _, _, _, _, _, _),
1712+ [64] = PINGROUP(64, qup17, _, _, _, _, _, _),
1713+ [65] = PINGROUP(65, tsense_pwm4, _, _, _, _, _, _),
1714+ [66] = PINGROUP(66, qup18, _, _, _, _, _, _),
1715+ [67] = PINGROUP(67, qup18, tsense_pwm3, _, _, _, _, _),
1716+ [68] = PINGROUP(68, qup18, emac1_mcg2, _, _, _, _, _),
1717+ [69] = PINGROUP(69, qup18, emac1_mcg3, tsense_pwm2, _, _, _, _),
1718+ [70] = PINGROUP(70, qup16, tsense_pwm1, _, _, _, _, _),
1719+ [71] = PINGROUP(71, qup16, atest_usb, _, _, _, _, _),
1720+ [72] = PINGROUP(72, qup16, atest_usb, _, _, _, _, _),
1721+ [73] = PINGROUP(73, qup16, atest_usb, _, _, _, _, _),
1722+ [74] = PINGROUP(74, qspi_clk, sdc4_clk, atest_usb, _, _, _, _),
1723+ [75] = PINGROUP(75, qspi_cs, sdc4_cmd, atest_usb, _, _, _, _),
1724+ [76] = PINGROUP(76, qspi, sdc40, atest_usb, _, _, _, _),
1725+ [77] = PINGROUP(77, _, _, _, _, _, _, _),
1726+ [78] = PINGROUP(78, qspi, sdc42, atest_usb, _, _, _, _),
1727+ [79] = PINGROUP(79, qspi, sdc43, atest_usb, ddr_pxi6, _, _, _),
1728+ [80] = PINGROUP(80, mi2s_mclk1, audio_ref, phase_flag, _, qdss_gpio, _, _),
1729+ [81] = PINGROUP(81, qup21, qspi_cs, phase_flag, _, vsense_trigger, _, _),
1730+ [82] = PINGROUP(82, qup21, phase_flag, _, _, _, _, _),
1731+ [83] = PINGROUP(83, qup21, qup22, phase_flag, _, _, _, _),
1732+ [84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _),
1733+ [85] = PINGROUP(85, qup22, _, _, _, _, _, _),
1734+ [86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _),
1735+ [87] = PINGROUP(87, qup20, phase_flag, _, _, _, _, _),
1736+ [88] = PINGROUP(88, qup20, phase_flag, _, _, _, _, _),
1737+ [89] = PINGROUP(89, qup20, phase_flag, _, _, _, _, _),
1738+ [90] = PINGROUP(90, qup20, phase_flag, _, _, _, _, _),
1739+ [91] = PINGROUP(91, qup20, hs2_mi2s, phase_flag, _, _, _, _),
1740+ [92] = PINGROUP(92, qup20, hs2_mi2s, phase_flag, _, _, _, _),
1741+ [93] = PINGROUP(93, mi2s0_sck, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
1742+ [94] = PINGROUP(94, mi2s0_ws, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
1743+ [95] = PINGROUP(95, mi2s0_data0, emac1_ptp, emac1_ptp, phase_flag, _, _, _),
1744+ [96] = PINGROUP(96, mi2s0_data1, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _),
1745+ [97] = PINGROUP(97, rgmii_1, atest_usb, _, _, _, _, _),
1746+ [98] = PINGROUP(98, rgmii_1, atest_usb, _, _, _, _, _),
1747+ [99] = PINGROUP(99, rgmii_1, _, _, _, _, _, _),
1748+ [100] = PINGROUP(100, mdp_vsync, rgmii_1, _, _, _, _, _),
1749+ [101] = PINGROUP(101, mdp_vsync, rgmii_1, tgu, atest_usb, _, _, _),
1750+ [102] = PINGROUP(102, rgmii_1, tgu, atest_usb, _, _, _, _),
1751+ [103] = PINGROUP(103, rgmii_1, tgu, atest_usb, _, _, _, _),
1752+ [104] = PINGROUP(104, rgmii_1, tgu, atest_usb, _, _, _, _),
1753+ [105] = PINGROUP(105, rgmii_1, tgu, atest_usb, _, _, _, _),
1754+ [106] = PINGROUP(106, rgmii_1, tgu, _, _, _, _, _),
1755+ [107] = PINGROUP(107, rgmii_1, tgu, _, _, _, _, _),
1756+ [108] = PINGROUP(108, rgmii_1, tgu, _, _, _, _, _),
1757+ [109] = PINGROUP(109, rgmii_1, _, _, _, _, _, _),
1758+ [110] = PINGROUP(110, qup20, rgmii_1, atest_usb, _, _, _, _),
1759+ [111] = PINGROUP(111, qup4, qup5, atest_usb, _, _, _, _),
1760+ [112] = PINGROUP(112, qup4, qup5, atest_usb, _, _, _, _),
1761+ [113] = PINGROUP(113, cci_i2c, atest_usb, _, _, _, _, _),
1762+ [114] = PINGROUP(114, cci_i2c, gcc_gp2, atest_usb, _, _, _, _),
1763+ [115] = PINGROUP(115, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _),
1764+ [116] = PINGROUP(116, cci_i2c, qdss_gpio, _, _, _, _, _),
1765+ [117] = PINGROUP(117, cci_i2c, _, qdss_gpio, _, _, _, _),
1766+ [118] = PINGROUP(118, cci_i2c, _, qdss_gpio, _, _, _, _),
1767+ [119] = PINGROUP(119, cam_mclk, cci_timer0, cci_async, gcc_gp1, qdss_gpio, _, _),
1768+ [120] = PINGROUP(120, cam_mclk, cci_timer1, cci_async, gcc_gp2, qdss_gpio, ddr_pxi3, _),
1769+ [121] = PINGROUP(121, qup2, qdss_gpio, _, atest_usb, ddr_pxi0, _, _),
1770+ [122] = PINGROUP(122, qup2, qdss_gpio, atest_usb, _, _, _, _),
1771+ [123] = PINGROUP(123, qup2, cci_i2c, cmu_rng, ddr_pxi2, _, _, _),
1772+ [124] = PINGROUP(124, qup2, cci_i2c, cmu_rng, ddr_pxi1, _, _, _),
1773+ [125] = PINGROUP(125, qup7, dbg_out, ddr_pxi1, _, _, _, _),
1774+ [126] = PINGROUP(126, qup7, cmu_rng, ddr_pxi0, _, _, _, _),
1775+ [127] = PINGROUP(127, emac0_phy, _, _, _, _, _, _),
1776+ [128] = PINGROUP(128, qup7, ibi_i3c, _, _, _, _, _),
1777+ [129] = PINGROUP(129, qup7, ibi_i3c, _, _, _, _, _),
1778+ [130] = PINGROUP(130, emac0_ptp, emac0_ptp, sd_write, atest_usb, _, _, _),
1779+ [131] = PINGROUP(131, emac0_ptp, emac0_ptp, atest_usb, _, _, _, _),
1780+ [132] = PINGROUP(132, usb0_usb4, phase_flag, _, _, _, _, _),
1781+ [133] = PINGROUP(133, usb2phy_ac, _, _, _, _, _, _),
1782+ [134] = PINGROUP(134, usb2phy_ac, atest_char, _, _, _, _, _),
1783+ [135] = PINGROUP(135, qup0, qup3, _, atest_usb, ddr_pxi7, _, _),
1784+ [136] = PINGROUP(136, qup0, qup3, cmu_rng, ddr_pxi7, _, _, _),
1785+ [137] = PINGROUP(137, qup3, qup0, _, atest_usb, ddr_pxi3, _, _),
1786+ [138] = PINGROUP(138, qup3, qup0, _, atest_usb, ddr_pxi2, _, _),
1787+ [139] = PINGROUP(139, cci_timer5, gcc_gp3, atest_char, _, _, _, _),
1788+ [140] = PINGROUP(140, pcie4_clkreq, jitter_bist, atest_char, _, _, _, _),
1789+ [141] = PINGROUP(141, _, _, _, _, _, _, _),
1790+ [142] = PINGROUP(142, pcie2a_clkreq, atest_char, _, _, _, _, _),
1791+ [143] = PINGROUP(143, _, atest_char, _, _, _, _, _),
1792+ [144] = PINGROUP(144, pcie2b_clkreq, phase_flag, _, _, _, _, _),
1793+ [145] = PINGROUP(145, qup5, cci_i2c, phase_flag, _, _, _, _),
1794+ [146] = PINGROUP(146, qup5, cci_i2c, phase_flag, _, _, _, _),
1795+ [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _),
1796+ [148] = PINGROUP(148, usb2phy_ac, _, atest_usb, _, _, _, _),
1797+ [149] = PINGROUP(149, usb2phy_ac, gcc_gp1, atest_usb, _, _, _, _),
1798+ [150] = PINGROUP(150, pcie3a_clkreq, _, _, _, _, _, _),
1799+ [151] = PINGROUP(151, _, _, _, _, _, _, _),
1800+ [152] = PINGROUP(152, pcie3b_clkreq, _, _, _, _, _, _),
1801+ [153] = PINGROUP(153, _, tb_trig, _, _, _, _, _),
1802+ [154] = PINGROUP(154, qup6, ibi_i3c, _, _, _, _, _),
1803+ [155] = PINGROUP(155, qup6, ibi_i3c, _, _, _, _, _),
1804+ [156] = PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _),
1805+ [157] = PINGROUP(157, qup6, emac0_ptp, emac0_ptp, tb_trig, _, _, _),
1806+ [158] = PINGROUP(158, qup1, emac0_ptp, emac0_ptp, _, _, _, _),
1807+ [159] = PINGROUP(159, qup1, emac0_ptp, emac0_ptp, _, _, _, _),
1808+ [160] = PINGROUP(160, cci_timer9, qup1, cci_async, emac0_mcg0, gcc_gp4, _, _),
1809+ [161] = PINGROUP(161, cci_timer4, cci_async, qup1, emac0_mcg1, qdss_gpio, _, _),
1810+ [162] = PINGROUP(162, cci_timer6, emac0_mcg2, gcc_gp4, qdss_gpio, _, _, _),
1811+ [163] = PINGROUP(163, cci_timer7, emac0_mcg3, _, _, _, _, _),
1812+ [164] = PINGROUP(164, cci_i2c, _, _, _, _, _, _),
1813+ [165] = PINGROUP(165, cci_i2c, _, _, _, _, _, _),
1814+ [166] = PINGROUP(166, usb0_phy, _, _, _, _, _, _),
1815+ [167] = PINGROUP(167, cci_timer8, cci_async, gcc_gp5, _, _, _, _),
1816+ [168] = PINGROUP(168, usb0_sbtx, gcc_gp5, _, _, _, _, _),
1817+ [169] = PINGROUP(169, usb0_sbtx, _, _, _, _, _, _),
1818+ [170] = PINGROUP(170, usb0_sbrx, _, _, _, _, _, _),
1819+ [171] = PINGROUP(171, qup4, _, _, _, _, _, _),
1820+ [172] = PINGROUP(172, qup4, _, _, _, _, _, _),
1821+ [173] = PINGROUP(173, qup4, _, _, _, _, _, _),
1822+ [174] = PINGROUP(174, qup4, _, _, _, _, _, _),
1823+ [175] = PINGROUP(175, qup4, rgmii_0, _, _, _, _, _),
1824+ [176] = PINGROUP(176, rgmii_0, _, _, _, _, _, _),
1825+ [177] = PINGROUP(177, rgmii_0, _, _, _, _, _, _),
1826+ [178] = PINGROUP(178, rgmii_0, _, _, _, _, _, _),
1827+ [179] = PINGROUP(179, rgmii_0, _, _, _, _, _, _),
1828+ [180] = PINGROUP(180, rgmii_0, _, _, _, _, _, _),
1829+ [181] = PINGROUP(181, rgmii_0, _, _, _, _, _, _),
1830+ [182] = PINGROUP(182, rgmii_0, _, _, _, _, _, _),
1831+ [183] = PINGROUP(183, rgmii_0, _, _, _, _, _, _),
1832+ [184] = PINGROUP(184, rgmii_0, _, _, _, _, _, _),
1833+ [185] = PINGROUP(185, rgmii_0, _, _, _, _, _, _),
1834+ [186] = PINGROUP(186, rgmii_0, _, _, _, _, _, _),
1835+ [187] = PINGROUP(187, rgmii_0, cri_trng0, _, _, _, _, _),
1836+ [188] = PINGROUP(188, rgmii_0, cri_trng1, _, _, _, _, _),
1837+ [189] = PINGROUP(189, prng_rosc0, _, _, _, _, _, egpio),
1838+ [190] = PINGROUP(190, cri_trng, _, _, _, _, _, egpio),
1839+ [191] = PINGROUP(191, prng_rosc1, _, _, _, _, _, egpio),
1840+ [192] = PINGROUP(192, _, _, _, _, _, _, egpio),
1841+ [193] = PINGROUP(193, prng_rosc2, _, _, _, _, _, egpio),
1842+ [194] = PINGROUP(194, prng_rosc3, _, _, _, _, _, egpio),
1843+ [195] = PINGROUP(195, phase_flag, _, qdss_gpio, _, _, _, egpio),
1844+ [196] = PINGROUP(196, phase_flag, _, qdss_gpio, _, _, _, egpio),
1845+ [197] = PINGROUP(197, phase_flag, _, qdss_gpio, _, _, _, egpio),
1846+ [198] = PINGROUP(198, phase_flag, _, qdss_gpio, _, _, _, egpio),
1847+ [199] = PINGROUP(199, _, _, _, _, _, _, egpio),
1848+ [200] = PINGROUP(200, _, _, _, _, _, _, egpio),
1849+ [201] = PINGROUP(201, qdss_gpio, _, _, _, _, _, egpio),
1850+ [202] = PINGROUP(202, phase_flag, _, qdss_gpio, _, _, _, egpio),
1851+ [203] = PINGROUP(203, _, _, _, _, _, _, egpio),
1852+ [204] = PINGROUP(204, _, _, _, _, _, _, egpio),
1853+ [205] = PINGROUP(205, _, _, _, _, _, _, egpio),
1854+ [206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, egpio),
1855+ [207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, egpio),
1856+ [208] = PINGROUP(208, hs1_mi2s, _, _, _, _, _, egpio),
1857+ [209] = PINGROUP(209, hs1_mi2s, _, _, _, _, _, egpio),
1858+ [210] = PINGROUP(210, hs1_mi2s, _, _, _, _, _, egpio),
1859+ [211] = PINGROUP(211, hs1_mi2s, _, _, _, _, _, egpio),
1860+ [212] = PINGROUP(212, mi2s2_sck, qdss_gpio, _, _, _, _, egpio),
1861+ [213] = PINGROUP(213, mi2s2_ws, qdss_gpio, _, _, _, _, egpio),
1862+ [214] = PINGROUP(214, mi2s2_data0, qdss_gpio, ddr_pxi5, _, _, _, egpio),
1863+ [215] = PINGROUP(215, mi2s2_data1, qdss_gpio, emac1_dll0, ddr_pxi5, _, _, egpio),
1864+ [216] = PINGROUP(216, mi2s_mclk1, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio),
1865+ [217] = PINGROUP(217, mi2s_mclk2, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio),
1866+ [218] = PINGROUP(218, hs2_mi2s, emac1_dll1, ddr_pxi6, _, _, _, egpio),
1867+ [219] = PINGROUP(219, hs2_mi2s, phase_flag, _, _, _, _, egpio),
1868+ [220] = PINGROUP(220, lpass_slimbus, mi2s1_sck, phase_flag, _, _, _, egpio),
1869+ [221] = PINGROUP(221, lpass_slimbus, mi2s1_ws, phase_flag, _, _, _, egpio),
1870+ [222] = PINGROUP(222, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, egpio),
1871+ [223] = PINGROUP(223, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, egpio),
1872+ [224] = PINGROUP(224, hs3_mi2s, phase_flag, _, _, _, _, egpio),
1873+ [225] = PINGROUP(225, hs3_mi2s, phase_flag, _, _, _, _, egpio),
1874+ [226] = PINGROUP(226, hs3_mi2s, phase_flag, _, _, _, _, egpio),
1875+ [227] = PINGROUP(227, hs3_mi2s, phase_flag, _, _, _, _, egpio),
1876+ [228] = UFS_RESET(ufs_reset, 0xf1004),
1877+ [229] = UFS_RESET(ufs1_reset, 0xf3004),
1878+ [230] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe8000, 14, 6),
1879+ [231] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe8000, 11, 3),
1880+ [232] = SDC_QDSD_PINGROUP(sdc2_data, 0xe8000, 9, 0),
1881+};
1882+
1883+static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = {
1884+ { 3, 245 }, { 4, 263 }, { 7, 254 }, { 21, 220 }, { 25, 244 },
1885+ { 26, 211 }, { 27, 172 }, { 29, 203 }, { 30, 169 }, { 31, 180 },
1886+ { 32, 181 }, { 33, 182 }, { 36, 206 }, { 39, 246 }, { 40, 183 },
1887+ { 42, 179 }, { 46, 247 }, { 53, 248 }, { 54, 190 }, { 55, 249 },
1888+ { 56, 250 }, { 58, 251 }, { 59, 207 }, { 62, 252 }, { 63, 191 },
1889+ { 64, 192 }, { 65, 193 }, { 69, 253 }, { 73, 255 }, { 84, 256 },
1890+ { 85, 208 }, { 90, 257 }, { 102, 214 }, { 103, 215 }, { 104, 216 },
1891+ { 107, 217 }, { 110, 218 }, { 124, 224 }, { 125, 189 },
1892+ { 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 },
1893+ { 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 },
1894+ { 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 },
1895+ { 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 },
1896+ { 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 },
1897+ { 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 },
1898+ { 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 },
1899+ { 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 },
1900+ { 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 },
1901+ { 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 },
1902+ { 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 },
1903+ { 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 },
1904+ { 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 },
1905+};
1906+
1907+static struct msm_pinctrl_soc_data sc8280xp_pinctrl = {
1908+ .pins = sc8280xp_pins,
1909+ .npins = ARRAY_SIZE(sc8280xp_pins),
1910+ .functions = sc8280xp_functions,
1911+ .nfunctions = ARRAY_SIZE(sc8280xp_functions),
1912+ .groups = sc8280xp_groups,
1913+ .ngroups = ARRAY_SIZE(sc8280xp_groups),
1914+ .ngpios = 230,
1915+ .wakeirq_map = sc8280xp_pdc_map,
1916+ .nwakeirq_map = ARRAY_SIZE(sc8280xp_pdc_map),
1917+ .egpio_func = 7,
1918+};
1919+
1920+static int sc8280xp_pinctrl_probe(struct platform_device *pdev)
1921+{
1922+ return msm_pinctrl_probe(pdev, &sc8280xp_pinctrl);
1923+}
1924+
1925+static const struct of_device_id sc8280xp_pinctrl_of_match[] = {
1926+ { .compatible = "qcom,sc8280xp-tlmm", },
1927+ { },
1928+};
1929+MODULE_DEVICE_TABLE(of, sc8280xp_pinctrl_of_match);
1930+
1931+static struct platform_driver sc8280xp_pinctrl_driver = {
1932+ .driver = {
1933+ .name = "sc8280xp-tlmm",
1934+ .of_match_table = sc8280xp_pinctrl_of_match,
1935+ },
1936+ .probe = sc8280xp_pinctrl_probe,
1937+ .remove = msm_pinctrl_remove,
1938+};
1939+
1940+static int __init sc8280xp_pinctrl_init(void)
1941+{
1942+ return platform_driver_register(&sc8280xp_pinctrl_driver);
1943+}
1944+arch_initcall(sc8280xp_pinctrl_init);
1945+
1946+static void __exit sc8280xp_pinctrl_exit(void)
1947+{
1948+ platform_driver_unregister(&sc8280xp_pinctrl_driver);
1949+}
1950+module_exit(sc8280xp_pinctrl_exit);
1951+
1952+MODULE_DESCRIPTION("Qualcomm SC8280XP TLMM pinctrl driver");
1953+MODULE_LICENSE("GPL");
drivers/pinctrl/qcom/pinctrl-sm6125.c+1−1
@@ -1,4 +1,4 @@
1−//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
1+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22
33 #include <linux/module.h>
44 #include <linux/of.h>
drivers/pinctrl/qcom/pinctrl-sm8450.c+61−45
@@ -46,6 +46,8 @@ · 45 unmodified lines
4646 .mux_bit = 2, \
4747 .pull_bit = 0, \
4848 .drv_bit = 6, \
49+ .egpio_enable = 12, \
50+ .egpio_present = 11, \
4951 .oe_bit = 9, \
5052 .in_bit = 0, \
5153 .out_bit = 1, \
@@ -567,6 +569,7 @@ enum sm8450_functions { · 515 unmodified lines
567569 msm_mux_ddr_pxi2,
568570 msm_mux_ddr_pxi3,
569571 msm_mux_dp_hot,
572+ msm_mux_egpio,
570573 msm_mux_gcc_gp1,
571574 msm_mux_gcc_gp2,
572575 msm_mux_gcc_gp3,
@@ -719,6 +722,17 @@ static const char * const gpio_groups[] = { · 146 unmodified lines
719722 "gpio207", "gpio208", "gpio209",
720723 };
721724
725+static const char * const egpio_groups[] = {
726+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
727+ "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
728+ "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
729+ "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
730+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
731+ "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
732+ "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
733+ "gpio207", "gpio208", "gpio209",
734+};
735+
722736 static const char * const aon_cam_groups[] = {
723737 "gpio108",
724738 };
@@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = { · 560 unmodified lines
12851299 FUNCTION(ddr_pxi2),
12861300 FUNCTION(ddr_pxi3),
12871301 FUNCTION(dp_hot),
1302+ FUNCTION(egpio),
12881303 FUNCTION(gcc_gp1),
12891304 FUNCTION(gcc_gp2),
12901305 FUNCTION(gcc_gp3),
@@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = { · 280 unmodified lines
15711586 [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),
15721587 [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),
15731588 [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),
1574− [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _),
1575− [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),
1576− [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
1577− [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
1578− [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
1579− [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
1580− [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
1581− [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
1582− [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
1583− [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _),
1584− [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),
1585− [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),
1586− [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _),
1587− [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
1588− [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
1589− [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
1590− [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
1591− [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
1592− [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _),
1593− [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _),
1594− [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _),
1595− [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _),
1596− [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _),
1597− [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _),
1598− [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _),
1599− [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
1600− [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
1601− [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _),
1602− [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _),
1603− [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _),
1604− [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _),
1605− [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _),
1606− [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _),
1607− [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _),
1608− [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _),
1609− [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _),
1610− [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _),
1611− [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _),
1612− [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _),
1613− [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _),
1614− [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _),
1615− [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _),
1616− [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _),
1617− [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _),
1618− [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _),
1589+ [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio),
1590+ [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio),
1591+ [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio),
1592+ [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio),
1593+ [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio),
1594+ [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio),
1595+ [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio),
1596+ [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio),
1597+ [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio),
1598+ [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio),
1599+ [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio),
1600+ [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio),
1601+ [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio),
1602+ [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio),
1603+ [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio),
1604+ [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio),
1605+ [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio),
1606+ [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio),
1607+ [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio),
1608+ [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio),
1609+ [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio),
1610+ [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio),
1611+ [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio),
1612+ [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio),
1613+ [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio),
1614+ [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio),
1615+ [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio),
1616+ [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio),
1617+ [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio),
1618+ [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio),
1619+ [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio),
1620+ [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio),
1621+ [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio),
1622+ [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio),
1623+ [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio),
1624+ [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio),
1625+ [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio),
1626+ [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio),
1627+ [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio),
1628+ [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio),
1629+ [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio),
1630+ [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio),
1631+ [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio),
1632+ [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio),
1633+ [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio),
16191634 [210] = UFS_RESET(ufs_reset, 0xde000),
16201635 [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
16211636 [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
@@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = { · 29 unmodified lines
16511666 .ngpios = 211,
16521667 .wakeirq_map = sm8450_pdc_map,
16531668 .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),
1669+ .egpio_func = 9,
16541670 };
16551671
16561672 static int sm8450_tlmm_probe(struct platform_device *pdev)
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c+1−0
@@ -1164,6 +1164,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { · 1163 unmodified lines
11641164 { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
11651165 { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
11661166 { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1167+ { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
11671168 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
11681169 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
11691170 /* pm8950 has 8 GPIOs with holes on 3 */
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c+1−0
@@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) · 960 unmodified lines
961961
962962 static const struct of_device_id pmic_mpp_of_match[] = {
963963 { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 },
964+ { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 },
964965 { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 },
965966 { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 },
966967 { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 },
drivers/pinctrl/renesas/Kconfig+9−2
@@ -37,7 +37,9 @@ config PINCTRL_RENESAS · 36 unmodified lines
3737 select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
3838 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
3939 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
40+ select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
4041 select PINCTRL_RZG2L if ARCH_R9A07G044
42+ select PINCTRL_RZG2L if ARCH_R9A07G054
4143 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
4244 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
4345 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -132,6 +134,10 @@ config PINCTRL_PFC_R8A77961 · 88 unmodified lines
132134 bool "pin control support for R-Car M3-W+" if COMPILE_TEST
133135 select PINCTRL_SH_PFC
134136
137+config PINCTRL_PFC_R8A779F0
138+ bool "pin control support for R-Car S4-8" if COMPILE_TEST
139+ select PINCTRL_SH_PFC
140+
135141 config PINCTRL_PFC_R8A7792
136142 bool "pin control support for R-Car V2H" if COMPILE_TEST
137143 select PINCTRL_SH_PFC
@@ -178,14 +184,15 @@ config PINCTRL_RZA2 · 40 unmodified lines
178184 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
179185
180186 config PINCTRL_RZG2L
181− bool "pin control support for RZ/G2L" if COMPILE_TEST
187+ bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST
182188 depends on OF
183189 select GPIOLIB
184190 select GENERIC_PINCTRL_GROUPS
185191 select GENERIC_PINMUX_FUNCTIONS
186192 select GENERIC_PINCONF
187193 help
188− This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
194+ This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}
195+ platforms.
189196
190197 config PINCTRL_PFC_R8A77470
191198 bool "pin control support for RZ/G1C" if COMPILE_TEST
drivers/pinctrl/renesas/Makefile+1−0
@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o · 29 unmodified lines
3030 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
3131 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
3232 obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
33+obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
3334 obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
3435 obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
3536 obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
drivers/pinctrl/renesas/core.c+199−20
@@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = { · 635 unmodified lines
636636 .data = &r8a779a0_pinmux_info,
637637 },
638638 #endif
639+#ifdef CONFIG_PINCTRL_PFC_R8A779F0
640+ {
641+ .compatible = "renesas,pfc-r8a779f0",
642+ .data = &r8a779f0_pinmux_info,
643+ },
644+#endif
639645 #ifdef CONFIG_PINCTRL_PFC_SH73A0
640646 {
641647 .compatible = "renesas,pfc-sh73a0",
@@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } · 99 unmodified lines
741747
742748 #ifdef DEBUG
743749 #define SH_PFC_MAX_REGS 300
744−#define SH_PFC_MAX_ENUMS 3000
750+#define SH_PFC_MAX_ENUMS 5000
745751
746752 static unsigned int sh_pfc_errors __initdata;
747753 static unsigned int sh_pfc_warnings __initdata;
754+static bool sh_pfc_bias_done __initdata;
755+static bool sh_pfc_drive_done __initdata;
756+static bool sh_pfc_power_done __initdata;
748757 static struct {
749758 u32 reg;
750759 u32 bits;
@@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata; · 7 unmodified lines
758767 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
759768 sh_pfc_errors++; \
760769 } while (0)
770+
771+#define sh_pfc_err_once(type, fmt, ...) \
772+ do { \
773+ if (!sh_pfc_ ## type ## _done) { \
774+ sh_pfc_ ## type ## _done = true; \
775+ sh_pfc_err(fmt, ##__VA_ARGS__); \
776+ } \
777+ } while (0)
778+
761779 #define sh_pfc_warn(fmt, ...) \
762780 do { \
763781 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
@@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n) · 13 unmodified lines
777795
778796 static bool __init same_name(const char *a, const char *b)
779797 {
780− if (!a || !b)
781− return false;
782−
783− return !strcmp(a, b);
798+ return a && b && !strcmp(a, b);
784799 }
785800
786801 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
@@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, · 52 unmodified lines
839854 }
840855 }
841856
842−static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
843− u32 reg, unsigned int pin)
857+static const struct sh_pfc_pin __init *sh_pfc_find_pin(
858+ const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
844859 {
845860 const char *drvname = info->name;
846861 unsigned int i;
847862
848863 if (pin == SH_PFC_PIN_NONE)
849− return;
864+ return NULL;
850865
851866 for (i = 0; i < info->nr_pins; i++) {
852867 if (pin == info->pins[i].pin)
853− return;
868+ return &info->pins[i];
854869 }
855870
856871 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
872+ return NULL;
857873 }
858874
859875 static void __init sh_pfc_check_cfg_reg(const char *drvname,
@@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, · 5 unmodified lines
865881 GENMASK(cfg_reg->reg_width - 1, 0));
866882
867883 if (cfg_reg->field_width) {
868− n = cfg_reg->reg_width / cfg_reg->field_width;
884+ fw = cfg_reg->field_width;
885+ n = (cfg_reg->reg_width / fw) << fw;
869886 /* Skip field checks (done at build time) */
870887 goto check_enum_ids;
871888 }
@@ -893,6 +910,8 @@ check_enum_ids: · 21 unmodified lines
893910 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
894911 const struct pinmux_drive_reg *drive)
895912 {
913+ const char *drvname = info->name;
914+ const struct sh_pfc_pin *pin;
896915 unsigned int i;
897916
898917 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
@@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, · 6 unmodified lines
905924 GENMASK(field->offset + field->size - 1,
906925 field->offset));
907926
908− sh_pfc_check_pin(info, drive->reg, field->pin);
927+ pin = sh_pfc_find_pin(info, drive->reg, field->pin);
928+ if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
929+ sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
930+ drive->reg, i, pin->name);
909931 }
910932 }
911933
912934 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
913935 const struct pinmux_bias_reg *bias)
914936 {
937+ const char *drvname = info->name;
938+ const struct sh_pfc_pin *pin;
915939 unsigned int i;
916940 u32 bits;
917941
@@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, · 5 unmodified lines
923947 sh_pfc_check_reg(info->name, bias->puen, bits);
924948 if (bias->pud)
925949 sh_pfc_check_reg(info->name, bias->pud, bits);
926− for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
927− sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
950+ for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
951+ pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
952+ if (!pin)
953+ continue;
954+
955+ if (bias->puen && bias->pud) {
956+ /*
957+ * Pull-enable and pull-up/down control registers
958+ * As some SoCs have pins that support only pull-up
959+ * or pull-down, we just check for one of them
960+ */
961+ if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
962+ sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
963+ bias->puen, i, pin->name);
964+ } else if (bias->puen) {
965+ /* Pull-up control register only */
966+ if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
967+ sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
968+ bias->puen, i, pin->name);
969+ } else if (bias->pud) {
970+ /* Pull-down control register only */
971+ if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
972+ sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
973+ bias->pud, i, pin->name);
974+ }
975+ }
976+}
977+
978+static void __init sh_pfc_compare_groups(const char *drvname,
979+ const struct sh_pfc_pin_group *a,
980+ const struct sh_pfc_pin_group *b)
981+{
982+ unsigned int i;
983+ size_t len;
984+
985+ if (same_name(a->name, b->name))
986+ sh_pfc_err("group %s: name conflict\n", a->name);
987+
988+ if (a->nr_pins > b->nr_pins)
989+ swap(a, b);
990+
991+ len = a->nr_pins * sizeof(a->pins[0]);
992+ for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
993+ if (a->pins == b->pins + i || a->mux == b->mux + i ||
994+ memcmp(a->pins, b->pins + i, len) ||
995+ memcmp(a->mux, b->mux + i, len))
996+ continue;
997+
998+ if (a->nr_pins == b->nr_pins)
999+ sh_pfc_warn("group %s can be an alias for %s\n",
1000+ a->name, b->name);
1001+ else
1002+ sh_pfc_warn("group %s is a subset of %s\n", a->name,
1003+ b->name);
1004+ }
9281005 }
9291006
9301007 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
9311008 {
1009+ const struct pinmux_drive_reg *drive_regs = info->drive_regs;
9321010 const struct pinmux_bias_reg *bias_regs = info->bias_regs;
9331011 const char *drvname = info->name;
9341012 unsigned int *refcnts;
@@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 2 unmodified lines
9371015 pr_info("sh_pfc: Checking %s\n", drvname);
9381016 sh_pfc_num_regs = 0;
9391017 sh_pfc_num_enums = 0;
1018+ sh_pfc_bias_done = false;
1019+ sh_pfc_drive_done = false;
1020+ sh_pfc_power_done = false;
9401021
9411022 /* Check pins */
9421023 for (i = 0; i < info->nr_pins; i++) {
9431024 const struct sh_pfc_pin *pin = &info->pins[i];
1025+ unsigned int x;
9441026
9451027 if (!pin->name) {
9461028 sh_pfc_err("empty pin %u\n", i);
@@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 15 unmodified lines
9621044 pin->name, pin2->name,
9631045 pin->enum_id);
9641046 }
1047+
1048+ if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
1049+ if (!info->ops || !info->ops->get_bias ||
1050+ !info->ops->set_bias)
1051+ sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
1052+
1053+ if (!bias_regs &&
1054+ (!info->ops || !info->ops->pin_to_portcr))
1055+ sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
1056+ }
1057+
1058+ if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
1059+ const struct pinmux_bias_reg *bias_reg =
1060+ rcar_pin_to_bias_reg(info, pin->pin, &x);
1061+
1062+ if (!bias_reg ||
1063+ ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
1064+ !bias_reg->puen))
1065+ sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
1066+ pin->name);
1067+
1068+ if (!bias_reg ||
1069+ ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
1070+ !bias_reg->pud))
1071+ sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
1072+ pin->name);
1073+ }
1074+
1075+ if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
1076+ if (!drive_regs) {
1077+ sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
1078+ } else {
1079+ for (j = 0; drive_regs[j / 8].reg; j++) {
1080+ if (!drive_regs[j / 8].fields[j % 8].pin &&
1081+ !drive_regs[j / 8].fields[j % 8].offset &&
1082+ !drive_regs[j / 8].fields[j % 8].size)
1083+ continue;
1084+
1085+ if (drive_regs[j / 8].fields[j % 8].pin == pin->pin)
1086+ break;
1087+ }
1088+
1089+ if (!drive_regs[j / 8].reg)
1090+ sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
1091+ pin->name);
1092+ }
1093+ }
1094+
1095+ if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
1096+ if (!info->ops || !info->ops->pin_to_pocctrl)
1097+ sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
1098+ else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
1099+ sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
1100+ pin->name);
1101+ } else if (info->ops && info->ops->pin_to_pocctrl &&
1102+ info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
1103+ sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
1104+ pin->name);
1105+ }
9651106 }
9661107
9671108 /* Check groups and functions */
@@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 35 unmodified lines
10031144 sh_pfc_err("empty group %u\n", i);
10041145 continue;
10051146 }
1006− for (j = 0; j < i; j++) {
1007− if (same_name(group->name, info->groups[j].name))
1008− sh_pfc_err("group %s: name conflict\n",
1009− group->name);
1010− }
1147+ for (j = 0; j < i; j++)
1148+ sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1149+
10111150 if (!refcnts[i])
10121151 sh_pfc_err("orphan group %s\n", group->name);
10131152 else if (refcnts[i] > 1)
@@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 8 unmodified lines
10221161 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
10231162
10241163 /* Check drive strength registers */
1025− for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
1026− sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
1164+ for (i = 0; drive_regs && drive_regs[i].reg; i++)
1165+ sh_pfc_check_drive_reg(info, &drive_regs[i]);
1166+
1167+ for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) {
1168+ if (!drive_regs[i / 8].fields[i % 8].pin &&
1169+ !drive_regs[i / 8].fields[i % 8].offset &&
1170+ !drive_regs[i / 8].fields[i % 8].size)
1171+ continue;
1172+
1173+ for (j = 0; j < i; j++) {
1174+ if (drive_regs[i / 8].fields[i % 8].pin ==
1175+ drive_regs[j / 8].fields[j % 8].pin &&
1176+ drive_regs[j / 8].fields[j % 8].offset &&
1177+ drive_regs[j / 8].fields[j % 8].size) {
1178+ sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n",
1179+ drive_regs[i / 8].reg, i % 8,
1180+ drive_regs[j / 8].reg, j % 8);
1181+ }
1182+ }
1183+ }
10271184
10281185 /* Check bias registers */
10291186 for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
10301187 sh_pfc_check_bias_reg(info, &bias_regs[i]);
10311188
1189+ for (i = 0; bias_regs &&
1190+ (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) {
1191+ if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE)
1192+ continue;
1193+
1194+ for (j = 0; j < i; j++) {
1195+ if (bias_regs[i / 32].pins[i % 32] !=
1196+ bias_regs[j / 32].pins[j % 32])
1197+ continue;
1198+
1199+ if (bias_regs[i / 32].puen && bias_regs[j / 32].puen)
1200+ sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
1201+ bias_regs[i / 32].puen, i % 32,
1202+ bias_regs[j / 32].puen, j % 32);
1203+ if (bias_regs[i / 32].pud && bias_regs[j / 32].pud)
1204+ sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n",
1205+ bias_regs[i / 32].pud, i % 32,
1206+ bias_regs[j / 32].pud, j % 32);
1207+ }
1208+
1209+ }
1210+
10321211 /* Check ioctrl registers */
10331212 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
10341213 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
drivers/pinctrl/renesas/pfc-emev2.c+17−54
@@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = { · 748 unmodified lines
749749 CF_CDB2_MARK,
750750 };
751751
752−static const unsigned int cf_data8_pins[] = {
753− /* CF_D[0:7] */
754− 77, 78, 79, 80,
755− 81, 82, 83, 84,
756−};
757−static const unsigned int cf_data8_mux[] = {
758− CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
759− CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
760−};
761−static const unsigned int cf_data16_pins[] = {
752+static const unsigned int cf_data_pins[] = {
762753 /* CF_D[0:15] */
763754 77, 78, 79, 80,
764755 81, 82, 83, 84,
765756 85, 86, 87, 88,
766757 89, 90, 91, 92,
767758 };
768−static const unsigned int cf_data16_mux[] = {
759+static const unsigned int cf_data_mux[] = {
769760 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
770761 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
771762 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
@@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = { · 123 unmodified lines
895886 SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
896887 };
897888
898−static const unsigned int sdi0_data1_pins[] = {
899− /* SDI0_DATA[0] */
900− 53,
901−};
902−static const unsigned int sdi0_data1_mux[] = {
903− SDI0_DATA0_MARK,
904−};
905−static const unsigned int sdi0_data4_pins[] = {
906− /* SDI0_DATA[0:3] */
907− 53, 54, 55, 56,
908−};
909−static const unsigned int sdi0_data4_mux[] = {
910− SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
911−};
912−static const unsigned int sdi0_data8_pins[] = {
889+static const unsigned int sdi0_data_pins[] = {
913890 /* SDI0_DATA[0:7] */
914891 53, 54, 55, 56,
915892 57, 58, 59, 60
916893 };
917−static const unsigned int sdi0_data8_mux[] = {
894+static const unsigned int sdi0_data_mux[] = {
918895 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
919896 SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
920897 };
@@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = { · 7 unmodified lines
928905 SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
929906 };
930907
931−static const unsigned int sdi1_data1_pins[] = {
932− /* SDI1_DATA[0] */
933− 64,
934−};
935−static const unsigned int sdi1_data1_mux[] = {
936− SDI1_DATA0_MARK,
937−};
938−static const unsigned int sdi1_data4_pins[] = {
908+static const unsigned int sdi1_data_pins[] = {
939909 /* SDI1_DATA[0:3] */
940910 64, 65, 66, 67,
941911 };
942−static const unsigned int sdi1_data4_mux[] = {
912+static const unsigned int sdi1_data_mux[] = {
943913 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
944914 };
945915
@@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = { · 6 unmodified lines
952922 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
953923 };
954924
955−static const unsigned int sdi2_data1_pins[] = {
956− /* SDI2_DATA[0] */
957− 89,
958−};
959−static const unsigned int sdi2_data1_mux[] = {
960− SDI2_DATA0_MARK,
961−};
962−static const unsigned int sdi2_data4_pins[] = {
925+static const unsigned int sdi2_data_pins[] = {
963926 /* SDI2_DATA[0:3] */
964927 89, 90, 91, 92,
965928 };
966−static const unsigned int sdi2_data4_mux[] = {
929+static const unsigned int sdi2_data_mux[] = {
967930 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
968931 };
969932
@@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 161 unmodified lines
11311094 SH_PFC_PIN_GROUP(cam),
11321095
11331096 SH_PFC_PIN_GROUP(cf_ctrl),
1134− SH_PFC_PIN_GROUP(cf_data8),
1135− SH_PFC_PIN_GROUP(cf_data16),
1097+ BUS_DATA_PIN_GROUP(cf_data, 8),
1098+ BUS_DATA_PIN_GROUP(cf_data, 16),
11361099
11371100 SH_PFC_PIN_GROUP(dtv_a),
11381101 SH_PFC_PIN_GROUP(dtv_b),
@@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 22 unmodified lines
11611124 SH_PFC_PIN_GROUP(sd_cki),
11621125
11631126 SH_PFC_PIN_GROUP(sdi0_ctrl),
1164− SH_PFC_PIN_GROUP(sdi0_data1),
1165− SH_PFC_PIN_GROUP(sdi0_data4),
1166− SH_PFC_PIN_GROUP(sdi0_data8),
1127+ BUS_DATA_PIN_GROUP(sdi0_data, 1),
1128+ BUS_DATA_PIN_GROUP(sdi0_data, 4),
1129+ BUS_DATA_PIN_GROUP(sdi0_data, 8),
11671130
11681131 SH_PFC_PIN_GROUP(sdi1_ctrl),
1169− SH_PFC_PIN_GROUP(sdi1_data1),
1170− SH_PFC_PIN_GROUP(sdi1_data4),
1132+ BUS_DATA_PIN_GROUP(sdi1_data, 1),
1133+ BUS_DATA_PIN_GROUP(sdi1_data, 4),
11711134
11721135 SH_PFC_PIN_GROUP(sdi2_ctrl),
1173− SH_PFC_PIN_GROUP(sdi2_data1),
1174− SH_PFC_PIN_GROUP(sdi2_data4),
1136+ BUS_DATA_PIN_GROUP(sdi2_data, 1),
1137+ BUS_DATA_PIN_GROUP(sdi2_data, 4),
11751138
11761139 SH_PFC_PIN_GROUP(tp33),
11771140
drivers/pinctrl/renesas/pfc-r8a73a4.c+24−73
@@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55); · 1448 unmodified lines
14491449 IRQC_PINS_MUX(328, 56);
14501450 IRQC_PINS_MUX(329, 57);
14511451 /* - MMCIF0 ----------------------------------------------------------------- */
1452−static const unsigned int mmc0_data1_pins[] = {
1453− /* D[0] */
1454− 164,
1455−};
1456−static const unsigned int mmc0_data1_mux[] = {
1457− MMCD0_0_MARK,
1458−};
1459−static const unsigned int mmc0_data4_pins[] = {
1460− /* D[0:3] */
1461− 164, 165, 166, 167,
1462−};
1463−static const unsigned int mmc0_data4_mux[] = {
1464− MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1465−};
1466−static const unsigned int mmc0_data8_pins[] = {
1452+static const unsigned int mmc0_data_pins[] = {
14671453 /* D[0:7] */
14681454 164, 165, 166, 167, 168, 169, 170, 171,
14691455 };
1470−static const unsigned int mmc0_data8_mux[] = {
1456+static const unsigned int mmc0_data_mux[] = {
14711457 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
14721458 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
14731459 };
@@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = { · 5 unmodified lines
14791465 MMCCMD0_MARK, MMCCLK0_MARK,
14801466 };
14811467 /* - MMCIF1 ----------------------------------------------------------------- */
1482−static const unsigned int mmc1_data1_pins[] = {
1483− /* D[0] */
1484− 199,
1485−};
1486−static const unsigned int mmc1_data1_mux[] = {
1487− MMCD1_0_MARK,
1488−};
1489−static const unsigned int mmc1_data4_pins[] = {
1490− /* D[0:3] */
1491− 199, 198, 197, 196,
1492−};
1493−static const unsigned int mmc1_data4_mux[] = {
1494− MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1495−};
1496−static const unsigned int mmc1_data8_pins[] = {
1468+static const unsigned int mmc1_data_pins[] = {
14971469 /* D[0:7] */
14981470 199, 198, 197, 196, 195, 194, 193, 192,
14991471 };
1500−static const unsigned int mmc1_data8_mux[] = {
1472+static const unsigned int mmc1_data_mux[] = {
15011473 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
15021474 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
15031475 };
@@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = { · 200 unmodified lines
17041676 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
17051677 };
17061678 /* - SDHI0 ------------------------------------------------------------------ */
1707−static const unsigned int sdhi0_data1_pins[] = {
1708− /* D0 */
1709− 302,
1710−};
1711−static const unsigned int sdhi0_data1_mux[] = {
1712− SDHID0_0_MARK,
1713−};
1714−static const unsigned int sdhi0_data4_pins[] = {
1679+static const unsigned int sdhi0_data_pins[] = {
17151680 /* D[0:3] */
17161681 302, 303, 304, 305,
17171682 };
1718−static const unsigned int sdhi0_data4_mux[] = {
1683+static const unsigned int sdhi0_data_mux[] = {
17191684 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
17201685 };
17211686 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
17401705 SDHIWP0_MARK,
17411706 };
17421707 /* - SDHI1 ------------------------------------------------------------------ */
1743−static const unsigned int sdhi1_data1_pins[] = {
1744− /* D0 */
1745− 289,
1746−};
1747−static const unsigned int sdhi1_data1_mux[] = {
1748− SDHID1_0_MARK,
1749−};
1750−static const unsigned int sdhi1_data4_pins[] = {
1708+static const unsigned int sdhi1_data_pins[] = {
17511709 /* D[0:3] */
17521710 289, 290, 291, 292,
17531711 };
1754−static const unsigned int sdhi1_data4_mux[] = {
1712+static const unsigned int sdhi1_data_mux[] = {
17551713 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
17561714 };
17571715 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = { · 4 unmodified lines
17621720 SDHICLK1_MARK, SDHICMD1_MARK,
17631721 };
17641722 /* - SDHI2 ------------------------------------------------------------------ */
1765−static const unsigned int sdhi2_data1_pins[] = {
1766− /* D0 */
1767− 295,
1768−};
1769−static const unsigned int sdhi2_data1_mux[] = {
1770− SDHID2_0_MARK,
1771−};
1772−static const unsigned int sdhi2_data4_pins[] = {
1723+static const unsigned int sdhi2_data_pins[] = {
17731724 /* D[0:3] */
17741725 295, 296, 297, 298,
17751726 };
1776−static const unsigned int sdhi2_data4_mux[] = {
1727+static const unsigned int sdhi2_data_mux[] = {
17771728 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
17781729 };
17791730 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 63 unmodified lines
18431794 SH_PFC_PIN_GROUP(irqc_irq55),
18441795 SH_PFC_PIN_GROUP(irqc_irq56),
18451796 SH_PFC_PIN_GROUP(irqc_irq57),
1846− SH_PFC_PIN_GROUP(mmc0_data1),
1847− SH_PFC_PIN_GROUP(mmc0_data4),
1848− SH_PFC_PIN_GROUP(mmc0_data8),
1797+ BUS_DATA_PIN_GROUP(mmc0_data, 1),
1798+ BUS_DATA_PIN_GROUP(mmc0_data, 4),
1799+ BUS_DATA_PIN_GROUP(mmc0_data, 8),
18491800 SH_PFC_PIN_GROUP(mmc0_ctrl),
1850− SH_PFC_PIN_GROUP(mmc1_data1),
1851− SH_PFC_PIN_GROUP(mmc1_data4),
1852− SH_PFC_PIN_GROUP(mmc1_data8),
1801+ BUS_DATA_PIN_GROUP(mmc1_data, 1),
1802+ BUS_DATA_PIN_GROUP(mmc1_data, 4),
1803+ BUS_DATA_PIN_GROUP(mmc1_data, 8),
18531804 SH_PFC_PIN_GROUP(mmc1_ctrl),
18541805 SH_PFC_PIN_GROUP(scifa0_data),
18551806 SH_PFC_PIN_GROUP(scifa0_clk),
@@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 22 unmodified lines
18781829 SH_PFC_PIN_GROUP(scifb3_data_b),
18791830 SH_PFC_PIN_GROUP(scifb3_clk_b),
18801831 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1881− SH_PFC_PIN_GROUP(sdhi0_data1),
1882− SH_PFC_PIN_GROUP(sdhi0_data4),
1832+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1833+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
18831834 SH_PFC_PIN_GROUP(sdhi0_ctrl),
18841835 SH_PFC_PIN_GROUP(sdhi0_cd),
18851836 SH_PFC_PIN_GROUP(sdhi0_wp),
1886− SH_PFC_PIN_GROUP(sdhi1_data1),
1887− SH_PFC_PIN_GROUP(sdhi1_data4),
1837+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
1838+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
18881839 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1889− SH_PFC_PIN_GROUP(sdhi2_data1),
1890− SH_PFC_PIN_GROUP(sdhi2_data4),
1840+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
1841+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
18911842 SH_PFC_PIN_GROUP(sdhi2_ctrl),
18921843 };
18931844
@@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = { · 761 unmodified lines
26552606 0x00002000, 0x00003000, 0x00003000,
26562607 };
26572608
2658−static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
2609+static int r8a73a4_pin_to_portcr(unsigned int pin)
26592610 {
2660− return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2611+ return r8a73a4_portcr_offsets[pin >> 5] + pin;
26612612 }
26622613
26632614 static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
drivers/pinctrl/renesas/pfc-r8a7740.c+48−234
@@ -1638,33 +1638,14 @@ static const struct sh_pfc_pin pinmux_pins[] = { · 1637 unmodified lines
16381638 };
16391639
16401640 /* - BSC -------------------------------------------------------------------- */
1641−static const unsigned int bsc_data8_pins[] = {
1642− /* D[0:7] */
1643− 157, 156, 155, 154, 153, 152, 151, 150,
1644−};
1645−static const unsigned int bsc_data8_mux[] = {
1646− D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1647− D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1648−};
1649−static const unsigned int bsc_data16_pins[] = {
1650− /* D[0:15] */
1651− 157, 156, 155, 154, 153, 152, 151, 150,
1652− 149, 148, 147, 146, 145, 144, 143, 142,
1653−};
1654−static const unsigned int bsc_data16_mux[] = {
1655− D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1656− D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1657− D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1658− D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1659−};
1660−static const unsigned int bsc_data32_pins[] = {
1641+static const unsigned int bsc_data_pins[] = {
16611642 /* D[0:31] */
16621643 157, 156, 155, 154, 153, 152, 151, 150,
16631644 149, 148, 147, 146, 145, 144, 143, 142,
16641645 171, 170, 169, 168, 167, 166, 173, 172,
16651646 165, 164, 163, 162, 161, 160, 159, 158,
16661647 };
1667−static const unsigned int bsc_data32_mux[] = {
1648+static const unsigned int bsc_data_mux[] = {
16681649 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
16691650 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
16701651 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
@@ -1723,25 +1704,11 @@ static const unsigned int bsc_cs6a_pins[] = { · 52 unmodified lines
17231704 static const unsigned int bsc_cs6a_mux[] = {
17241705 CS6A_MARK,
17251706 };
1726−static const unsigned int bsc_rd_we8_pins[] = {
1727− /* RD, WE[0] */
1728− 115, 113,
1729−};
1730−static const unsigned int bsc_rd_we8_mux[] = {
1731− RD_FSC_MARK, WE0_FWE_MARK,
1732−};
1733−static const unsigned int bsc_rd_we16_pins[] = {
1734− /* RD, WE[0:1] */
1735− 115, 113, 112,
1736−};
1737−static const unsigned int bsc_rd_we16_mux[] = {
1738− RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1739−};
1740−static const unsigned int bsc_rd_we32_pins[] = {
1707+static const unsigned int bsc_rd_we_pins[] = {
17411708 /* RD, WE[0:3] */
17421709 115, 113, 112, 108, 107,
17431710 };
1744−static const unsigned int bsc_rd_we32_mux[] = {
1711+static const unsigned int bsc_rd_we_mux[] = {
17451712 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
17461713 };
17471714 static const unsigned int bsc_bs_pins[] = {
@@ -2064,58 +2031,6 @@ IRQC_PINS_MUX(31, 0, 41); · 316 unmodified lines
20642031 IRQC_PINS_MUX(31, 1, 167);
20652032
20662033 /* - LCD0 ------------------------------------------------------------------- */
2067−static const unsigned int lcd0_data8_pins[] = {
2068− /* D[0:7] */
2069− 58, 57, 56, 55, 54, 53, 52, 51,
2070−};
2071−static const unsigned int lcd0_data8_mux[] = {
2072− LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2073− LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2074−};
2075−static const unsigned int lcd0_data9_pins[] = {
2076− /* D[0:8] */
2077− 58, 57, 56, 55, 54, 53, 52, 51,
2078− 50,
2079−};
2080−static const unsigned int lcd0_data9_mux[] = {
2081− LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2082− LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2083− LCD0_D8_MARK,
2084−};
2085−static const unsigned int lcd0_data12_pins[] = {
2086− /* D[0:11] */
2087− 58, 57, 56, 55, 54, 53, 52, 51,
2088− 50, 49, 48, 47,
2089−};
2090−static const unsigned int lcd0_data12_mux[] = {
2091− LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2092− LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2093− LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2094−};
2095−static const unsigned int lcd0_data16_pins[] = {
2096− /* D[0:15] */
2097− 58, 57, 56, 55, 54, 53, 52, 51,
2098− 50, 49, 48, 47, 46, 45, 44, 43,
2099−};
2100−static const unsigned int lcd0_data16_mux[] = {
2101− LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2102− LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2103− LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2104− LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2105−};
2106−static const unsigned int lcd0_data18_pins[] = {
2107− /* D[0:17] */
2108− 58, 57, 56, 55, 54, 53, 52, 51,
2109− 50, 49, 48, 47, 46, 45, 44, 43,
2110− 42, 41,
2111−};
2112−static const unsigned int lcd0_data18_mux[] = {
2113− LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2114− LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2115− LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2116− LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2117− LCD0_D16_MARK, LCD0_D17_MARK,
2118−};
21192034 static const unsigned int lcd0_data24_0_pins[] = {
21202035 /* D[0:23] */
21212036 58, 57, 56, 55, 54, 53, 52, 51,
@@ -2182,65 +2097,13 @@ static const unsigned int lcd0_sys_mux[] = { · 60 unmodified lines
21822097 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
21832098 };
21842099 /* - LCD1 ------------------------------------------------------------------- */
2185−static const unsigned int lcd1_data8_pins[] = {
2186− /* D[0:7] */
2187− 4, 3, 2, 1, 0, 91, 92, 23,
2188−};
2189−static const unsigned int lcd1_data8_mux[] = {
2190− LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2191− LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2192−};
2193−static const unsigned int lcd1_data9_pins[] = {
2194− /* D[0:8] */
2195− 4, 3, 2, 1, 0, 91, 92, 23,
2196− 93,
2197−};
2198−static const unsigned int lcd1_data9_mux[] = {
2199− LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2200− LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2201− LCD1_D8_MARK,
2202−};
2203−static const unsigned int lcd1_data12_pins[] = {
2204− /* D[0:11] */
2205− 4, 3, 2, 1, 0, 91, 92, 23,
2206− 93, 94, 21, 201,
2207−};
2208−static const unsigned int lcd1_data12_mux[] = {
2209− LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2210− LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2211− LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2212−};
2213−static const unsigned int lcd1_data16_pins[] = {
2214− /* D[0:15] */
2215− 4, 3, 2, 1, 0, 91, 92, 23,
2216− 93, 94, 21, 201, 200, 199, 196, 195,
2217−};
2218−static const unsigned int lcd1_data16_mux[] = {
2219− LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2220− LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2221− LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2222− LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2223−};
2224−static const unsigned int lcd1_data18_pins[] = {
2225− /* D[0:17] */
2226− 4, 3, 2, 1, 0, 91, 92, 23,
2227− 93, 94, 21, 201, 200, 199, 196, 195,
2228− 194, 193,
2229−};
2230−static const unsigned int lcd1_data18_mux[] = {
2231− LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2232− LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2233− LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2234− LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2235− LCD1_D16_MARK, LCD1_D17_MARK,
2236−};
2237−static const unsigned int lcd1_data24_pins[] = {
2100+static const unsigned int lcd1_data_pins[] = {
22382101 /* D[0:23] */
22392102 4, 3, 2, 1, 0, 91, 92, 23,
22402103 93, 94, 21, 201, 200, 199, 196, 195,
22412104 194, 193, 198, 197, 75, 74, 15, 14,
22422105 };
2243−static const unsigned int lcd1_data24_mux[] = {
2106+static const unsigned int lcd1_data_mux[] = {
22442107 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
22452108 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
22462109 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
@@ -2277,25 +2140,11 @@ static const unsigned int lcd1_sys_mux[] = { · 30 unmodified lines
22772140 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
22782141 };
22792142 /* - MMCIF ------------------------------------------------------------------ */
2280−static const unsigned int mmc0_data1_0_pins[] = {
2281− /* D[0] */
2282− 68,
2283−};
2284−static const unsigned int mmc0_data1_0_mux[] = {
2285− MMC0_D0_PORT68_MARK,
2286−};
2287−static const unsigned int mmc0_data4_0_pins[] = {
2288− /* D[0:3] */
2289− 68, 69, 70, 71,
2290−};
2291−static const unsigned int mmc0_data4_0_mux[] = {
2292− MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2293−};
2294−static const unsigned int mmc0_data8_0_pins[] = {
2143+static const unsigned int mmc0_data_0_pins[] = {
22952144 /* D[0:7] */
22962145 68, 69, 70, 71, 72, 73, 74, 75,
22972146 };
2298−static const unsigned int mmc0_data8_0_mux[] = {
2147+static const unsigned int mmc0_data_0_mux[] = {
22992148 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
23002149 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
23012150 };
@@ -2307,25 +2156,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = { · 5 unmodified lines
23072156 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
23082157 };
23092158
2310−static const unsigned int mmc0_data1_1_pins[] = {
2311− /* D[0] */
2312− 149,
2313−};
2314−static const unsigned int mmc0_data1_1_mux[] = {
2315− MMC1_D0_PORT149_MARK,
2316−};
2317−static const unsigned int mmc0_data4_1_pins[] = {
2318− /* D[0:3] */
2319− 149, 148, 147, 146,
2320−};
2321−static const unsigned int mmc0_data4_1_mux[] = {
2322− MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2323−};
2324−static const unsigned int mmc0_data8_1_pins[] = {
2159+static const unsigned int mmc0_data_1_pins[] = {
23252160 /* D[0:7] */
23262161 149, 148, 147, 146, 145, 144, 143, 142,
23272162 };
2328−static const unsigned int mmc0_data8_1_mux[] = {
2163+static const unsigned int mmc0_data_1_mux[] = {
23292164 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
23302165 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
23312166 };
@@ -2591,18 +2426,11 @@ static const unsigned int scifb_ctrl_1_mux[] = { · 259 unmodified lines
25912426 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
25922427 };
25932428 /* - SDHI0 ------------------------------------------------------------------ */
2594−static const unsigned int sdhi0_data1_pins[] = {
2595− /* D0 */
2596− 77,
2597−};
2598−static const unsigned int sdhi0_data1_mux[] = {
2599− SDHI0_D0_MARK,
2600−};
2601−static const unsigned int sdhi0_data4_pins[] = {
2429+static const unsigned int sdhi0_data_pins[] = {
26022430 /* D[0:3] */
26032431 77, 78, 79, 80,
26042432 };
2605−static const unsigned int sdhi0_data4_mux[] = {
2433+static const unsigned int sdhi0_data_mux[] = {
26062434 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
26072435 };
26082436 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -2627,18 +2455,11 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
26272455 SDHI0_WP_MARK,
26282456 };
26292457 /* - SDHI1 ------------------------------------------------------------------ */
2630−static const unsigned int sdhi1_data1_pins[] = {
2631− /* D0 */
2632− 68,
2633−};
2634−static const unsigned int sdhi1_data1_mux[] = {
2635− SDHI1_D0_MARK,
2636−};
2637−static const unsigned int sdhi1_data4_pins[] = {
2458+static const unsigned int sdhi1_data_pins[] = {
26382459 /* D[0:3] */
26392460 68, 69, 70, 71,
26402461 };
2641−static const unsigned int sdhi1_data4_mux[] = {
2462+static const unsigned int sdhi1_data_mux[] = {
26422463 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
26432464 };
26442465 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -2663,18 +2484,11 @@ static const unsigned int sdhi1_wp_mux[] = { · 18 unmodified lines
26632484 SDHI1_WP_MARK,
26642485 };
26652486 /* - SDHI2 ------------------------------------------------------------------ */
2666−static const unsigned int sdhi2_data1_pins[] = {
2667− /* D0 */
2668− 205,
2669−};
2670−static const unsigned int sdhi2_data1_mux[] = {
2671− SDHI2_D0_MARK,
2672−};
2673−static const unsigned int sdhi2_data4_pins[] = {
2487+static const unsigned int sdhi2_data_pins[] = {
26742488 /* D[0:3] */
26752489 205, 206, 207, 208,
26762490 };
2677−static const unsigned int sdhi2_data4_mux[] = {
2491+static const unsigned int sdhi2_data_mux[] = {
26782492 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
26792493 };
26802494 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -2750,9 +2564,9 @@ static const unsigned int tpu0_to3_mux[] = { · 69 unmodified lines
27502564 };
27512565
27522566 static const struct sh_pfc_pin_group pinmux_groups[] = {
2753− SH_PFC_PIN_GROUP(bsc_data8),
2754− SH_PFC_PIN_GROUP(bsc_data16),
2755− SH_PFC_PIN_GROUP(bsc_data32),
2567+ BUS_DATA_PIN_GROUP(bsc_data, 8),
2568+ BUS_DATA_PIN_GROUP(bsc_data, 16),
2569+ BUS_DATA_PIN_GROUP(bsc_data, 32),
27562570 SH_PFC_PIN_GROUP(bsc_cs0),
27572571 SH_PFC_PIN_GROUP(bsc_cs2),
27582572 SH_PFC_PIN_GROUP(bsc_cs4),
@@ -2760,9 +2574,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 1 unmodified line
27602574 SH_PFC_PIN_GROUP(bsc_cs5a_1),
27612575 SH_PFC_PIN_GROUP(bsc_cs5b),
27622576 SH_PFC_PIN_GROUP(bsc_cs6a),
2763− SH_PFC_PIN_GROUP(bsc_rd_we8),
2764− SH_PFC_PIN_GROUP(bsc_rd_we16),
2765− SH_PFC_PIN_GROUP(bsc_rd_we32),
2577+ SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
2578+ SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
2579+ SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
27662580 SH_PFC_PIN_GROUP(bsc_bs),
27672581 SH_PFC_PIN_GROUP(bsc_rdwr),
27682582 SH_PFC_PIN_GROUP(ceu0_data_0_7),
@@ -2847,11 +2661,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 78 unmodified lines
28472661 SH_PFC_PIN_GROUP(intc_irq30_1),
28482662 SH_PFC_PIN_GROUP(intc_irq31_0),
28492663 SH_PFC_PIN_GROUP(intc_irq31_1),
2850− SH_PFC_PIN_GROUP(lcd0_data8),
2851− SH_PFC_PIN_GROUP(lcd0_data9),
2852− SH_PFC_PIN_GROUP(lcd0_data12),
2853− SH_PFC_PIN_GROUP(lcd0_data16),
2854− SH_PFC_PIN_GROUP(lcd0_data18),
2664+ SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
2665+ SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
2666+ SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
2667+ SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
2668+ SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
28552669 SH_PFC_PIN_GROUP(lcd0_data24_0),
28562670 SH_PFC_PIN_GROUP(lcd0_data24_1),
28572671 SH_PFC_PIN_GROUP(lcd0_display),
@@ -2859,23 +2673,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 1 unmodified line
28592673 SH_PFC_PIN_GROUP(lcd0_lclk_1),
28602674 SH_PFC_PIN_GROUP(lcd0_sync),
28612675 SH_PFC_PIN_GROUP(lcd0_sys),
2862− SH_PFC_PIN_GROUP(lcd1_data8),
2863− SH_PFC_PIN_GROUP(lcd1_data9),
2864− SH_PFC_PIN_GROUP(lcd1_data12),
2865− SH_PFC_PIN_GROUP(lcd1_data16),
2866− SH_PFC_PIN_GROUP(lcd1_data18),
2867− SH_PFC_PIN_GROUP(lcd1_data24),
2676+ BUS_DATA_PIN_GROUP(lcd1_data, 8),
2677+ BUS_DATA_PIN_GROUP(lcd1_data, 9),
2678+ BUS_DATA_PIN_GROUP(lcd1_data, 12),
2679+ BUS_DATA_PIN_GROUP(lcd1_data, 16),
2680+ BUS_DATA_PIN_GROUP(lcd1_data, 18),
2681+ BUS_DATA_PIN_GROUP(lcd1_data, 24),
28682682 SH_PFC_PIN_GROUP(lcd1_display),
28692683 SH_PFC_PIN_GROUP(lcd1_lclk),
28702684 SH_PFC_PIN_GROUP(lcd1_sync),
28712685 SH_PFC_PIN_GROUP(lcd1_sys),
2872− SH_PFC_PIN_GROUP(mmc0_data1_0),
2873− SH_PFC_PIN_GROUP(mmc0_data4_0),
2874− SH_PFC_PIN_GROUP(mmc0_data8_0),
2686+ BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
2687+ BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
2688+ BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
28752689 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2876− SH_PFC_PIN_GROUP(mmc0_data1_1),
2877− SH_PFC_PIN_GROUP(mmc0_data4_1),
2878− SH_PFC_PIN_GROUP(mmc0_data8_1),
2690+ BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
2691+ BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
2692+ BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
28792693 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
28802694 SH_PFC_PIN_GROUP(scifa0_data),
28812695 SH_PFC_PIN_GROUP(scifa0_clk),
@@ -2912,18 +2726,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 30 unmodified lines
29122726 SH_PFC_PIN_GROUP(scifb_data_1),
29132727 SH_PFC_PIN_GROUP(scifb_clk_1),
29142728 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2915− SH_PFC_PIN_GROUP(sdhi0_data1),
2916− SH_PFC_PIN_GROUP(sdhi0_data4),
2729+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2730+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
29172731 SH_PFC_PIN_GROUP(sdhi0_ctrl),
29182732 SH_PFC_PIN_GROUP(sdhi0_cd),
29192733 SH_PFC_PIN_GROUP(sdhi0_wp),
2920− SH_PFC_PIN_GROUP(sdhi1_data1),
2921− SH_PFC_PIN_GROUP(sdhi1_data4),
2734+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
2735+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
29222736 SH_PFC_PIN_GROUP(sdhi1_ctrl),
29232737 SH_PFC_PIN_GROUP(sdhi1_cd),
29242738 SH_PFC_PIN_GROUP(sdhi1_wp),
2925− SH_PFC_PIN_GROUP(sdhi2_data1),
2926− SH_PFC_PIN_GROUP(sdhi2_data4),
2739+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2740+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
29272741 SH_PFC_PIN_GROUP(sdhi2_ctrl),
29282742 SH_PFC_PIN_GROUP(sdhi2_cd_0),
29292743 SH_PFC_PIN_GROUP(sdhi2_wp_0),
@@ -3681,7 +3495,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { · 751 unmodified lines
36813495 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
36823496 };
36833497
3684−static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
3498+static int r8a7740_pin_to_portcr(unsigned int pin)
36853499 {
36863500 unsigned int i;
36873501
@@ -3690,10 +3504,10 @@ static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) · 2 unmodified lines
36903504 &r8a7740_portcr_offsets[i];
36913505
36923506 if (pin <= group->end_pin)
3693− return pfc->windows->virt + group->offset + pin;
3507+ return group->offset + pin;
36943508 }
36953509
3696− return NULL;
3510+ return -1;
36973511 }
36983512
36993513 static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
drivers/pinctrl/renesas/pfc-r8a77470.c+82−158
@@ -1595,30 +1595,14 @@ static const unsigned int i2c4_e_mux[] = { · 1594 unmodified lines
15951595 SCL4_E_MARK, SDA4_E_MARK,
15961596 };
15971597 /* - MMC -------------------------------------------------------------------- */
1598−static const unsigned int mmc_data1_pins[] = {
1599− /* D0 */
1600− RCAR_GP_PIN(0, 15),
1601−};
1602−static const unsigned int mmc_data1_mux[] = {
1603− MMC0_D0_SDHI1_D0_MARK,
1604−};
1605−static const unsigned int mmc_data4_pins[] = {
1606− /* D[0:3] */
1607− RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1608− RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1609−};
1610−static const unsigned int mmc_data4_mux[] = {
1611− MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1612− MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1613−};
1614−static const unsigned int mmc_data8_pins[] = {
1598+static const unsigned int mmc_data_pins[] = {
16151599 /* D[0:3] */
16161600 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
16171601 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
16181602 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
16191603 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
16201604 };
1621−static const unsigned int mmc_data8_mux[] = {
1605+static const unsigned int mmc_data_mux[] = {
16221606 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
16231607 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
16241608 MMC0_D4_MARK, MMC0_D5_MARK,
@@ -1639,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = { · 14 unmodified lines
16391623 static const unsigned int qspi0_ctrl_mux[] = {
16401624 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
16411625 };
1642−static const unsigned int qspi0_data2_pins[] = {
1643− /* MOSI_IO0, MISO_IO1 */
1644− RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
1645−};
1646−static const unsigned int qspi0_data2_mux[] = {
1647− QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1648−};
1649−static const unsigned int qspi0_data4_pins[] = {
1626+static const unsigned int qspi0_data_pins[] = {
16501627 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
16511628 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
16521629 RCAR_GP_PIN(1, 20),
16531630 };
1654−static const unsigned int qspi0_data4_mux[] = {
1631+static const unsigned int qspi0_data_mux[] = {
16551632 QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
16561633 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
16571634 };
@@ -1662,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = { · 4 unmodified lines
16621639 static const unsigned int qspi1_ctrl_mux[] = {
16631640 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
16641641 };
1665−static const unsigned int qspi1_data2_pins[] = {
1666− /* MOSI_IO0, MISO_IO1 */
1667− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1668−};
1669−static const unsigned int qspi1_data2_mux[] = {
1670− QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1671−};
1672−static const unsigned int qspi1_data4_pins[] = {
1642+static const unsigned int qspi1_data_pins[] = {
16731643 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
16741644 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
16751645 RCAR_GP_PIN(4, 8),
16761646 };
1677−static const unsigned int qspi1_data4_mux[] = {
1647+static const unsigned int qspi1_data_mux[] = {
16781648 QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
16791649 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
16801650 };
@@ -1917,19 +1887,12 @@ static const unsigned int scif_clk_b_mux[] = { · 236 unmodified lines
19171887 SCIF_CLK_B_MARK,
19181888 };
19191889 /* - SDHI0 ------------------------------------------------------------------ */
1920−static const unsigned int sdhi0_data1_pins[] = {
1921− /* D0 */
1922− RCAR_GP_PIN(0, 7),
1923−};
1924−static const unsigned int sdhi0_data1_mux[] = {
1925− SD0_DAT0_MARK,
1926−};
1927−static const unsigned int sdhi0_data4_pins[] = {
1890+static const unsigned int sdhi0_data_pins[] = {
19281891 /* D[0:3] */
19291892 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
19301893 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
19311894 };
1932−static const unsigned int sdhi0_data4_mux[] = {
1895+static const unsigned int sdhi0_data_mux[] = {
19331896 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
19341897 };
19351898 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -1954,29 +1917,6 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
19541917 SD0_WP_MARK,
19551918 };
19561919 /* - SDHI1 ------------------------------------------------------------------ */
1957−static const unsigned int sdhi1_data1_pins[] = {
1958− /* D0 */
1959− RCAR_GP_PIN(0, 15),
1960−};
1961−static const unsigned int sdhi1_data1_mux[] = {
1962− MMC0_D0_SDHI1_D0_MARK,
1963−};
1964−static const unsigned int sdhi1_data4_pins[] = {
1965− /* D[0:3] */
1966− RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1967− RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1968−};
1969−static const unsigned int sdhi1_data4_mux[] = {
1970− MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1971− MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1972−};
1973−static const unsigned int sdhi1_ctrl_pins[] = {
1974− /* CLK, CMD */
1975− RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1976−};
1977−static const unsigned int sdhi1_ctrl_mux[] = {
1978− MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1979−};
19801920 static const unsigned int sdhi1_cd_pins[] = {
19811921 /* CD */
19821922 RCAR_GP_PIN(0, 19),
@@ -1992,19 +1932,12 @@ static const unsigned int sdhi1_wp_mux[] = { · 9 unmodified lines
19921932 SD1_WP_MARK,
19931933 };
19941934 /* - SDHI2 ------------------------------------------------------------------ */
1995−static const unsigned int sdhi2_data1_pins[] = {
1996− /* D0 */
1997− RCAR_GP_PIN(4, 16),
1998−};
1999−static const unsigned int sdhi2_data1_mux[] = {
2000− SD2_DAT0_MARK,
2001−};
2002−static const unsigned int sdhi2_data4_pins[] = {
1935+static const unsigned int sdhi2_data_pins[] = {
20031936 /* D[0:3] */
20041937 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
20051938 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
20061939 };
2007−static const unsigned int sdhi2_data4_mux[] = {
1940+static const unsigned int sdhi2_data_mux[] = {
20081941 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
20091942 };
20101943 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -2047,43 +1980,39 @@ static const unsigned int usb1_mux[] = { · 36 unmodified lines
20471980 USB1_OVC_MARK,
20481981 };
20491982 /* - VIN0 ------------------------------------------------------------------- */
2050−static const union vin_data vin0_data_pins = {
2051− .data24 = {
2052− /* B */
2053− RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2054− RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2055− RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2056− RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2057− /* G */
2058− RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2059− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2060− RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2061− RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2062− /* R */
2063− RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2064− RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2065− RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2066− RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2067− },
1983+static const unsigned int vin0_data_pins[] = {
1984+ /* B */
1985+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1986+ RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1987+ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1988+ RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1989+ /* G */
1990+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1991+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1992+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
1993+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1994+ /* R */
1995+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
1996+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1997+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1998+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
20681999 };
2069−static const union vin_data vin0_data_mux = {
2070− .data24 = {
2071− /* B */
2072− VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2073− VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2074− VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2075− VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2076− /* G */
2077− VI0_G0_MARK, VI0_G1_MARK,
2078− VI0_G2_MARK, VI0_G3_MARK,
2079− VI0_G4_MARK, VI0_G5_MARK,
2080− VI0_G6_MARK, VI0_G7_MARK,
2081− /* R */
2082− VI0_R0_MARK, VI0_R1_MARK,
2083− VI0_R2_MARK, VI0_R3_MARK,
2084− VI0_R4_MARK, VI0_R5_MARK,
2085− VI0_R6_MARK, VI0_R7_MARK,
2086− },
2000+static const unsigned int vin0_data_mux[] = {
2001+ /* B */
2002+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2003+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2004+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2005+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2006+ /* G */
2007+ VI0_G0_MARK, VI0_G1_MARK,
2008+ VI0_G2_MARK, VI0_G3_MARK,
2009+ VI0_G4_MARK, VI0_G5_MARK,
2010+ VI0_G6_MARK, VI0_G7_MARK,
2011+ /* R */
2012+ VI0_R0_MARK, VI0_R1_MARK,
2013+ VI0_R2_MARK, VI0_R3_MARK,
2014+ VI0_R4_MARK, VI0_R5_MARK,
2015+ VI0_R6_MARK, VI0_R7_MARK,
20872016 };
20882017 static const unsigned int vin0_data18_pins[] = {
20892018 /* B */
@@ -2140,25 +2069,21 @@ static const unsigned int vin0_clk_mux[] = { · 50 unmodified lines
21402069 VI0_CLK_MARK,
21412070 };
21422071 /* - VIN1 ------------------------------------------------------------------- */
2143−static const union vin_data vin1_data_pins = {
2144− .data12 = {
2145− RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2146− RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2147− RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2148− RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2149− RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2150− RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2151− },
2072+static const unsigned int vin1_data_pins[] = {
2073+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2074+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2075+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2076+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2077+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2078+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
21522079 };
2153−static const union vin_data vin1_data_mux = {
2154− .data12 = {
2155− VI1_DATA0_MARK, VI1_DATA1_MARK,
2156− VI1_DATA2_MARK, VI1_DATA3_MARK,
2157− VI1_DATA4_MARK, VI1_DATA5_MARK,
2158− VI1_DATA6_MARK, VI1_DATA7_MARK,
2159− VI1_DATA8_MARK, VI1_DATA9_MARK,
2160− VI1_DATA10_MARK, VI1_DATA11_MARK,
2161− },
2080+static const unsigned int vin1_data_mux[] = {
2081+ VI1_DATA0_MARK, VI1_DATA1_MARK,
2082+ VI1_DATA2_MARK, VI1_DATA3_MARK,
2083+ VI1_DATA4_MARK, VI1_DATA5_MARK,
2084+ VI1_DATA6_MARK, VI1_DATA7_MARK,
2085+ VI1_DATA8_MARK, VI1_DATA9_MARK,
2086+ VI1_DATA10_MARK, VI1_DATA11_MARK,
21622087 };
21632088 static const unsigned int vin1_sync_pins[] = {
21642089 RCAR_GP_PIN(3, 11), /* HSYNC */
@@ -2243,16 +2168,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 78 unmodified lines
22432168 SH_PFC_PIN_GROUP(i2c4_c),
22442169 SH_PFC_PIN_GROUP(i2c4_d),
22452170 SH_PFC_PIN_GROUP(i2c4_e),
2246− SH_PFC_PIN_GROUP(mmc_data1),
2247− SH_PFC_PIN_GROUP(mmc_data4),
2248− SH_PFC_PIN_GROUP(mmc_data8),
2171+ BUS_DATA_PIN_GROUP(mmc_data, 1),
2172+ BUS_DATA_PIN_GROUP(mmc_data, 4),
2173+ BUS_DATA_PIN_GROUP(mmc_data, 8),
22492174 SH_PFC_PIN_GROUP(mmc_ctrl),
22502175 SH_PFC_PIN_GROUP(qspi0_ctrl),
2251− SH_PFC_PIN_GROUP(qspi0_data2),
2252− SH_PFC_PIN_GROUP(qspi0_data4),
2176+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
2177+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
22532178 SH_PFC_PIN_GROUP(qspi1_ctrl),
2254− SH_PFC_PIN_GROUP(qspi1_data2),
2255− SH_PFC_PIN_GROUP(qspi1_data4),
2179+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
2180+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
22562181 SH_PFC_PIN_GROUP(scif0_data_a),
22572182 SH_PFC_PIN_GROUP(scif0_data_b),
22582183 SH_PFC_PIN_GROUP(scif0_data_c),
@@ -2286,37 +2211,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 27 unmodified lines
22862211 SH_PFC_PIN_GROUP(scif5_data_f),
22872212 SH_PFC_PIN_GROUP(scif_clk_a),
22882213 SH_PFC_PIN_GROUP(scif_clk_b),
2289− SH_PFC_PIN_GROUP(sdhi0_data1),
2290− SH_PFC_PIN_GROUP(sdhi0_data4),
2214+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2215+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
22912216 SH_PFC_PIN_GROUP(sdhi0_ctrl),
22922217 SH_PFC_PIN_GROUP(sdhi0_cd),
22932218 SH_PFC_PIN_GROUP(sdhi0_wp),
2294− SH_PFC_PIN_GROUP(sdhi1_data1),
2295− SH_PFC_PIN_GROUP(sdhi1_data4),
2296− SH_PFC_PIN_GROUP(sdhi1_ctrl),
2219+ SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
2220+ SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
2221+ SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
22972222 SH_PFC_PIN_GROUP(sdhi1_cd),
22982223 SH_PFC_PIN_GROUP(sdhi1_wp),
2299− SH_PFC_PIN_GROUP(sdhi2_data1),
2300− SH_PFC_PIN_GROUP(sdhi2_data4),
2224+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2225+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
23012226 SH_PFC_PIN_GROUP(sdhi2_ctrl),
23022227 SH_PFC_PIN_GROUP(sdhi2_cd),
23032228 SH_PFC_PIN_GROUP(sdhi2_wp),
23042229 SH_PFC_PIN_GROUP(usb0),
23052230 SH_PFC_PIN_GROUP(usb1),
2306− VIN_DATA_PIN_GROUP(vin0_data, 24),
2307− VIN_DATA_PIN_GROUP(vin0_data, 20),
2231+ BUS_DATA_PIN_GROUP(vin0_data, 24),
2232+ BUS_DATA_PIN_GROUP(vin0_data, 20),
23082233 SH_PFC_PIN_GROUP(vin0_data18),
2309− VIN_DATA_PIN_GROUP(vin0_data, 16),
2310− VIN_DATA_PIN_GROUP(vin0_data, 12),
2311− VIN_DATA_PIN_GROUP(vin0_data, 10),
2312− VIN_DATA_PIN_GROUP(vin0_data, 8),
2234+ BUS_DATA_PIN_GROUP(vin0_data, 16),
2235+ BUS_DATA_PIN_GROUP(vin0_data, 12),
2236+ BUS_DATA_PIN_GROUP(vin0_data, 10),
2237+ BUS_DATA_PIN_GROUP(vin0_data, 8),
23132238 SH_PFC_PIN_GROUP(vin0_sync),
23142239 SH_PFC_PIN_GROUP(vin0_field),
23152240 SH_PFC_PIN_GROUP(vin0_clkenb),
23162241 SH_PFC_PIN_GROUP(vin0_clk),
2317− VIN_DATA_PIN_GROUP(vin1_data, 12),
2318− VIN_DATA_PIN_GROUP(vin1_data, 10),
2319− VIN_DATA_PIN_GROUP(vin1_data, 8),
2242+ BUS_DATA_PIN_GROUP(vin1_data, 12),
2243+ BUS_DATA_PIN_GROUP(vin1_data, 10),
2244+ BUS_DATA_PIN_GROUP(vin1_data, 8),
23202245 SH_PFC_PIN_GROUP(vin1_sync),
23212246 SH_PFC_PIN_GROUP(vin1_field),
23222247 SH_PFC_PIN_GROUP(vin1_clkenb),
@@ -3420,8 +3345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 1097 unmodified lines
34203345 { },
34213346 };
34223347
3423−static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
3424− u32 *pocctrl)
3348+static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
34253349 {
34263350 int bit = -EINVAL;
34273351
@@ -3683,7 +3607,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 255 unmodified lines
36833607 { /* sentinel */ }
36843608 };
36853609
3686−static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
3610+static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
36873611 .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
36883612 .get_bias = rcar_pinmux_get_bias,
36893613 .set_bias = rcar_pinmux_set_bias,
@@ -3692,7 +3616,7 @@ static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { · 2 unmodified lines
36923616 #ifdef CONFIG_PINCTRL_PFC_R8A77470
36933617 const struct sh_pfc_soc_info r8a77470_pinmux_info = {
36943618 .name = "r8a77470_pfc",
3695− .ops = &r8a77470_pinmux_ops,
3619+ .ops = &r8a77470_pfc_ops,
36963620 .unlock_reg = 0xe6060000, /* PMMR */
36973621
36983622 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a7778.c+25−44
@@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); · 1426 unmodified lines
14271427 /* - MMC macro -------------------------------------------------------------- */
14281428 #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
14291429 #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
1430−#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
1431−#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
14321430 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
14331431 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
14341432
14351433 /* - MMC -------------------------------------------------------------------- */
14361434 MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
14371435 MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
1438−MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
1439−MMC_PFC_DAT1(mmc_data1, MMC_D0);
1440−MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1441− RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1442−MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
1443− MMC_D2, MMC_D3);
1444−MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1436+MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
14451437 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
14461438 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
14471439 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
1448−MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
1440+MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1,
14491441 MMC_D2, MMC_D3,
14501442 MMC_D4, MMC_D5,
14511443 MMC_D6, MMC_D7);
@@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); · 78 unmodified lines
15301522
15311523 /* - SDHI macro ------------------------------------------------------------- */
15321524 #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1533−#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
15341525 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
15351526 #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
15361527 #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
@@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); · 4 unmodified lines
15411532 SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
15421533 SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
15431534 SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
1544−SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
1545−SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
1546−SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1535+SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
15471536 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
1548−SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
1537+SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1,
15491538 SD0_DAT2, SD0_DAT3);
15501539 SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
15511540 SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
@@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); · 7 unmodified lines
15591548 SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
15601549 SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
15611550 SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
1562−SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
1563−SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
1564−SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
1565−SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
1566−SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1551+SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
15671552 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1568−SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
1553+SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A,
15691554 SD1_DAT2_A, SD1_DAT3_A);
1570−SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1555+SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
15711556 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1572−SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
1557+SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B,
15731558 SD1_DAT2_B, SD1_DAT3_B);
15741559 SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
15751560 SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
@@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); · 9 unmodified lines
15851570 SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
15861571 SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
15871572 SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
1588−SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
1589−SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
1590−SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
1591−SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
1592−SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
1573+SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
15931574 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
1594−SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
1575+SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A,
15951576 SD2_DAT2_A, SD2_DAT3_A);
1596−SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
1577+SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
15971578 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
1598−SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
1579+SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B,
15991580 SD2_DAT2_B, SD2_DAT3_B);
16001581 SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
16011582 SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
@@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 142 unmodified lines
17441725 SH_PFC_PIN_GROUP(i2c3_b),
17451726 SH_PFC_PIN_GROUP(i2c3_c),
17461727 SH_PFC_PIN_GROUP(mmc_ctrl),
1747− SH_PFC_PIN_GROUP(mmc_data1),
1748− SH_PFC_PIN_GROUP(mmc_data4),
1749− SH_PFC_PIN_GROUP(mmc_data8),
1728+ BUS_DATA_PIN_GROUP(mmc_data, 1),
1729+ BUS_DATA_PIN_GROUP(mmc_data, 4),
1730+ BUS_DATA_PIN_GROUP(mmc_data, 8),
17501731 SH_PFC_PIN_GROUP(scif_clk),
17511732 SH_PFC_PIN_GROUP(scif0_data_a),
17521733 SH_PFC_PIN_GROUP(scif0_data_b),
@@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 28 unmodified lines
17811762 SH_PFC_PIN_GROUP(scif5_data_b),
17821763 SH_PFC_PIN_GROUP(sdhi0_cd),
17831764 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1784− SH_PFC_PIN_GROUP(sdhi0_data1),
1785− SH_PFC_PIN_GROUP(sdhi0_data4),
1765+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1766+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
17861767 SH_PFC_PIN_GROUP(sdhi0_wp),
17871768 SH_PFC_PIN_GROUP(sdhi1_cd_a),
17881769 SH_PFC_PIN_GROUP(sdhi1_cd_b),
17891770 SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
17901771 SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1791− SH_PFC_PIN_GROUP(sdhi1_data1_a),
1792− SH_PFC_PIN_GROUP(sdhi1_data1_b),
1793− SH_PFC_PIN_GROUP(sdhi1_data4_a),
1794− SH_PFC_PIN_GROUP(sdhi1_data4_b),
1772+ BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a),
1773+ BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b),
1774+ BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a),
1775+ BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b),
17951776 SH_PFC_PIN_GROUP(sdhi1_wp_a),
17961777 SH_PFC_PIN_GROUP(sdhi1_wp_b),
17971778 SH_PFC_PIN_GROUP(sdhi2_cd_a),
17981779 SH_PFC_PIN_GROUP(sdhi2_cd_b),
17991780 SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
18001781 SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1801− SH_PFC_PIN_GROUP(sdhi2_data1_a),
1802− SH_PFC_PIN_GROUP(sdhi2_data1_b),
1803− SH_PFC_PIN_GROUP(sdhi2_data4_a),
1804− SH_PFC_PIN_GROUP(sdhi2_data4_b),
1782+ BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a),
1783+ BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b),
1784+ BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a),
1785+ BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b),
18051786 SH_PFC_PIN_GROUP(sdhi2_wp_a),
18061787 SH_PFC_PIN_GROUP(sdhi2_wp_b),
18071788 SH_PFC_PIN_GROUP(ssi012_ctrl),
drivers/pinctrl/renesas/pfc-r8a7779.c+30−88
@@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = { · 1927 unmodified lines
19281928 EX_CS5_MARK,
19291929 };
19301930 /* - MMCIF ------------------------------------------------------------------ */
1931−static const unsigned int mmc0_data1_pins[] = {
1932− /* D[0] */
1933− RCAR_GP_PIN(0, 19),
1934−};
1935−static const unsigned int mmc0_data1_mux[] = {
1936− MMC0_D0_MARK,
1937−};
1938−static const unsigned int mmc0_data4_pins[] = {
1939− /* D[0:3] */
1940− RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1941− RCAR_GP_PIN(0, 2),
1942−};
1943−static const unsigned int mmc0_data4_mux[] = {
1944− MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1945−};
1946−static const unsigned int mmc0_data8_pins[] = {
1931+static const unsigned int mmc0_data_pins[] = {
19471932 /* D[0:7] */
19481933 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
19491934 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
19501935 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
19511936 };
1952−static const unsigned int mmc0_data8_mux[] = {
1937+static const unsigned int mmc0_data_mux[] = {
19531938 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
19541939 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
19551940 };
@@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = { · 4 unmodified lines
19601945 static const unsigned int mmc0_ctrl_mux[] = {
19611946 MMC0_CMD_MARK, MMC0_CLK_MARK,
19621947 };
1963−static const unsigned int mmc1_data1_pins[] = {
1964− /* D[0] */
1965− RCAR_GP_PIN(2, 8),
1966−};
1967−static const unsigned int mmc1_data1_mux[] = {
1968− MMC1_D0_MARK,
1969−};
1970−static const unsigned int mmc1_data4_pins[] = {
1971− /* D[0:3] */
1972− RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1973− RCAR_GP_PIN(2, 11),
1974−};
1975−static const unsigned int mmc1_data4_mux[] = {
1976− MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1977−};
1978−static const unsigned int mmc1_data8_pins[] = {
1948+static const unsigned int mmc1_data_pins[] = {
19791949 /* D[0:7] */
19801950 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
19811951 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
19821952 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
19831953 };
1984−static const unsigned int mmc1_data8_mux[] = {
1954+static const unsigned int mmc1_data_mux[] = {
19851955 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
19861956 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
19871957 };
@@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = { · 398 unmodified lines
23862356 SCIF_CLK_D_MARK,
23872357 };
23882358 /* - SDHI0 ------------------------------------------------------------------ */
2389−static const unsigned int sdhi0_data1_pins[] = {
2390− /* D0 */
2391− RCAR_GP_PIN(3, 21),
2392−};
2393−static const unsigned int sdhi0_data1_mux[] = {
2394− SD0_DAT0_MARK,
2395−};
2396−static const unsigned int sdhi0_data4_pins[] = {
2359+static const unsigned int sdhi0_data_pins[] = {
23972360 /* D[0:3] */
23982361 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
23992362 RCAR_GP_PIN(3, 24),
24002363 };
2401−static const unsigned int sdhi0_data4_mux[] = {
2364+static const unsigned int sdhi0_data_mux[] = {
24022365 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
24032366 };
24042367 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
24232386 SD0_WP_MARK,
24242387 };
24252388 /* - SDHI1 ------------------------------------------------------------------ */
2426−static const unsigned int sdhi1_data1_pins[] = {
2427− /* D0 */
2428− RCAR_GP_PIN(0, 19),
2429−};
2430−static const unsigned int sdhi1_data1_mux[] = {
2431− SD1_DAT0_MARK,
2432−};
2433−static const unsigned int sdhi1_data4_pins[] = {
2389+static const unsigned int sdhi1_data_pins[] = {
24342390 /* D[0:3] */
24352391 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
24362392 RCAR_GP_PIN(0, 2),
24372393 };
2438−static const unsigned int sdhi1_data4_mux[] = {
2394+static const unsigned int sdhi1_data_mux[] = {
24392395 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
24402396 };
24412397 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = { · 18 unmodified lines
24602416 SD1_WP_MARK,
24612417 };
24622418 /* - SDHI2 ------------------------------------------------------------------ */
2463−static const unsigned int sdhi2_data1_pins[] = {
2464− /* D0 */
2465− RCAR_GP_PIN(3, 1),
2466−};
2467−static const unsigned int sdhi2_data1_mux[] = {
2468− SD2_DAT0_MARK,
2469−};
2470−static const unsigned int sdhi2_data4_pins[] = {
2419+static const unsigned int sdhi2_data_pins[] = {
24712420 /* D[0:3] */
24722421 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
24732422 RCAR_GP_PIN(3, 4),
24742423 };
2475−static const unsigned int sdhi2_data4_mux[] = {
2424+static const unsigned int sdhi2_data_mux[] = {
24762425 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
24772426 };
24782427 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = { · 18 unmodified lines
24972446 SD2_WP_MARK,
24982447 };
24992448 /* - SDHI3 ------------------------------------------------------------------ */
2500−static const unsigned int sdhi3_data1_pins[] = {
2501− /* D0 */
2502− RCAR_GP_PIN(1, 18),
2503−};
2504−static const unsigned int sdhi3_data1_mux[] = {
2505− SD3_DAT0_MARK,
2506−};
2507−static const unsigned int sdhi3_data4_pins[] = {
2449+static const unsigned int sdhi3_data_pins[] = {
25082450 /* D[0:3] */
25092451 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
25102452 RCAR_GP_PIN(1, 21),
25112453 };
2512−static const unsigned int sdhi3_data4_mux[] = {
2454+static const unsigned int sdhi3_data_mux[] = {
25132455 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
25142456 };
25152457 static const unsigned int sdhi3_ctrl_pins[] = {
@@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 233 unmodified lines
27492691 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
27502692 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
27512693 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2752− SH_PFC_PIN_GROUP(mmc0_data1),
2753− SH_PFC_PIN_GROUP(mmc0_data4),
2754− SH_PFC_PIN_GROUP(mmc0_data8),
2694+ BUS_DATA_PIN_GROUP(mmc0_data, 1),
2695+ BUS_DATA_PIN_GROUP(mmc0_data, 4),
2696+ BUS_DATA_PIN_GROUP(mmc0_data, 8),
27552697 SH_PFC_PIN_GROUP(mmc0_ctrl),
2756− SH_PFC_PIN_GROUP(mmc1_data1),
2757− SH_PFC_PIN_GROUP(mmc1_data4),
2758− SH_PFC_PIN_GROUP(mmc1_data8),
2698+ BUS_DATA_PIN_GROUP(mmc1_data, 1),
2699+ BUS_DATA_PIN_GROUP(mmc1_data, 4),
2700+ BUS_DATA_PIN_GROUP(mmc1_data, 8),
27592701 SH_PFC_PIN_GROUP(mmc1_ctrl),
27602702 SH_PFC_PIN_GROUP(scif0_data),
27612703 SH_PFC_PIN_GROUP(scif0_clk),
@@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 50 unmodified lines
28122754 SH_PFC_PIN_GROUP(scif_clk_b),
28132755 SH_PFC_PIN_GROUP(scif_clk_c),
28142756 SH_PFC_PIN_GROUP(scif_clk_d),
2815− SH_PFC_PIN_GROUP(sdhi0_data1),
2816− SH_PFC_PIN_GROUP(sdhi0_data4),
2757+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2758+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
28172759 SH_PFC_PIN_GROUP(sdhi0_ctrl),
28182760 SH_PFC_PIN_GROUP(sdhi0_cd),
28192761 SH_PFC_PIN_GROUP(sdhi0_wp),
2820− SH_PFC_PIN_GROUP(sdhi1_data1),
2821− SH_PFC_PIN_GROUP(sdhi1_data4),
2762+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
2763+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
28222764 SH_PFC_PIN_GROUP(sdhi1_ctrl),
28232765 SH_PFC_PIN_GROUP(sdhi1_cd),
28242766 SH_PFC_PIN_GROUP(sdhi1_wp),
2825− SH_PFC_PIN_GROUP(sdhi2_data1),
2826− SH_PFC_PIN_GROUP(sdhi2_data4),
2767+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2768+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
28272769 SH_PFC_PIN_GROUP(sdhi2_ctrl),
28282770 SH_PFC_PIN_GROUP(sdhi2_cd),
28292771 SH_PFC_PIN_GROUP(sdhi2_wp),
2830− SH_PFC_PIN_GROUP(sdhi3_data1),
2831− SH_PFC_PIN_GROUP(sdhi3_data4),
2772+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
2773+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
28322774 SH_PFC_PIN_GROUP(sdhi3_ctrl),
28332775 SH_PFC_PIN_GROUP(sdhi3_cd),
28342776 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -3133,10 +3075,6 @@ static const struct sh_pfc_function pinmux_functions[] = { · 298 unmodified lines
31333075 SH_PFC_FUNCTION(lbsc),
31343076 SH_PFC_FUNCTION(mmc0),
31353077 SH_PFC_FUNCTION(mmc1),
3136− SH_PFC_FUNCTION(sdhi0),
3137− SH_PFC_FUNCTION(sdhi1),
3138− SH_PFC_FUNCTION(sdhi2),
3139− SH_PFC_FUNCTION(sdhi3),
31403078 SH_PFC_FUNCTION(scif0),
31413079 SH_PFC_FUNCTION(scif1),
31423080 SH_PFC_FUNCTION(scif2),
@@ -3144,6 +3082,10 @@ static const struct sh_pfc_function pinmux_functions[] = { · 1 unmodified line
31443082 SH_PFC_FUNCTION(scif4),
31453083 SH_PFC_FUNCTION(scif5),
31463084 SH_PFC_FUNCTION(scif_clk),
3085+ SH_PFC_FUNCTION(sdhi0),
3086+ SH_PFC_FUNCTION(sdhi1),
3087+ SH_PFC_FUNCTION(sdhi2),
3088+ SH_PFC_FUNCTION(sdhi3),
31473089 SH_PFC_FUNCTION(usb0),
31483090 SH_PFC_FUNCTION(usb1),
31493091 SH_PFC_FUNCTION(usb2),
drivers/pinctrl/renesas/pfc-r8a7790.c+208−322
@@ -194,24 +194,24 @@ enum { · 193 unmodified lines
194194 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
195195 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
196196 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
197− FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
197+ FN_WE0_N, FN_IECLK, FN_CAN_CLK,
198198 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
199199 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
200200 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
201− FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
201+ FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
202202 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
203203 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
204204 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
205205 FN_SSI_WS78_B,
206206
207207 /* IPSR6 */
208− FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
208+ FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
209209 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
210210 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
211211 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
212− FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
212+ FN_SSI_WS6_B, FN_SSI_SDATA8_C,
213213 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
214− FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
214+ FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
215215 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
216216 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
217217 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
@@ -568,23 +568,23 @@ enum { · 350 unmodified lines
568568 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
569569 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
570570 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
571− INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
571+ WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
572572 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
573573 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
574574 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
575− IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
575+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
576576 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
577577 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
578578 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
579579 SSI_WS78_B_MARK,
580580
581− DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
581+ DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
582582 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
583583 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
584584 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
585− INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
585+ SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
586586 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
587− MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
587+ MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
588588 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
589589 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
590590 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
@@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = { · 503 unmodified lines
10941094 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
10951095 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
10961096 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1097− PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
10981097 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
10991098 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
11001099 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
@@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = { · 10 unmodified lines
11111110 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
11121111 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
11131112 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1114− PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
11151113 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
11161114 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
11171115 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
@@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = { · 7 unmodified lines
11251123
11261124 PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
11271125 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1128− PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
11291126 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
11301127 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
11311128 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
@@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = { · 5 unmodified lines
11371134 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
11381135 PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
11391136 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1140− PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
11411137 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
11421138 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
11431139 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
@@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = { · 2 unmodified lines
11461142 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
11471143 PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
11481144 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1149− PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
11501145 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
11511146 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
11521147 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
@@ -2410,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = { · 1257 unmodified lines
24102405 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
24112406
24122407 /* - MMCIF0 ----------------------------------------------------------------- */
2413−static const unsigned int mmc0_data1_pins[] = {
2414− /* D[0] */
2415− RCAR_GP_PIN(3, 18),
2416−};
2417−static const unsigned int mmc0_data1_mux[] = {
2418− MMC0_D0_MARK,
2419−};
2420−static const unsigned int mmc0_data4_pins[] = {
2421− /* D[0:3] */
2422− RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2423− RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2424−};
2425−static const unsigned int mmc0_data4_mux[] = {
2426− MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2427−};
2428−static const unsigned int mmc0_data8_pins[] = {
2408+static const unsigned int mmc0_data_pins[] = {
24292409 /* D[0:7] */
24302410 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
24312411 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
24322412 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
24332413 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
24342414 };
2435−static const unsigned int mmc0_data8_mux[] = {
2415+static const unsigned int mmc0_data_mux[] = {
24362416 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
24372417 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
24382418 };
@@ -2444,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = { · 5 unmodified lines
24442424 MMC0_CLK_MARK, MMC0_CMD_MARK,
24452425 };
24462426 /* - MMCIF1 ----------------------------------------------------------------- */
2447−static const unsigned int mmc1_data1_pins[] = {
2448− /* D[0] */
2449− RCAR_GP_PIN(3, 26),
2450−};
2451−static const unsigned int mmc1_data1_mux[] = {
2452− MMC1_D0_MARK,
2453−};
2454−static const unsigned int mmc1_data4_pins[] = {
2455− /* D[0:3] */
2456− RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2457− RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2458−};
2459−static const unsigned int mmc1_data4_mux[] = {
2460− MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2461−};
2462−static const unsigned int mmc1_data8_pins[] = {
2427+static const unsigned int mmc1_data_pins[] = {
24632428 /* D[0:7] */
24642429 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
24652430 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
24662431 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
24672432 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
24682433 };
2469−static const unsigned int mmc1_data8_mux[] = {
2434+static const unsigned int mmc1_data_mux[] = {
24702435 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
24712436 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
24722437 };
@@ -2813,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = { · 340 unmodified lines
28132778 static const unsigned int qspi_ctrl_mux[] = {
28142779 SPCLK_MARK, SSL_MARK,
28152780 };
2816−static const unsigned int qspi_data2_pins[] = {
2817− /* MOSI_IO0, MISO_IO1 */
2818− RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2819−};
2820−static const unsigned int qspi_data2_mux[] = {
2821− MOSI_IO0_MARK, MISO_IO1_MARK,
2822−};
2823−static const unsigned int qspi_data4_pins[] = {
2781+static const unsigned int qspi_data_pins[] = {
28242782 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
28252783 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
28262784 RCAR_GP_PIN(1, 8),
28272785 };
2828−static const unsigned int qspi_data4_mux[] = {
2786+static const unsigned int qspi_data_mux[] = {
28292787 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
28302788 };
28312789 /* - SCIF0 ------------------------------------------------------------------ */
@@ -3322,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = { · 490 unmodified lines
33223280 SCIF_CLK_B_MARK,
33233281 };
33243282 /* - SDHI0 ------------------------------------------------------------------ */
3325−static const unsigned int sdhi0_data1_pins[] = {
3326− /* D0 */
3327− RCAR_GP_PIN(3, 2),
3328−};
3329−static const unsigned int sdhi0_data1_mux[] = {
3330− SD0_DAT0_MARK,
3331−};
3332−static const unsigned int sdhi0_data4_pins[] = {
3283+static const unsigned int sdhi0_data_pins[] = {
33333284 /* D[0:3] */
33343285 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
33353286 };
3336−static const unsigned int sdhi0_data4_mux[] = {
3287+static const unsigned int sdhi0_data_mux[] = {
33373288 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
33383289 };
33393290 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -3358,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
33583309 SD0_WP_MARK,
33593310 };
33603311 /* - SDHI1 ------------------------------------------------------------------ */
3361−static const unsigned int sdhi1_data1_pins[] = {
3362− /* D0 */
3363− RCAR_GP_PIN(3, 10),
3364−};
3365−static const unsigned int sdhi1_data1_mux[] = {
3366− SD1_DAT0_MARK,
3367−};
3368−static const unsigned int sdhi1_data4_pins[] = {
3312+static const unsigned int sdhi1_data_pins[] = {
33693313 /* D[0:3] */
33703314 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
33713315 };
3372−static const unsigned int sdhi1_data4_mux[] = {
3316+static const unsigned int sdhi1_data_mux[] = {
33733317 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
33743318 };
33753319 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -3394,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = { · 18 unmodified lines
33943338 SD1_WP_MARK,
33953339 };
33963340 /* - SDHI2 ------------------------------------------------------------------ */
3397−static const unsigned int sdhi2_data1_pins[] = {
3398− /* D0 */
3399− RCAR_GP_PIN(3, 18),
3400−};
3401−static const unsigned int sdhi2_data1_mux[] = {
3402− SD2_DAT0_MARK,
3403−};
3404−static const unsigned int sdhi2_data4_pins[] = {
3341+static const unsigned int sdhi2_data_pins[] = {
34053342 /* D[0:3] */
34063343 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
34073344 };
3408−static const unsigned int sdhi2_data4_mux[] = {
3345+static const unsigned int sdhi2_data_mux[] = {
34093346 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
34103347 };
34113348 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -3430,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = { · 18 unmodified lines
34303367 SD2_WP_MARK,
34313368 };
34323369 /* - SDHI3 ------------------------------------------------------------------ */
3433−static const unsigned int sdhi3_data1_pins[] = {
3434− /* D0 */
3435− RCAR_GP_PIN(3, 26),
3436−};
3437−static const unsigned int sdhi3_data1_mux[] = {
3438− SD3_DAT0_MARK,
3439−};
3440−static const unsigned int sdhi3_data4_pins[] = {
3370+static const unsigned int sdhi3_data_pins[] = {
34413371 /* D[0:3] */
34423372 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
34433373 };
3444−static const unsigned int sdhi3_data4_mux[] = {
3374+static const unsigned int sdhi3_data_mux[] = {
34453375 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
34463376 };
34473377 static const unsigned int sdhi3_ctrl_pins[] = {
@@ -3679,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = { · 231 unmodified lines
36793609 };
36803610 /* - USB0 ------------------------------------------------------------------- */
36813611 static const unsigned int usb0_pins[] = {
3682− /* PWEN, OVC/VBUS */
3683− RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3612+ /* OVC/VBUS, PWEN */
3613+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
36843614 };
36853615 static const unsigned int usb0_mux[] = {
3686− USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3687−};
3688−static const unsigned int usb0_ovc_vbus_pins[] = {
3689− /* OVC/VBUS */
3690− RCAR_GP_PIN(5, 19),
3691−};
3692−static const unsigned int usb0_ovc_vbus_mux[] = {
3693− USB0_OVC_VBUS_MARK,
3616+ USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
36943617 };
36953618 /* - USB1 ------------------------------------------------------------------- */
36963619 static const unsigned int usb1_pins[] = {
@@ -3700,13 +3623,6 @@ static const unsigned int usb1_pins[] = { · 3 unmodified lines
37003623 static const unsigned int usb1_mux[] = {
37013624 USB1_PWEN_MARK, USB1_OVC_MARK,
37023625 };
3703−static const unsigned int usb1_pwen_pins[] = {
3704− /* PWEN */
3705− RCAR_GP_PIN(5, 20),
3706−};
3707−static const unsigned int usb1_pwen_mux[] = {
3708− USB1_PWEN_MARK,
3709−};
37103626 /* - USB2 ------------------------------------------------------------------- */
37113627 static const unsigned int usb2_pins[] = {
37123628 /* PWEN, OVC */
@@ -3716,43 +3632,39 @@ static const unsigned int usb2_mux[] = { · 3 unmodified lines
37163632 USB2_PWEN_MARK, USB2_OVC_MARK,
37173633 };
37183634 /* - VIN0 ------------------------------------------------------------------- */
3719−static const union vin_data vin0_data_pins = {
3720− .data24 = {
3721− /* B */
3722− RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3723− RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3724− RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3725− RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3726− /* G */
3727− RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3728− RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3729− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3730− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3731− /* R */
3732− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3733− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3734− RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3735− RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3736− },
3635+static const unsigned int vin0_data_pins[] = {
3636+ /* B */
3637+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3638+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3639+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3640+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3641+ /* G */
3642+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3643+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3644+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3645+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3646+ /* R */
3647+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3648+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3649+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3650+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
37373651 };
3738−static const union vin_data vin0_data_mux = {
3739− .data24 = {
3740− /* B */
3741− VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3742− VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3743− VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3744− VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3745− /* G */
3746− VI0_G0_MARK, VI0_G1_MARK,
3747− VI0_G2_MARK, VI0_G3_MARK,
3748− VI0_G4_MARK, VI0_G5_MARK,
3749− VI0_G6_MARK, VI0_G7_MARK,
3750− /* R */
3751− VI0_R0_MARK, VI0_R1_MARK,
3752− VI0_R2_MARK, VI0_R3_MARK,
3753− VI0_R4_MARK, VI0_R5_MARK,
3754− VI0_R6_MARK, VI0_R7_MARK,
3755− },
3652+static const unsigned int vin0_data_mux[] = {
3653+ /* B */
3654+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3655+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3656+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3657+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3658+ /* G */
3659+ VI0_G0_MARK, VI0_G1_MARK,
3660+ VI0_G2_MARK, VI0_G3_MARK,
3661+ VI0_G4_MARK, VI0_G5_MARK,
3662+ VI0_G6_MARK, VI0_G7_MARK,
3663+ /* R */
3664+ VI0_R0_MARK, VI0_R1_MARK,
3665+ VI0_R2_MARK, VI0_R3_MARK,
3666+ VI0_R4_MARK, VI0_R5_MARK,
3667+ VI0_R6_MARK, VI0_R7_MARK,
37563668 };
37573669 static const unsigned int vin0_data18_pins[] = {
37583670 /* B */
@@ -3809,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = { · 50 unmodified lines
38093721 VI0_CLK_MARK,
38103722 };
38113723 /* - VIN1 ------------------------------------------------------------------- */
3812−static const union vin_data vin1_data_pins = {
3813− .data24 = {
3814− /* B */
3815− RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3816− RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3817− RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3818− RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3819− /* G */
3820− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3821− RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3822− RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3823− RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3824− /* R */
3825− RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3826− RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3827− RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3828− RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3829− },
3724+static const unsigned int vin1_data_pins[] = {
3725+ /* B */
3726+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3727+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3728+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3729+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3730+ /* G */
3731+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3732+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3733+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3734+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3735+ /* R */
3736+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3737+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3738+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3739+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
38303740 };
3831−static const union vin_data vin1_data_mux = {
3832− .data24 = {
3833− /* B */
3834− VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3835− VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3836− VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3837− VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3838− /* G */
3839− VI1_G0_MARK, VI1_G1_MARK,
3840− VI1_G2_MARK, VI1_G3_MARK,
3841− VI1_G4_MARK, VI1_G5_MARK,
3842− VI1_G6_MARK, VI1_G7_MARK,
3843− /* R */
3844− VI1_R0_MARK, VI1_R1_MARK,
3845− VI1_R2_MARK, VI1_R3_MARK,
3846− VI1_R4_MARK, VI1_R5_MARK,
3847− VI1_R6_MARK, VI1_R7_MARK,
3848− },
3741+static const unsigned int vin1_data_mux[] = {
3742+ /* B */
3743+ VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3744+ VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3745+ VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3746+ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3747+ /* G */
3748+ VI1_G0_MARK, VI1_G1_MARK,
3749+ VI1_G2_MARK, VI1_G3_MARK,
3750+ VI1_G4_MARK, VI1_G5_MARK,
3751+ VI1_G6_MARK, VI1_G7_MARK,
3752+ /* R */
3753+ VI1_R0_MARK, VI1_R1_MARK,
3754+ VI1_R2_MARK, VI1_R3_MARK,
3755+ VI1_R4_MARK, VI1_R5_MARK,
3756+ VI1_R6_MARK, VI1_R7_MARK,
38493757 };
38503758 static const unsigned int vin1_data18_pins[] = {
38513759 /* B */
@@ -3875,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = { · 23 unmodified lines
38753783 VI1_R4_MARK, VI1_R5_MARK,
38763784 VI1_R6_MARK, VI1_R7_MARK,
38773785 };
3878−static const union vin_data vin1_data_b_pins = {
3879− .data24 = {
3880− /* B */
3881− RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3882− RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3883− RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3884− RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3885− /* G */
3886− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3887− RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3888− RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3889− RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3890− /* R */
3891− RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3892− RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3893− RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3894− RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3895− },
3786+static const unsigned int vin1_data_b_pins[] = {
3787+ /* B */
3788+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3789+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3790+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3791+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3792+ /* G */
3793+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3794+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3795+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3796+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3797+ /* R */
3798+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3799+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3800+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3801+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
38963802 };
3897−static const union vin_data vin1_data_b_mux = {
3898− .data24 = {
3899− /* B */
3900− VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3901− VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3902− VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3903− VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3904− /* G */
3905− VI1_G0_B_MARK, VI1_G1_B_MARK,
3906− VI1_G2_B_MARK, VI1_G3_B_MARK,
3907− VI1_G4_B_MARK, VI1_G5_B_MARK,
3908− VI1_G6_B_MARK, VI1_G7_B_MARK,
3909− /* R */
3910− VI1_R0_B_MARK, VI1_R1_B_MARK,
3911− VI1_R2_B_MARK, VI1_R3_B_MARK,
3912− VI1_R4_B_MARK, VI1_R5_B_MARK,
3913− VI1_R6_B_MARK, VI1_R7_B_MARK,
3914− },
3803+static const unsigned int vin1_data_b_mux[] = {
3804+ /* B */
3805+ VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3806+ VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3807+ VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3808+ VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3809+ /* G */
3810+ VI1_G0_B_MARK, VI1_G1_B_MARK,
3811+ VI1_G2_B_MARK, VI1_G3_B_MARK,
3812+ VI1_G4_B_MARK, VI1_G5_B_MARK,
3813+ VI1_G6_B_MARK, VI1_G7_B_MARK,
3814+ /* R */
3815+ VI1_R0_B_MARK, VI1_R1_B_MARK,
3816+ VI1_R2_B_MARK, VI1_R3_B_MARK,
3817+ VI1_R4_B_MARK, VI1_R5_B_MARK,
3818+ VI1_R6_B_MARK, VI1_R7_B_MARK,
39153819 };
39163820 static const unsigned int vin1_data18_b_pins[] = {
39173821 /* B */
@@ -3994,83 +3898,67 @@ static const unsigned int vin1_clk_b_mux[] = { · 76 unmodified lines
39943898 VI1_CLK_B_MARK,
39953899 };
39963900 /* - VIN2 ----------------------------------------------------------------- */
3997−static const union vin_data vin2_data_pins = {
3998− .data24 = {
3999− /* B */
4000− RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4001− RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4002− RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4003− RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4004− /* G */
4005− RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
4006− RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
4007− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4008− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4009− /* R */
4010− RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4011− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4012− RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
4013− RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
4014− },
4015−};
4016−static const union vin_data vin2_data_mux = {
4017− .data24 = {
4018− /* B */
4019− VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
4020− VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
4021− VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
4022− VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
4023− /* G */
4024− VI2_G0_MARK, VI2_G1_MARK,
4025− VI2_G2_MARK, VI2_G3_MARK,
4026− VI2_G4_MARK, VI2_G5_MARK,
4027− VI2_G6_MARK, VI2_G7_MARK,
4028− /* R */
4029− VI2_R0_MARK, VI2_R1_MARK,
4030− VI2_R2_MARK, VI2_R3_MARK,
4031− VI2_R4_MARK, VI2_R5_MARK,
4032− VI2_R6_MARK, VI2_R7_MARK,
4033− },
4034−};
4035−static const unsigned int vin2_data18_pins[] = {
3901+static const unsigned int vin2_data_pins[] = {
40363902 /* B */
3903+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
40373904 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
40383905 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
40393906 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
40403907 /* G */
3908+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
40413909 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
40423910 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
40433911 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
40443912 /* R */
3913+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
40453914 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
40463915 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
40473916 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
40483917 };
4049−static const unsigned int vin2_data18_mux[] = {
3918+static const unsigned int vin2_data_mux[] = {
40503919 /* B */
3920+ VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
40513921 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
40523922 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
40533923 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
40543924 /* G */
3925+ VI2_G0_MARK, VI2_G1_MARK,
40553926 VI2_G2_MARK, VI2_G3_MARK,
40563927 VI2_G4_MARK, VI2_G5_MARK,
40573928 VI2_G6_MARK, VI2_G7_MARK,
40583929 /* R */
3930+ VI2_R0_MARK, VI2_R1_MARK,
40593931 VI2_R2_MARK, VI2_R3_MARK,
40603932 VI2_R4_MARK, VI2_R5_MARK,
40613933 VI2_R6_MARK, VI2_R7_MARK,
40623934 };
4063−static const unsigned int vin2_g8_pins[] = {
4064− RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3935+static const unsigned int vin2_data18_pins[] = {
3936+ /* B */
3937+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3938+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3939+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3940+ /* G */
40653941 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
40663942 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
40673943 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3944+ /* R */
3945+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3946+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3947+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
40683948 };
4069−static const unsigned int vin2_g8_mux[] = {
4070− VI2_G0_MARK, VI2_G1_MARK,
3949+static const unsigned int vin2_data18_mux[] = {
3950+ /* B */
3951+ VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3952+ VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3953+ VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3954+ /* G */
40713955 VI2_G2_MARK, VI2_G3_MARK,
40723956 VI2_G4_MARK, VI2_G5_MARK,
40733957 VI2_G6_MARK, VI2_G7_MARK,
3958+ /* R */
3959+ VI2_R2_MARK, VI2_R3_MARK,
3960+ VI2_R4_MARK, VI2_R5_MARK,
3961+ VI2_R6_MARK, VI2_R7_MARK,
40743962 };
40753963 static const unsigned int vin2_sync_pins[] = {
40763964 RCAR_GP_PIN(1, 16), /* HSYNC */
@@ -4223,13 +4111,13 @@ static const struct { · 146 unmodified lines
42234111 SH_PFC_PIN_GROUP(intc_irq1),
42244112 SH_PFC_PIN_GROUP(intc_irq2),
42254113 SH_PFC_PIN_GROUP(intc_irq3),
4226− SH_PFC_PIN_GROUP(mmc0_data1),
4227− SH_PFC_PIN_GROUP(mmc0_data4),
4228− SH_PFC_PIN_GROUP(mmc0_data8),
4114+ BUS_DATA_PIN_GROUP(mmc0_data, 1),
4115+ BUS_DATA_PIN_GROUP(mmc0_data, 4),
4116+ BUS_DATA_PIN_GROUP(mmc0_data, 8),
42294117 SH_PFC_PIN_GROUP(mmc0_ctrl),
4230− SH_PFC_PIN_GROUP(mmc1_data1),
4231− SH_PFC_PIN_GROUP(mmc1_data4),
4232− SH_PFC_PIN_GROUP(mmc1_data8),
4118+ BUS_DATA_PIN_GROUP(mmc1_data, 1),
4119+ BUS_DATA_PIN_GROUP(mmc1_data, 4),
4120+ BUS_DATA_PIN_GROUP(mmc1_data, 8),
42334121 SH_PFC_PIN_GROUP(mmc1_ctrl),
42344122 SH_PFC_PIN_GROUP(msiof0_clk),
42354123 SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4279,8 +4167,8 @@ static const struct { · 43 unmodified lines
42794167 SH_PFC_PIN_GROUP(pwm5),
42804168 SH_PFC_PIN_GROUP(pwm6),
42814169 SH_PFC_PIN_GROUP(qspi_ctrl),
4282− SH_PFC_PIN_GROUP(qspi_data2),
4283− SH_PFC_PIN_GROUP(qspi_data4),
4170+ BUS_DATA_PIN_GROUP(qspi_data, 2),
4171+ BUS_DATA_PIN_GROUP(qspi_data, 4),
42844172 SH_PFC_PIN_GROUP(scif0_data),
42854173 SH_PFC_PIN_GROUP(scif0_clk),
42864174 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4350,23 +4238,23 @@ static const struct { · 63 unmodified lines
43504238 SH_PFC_PIN_GROUP(scifb2_data_c),
43514239 SH_PFC_PIN_GROUP(scif_clk),
43524240 SH_PFC_PIN_GROUP(scif_clk_b),
4353− SH_PFC_PIN_GROUP(sdhi0_data1),
4354− SH_PFC_PIN_GROUP(sdhi0_data4),
4241+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4242+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
43554243 SH_PFC_PIN_GROUP(sdhi0_ctrl),
43564244 SH_PFC_PIN_GROUP(sdhi0_cd),
43574245 SH_PFC_PIN_GROUP(sdhi0_wp),
4358− SH_PFC_PIN_GROUP(sdhi1_data1),
4359− SH_PFC_PIN_GROUP(sdhi1_data4),
4246+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4247+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
43604248 SH_PFC_PIN_GROUP(sdhi1_ctrl),
43614249 SH_PFC_PIN_GROUP(sdhi1_cd),
43624250 SH_PFC_PIN_GROUP(sdhi1_wp),
4363− SH_PFC_PIN_GROUP(sdhi2_data1),
4364− SH_PFC_PIN_GROUP(sdhi2_data4),
4251+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4252+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
43654253 SH_PFC_PIN_GROUP(sdhi2_ctrl),
43664254 SH_PFC_PIN_GROUP(sdhi2_cd),
43674255 SH_PFC_PIN_GROUP(sdhi2_wp),
4368− SH_PFC_PIN_GROUP(sdhi3_data1),
4369− SH_PFC_PIN_GROUP(sdhi3_data4),
4256+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4257+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
43704258 SH_PFC_PIN_GROUP(sdhi3_ctrl),
43714259 SH_PFC_PIN_GROUP(sdhi3_cd),
43724260 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -4401,38 +4289,38 @@ static const struct { · 28 unmodified lines
44014289 SH_PFC_PIN_GROUP(tpu0_to2),
44024290 SH_PFC_PIN_GROUP(tpu0_to3),
44034291 SH_PFC_PIN_GROUP(usb0),
4404− SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4292+ SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
44054293 SH_PFC_PIN_GROUP(usb1),
4406− SH_PFC_PIN_GROUP(usb1_pwen),
4294+ SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
44074295 SH_PFC_PIN_GROUP(usb2),
4408− VIN_DATA_PIN_GROUP(vin0_data, 24),
4409− VIN_DATA_PIN_GROUP(vin0_data, 20),
4296+ BUS_DATA_PIN_GROUP(vin0_data, 24),
4297+ BUS_DATA_PIN_GROUP(vin0_data, 20),
44104298 SH_PFC_PIN_GROUP(vin0_data18),
4411− VIN_DATA_PIN_GROUP(vin0_data, 16),
4412− VIN_DATA_PIN_GROUP(vin0_data, 12),
4413− VIN_DATA_PIN_GROUP(vin0_data, 10),
4414− VIN_DATA_PIN_GROUP(vin0_data, 8),
4415− VIN_DATA_PIN_GROUP(vin0_data, 4),
4299+ BUS_DATA_PIN_GROUP(vin0_data, 16),
4300+ BUS_DATA_PIN_GROUP(vin0_data, 12),
4301+ BUS_DATA_PIN_GROUP(vin0_data, 10),
4302+ BUS_DATA_PIN_GROUP(vin0_data, 8),
4303+ BUS_DATA_PIN_GROUP(vin0_data, 4),
44164304 SH_PFC_PIN_GROUP(vin0_sync),
44174305 SH_PFC_PIN_GROUP(vin0_field),
44184306 SH_PFC_PIN_GROUP(vin0_clkenb),
44194307 SH_PFC_PIN_GROUP(vin0_clk),
4420− VIN_DATA_PIN_GROUP(vin1_data, 24),
4421− VIN_DATA_PIN_GROUP(vin1_data, 20),
4308+ BUS_DATA_PIN_GROUP(vin1_data, 24),
4309+ BUS_DATA_PIN_GROUP(vin1_data, 20),
44224310 SH_PFC_PIN_GROUP(vin1_data18),
4423− VIN_DATA_PIN_GROUP(vin1_data, 16),
4424− VIN_DATA_PIN_GROUP(vin1_data, 12),
4425− VIN_DATA_PIN_GROUP(vin1_data, 10),
4426− VIN_DATA_PIN_GROUP(vin1_data, 8),
4427− VIN_DATA_PIN_GROUP(vin1_data, 4),
4428− VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4429− VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4311+ BUS_DATA_PIN_GROUP(vin1_data, 16),
4312+ BUS_DATA_PIN_GROUP(vin1_data, 12),
4313+ BUS_DATA_PIN_GROUP(vin1_data, 10),
4314+ BUS_DATA_PIN_GROUP(vin1_data, 8),
4315+ BUS_DATA_PIN_GROUP(vin1_data, 4),
4316+ BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4317+ BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
44304318 SH_PFC_PIN_GROUP(vin1_data18_b),
4431− VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4432− VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4433− VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4434− VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4435− VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
4319+ BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4320+ BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4321+ BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4322+ BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
4323+ BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
44364324 SH_PFC_PIN_GROUP(vin1_sync),
44374325 SH_PFC_PIN_GROUP(vin1_sync_b),
44384326 SH_PFC_PIN_GROUP(vin1_field),
@@ -4441,12 +4329,12 @@ static const struct { · 2 unmodified lines
44414329 SH_PFC_PIN_GROUP(vin1_clkenb_b),
44424330 SH_PFC_PIN_GROUP(vin1_clk),
44434331 SH_PFC_PIN_GROUP(vin1_clk_b),
4444− VIN_DATA_PIN_GROUP(vin2_data, 24),
4332+ BUS_DATA_PIN_GROUP(vin2_data, 24),
44454333 SH_PFC_PIN_GROUP(vin2_data18),
4446− VIN_DATA_PIN_GROUP(vin2_data, 16),
4447− VIN_DATA_PIN_GROUP(vin2_data, 8),
4448− VIN_DATA_PIN_GROUP(vin2_data, 4),
4449− SH_PFC_PIN_GROUP(vin2_g8),
4334+ BUS_DATA_PIN_GROUP(vin2_data, 16),
4335+ BUS_DATA_PIN_GROUP(vin2_data, 8),
4336+ BUS_DATA_PIN_GROUP(vin2_data, 4),
4337+ SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
44504338 SH_PFC_PIN_GROUP(vin2_sync),
44514339 SH_PFC_PIN_GROUP(vin2_field),
44524340 SH_PFC_PIN_GROUP(vin2_clkenb),
@@ -4964,10 +4852,10 @@ static const struct { · 511 unmodified lines
49644852 .common = {
49654853 SH_PFC_FUNCTION(audio_clk),
49664854 SH_PFC_FUNCTION(avb),
4967− SH_PFC_FUNCTION(du),
49684855 SH_PFC_FUNCTION(can0),
49694856 SH_PFC_FUNCTION(can1),
49704857 SH_PFC_FUNCTION(can_clk),
4858+ SH_PFC_FUNCTION(du),
49714859 SH_PFC_FUNCTION(du0),
49724860 SH_PFC_FUNCTION(du1),
49734861 SH_PFC_FUNCTION(du2),
@@ -5415,9 +5303,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 441 unmodified lines
54155303 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
54165304 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
54175305 /* IP5_26_24 [3] */
5418− FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5419− FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5420− FN_MSIOF0_SCK_B, 0,
5306+ FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
5307+ FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
54215308 /* IP5_23_21 [3] */
54225309 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
54235310 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
@@ -5426,7 +5313,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 2 unmodified lines
54265313 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
54275314 /* IP5_17_15 [3] */
54285315 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5429− FN_INTC_IRQ4_N, 0, 0,
5316+ 0, 0, 0,
54305317 /* IP5_14_13 [2] */
54315318 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
54325319 /* IP5_12_10 [3] */
@@ -5467,19 +5354,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 34 unmodified lines
54675354 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
54685355 FN_I2C2_SCL_E, 0,
54695356 /* IP6_13_11 [3] */
5470− FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5471− FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5357+ FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
5358+ FN_MSIOF0_RXD_B, 0, 0,
54725359 /* IP6_10_9 [2] */
54735360 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
54745361 /* IP6_8_6 [3] */
5475− FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5476− FN_SSI_SDATA8_C, 0, 0, 0,
5362+ FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
54775363 /* IP6_5_3 [3] */
54785364 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
54795365 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
54805366 /* IP6_2_0 [3] */
5481− FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5482− FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5367+ FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
5368+ FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
54835369 },
54845370 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
54855371 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
@@ -5987,7 +5873,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 501 unmodified lines
59875873 { },
59885874 };
59895875
5990−static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5876+static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
59915877 {
59925878 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
59935879 return -EINVAL;
@@ -6289,7 +6175,7 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) · 295 unmodified lines
62896175 return 0;
62906176 }
62916177
6292−static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
6178+static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
62936179 .init = r8a7790_pinmux_soc_init,
62946180 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
62956181 .get_bias = rcar_pinmux_get_bias,
@@ -6299,7 +6185,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { · 3 unmodified lines
62996185 #ifdef CONFIG_PINCTRL_PFC_R8A7742
63006186 const struct sh_pfc_soc_info r8a7742_pinmux_info = {
63016187 .name = "r8a77420_pfc",
6302− .ops = &r8a7790_pinmux_ops,
6188+ .ops = &r8a7790_pfc_ops,
63036189 .unlock_reg = 0xe6060000, /* PMMR */
63046190
63056191 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6322,7 +6208,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = { · 16 unmodified lines
63226208 #ifdef CONFIG_PINCTRL_PFC_R8A7790
63236209 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
63246210 .name = "r8a77900_pfc",
6325− .ops = &r8a7790_pinmux_ops,
6211+ .ops = &r8a7790_pfc_ops,
63266212 .unlock_reg = 0xe6060000, /* PMMR */
63276213
63286214 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a7791.c+126−196
@@ -234,11 +234,11 @@ enum { · 233 unmodified lines
234234 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
235235 FN_SCIFA2_RXD, FN_FMIN_E,
236236 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
237− FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
238− FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
239− FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
240− FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
241− FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
237+ FN_IRQ0, FN_SCIFB1_RXD_D,
238+ FN_IRQ1, FN_SCIFB1_SCK_C,
239+ FN_IRQ2, FN_SCIFB1_TXD_D,
240+ FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
241+ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
242242 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
243243 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
244244 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
@@ -606,12 +606,12 @@ enum { · 361 unmodified lines
606606 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
607607 SCIFA2_RXD_MARK, FMIN_E_MARK,
608608 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
609− IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
610− IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
611− IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
612− IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
609+ IRQ0_MARK, SCIFB1_RXD_D_MARK,
610+ IRQ1_MARK, SCIFB1_SCK_C_MARK,
611+ IRQ2_MARK, SCIFB1_TXD_D_MARK,
612+ IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
613613 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
614− MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
614+ MSIOF2_RXD_E_MARK,
615615 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
616616 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
617617 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
@@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = { · 522 unmodified lines
11401140 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
11411141 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
11421142 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1143− PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
11441143 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
11451144 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1146− PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
11471145 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
11481146 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1149− PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
11501147 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
11511148 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
11521149 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1153− PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
11541150 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
11551151 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
11561152 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
11571153 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1158− PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
11591154 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
11601155 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
11611156 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
@@ -2303,13 +2298,6 @@ static const unsigned int hscif1_data_d_pins[] = { · 1141 unmodified lines
23032298 static const unsigned int hscif1_data_d_mux[] = {
23042299 HRX1_D_MARK, HTX1_D_MARK,
23052300 };
2306−static const unsigned int hscif1_data_e_pins[] = {
2307− /* RX, TX */
2308− RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2309−};
2310−static const unsigned int hscif1_data_e_mux[] = {
2311− HRX1_C_MARK, HTX1_C_MARK,
2312−};
23132301 static const unsigned int hscif1_clk_e_pins[] = {
23142302 /* SCK */
23152303 RCAR_GP_PIN(2, 6),
@@ -2604,40 +2592,25 @@ static const unsigned int mlb_3pin_mux[] = { · 288 unmodified lines
26042592 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
26052593
26062594 /* - MMCIF ------------------------------------------------------------------ */
2607−static const unsigned int mmc_data1_pins[] = {
2608− /* D[0] */
2609− RCAR_GP_PIN(6, 18),
2610−};
2611−static const unsigned int mmc_data1_mux[] = {
2612− MMC_D0_MARK,
2613−};
2614−static const unsigned int mmc_data4_pins[] = {
2615− /* D[0:3] */
2616− RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2617− RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2618−};
2619−static const unsigned int mmc_data4_mux[] = {
2620− MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2621−};
2622−static const unsigned int mmc_data8_pins[] = {
2595+static const unsigned int mmc_data_pins[] = {
26232596 /* D[0:7] */
26242597 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
26252598 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
26262599 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
26272600 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
26282601 };
2629−static const unsigned int mmc_data8_mux[] = {
2602+static const unsigned int mmc_data_mux[] = {
26302603 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
26312604 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
26322605 };
2633−static const unsigned int mmc_data8_b_pins[] = {
2606+static const unsigned int mmc_data_b_pins[] = {
26342607 /* D[0:7] */
26352608 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
26362609 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
26372610 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
26382611 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
26392612 };
2640−static const unsigned int mmc_data8_b_mux[] = {
2613+static const unsigned int mmc_data_b_mux[] = {
26412614 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
26422615 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
26432616 };
@@ -3225,19 +3198,12 @@ static const unsigned int qspi_ctrl_pins[] = { · 581 unmodified lines
32253198 static const unsigned int qspi_ctrl_mux[] = {
32263199 SPCLK_MARK, SSL_MARK,
32273200 };
3228−static const unsigned int qspi_data2_pins[] = {
3229− /* MOSI_IO0, MISO_IO1 */
3230− RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3231−};
3232−static const unsigned int qspi_data2_mux[] = {
3233− MOSI_IO0_MARK, MISO_IO1_MARK,
3234−};
3235−static const unsigned int qspi_data4_pins[] = {
3201+static const unsigned int qspi_data_pins[] = {
32363202 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
32373203 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
32383204 RCAR_GP_PIN(1, 8),
32393205 };
3240−static const unsigned int qspi_data4_mux[] = {
3206+static const unsigned int qspi_data_mux[] = {
32413207 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
32423208 };
32433209
@@ -3248,19 +3214,12 @@ static const unsigned int qspi_ctrl_b_pins[] = { · 4 unmodified lines
32483214 static const unsigned int qspi_ctrl_b_mux[] = {
32493215 SPCLK_B_MARK, SSL_B_MARK,
32503216 };
3251−static const unsigned int qspi_data2_b_pins[] = {
3252− /* MOSI_IO0, MISO_IO1 */
3253− RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3254−};
3255−static const unsigned int qspi_data2_b_mux[] = {
3256− MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3257−};
3258−static const unsigned int qspi_data4_b_pins[] = {
3217+static const unsigned int qspi_data_b_pins[] = {
32593218 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
32603219 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
32613220 RCAR_GP_PIN(6, 4),
32623221 };
3263−static const unsigned int qspi_data4_b_mux[] = {
3222+static const unsigned int qspi_data_b_mux[] = {
32643223 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
32653224 };
32663225 /* - SCIF0 ------------------------------------------------------------------ */
@@ -3821,19 +3780,12 @@ static const unsigned int scif_clk_b_mux[] = { · 554 unmodified lines
38213780 };
38223781
38233782 /* - SDHI0 ------------------------------------------------------------------ */
3824−static const unsigned int sdhi0_data1_pins[] = {
3825− /* D0 */
3826− RCAR_GP_PIN(6, 2),
3827−};
3828−static const unsigned int sdhi0_data1_mux[] = {
3829− SD0_DATA0_MARK,
3830−};
3831−static const unsigned int sdhi0_data4_pins[] = {
3783+static const unsigned int sdhi0_data_pins[] = {
38323784 /* D[0:3] */
38333785 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
38343786 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
38353787 };
3836−static const unsigned int sdhi0_data4_mux[] = {
3788+static const unsigned int sdhi0_data_mux[] = {
38373789 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
38383790 };
38393791 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -3858,19 +3810,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
38583810 SD0_WP_MARK,
38593811 };
38603812 /* - SDHI1 ------------------------------------------------------------------ */
3861−static const unsigned int sdhi1_data1_pins[] = {
3862− /* D0 */
3863− RCAR_GP_PIN(6, 10),
3864−};
3865−static const unsigned int sdhi1_data1_mux[] = {
3866− SD1_DATA0_MARK,
3867−};
3868−static const unsigned int sdhi1_data4_pins[] = {
3813+static const unsigned int sdhi1_data_pins[] = {
38693814 /* D[0:3] */
38703815 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
38713816 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
38723817 };
3873−static const unsigned int sdhi1_data4_mux[] = {
3818+static const unsigned int sdhi1_data_mux[] = {
38743819 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
38753820 };
38763821 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -3895,19 +3840,12 @@ static const unsigned int sdhi1_wp_mux[] = { · 18 unmodified lines
38953840 SD1_WP_MARK,
38963841 };
38973842 /* - SDHI2 ------------------------------------------------------------------ */
3898−static const unsigned int sdhi2_data1_pins[] = {
3899− /* D0 */
3900− RCAR_GP_PIN(6, 18),
3901−};
3902−static const unsigned int sdhi2_data1_mux[] = {
3903− SD2_DATA0_MARK,
3904−};
3905−static const unsigned int sdhi2_data4_pins[] = {
3843+static const unsigned int sdhi2_data_pins[] = {
39063844 /* D[0:3] */
39073845 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
39083846 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
39093847 };
3910−static const unsigned int sdhi2_data4_mux[] = {
3848+static const unsigned int sdhi2_data_mux[] = {
39113849 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
39123850 };
39133851 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -4230,43 +4168,39 @@ static const unsigned int usb1_mux[] = { · 316 unmodified lines
42304168 USB1_OVC_MARK,
42314169 };
42324170 /* - VIN0 ------------------------------------------------------------------- */
4233−static const union vin_data vin0_data_pins = {
4234− .data24 = {
4235− /* B */
4236− RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4237− RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4238− RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4239− RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4240− /* G */
4241− RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4242− RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4243− RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4244− RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4245− /* R */
4246− RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4247− RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4248− RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4249− RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4250− },
4171+static const unsigned int vin0_data_pins[] = {
4172+ /* B */
4173+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4174+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4175+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4176+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4177+ /* G */
4178+ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4179+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4180+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4181+ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4182+ /* R */
4183+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4184+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4185+ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4186+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
42514187 };
4252−static const union vin_data vin0_data_mux = {
4253− .data24 = {
4254− /* B */
4255− VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4256− VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4257− VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4258− VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4259− /* G */
4260− VI0_G0_MARK, VI0_G1_MARK,
4261− VI0_G2_MARK, VI0_G3_MARK,
4262− VI0_G4_MARK, VI0_G5_MARK,
4263− VI0_G6_MARK, VI0_G7_MARK,
4264− /* R */
4265− VI0_R0_MARK, VI0_R1_MARK,
4266− VI0_R2_MARK, VI0_R3_MARK,
4267− VI0_R4_MARK, VI0_R5_MARK,
4268− VI0_R6_MARK, VI0_R7_MARK,
4269− },
4188+static const unsigned int vin0_data_mux[] = {
4189+ /* B */
4190+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4191+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4192+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4193+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4194+ /* G */
4195+ VI0_G0_MARK, VI0_G1_MARK,
4196+ VI0_G2_MARK, VI0_G3_MARK,
4197+ VI0_G4_MARK, VI0_G5_MARK,
4198+ VI0_G6_MARK, VI0_G7_MARK,
4199+ /* R */
4200+ VI0_R0_MARK, VI0_R1_MARK,
4201+ VI0_R2_MARK, VI0_R3_MARK,
4202+ VI0_R4_MARK, VI0_R5_MARK,
4203+ VI0_R6_MARK, VI0_R7_MARK,
42704204 };
42714205 static const unsigned int vin0_data18_pins[] = {
42724206 /* B */
@@ -4361,43 +4295,39 @@ static const unsigned int vin1_clk_pins[] = { · 88 unmodified lines
43614295 static const unsigned int vin1_clk_mux[] = {
43624296 VI1_CLK_MARK,
43634297 };
4364−static const union vin_data vin1_data_b_pins = {
4365− .data24 = {
4366− /* B */
4367− RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4368− RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4369− RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4370− RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4371− /* G */
4372− RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4373− RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4374− RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4375− RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4376− /* R */
4377− RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4378− RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4379− RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4380− RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4381− },
4298+static const unsigned int vin1_data_b_pins[] = {
4299+ /* B */
4300+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4301+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4302+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4303+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4304+ /* G */
4305+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4306+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4307+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4308+ RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4309+ /* R */
4310+ RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4311+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4312+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4313+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
43824314 };
4383−static const union vin_data vin1_data_b_mux = {
4384− .data24 = {
4385− /* B */
4386− VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4387− VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4388− VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4389− VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4390− /* G */
4391− VI1_G0_B_MARK, VI1_G1_B_MARK,
4392− VI1_G2_B_MARK, VI1_G3_B_MARK,
4393− VI1_G4_B_MARK, VI1_G5_B_MARK,
4394− VI1_G6_B_MARK, VI1_G7_B_MARK,
4395− /* R */
4396− VI1_R0_B_MARK, VI1_R1_B_MARK,
4397− VI1_R2_B_MARK, VI1_R3_B_MARK,
4398− VI1_R4_B_MARK, VI1_R5_B_MARK,
4399− VI1_R6_B_MARK, VI1_R7_B_MARK,
4400− },
4315+static const unsigned int vin1_data_b_mux[] = {
4316+ /* B */
4317+ VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4318+ VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4319+ VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4320+ VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4321+ /* G */
4322+ VI1_G0_B_MARK, VI1_G1_B_MARK,
4323+ VI1_G2_B_MARK, VI1_G3_B_MARK,
4324+ VI1_G4_B_MARK, VI1_G5_B_MARK,
4325+ VI1_G6_B_MARK, VI1_G7_B_MARK,
4326+ /* R */
4327+ VI1_R0_B_MARK, VI1_R1_B_MARK,
4328+ VI1_R2_B_MARK, VI1_R3_B_MARK,
4329+ VI1_R4_B_MARK, VI1_R5_B_MARK,
4330+ VI1_R6_B_MARK, VI1_R7_B_MARK,
44014331 };
44024332 static const unsigned int vin1_data18_b_pins[] = {
44034333 /* B */
@@ -4556,7 +4486,7 @@ static const struct { · 152 unmodified lines
45564486 SH_PFC_PIN_GROUP(hscif1_clk_c),
45574487 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
45584488 SH_PFC_PIN_GROUP(hscif1_data_d),
4559− SH_PFC_PIN_GROUP(hscif1_data_e),
4489+ SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
45604490 SH_PFC_PIN_GROUP(hscif1_clk_e),
45614491 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
45624492 SH_PFC_PIN_GROUP(hscif2_data),
@@ -4596,10 +4526,10 @@ static const struct { · 33 unmodified lines
45964526 SH_PFC_PIN_GROUP(intc_irq1),
45974527 SH_PFC_PIN_GROUP(intc_irq2),
45984528 SH_PFC_PIN_GROUP(intc_irq3),
4599− SH_PFC_PIN_GROUP(mmc_data1),
4600− SH_PFC_PIN_GROUP(mmc_data4),
4601− SH_PFC_PIN_GROUP(mmc_data8),
4602− SH_PFC_PIN_GROUP(mmc_data8_b),
4529+ BUS_DATA_PIN_GROUP(mmc_data, 1),
4530+ BUS_DATA_PIN_GROUP(mmc_data, 4),
4531+ BUS_DATA_PIN_GROUP(mmc_data, 8),
4532+ BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
46034533 SH_PFC_PIN_GROUP(mmc_ctrl),
46044534 SH_PFC_PIN_GROUP(msiof0_clk),
46054535 SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4683,11 +4613,11 @@ static const struct { · 77 unmodified lines
46834613 SH_PFC_PIN_GROUP(pwm5_b),
46844614 SH_PFC_PIN_GROUP(pwm6),
46854615 SH_PFC_PIN_GROUP(qspi_ctrl),
4686− SH_PFC_PIN_GROUP(qspi_data2),
4687− SH_PFC_PIN_GROUP(qspi_data4),
4616+ BUS_DATA_PIN_GROUP(qspi_data, 2),
4617+ BUS_DATA_PIN_GROUP(qspi_data, 4),
46884618 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4689− SH_PFC_PIN_GROUP(qspi_data2_b),
4690− SH_PFC_PIN_GROUP(qspi_data4_b),
4619+ BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
4620+ BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
46914621 SH_PFC_PIN_GROUP(scif0_data),
46924622 SH_PFC_PIN_GROUP(scif0_data_b),
46934623 SH_PFC_PIN_GROUP(scif0_data_c),
@@ -4765,18 +4695,18 @@ static const struct { · 71 unmodified lines
47654695 SH_PFC_PIN_GROUP(scifb2_data_d),
47664696 SH_PFC_PIN_GROUP(scif_clk),
47674697 SH_PFC_PIN_GROUP(scif_clk_b),
4768− SH_PFC_PIN_GROUP(sdhi0_data1),
4769− SH_PFC_PIN_GROUP(sdhi0_data4),
4698+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4699+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
47704700 SH_PFC_PIN_GROUP(sdhi0_ctrl),
47714701 SH_PFC_PIN_GROUP(sdhi0_cd),
47724702 SH_PFC_PIN_GROUP(sdhi0_wp),
4773− SH_PFC_PIN_GROUP(sdhi1_data1),
4774− SH_PFC_PIN_GROUP(sdhi1_data4),
4703+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4704+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
47754705 SH_PFC_PIN_GROUP(sdhi1_ctrl),
47764706 SH_PFC_PIN_GROUP(sdhi1_cd),
47774707 SH_PFC_PIN_GROUP(sdhi1_wp),
4778− SH_PFC_PIN_GROUP(sdhi2_data1),
4779− SH_PFC_PIN_GROUP(sdhi2_data4),
4708+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4709+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
47804710 SH_PFC_PIN_GROUP(sdhi2_ctrl),
47814711 SH_PFC_PIN_GROUP(sdhi2_cd),
47824712 SH_PFC_PIN_GROUP(sdhi2_wp),
@@ -4814,13 +4744,13 @@ static const struct { · 31 unmodified lines
48144744 SH_PFC_PIN_GROUP(tpu_to3),
48154745 SH_PFC_PIN_GROUP(usb0),
48164746 SH_PFC_PIN_GROUP(usb1),
4817− VIN_DATA_PIN_GROUP(vin0_data, 24),
4818− VIN_DATA_PIN_GROUP(vin0_data, 20),
4747+ BUS_DATA_PIN_GROUP(vin0_data, 24),
4748+ BUS_DATA_PIN_GROUP(vin0_data, 20),
48194749 SH_PFC_PIN_GROUP(vin0_data18),
4820− VIN_DATA_PIN_GROUP(vin0_data, 16),
4821− VIN_DATA_PIN_GROUP(vin0_data, 12),
4822− VIN_DATA_PIN_GROUP(vin0_data, 10),
4823− VIN_DATA_PIN_GROUP(vin0_data, 8),
4750+ BUS_DATA_PIN_GROUP(vin0_data, 16),
4751+ BUS_DATA_PIN_GROUP(vin0_data, 12),
4752+ BUS_DATA_PIN_GROUP(vin0_data, 10),
4753+ BUS_DATA_PIN_GROUP(vin0_data, 8),
48244754 SH_PFC_PIN_GROUP(vin0_sync),
48254755 SH_PFC_PIN_GROUP(vin0_field),
48264756 SH_PFC_PIN_GROUP(vin0_clkenb),
@@ -4830,13 +4760,13 @@ static const struct { · 3 unmodified lines
48304760 SH_PFC_PIN_GROUP(vin1_field),
48314761 SH_PFC_PIN_GROUP(vin1_clkenb),
48324762 SH_PFC_PIN_GROUP(vin1_clk),
4833− VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4834− VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4763+ BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4764+ BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
48354765 SH_PFC_PIN_GROUP(vin1_data18_b),
4836− VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4837− VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4838− VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4839− VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4766+ BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4767+ BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4768+ BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4769+ BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
48404770 SH_PFC_PIN_GROUP(vin1_sync_b),
48414771 SH_PFC_PIN_GROUP(vin1_field_b),
48424772 SH_PFC_PIN_GROUP(vin1_clkenb_b),
@@ -6033,15 +5963,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 1190 unmodified lines
60335963 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
60345964 /* IP6_18_16 [3] */
60355965 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
6036− FN_INTC_IRQ4_N, 0, 0, 0,
5966+ 0, 0, 0, 0,
60375967 /* IP6_15_14 [2] */
6038− FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5968+ FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
60395969 /* IP6_13_12 [2] */
6040− FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5970+ FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
60415971 /* IP6_11_10 [2] */
6042− FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5972+ FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
60435973 /* IP6_9_8 [2] */
6044− FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5974+ FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
60455975 /* IP6_7_6 [2] */
60465976 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
60475977 /* IP6_5_3 [3] */
@@ -6672,7 +6602,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 624 unmodified lines
66726602 { },
66736603 };
66746604
6675−static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6605+static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
66766606 {
66776607 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
66786608 return -EINVAL;
@@ -6994,7 +6924,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 315 unmodified lines
69946924 { /* sentinel */ },
69956925 };
69966926
6997−static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6927+static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
69986928 .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
69996929 .get_bias = rcar_pinmux_get_bias,
70006930 .set_bias = rcar_pinmux_set_bias,
@@ -7003,7 +6933,7 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { · 2 unmodified lines
70036933 #ifdef CONFIG_PINCTRL_PFC_R8A7743
70046934 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
70056935 .name = "r8a77430_pfc",
7006− .ops = &r8a7791_pinmux_ops,
6936+ .ops = &r8a7791_pfc_ops,
70076937 .unlock_reg = 0xe6060000, /* PMMR */
70086938
70096939 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -7026,7 +6956,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { · 16 unmodified lines
70266956 #ifdef CONFIG_PINCTRL_PFC_R8A7744
70276957 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
70286958 .name = "r8a77440_pfc",
7029− .ops = &r8a7791_pinmux_ops,
6959+ .ops = &r8a7791_pfc_ops,
70306960 .unlock_reg = 0xe6060000, /* PMMR */
70316961
70326962 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -7049,7 +6979,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { · 16 unmodified lines
70496979 #ifdef CONFIG_PINCTRL_PFC_R8A7791
70506980 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
70516981 .name = "r8a77910_pfc",
7052− .ops = &r8a7791_pinmux_ops,
6982+ .ops = &r8a7791_pfc_ops,
70536983 .unlock_reg = 0xe6060000, /* PMMR */
70546984
70556985 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -7074,7 +7004,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { · 18 unmodified lines
70747004 #ifdef CONFIG_PINCTRL_PFC_R8A7793
70757005 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
70767006 .name = "r8a77930_pfc",
7077− .ops = &r8a7791_pinmux_ops,
7007+ .ops = &r8a7791_pfc_ops,
70787008 .unlock_reg = 0xe6060000, /* PMMR */
70797009
70807010 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a7792.c+202−244
@@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = { · 1115 unmodified lines
11161116 static const unsigned int qspi_ctrl_mux[] = {
11171117 SPCLK_MARK, SSL_MARK,
11181118 };
1119−static const unsigned int qspi_data2_pins[] = {
1120− /* MOSI_IO0, MISO_IO1 */
1121− RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1122−};
1123−static const unsigned int qspi_data2_mux[] = {
1124− MOSI_IO0_MARK, MISO_IO1_MARK,
1125−};
1126−static const unsigned int qspi_data4_pins[] = {
1119+static const unsigned int qspi_data_pins[] = {
11271120 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
11281121 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
11291122 RCAR_GP_PIN(3, 24),
11301123 };
1131−static const unsigned int qspi_data4_mux[] = {
1124+static const unsigned int qspi_data_mux[] = {
11321125 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
11331126 };
11341127 /* - SCIF0 ------------------------------------------------------------------ */
@@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = { · 71 unmodified lines
12061199 SCK3_MARK,
12071200 };
12081201 /* - SDHI0 ------------------------------------------------------------------ */
1209−static const unsigned int sdhi0_data1_pins[] = {
1210− /* DAT0 */
1211− RCAR_GP_PIN(11, 7),
1212−};
1213−static const unsigned int sdhi0_data1_mux[] = {
1214− SD0_DAT0_MARK,
1215−};
1216−static const unsigned int sdhi0_data4_pins[] = {
1202+static const unsigned int sdhi0_data_pins[] = {
12171203 /* DAT[0-3] */
12181204 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
12191205 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
12201206 };
1221−static const unsigned int sdhi0_data4_mux[] = {
1207+static const unsigned int sdhi0_data_mux[] = {
12221208 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
12231209 };
12241210 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
12431229 SD0_WP_MARK,
12441230 };
12451231 /* - VIN0 ------------------------------------------------------------------- */
1246−static const union vin_data vin0_data_pins = {
1247− .data24 = {
1248− /* B */
1249− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1250− RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1251− RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1252− RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1253− /* G */
1254− RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1255− RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1256− RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1257− RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1258− /* R */
1259− RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1260− RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1261− RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1262− RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1263− },
1232+static const unsigned int vin0_data_pins[] = {
1233+ /* B */
1234+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1235+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1236+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1237+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1238+ /* G */
1239+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1240+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1241+ RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1242+ RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1243+ /* R */
1244+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1245+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1246+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1247+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
12641248 };
1265−static const union vin_data vin0_data_mux = {
1266− .data24 = {
1267− /* B */
1268− VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1269− VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1270− VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1271− VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1272− /* G */
1273− VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1274− VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1275− VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1276− VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1277− /* R */
1278− VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1279− VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1280− VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1281− VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1282− },
1249+static const unsigned int vin0_data_mux[] = {
1250+ /* B */
1251+ VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1252+ VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1253+ VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1254+ VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1255+ /* G */
1256+ VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1257+ VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1258+ VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1259+ VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1260+ /* R */
1261+ VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1262+ VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1263+ VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1264+ VI0_D22_R6_MARK, VI0_D23_R7_MARK,
12831265 };
12841266 static const unsigned int vin0_data18_pins[] = {
12851267 /* B */
@@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = { · 49 unmodified lines
13351317 VI0_CLK_MARK,
13361318 };
13371319 /* - VIN1 ------------------------------------------------------------------- */
1338−static const union vin_data vin1_data_pins = {
1339− .data24 = {
1340− /* B */
1341− RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1342− RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1343− RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1344− RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1345− /* G */
1346− RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1347− RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1348− RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1349− RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1350− /* R */
1351− RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1352− RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1353− RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1354− RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1355− },
1320+static const unsigned int vin1_data_pins[] = {
1321+ /* B */
1322+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1323+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1324+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1325+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1326+ /* G */
1327+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1328+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1329+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1330+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1331+ /* R */
1332+ RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1333+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1334+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1335+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
13561336 };
1357−static const union vin_data vin1_data_mux = {
1358− .data24 = {
1359− /* B */
1360− VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1361− VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1362− VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1363− VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1364− /* G */
1365− VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1366− VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1367− VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1368− VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1369− /* R */
1370− VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1371− VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1372− VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1373− VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1374− },
1337+static const unsigned int vin1_data_mux[] = {
1338+ /* B */
1339+ VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1340+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1341+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1342+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1343+ /* G */
1344+ VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1345+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1346+ VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1347+ VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1348+ /* R */
1349+ VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1350+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1351+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1352+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
13751353 };
13761354 static const unsigned int vin1_data18_pins[] = {
13771355 /* B */
@@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = { · 23 unmodified lines
14011379 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
14021380 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
14031381 };
1404−static const union vin_data vin1_data_b_pins = {
1405− .data24 = {
1406− /* B */
1407− RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1408− RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1409− RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1410− RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1411− /* G */
1412− RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1413− RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1414− RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1415− RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1416− /* R */
1417− RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1418− RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1419− RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1420− RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1421− },
1382+static const unsigned int vin1_data_b_pins[] = {
1383+ /* B */
1384+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1385+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1386+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1387+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1388+ /* G */
1389+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1390+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1391+ RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1392+ RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1393+ /* R */
1394+ RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1395+ RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1396+ RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1397+ RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
14221398 };
1423−static const union vin_data vin1_data_b_mux = {
1424− .data24 = {
1425− /* B */
1426− VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1427− VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1428− VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1429− VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1430− /* G */
1431− VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1432− VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1433− VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1434− VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1435− /* R */
1436− VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1437− VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1438− VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1439− VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1440− },
1399+static const unsigned int vin1_data_b_mux[] = {
1400+ /* B */
1401+ VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1402+ VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1403+ VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1404+ VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1405+ /* G */
1406+ VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1407+ VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1408+ VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1409+ VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1410+ /* R */
1411+ VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1412+ VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1413+ VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1414+ VI1_D22_R6_MARK, VI1_D23_R7_MARK,
14411415 };
14421416 static const unsigned int vin1_data18_b_pins[] = {
14431417 /* B */
@@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = { · 49 unmodified lines
14931467 VI1_CLK_MARK,
14941468 };
14951469 /* - VIN2 ------------------------------------------------------------------- */
1496−static const union vin_data16 vin2_data_pins = {
1497− .data16 = {
1498− RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1499− RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1500− RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1501− RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1502− RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1503− RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1504− RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1505− RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1506− },
1470+static const unsigned int vin2_data_pins[] = {
1471+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1472+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1473+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1474+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1475+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1476+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1477+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1478+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
15071479 };
1508−static const union vin_data16 vin2_data_mux = {
1509− .data16 = {
1510− VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1511− VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1512− VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1513− VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1514− VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1515− VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1516− VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1517− VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1518− },
1480+static const unsigned int vin2_data_mux[] = {
1481+ VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1482+ VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1483+ VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1484+ VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1485+ VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1486+ VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1487+ VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1488+ VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
15191489 };
15201490 static const unsigned int vin2_sync_pins[] = {
15211491 /* HSYNC#, VSYNC# */
@@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = { · 21 unmodified lines
15431513 VI2_CLK_MARK,
15441514 };
15451515 /* - VIN3 ------------------------------------------------------------------- */
1546−static const union vin_data16 vin3_data_pins = {
1547− .data16 = {
1548− RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1549− RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1550− RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1551− RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1552− RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1553− RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1554− RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1555− RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1556− },
1557−};
1558−static const union vin_data16 vin3_data_mux = {
1559− .data16 = {
1560− VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1561− VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1562− VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1563− VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1564− VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1565− VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1566− VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1567− VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1568− },
1516+static const unsigned int vin3_data_pins[] = {
1517+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1518+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1519+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1520+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1521+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1522+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1523+ RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1524+ RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1525+};
1526+static const unsigned int vin3_data_mux[] = {
1527+ VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1528+ VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1529+ VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1530+ VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1531+ VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1532+ VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1533+ VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1534+ VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
15691535 };
15701536 static const unsigned int vin3_sync_pins[] = {
15711537 /* HSYNC#, VSYNC# */
@@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = { · 21 unmodified lines
15931559 VI3_CLK_MARK,
15941560 };
15951561 /* - VIN4 ------------------------------------------------------------------- */
1596−static const union vin_data12 vin4_data_pins = {
1597− .data12 = {
1598− RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1599− RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1600− RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1601− RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1602− RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1603− RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1604− },
1605−};
1606−static const union vin_data12 vin4_data_mux = {
1607− .data12 = {
1608− VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1609− VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1610− VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1611− VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1612− VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1613− VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1614− },
1562+static const unsigned int vin4_data_pins[] = {
1563+ RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1564+ RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1565+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1566+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1567+ RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1568+ RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1569+};
1570+static const unsigned int vin4_data_mux[] = {
1571+ VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1572+ VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1573+ VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1574+ VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1575+ VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1576+ VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
16151577 };
16161578 static const unsigned int vin4_sync_pins[] = {
16171579 /* HSYNC#, VSYNC# */
@@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = { · 21 unmodified lines
16391601 VI4_CLK_MARK,
16401602 };
16411603 /* - VIN5 ------------------------------------------------------------------- */
1642−static const union vin_data12 vin5_data_pins = {
1643− .data12 = {
1644− RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1645− RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1646− RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1647− RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1648− RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1649− RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1650− },
1651−};
1652−static const union vin_data12 vin5_data_mux = {
1653− .data12 = {
1654− VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1655− VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1656− VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1657− VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1658− VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1659− VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1660− },
1604+static const unsigned int vin5_data_pins[] = {
1605+ RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1606+ RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1607+ RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1608+ RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1609+ RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1610+ RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1611+};
1612+static const unsigned int vin5_data_mux[] = {
1613+ VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1614+ VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1615+ VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1616+ VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1617+ VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1618+ VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
16611619 };
16621620 static const unsigned int vin5_sync_pins[] = {
16631621 /* HSYNC#, VSYNC# */
@@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 64 unmodified lines
17281686 SH_PFC_PIN_GROUP(msiof1_rx),
17291687 SH_PFC_PIN_GROUP(msiof1_tx),
17301688 SH_PFC_PIN_GROUP(qspi_ctrl),
1731− SH_PFC_PIN_GROUP(qspi_data2),
1732− SH_PFC_PIN_GROUP(qspi_data4),
1689+ BUS_DATA_PIN_GROUP(qspi_data, 2),
1690+ BUS_DATA_PIN_GROUP(qspi_data, 4),
17331691 SH_PFC_PIN_GROUP(scif0_data),
17341692 SH_PFC_PIN_GROUP(scif0_clk),
17351693 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 4 unmodified lines
17401698 SH_PFC_PIN_GROUP(scif2_clk),
17411699 SH_PFC_PIN_GROUP(scif3_data),
17421700 SH_PFC_PIN_GROUP(scif3_clk),
1743− SH_PFC_PIN_GROUP(sdhi0_data1),
1744− SH_PFC_PIN_GROUP(sdhi0_data4),
1701+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1702+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
17451703 SH_PFC_PIN_GROUP(sdhi0_ctrl),
17461704 SH_PFC_PIN_GROUP(sdhi0_cd),
17471705 SH_PFC_PIN_GROUP(sdhi0_wp),
1748− VIN_DATA_PIN_GROUP(vin0_data, 24),
1749− VIN_DATA_PIN_GROUP(vin0_data, 20),
1706+ BUS_DATA_PIN_GROUP(vin0_data, 24),
1707+ BUS_DATA_PIN_GROUP(vin0_data, 20),
17501708 SH_PFC_PIN_GROUP(vin0_data18),
1751− VIN_DATA_PIN_GROUP(vin0_data, 16),
1752− VIN_DATA_PIN_GROUP(vin0_data, 12),
1753− VIN_DATA_PIN_GROUP(vin0_data, 10),
1754− VIN_DATA_PIN_GROUP(vin0_data, 8),
1709+ BUS_DATA_PIN_GROUP(vin0_data, 16),
1710+ BUS_DATA_PIN_GROUP(vin0_data, 12),
1711+ BUS_DATA_PIN_GROUP(vin0_data, 10),
1712+ BUS_DATA_PIN_GROUP(vin0_data, 8),
17551713 SH_PFC_PIN_GROUP(vin0_sync),
17561714 SH_PFC_PIN_GROUP(vin0_field),
17571715 SH_PFC_PIN_GROUP(vin0_clkenb),
17581716 SH_PFC_PIN_GROUP(vin0_clk),
1759− VIN_DATA_PIN_GROUP(vin1_data, 24),
1760− VIN_DATA_PIN_GROUP(vin1_data, 20),
1717+ BUS_DATA_PIN_GROUP(vin1_data, 24),
1718+ BUS_DATA_PIN_GROUP(vin1_data, 20),
17611719 SH_PFC_PIN_GROUP(vin1_data18),
1762− VIN_DATA_PIN_GROUP(vin1_data, 16),
1763− VIN_DATA_PIN_GROUP(vin1_data, 12),
1764− VIN_DATA_PIN_GROUP(vin1_data, 10),
1765− VIN_DATA_PIN_GROUP(vin1_data, 8),
1766− VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
1767− VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
1720+ BUS_DATA_PIN_GROUP(vin1_data, 16),
1721+ BUS_DATA_PIN_GROUP(vin1_data, 12),
1722+ BUS_DATA_PIN_GROUP(vin1_data, 10),
1723+ BUS_DATA_PIN_GROUP(vin1_data, 8),
1724+ BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
1725+ BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
17681726 SH_PFC_PIN_GROUP(vin1_data18_b),
1769− VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
1727+ BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
17701728 SH_PFC_PIN_GROUP(vin1_sync),
17711729 SH_PFC_PIN_GROUP(vin1_field),
17721730 SH_PFC_PIN_GROUP(vin1_clkenb),
17731731 SH_PFC_PIN_GROUP(vin1_clk),
1774− VIN_DATA_PIN_GROUP(vin2_data, 16),
1775− VIN_DATA_PIN_GROUP(vin2_data, 12),
1776− VIN_DATA_PIN_GROUP(vin2_data, 10),
1777− VIN_DATA_PIN_GROUP(vin2_data, 8),
1732+ BUS_DATA_PIN_GROUP(vin2_data, 16),
1733+ BUS_DATA_PIN_GROUP(vin2_data, 12),
1734+ BUS_DATA_PIN_GROUP(vin2_data, 10),
1735+ BUS_DATA_PIN_GROUP(vin2_data, 8),
17781736 SH_PFC_PIN_GROUP(vin2_sync),
17791737 SH_PFC_PIN_GROUP(vin2_field),
17801738 SH_PFC_PIN_GROUP(vin2_clkenb),
17811739 SH_PFC_PIN_GROUP(vin2_clk),
1782− VIN_DATA_PIN_GROUP(vin3_data, 16),
1783− VIN_DATA_PIN_GROUP(vin3_data, 12),
1784− VIN_DATA_PIN_GROUP(vin3_data, 10),
1785− VIN_DATA_PIN_GROUP(vin3_data, 8),
1740+ BUS_DATA_PIN_GROUP(vin3_data, 16),
1741+ BUS_DATA_PIN_GROUP(vin3_data, 12),
1742+ BUS_DATA_PIN_GROUP(vin3_data, 10),
1743+ BUS_DATA_PIN_GROUP(vin3_data, 8),
17861744 SH_PFC_PIN_GROUP(vin3_sync),
17871745 SH_PFC_PIN_GROUP(vin3_field),
17881746 SH_PFC_PIN_GROUP(vin3_clkenb),
17891747 SH_PFC_PIN_GROUP(vin3_clk),
1790− VIN_DATA_PIN_GROUP(vin4_data, 12),
1791− VIN_DATA_PIN_GROUP(vin4_data, 10),
1792− VIN_DATA_PIN_GROUP(vin4_data, 8),
1748+ BUS_DATA_PIN_GROUP(vin4_data, 12),
1749+ BUS_DATA_PIN_GROUP(vin4_data, 10),
1750+ BUS_DATA_PIN_GROUP(vin4_data, 8),
17931751 SH_PFC_PIN_GROUP(vin4_sync),
17941752 SH_PFC_PIN_GROUP(vin4_field),
17951753 SH_PFC_PIN_GROUP(vin4_clkenb),
17961754 SH_PFC_PIN_GROUP(vin4_clk),
1797− VIN_DATA_PIN_GROUP(vin5_data, 12),
1798− VIN_DATA_PIN_GROUP(vin5_data, 10),
1799− VIN_DATA_PIN_GROUP(vin5_data, 8),
1755+ BUS_DATA_PIN_GROUP(vin5_data, 12),
1756+ BUS_DATA_PIN_GROUP(vin5_data, 10),
1757+ BUS_DATA_PIN_GROUP(vin5_data, 8),
18001758 SH_PFC_PIN_GROUP(vin5_sync),
18011759 SH_PFC_PIN_GROUP(vin5_field),
18021760 SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 1478 unmodified lines
32813239 { /* sentinel */ }
32823240 };
32833241
3284−static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {
3242+static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
32853243 .get_bias = rcar_pinmux_get_bias,
32863244 .set_bias = rcar_pinmux_set_bias,
32873245 };
32883246
32893247 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
32903248 .name = "r8a77920_pfc",
3291− .ops = &r8a7792_pinmux_ops,
3249+ .ops = &r8a7792_pfc_ops,
32923250 .unlock_reg = 0xe6060000, /* PMMR */
32933251
32943252 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a7794.c+83−131
@@ -2388,29 +2388,14 @@ static const unsigned int intc_irq9_mux[] = { · 2387 unmodified lines
23882388 IRQ9_MARK,
23892389 };
23902390 /* - MMCIF ------------------------------------------------------------------ */
2391−static const unsigned int mmc_data1_pins[] = {
2392− /* D[0] */
2393− RCAR_GP_PIN(6, 18),
2394−};
2395−static const unsigned int mmc_data1_mux[] = {
2396− MMC_D0_MARK,
2397−};
2398−static const unsigned int mmc_data4_pins[] = {
2399− /* D[0:3] */
2400− RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2401− RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2402−};
2403−static const unsigned int mmc_data4_mux[] = {
2404− MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2405−};
2406−static const unsigned int mmc_data8_pins[] = {
2391+static const unsigned int mmc_data_pins[] = {
24072392 /* D[0:7] */
24082393 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
24092394 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
24102395 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
24112396 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
24122397 };
2413−static const unsigned int mmc_data8_mux[] = {
2398+static const unsigned int mmc_data_mux[] = {
24142399 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
24152400 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
24162401 };
@@ -2745,19 +2730,12 @@ static const unsigned int qspi_ctrl_pins[] = { · 328 unmodified lines
27452730 static const unsigned int qspi_ctrl_mux[] = {
27462731 SPCLK_MARK, SSL_MARK,
27472732 };
2748−static const unsigned int qspi_data2_pins[] = {
2749− /* MOSI_IO0, MISO_IO1 */
2750− RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2751−};
2752−static const unsigned int qspi_data2_mux[] = {
2753− MOSI_IO0_MARK, MISO_IO1_MARK,
2754−};
2755−static const unsigned int qspi_data4_pins[] = {
2733+static const unsigned int qspi_data_pins[] = {
27562734 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
27572735 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
27582736 RCAR_GP_PIN(1, 8),
27592737 };
2760−static const unsigned int qspi_data4_mux[] = {
2738+static const unsigned int qspi_data_mux[] = {
27612739 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
27622740 };
27632741 /* - SCIF0 ------------------------------------------------------------------ */
@@ -3232,19 +3210,12 @@ static const unsigned int scif_clk_b_mux[] = { · 468 unmodified lines
32323210 SCIF_CLK_B_MARK,
32333211 };
32343212 /* - SDHI0 ------------------------------------------------------------------ */
3235−static const unsigned int sdhi0_data1_pins[] = {
3236− /* D0 */
3237− RCAR_GP_PIN(6, 2),
3238−};
3239−static const unsigned int sdhi0_data1_mux[] = {
3240− SD0_DATA0_MARK,
3241−};
3242−static const unsigned int sdhi0_data4_pins[] = {
3213+static const unsigned int sdhi0_data_pins[] = {
32433214 /* D[0:3] */
32443215 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
32453216 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
32463217 };
3247−static const unsigned int sdhi0_data4_mux[] = {
3218+static const unsigned int sdhi0_data_mux[] = {
32483219 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
32493220 };
32503221 static const unsigned int sdhi0_ctrl_pins[] = {
@@ -3269,19 +3240,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 18 unmodified lines
32693240 SD0_WP_MARK,
32703241 };
32713242 /* - SDHI1 ------------------------------------------------------------------ */
3272−static const unsigned int sdhi1_data1_pins[] = {
3273− /* D0 */
3274− RCAR_GP_PIN(6, 10),
3275−};
3276−static const unsigned int sdhi1_data1_mux[] = {
3277− SD1_DATA0_MARK,
3278−};
3279−static const unsigned int sdhi1_data4_pins[] = {
3243+static const unsigned int sdhi1_data_pins[] = {
32803244 /* D[0:3] */
32813245 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
32823246 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
32833247 };
3284−static const unsigned int sdhi1_data4_mux[] = {
3248+static const unsigned int sdhi1_data_mux[] = {
32853249 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
32863250 };
32873251 static const unsigned int sdhi1_ctrl_pins[] = {
@@ -3306,19 +3270,12 @@ static const unsigned int sdhi1_wp_mux[] = { · 18 unmodified lines
33063270 SD1_WP_MARK,
33073271 };
33083272 /* - SDHI2 ------------------------------------------------------------------ */
3309−static const unsigned int sdhi2_data1_pins[] = {
3310− /* D0 */
3311− RCAR_GP_PIN(6, 18),
3312−};
3313−static const unsigned int sdhi2_data1_mux[] = {
3314− SD2_DATA0_MARK,
3315−};
3316−static const unsigned int sdhi2_data4_pins[] = {
3273+static const unsigned int sdhi2_data_pins[] = {
33173274 /* D[0:3] */
33183275 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
33193276 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
33203277 };
3321−static const unsigned int sdhi2_data4_mux[] = {
3278+static const unsigned int sdhi2_data_mux[] = {
33223279 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
33233280 };
33243281 static const unsigned int sdhi2_ctrl_pins[] = {
@@ -3673,43 +3630,39 @@ static const unsigned int usb1_mux[] = { · 348 unmodified lines
36733630 USB1_OVC_MARK,
36743631 };
36753632 /* - VIN0 ------------------------------------------------------------------- */
3676−static const union vin_data vin0_data_pins = {
3677− .data24 = {
3678− /* B */
3679− RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3680− RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3681− RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3682− RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3683− /* G */
3684− RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3685− RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3686− RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3687− RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3688− /* R */
3689− RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3690− RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3691− RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3692− RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3693− },
3633+static const unsigned int vin0_data_pins[] = {
3634+ /* B */
3635+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3636+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3637+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3638+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3639+ /* G */
3640+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3641+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3642+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3643+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3644+ /* R */
3645+ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3646+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3647+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3648+ RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
36943649 };
3695−static const union vin_data vin0_data_mux = {
3696− .data24 = {
3697− /* B */
3698− VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3699− VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3700− VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3701− VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3702− /* G */
3703− VI0_G0_MARK, VI0_G1_MARK,
3704− VI0_G2_MARK, VI0_G3_MARK,
3705− VI0_G4_MARK, VI0_G5_MARK,
3706− VI0_G6_MARK, VI0_G7_MARK,
3707− /* R */
3708− VI0_R0_MARK, VI0_R1_MARK,
3709− VI0_R2_MARK, VI0_R3_MARK,
3710− VI0_R4_MARK, VI0_R5_MARK,
3711− VI0_R6_MARK, VI0_R7_MARK,
3712− },
3650+static const unsigned int vin0_data_mux[] = {
3651+ /* B */
3652+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3653+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3654+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3655+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3656+ /* G */
3657+ VI0_G0_MARK, VI0_G1_MARK,
3658+ VI0_G2_MARK, VI0_G3_MARK,
3659+ VI0_G4_MARK, VI0_G5_MARK,
3660+ VI0_G6_MARK, VI0_G7_MARK,
3661+ /* R */
3662+ VI0_R0_MARK, VI0_R1_MARK,
3663+ VI0_R2_MARK, VI0_R3_MARK,
3664+ VI0_R4_MARK, VI0_R5_MARK,
3665+ VI0_R6_MARK, VI0_R7_MARK,
37133666 };
37143667 static const unsigned int vin0_data18_pins[] = {
37153668 /* B */
@@ -3766,25 +3719,21 @@ static const unsigned int vin0_clk_mux[] = { · 50 unmodified lines
37663719 VI0_CLK_MARK,
37673720 };
37683721 /* - VIN1 ------------------------------------------------------------------- */
3769−static const union vin_data12 vin1_data_pins = {
3770− .data12 = {
3771− RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3772− RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3773− RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3774− RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3775− RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3776− RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3777− },
3722+static const unsigned int vin1_data_pins[] = {
3723+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3724+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3725+ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3726+ RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3727+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3728+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
37783729 };
3779−static const union vin_data12 vin1_data_mux = {
3780− .data12 = {
3781− VI1_DATA0_MARK, VI1_DATA1_MARK,
3782− VI1_DATA2_MARK, VI1_DATA3_MARK,
3783− VI1_DATA4_MARK, VI1_DATA5_MARK,
3784− VI1_DATA6_MARK, VI1_DATA7_MARK,
3785− VI1_DATA8_MARK, VI1_DATA9_MARK,
3786− VI1_DATA10_MARK, VI1_DATA11_MARK,
3787− },
3730+static const unsigned int vin1_data_mux[] = {
3731+ VI1_DATA0_MARK, VI1_DATA1_MARK,
3732+ VI1_DATA2_MARK, VI1_DATA3_MARK,
3733+ VI1_DATA4_MARK, VI1_DATA5_MARK,
3734+ VI1_DATA6_MARK, VI1_DATA7_MARK,
3735+ VI1_DATA8_MARK, VI1_DATA9_MARK,
3736+ VI1_DATA10_MARK, VI1_DATA11_MARK,
37883737 };
37893738 static const unsigned int vin1_sync_pins[] = {
37903739 RCAR_GP_PIN(5, 22), /* HSYNC */
@@ -3923,9 +3872,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 132 unmodified lines
39233872 SH_PFC_PIN_GROUP(intc_irq7),
39243873 SH_PFC_PIN_GROUP(intc_irq8),
39253874 SH_PFC_PIN_GROUP(intc_irq9),
3926− SH_PFC_PIN_GROUP(mmc_data1),
3927− SH_PFC_PIN_GROUP(mmc_data4),
3928− SH_PFC_PIN_GROUP(mmc_data8),
3875+ BUS_DATA_PIN_GROUP(mmc_data, 1),
3876+ BUS_DATA_PIN_GROUP(mmc_data, 4),
3877+ BUS_DATA_PIN_GROUP(mmc_data, 8),
39293878 SH_PFC_PIN_GROUP(mmc_ctrl),
39303879 SH_PFC_PIN_GROUP(msiof0_clk),
39313880 SH_PFC_PIN_GROUP(msiof0_sync),
@@ -3975,8 +3924,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 43 unmodified lines
39753924 SH_PFC_PIN_GROUP(pwm6),
39763925 SH_PFC_PIN_GROUP(pwm6_b),
39773926 SH_PFC_PIN_GROUP(qspi_ctrl),
3978− SH_PFC_PIN_GROUP(qspi_data2),
3979− SH_PFC_PIN_GROUP(qspi_data4),
3927+ BUS_DATA_PIN_GROUP(qspi_data, 2),
3928+ BUS_DATA_PIN_GROUP(qspi_data, 4),
39803929 SH_PFC_PIN_GROUP(scif0_data),
39813930 SH_PFC_PIN_GROUP(scif0_data_b),
39823931 SH_PFC_PIN_GROUP(scif0_data_c),
@@ -4042,18 +3991,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 59 unmodified lines
40423991 SH_PFC_PIN_GROUP(scifb2_ctrl),
40433992 SH_PFC_PIN_GROUP(scif_clk),
40443993 SH_PFC_PIN_GROUP(scif_clk_b),
4045− SH_PFC_PIN_GROUP(sdhi0_data1),
4046− SH_PFC_PIN_GROUP(sdhi0_data4),
3994+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
3995+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
40473996 SH_PFC_PIN_GROUP(sdhi0_ctrl),
40483997 SH_PFC_PIN_GROUP(sdhi0_cd),
40493998 SH_PFC_PIN_GROUP(sdhi0_wp),
4050− SH_PFC_PIN_GROUP(sdhi1_data1),
4051− SH_PFC_PIN_GROUP(sdhi1_data4),
3999+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4000+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
40524001 SH_PFC_PIN_GROUP(sdhi1_ctrl),
40534002 SH_PFC_PIN_GROUP(sdhi1_cd),
40544003 SH_PFC_PIN_GROUP(sdhi1_wp),
4055− SH_PFC_PIN_GROUP(sdhi2_data1),
4056− SH_PFC_PIN_GROUP(sdhi2_data4),
4004+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4005+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
40574006 SH_PFC_PIN_GROUP(sdhi2_ctrl),
40584007 SH_PFC_PIN_GROUP(sdhi2_cd),
40594008 SH_PFC_PIN_GROUP(sdhi2_wp),
@@ -4105,20 +4054,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 45 unmodified lines
41054054 SH_PFC_PIN_GROUP(tpu_to3_c),
41064055 SH_PFC_PIN_GROUP(usb0),
41074056 SH_PFC_PIN_GROUP(usb1),
4108− VIN_DATA_PIN_GROUP(vin0_data, 24),
4109− VIN_DATA_PIN_GROUP(vin0_data, 20),
4057+ BUS_DATA_PIN_GROUP(vin0_data, 24),
4058+ BUS_DATA_PIN_GROUP(vin0_data, 20),
41104059 SH_PFC_PIN_GROUP(vin0_data18),
4111− VIN_DATA_PIN_GROUP(vin0_data, 16),
4112− VIN_DATA_PIN_GROUP(vin0_data, 12),
4113− VIN_DATA_PIN_GROUP(vin0_data, 10),
4114− VIN_DATA_PIN_GROUP(vin0_data, 8),
4060+ BUS_DATA_PIN_GROUP(vin0_data, 16),
4061+ BUS_DATA_PIN_GROUP(vin0_data, 12),
4062+ BUS_DATA_PIN_GROUP(vin0_data, 10),
4063+ BUS_DATA_PIN_GROUP(vin0_data, 8),
41154064 SH_PFC_PIN_GROUP(vin0_sync),
41164065 SH_PFC_PIN_GROUP(vin0_field),
41174066 SH_PFC_PIN_GROUP(vin0_clkenb),
41184067 SH_PFC_PIN_GROUP(vin0_clk),
4119− VIN_DATA_PIN_GROUP(vin1_data, 12),
4120− VIN_DATA_PIN_GROUP(vin1_data, 10),
4121− VIN_DATA_PIN_GROUP(vin1_data, 8),
4068+ BUS_DATA_PIN_GROUP(vin1_data, 12),
4069+ BUS_DATA_PIN_GROUP(vin1_data, 10),
4070+ BUS_DATA_PIN_GROUP(vin1_data, 8),
41224071 SH_PFC_PIN_GROUP(vin1_sync),
41234072 SH_PFC_PIN_GROUP(vin1_field),
41244073 SH_PFC_PIN_GROUP(vin1_clkenb),
@@ -5621,8 +5570,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 1496 unmodified lines
56215570 { },
56225571 };
56235572
5624−static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5573+static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
56255574 {
5575+ if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
5576+ return -EINVAL;
5577+
56265578 *pocctrl = 0xe606006c;
56275579
56285580 switch (pin & 0x1f) {
@@ -5932,7 +5884,7 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) · 303 unmodified lines
59325884 return 0;
59335885 }
59345886
5935−static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5887+static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
59365888 .init = r8a7794_pinmux_soc_init,
59375889 .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
59385890 .get_bias = rcar_pinmux_get_bias,
@@ -5942,7 +5894,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { · 3 unmodified lines
59425894 #ifdef CONFIG_PINCTRL_PFC_R8A7745
59435895 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
59445896 .name = "r8a77450_pfc",
5945− .ops = &r8a7794_pinmux_ops,
5897+ .ops = &r8a7794_pfc_ops,
59465898 .unlock_reg = 0xe6060000, /* PMMR */
59475899
59485900 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -5965,7 +5917,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { · 16 unmodified lines
59655917 #ifdef CONFIG_PINCTRL_PFC_R8A7794
59665918 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
59675919 .name = "r8a77940_pfc",
5968− .ops = &r8a7794_pinmux_ops,
5920+ .ops = &r8a7794_pfc_ops,
59695921 .unlock_reg = 0xe6060000, /* PMMR */
59705922
59715923 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a77950.c+29−90
@@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = { · 3139 unmodified lines
31403140 static const unsigned int qspi0_ctrl_mux[] = {
31413141 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
31423142 };
3143−static const unsigned int qspi0_data2_pins[] = {
3144− /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3145− PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3146−};
3147−static const unsigned int qspi0_data2_mux[] = {
3148− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3149−};
3150−static const unsigned int qspi0_data4_pins[] = {
3143+static const unsigned int qspi0_data_pins[] = {
31513144 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
31523145 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
31533146 };
3154−static const unsigned int qspi0_data4_mux[] = {
3147+static const unsigned int qspi0_data_mux[] = {
31553148 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
31563149 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
31573150 };
@@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = { · 5 unmodified lines
31633156 static const unsigned int qspi1_ctrl_mux[] = {
31643157 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
31653158 };
3166−static const unsigned int qspi1_data2_pins[] = {
3167− /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3168− PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3169−};
3170−static const unsigned int qspi1_data2_mux[] = {
3171− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3172−};
3173−static const unsigned int qspi1_data4_pins[] = {
3159+static const unsigned int qspi1_data_pins[] = {
31743160 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
31753161 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
31763162 };
3177−static const unsigned int qspi1_data4_mux[] = {
3163+static const unsigned int qspi1_data_mux[] = {
31783164 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
31793165 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
31803166 };
@@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = { · 214 unmodified lines
33953381 };
33963382
33973383 /* - SDHI0 ------------------------------------------------------------------ */
3398−static const unsigned int sdhi0_data1_pins[] = {
3399− /* D0 */
3400− RCAR_GP_PIN(3, 2),
3401−};
3402−static const unsigned int sdhi0_data1_mux[] = {
3403− SD0_DAT0_MARK,
3404−};
3405−static const unsigned int sdhi0_data4_pins[] = {
3384+static const unsigned int sdhi0_data_pins[] = {
34063385 /* D[0:3] */
34073386 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
34083387 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
34093388 };
3410−static const unsigned int sdhi0_data4_mux[] = {
3389+static const unsigned int sdhi0_data_mux[] = {
34113390 SD0_DAT0_MARK, SD0_DAT1_MARK,
34123391 SD0_DAT2_MARK, SD0_DAT3_MARK,
34133392 };
@@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 19 unmodified lines
34333412 SD0_WP_MARK,
34343413 };
34353414 /* - SDHI1 ------------------------------------------------------------------ */
3436−static const unsigned int sdhi1_data1_pins[] = {
3437− /* D0 */
3438− RCAR_GP_PIN(3, 8),
3439−};
3440−static const unsigned int sdhi1_data1_mux[] = {
3441− SD1_DAT0_MARK,
3442−};
3443−static const unsigned int sdhi1_data4_pins[] = {
3415+static const unsigned int sdhi1_data_pins[] = {
34443416 /* D[0:3] */
34453417 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
34463418 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
34473419 };
3448−static const unsigned int sdhi1_data4_mux[] = {
3420+static const unsigned int sdhi1_data_mux[] = {
34493421 SD1_DAT0_MARK, SD1_DAT1_MARK,
34503422 SD1_DAT2_MARK, SD1_DAT3_MARK,
34513423 };
@@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = { · 19 unmodified lines
34713443 SD1_WP_MARK,
34723444 };
34733445 /* - SDHI2 ------------------------------------------------------------------ */
3474−static const unsigned int sdhi2_data1_pins[] = {
3475− /* D0 */
3476− RCAR_GP_PIN(4, 2),
3477−};
3478−static const unsigned int sdhi2_data1_mux[] = {
3479− SD2_DAT0_MARK,
3480−};
3481−static const unsigned int sdhi2_data4_pins[] = {
3482− /* D[0:3] */
3483− RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3484− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3485−};
3486−static const unsigned int sdhi2_data4_mux[] = {
3487− SD2_DAT0_MARK, SD2_DAT1_MARK,
3488− SD2_DAT2_MARK, SD2_DAT3_MARK,
3489−};
3490−static const unsigned int sdhi2_data8_pins[] = {
3446+static const unsigned int sdhi2_data_pins[] = {
34913447 /* D[0:7] */
34923448 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
34933449 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
34943450 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
34953451 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
34963452 };
3497−static const unsigned int sdhi2_data8_mux[] = {
3453+static const unsigned int sdhi2_data_mux[] = {
34983454 SD2_DAT0_MARK, SD2_DAT1_MARK,
34993455 SD2_DAT2_MARK, SD2_DAT3_MARK,
35003456 SD2_DAT4_MARK, SD2_DAT5_MARK,
@@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = { · 42 unmodified lines
35433499 SD2_DS_MARK,
35443500 };
35453501 /* - SDHI3 ------------------------------------------------------------------ */
3546−static const unsigned int sdhi3_data1_pins[] = {
3547− /* D0 */
3548− RCAR_GP_PIN(4, 9),
3549−};
3550−static const unsigned int sdhi3_data1_mux[] = {
3551− SD3_DAT0_MARK,
3552−};
3553−static const unsigned int sdhi3_data4_pins[] = {
3554− /* D[0:3] */
3555− RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3556− RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3557−};
3558−static const unsigned int sdhi3_data4_mux[] = {
3559− SD3_DAT0_MARK, SD3_DAT1_MARK,
3560− SD3_DAT2_MARK, SD3_DAT3_MARK,
3561−};
3562−static const unsigned int sdhi3_data8_pins[] = {
3502+static const unsigned int sdhi3_data_pins[] = {
35633503 /* D[0:7] */
35643504 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
35653505 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
35663506 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
35673507 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
35683508 };
3569−static const unsigned int sdhi3_data8_mux[] = {
3509+static const unsigned int sdhi3_data_mux[] = {
35703510 SD3_DAT0_MARK, SD3_DAT1_MARK,
35713511 SD3_DAT2_MARK, SD3_DAT3_MARK,
35723512 SD3_DAT4_MARK, SD3_DAT5_MARK,
@@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 530 unmodified lines
41034043 SH_PFC_PIN_GROUP(pwm6_a),
41044044 SH_PFC_PIN_GROUP(pwm6_b),
41054045 SH_PFC_PIN_GROUP(qspi0_ctrl),
4106− SH_PFC_PIN_GROUP(qspi0_data2),
4107− SH_PFC_PIN_GROUP(qspi0_data4),
4046+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
4047+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
41084048 SH_PFC_PIN_GROUP(qspi1_ctrl),
4109− SH_PFC_PIN_GROUP(qspi1_data2),
4110− SH_PFC_PIN_GROUP(qspi1_data4),
4049+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
4050+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
41114051 SH_PFC_PIN_GROUP(sata0_devslp_a),
41124052 SH_PFC_PIN_GROUP(sata0_devslp_b),
41134053 SH_PFC_PIN_GROUP(scif0_data),
@@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 23 unmodified lines
41374077 SH_PFC_PIN_GROUP(scif5_clk),
41384078 SH_PFC_PIN_GROUP(scif_clk_a),
41394079 SH_PFC_PIN_GROUP(scif_clk_b),
4140− SH_PFC_PIN_GROUP(sdhi0_data1),
4141− SH_PFC_PIN_GROUP(sdhi0_data4),
4080+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4081+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
41424082 SH_PFC_PIN_GROUP(sdhi0_ctrl),
41434083 SH_PFC_PIN_GROUP(sdhi0_cd),
41444084 SH_PFC_PIN_GROUP(sdhi0_wp),
4145− SH_PFC_PIN_GROUP(sdhi1_data1),
4146− SH_PFC_PIN_GROUP(sdhi1_data4),
4085+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4086+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
41474087 SH_PFC_PIN_GROUP(sdhi1_ctrl),
41484088 SH_PFC_PIN_GROUP(sdhi1_cd),
41494089 SH_PFC_PIN_GROUP(sdhi1_wp),
4150− SH_PFC_PIN_GROUP(sdhi2_data1),
4151− SH_PFC_PIN_GROUP(sdhi2_data4),
4152− SH_PFC_PIN_GROUP(sdhi2_data8),
4090+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4091+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4092+ BUS_DATA_PIN_GROUP(sdhi2_data, 8),
41534093 SH_PFC_PIN_GROUP(sdhi2_ctrl),
41544094 SH_PFC_PIN_GROUP(sdhi2_cd_a),
41554095 SH_PFC_PIN_GROUP(sdhi2_wp_a),
41564096 SH_PFC_PIN_GROUP(sdhi2_cd_b),
41574097 SH_PFC_PIN_GROUP(sdhi2_wp_b),
41584098 SH_PFC_PIN_GROUP(sdhi2_ds),
4159− SH_PFC_PIN_GROUP(sdhi3_data1),
4160− SH_PFC_PIN_GROUP(sdhi3_data4),
4161− SH_PFC_PIN_GROUP(sdhi3_data8),
4099+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4100+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4101+ BUS_DATA_PIN_GROUP(sdhi3_data, 8),
41624102 SH_PFC_PIN_GROUP(sdhi3_ctrl),
41634103 SH_PFC_PIN_GROUP(sdhi3_cd),
41644104 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 1409 unmodified lines
55745514 { /* sentinel */ },
55755515 };
55765516
5577−static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5578− u32 *pocctrl)
5517+static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
55795518 {
55805519 int bit = -EINVAL;
55815520
@@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
58325771 { /* sentinel */ },
58335772 };
58345773
5835−static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
5774+static const struct sh_pfc_soc_operations r8a77950_pfc_ops = {
58365775 .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
58375776 .get_bias = rcar_pinmux_get_bias,
58385777 .set_bias = rcar_pinmux_set_bias,
@@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { · 1 unmodified line
58405779
58415780 const struct sh_pfc_soc_info r8a77950_pinmux_info = {
58425781 .name = "r8a77950_pfc",
5843− .ops = &r8a77950_pinmux_ops,
5782+ .ops = &r8a77950_pfc_ops,
58445783 .unlock_reg = 0xe6060000, /* PMMR */
58455784
58465785 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a77951.c+108−205
@@ -3268,20 +3268,13 @@ static const unsigned int qspi0_ctrl_pins[] = { · 3267 unmodified lines
32683268 static const unsigned int qspi0_ctrl_mux[] = {
32693269 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
32703270 };
3271−static const unsigned int qspi0_data2_pins[] = {
3272− /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3273− PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3274−};
3275−static const unsigned int qspi0_data2_mux[] = {
3276− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3277−};
3278−static const unsigned int qspi0_data4_pins[] = {
3271+static const unsigned int qspi0_data_pins[] = {
32793272 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
32803273 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
32813274 /* QSPI0_IO2, QSPI0_IO3 */
32823275 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
32833276 };
3284−static const unsigned int qspi0_data4_mux[] = {
3277+static const unsigned int qspi0_data_mux[] = {
32853278 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
32863279 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
32873280 };
@@ -3293,20 +3286,13 @@ static const unsigned int qspi1_ctrl_pins[] = { · 5 unmodified lines
32933286 static const unsigned int qspi1_ctrl_mux[] = {
32943287 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
32953288 };
3296−static const unsigned int qspi1_data2_pins[] = {
3297− /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3298− PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3299−};
3300−static const unsigned int qspi1_data2_mux[] = {
3301− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3302−};
3303−static const unsigned int qspi1_data4_pins[] = {
3289+static const unsigned int qspi1_data_pins[] = {
33043290 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
33053291 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
33063292 /* QSPI1_IO2, QSPI1_IO3 */
33073293 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
33083294 };
3309−static const unsigned int qspi1_data4_mux[] = {
3295+static const unsigned int qspi1_data_mux[] = {
33103296 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
33113297 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
33123298 };
@@ -3541,19 +3527,12 @@ static const unsigned int scif_clk_b_mux[] = { · 228 unmodified lines
35413527 };
35423528
35433529 /* - SDHI0 ------------------------------------------------------------------ */
3544−static const unsigned int sdhi0_data1_pins[] = {
3545− /* D0 */
3546− RCAR_GP_PIN(3, 2),
3547−};
3548−static const unsigned int sdhi0_data1_mux[] = {
3549− SD0_DAT0_MARK,
3550−};
3551−static const unsigned int sdhi0_data4_pins[] = {
3530+static const unsigned int sdhi0_data_pins[] = {
35523531 /* D[0:3] */
35533532 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
35543533 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
35553534 };
3556−static const unsigned int sdhi0_data4_mux[] = {
3535+static const unsigned int sdhi0_data_mux[] = {
35573536 SD0_DAT0_MARK, SD0_DAT1_MARK,
35583537 SD0_DAT2_MARK, SD0_DAT3_MARK,
35593538 };
@@ -3579,19 +3558,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 19 unmodified lines
35793558 SD0_WP_MARK,
35803559 };
35813560 /* - SDHI1 ------------------------------------------------------------------ */
3582−static const unsigned int sdhi1_data1_pins[] = {
3583− /* D0 */
3584− RCAR_GP_PIN(3, 8),
3585−};
3586−static const unsigned int sdhi1_data1_mux[] = {
3587− SD1_DAT0_MARK,
3588−};
3589−static const unsigned int sdhi1_data4_pins[] = {
3561+static const unsigned int sdhi1_data_pins[] = {
35903562 /* D[0:3] */
35913563 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
35923564 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
35933565 };
3594−static const unsigned int sdhi1_data4_mux[] = {
3566+static const unsigned int sdhi1_data_mux[] = {
35953567 SD1_DAT0_MARK, SD1_DAT1_MARK,
35963568 SD1_DAT2_MARK, SD1_DAT3_MARK,
35973569 };
@@ -3617,30 +3589,14 @@ static const unsigned int sdhi1_wp_mux[] = { · 19 unmodified lines
36173589 SD1_WP_MARK,
36183590 };
36193591 /* - SDHI2 ------------------------------------------------------------------ */
3620−static const unsigned int sdhi2_data1_pins[] = {
3621− /* D0 */
3622− RCAR_GP_PIN(4, 2),
3623−};
3624−static const unsigned int sdhi2_data1_mux[] = {
3625− SD2_DAT0_MARK,
3626−};
3627−static const unsigned int sdhi2_data4_pins[] = {
3628− /* D[0:3] */
3629− RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3630− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3631−};
3632−static const unsigned int sdhi2_data4_mux[] = {
3633− SD2_DAT0_MARK, SD2_DAT1_MARK,
3634− SD2_DAT2_MARK, SD2_DAT3_MARK,
3635−};
3636−static const unsigned int sdhi2_data8_pins[] = {
3592+static const unsigned int sdhi2_data_pins[] = {
36373593 /* D[0:7] */
36383594 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
36393595 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
36403596 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
36413597 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
36423598 };
3643−static const unsigned int sdhi2_data8_mux[] = {
3599+static const unsigned int sdhi2_data_mux[] = {
36443600 SD2_DAT0_MARK, SD2_DAT1_MARK,
36453601 SD2_DAT2_MARK, SD2_DAT3_MARK,
36463602 SD2_DAT4_MARK, SD2_DAT5_MARK,
@@ -3689,30 +3645,14 @@ static const unsigned int sdhi2_ds_mux[] = { · 42 unmodified lines
36893645 SD2_DS_MARK,
36903646 };
36913647 /* - SDHI3 ------------------------------------------------------------------ */
3692−static const unsigned int sdhi3_data1_pins[] = {
3693− /* D0 */
3694− RCAR_GP_PIN(4, 9),
3695−};
3696−static const unsigned int sdhi3_data1_mux[] = {
3697− SD3_DAT0_MARK,
3698−};
3699−static const unsigned int sdhi3_data4_pins[] = {
3700− /* D[0:3] */
3701− RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3702− RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3703−};
3704−static const unsigned int sdhi3_data4_mux[] = {
3705− SD3_DAT0_MARK, SD3_DAT1_MARK,
3706− SD3_DAT2_MARK, SD3_DAT3_MARK,
3707−};
3708−static const unsigned int sdhi3_data8_pins[] = {
3648+static const unsigned int sdhi3_data_pins[] = {
37093649 /* D[0:7] */
37103650 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
37113651 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
37123652 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
37133653 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
37143654 };
3715−static const unsigned int sdhi3_data8_mux[] = {
3655+static const unsigned int sdhi3_data_mux[] = {
37163656 SD3_DAT0_MARK, SD3_DAT1_MARK,
37173657 SD3_DAT2_MARK, SD3_DAT3_MARK,
37183658 SD3_DAT4_MARK, SD3_DAT5_MARK,
@@ -4071,81 +4011,61 @@ static const unsigned int vin4_data18_b_mux[] = { · 352 unmodified lines
40714011 VI4_DATA20_MARK, VI4_DATA21_MARK,
40724012 VI4_DATA22_MARK, VI4_DATA23_MARK,
40734013 };
4074−static const union vin_data vin4_data_a_pins = {
4075− .data24 = {
4076− RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4077− RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4078− RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4079− RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4080− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4081− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4082− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4083− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4084− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4085− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4086− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4087− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4088− },
4089−};
4090−static const union vin_data vin4_data_a_mux = {
4091− .data24 = {
4092− VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4093− VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4094− VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4095− VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4096− VI4_DATA8_MARK, VI4_DATA9_MARK,
4097− VI4_DATA10_MARK, VI4_DATA11_MARK,
4098− VI4_DATA12_MARK, VI4_DATA13_MARK,
4099− VI4_DATA14_MARK, VI4_DATA15_MARK,
4100− VI4_DATA16_MARK, VI4_DATA17_MARK,
4101− VI4_DATA18_MARK, VI4_DATA19_MARK,
4102− VI4_DATA20_MARK, VI4_DATA21_MARK,
4103− VI4_DATA22_MARK, VI4_DATA23_MARK,
4104− },
4105−};
4106−static const union vin_data vin4_data_b_pins = {
4107− .data24 = {
4108− RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4109− RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4110− RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4111− RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4112− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4113− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4114− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4115− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4116− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4117− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4118− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4119− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4120− },
4014+static const unsigned int vin4_data_a_pins[] = {
4015+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4016+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4017+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4018+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4019+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4020+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4021+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4022+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4023+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4024+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4025+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4026+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
41214027 };
4122−static const union vin_data vin4_data_b_mux = {
4123− .data24 = {
4124− VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4125− VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4126− VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4127− VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4128− VI4_DATA8_MARK, VI4_DATA9_MARK,
4129− VI4_DATA10_MARK, VI4_DATA11_MARK,
4130− VI4_DATA12_MARK, VI4_DATA13_MARK,
4131− VI4_DATA14_MARK, VI4_DATA15_MARK,
4132− VI4_DATA16_MARK, VI4_DATA17_MARK,
4133− VI4_DATA18_MARK, VI4_DATA19_MARK,
4134− VI4_DATA20_MARK, VI4_DATA21_MARK,
4135− VI4_DATA22_MARK, VI4_DATA23_MARK,
4136− },
4028+static const unsigned int vin4_data_a_mux[] = {
4029+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4030+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4031+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4032+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4033+ VI4_DATA8_MARK, VI4_DATA9_MARK,
4034+ VI4_DATA10_MARK, VI4_DATA11_MARK,
4035+ VI4_DATA12_MARK, VI4_DATA13_MARK,
4036+ VI4_DATA14_MARK, VI4_DATA15_MARK,
4037+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4038+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4039+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4040+ VI4_DATA22_MARK, VI4_DATA23_MARK,
41374041 };
4138−static const unsigned int vin4_g8_pins[] = {
4139− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4140− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4141− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4142− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4042+static const unsigned int vin4_data_b_pins[] = {
4043+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4044+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4045+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4046+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4047+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4048+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4049+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4050+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4051+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4052+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4053+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4054+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
41434055 };
4144−static const unsigned int vin4_g8_mux[] = {
4056+static const unsigned int vin4_data_b_mux[] = {
4057+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4058+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4059+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4060+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
41454061 VI4_DATA8_MARK, VI4_DATA9_MARK,
41464062 VI4_DATA10_MARK, VI4_DATA11_MARK,
41474063 VI4_DATA12_MARK, VI4_DATA13_MARK,
41484064 VI4_DATA14_MARK, VI4_DATA15_MARK,
4065+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4066+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4067+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4068+ VI4_DATA22_MARK, VI4_DATA23_MARK,
41494069 };
41504070 static const unsigned int vin4_sync_pins[] = {
41514071 /* HSYNC#, VSYNC# */
@@ -4177,37 +4097,21 @@ static const unsigned int vin4_clk_mux[] = { · 25 unmodified lines
41774097 };
41784098
41794099 /* - VIN5 ------------------------------------------------------------------- */
4180−static const union vin_data16 vin5_data_pins = {
4181− .data16 = {
4182− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4183− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4184− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4185− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4186− RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4187− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4188− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4189− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4190− },
4191−};
4192−static const union vin_data16 vin5_data_mux = {
4193− .data16 = {
4194− VI5_DATA0_MARK, VI5_DATA1_MARK,
4195− VI5_DATA2_MARK, VI5_DATA3_MARK,
4196− VI5_DATA4_MARK, VI5_DATA5_MARK,
4197− VI5_DATA6_MARK, VI5_DATA7_MARK,
4198− VI5_DATA8_MARK, VI5_DATA9_MARK,
4199− VI5_DATA10_MARK, VI5_DATA11_MARK,
4200− VI5_DATA12_MARK, VI5_DATA13_MARK,
4201− VI5_DATA14_MARK, VI5_DATA15_MARK,
4202− },
4203−};
4204−static const unsigned int vin5_high8_pins[] = {
4100+static const unsigned int vin5_data_pins[] = {
4101+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4102+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4103+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4104+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
42054105 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
42064106 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4207− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4208− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4107+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4108+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
42094109 };
4210−static const unsigned int vin5_high8_mux[] = {
4110+static const unsigned int vin5_data_mux[] = {
4111+ VI5_DATA0_MARK, VI5_DATA1_MARK,
4112+ VI5_DATA2_MARK, VI5_DATA3_MARK,
4113+ VI5_DATA4_MARK, VI5_DATA5_MARK,
4114+ VI5_DATA6_MARK, VI5_DATA7_MARK,
42114115 VI5_DATA8_MARK, VI5_DATA9_MARK,
42124116 VI5_DATA10_MARK, VI5_DATA11_MARK,
42134117 VI5_DATA12_MARK, VI5_DATA13_MARK,
@@ -4449,11 +4353,11 @@ static const struct { · 235 unmodified lines
44494353 SH_PFC_PIN_GROUP(pwm6_a),
44504354 SH_PFC_PIN_GROUP(pwm6_b),
44514355 SH_PFC_PIN_GROUP(qspi0_ctrl),
4452− SH_PFC_PIN_GROUP(qspi0_data2),
4453− SH_PFC_PIN_GROUP(qspi0_data4),
4356+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
4357+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
44544358 SH_PFC_PIN_GROUP(qspi1_ctrl),
4455− SH_PFC_PIN_GROUP(qspi1_data2),
4456− SH_PFC_PIN_GROUP(qspi1_data4),
4359+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
4360+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
44574361 SH_PFC_PIN_GROUP(sata0_devslp_a),
44584362 SH_PFC_PIN_GROUP(sata0_devslp_b),
44594363 SH_PFC_PIN_GROUP(scif0_data),
@@ -4485,28 +4389,28 @@ static const struct { · 25 unmodified lines
44854389 SH_PFC_PIN_GROUP(scif5_clk_b),
44864390 SH_PFC_PIN_GROUP(scif_clk_a),
44874391 SH_PFC_PIN_GROUP(scif_clk_b),
4488− SH_PFC_PIN_GROUP(sdhi0_data1),
4489− SH_PFC_PIN_GROUP(sdhi0_data4),
4392+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4393+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
44904394 SH_PFC_PIN_GROUP(sdhi0_ctrl),
44914395 SH_PFC_PIN_GROUP(sdhi0_cd),
44924396 SH_PFC_PIN_GROUP(sdhi0_wp),
4493− SH_PFC_PIN_GROUP(sdhi1_data1),
4494− SH_PFC_PIN_GROUP(sdhi1_data4),
4397+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4398+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
44954399 SH_PFC_PIN_GROUP(sdhi1_ctrl),
44964400 SH_PFC_PIN_GROUP(sdhi1_cd),
44974401 SH_PFC_PIN_GROUP(sdhi1_wp),
4498− SH_PFC_PIN_GROUP(sdhi2_data1),
4499− SH_PFC_PIN_GROUP(sdhi2_data4),
4500− SH_PFC_PIN_GROUP(sdhi2_data8),
4402+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4403+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4404+ BUS_DATA_PIN_GROUP(sdhi2_data, 8),
45014405 SH_PFC_PIN_GROUP(sdhi2_ctrl),
45024406 SH_PFC_PIN_GROUP(sdhi2_cd_a),
45034407 SH_PFC_PIN_GROUP(sdhi2_wp_a),
45044408 SH_PFC_PIN_GROUP(sdhi2_cd_b),
45054409 SH_PFC_PIN_GROUP(sdhi2_wp_b),
45064410 SH_PFC_PIN_GROUP(sdhi2_ds),
4507− SH_PFC_PIN_GROUP(sdhi3_data1),
4508− SH_PFC_PIN_GROUP(sdhi3_data4),
4509− SH_PFC_PIN_GROUP(sdhi3_data8),
4411+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4412+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4413+ BUS_DATA_PIN_GROUP(sdhi3_data, 8),
45104414 SH_PFC_PIN_GROUP(sdhi3_ctrl),
45114415 SH_PFC_PIN_GROUP(sdhi3_cd),
45124416 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -4549,30 +4453,30 @@ static const struct { · 36 unmodified lines
45494453 SH_PFC_PIN_GROUP(usb2),
45504454 SH_PFC_PIN_GROUP(usb2_ch3),
45514455 SH_PFC_PIN_GROUP(usb30),
4552− VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4553− VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4554− VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4555− VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4456+ BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4457+ BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4458+ BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4459+ BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
45564460 SH_PFC_PIN_GROUP(vin4_data18_a),
4557− VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4558− VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4559− VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4560− VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4561− VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4562− VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4461+ BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4462+ BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4463+ BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4464+ BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4465+ BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4466+ BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
45634467 SH_PFC_PIN_GROUP(vin4_data18_b),
4564− VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4565− VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4566− SH_PFC_PIN_GROUP(vin4_g8),
4468+ BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4469+ BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4470+ SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
45674471 SH_PFC_PIN_GROUP(vin4_sync),
45684472 SH_PFC_PIN_GROUP(vin4_field),
45694473 SH_PFC_PIN_GROUP(vin4_clkenb),
45704474 SH_PFC_PIN_GROUP(vin4_clk),
4571− VIN_DATA_PIN_GROUP(vin5_data, 8),
4572− VIN_DATA_PIN_GROUP(vin5_data, 10),
4573− VIN_DATA_PIN_GROUP(vin5_data, 12),
4574− VIN_DATA_PIN_GROUP(vin5_data, 16),
4575− SH_PFC_PIN_GROUP(vin5_high8),
4475+ BUS_DATA_PIN_GROUP(vin5_data, 8),
4476+ BUS_DATA_PIN_GROUP(vin5_data, 10),
4477+ BUS_DATA_PIN_GROUP(vin5_data, 12),
4478+ BUS_DATA_PIN_GROUP(vin5_data, 16),
4479+ SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
45764480 SH_PFC_PIN_GROUP(vin5_sync),
45774481 SH_PFC_PIN_GROUP(vin5_field),
45784482 SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -6058,8 +5962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 1479 unmodified lines
60585962 { /* sentinel */ },
60595963 };
60605964
6061−static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
6062− unsigned int pin, u32 *pocctrl)
5965+static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
60635966 {
60645967 int bit = -EINVAL;
60655968
@@ -6316,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
63166219 { /* sentinel */ },
63176220 };
63186221
6319−static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
6222+static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
63206223 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
63216224 .get_bias = rcar_pinmux_get_bias,
63226225 .set_bias = rcar_pinmux_set_bias,
@@ -6325,7 +6228,7 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { · 2 unmodified lines
63256228 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
63266229 const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
63276230 .name = "r8a774e1_pfc",
6328− .ops = &r8a77951_pinmux_ops,
6231+ .ops = &r8a77951_pfc_ops,
63296232 .unlock_reg = 0xe6060000, /* PMMR */
63306233
63316234 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6350,7 +6253,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { · 18 unmodified lines
63506253 #ifdef CONFIG_PINCTRL_PFC_R8A77951
63516254 const struct sh_pfc_soc_info r8a77951_pinmux_info = {
63526255 .name = "r8a77951_pfc",
6353− .ops = &r8a77951_pinmux_ops,
6256+ .ops = &r8a77951_pfc_ops,
63546257 .unlock_reg = 0xe6060000, /* PMMR */
63556258
63566259 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a7796.c+109−206
@@ -3274,20 +3274,13 @@ static const unsigned int qspi0_ctrl_pins[] = { · 3273 unmodified lines
32743274 static const unsigned int qspi0_ctrl_mux[] = {
32753275 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
32763276 };
3277−static const unsigned int qspi0_data2_pins[] = {
3278− /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3279− PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3280−};
3281−static const unsigned int qspi0_data2_mux[] = {
3282− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3283−};
3284−static const unsigned int qspi0_data4_pins[] = {
3277+static const unsigned int qspi0_data_pins[] = {
32853278 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
32863279 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
32873280 /* QSPI0_IO2, QSPI0_IO3 */
32883281 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
32893282 };
3290−static const unsigned int qspi0_data4_mux[] = {
3283+static const unsigned int qspi0_data_mux[] = {
32913284 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
32923285 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
32933286 };
@@ -3299,20 +3292,13 @@ static const unsigned int qspi1_ctrl_pins[] = { · 5 unmodified lines
32993292 static const unsigned int qspi1_ctrl_mux[] = {
33003293 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
33013294 };
3302−static const unsigned int qspi1_data2_pins[] = {
3303− /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3304− PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3305−};
3306−static const unsigned int qspi1_data2_mux[] = {
3307− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3308−};
3309−static const unsigned int qspi1_data4_pins[] = {
3295+static const unsigned int qspi1_data_pins[] = {
33103296 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
33113297 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
33123298 /* QSPI1_IO2, QSPI1_IO3 */
33133299 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
33143300 };
3315−static const unsigned int qspi1_data4_mux[] = {
3301+static const unsigned int qspi1_data_mux[] = {
33163302 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
33173303 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
33183304 };
@@ -3532,19 +3518,12 @@ static const unsigned int scif_clk_b_mux[] = { · 213 unmodified lines
35323518 };
35333519
35343520 /* - SDHI0 ------------------------------------------------------------------ */
3535−static const unsigned int sdhi0_data1_pins[] = {
3536− /* D0 */
3537− RCAR_GP_PIN(3, 2),
3538−};
3539−static const unsigned int sdhi0_data1_mux[] = {
3540− SD0_DAT0_MARK,
3541−};
3542−static const unsigned int sdhi0_data4_pins[] = {
3521+static const unsigned int sdhi0_data_pins[] = {
35433522 /* D[0:3] */
35443523 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
35453524 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
35463525 };
3547−static const unsigned int sdhi0_data4_mux[] = {
3526+static const unsigned int sdhi0_data_mux[] = {
35483527 SD0_DAT0_MARK, SD0_DAT1_MARK,
35493528 SD0_DAT2_MARK, SD0_DAT3_MARK,
35503529 };
@@ -3570,19 +3549,12 @@ static const unsigned int sdhi0_wp_mux[] = { · 19 unmodified lines
35703549 SD0_WP_MARK,
35713550 };
35723551 /* - SDHI1 ------------------------------------------------------------------ */
3573−static const unsigned int sdhi1_data1_pins[] = {
3574− /* D0 */
3575− RCAR_GP_PIN(3, 8),
3576−};
3577−static const unsigned int sdhi1_data1_mux[] = {
3578− SD1_DAT0_MARK,
3579−};
3580−static const unsigned int sdhi1_data4_pins[] = {
3552+static const unsigned int sdhi1_data_pins[] = {
35813553 /* D[0:3] */
35823554 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
35833555 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
35843556 };
3585−static const unsigned int sdhi1_data4_mux[] = {
3557+static const unsigned int sdhi1_data_mux[] = {
35863558 SD1_DAT0_MARK, SD1_DAT1_MARK,
35873559 SD1_DAT2_MARK, SD1_DAT3_MARK,
35883560 };
@@ -3608,30 +3580,14 @@ static const unsigned int sdhi1_wp_mux[] = { · 19 unmodified lines
36083580 SD1_WP_MARK,
36093581 };
36103582 /* - SDHI2 ------------------------------------------------------------------ */
3611−static const unsigned int sdhi2_data1_pins[] = {
3612− /* D0 */
3613− RCAR_GP_PIN(4, 2),
3614−};
3615−static const unsigned int sdhi2_data1_mux[] = {
3616− SD2_DAT0_MARK,
3617−};
3618−static const unsigned int sdhi2_data4_pins[] = {
3619− /* D[0:3] */
3620− RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3621− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3622−};
3623−static const unsigned int sdhi2_data4_mux[] = {
3624− SD2_DAT0_MARK, SD2_DAT1_MARK,
3625− SD2_DAT2_MARK, SD2_DAT3_MARK,
3626−};
3627−static const unsigned int sdhi2_data8_pins[] = {
3583+static const unsigned int sdhi2_data_pins[] = {
36283584 /* D[0:7] */
36293585 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
36303586 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
36313587 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
36323588 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
36333589 };
3634−static const unsigned int sdhi2_data8_mux[] = {
3590+static const unsigned int sdhi2_data_mux[] = {
36353591 SD2_DAT0_MARK, SD2_DAT1_MARK,
36363592 SD2_DAT2_MARK, SD2_DAT3_MARK,
36373593 SD2_DAT4_MARK, SD2_DAT5_MARK,
@@ -3680,30 +3636,14 @@ static const unsigned int sdhi2_ds_mux[] = { · 42 unmodified lines
36803636 SD2_DS_MARK,
36813637 };
36823638 /* - SDHI3 ------------------------------------------------------------------ */
3683−static const unsigned int sdhi3_data1_pins[] = {
3684− /* D0 */
3685− RCAR_GP_PIN(4, 9),
3686−};
3687−static const unsigned int sdhi3_data1_mux[] = {
3688− SD3_DAT0_MARK,
3689−};
3690−static const unsigned int sdhi3_data4_pins[] = {
3691− /* D[0:3] */
3692− RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3693− RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3694−};
3695−static const unsigned int sdhi3_data4_mux[] = {
3696− SD3_DAT0_MARK, SD3_DAT1_MARK,
3697− SD3_DAT2_MARK, SD3_DAT3_MARK,
3698−};
3699−static const unsigned int sdhi3_data8_pins[] = {
3639+static const unsigned int sdhi3_data_pins[] = {
37003640 /* D[0:7] */
37013641 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
37023642 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
37033643 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
37043644 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
37053645 };
3706−static const unsigned int sdhi3_data8_mux[] = {
3646+static const unsigned int sdhi3_data_mux[] = {
37073647 SD3_DAT0_MARK, SD3_DAT1_MARK,
37083648 SD3_DAT2_MARK, SD3_DAT3_MARK,
37093649 SD3_DAT4_MARK, SD3_DAT5_MARK,
@@ -4046,81 +3986,61 @@ static const unsigned int vin4_data18_b_mux[] = { · 336 unmodified lines
40463986 VI4_DATA20_MARK, VI4_DATA21_MARK,
40473987 VI4_DATA22_MARK, VI4_DATA23_MARK,
40483988 };
4049−static const union vin_data vin4_data_a_pins = {
4050− .data24 = {
4051− RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4052− RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4053− RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4054− RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4055− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4056− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4057− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4058− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4059− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4060− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4061− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4062− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4063− },
4064−};
4065−static const union vin_data vin4_data_a_mux = {
4066− .data24 = {
4067− VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4068− VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4069− VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4070− VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4071− VI4_DATA8_MARK, VI4_DATA9_MARK,
4072− VI4_DATA10_MARK, VI4_DATA11_MARK,
4073− VI4_DATA12_MARK, VI4_DATA13_MARK,
4074− VI4_DATA14_MARK, VI4_DATA15_MARK,
4075− VI4_DATA16_MARK, VI4_DATA17_MARK,
4076− VI4_DATA18_MARK, VI4_DATA19_MARK,
4077− VI4_DATA20_MARK, VI4_DATA21_MARK,
4078− VI4_DATA22_MARK, VI4_DATA23_MARK,
4079− },
4080−};
4081−static const union vin_data vin4_data_b_pins = {
4082− .data24 = {
4083− RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4084− RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4085− RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4086− RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4087− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4088− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4089− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4090− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4091− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4092− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4093− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4094− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4095− },
3989+static const unsigned int vin4_data_a_pins[] = {
3990+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3991+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3992+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3993+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3994+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3995+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3996+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3997+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3998+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3999+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4000+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4001+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
40964002 };
4097−static const union vin_data vin4_data_b_mux = {
4098− .data24 = {
4099− VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4100− VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4101− VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4102− VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4103− VI4_DATA8_MARK, VI4_DATA9_MARK,
4104− VI4_DATA10_MARK, VI4_DATA11_MARK,
4105− VI4_DATA12_MARK, VI4_DATA13_MARK,
4106− VI4_DATA14_MARK, VI4_DATA15_MARK,
4107− VI4_DATA16_MARK, VI4_DATA17_MARK,
4108− VI4_DATA18_MARK, VI4_DATA19_MARK,
4109− VI4_DATA20_MARK, VI4_DATA21_MARK,
4110− VI4_DATA22_MARK, VI4_DATA23_MARK,
4111− },
4003+static const unsigned int vin4_data_a_mux[] = {
4004+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4005+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4006+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4007+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4008+ VI4_DATA8_MARK, VI4_DATA9_MARK,
4009+ VI4_DATA10_MARK, VI4_DATA11_MARK,
4010+ VI4_DATA12_MARK, VI4_DATA13_MARK,
4011+ VI4_DATA14_MARK, VI4_DATA15_MARK,
4012+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4013+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4014+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4015+ VI4_DATA22_MARK, VI4_DATA23_MARK,
41124016 };
4113−static const unsigned int vin4_g8_pins[] = {
4114− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4115− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4116− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4117− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4017+static const unsigned int vin4_data_b_pins[] = {
4018+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4019+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4020+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4021+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4022+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4023+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4024+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4025+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4026+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4027+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4028+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4029+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
41184030 };
4119−static const unsigned int vin4_g8_mux[] = {
4031+static const unsigned int vin4_data_b_mux[] = {
4032+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4033+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4034+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4035+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
41204036 VI4_DATA8_MARK, VI4_DATA9_MARK,
41214037 VI4_DATA10_MARK, VI4_DATA11_MARK,
41224038 VI4_DATA12_MARK, VI4_DATA13_MARK,
41234039 VI4_DATA14_MARK, VI4_DATA15_MARK,
4040+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4041+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4042+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4043+ VI4_DATA22_MARK, VI4_DATA23_MARK,
41244044 };
41254045 static const unsigned int vin4_sync_pins[] = {
41264046 /* HSYNC#, VSYNC# */
@@ -4152,37 +4072,21 @@ static const unsigned int vin4_clk_mux[] = { · 25 unmodified lines
41524072 };
41534073
41544074 /* - VIN5 ------------------------------------------------------------------- */
4155−static const union vin_data16 vin5_data_pins = {
4156− .data16 = {
4157− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4158− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4159− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4160− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4161− RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4162− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4163− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4164− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4165− },
4166−};
4167−static const union vin_data16 vin5_data_mux = {
4168− .data16 = {
4169− VI5_DATA0_MARK, VI5_DATA1_MARK,
4170− VI5_DATA2_MARK, VI5_DATA3_MARK,
4171− VI5_DATA4_MARK, VI5_DATA5_MARK,
4172− VI5_DATA6_MARK, VI5_DATA7_MARK,
4173− VI5_DATA8_MARK, VI5_DATA9_MARK,
4174− VI5_DATA10_MARK, VI5_DATA11_MARK,
4175− VI5_DATA12_MARK, VI5_DATA13_MARK,
4176− VI5_DATA14_MARK, VI5_DATA15_MARK,
4177− },
4178−};
4179−static const unsigned int vin5_high8_pins[] = {
4075+static const unsigned int vin5_data_pins[] = {
4076+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4077+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4078+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4079+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
41804080 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
41814081 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4182− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4183− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4082+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4083+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
41844084 };
4185−static const unsigned int vin5_high8_mux[] = {
4085+static const unsigned int vin5_data_mux[] = {
4086+ VI5_DATA0_MARK, VI5_DATA1_MARK,
4087+ VI5_DATA2_MARK, VI5_DATA3_MARK,
4088+ VI5_DATA4_MARK, VI5_DATA5_MARK,
4089+ VI5_DATA6_MARK, VI5_DATA7_MARK,
41864090 VI5_DATA8_MARK, VI5_DATA9_MARK,
41874091 VI5_DATA10_MARK, VI5_DATA11_MARK,
41884092 VI5_DATA12_MARK, VI5_DATA13_MARK,
@@ -4424,11 +4328,11 @@ static const struct { · 235 unmodified lines
44244328 SH_PFC_PIN_GROUP(pwm6_a),
44254329 SH_PFC_PIN_GROUP(pwm6_b),
44264330 SH_PFC_PIN_GROUP(qspi0_ctrl),
4427− SH_PFC_PIN_GROUP(qspi0_data2),
4428− SH_PFC_PIN_GROUP(qspi0_data4),
4331+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
4332+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
44294333 SH_PFC_PIN_GROUP(qspi1_ctrl),
4430− SH_PFC_PIN_GROUP(qspi1_data2),
4431− SH_PFC_PIN_GROUP(qspi1_data4),
4334+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
4335+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
44324336 SH_PFC_PIN_GROUP(scif0_data),
44334337 SH_PFC_PIN_GROUP(scif0_clk),
44344338 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4458,28 +4362,28 @@ static const struct { · 23 unmodified lines
44584362 SH_PFC_PIN_GROUP(scif5_clk_b),
44594363 SH_PFC_PIN_GROUP(scif_clk_a),
44604364 SH_PFC_PIN_GROUP(scif_clk_b),
4461− SH_PFC_PIN_GROUP(sdhi0_data1),
4462− SH_PFC_PIN_GROUP(sdhi0_data4),
4365+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4366+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
44634367 SH_PFC_PIN_GROUP(sdhi0_ctrl),
44644368 SH_PFC_PIN_GROUP(sdhi0_cd),
44654369 SH_PFC_PIN_GROUP(sdhi0_wp),
4466− SH_PFC_PIN_GROUP(sdhi1_data1),
4467− SH_PFC_PIN_GROUP(sdhi1_data4),
4370+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4371+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
44684372 SH_PFC_PIN_GROUP(sdhi1_ctrl),
44694373 SH_PFC_PIN_GROUP(sdhi1_cd),
44704374 SH_PFC_PIN_GROUP(sdhi1_wp),
4471− SH_PFC_PIN_GROUP(sdhi2_data1),
4472− SH_PFC_PIN_GROUP(sdhi2_data4),
4473− SH_PFC_PIN_GROUP(sdhi2_data8),
4375+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4376+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4377+ BUS_DATA_PIN_GROUP(sdhi2_data, 8),
44744378 SH_PFC_PIN_GROUP(sdhi2_ctrl),
44754379 SH_PFC_PIN_GROUP(sdhi2_cd_a),
44764380 SH_PFC_PIN_GROUP(sdhi2_wp_a),
44774381 SH_PFC_PIN_GROUP(sdhi2_cd_b),
44784382 SH_PFC_PIN_GROUP(sdhi2_wp_b),
44794383 SH_PFC_PIN_GROUP(sdhi2_ds),
4480− SH_PFC_PIN_GROUP(sdhi3_data1),
4481− SH_PFC_PIN_GROUP(sdhi3_data4),
4482− SH_PFC_PIN_GROUP(sdhi3_data8),
4384+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4385+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4386+ BUS_DATA_PIN_GROUP(sdhi3_data, 8),
44834387 SH_PFC_PIN_GROUP(sdhi3_ctrl),
44844388 SH_PFC_PIN_GROUP(sdhi3_cd),
44854389 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -4520,30 +4424,30 @@ static const struct { · 34 unmodified lines
45204424 SH_PFC_PIN_GROUP(usb0),
45214425 SH_PFC_PIN_GROUP(usb1),
45224426 SH_PFC_PIN_GROUP(usb30),
4523− VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4524− VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4525− VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4526− VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4427+ BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4428+ BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4429+ BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4430+ BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
45274431 SH_PFC_PIN_GROUP(vin4_data18_a),
4528− VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4529− VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4530− VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4531− VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4532− VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4533− VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4432+ BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4433+ BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4434+ BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4435+ BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4436+ BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4437+ BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
45344438 SH_PFC_PIN_GROUP(vin4_data18_b),
4535− VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4536− VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4537− SH_PFC_PIN_GROUP(vin4_g8),
4439+ BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4440+ BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4441+ SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
45384442 SH_PFC_PIN_GROUP(vin4_sync),
45394443 SH_PFC_PIN_GROUP(vin4_field),
45404444 SH_PFC_PIN_GROUP(vin4_clkenb),
45414445 SH_PFC_PIN_GROUP(vin4_clk),
4542− VIN_DATA_PIN_GROUP(vin5_data, 8),
4543− VIN_DATA_PIN_GROUP(vin5_data, 10),
4544− VIN_DATA_PIN_GROUP(vin5_data, 12),
4545− VIN_DATA_PIN_GROUP(vin5_data, 16),
4546− SH_PFC_PIN_GROUP(vin5_high8),
4446+ BUS_DATA_PIN_GROUP(vin5_data, 8),
4447+ BUS_DATA_PIN_GROUP(vin5_data, 10),
4448+ BUS_DATA_PIN_GROUP(vin5_data, 12),
4449+ BUS_DATA_PIN_GROUP(vin5_data, 16),
4450+ SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
45474451 SH_PFC_PIN_GROUP(vin5_sync),
45484452 SH_PFC_PIN_GROUP(vin5_field),
45494453 SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -6009,8 +5913,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 1459 unmodified lines
60095913 { /* sentinel */ },
60105914 };
60115915
6012−static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
6013− unsigned int pin, u32 *pocctrl)
5916+static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
60145917 {
60155918 int bit = -EINVAL;
60165919
@@ -6267,7 +6170,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
62676170 { /* sentinel */ },
62686171 };
62696172
6270−static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6173+static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
62716174 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
62726175 .get_bias = rcar_pinmux_get_bias,
62736176 .set_bias = rcar_pinmux_set_bias,
@@ -6276,7 +6179,7 @@ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { · 2 unmodified lines
62766179 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
62776180 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
62786181 .name = "r8a774a1_pfc",
6279− .ops = &r8a7796_pinmux_ops,
6182+ .ops = &r8a7796_pfc_ops,
62806183 .unlock_reg = 0xe6060000, /* PMMR */
62816184
62826185 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6301,7 +6204,7 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = { · 18 unmodified lines
63016204 #ifdef CONFIG_PINCTRL_PFC_R8A77960
63026205 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
63036206 .name = "r8a77960_pfc",
6304− .ops = &r8a7796_pinmux_ops,
6207+ .ops = &r8a7796_pfc_ops,
63056208 .unlock_reg = 0xe6060000, /* PMMR */
63066209
63076210 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6328,7 +6231,7 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = { · 20 unmodified lines
63286231 #ifdef CONFIG_PINCTRL_PFC_R8A77961
63296232 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
63306233 .name = "r8a77961_pfc",
6331− .ops = &r8a7796_pinmux_ops,
6234+ .ops = &r8a7796_pfc_ops,
63326235 .unlock_reg = 0xe6060000, /* PMMR */
63336236
63346237 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a77965.c+110−223
@@ -3424,20 +3424,13 @@ static const unsigned int qspi0_ctrl_pins[] = { · 3423 unmodified lines
34243424 static const unsigned int qspi0_ctrl_mux[] = {
34253425 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
34263426 };
3427−static const unsigned int qspi0_data2_pins[] = {
3428− /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3429− PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3430−};
3431−static const unsigned int qspi0_data2_mux[] = {
3432− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3433−};
3434−static const unsigned int qspi0_data4_pins[] = {
3427+static const unsigned int qspi0_data_pins[] = {
34353428 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
34363429 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
34373430 /* QSPI0_IO2, QSPI0_IO3 */
34383431 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
34393432 };
3440−static const unsigned int qspi0_data4_mux[] = {
3433+static const unsigned int qspi0_data_mux[] = {
34413434 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
34423435 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
34433436 };
@@ -3449,20 +3442,13 @@ static const unsigned int qspi1_ctrl_pins[] = { · 5 unmodified lines
34493442 static const unsigned int qspi1_ctrl_mux[] = {
34503443 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
34513444 };
3452−static const unsigned int qspi1_data2_pins[] = {
3453− /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3454− PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3455−};
3456−static const unsigned int qspi1_data2_mux[] = {
3457− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3458−};
3459−static const unsigned int qspi1_data4_pins[] = {
3445+static const unsigned int qspi1_data_pins[] = {
34603446 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
34613447 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
34623448 /* QSPI1_IO2, QSPI1_IO3 */
34633449 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
34643450 };
3465−static const unsigned int qspi1_data4_mux[] = {
3451+static const unsigned int qspi1_data_mux[] = {
34663452 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
34673453 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
34683454 };
@@ -3698,22 +3684,13 @@ static const unsigned int scif_clk_b_mux[] = { · 229 unmodified lines
36983684 };
36993685
37003686 /* - SDHI0 ------------------------------------------------------------------ */
3701−static const unsigned int sdhi0_data1_pins[] = {
3702− /* D0 */
3703− RCAR_GP_PIN(3, 2),
3704−};
3705−
3706−static const unsigned int sdhi0_data1_mux[] = {
3707− SD0_DAT0_MARK,
3708−};
3709−
3710−static const unsigned int sdhi0_data4_pins[] = {
3687+static const unsigned int sdhi0_data_pins[] = {
37113688 /* D[0:3] */
37123689 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
37133690 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
37143691 };
37153692
3716−static const unsigned int sdhi0_data4_mux[] = {
3693+static const unsigned int sdhi0_data_mux[] = {
37173694 SD0_DAT0_MARK, SD0_DAT1_MARK,
37183695 SD0_DAT2_MARK, SD0_DAT3_MARK,
37193696 };
@@ -3746,22 +3723,13 @@ static const unsigned int sdhi0_wp_mux[] = { · 26 unmodified lines
37463723 };
37473724
37483725 /* - SDHI1 ------------------------------------------------------------------ */
3749−static const unsigned int sdhi1_data1_pins[] = {
3750− /* D0 */
3751− RCAR_GP_PIN(3, 8),
3752−};
3753−
3754−static const unsigned int sdhi1_data1_mux[] = {
3755− SD1_DAT0_MARK,
3756−};
3757−
3758−static const unsigned int sdhi1_data4_pins[] = {
3726+static const unsigned int sdhi1_data_pins[] = {
37593727 /* D[0:3] */
37603728 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
37613729 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
37623730 };
37633731
3764−static const unsigned int sdhi1_data4_mux[] = {
3732+static const unsigned int sdhi1_data_mux[] = {
37653733 SD1_DAT0_MARK, SD1_DAT1_MARK,
37663734 SD1_DAT2_MARK, SD1_DAT3_MARK,
37673735 };
@@ -3794,27 +3762,7 @@ static const unsigned int sdhi1_wp_mux[] = { · 26 unmodified lines
37943762 };
37953763
37963764 /* - SDHI2 ------------------------------------------------------------------ */
3797−static const unsigned int sdhi2_data1_pins[] = {
3798− /* D0 */
3799− RCAR_GP_PIN(4, 2),
3800−};
3801−
3802−static const unsigned int sdhi2_data1_mux[] = {
3803− SD2_DAT0_MARK,
3804−};
3805−
3806−static const unsigned int sdhi2_data4_pins[] = {
3807− /* D[0:3] */
3808− RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3809− RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3810−};
3811−
3812−static const unsigned int sdhi2_data4_mux[] = {
3813− SD2_DAT0_MARK, SD2_DAT1_MARK,
3814− SD2_DAT2_MARK, SD2_DAT3_MARK,
3815−};
3816−
3817−static const unsigned int sdhi2_data8_pins[] = {
3765+static const unsigned int sdhi2_data_pins[] = {
38183766 /* D[0:7] */
38193767 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
38203768 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
@@ -3822,7 +3770,7 @@ static const unsigned int sdhi2_data8_pins[] = { · 1 unmodified line
38223770 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
38233771 };
38243772
3825−static const unsigned int sdhi2_data8_mux[] = {
3773+static const unsigned int sdhi2_data_mux[] = {
38263774 SD2_DAT0_MARK, SD2_DAT1_MARK,
38273775 SD2_DAT2_MARK, SD2_DAT3_MARK,
38283776 SD2_DAT4_MARK, SD2_DAT5_MARK,
@@ -3884,27 +3832,7 @@ static const unsigned int sdhi2_ds_mux[] = { · 55 unmodified lines
38843832 };
38853833
38863834 /* - SDHI3 ------------------------------------------------------------------ */
3887−static const unsigned int sdhi3_data1_pins[] = {
3888− /* D0 */
3889− RCAR_GP_PIN(4, 9),
3890−};
3891−
3892−static const unsigned int sdhi3_data1_mux[] = {
3893− SD3_DAT0_MARK,
3894−};
3895−
3896−static const unsigned int sdhi3_data4_pins[] = {
3897− /* D[0:3] */
3898− RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3899− RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3900−};
3901−
3902−static const unsigned int sdhi3_data4_mux[] = {
3903− SD3_DAT0_MARK, SD3_DAT1_MARK,
3904− SD3_DAT2_MARK, SD3_DAT3_MARK,
3905−};
3906−
3907−static const unsigned int sdhi3_data8_pins[] = {
3835+static const unsigned int sdhi3_data_pins[] = {
39083836 /* D[0:7] */
39093837 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
39103838 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
@@ -3912,7 +3840,7 @@ static const unsigned int sdhi3_data8_pins[] = { · 1 unmodified line
39123840 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
39133841 };
39143842
3915−static const unsigned int sdhi3_data8_mux[] = {
3843+static const unsigned int sdhi3_data_mux[] = {
39163844 SD3_DAT0_MARK, SD3_DAT1_MARK,
39173845 SD3_DAT2_MARK, SD3_DAT3_MARK,
39183846 SD3_DAT4_MARK, SD3_DAT5_MARK,
@@ -4254,38 +4182,34 @@ static const unsigned int vin4_data18_a_mux[] = { · 335 unmodified lines
42544182 VI4_DATA22_MARK, VI4_DATA23_MARK,
42554183 };
42564184
4257−static const union vin_data vin4_data_a_pins = {
4258− .data24 = {
4259− RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4260− RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4261− RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4262− RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4263− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4264− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4265− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4266− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4267− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4268− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4269− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4270− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4271− },
4185+static const unsigned int vin4_data_a_pins[] = {
4186+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4187+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4188+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4189+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4190+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4191+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4192+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4193+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4194+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4195+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4196+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4197+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
42724198 };
42734199
4274−static const union vin_data vin4_data_a_mux = {
4275− .data24 = {
4276− VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4277− VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4278− VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4279− VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4280− VI4_DATA8_MARK, VI4_DATA9_MARK,
4281− VI4_DATA10_MARK, VI4_DATA11_MARK,
4282− VI4_DATA12_MARK, VI4_DATA13_MARK,
4283− VI4_DATA14_MARK, VI4_DATA15_MARK,
4284− VI4_DATA16_MARK, VI4_DATA17_MARK,
4285− VI4_DATA18_MARK, VI4_DATA19_MARK,
4286− VI4_DATA20_MARK, VI4_DATA21_MARK,
4287− VI4_DATA22_MARK, VI4_DATA23_MARK,
4288− },
4200+static const unsigned int vin4_data_a_mux[] = {
4201+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4202+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4203+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4204+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4205+ VI4_DATA8_MARK, VI4_DATA9_MARK,
4206+ VI4_DATA10_MARK, VI4_DATA11_MARK,
4207+ VI4_DATA12_MARK, VI4_DATA13_MARK,
4208+ VI4_DATA14_MARK, VI4_DATA15_MARK,
4209+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4210+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4211+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4212+ VI4_DATA22_MARK, VI4_DATA23_MARK,
42894213 };
42904214
42914215 static const unsigned int vin4_data18_b_pins[] = {
@@ -4312,52 +4236,34 @@ static const unsigned int vin4_data18_b_mux[] = { · 20 unmodified lines
43124236 VI4_DATA22_MARK, VI4_DATA23_MARK,
43134237 };
43144238
4315−static const union vin_data vin4_data_b_pins = {
4316− .data24 = {
4317− RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4318− RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4319− RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4320− RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4321− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4322− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4323− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4324− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4325− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4326− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4327− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4328− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4329− },
4330−};
4331−
4332−static const union vin_data vin4_data_b_mux = {
4333− .data24 = {
4334− VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4335− VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4336− VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4337− VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4338− VI4_DATA8_MARK, VI4_DATA9_MARK,
4339− VI4_DATA10_MARK, VI4_DATA11_MARK,
4340− VI4_DATA12_MARK, VI4_DATA13_MARK,
4341− VI4_DATA14_MARK, VI4_DATA15_MARK,
4342− VI4_DATA16_MARK, VI4_DATA17_MARK,
4343− VI4_DATA18_MARK, VI4_DATA19_MARK,
4344− VI4_DATA20_MARK, VI4_DATA21_MARK,
4345− VI4_DATA22_MARK, VI4_DATA23_MARK,
4346− },
4347−};
4348−
4349−static const unsigned int vin4_g8_pins[] = {
4350− RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4351− RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4352− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4353− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4239+static const unsigned int vin4_data_b_pins[] = {
4240+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4241+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4242+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4243+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4244+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4245+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4246+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4247+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4248+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4249+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4250+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4251+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
43544252 };
43554253
4356−static const unsigned int vin4_g8_mux[] = {
4357− VI4_DATA8_MARK, VI4_DATA9_MARK,
4358− VI4_DATA10_MARK, VI4_DATA11_MARK,
4359− VI4_DATA12_MARK, VI4_DATA13_MARK,
4360− VI4_DATA14_MARK, VI4_DATA15_MARK,
4254+static const unsigned int vin4_data_b_mux[] = {
4255+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4256+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4257+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4258+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4259+ VI4_DATA8_MARK, VI4_DATA9_MARK,
4260+ VI4_DATA10_MARK, VI4_DATA11_MARK,
4261+ VI4_DATA12_MARK, VI4_DATA13_MARK,
4262+ VI4_DATA14_MARK, VI4_DATA15_MARK,
4263+ VI4_DATA16_MARK, VI4_DATA17_MARK,
4264+ VI4_DATA18_MARK, VI4_DATA19_MARK,
4265+ VI4_DATA20_MARK, VI4_DATA21_MARK,
4266+ VI4_DATA22_MARK, VI4_DATA23_MARK,
43614267 };
43624268
43634269 static const unsigned int vin4_sync_pins[] = {
@@ -4394,40 +4300,22 @@ static const unsigned int vin4_clk_mux[] = { · 30 unmodified lines
43944300 };
43954301
43964302 /* - VIN5 ------------------------------------------------------------------- */
4397−static const union vin_data16 vin5_data_pins = {
4398− .data16 = {
4399− RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4400− RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4401− RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4402− RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4403− RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4404− RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4405− RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4406− RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4407− },
4408−};
4409−
4410−static const union vin_data16 vin5_data_mux = {
4411− .data16 = {
4412− VI5_DATA0_MARK, VI5_DATA1_MARK,
4413− VI5_DATA2_MARK, VI5_DATA3_MARK,
4414− VI5_DATA4_MARK, VI5_DATA5_MARK,
4415− VI5_DATA6_MARK, VI5_DATA7_MARK,
4416− VI5_DATA8_MARK, VI5_DATA9_MARK,
4417− VI5_DATA10_MARK, VI5_DATA11_MARK,
4418− VI5_DATA12_MARK, VI5_DATA13_MARK,
4419− VI5_DATA14_MARK, VI5_DATA15_MARK,
4420− },
4421−};
4422−
4423−static const unsigned int vin5_high8_pins[] = {
4303+static const unsigned int vin5_data_pins[] = {
4304+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4305+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4306+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4307+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
44244308 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
44254309 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
44264310 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
44274311 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
44284312 };
44294313
4430−static const unsigned int vin5_high8_mux[] = {
4314+static const unsigned int vin5_data_mux[] = {
4315+ VI5_DATA0_MARK, VI5_DATA1_MARK,
4316+ VI5_DATA2_MARK, VI5_DATA3_MARK,
4317+ VI5_DATA4_MARK, VI5_DATA5_MARK,
4318+ VI5_DATA6_MARK, VI5_DATA7_MARK,
44314319 VI5_DATA8_MARK, VI5_DATA9_MARK,
44324320 VI5_DATA10_MARK, VI5_DATA11_MARK,
44334321 VI5_DATA12_MARK, VI5_DATA13_MARK,
@@ -4674,11 +4562,11 @@ static const struct { · 240 unmodified lines
46744562 SH_PFC_PIN_GROUP(pwm6_a),
46754563 SH_PFC_PIN_GROUP(pwm6_b),
46764564 SH_PFC_PIN_GROUP(qspi0_ctrl),
4677− SH_PFC_PIN_GROUP(qspi0_data2),
4678− SH_PFC_PIN_GROUP(qspi0_data4),
4565+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
4566+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
46794567 SH_PFC_PIN_GROUP(qspi1_ctrl),
4680− SH_PFC_PIN_GROUP(qspi1_data2),
4681− SH_PFC_PIN_GROUP(qspi1_data4),
4568+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
4569+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
46824570 SH_PFC_PIN_GROUP(sata0_devslp_a),
46834571 SH_PFC_PIN_GROUP(sata0_devslp_b),
46844572 SH_PFC_PIN_GROUP(scif0_data),
@@ -4710,28 +4598,28 @@ static const struct { · 25 unmodified lines
47104598 SH_PFC_PIN_GROUP(scif5_clk_b),
47114599 SH_PFC_PIN_GROUP(scif_clk_a),
47124600 SH_PFC_PIN_GROUP(scif_clk_b),
4713− SH_PFC_PIN_GROUP(sdhi0_data1),
4714− SH_PFC_PIN_GROUP(sdhi0_data4),
4601+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4602+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
47154603 SH_PFC_PIN_GROUP(sdhi0_ctrl),
47164604 SH_PFC_PIN_GROUP(sdhi0_cd),
47174605 SH_PFC_PIN_GROUP(sdhi0_wp),
4718− SH_PFC_PIN_GROUP(sdhi1_data1),
4719− SH_PFC_PIN_GROUP(sdhi1_data4),
4606+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4607+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
47204608 SH_PFC_PIN_GROUP(sdhi1_ctrl),
47214609 SH_PFC_PIN_GROUP(sdhi1_cd),
47224610 SH_PFC_PIN_GROUP(sdhi1_wp),
4723− SH_PFC_PIN_GROUP(sdhi2_data1),
4724− SH_PFC_PIN_GROUP(sdhi2_data4),
4725− SH_PFC_PIN_GROUP(sdhi2_data8),
4611+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4612+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4613+ BUS_DATA_PIN_GROUP(sdhi2_data, 8),
47264614 SH_PFC_PIN_GROUP(sdhi2_ctrl),
47274615 SH_PFC_PIN_GROUP(sdhi2_cd_a),
47284616 SH_PFC_PIN_GROUP(sdhi2_wp_a),
47294617 SH_PFC_PIN_GROUP(sdhi2_cd_b),
47304618 SH_PFC_PIN_GROUP(sdhi2_wp_b),
47314619 SH_PFC_PIN_GROUP(sdhi2_ds),
4732− SH_PFC_PIN_GROUP(sdhi3_data1),
4733− SH_PFC_PIN_GROUP(sdhi3_data4),
4734− SH_PFC_PIN_GROUP(sdhi3_data8),
4620+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4621+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4622+ BUS_DATA_PIN_GROUP(sdhi3_data, 8),
47354623 SH_PFC_PIN_GROUP(sdhi3_ctrl),
47364624 SH_PFC_PIN_GROUP(sdhi3_cd),
47374625 SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -4772,30 +4660,30 @@ static const struct { · 34 unmodified lines
47724660 SH_PFC_PIN_GROUP(usb0),
47734661 SH_PFC_PIN_GROUP(usb1),
47744662 SH_PFC_PIN_GROUP(usb30),
4775− VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4776− VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4777− VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4778− VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4663+ BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4664+ BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4665+ BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4666+ BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
47794667 SH_PFC_PIN_GROUP(vin4_data18_a),
4780− VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4781− VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4782− VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4783− VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4784− VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4785− VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4668+ BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4669+ BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4670+ BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4671+ BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4672+ BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4673+ BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
47864674 SH_PFC_PIN_GROUP(vin4_data18_b),
4787− VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4788− VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4789− SH_PFC_PIN_GROUP(vin4_g8),
4675+ BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4676+ BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4677+ SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
47904678 SH_PFC_PIN_GROUP(vin4_sync),
47914679 SH_PFC_PIN_GROUP(vin4_field),
47924680 SH_PFC_PIN_GROUP(vin4_clkenb),
47934681 SH_PFC_PIN_GROUP(vin4_clk),
4794− VIN_DATA_PIN_GROUP(vin5_data, 8),
4795− VIN_DATA_PIN_GROUP(vin5_data, 10),
4796− VIN_DATA_PIN_GROUP(vin5_data, 12),
4797− VIN_DATA_PIN_GROUP(vin5_data, 16),
4798− SH_PFC_PIN_GROUP(vin5_high8),
4682+ BUS_DATA_PIN_GROUP(vin5_data, 8),
4683+ BUS_DATA_PIN_GROUP(vin5_data, 10),
4684+ BUS_DATA_PIN_GROUP(vin5_data, 12),
4685+ BUS_DATA_PIN_GROUP(vin5_data, 16),
4686+ SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
47994687 SH_PFC_PIN_GROUP(vin5_sync),
48004688 SH_PFC_PIN_GROUP(vin5_field),
48014689 SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -6266,8 +6154,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 1464 unmodified lines
62666154 { /* sentinel */ },
62676155 };
62686156
6269−static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
6270− unsigned int pin, u32 *pocctrl)
6157+static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
62716158 {
62726159 int bit = -EINVAL;
62736160
@@ -6524,7 +6411,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
65246411 { /* sentinel */ },
65256412 };
65266413
6527−static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6414+static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
65286415 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
65296416 .get_bias = rcar_pinmux_get_bias,
65306417 .set_bias = rcar_pinmux_set_bias,
@@ -6533,7 +6420,7 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { · 2 unmodified lines
65336420 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
65346421 const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
65356422 .name = "r8a774b1_pfc",
6536− .ops = &r8a77965_pinmux_ops,
6423+ .ops = &r8a77965_pfc_ops,
65376424 .unlock_reg = 0xe6060000, /* PMMR */
65386425
65396426 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6558,7 +6445,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = { · 18 unmodified lines
65586445 #ifdef CONFIG_PINCTRL_PFC_R8A77965
65596446 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
65606447 .name = "r8a77965_pfc",
6561− .ops = &r8a77965_pinmux_ops,
6448+ .ops = &r8a77965_pfc_ops,
65626449 .unlock_reg = 0xe6060000, /* PMMR */
65636450
65646451 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a77970.c+51−114
@@ -1102,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = { · 1101 unmodified lines
11021102 };
11031103
11041104 /* - MMC -------------------------------------------------------------------- */
1105−static const unsigned int mmc_data1_pins[] = {
1106− /* D0 */
1107− RCAR_GP_PIN(3, 6),
1108−};
1109−static const unsigned int mmc_data1_mux[] = {
1110− MMC_D0_MARK,
1111−};
1112−static const unsigned int mmc_data4_pins[] = {
1113− /* D[0:3] */
1114− RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1115− RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1116−};
1117−static const unsigned int mmc_data4_mux[] = {
1118− MMC_D0_MARK, MMC_D1_MARK,
1119− MMC_D2_MARK, MMC_D3_MARK,
1120−};
1121−static const unsigned int mmc_data8_pins[] = {
1105+static const unsigned int mmc_data_pins[] = {
11221106 /* D[0:7] */
11231107 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
11241108 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
11251109 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
11261110 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
11271111 };
1128−static const unsigned int mmc_data8_mux[] = {
1112+static const unsigned int mmc_data_mux[] = {
11291113 MMC_D0_MARK, MMC_D1_MARK,
11301114 MMC_D2_MARK, MMC_D3_MARK,
11311115 MMC_D4_MARK, MMC_D5_MARK,
@@ -1393,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = { · 261 unmodified lines
13931377 static const unsigned int qspi0_ctrl_mux[] = {
13941378 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
13951379 };
1396−static const unsigned int qspi0_data2_pins[] = {
1397− /* MOSI_IO0, MISO_IO1 */
1398− RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1399−};
1400−static const unsigned int qspi0_data2_mux[] = {
1401− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1402−};
1403−static const unsigned int qspi0_data4_pins[] = {
1404− /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1405− RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1406− RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1407−};
1408−static const unsigned int qspi0_data4_mux[] = {
1409− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1410− QSPI0_IO2_MARK, QSPI0_IO3_MARK
1411−};
14121380
14131381 /* - QSPI1 ------------------------------------------------------------------ */
14141382 static const unsigned int qspi1_ctrl_pins[] = {
@@ -1418,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = { · 3 unmodified lines
14181386 static const unsigned int qspi1_ctrl_mux[] = {
14191387 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
14201388 };
1421−static const unsigned int qspi1_data2_pins[] = {
1422− /* MOSI_IO0, MISO_IO1 */
1423− RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1424−};
1425−static const unsigned int qspi1_data2_mux[] = {
1426− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1427−};
1428−static const unsigned int qspi1_data4_pins[] = {
1429− /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1430− RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1431− RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1432−};
1433−static const unsigned int qspi1_data4_mux[] = {
1434− QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1435− QSPI1_IO2_MARK, QSPI1_IO3_MARK
1436−};
14371389
14381390 /* - RPC -------------------------------------------------------------------- */
1439−static const unsigned int rpc_clk1_pins[] = {
1391+static const unsigned int rpc_clk_pins[] = {
14401392 /* Octal-SPI flash: C/SCLK */
1441− RCAR_GP_PIN(5, 0),
1442−};
1443−static const unsigned int rpc_clk1_mux[] = {
1444− QSPI0_SPCLK_MARK,
1445−};
1446−static const unsigned int rpc_clk2_pins[] = {
14471393 /* HyperFlash: CK, CK# */
14481394 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
14491395 };
1450−static const unsigned int rpc_clk2_mux[] = {
1396+static const unsigned int rpc_clk_mux[] = {
14511397 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
14521398 };
14531399 static const unsigned int rpc_ctrl_pins[] = {
@@ -1639,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = { · 185 unmodified lines
16391585 };
16401586
16411587 /* - VIN0 ------------------------------------------------------------------- */
1642−static const union vin_data12 vin0_data_pins = {
1643− .data12 = {
1644− RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1645− RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1646− RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1647− RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1648− RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1649− RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1650− },
1651−};
1652−static const union vin_data12 vin0_data_mux = {
1653− .data12 = {
1654− VI0_DATA0_MARK, VI0_DATA1_MARK,
1655− VI0_DATA2_MARK, VI0_DATA3_MARK,
1656− VI0_DATA4_MARK, VI0_DATA5_MARK,
1657− VI0_DATA6_MARK, VI0_DATA7_MARK,
1658− VI0_DATA8_MARK, VI0_DATA9_MARK,
1659− VI0_DATA10_MARK, VI0_DATA11_MARK,
1660− },
1588+static const unsigned int vin0_data_pins[] = {
1589+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1590+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1591+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1592+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1593+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1594+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1595+};
1596+static const unsigned int vin0_data_mux[] = {
1597+ VI0_DATA0_MARK, VI0_DATA1_MARK,
1598+ VI0_DATA2_MARK, VI0_DATA3_MARK,
1599+ VI0_DATA4_MARK, VI0_DATA5_MARK,
1600+ VI0_DATA6_MARK, VI0_DATA7_MARK,
1601+ VI0_DATA8_MARK, VI0_DATA9_MARK,
1602+ VI0_DATA10_MARK, VI0_DATA11_MARK,
16611603 };
16621604 static const unsigned int vin0_sync_pins[] = {
16631605 /* HSYNC#, VSYNC# */
@@ -1689,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = { · 25 unmodified lines
16891631 };
16901632
16911633 /* - VIN1 ------------------------------------------------------------------- */
1692−static const union vin_data12 vin1_data_pins = {
1693− .data12 = {
1694− RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1695− RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1696− RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1697− RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1698− RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1699− RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1700− },
1634+static const unsigned int vin1_data_pins[] = {
1635+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1636+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1637+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1638+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1639+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1640+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
17011641 };
1702−static const union vin_data12 vin1_data_mux = {
1703− .data12 = {
1704− VI1_DATA0_MARK, VI1_DATA1_MARK,
1705− VI1_DATA2_MARK, VI1_DATA3_MARK,
1706− VI1_DATA4_MARK, VI1_DATA5_MARK,
1707− VI1_DATA6_MARK, VI1_DATA7_MARK,
1708− VI1_DATA8_MARK, VI1_DATA9_MARK,
1709− VI1_DATA10_MARK, VI1_DATA11_MARK,
1710− },
1642+static const unsigned int vin1_data_mux[] = {
1643+ VI1_DATA0_MARK, VI1_DATA1_MARK,
1644+ VI1_DATA2_MARK, VI1_DATA3_MARK,
1645+ VI1_DATA4_MARK, VI1_DATA5_MARK,
1646+ VI1_DATA6_MARK, VI1_DATA7_MARK,
1647+ VI1_DATA8_MARK, VI1_DATA9_MARK,
1648+ VI1_DATA10_MARK, VI1_DATA11_MARK,
17111649 };
17121650 static const unsigned int vin1_sync_pins[] = {
17131651 /* HSYNC#, VSYNC# */
@@ -1783,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 69 unmodified lines
17831721 SH_PFC_PIN_GROUP(intc_ex_irq3),
17841722 SH_PFC_PIN_GROUP(intc_ex_irq4),
17851723 SH_PFC_PIN_GROUP(intc_ex_irq5),
1786− SH_PFC_PIN_GROUP(mmc_data1),
1787− SH_PFC_PIN_GROUP(mmc_data4),
1788− SH_PFC_PIN_GROUP(mmc_data8),
1724+ BUS_DATA_PIN_GROUP(mmc_data, 1),
1725+ BUS_DATA_PIN_GROUP(mmc_data, 4),
1726+ BUS_DATA_PIN_GROUP(mmc_data, 8),
17891727 SH_PFC_PIN_GROUP(mmc_ctrl),
17901728 SH_PFC_PIN_GROUP(msiof0_clk),
17911729 SH_PFC_PIN_GROUP(msiof0_sync),
@@ -1822,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 30 unmodified lines
18221760 SH_PFC_PIN_GROUP(pwm4_a),
18231761 SH_PFC_PIN_GROUP(pwm4_b),
18241762 SH_PFC_PIN_GROUP(qspi0_ctrl),
1825− SH_PFC_PIN_GROUP(qspi0_data2),
1826− SH_PFC_PIN_GROUP(qspi0_data4),
1763+ SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
1764+ SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
18271765 SH_PFC_PIN_GROUP(qspi1_ctrl),
1828− SH_PFC_PIN_GROUP(qspi1_data2),
1829− SH_PFC_PIN_GROUP(qspi1_data4),
1830− SH_PFC_PIN_GROUP(rpc_clk1),
1831− SH_PFC_PIN_GROUP(rpc_clk2),
1766+ SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
1767+ SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
1768+ BUS_DATA_PIN_GROUP(rpc_clk, 1),
1769+ BUS_DATA_PIN_GROUP(rpc_clk, 2),
18321770 SH_PFC_PIN_GROUP(rpc_ctrl),
18331771 SH_PFC_PIN_GROUP(rpc_data),
18341772 SH_PFC_PIN_GROUP(rpc_reset),
@@ -1853,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 18 unmodified lines
18531791 SH_PFC_PIN_GROUP(tmu_tclk1_b),
18541792 SH_PFC_PIN_GROUP(tmu_tclk2_a),
18551793 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1856− VIN_DATA_PIN_GROUP(vin0_data, 8),
1857− VIN_DATA_PIN_GROUP(vin0_data, 10),
1858− VIN_DATA_PIN_GROUP(vin0_data, 12),
1794+ BUS_DATA_PIN_GROUP(vin0_data, 8),
1795+ BUS_DATA_PIN_GROUP(vin0_data, 10),
1796+ BUS_DATA_PIN_GROUP(vin0_data, 12),
18591797 SH_PFC_PIN_GROUP(vin0_sync),
18601798 SH_PFC_PIN_GROUP(vin0_field),
18611799 SH_PFC_PIN_GROUP(vin0_clkenb),
18621800 SH_PFC_PIN_GROUP(vin0_clk),
1863− VIN_DATA_PIN_GROUP(vin1_data, 8),
1864− VIN_DATA_PIN_GROUP(vin1_data, 10),
1865− VIN_DATA_PIN_GROUP(vin1_data, 12),
1801+ BUS_DATA_PIN_GROUP(vin1_data, 8),
1802+ BUS_DATA_PIN_GROUP(vin1_data, 10),
1803+ BUS_DATA_PIN_GROUP(vin1_data, 12),
18661804 SH_PFC_PIN_GROUP(vin1_sync),
18671805 SH_PFC_PIN_GROUP(vin1_field),
18681806 SH_PFC_PIN_GROUP(vin1_clkenb),
@@ -2496,8 +2434,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 627 unmodified lines
24962434 { /* sentinel */ },
24972435 };
24982436
2499−static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2500− u32 *pocctrl)
2437+static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
25012438 {
25022439 int bit = pin & 0x1f;
25032440
@@ -2656,7 +2593,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 152 unmodified lines
26562593 { /* sentinel */ }
26572594 };
26582595
2659−static const struct sh_pfc_soc_operations pinmux_ops = {
2596+static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
26602597 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
26612598 .get_bias = rcar_pinmux_get_bias,
26622599 .set_bias = rcar_pinmux_set_bias,
@@ -2664,7 +2601,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { · 1 unmodified line
26642601
26652602 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
26662603 .name = "r8a77970_pfc",
2667− .ops = &pinmux_ops,
2604+ .ops = &r8a77970_pfc_ops,
26682605 .unlock_reg = 0xe6060000, /* PMMR */
26692606
26702607 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/renesas/pfc-r8a77980.c+65−128
@@ -1365,30 +1365,14 @@ static const unsigned int intc_ex_irq5_mux[] = { · 1364 unmodified lines
13651365 };
13661366
13671367 /* - MMC -------------------------------------------------------------------- */
1368−static const unsigned int mmc_data1_pins[] = {
1369− /* MMC_D0 */
1370− RCAR_GP_PIN(3, 8),
1371−};
1372−static const unsigned int mmc_data1_mux[] = {
1373− MMC_D0_MARK,
1374−};
1375−static const unsigned int mmc_data4_pins[] = {
1376− /* MMC_D[0:3] */
1377− RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1378− RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1379−};
1380−static const unsigned int mmc_data4_mux[] = {
1381− MMC_D0_MARK, MMC_D1_MARK,
1382− MMC_D2_MARK, MMC_D3_MARK,
1383−};
1384−static const unsigned int mmc_data8_pins[] = {
1368+static const unsigned int mmc_data_pins[] = {
13851369 /* MMC_D[0:7] */
13861370 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
13871371 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
13881372 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
13891373 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
13901374 };
1391−static const unsigned int mmc_data8_mux[] = {
1375+static const unsigned int mmc_data_mux[] = {
13921376 MMC_D0_MARK, MMC_D1_MARK,
13931377 MMC_D2_MARK, MMC_D3_MARK,
13941378 MMC_D4_MARK, MMC_D5_MARK,
@@ -1687,22 +1671,6 @@ static const unsigned int qspi0_ctrl_pins[] = { · 292 unmodified lines
16871671 static const unsigned int qspi0_ctrl_mux[] = {
16881672 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
16891673 };
1690−static const unsigned int qspi0_data2_pins[] = {
1691− /* MOSI_IO0, MISO_IO1 */
1692− RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1693−};
1694−static const unsigned int qspi0_data2_mux[] = {
1695− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1696−};
1697−static const unsigned int qspi0_data4_pins[] = {
1698− /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1699− RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1700− RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1701−};
1702−static const unsigned int qspi0_data4_mux[] = {
1703− QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1704− QSPI0_IO2_MARK, QSPI0_IO3_MARK
1705−};
17061674
17071675 /* - QSPI1 ------------------------------------------------------------------ */
17081676 static const unsigned int qspi1_ctrl_pins[] = {
@@ -1712,36 +1680,14 @@ static const unsigned int qspi1_ctrl_pins[] = { · 3 unmodified lines
17121680 static const unsigned int qspi1_ctrl_mux[] = {
17131681 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
17141682 };

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drivers/pinctrl/renesas/pfc-r8a77990.c+129−204

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