/* * i386 specific functions for TCC assembler * * Copyright (c) 2001, 2002 Fabrice Bellard * Copyright (c) 2009 Frédéric Feret (x86_64 support) * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #define USING_GLOBALS#include "tcc.h" #define MAX_OPERANDS 3 #define TOK_ASM_first TOK_ASM_clc#define TOK_ASM_last TOK_ASM_emms#define TOK_ASM_alllast TOK_ASM_subps #define OPC_B 0x01 /* only used with OPC_WL */#define OPC_WL 0x02 /* accepts w, l or no suffix */#define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */#define OPC_REG 0x04 /* register is added to opcode */#define OPC_MODRM 0x08 /* modrm encoding */ #define OPCT_MASK 0x70#define OPC_FWAIT 0x10 /* add fwait opcode */#define OPC_SHIFT 0x20 /* shift opcodes */#define OPC_ARITH 0x30 /* arithmetic opcodes */#define OPC_FARITH 0x40 /* FPU arithmetic opcodes */#define OPC_TEST 0x50 /* test opcodes */#define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i)) #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */#define OPC_48 0x200 /* Always has REX prefix */#ifdef TCC_TARGET_X86_64# define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */# define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */# define OPC_WLX OPC_WLQ# define OPC_BWLX OPC_BWLQ#else# define OPC_WLX OPC_WL# define OPC_BWLX OPC_BWL#endif #define OPC_GROUP_SHIFT 13 /* in order to compress the operand type, we use specific operands and we or only with EA */enum { OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */#ifdef TCC_TARGET_X86_64 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */#endif OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_SEG, OPT_ST,#ifdef TCC_TARGET_X86_64 OPT_REG8_LOW, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but with REX prefix, not used in insn templates */#endif OPT_IM8, OPT_IM8S, OPT_IM16, OPT_IM32,#ifdef TCC_TARGET_X86_64 OPT_IM64,#endif OPT_EAX, /* %al, %ax, %eax or %rax register */ OPT_ST0, /* %st(0) register */ OPT_CL, /* %cl register */ OPT_DX, /* %dx register */ OPT_ADDR, /* OP_EA with only offset */ OPT_INDIR, /* *(expr) */ /* composite types */ OPT_COMPOSITE_FIRST, OPT_IM, /* IM8 | IM16 | IM32 */ OPT_REG, /* REG8 | REG16 | REG32 | REG64 */ OPT_REGW, /* REG16 | REG32 | REG64 */ OPT_IMW, /* IM16 | IM32 */ OPT_MMXSSE, /* MMX | SSE */ OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */ OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */ /* can be ored with any OPT_xxx */ OPT_EA = 0x80}; #define OP_REG8 (1 << OPT_REG8)#define OP_REG16 (1 << OPT_REG16)#define OP_REG32 (1 << OPT_REG32)#define OP_MMX (1 << OPT_MMX)#define OP_SSE (1 << OPT_SSE)#define OP_CR (1 << OPT_CR)#define OP_TR (1 << OPT_TR)#define OP_DB (1 << OPT_DB)#define OP_SEG (1 << OPT_SEG)#define OP_ST (1 << OPT_ST)#define OP_IM8 (1 << OPT_IM8)#define OP_IM8S (1 << OPT_IM8S)#define OP_IM16 (1 << OPT_IM16)#define OP_IM32 (1 << OPT_IM32)#define OP_EAX (1 << OPT_EAX)#define OP_ST0 (1 << OPT_ST0)#define OP_CL (1 << OPT_CL)#define OP_DX (1 << OPT_DX)#define OP_ADDR (1 << OPT_ADDR)#define OP_INDIR (1 << OPT_INDIR)#ifdef TCC_TARGET_X86_64# define OP_REG64 (1 << OPT_REG64)# define OP_REG8_LOW (1 << OPT_REG8_LOW)# define OP_IM64 (1 << OPT_IM64)# define OP_EA32 (OP_EA << 1)#else# define OP_REG64 0# define OP_REG8_LOW 0# define OP_IM64 0# define OP_EA32 0#endif #define OP_EA 0x40000000#define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64) #ifdef TCC_TARGET_X86_64# define TREG_XAX TREG_RAX# define TREG_XCX TREG_RCX# define TREG_XDX TREG_RDX#else# define TREG_XAX TREG_EAX# define TREG_XCX TREG_ECX# define TREG_XDX TREG_EDX#endif typedef struct ASMInstr { uint16_t sym; uint16_t opcode; uint16_t instr_type; uint8_t nb_ops; uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */} ASMInstr; typedef struct Operand { uint32_t type; int8_t reg; /* register, -1 if none */ int8_t reg2; /* second register, -1 if none */ uint8_t shift; ExprValue e;} Operand; static const uint8_t reg_to_size[9] = {/* [OP_REG8] = 0, [OP_REG16] = 1, [OP_REG32] = 2,#ifdef TCC_TARGET_X86_64 [OP_REG64] = 3,#endif*/ 0, 0, 1, 0, 2, 0, 0, 0, 3}; #define NB_TEST_OPCODES 30 static const uint8_t test_bits[NB_TEST_OPCODES] = { 0x00, /* o */ 0x01, /* no */ 0x02, /* b */ 0x02, /* c */ 0x02, /* nae */ 0x03, /* nb */ 0x03, /* nc */ 0x03, /* ae */ 0x04, /* e */ 0x04, /* z */ 0x05, /* ne */ 0x05, /* nz */ 0x06, /* be */ 0x06, /* na */ 0x07, /* nbe */ 0x07, /* a */ 0x08, /* s */ 0x09, /* ns */ 0x0a, /* p */ 0x0a, /* pe */ 0x0b, /* np */ 0x0b, /* po */ 0x0c, /* l */ 0x0c, /* nge */ 0x0d, /* nl */ 0x0d, /* ge */ 0x0e, /* le */ 0x0e, /* ng */ 0x0f, /* nle */ 0x0f, /* g */}; static const uint8_t segment_prefixes[] = { 0x26, /* es */ 0x2e, /* cs */ 0x36, /* ss */ 0x3e, /* ds */ 0x64, /* fs */ 0x65 /* gs */}; static const ASMInstr asm_instrs[] = {#define ALT(x) x/* This removes a 0x0f in the second byte */#define O(o) ((uint64_t) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o)))/* This constructs instr_type from opcode, type and group. */#define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))#define DEF_ASM_OP0(name, opcode)#define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0, { 0 } },#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},#ifdef TCC_TARGET_X86_64# include "x86_64-asm.h"#else# include "i386-asm.h"#endif /* last operation */ { 0, },}; static const uint16_t op0_codes[] = {#define ALT(x)#define DEF_ASM_OP0(x, opcode) opcode,#define DEF_ASM_OP0L(name, opcode, group, instr_type)#define DEF_ASM_OP1(name, opcode, group, instr_type, op0)#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)#ifdef TCC_TARGET_X86_64# include "x86_64-asm.h"#else# include "i386-asm.h"#endif}; static inline int get_reg_shift(TCCState *s1){ int shift, v; v = asm_int_expr(s1); switch(v) { case 1: shift = 0; break; case 2: shift = 1; break; case 4: shift = 2; break; case 8: shift = 3; break; default: expect("1, 2, 4 or 8 constant"); shift = 0; break; } return shift;} #ifdef TCC_TARGET_X86_64static int asm_parse_numeric_reg(int t, unsigned int *type){ int reg = -1; if (t >= TOK_IDENT && t < tok_ident) { const char *s = table_ident[t - TOK_IDENT]->str; char c; *type = OP_REG64; if (*s == 'c') { s++; *type = OP_CR; } if (*s++ != 'r') return -1; /* Don't allow leading '0'. */ if ((c = *s++) >= '1' && c <= '9') reg = c - '0'; else return -1; if ((c = *s) >= '0' && c <= '5') s++, reg = reg * 10 + c - '0'; if (reg > 15) return -1; if ((c = *s) == 0) ; else if (*type != OP_REG64) return -1; else if (c == 'b' && !s[1]) *type = OP_REG8; else if (c == 'w' && !s[1]) *type = OP_REG16; else if (c == 'd' && !s[1]) *type = OP_REG32; else return -1; } return reg;}#endif static int asm_parse_reg(unsigned int *type){ int reg = 0; *type = 0; if (tok != '%') goto error_32; next(); if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) { reg = tok - TOK_ASM_eax; *type = OP_REG32;#ifdef TCC_TARGET_X86_64 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) { reg = tok - TOK_ASM_rax; *type = OP_REG64; } else if (tok == TOK_ASM_rip) { reg = -2; /* Probably should use different escape code. */ *type = OP_REG64; } else if ((reg = asm_parse_numeric_reg(tok, type)) >= 0 && (*type == OP_REG32 || *type == OP_REG64)) { ;#endif } else { error_32: expect("register"); } next(); return reg;} static void parse_operand(TCCState *s1, Operand *op){ ExprValue e; int reg, indir; const char *p; indir = 0; if (tok == '*') { next(); indir = OP_INDIR; } if (tok == '%') { next(); if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) { reg = tok - TOK_ASM_al; op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */ op->reg = reg & 7; if ((op->type & OP_REG) && op->reg == TREG_XAX) op->type |= OP_EAX; else if (op->type == OP_REG8 && op->reg == TREG_XCX) op->type |= OP_CL; else if (op->type == OP_REG16 && op->reg == TREG_XDX) op->type |= OP_DX; } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) { op->type = OP_DB; op->reg = tok - TOK_ASM_dr0; } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) { op->type = OP_SEG; op->reg = tok - TOK_ASM_es; } else if (tok == TOK_ASM_st) { op->type = OP_ST; op->reg = 0; next(); if (tok == '(') { next(); if (tok != TOK_PPNUM) goto reg_error; p = tokc.str.data; reg = p[0] - '0'; if ((unsigned)reg >= 8 || p[1] != '\0') goto reg_error; op->reg = reg; next(); skip(')'); } if (op->reg == 0) op->type |= OP_ST0; goto no_skip;#ifdef TCC_TARGET_X86_64 } else if (tok >= TOK_ASM_spl && tok <= TOK_ASM_dil) { op->type = OP_REG8 | OP_REG8_LOW; op->reg = 4 + tok - TOK_ASM_spl; } else if ((op->reg = asm_parse_numeric_reg(tok, &op->type)) >= 0) { ;#endif } else { reg_error: tcc_error("unknown register %%%s", get_tok_str(tok, &tokc)); } next(); no_skip: ; } else if (tok == '$') { /* constant value */ next(); asm_expr(s1, &e); op->type = OP_IM32; op->e = e; if (!op->e.sym) { if (op->e.v == (uint8_t)op->e.v) op->type |= OP_IM8; if (op->e.v == (int8_t)op->e.v) op->type |= OP_IM8S; if (op->e.v == (uint16_t)op->e.v) op->type |= OP_IM16;#ifdef TCC_TARGET_X86_64 if (op->e.v != (int32_t)op->e.v && op->e.v != (uint32_t)op->e.v) op->type = OP_IM64;#endif } } else { /* address(reg,reg2,shift) with all variants */ op->type = OP_EA; op->reg = -1; op->reg2 = -1; op->shift = 0; if (tok != '(') { asm_expr(s1, &e); op->e = e; } else { next(); if (tok == '%') { unget_tok('('); op->e.v = 0; op->e.sym = NULL; } else { /* bracketed offset expression */ asm_expr(s1, &e); if (tok != ')') expect(")"); next(); op->e.v = e.v; op->e.sym = e.sym; } op->e.pcrel = 0; } if (tok == '(') { unsigned int type = 0; next(); if (tok != ',') { op->reg = asm_parse_reg(&type); } if (tok == ',') { next(); if (tok != ',') { op->reg2 = asm_parse_reg(&type); } if (tok == ',') { next(); op->shift = get_reg_shift(s1); } } if (type & OP_REG32) op->type |= OP_EA32; skip(')'); } if (op->reg == -1 && op->reg2 == -1) op->type |= OP_ADDR; } op->type |= indir;} /* XXX: unify with C code output ? */ST_FUNC void gen_expr32(ExprValue *pe){ if (pe->pcrel) /* If PC-relative, always set VT_SYM, even without symbol, so as to force a relocation to be emitted. */ gen_addrpc32(VT_SYM, pe->sym, pe->v); else gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);} #ifdef TCC_TARGET_X86_64ST_FUNC void gen_expr64(ExprValue *pe){ gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);}#endif /* XXX: unify with C code output ? */Lines 1–500 of 1726. Load more
/* * i386 specific functions for TCC assembler * * Copyright (c) 2001, 2002 Fabrice Bellard * Copyright (c) 2009 Frédéric Feret (x86_64 support) * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #define USING_GLOBALS #include "tcc.h" #define MAX_OPERANDS 3 #define TOK_ASM_first TOK_ASM_clc #define TOK_ASM_last TOK_ASM_emms #define TOK_ASM_alllast TOK_ASM_subps #define OPC_B 0x01 /* only used with OPC_WL */ #define OPC_WL 0x02 /* accepts w, l or no suffix */ #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */ #define OPC_REG 0x04 /* register is added to opcode */ #define OPC_MODRM 0x08 /* modrm encoding */ #define OPCT_MASK 0x70 #define OPC_FWAIT 0x10 /* add fwait opcode */ #define OPC_SHIFT 0x20 /* shift opcodes */ #define OPC_ARITH 0x30 /* arithmetic opcodes */ #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */ #define OPC_TEST 0x50 /* test opcodes */ #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i)) #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */ #define OPC_48 0x200 /* Always has REX prefix */ #ifdef TCC_TARGET_X86_64 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */ # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */ # define OPC_WLX OPC_WLQ # define OPC_BWLX OPC_BWLQ #else # define OPC_WLX OPC_WL # define OPC_BWLX OPC_BWL #endif #define OPC_GROUP_SHIFT 13 /* in order to compress the operand type, we use specific operands and we or only with EA */ enum { OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */ #ifdef TCC_TARGET_X86_64 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */ #endif OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */ OPT_SEG, OPT_ST, #ifdef TCC_TARGET_X86_64 OPT_REG8_LOW, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but with REX prefix, not used in insn templates */ #endif OPT_IM8, OPT_IM8S, OPT_IM16, OPT_IM32, #ifdef TCC_TARGET_X86_64 OPT_IM64, #endif OPT_EAX, /* %al, %ax, %eax or %rax register */ OPT_ST0, /* %st(0) register */ OPT_CL, /* %cl register */ OPT_DX, /* %dx register */ OPT_ADDR, /* OP_EA with only offset */ OPT_INDIR, /* *(expr) */ /* composite types */ OPT_COMPOSITE_FIRST, OPT_IM, /* IM8 | IM16 | IM32 */ OPT_REG, /* REG8 | REG16 | REG32 | REG64 */ OPT_REGW, /* REG16 | REG32 | REG64 */ OPT_IMW, /* IM16 | IM32 */ OPT_MMXSSE, /* MMX | SSE */ OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */ OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */ /* can be ored with any OPT_xxx */ OPT_EA = 0x80 }; #define OP_REG8 (1 << OPT_REG8) #define OP_REG16 (1 << OPT_REG16) #define OP_REG32 (1 << OPT_REG32) #define OP_MMX (1 << OPT_MMX) #define OP_SSE (1 << OPT_SSE) #define OP_CR (1 << OPT_CR) #define OP_TR (1 << OPT_TR) #define OP_DB (1 << OPT_DB) #define OP_SEG (1 << OPT_SEG) #define OP_ST (1 << OPT_ST) #define OP_IM8 (1 << OPT_IM8) #define OP_IM8S (1 << OPT_IM8S) #define OP_IM16 (1 << OPT_IM16) #define OP_IM32 (1 << OPT_IM32) #define OP_EAX (1 << OPT_EAX) #define OP_ST0 (1 << OPT_ST0) #define OP_CL (1 << OPT_CL) #define OP_DX (1 << OPT_DX) #define OP_ADDR (1 << OPT_ADDR) #define OP_INDIR (1 << OPT_INDIR) #ifdef TCC_TARGET_X86_64 # define OP_REG64 (1 << OPT_REG64) # define OP_REG8_LOW (1 << OPT_REG8_LOW) # define OP_IM64 (1 << OPT_IM64) # define OP_EA32 (OP_EA << 1) #else # define OP_REG64 0 # define OP_REG8_LOW 0 # define OP_IM64 0 # define OP_EA32 0 #endif #define OP_EA 0x40000000 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64) #ifdef TCC_TARGET_X86_64 # define TREG_XAX TREG_RAX # define TREG_XCX TREG_RCX # define TREG_XDX TREG_RDX #else # define TREG_XAX TREG_EAX # define TREG_XCX TREG_ECX # define TREG_XDX TREG_EDX #endif typedef struct ASMInstr { uint16_t sym; uint16_t opcode; uint16_t instr_type; uint8_t nb_ops; uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */ } ASMInstr; typedef struct Operand { uint32_t type; int8_t reg; /* register, -1 if none */ int8_t reg2; /* second register, -1 if none */ uint8_t shift; ExprValue e; } Operand; static const uint8_t reg_to_size[9] = { /* [OP_REG8] = 0, [OP_REG16] = 1, [OP_REG32] = 2, #ifdef TCC_TARGET_X86_64 [OP_REG64] = 3, #endif */ 0, 0, 1, 0, 2, 0, 0, 0, 3 }; #define NB_TEST_OPCODES 30 static const uint8_t test_bits[NB_TEST_OPCODES] = { 0x00, /* o */ 0x01, /* no */ 0x02, /* b */ 0x02, /* c */ 0x02, /* nae */ 0x03, /* nb */ 0x03, /* nc */ 0x03, /* ae */ 0x04, /* e */ 0x04, /* z */ 0x05, /* ne */ 0x05, /* nz */ 0x06, /* be */ 0x06, /* na */ 0x07, /* nbe */ 0x07, /* a */ 0x08, /* s */ 0x09, /* ns */ 0x0a, /* p */ 0x0a, /* pe */ 0x0b, /* np */ 0x0b, /* po */ 0x0c, /* l */ 0x0c, /* nge */ 0x0d, /* nl */ 0x0d, /* ge */ 0x0e, /* le */ 0x0e, /* ng */ 0x0f, /* nle */ 0x0f, /* g */ }; static const uint8_t segment_prefixes[] = { 0x26, /* es */ 0x2e, /* cs */ 0x36, /* ss */ 0x3e, /* ds */ 0x64, /* fs */ 0x65 /* gs */ }; static const ASMInstr asm_instrs[] = { #define ALT(x) x /* This removes a 0x0f in the second byte */ #define O(o) ((uint64_t) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))) /* This constructs instr_type from opcode, type and group. */ #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0)) #define DEF_ASM_OP0(name, opcode) #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0, { 0 } }, #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }}, #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }}, #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }}, #ifdef TCC_TARGET_X86_64 # include "x86_64-asm.h" #else # include "i386-asm.h" #endif /* last operation */ { 0, }, }; static const uint16_t op0_codes[] = { #define ALT(x) #define DEF_ASM_OP0(x, opcode) opcode, #define DEF_ASM_OP0L(name, opcode, group, instr_type) #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) #ifdef TCC_TARGET_X86_64 # include "x86_64-asm.h" #else # include "i386-asm.h" #endif }; static inline int get_reg_shift(TCCState *s1) { int shift, v; v = asm_int_expr(s1); switch(v) { case 1: shift = 0; break; case 2: shift = 1; break; case 4: shift = 2; break; case 8: shift = 3; break; default: expect("1, 2, 4 or 8 constant"); shift = 0; break; } return shift; } #ifdef TCC_TARGET_X86_64 static int asm_parse_numeric_reg(int t, unsigned int *type) { int reg = -1; if (t >= TOK_IDENT && t < tok_ident) { const char *s = table_ident[t - TOK_IDENT]->str; char c; *type = OP_REG64; if (*s == 'c') { s++; *type = OP_CR; } if (*s++ != 'r') return -1; /* Don't allow leading '0'. */ if ((c = *s++) >= '1' && c <= '9') reg = c - '0'; else return -1; if ((c = *s) >= '0' && c <= '5') s++, reg = reg * 10 + c - '0'; if (reg > 15) return -1; if ((c = *s) == 0) ; else if (*type != OP_REG64) return -1; else if (c == 'b' && !s[1]) *type = OP_REG8; else if (c == 'w' && !s[1]) *type = OP_REG16; else if (c == 'd' && !s[1]) *type = OP_REG32; else return -1; } return reg; } #endif static int asm_parse_reg(unsigned int *type) { int reg = 0; *type = 0; if (tok != '%') goto error_32; next(); if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) { reg = tok - TOK_ASM_eax; *type = OP_REG32; #ifdef TCC_TARGET_X86_64 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) { reg = tok - TOK_ASM_rax; *type = OP_REG64; } else if (tok == TOK_ASM_rip) { reg = -2; /* Probably should use different escape code. */ *type = OP_REG64; } else if ((reg = asm_parse_numeric_reg(tok, type)) >= 0 && (*type == OP_REG32 || *type == OP_REG64)) { ; #endif } else { error_32: expect("register"); } next(); return reg; } static void parse_operand(TCCState *s1, Operand *op) { ExprValue e; int reg, indir; const char *p; indir = 0; if (tok == '*') { next(); indir = OP_INDIR; } if (tok == '%') { next(); if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) { reg = tok - TOK_ASM_al; op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */ op->reg = reg & 7; if ((op->type & OP_REG) && op->reg == TREG_XAX) op->type |= OP_EAX; else if (op->type == OP_REG8 && op->reg == TREG_XCX) op->type |= OP_CL; else if (op->type == OP_REG16 && op->reg == TREG_XDX) op->type |= OP_DX; } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) { op->type = OP_DB; op->reg = tok - TOK_ASM_dr0; } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) { op->type = OP_SEG; op->reg = tok - TOK_ASM_es; } else if (tok == TOK_ASM_st) { op->type = OP_ST; op->reg = 0; next(); if (tok == '(') { next(); if (tok != TOK_PPNUM) goto reg_error; p = tokc.str.data; reg = p[0] - '0'; if ((unsigned)reg >= 8 || p[1] != '\0') goto reg_error; op->reg = reg; next(); skip(')'); } if (op->reg == 0) op->type |= OP_ST0; goto no_skip; #ifdef TCC_TARGET_X86_64 } else if (tok >= TOK_ASM_spl && tok <= TOK_ASM_dil) { op->type = OP_REG8 | OP_REG8_LOW; op->reg = 4 + tok - TOK_ASM_spl; } else if ((op->reg = asm_parse_numeric_reg(tok, &op->type)) >= 0) { ; #endif } else { reg_error: tcc_error("unknown register %%%s", get_tok_str(tok, &tokc)); } next(); no_skip: ; } else if (tok == '$') { /* constant value */ next(); asm_expr(s1, &e); op->type = OP_IM32; op->e = e; if (!op->e.sym) { if (op->e.v == (uint8_t)op->e.v) op->type |= OP_IM8; if (op->e.v == (int8_t)op->e.v) op->type |= OP_IM8S; if (op->e.v == (uint16_t)op->e.v) op->type |= OP_IM16; #ifdef TCC_TARGET_X86_64 if (op->e.v != (int32_t)op->e.v && op->e.v != (uint32_t)op->e.v) op->type = OP_IM64; #endif } } else { /* address(reg,reg2,shift) with all variants */ op->type = OP_EA; op->reg = -1; op->reg2 = -1; op->shift = 0; if (tok != '(') { asm_expr(s1, &e); op->e = e; } else { next(); if (tok == '%') { unget_tok('('); op->e.v = 0; op->e.sym = NULL; } else { /* bracketed offset expression */ asm_expr(s1, &e); if (tok != ')') expect(")"); next(); op->e.v = e.v; op->e.sym = e.sym; } op->e.pcrel = 0; } if (tok == '(') { unsigned int type = 0; next(); if (tok != ',') { op->reg = asm_parse_reg(&type); } if (tok == ',') { next(); if (tok != ',') { op->reg2 = asm_parse_reg(&type); } if (tok == ',') { next(); op->shift = get_reg_shift(s1); } } if (type & OP_REG32) op->type |= OP_EA32; skip(')'); } if (op->reg == -1 && op->reg2 == -1) op->type |= OP_ADDR; } op->type |= indir; } /* XXX: unify with C code output ? */ ST_FUNC void gen_expr32(ExprValue *pe) { if (pe->pcrel) /* If PC-relative, always set VT_SYM, even without symbol, so as to force a relocation to be emitted. */ gen_addrpc32(VT_SYM, pe->sym, pe->v); else gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v); } #ifdef TCC_TARGET_X86_64 ST_FUNC void gen_expr64(ExprValue *pe) { gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v); } #endif /* XXX: unify with C code output ? */