and support sp in intr
Unified · Split
| @@ -79,6 +79,8 @@ enum { · 78 unmodified lines | ||
| 79 | 79 | TREG_F6, |
| 80 | 80 | TREG_F7, |
| 81 | 81 | #endif |
| 82 | + TREG_SP = 13, | |
| 83 | + TREG_LR, | |
| 82 | 84 | }; |
| 83 | 85 | |
| 84 | 86 | #ifdef TCC_ARM_VFP |
| @@ -406,24 +408,26 @@ static uint32_t vfpr(int r) · 321 unmodified lines | ||
| 406 | 408 | { |
| 407 | 409 | if(r<TREG_F0 || r>TREG_F7) |
| 408 | 410 | tcc_error("compiler error! register %i is no vfp register",r); |
| 409 | − return r-5; | |
| 411 | + return r - TREG_F0; | |
| 410 | 412 | } |
| 411 | 413 | #else |
| 412 | 414 | static uint32_t fpr(int r) |
| 413 | 415 | { |
| 414 | 416 | if(r<TREG_F0 || r>TREG_F3) |
| 415 | 417 | tcc_error("compiler error! register %i is no fpa register",r); |
| 416 | − return r-5; | |
| 418 | + return r - TREG_F0; | |
| 417 | 419 | } |
| 418 | 420 | #endif |
| 419 | 421 | |
| 420 | 422 | static uint32_t intr(int r) |
| 421 | 423 | { |
| 422 | − if(r==4) | |
| 424 | + if(r == TREG_R12) | |
| 423 | 425 | return 12; |
| 424 | − if((r<0 || r>4) && r!=14) | |
| 425 | − tcc_error("compiler error! register %i is no int register",r); | |
| 426 | − return r; | |
| 426 | + if(r >= TREG_R0 && r <= TREG_R3) | |
| 427 | + return r - TREG_R0; | |
| 428 | + if (r >= TREG_SP && r <= TREG_LR) | |
| 429 | + return r + (13 - TREG_SP); | |
| 430 | + tcc_error("compiler error! register %i is no int register",r); | |
| 427 | 431 | } |
| 428 | 432 | |
| 429 | 433 | static void calcaddr(uint32_t *base, int *off, int *sgn, int maxoff, unsigned shift) |
| @@ -544,7 +548,8 @@ void load(int r, SValue *sv) · 114 unmodified lines | ||
| 544 | 548 | v1.type.t = VT_PTR; |
| 545 | 549 | v1.r = VT_LOCAL | VT_LVAL; |
| 546 | 550 | v1.c.i = sv->c.i; |
| 547 | − load(base=14 /* lr */, &v1); | |
| 551 | + load(TREG_LR, &v1); | |
| 552 | + base = 14; /* lr */ | |
| 548 | 553 | fc=sign=0; |
| 549 | 554 | v=VT_LOCAL; |
| 550 | 555 | } else if(v == VT_CONST) { |
| @@ -552,7 +557,8 @@ void load(int r, SValue *sv) · 1 unmodified line | ||
| 552 | 557 | v1.r = fr&~VT_LVAL; |
| 553 | 558 | v1.c.i = sv->c.i; |
| 554 | 559 | v1.sym=sv->sym; |
| 555 | − load(base=14, &v1); | |
| 560 | + load(TREG_LR, &v1); | |
| 561 | + base = 14; /* lr */ | |
| 556 | 562 | fc=sign=0; |
| 557 | 563 | v=VT_LOCAL; |
| 558 | 564 | } else if(v < VT_CONST) { |
| @@ -678,7 +684,7 @@ void store(int r, SValue *sv) · 119 unmodified lines | ||
| 678 | 684 | |
| 679 | 685 | v = fr & VT_VALMASK; |
| 680 | 686 | if (fr & VT_LVAL || fr == VT_LOCAL) { |
| 681 | − uint32_t base = 0xb; | |
| 687 | + uint32_t base = 0xb; /* fp */ | |
| 682 | 688 | if(v < VT_CONST) { |
| 683 | 689 | base=intr(v); |
| 684 | 690 | v=VT_LOCAL; |
| @@ -688,7 +694,8 @@ void store(int r, SValue *sv) · 3 unmodified lines | ||
| 688 | 694 | v1.r = fr&~VT_LVAL; |
| 689 | 695 | v1.c.i = sv->c.i; |
| 690 | 696 | v1.sym=sv->sym; |
| 691 | − load(base=14, &v1); | |
| 697 | + load(TREG_LR, &v1); | |
| 698 | + base = 14; /* lr */ | |
| 692 | 699 | fc=sign=0; |
| 693 | 700 | v=VT_LOCAL; |
| 694 | 701 | } |