global scale sheevaplug & guruplug marvell 88f6281 (feroceon kirkwood) SoCarm926ej-s rev 1 [56251311] (armv5tejl) 1.2GHz cpu l1 I & D VIVT caches 16K each: 4-way, 128 sets, 32-byte lines	l1 D is write-through, l1 I is write-backunified l2 PIPT cache 256K: 4-way, 2048 sets, 32-byte lines	potentially 512K: 8-way apparently the mmu walks the page tables in dram and won't look in thel2 cache.  there is no hardware cache coherence, thus the l1 cachesneed to be flushed or invalidated when mmu mappings change, but l2only needs to be flushed or invalidated around dma operations and pagetable changes, and only the affected dma buffers and descriptors orpage table entries need to be flushed or invalidated in l2. we arrange that device registers are uncached. be aware that cache operations act on cache lines (of CACHELINESZbytes) as atomic units, so if you invalidate one word of a cache line,you invalidate the entire cache line, whether it's been written back(is clean) or not (is dirty).  mixed data structures with partsmaintained by hardware and other parts by software are especiallytricky.  we try to pad the initial hardware parts so that the softwareparts start in a new cache line. there are no video controllers so far, so this port is a cpukernel only. 512MB of dram at physical address 0512MB of nand flash16550 uart for consolesee http://www.marvell.com/files/products/embedded_processors/kirkwood/\	FS_88F6180_9x_6281_OpenSource.pdf, stored locally as	/public/doc/marvell/88f61xx.kirkwood.pdf If you plan to use flash, it would be wise to avoid touching the firstmegabyte, which contains u-boot, right up to 0x100000.  There's alinux kernel from there to 0x400000, if you care.  You'll also likelywant to use paqfs rather than fossil or kfs for file systems in flashsince there is no wear-levelling. The code is fairly heavy-handed with the use of barrier instructions(BARRIERS in assembler, coherence in C), partly in reaction to badexperience doing Power PC ports, but also just as precautions againstmodern processors, which may feel free to execute instructions out oforder or some time later, store to memory out of order or some timelater, otherwise break the model of traditional sequential processors,or any combination of the above. this plan 9 port is based on the port of native inferno to thesheevaplug by Salva Peiró (saoret.one@gmail.com) and Mechiel Lukkien(mechiel@ueber.net). ___ # type this once at u-boot, replacing 00504301c49e with your plug's# mac address; thereafter the plug will pxe boot:setenv bootdelay 2setenv bootcmd 'bootp; bootp; tftp 0x1000 /cfg/pxe/00504301c49e; bootp; tftp 0x800000; go 0x800000'saveenv # see /cfg/pxe/example-kw  	physical mem map hex addr size	what----0	 512MB	sdramc8010000 2K	cesa sram 	virtual mem map (from cpu address map & mmu mappings) hex addr size	what----0	 512MB	user process address space60000000 512MB	kzero, mapped to 090000000 256MB	pcie mem	# identity mapped by u-bootd0000000 1MB	internal regs default address at resetd8000000 128MB	nand flash	# 512MB addressed through this (guru)f0000000 16MB	pcie i/o	# mapped to 0xc0000000 by u-bootf1000000 1MB 	internal regs (on-chip devices) as mapped by u-bootf1000000 64K	dram regsf1010000 64K	uart, flashes, rtc, gpio, etc.f1030000 64K	crypto accelerator (cesa)f1040000 64K	pcie regsf1050000 64K	usb otg regs (ehci-like)f1070000 64K	gbe regsf1080000 64K	non-ahci sata regsf1090000 64K	sdio regsf8000000 16MB	spi flash	# mapped to 0 by u-bootf9000000 8MB	nand flash	# identity mapped by u-boot (sheeva/openrd)fb000000 64KB	crypto engine	# identity mapped by u-bootff000000 16MB	boot rom	# identity mapped by u-boot... 		as per physical map