#include "mem.h" /* use of SPRG registers in save/restore */#define SAVER0 SPRG0#define SAVER1 SPRG1#define SAVELR SPRG2#define SAVEXX SPRG3 #ifdef ucuconf/* These only exist on the PPC 755: */#define SAVER4 SPRG4#define SAVER5 SPRG5#define SAVER6 SPRG6#define SAVER7 SPRG7#endif /* ucuconf */ /* special instruction definitions */#define BDNZ BC 16, 0,#define BDNE BC 0, 2,#define MTCRF(r, crm) WORD $((31<<26)|((r)<<21)|(crm<<12)|(144<<1)) /* #define TLBIA WORD $((31<<26)|(370<<1)) Not implemented on the 603e */#define TLBSYNC WORD $((31<<26)|(566<<1))#define TLBLI(n) WORD $((31<<26)|((n)<<11)|(1010<<1))#define TLBLD(n) WORD $((31<<26)|((n)<<11)|(978<<1)) /* on some models mtmsr doesn't synchronise enough (eg, 603e) */#define MSRSYNC SYNC #define UREGSPACE (UREGSIZE+8) TEXT start(SB), $-4 /* * setup MSR * turn off interrupts * use 0x000 as exception prefix * enable machine check */ MOVW MSR, R3 MOVW $(MSR_ME|MSR_EE|MSR_IP), R4 ANDN R4, R3 SYNC MOVW R3, MSR MSRSYNC /* except during trap handling, R0 is zero from now on */ MOVW $0, R0 /* setup SB for pre mmu */ MOVW $setSB(SB), R2 MOVW $KZERO, R3 ANDN R3, R2 /* before this we're not running above KZERO */ BL mmuinit0(SB) /* after this we are */ #ifdef ucuconf MOVW $0x2000000, R4 /* size */ MOVW $0, R3 /* base address */ RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE _dcf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTR_dcf0: DCBF (R5) ADD $CACHELINESZ, R5 BDNZ _dcf0_dcf1: SYNC /* BAT0, 3 unused, copy of BAT2 */ MOVW SPR(IBATL(2)), R3 MOVW R3, SPR(IBATL(0)) MOVW SPR(IBATU(2)), R3 MOVW R3, SPR(IBATU(0)) MOVW SPR(DBATL(2)), R3 MOVW R3, SPR(DBATL(0)) MOVW SPR(DBATU(2)), R3 MOVW R3, SPR(DBATU(0)) MOVW SPR(IBATL(2)), R3 MOVW R3, SPR(IBATL(3)) MOVW SPR(IBATU(2)), R3 MOVW R3, SPR(IBATU(3)) MOVW SPR(DBATL(2)), R3 MOVW R3, SPR(DBATL(3)) MOVW SPR(DBATU(2)), R3 MOVW R3, SPR(DBATU(3))#endif /* ucuconf */ /* running with MMU on!! */ /* set R2 to correct value */ MOVW $setSB(SB), R2 /* set up Mach */ MOVW $MACHADDR, R(MACH) ADD $(MACHSIZE-8), R(MACH), R1 /* set stack */ MOVW R0, R(USER) /* up-> set to zero */ MOVW R0, 0(R(MACH)) /* machno set to zero */ BL main(SB) RETURN /* not reached */ /* * on return from this function we will be running in virtual mode. * We set up the Block Address Translation (BAT) registers thus: * 1) first 3 BATs are 256M blocks, starting from KZERO->0 * 2) remaining BAT maps last 256M directly */TEXT mmuinit0(SB), $0 /* reset all the tlbs */ MOVW $64, R3 MOVW R3, CTR MOVW $0, R4 tlbloop: TLBIE R4 SYNC ADD $BIT(19), R4 BDNZ tlbloop TLBSYNC #ifndef ucuconf /* BATs 0 and 1 cover memory from 0x00000000 to 0x20000000 */ /* KZERO -> 0, IBAT and DBAT, 256 MB */ MOVW $(KZERO|(0x7ff<<2)|2), R3 MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */ MOVW R3, SPR(IBATU(0)) MOVW R4, SPR(IBATL(0)) MOVW R3, SPR(DBATU(0)) MOVW R4, SPR(DBATL(0)) /* KZERO+256M -> 256M, IBAT and DBAT, 256 MB */ ADD $(1<<28), R3 ADD $(1<<28), R4 MOVW R3, SPR(IBATU(1)) MOVW R4, SPR(IBATL(1)) MOVW R3, SPR(DBATU(1)) MOVW R4, SPR(DBATL(1)) /* FPGABASE -> FPGABASE, DBAT, 16 MB */ MOVW $(FPGABASE|(0x7f<<2)|2), R3 MOVW $(FPGABASE|PTEWRITE|PTEUNCACHED), R4 /* FPGA memory, don't cache */ MOVW R3, SPR(DBATU(2)) MOVW R4, SPR(DBATL(2)) /* IBAT 2 unused */ MOVW R0, SPR(IBATU(2)) MOVW R0, SPR(IBATL(2)) /* direct map last block, uncached, (not guarded, doesn't work for BAT), DBAT only */ MOVW $(INTMEM|(0x7ff<<2)|2), R3 MOVW $(INTMEM|PTEWRITE|PTEUNCACHED), R4 /* Don't set PTEVALID here */ MOVW R3, SPR(DBATU(3)) MOVW R4, SPR(DBATL(3)) /* IBAT 3 unused */ MOVW R0, SPR(IBATU(3)) MOVW R0, SPR(IBATL(3))#else /* ucuconf */ /* BAT 2 covers memory from 0x00000000 to 0x10000000 */ /* KZERO -> 0, IBAT2 and DBAT2, 256 MB */ MOVW $(KZERO|(0x7ff<<2)|2), R3 MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */ MOVW R3, SPR(DBATU(2)) MOVW R4, SPR(DBATL(2)) MOVW R3, SPR(IBATU(2)) MOVW R4, SPR(IBATL(2))#endif /* ucuconf */ /* enable MMU */ MOVW LR, R3 OR $KZERO, R3 MOVW R3, SPR(SRR0) /* Stored PC for RFI instruction */ MOVW MSR, R4 OR $(MSR_IR|MSR_DR|MSR_RI|MSR_FP), R4 MOVW R4, SPR(SRR1) RFI /* resume in kernel mode in caller */ RETURN TEXT kfpinit(SB), $0 MOVFL $0, FPSCR(7) MOVFL $0xD, FPSCR(6) /* VE, OE, ZE */ MOVFL $0, FPSCR(5) MOVFL $0, FPSCR(3) MOVFL $0, FPSCR(2) MOVFL $0, FPSCR(1) MOVFL $0, FPSCR(0) FMOVD $4503601774854144.0, F27 FMOVD $0.5, F29 FSUB F29, F29, F28 FADD F29, F29, F30 FADD F30, F30, F31 FMOVD F28, F0 FMOVD F28, F1 FMOVD F28, F2 FMOVD F28, F3 FMOVD F28, F4 FMOVD F28, F5 FMOVD F28, F6 FMOVD F28, F7 FMOVD F28, F8 FMOVD F28, F9 FMOVD F28, F10 FMOVD F28, F11 FMOVD F28, F12 FMOVD F28, F13 FMOVD F28, F14 FMOVD F28, F15 FMOVD F28, F16 FMOVD F28, F17 FMOVD F28, F18 FMOVD F28, F19 FMOVD F28, F20 FMOVD F28, F21 FMOVD F28, F22 FMOVD F28, F23 FMOVD F28, F24 FMOVD F28, F25 FMOVD F28, F26 RETURN TEXT splhi(SB), $0 MOVW LR, R31 MOVW R31, 4(R(MACH)) /* save PC in m->splpc */ MOVW MSR, R3 RLWNM $0, R3, $~MSR_EE, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT splx(SB), $0 /* fall though */ TEXT splxpc(SB), $0 MOVW LR, R31 MOVW R31, 4(R(MACH)) /* save PC in m->splpc */ MOVW MSR, R4 RLWMI $0, R3, $MSR_EE, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT spllo(SB), $0 MOVW MSR, R3 OR $MSR_EE, R3, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT spldone(SB), $0 RETURN TEXT islo(SB), $0 MOVW MSR, R3 RLWNM $0, R3, $MSR_EE, R3 RETURN TEXT setlabel(SB), $-4 MOVW LR, R31 MOVW R1, 0(R3) MOVW R31, 4(R3) MOVW $0, R3 RETURN TEXT gotolabel(SB), $-4 MOVW 4(R3), R31 MOVW R31, LR MOVW 0(R3), R1 MOVW $1, R3 RETURN TEXT touser(SB), $-4 MOVW $(UTZERO+32), R5 /* header appears in text */ MOVW $(MSR_EE|MSR_PR|MSR_IR|MSR_DR|MSR_RI), R4 MOVW R4, SPR(SRR1) MOVW R3, R1 MOVW R5, SPR(SRR0) RFI TEXT dczap(SB), $-4 /* dczap(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE dcz1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTRdcz0: DCBI (R5) ADD $CACHELINESZ, R5 BDNZ dcz0dcz1: SYNC RETURN TEXT dcflush(SB), $-4 /* dcflush(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE dcf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTRdcf0: DCBST (R5) ADD $CACHELINESZ, R5 BDNZ dcf0dcf1: SYNC RETURN TEXT icflush(SB), $-4 /* icflush(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE icf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTRicf0: ICBI (R5) /* invalidate the instruction cache */ ADD $CACHELINESZ, R5 BDNZ icf0 ISYNCicf1: RETURN TEXT tas(SB), $0 MOVW R3, R4 MOVW $0xdead, R5tas1: DCBF (R4) /* fix for 603x bug */ SYNC LWAR (R4), R3 CMP R3, $0 BNE tas0 STWCCC R5, (R4) BNE tas1 EIEIOtas0: SYNC RETURN TEXT _xinc(SB), $0 /* void _xinc(long *); */ MOVW R3, R4xincloop: DCBF (R4) /* fix for 603x bug */ LWAR (R4), R3 ADD $1, R3 STWCCC R3, (R4) BNE xincloop RETURN TEXT _xdec(SB), $0 /* long _xdec(long *); */ MOVW R3, R4xdecloop: DCBF (R4) /* fix for 603x bug */ LWAR (R4), R3 ADD $-1, R3 STWCCC R3, (R4) BNE xdecloop RETURN TEXT cmpswap(SB),$0 /* int cmpswap(long*, long, long) */ MOVW R3, R4 /* addr */ MOVW old+4(FP), R5 MOVW new+8(FP), R6 DCBF (R4) /* fix for 603x bug? */ LWAR (R4), R3 CMP R3, R5 BNE fail STWCCC R6, (R4) BNE fail MOVW $1, R3 RETURNfail: MOVW $0, R3 RETURN TEXT tlbflushall(SB), $0 MOVW $TLBENTRIES, R3 MOVW R3, CTR MOVW $0, R4 ISYNCtlbflushall0: TLBIE R4 SYNC ADD $BIT(19), R4 BDNZ tlbflushall0 TLBSYNC RETURN TEXT tlbflush(SB), $0 ISYNC TLBIE R3 SYNC TLBSYNC RETURN TEXT gotopc(SB), $0 MOVW R3, CTR MOVW LR, R31 /* for trace back */ BR (CTR) /* On an imiss, we get here. If we can resolve it, we do. * Otherwise take the real trap. The code at the vector is * MOVW R0, SPR(SAVER0) No point to this, of course * MOVW LR, R0 * MOVW R0, SPR(SAVELR) * BL imiss(SB) or dmiss, as the case may be * BL tlbvec(SB) */TEXT imiss(SB), $-4 /* Statistics */ MOVW $MACHPADDR, R1 MOVW 0xc(R1), R3 /* count m->tlbfault */ ADD $1, R3 MOVW R3, 0xc(R1) MOVW 0x10(R1), R3 /* count m->imiss */ ADD $1, R3 MOVW R3, 0x10(R1) /* Real work */ MOVW SPR(HASH1), R1 /* (phys) pointer into the hash table */ ADD $BY2PTEG, R1, R2 /* end pointer */ MOVW SPR(iCMP), R3 /* pattern to look for */imiss1: MOVW (R1), R0 CMP R3, R0 BEQ imiss2 /* found the entry */ ADD $8, R1 CMP R1, R2 /* test end of loop */ BNE imiss1 /* Loop */ /* Failed to find an entry; take the full trap */ MOVW SPR(SRR1), R1 MTCRF(1, 0x80) /* restore CR0 bits (they're auto saved in SRR1) */ RETURNimiss2: /* Found the entry */ MOVW 4(R1), R2 /* Phys addr */ MOVW R2, SPR(RPA) MOVW SPR(IMISS), R3 TLBLI(3) /* Restore Registers */ MOVW SPR(SRR1), R1 /* Restore the CR0 field of the CR register from SRR1 */ MTCRF(1, 0x80) MOVW SPR(SAVELR), R0 MOVW R0, LR RFI /* On a data load or store miss, we get here. If we can resolve it, we do. * Otherwise take the real trap */TEXT dmiss(SB), $-4 /* Statistics */ MOVW $MACHPADDR, R1 MOVW 0xc(R1), R3 /* count m->tlbfault */ ADD $1, R3 MOVW R3, 0xc(R1) MOVW 0x14(R1), R3 /* count m->dmiss */ ADD $1, R3 MOVW R3, 0x14(R1) /* Real work */ MOVW SPR(HASH1), R1 /* (phys) pointer into the hash table */ ADD $BY2PTEG, R1, R2 /* end pointer */ MOVW SPR(DCMP), R3 /* pattern to look for */dmiss1: MOVW (R1), R0 CMP R3, R0 BEQ dmiss2 /* found the entry */ ADD $8, R1 CMP R1, R2 /* test end of loop */ BNE dmiss1 /* Loop */ /* Failed to find an entry; take the full trap */ MOVW SPR(SRR1), R1 MTCRF(1, 0x80) /* restore CR0 bits (they're auto saved in SRR1) */ RETURNdmiss2: /* Found the entry */Lines 1–500 of 1053. Load more
#include "mem.h" /* use of SPRG registers in save/restore */ #define SAVER0 SPRG0 #define SAVER1 SPRG1 #define SAVELR SPRG2 #define SAVEXX SPRG3 #ifdef ucuconf /* These only exist on the PPC 755: */ #define SAVER4 SPRG4 #define SAVER5 SPRG5 #define SAVER6 SPRG6 #define SAVER7 SPRG7 #endif /* ucuconf */ /* special instruction definitions */ #define BDNZ BC 16, 0, #define BDNE BC 0, 2, #define MTCRF(r, crm) WORD $((31<<26)|((r)<<21)|(crm<<12)|(144<<1)) /* #define TLBIA WORD $((31<<26)|(370<<1)) Not implemented on the 603e */ #define TLBSYNC WORD $((31<<26)|(566<<1)) #define TLBLI(n) WORD $((31<<26)|((n)<<11)|(1010<<1)) #define TLBLD(n) WORD $((31<<26)|((n)<<11)|(978<<1)) /* on some models mtmsr doesn't synchronise enough (eg, 603e) */ #define MSRSYNC SYNC #define UREGSPACE (UREGSIZE+8) TEXT start(SB), $-4 /* * setup MSR * turn off interrupts * use 0x000 as exception prefix * enable machine check */ MOVW MSR, R3 MOVW $(MSR_ME|MSR_EE|MSR_IP), R4 ANDN R4, R3 SYNC MOVW R3, MSR MSRSYNC /* except during trap handling, R0 is zero from now on */ MOVW $0, R0 /* setup SB for pre mmu */ MOVW $setSB(SB), R2 MOVW $KZERO, R3 ANDN R3, R2 /* before this we're not running above KZERO */ BL mmuinit0(SB) /* after this we are */ #ifdef ucuconf MOVW $0x2000000, R4 /* size */ MOVW $0, R3 /* base address */ RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE _dcf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTR _dcf0: DCBF (R5) ADD $CACHELINESZ, R5 BDNZ _dcf0 _dcf1: SYNC /* BAT0, 3 unused, copy of BAT2 */ MOVW SPR(IBATL(2)), R3 MOVW R3, SPR(IBATL(0)) MOVW SPR(IBATU(2)), R3 MOVW R3, SPR(IBATU(0)) MOVW SPR(DBATL(2)), R3 MOVW R3, SPR(DBATL(0)) MOVW SPR(DBATU(2)), R3 MOVW R3, SPR(DBATU(0)) MOVW SPR(IBATL(2)), R3 MOVW R3, SPR(IBATL(3)) MOVW SPR(IBATU(2)), R3 MOVW R3, SPR(IBATU(3)) MOVW SPR(DBATL(2)), R3 MOVW R3, SPR(DBATL(3)) MOVW SPR(DBATU(2)), R3 MOVW R3, SPR(DBATU(3)) #endif /* ucuconf */ /* running with MMU on!! */ /* set R2 to correct value */ MOVW $setSB(SB), R2 /* set up Mach */ MOVW $MACHADDR, R(MACH) ADD $(MACHSIZE-8), R(MACH), R1 /* set stack */ MOVW R0, R(USER) /* up-> set to zero */ MOVW R0, 0(R(MACH)) /* machno set to zero */ BL main(SB) RETURN /* not reached */ /* * on return from this function we will be running in virtual mode. * We set up the Block Address Translation (BAT) registers thus: * 1) first 3 BATs are 256M blocks, starting from KZERO->0 * 2) remaining BAT maps last 256M directly */ TEXT mmuinit0(SB), $0 /* reset all the tlbs */ MOVW $64, R3 MOVW R3, CTR MOVW $0, R4 tlbloop: TLBIE R4 SYNC ADD $BIT(19), R4 BDNZ tlbloop TLBSYNC #ifndef ucuconf /* BATs 0 and 1 cover memory from 0x00000000 to 0x20000000 */ /* KZERO -> 0, IBAT and DBAT, 256 MB */ MOVW $(KZERO|(0x7ff<<2)|2), R3 MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */ MOVW R3, SPR(IBATU(0)) MOVW R4, SPR(IBATL(0)) MOVW R3, SPR(DBATU(0)) MOVW R4, SPR(DBATL(0)) /* KZERO+256M -> 256M, IBAT and DBAT, 256 MB */ ADD $(1<<28), R3 ADD $(1<<28), R4 MOVW R3, SPR(IBATU(1)) MOVW R4, SPR(IBATL(1)) MOVW R3, SPR(DBATU(1)) MOVW R4, SPR(DBATL(1)) /* FPGABASE -> FPGABASE, DBAT, 16 MB */ MOVW $(FPGABASE|(0x7f<<2)|2), R3 MOVW $(FPGABASE|PTEWRITE|PTEUNCACHED), R4 /* FPGA memory, don't cache */ MOVW R3, SPR(DBATU(2)) MOVW R4, SPR(DBATL(2)) /* IBAT 2 unused */ MOVW R0, SPR(IBATU(2)) MOVW R0, SPR(IBATL(2)) /* direct map last block, uncached, (not guarded, doesn't work for BAT), DBAT only */ MOVW $(INTMEM|(0x7ff<<2)|2), R3 MOVW $(INTMEM|PTEWRITE|PTEUNCACHED), R4 /* Don't set PTEVALID here */ MOVW R3, SPR(DBATU(3)) MOVW R4, SPR(DBATL(3)) /* IBAT 3 unused */ MOVW R0, SPR(IBATU(3)) MOVW R0, SPR(IBATL(3)) #else /* ucuconf */ /* BAT 2 covers memory from 0x00000000 to 0x10000000 */ /* KZERO -> 0, IBAT2 and DBAT2, 256 MB */ MOVW $(KZERO|(0x7ff<<2)|2), R3 MOVW $(PTEVALID|PTEWRITE), R4 /* PTEVALID => Cache coherency on */ MOVW R3, SPR(DBATU(2)) MOVW R4, SPR(DBATL(2)) MOVW R3, SPR(IBATU(2)) MOVW R4, SPR(IBATL(2)) #endif /* ucuconf */ /* enable MMU */ MOVW LR, R3 OR $KZERO, R3 MOVW R3, SPR(SRR0) /* Stored PC for RFI instruction */ MOVW MSR, R4 OR $(MSR_IR|MSR_DR|MSR_RI|MSR_FP), R4 MOVW R4, SPR(SRR1) RFI /* resume in kernel mode in caller */ RETURN TEXT kfpinit(SB), $0 MOVFL $0, FPSCR(7) MOVFL $0xD, FPSCR(6) /* VE, OE, ZE */ MOVFL $0, FPSCR(5) MOVFL $0, FPSCR(3) MOVFL $0, FPSCR(2) MOVFL $0, FPSCR(1) MOVFL $0, FPSCR(0) FMOVD $4503601774854144.0, F27 FMOVD $0.5, F29 FSUB F29, F29, F28 FADD F29, F29, F30 FADD F30, F30, F31 FMOVD F28, F0 FMOVD F28, F1 FMOVD F28, F2 FMOVD F28, F3 FMOVD F28, F4 FMOVD F28, F5 FMOVD F28, F6 FMOVD F28, F7 FMOVD F28, F8 FMOVD F28, F9 FMOVD F28, F10 FMOVD F28, F11 FMOVD F28, F12 FMOVD F28, F13 FMOVD F28, F14 FMOVD F28, F15 FMOVD F28, F16 FMOVD F28, F17 FMOVD F28, F18 FMOVD F28, F19 FMOVD F28, F20 FMOVD F28, F21 FMOVD F28, F22 FMOVD F28, F23 FMOVD F28, F24 FMOVD F28, F25 FMOVD F28, F26 RETURN TEXT splhi(SB), $0 MOVW LR, R31 MOVW R31, 4(R(MACH)) /* save PC in m->splpc */ MOVW MSR, R3 RLWNM $0, R3, $~MSR_EE, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT splx(SB), $0 /* fall though */ TEXT splxpc(SB), $0 MOVW LR, R31 MOVW R31, 4(R(MACH)) /* save PC in m->splpc */ MOVW MSR, R4 RLWMI $0, R3, $MSR_EE, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT spllo(SB), $0 MOVW MSR, R3 OR $MSR_EE, R3, R4 SYNC MOVW R4, MSR MSRSYNC RETURN TEXT spldone(SB), $0 RETURN TEXT islo(SB), $0 MOVW MSR, R3 RLWNM $0, R3, $MSR_EE, R3 RETURN TEXT setlabel(SB), $-4 MOVW LR, R31 MOVW R1, 0(R3) MOVW R31, 4(R3) MOVW $0, R3 RETURN TEXT gotolabel(SB), $-4 MOVW 4(R3), R31 MOVW R31, LR MOVW 0(R3), R1 MOVW $1, R3 RETURN TEXT touser(SB), $-4 MOVW $(UTZERO+32), R5 /* header appears in text */ MOVW $(MSR_EE|MSR_PR|MSR_IR|MSR_DR|MSR_RI), R4 MOVW R4, SPR(SRR1) MOVW R3, R1 MOVW R5, SPR(SRR0) RFI TEXT dczap(SB), $-4 /* dczap(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE dcz1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTR dcz0: DCBI (R5) ADD $CACHELINESZ, R5 BDNZ dcz0 dcz1: SYNC RETURN TEXT dcflush(SB), $-4 /* dcflush(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE dcf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTR dcf0: DCBST (R5) ADD $CACHELINESZ, R5 BDNZ dcf0 dcf1: SYNC RETURN TEXT icflush(SB), $-4 /* icflush(virtaddr, count) */ MOVW n+4(FP), R4 RLWNM $0, R3, $~(CACHELINESZ-1), R5 CMP R4, $0 BLE icf1 SUB R5, R3 ADD R3, R4 ADD $(CACHELINESZ-1), R4 SRAW $CACHELINELOG, R4 MOVW R4, CTR icf0: ICBI (R5) /* invalidate the instruction cache */ ADD $CACHELINESZ, R5 BDNZ icf0 ISYNC icf1: RETURN TEXT tas(SB), $0 MOVW R3, R4 MOVW $0xdead, R5 tas1: DCBF (R4) /* fix for 603x bug */ SYNC LWAR (R4), R3 CMP R3, $0 BNE tas0 STWCCC R5, (R4) BNE tas1 EIEIO tas0: SYNC RETURN TEXT _xinc(SB), $0 /* void _xinc(long *); */ MOVW R3, R4 xincloop: DCBF (R4) /* fix for 603x bug */ LWAR (R4), R3 ADD $1, R3 STWCCC R3, (R4) BNE xincloop RETURN TEXT _xdec(SB), $0 /* long _xdec(long *); */ MOVW R3, R4 xdecloop: DCBF (R4) /* fix for 603x bug */ LWAR (R4), R3 ADD $-1, R3 STWCCC R3, (R4) BNE xdecloop RETURN TEXT cmpswap(SB),$0 /* int cmpswap(long*, long, long) */ MOVW R3, R4 /* addr */ MOVW old+4(FP), R5 MOVW new+8(FP), R6 DCBF (R4) /* fix for 603x bug? */ LWAR (R4), R3 CMP R3, R5 BNE fail STWCCC R6, (R4) BNE fail MOVW $1, R3 RETURN fail: MOVW $0, R3 RETURN TEXT tlbflushall(SB), $0 MOVW $TLBENTRIES, R3 MOVW R3, CTR MOVW $0, R4 ISYNC tlbflushall0: TLBIE R4 SYNC ADD $BIT(19), R4 BDNZ tlbflushall0 TLBSYNC RETURN TEXT tlbflush(SB), $0 ISYNC TLBIE R3 SYNC TLBSYNC RETURN TEXT gotopc(SB), $0 MOVW R3, CTR MOVW LR, R31 /* for trace back */ BR (CTR) /* On an imiss, we get here. If we can resolve it, we do. * Otherwise take the real trap. The code at the vector is * MOVW R0, SPR(SAVER0) No point to this, of course * MOVW LR, R0 * MOVW R0, SPR(SAVELR) * BL imiss(SB) or dmiss, as the case may be * BL tlbvec(SB) */ TEXT imiss(SB), $-4 /* Statistics */ MOVW $MACHPADDR, R1 MOVW 0xc(R1), R3 /* count m->tlbfault */ ADD $1, R3 MOVW R3, 0xc(R1) MOVW 0x10(R1), R3 /* count m->imiss */ ADD $1, R3 MOVW R3, 0x10(R1) /* Real work */ MOVW SPR(HASH1), R1 /* (phys) pointer into the hash table */ ADD $BY2PTEG, R1, R2 /* end pointer */ MOVW SPR(iCMP), R3 /* pattern to look for */ imiss1: MOVW (R1), R0 CMP R3, R0 BEQ imiss2 /* found the entry */ ADD $8, R1 CMP R1, R2 /* test end of loop */ BNE imiss1 /* Loop */ /* Failed to find an entry; take the full trap */ MOVW SPR(SRR1), R1 MTCRF(1, 0x80) /* restore CR0 bits (they're auto saved in SRR1) */ RETURN imiss2: /* Found the entry */ MOVW 4(R1), R2 /* Phys addr */ MOVW R2, SPR(RPA) MOVW SPR(IMISS), R3 TLBLI(3) /* Restore Registers */ MOVW SPR(SRR1), R1 /* Restore the CR0 field of the CR register from SRR1 */ MTCRF(1, 0x80) MOVW SPR(SAVELR), R0 MOVW R0, LR RFI /* On a data load or store miss, we get here. If we can resolve it, we do. * Otherwise take the real trap */ TEXT dmiss(SB), $-4 /* Statistics */ MOVW $MACHPADDR, R1 MOVW 0xc(R1), R3 /* count m->tlbfault */ ADD $1, R3 MOVW R3, 0xc(R1) MOVW 0x14(R1), R3 /* count m->dmiss */ ADD $1, R3 MOVW R3, 0x14(R1) /* Real work */ MOVW SPR(HASH1), R1 /* (phys) pointer into the hash table */ ADD $BY2PTEG, R1, R2 /* end pointer */ MOVW SPR(DCMP), R3 /* pattern to look for */ dmiss1: MOVW (R1), R0 CMP R3, R0 BEQ dmiss2 /* found the entry */ ADD $8, R1 CMP R1, R2 /* test end of loop */ BNE dmiss1 /* Loop */ /* Failed to find an entry; take the full trap */ MOVW SPR(SRR1), R1 MTCRF(1, 0x80) /* restore CR0 bits (they're auto saved in SRR1) */ RETURN dmiss2: /* Found the entry */