/*  * This file is part of the UCB release of Plan 9. It is subject to the license * terms in the LICENSE file found in the top-level directory of this * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No * part of the UCB release of Plan 9, including this file, may be copied, * modified, propagated, or distributed except according to the terms contained * in the LICENSE file. */ #include <u.h>#include <libc.h>#include <bio.h>#include <mach.h>#define Extern extern#include "sparc.h" void add(ulong);void and(ulong);void or(ulong);void xor(ulong);void sub(ulong);void andn(ulong);void xnor(ulong);void subcc(ulong);void sll(ulong);void srl(ulong);void sra(ulong);void jmpl(ulong);void andcc(ulong);void xorcc(ulong);void andncc(ulong);void wry(ulong);void rdy(ulong);void mulscc(ulong);void fcmp(ulong);void farith(ulong);void addcc(ulong);void addx(ulong);void addxcc(ulong);void orcc(ulong);void orncc(ulong);void xnorcc(ulong);void orn(ulong); Inst op2[] = {	{ add,		"add",	Iarith },	{ and,		"and",	Iarith },	{ or,		"or",	Iarith },	{ xor,		"xor",	Iarith },	{ sub,		"sub",	Iarith },	{ andn,		"andn", Iarith },	{ orn,		"orn",	Inop },	{ xnor,		"xnor", Iarith },	{ addx,		"addx", Iarith },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ addcc, 	"addcc", Iarith },	{ andcc, 	"andcc", Iarith },	{ orcc,	 	"orcc",  Iarith },	{ xorcc, 	"xorcc", Iarith },	{ subcc, 	"subcc", Iarith },	{ andncc,	"andncc",Iarith },	{ orncc, 	"orncc", Iarith },	{ xnorcc,	"xnorcc",Iarith },	{ addxcc,	"addxcc",Iarith },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ mulscc,	"mulscc", Iarith },	{ sll,		"sll",	Iarith },	{ srl,		"srl",	Iarith },	{ sra,		"sra",	Iarith },	{ rdy,		"rdy",	Ireg },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ wry,		"wry",	Ireg },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ farith,	"farith", Ifloat },	{ fcmp,		"fcmp", Ifloat },	{ undef,	"" },	{ undef,	"" },	{ jmpl,		"jmpl", Ibranch },	{ undef,	"" },	{ ta,		"ta",	Isyscall },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ 0 }}; void st(ulong);void stb(ulong);void sth(ulong);void ld(ulong);void ldub(ulong);void ldsb(ulong);void lduh(ulong);void stf(ulong);void ldf(ulong);void ldsh(ulong);void std(ulong);void ldd(ulong);void ldstub(ulong);void swap(ulong);void lddf(ulong);void stdf(ulong); Inst op3[] = {	{ ld,		"ld",	Iload },	{ ldub,		"ldub",	Iload },	{ lduh,		"lduh",	Iload },	{ ldd,		"ldd",	Iload },	{ st,		"st",	Istore },	{ stb,		"stb",	Istore },	{ sth,		"sth",	Istore },	{ std,		"std",	Istore },	{ undef,	"" },	{ ldsb,		"ldsb",	Iload },	{ ldsh,		"ldsh", Iload },	{ undef,	"" },	{ undef,	"" },	{ ldstub,	"ldstub", Iload },	{ undef,	"" },	{ swap,		"swap",	Iload },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ ldf,		"ldf",	Ifloat },	{ undef,	"" },	{ undef,	"" },	{ lddf,		"lddf", Ifloat },	{ stf,		"stf",	Ifloat },	{ undef,	"" },	{ undef,	"" },	{ stdf,		"stdf",	Ifloat },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ undef,	"" },	{ 0 }}; void sethi(ulong);void bicc(ulong);void fbcc(ulong);void call(ulong); Inst op0[] = {	{ undef,	"" },	{ undef,	"" },	{ bicc,		"bicc",	Ibranch },	{ undef,	"" },	{ sethi,	"sethi",Iarith },	{ undef,	"" },	{ fbcc,		"fbcc",	Ibranch },	{ undef,	"" },	/* This is a fake and connot be reached by op0 decode */	{ call,		"call", Ibranch },	{ 0 }}; void call(ulong); voidrun(void){	do {		reg.r[0] = 0;		reg.ir = ifetch(reg.pc);		switch(reg.ir>>30) {		case 0:			ci = &op0[(reg.ir>>22)&0x07];			ci->count++;			(*ci->func)(reg.ir);			break;		case 1:			ci = &op0[8];			ci->count++;			call(reg.ir);			break;		case 2:			ci = &op2[(reg.ir>>19)&0x3f];			ci->count++;			(*ci->func)(reg.ir);			break;		case 3:			ci = &op3[(reg.ir>>19)&0x3f];			ci->count++;			(*ci->func)(reg.ir);			break;		}		reg.pc += 4;		if(bplist)			brkchk(reg.pc, Instruction);	}while(--count);} voidilock(int rd){	ulong ir; 	ir = getmem_4(reg.pc+4);	switch(ir>>30) {	case 0:	case 1:		break;	case 2:		if(((ir>>20)&0x1f) == 0x1a)		/* floating point */			break;	case 3:		if(rd == ((ir>>14)&0x1f)) {			loadlock++;			break;		}		if(ir&IMMBIT)			break;		if(rd == (ir&0x1f))			loadlock++;		break;	}} voiddelay(ulong npc){	ulong opc; 	reg.r[0] = 0;	if(reg.ir != NOP)		ci->useddelay++;	switch(reg.ir>>30) {	case 0:		ci = &op0[(reg.ir>>22)&0x07];		ci->count++;		(*ci->func)(reg.ir);		break;	case 1:		ci = &op0[8];		ci->count++;		call(reg.ir);		break;	case 2:		ci = &op2[(reg.ir>>19)&0x3f];		ci->count++;		opc = reg.pc;		reg.pc = npc-4;		(*ci->func)(reg.ir);		reg.pc = opc;		break;	case 3:		ci = &op3[(reg.ir>>19)&0x3f];		ci->count++;		opc = reg.pc;		reg.pc = npc-4;		(*ci->func)(reg.ir);		reg.pc = opc;		break;	}} voidundef(ulong ir){/*	Bprint(bioout, "op=%d op2=%d op3=%d\n", ir>>30, (ir>>21)&0x7, (ir>>19)&0x3f); */	Bprint(bioout, "illegal_instruction IR #%.8lux\n", ir);	longjmp(errjmp, 0);} voidsub(ulong ir){	long v;	int rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("sub\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("sub\tr%d,r%d,r%d", rs1, rs2, rd);	}	reg.r[rd] = reg.r[rs1] - v;} voidsll(ulong ir){	long v;	int rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("sll\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2]&0x1F;		if(trace)			itrace("sll\tr%d,r%d,r%d", rs1, rs2, rd);	}	reg.r[rd] = reg.r[rs1] << v;} voidsrl(ulong ir){	long v;	int rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("srl\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("srl\tr%d,r%d,r%d", rs1, rs2, rd);	}	reg.r[rd] = (ulong)reg.r[rs1] >> v;} voidsra(ulong ir){	long v;	int rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("sra\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("sra\tr%d,r%d,r%d", rs1, rs2, rd);	}	if(reg.r[rs1]&SIGNBIT)		reg.r[rd] = reg.r[rs1]>>v | ~((1<<(32-v))-1);	else		reg.r[rd] = reg.r[rs1]>>v;} voidsubcc(ulong ir){	long v;	int b31rs1, b31op2, b31res, r, rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("subcc\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("subcc\tr%d,r%d,r%d", rs1, rs2, rd);	}	r = reg.r[rs1] - v;	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);	if(r == 0)		reg.psr |= PSR_z;	if(r < 0)		reg.psr |= PSR_n; 	b31rs1 = reg.r[rs1]>>31;	b31op2 = v>>31;	b31res = r>>31; 	if((b31rs1 & ~b31op2 & ~b31res)|(~b31rs1 & b31op2 & b31res))		reg.psr |= PSR_v; 	if((~b31rs1 & b31op2)|(b31res & (~b31rs1|b31op2)))		reg.psr |= PSR_c; 	reg.r[rd] = r; } voidadd(ulong ir){	long v;	int rd, rs1, rs2; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("add\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("add\tr%d,r%d,r%d", rs1, rs2, rd);	}	reg.r[rd] = reg.r[rs1] + v;} voidaddcc(ulong ir){	long v, r;	int rd, rs1, rs2, b31rs1, b31op2, b31r; 	getrop23(ir);	if(ir&IMMBIT) {		ximm(v, ir);		if(trace)			itrace("addcc\tr%d,#0x%x,r%d", rs1, v, rd);	}	else {		v = reg.r[rs2];		if(trace)			itrace("addcc\tr%d,r%d,r%d", rs1, rs2, rd);	}	r = reg.r[rs1] + v;	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);	if(r == 0)		reg.psr |= PSR_z;	if(r < 0)		reg.psr |= PSR_n; 	b31rs1 = reg.r[rs1]>>31;	b31op2 = v>>31;	b31r = r>>31;	if((b31rs1 & b31op2 & ~b31r)|(~b31rs1 & ~b31op2 & b31r))		reg.psr |= PSR_v;	if((b31rs1 & b31op2) | (~b31r & (b31rs1 | b31op2)))		reg.psr |= PSR_c; 	reg.r[rd] = r;} 

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