#include <lib9.h>#include <kernel.h> /* * 68020-specific debugger interface */ static int m68020inst(ulong, char, char*, int);static int m68020das(ulong, char*, int);static int m68020instlen(ulong); #define werrstr print/* * 68020 exception frames */ #define BPTTRAP 4 /* breakpoint gives illegal inst */ static char * excep[] = { [2] "bus error", [3] "address error", [4] "illegal instruction", [5] "zero divide", [6] "CHK", [7] "TRAP", [8] "privilege violation", [9] "Trace", [10] "line 1010", [11] "line 1011", [13] "coprocessor protocol violation", [24] "spurious", [25] "incon", [26] "tac", [27] "auto 3", [28] "clock", [29] "auto 5", [30] "parity", [31] "mouse", [32] "system call", [33] "system call 1", [48] "FPCP branch", [49] "FPCP inexact", [50] "FPCP zero div", [51] "FPCP underflow", [52] "FPCP operand err", [53] "FPCP overflow", [54] "FPCP signal NAN",}; static int m68020vec;staticstruct ftype{ short fmt; short len; char *name;} ftype[] = { /* section 6.5.7 page 6-24 */ { 0, 4*2, "Short Format" }, { 1, 4*2, "Throwaway" }, { 2, 6*2, "Instruction Exception" }, { 3, 6*2, "MC68040 Floating Point Exception" }, { 8, 29*2, "MC68010 Bus Fault" }, { 7, 30*2, "MC68040 Bus Fault" }, { 9, 10*2, "Coprocessor mid-Instruction" }, { 10, 16*2, "MC68020 Short Bus Fault" }, { 11, 46*2, "MC68020 Long Bus Fault" }, { 0, 0, 0 }};static uchar *dasdata; static char *_hexify(char *buf, ulong p, int zeros){ ulong d; d = p/16; if(d) buf = _hexify(buf, d, zeros-1); else while(zeros--) *buf++ = '0'; *buf++ = "0123456789abcdef"[p&0x0f]; return buf;} /* 68020 Disassembler and related functions *//*not supported: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc, cpRESTORE, cpSAVE opcode: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0%y - register number x x x%f - trap vector x x x%e - destination eff addr x x x x x x%p - conditional predicate x x x x x x%s - size code x x%C - cache code x x%E - source eff addr. x x x x x x%d - direction bit x%c - condition code x x x x%x - register number x x x%b - shift count x x x%q - daffy 3-bit quick operand or shift count x x x%i - immediate operand <varies>%t - offset(PC) <varies> word 1: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0%a - register number x x x%w - bit field width x x x x x%L - MMU function code (SFC/DFC/D%a/#[0-3]) x x x x x%P - conditional predicate x x x x x x%k - k factor x x x x x x x%m - register mask x x x x x x x x%N - control register id x x x x x x x x x x x x%j - (Dq != Dr) ? Dq:Dr : Dr x x x x x x%K - dynamic k register x x x%h - register number x x x%I - MMU function code mask x x x x%o - bit field offset x x x x x%u - register number x x x%D - float dest reg x x x%F - (fdr==fsr) ? "F%D" :"F%B,F%D" x x x x x x%S - float source type x x x%B - float source register x x x%Z - ATC level number x x x%H - MMU register x x x x%r - register type/number x x x x word 2: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0%A - register number x x x%U - register number x x x%R - register type,number x x x x ----------------------------------------------------------------------------- %a - register [word 1: 0-2]%c - condition code [opcode: 8-11]%d - direction [opcode: 8]%e - destination effective address [opcode: 0-5]%f - trap vector [opcode: 0-3]%h - register [word 1: 5-7]%i - immediate operand (1, 2, or 4 bytes)%j - Dq:Dr if Dq != Dr; else Dr => Dr [word 1: 0-2] Dq [word 1: 12-14]%k - k factor [word 1: 0-6]%m - register mask [word 1: 0-7]%o - bit field offset [word 1: 6-10]%p - conditional predicate [opcode: 0-5]%q - daffy 3-bit quick operand [opcode: 9-11]%r - register type, [word 1: 15], register [word 1: 12-14]%s - size [opcode: 6-7]%t - offset beyond pc (text address) (2 or 4 bytes)%u - register [word 1: 6-8]%w - bit field width [word 1: 0-4]%x - register [opcode: 9-11]%y - register [opcode: 0-2]%A - register [word 2: 0-2]%B - float source register [word 1: 10-12]%C - cache identifier [opcode: 6-7] (IC, DC, or BC)%D - float dest reg [word 1: 7-9]%E - dest effective address [opcode: 6-11]%F - float dest reg == float src reg => "F%D"; else "F%B,F%D"%H - MMU reg [word 1: 10-13] (see above & p 4-53/54)%I - MMU function code mask [word 1: 5-8]%K - dynamic k factor register [word 1: 4-6]%L - MMU function code [word 1: 0-4] (SFC, DFC, D%a, or #[0-3])%N - control register [word 1: 0-11]%P - conditional predicate [word 1: 0-5]%R - register type, [word 2: 15], register [word 2: 12-14]%S - float source type code [word 1: 10-12]%U - register [word 2: 6-8]%Z - ATC level number [word 1: 10-12]%1 - Special case: EA as second operand*/ /* Operand classes */enum { EAPI = 1, /* extended address: pre decrement only */ EACA, /* extended address: control alterable */ EACAD, /* extended address: control alterable or Dreg */ EACAPI, /* extended address: control alterable or post-incr */ EACAPD, /* extended address: control alterable or pre-decr */ EAMA, /* extended address: memory alterable */ EADA, /* extended address: data alterable */ EAA, /* extended address: alterable */ EAC, /* extended address: control addressing */ EACPI, /* extended address: control addressing or post-incr */ EACD, /* extended address: control addressing or Dreg */ EAD, /* extended address: data addressing */ EAM, /* extended address: memory addressing */ EAM_B, /* EAM with byte immediate data */ EADI, /* extended address: data addressing or immediate */ EADI_L, /* EADI with long immediate data */ EADI_W, /* EADI with word immediate data */ EAALL, /* extended address: all modes */ EAALL_L, /* EAALL with long immediate data */ EAALL_W, /* EAALL with word immediate data */ EAALL_B, /* EAALL with byte immediate date */ /* special codes not directly used for validation */ EAFLT, /* extended address: EADI for B, W, L, or S; else EAM */ EADDA, /* destination extended address: EADA */ BREAC, /* EAC operand for JMP or CALL */ OP8, /* low 8 bits of op word */ I8, /* low 8-bits of first extension word */ I16, /* 16 bits in first extension word */ I32, /* 32 bits in first and second extension words */ IV, /* 8, 16 or 32 bit data in first & 2nd extension words */ C16, /* CAS2 16 bit immediate with bits 9-11 & 3-5 zero */ BR8, /* 8 bits in op word or 16 or 32 bits in extension words branch instruction format (p. 2-25) */ BR16, /* 16-bit branch displacement */ BR32, /* 32-bit branch displacement */ STACK, /* return PC on stack - follow set only */}; /* validation bit masks for various EA classes */enum { Dn = 0x0001, /* Data register */ An = 0x0002, /* Address register */ Ind = 0x0004, /* Address register indirect */ Pinc = 0x0008, /* Address register indirect post-increment */ Pdec = 0x0010, /* Address register indirect pre-decrement */ Bdisp = 0x0020, /* Base/Displacement in all its forms */ PCrel = 0x0040, /* PC relative addressing in all its forms */ Imm = 0x0080, /* Immediate data */ Abs = 0x0100, /* Absolute */}; /* EA validation table indexed by operand class number */ static short validea[] ={ 0, /* none */ Pdec, /* EAPI */ Abs|Bdisp|Ind, /* EACA */ Abs|Bdisp|Ind|Dn, /* EACAD */ Abs|Bdisp|Pinc|Ind, /* EACAPI */ Abs|Bdisp|Pdec|Ind, /* EACAPD */ Abs|Bdisp|Pdec|Pinc|Ind, /* EAMA */ Abs|Bdisp|Pdec|Pinc|Ind|Dn, /* EADA */ Abs|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAA */ Abs|PCrel|Bdisp|Ind, /* EAC */ Abs|PCrel|Bdisp|Pinc|Ind, /* EACPI */ Abs|PCrel|Bdisp|Ind|Dn, /* EACD */ Abs|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EAD */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM_B */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_L */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_W */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_L */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_W */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_B */}; /* EA types */enum{ Dreg, /* Dn */ Areg, /* An */ AInd, /* (An) */ APdec, /* -(An) */ APinc, /* (An)+ */ ADisp, /* Displacement beyond (An) */ BXD, /* Base, Index, Displacement */ PDisp, /* Displacement beyond PC */ PXD, /* PC, Index, Displacement */ ABS, /* absolute */ IMM, /* immediate */ IREAL, /* single precision real immediate */ IEXT, /* extended precision real immediate */ IPACK, /* packed real immediate */ IDBL, /* double precision real immediate */}; typedef struct optable Optable;typedef struct operand Operand;typedef struct inst Inst; struct optable{ ushort opcode; ushort mask0; ushort op2; ushort mask1; char opdata[2]; char *format;}; struct operand{ int eatype; short ext; union { long immediate; /* sign-extended integer byte/word/long */ struct { /* index mode displacements */ long disp; long outer; }; char floater[24]; /* floating point immediates */ };}; struct inst{ int n; /* # bytes in instruction */ ulong addr; /* addr of start of instruction */ ushort raw[4+12]; /* longest instruction: 24 byte packed immediate */ Operand and[2]; char *end; /* end of print buffer */ char *curr; /* current fill point in buffer */ char *errmsg;}; /* class 0: bit field, MOVEP & immediate instructions */static Optable t0[] = {{ 0x003c, 0xffff, 0x0000, 0xff00, {I8}, "ORB %i,CCR" },{ 0x007c, 0xffff, 0x0000, 0x0000, {I16}, "ORW %i,SR" },{ 0x023c, 0xffff, 0x0000, 0xff00, {I8}, "ANDB %i,CCR" },{ 0x027c, 0xffff, 0x0000, 0x0000, {I16}, "ANDW %i,SR" },{ 0x0a3c, 0xffff, 0x0000, 0xff00, {I8}, "EORB %i,CCR" },{ 0x0a7c, 0xffff, 0x0000, 0x0000, {I16}, "EORW %i,SR" },{ 0x0cfc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2W R%a:R%A,R%u:R%U,(%r):(%R)"} ,{ 0x0efc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2L R%a:R%A,R%u:R%U,(%r):(%R)"} , { 0x06c0, 0xfff8, 0x0000, 0x0000, {0}, "RTM R%y" },{ 0x06c8, 0xfff8, 0x0000, 0x0000, {0}, "RTM A%y" },{ 0x0800, 0xfff8, 0x0000, 0x0000, {I16}, "BTSTL %i,R%y" },{ 0x0840, 0xfff8, 0x0000, 0x0000, {I16}, "BCHGL %i,R%y" },{ 0x0880, 0xfff8, 0x0000, 0x0000, {I16}, "BCLRL %i,R%y" }, { 0x00c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2B %e,%r" },{ 0x00c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2B %e,%r" },{ 0x02c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2W %e,%r" },{ 0x02c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2W %e,%r" },{ 0x04c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2L %e,%r" },{ 0x04c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2L %e,%r" },{ 0x06c0, 0xffc0, 0x0000, 0x0000, {I16, BREAC}, "CALLM %i,%e" },{ 0x0800, 0xffc0, 0x0000, 0x0000, {I16, EAD}, "BTSTB %i,%e" },{ 0x0840, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCHG %i,%e" },{ 0x0880, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCLR %i,%e" },{ 0x08c0, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BSET %i,%e" },{ 0x0ac0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASB R%a,R%u,%e" },{ 0x0cc0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASW R%a,R%u,%e" },{ 0x0ec0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASL R%a,R%u,%e" }, { 0x0000, 0xff00, 0x0000, 0x0000, {IV, EADA}, "OR%s %i,%e" },{ 0x0200, 0xff00, 0x0000, 0x0000, {IV, EADA}, "AND%s %i,%e" },{ 0x0400, 0xff00, 0x0000, 0x0000, {IV, EADA}, "SUB%s %i,%e" },{ 0x0600, 0xff00, 0x0000, 0x0000, {IV, EADA}, "ADD%s %i,%e" },{ 0x0a00, 0xff00, 0x0000, 0x0000, {IV, EADA}, "EOR%s %i,%e" },{ 0x0c00, 0xff00, 0x0000, 0x0000, {IV, EAD}, "CMP%s %i,%e" },{ 0x0e00, 0xff00, 0x0000, 0x0800, {EAMA}, "MOVES%s %e,%r" },{ 0x0e00, 0xff00, 0x0800, 0x0800, {EAMA}, "MOVES%s %r,%e" }, { 0x0108, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW (%i,A%y),R%x" },{ 0x0148, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL (%i,A%y),R%x" },{ 0x0188, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW R%x,(%i,A%y)" },{ 0x01c8, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL R%x,(%i,A%y)" },{ 0x0100, 0xf1f8, 0x0000, 0x0000, {0}, "BTSTL R%x,R%y" },{ 0x0140, 0xf1f8, 0x0000, 0x0000, {0}, "BCHGL R%x,R%y" },{ 0x0180, 0xf1f8, 0x0000, 0x0000, {0}, "BCLRL R%x,R%y" },{ 0x01c0, 0xf1f8, 0x0000, 0x0000, {0}, "BSET R%x,R%y" }, { 0x0100, 0xf1c0, 0x0000, 0x0000, {EAM_B}, "BTSTB R%x,%e" },{ 0x0140, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCHG R%x,%e" },{ 0x0180, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCLR R%x,%e" },{ 0x01c0, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BSET R%x,%e" },{ 0,0,0,0,{0},0 },}; /* class 1: move byte */static Optable t1[] = {{ 0x1000, 0xf000, 0x0000, 0x0000, {EAALL_B,EADDA},"MOVB %e,%E" },{ 0,0,0,0,{0},0 },}; /* class 2: move long */static Optable t2[] = {{ 0x2040, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "MOVL %e,A%x" }, { 0x2000, 0xf000, 0x0000, 0x0000, {EAALL_L,EADDA},"MOVL %e,%E" },{ 0,0,0,0,{0},0 },}; /* class 3: move word */static Optable t3[] = {{ 0x3040, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "MOVW %e,A%x" }, { 0x3000, 0xf000, 0x0000, 0x0000, {EAALL_W,EADDA},"MOVW %e,%E" },{ 0,0,0,0,{0},0 },}; /* class 4: miscellaneous */static Optable t4[] = {{ 0x4e75, 0xffff, 0x0000, 0x0000, {STACK}, "RTS" },{ 0x4e77, 0xffff, 0x0000, 0x0000, {STACK}, "RTR" },{ 0x4afc, 0xffff, 0x0000, 0x0000, {0}, "ILLEGAL" },{ 0x4e71, 0xffff, 0x0000, 0x0000, {0}, "NOP" },{ 0x4e74, 0xffff, 0x0000, 0x0000, {I16, STACK}, "RTD %i" },{ 0x4e76, 0xffff, 0x0000, 0x0000, {0}, "TRAPV" },{ 0x4e70, 0xffff, 0x0000, 0x0000, {0}, "RESET" },{ 0x4e72, 0xffff, 0x0000, 0x0000, {I16}, "STOP %i" },{ 0x4e73, 0xffff, 0x0000, 0x0000, {0}, "RTE" },{ 0x4e7a, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %N,%r" },{ 0x4e7b, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %r,%N" }, { 0x4808, 0xfff8, 0x0000, 0x0000, {I32}, "LINKL A%y,%i" },{ 0x4840, 0xfff8, 0x0000, 0x0000, {0}, "SWAPW R%y" },{ 0x4848, 0xfff8, 0x0000, 0x0000, {0}, "BKPT #%y" },{ 0x4880, 0xfff8, 0x0000, 0x0000, {0}, "EXTW R%y" },{ 0x48C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTL R%y" },{ 0x49C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTBL R%y" },{ 0x4e50, 0xfff8, 0x0000, 0x0000, {I16}, "LINKW A%y,%i" },{ 0x4e58, 0xfff8, 0x0000, 0x0000, {0}, "UNLK A%y" },{ 0x4e60, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL (A%y),USP" },{ 0x4e68, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL USP,(A%y)" }, { 0x4e40, 0xfff0, 0x0000, 0x0000, {0}, "SYS %f" }, { 0x40c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW SR,%e" },{ 0x42c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW CCR,%e" },{ 0x44c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,CCR" },{ 0x46c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,SR" },{ 0x4800, 0xffc0, 0x0000, 0x0000, {EADA}, "NBCDB %e" },{ 0x4840, 0xffc0, 0x0000, 0x0000, {EAC}, "PEA %e" },{ 0x4880, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEMW %i,%e" },{ 0x48c0, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEML %i,%e" },{ 0x4ac0, 0xffc0, 0x0000, 0x0000, {EADA}, "TAS %e" },{ 0x4a00, 0xffc0, 0x0000, 0x0000, {EAD}, "TSTB %e" },{ 0x4c00, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "MULUL %e,%r" },{ 0x4c00, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "MULUL %e,R%a:%r" },{ 0x4c00, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "MULSL %e,%r" },{ 0x4c00, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "MULSL %e,R%a:%r" },{ 0x4c40, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "DIVUL %e,%j" },{ 0x4c40, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "DIVUD %e,%r:R%a" },{ 0x4c40, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "DIVSL %e,%j" },{ 0x4c40, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "DIVSD %e,%r:R%a" },{ 0x4c80, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEMW %1,%i" },{ 0x4cc0, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEML %1,%i" },{ 0x4e80, 0xffc0, 0x0000, 0x0000, {BREAC}, "JSR %e" },{ 0x4ec0, 0xffc0, 0x0000, 0x0000, {BREAC}, "JMP %e" }, { 0x4000, 0xff00, 0x0000, 0x0000, {EADA}, "NEGX%s %e" },{ 0x4200, 0xff00, 0x0000, 0x0000, {EADA}, "CLR%s %e" },{ 0x4400, 0xff00, 0x0000, 0x0000, {EADA}, "NEG%s %e" },{ 0x4600, 0xff00, 0x0000, 0x0000, {EADA}, "NOT%s %e" },{ 0x4a00, 0xff00, 0x0000, 0x0000, {EAALL}, "TST%s %e" }, { 0x4180, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "CHKW %e,R%x" },{ 0x41c0, 0xf1c0, 0x0000, 0x0000, {EAC}, "LEA %e,A%x" },{ 0x4100, 0xf1c0, 0x0000, 0x0000, {EADI_L}, "CHKL %e,R%x" },{ 0,0,0,0,{0},0 },}; /* class 5: miscellaneous quick, branch & trap instructions */static Optable t5[] = {{ 0x5000, 0xf1c0, 0x0000, 0x0000, {EADA}, "ADDB $Q#%q,%e" },{ 0x5100, 0xf1c0, 0x0000, 0x0000, {EADA}, "SUBB $Q#%q,%e" }, { 0x50c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" },{ 0x51c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" }, { 0x5000, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDB $Q#%q,%e" },{ 0x5040, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDW $Q#%q,%e" },{ 0x5080, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDL $Q#%q,%e" },{ 0x5100, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBB $Q#%q,%e" },{ 0x5140, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBW $Q#%q,%e" },{ 0x5180, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBL $Q#%q,%e" }, { 0x50fa, 0xf0ff, 0x0000, 0x0000, {I16}, "TRAP%cW %i" },{ 0x50fb, 0xf0ff, 0x0000, 0x0000, {I32}, "TRAP%cL %i" },{ 0x50fc, 0xf0ff, 0x0000, 0x0000, {0}, "TRAP%c" }, { 0x50c0, 0xf0c0, 0x0000, 0x0000, {EADA}, "S%c %e" },{ 0,0,0,0,{0},0 },}; /* class 6: branch instructions */static Optable t6[] = {{ 0x6000, 0xff00, 0x0000, 0x0000, {BR8}, "BRA %t" },{ 0x6100, 0xff00, 0x0000, 0x0000, {BR8}, "BSR %t" },{ 0x6000, 0xf000, 0x0000, 0x0000, {BR8}, "B%c %t" },{ 0,0,0,0,{0},0 },}; /* class 7: move quick */static Optable t7[] = {{ 0x7000, 0xf100, 0x0000, 0x0000, {OP8}, "MOVL $Q%i,R%x" },{ 0,0,0,0,{0},0 },}; /* class 8: BCD operations, DIV, and OR instructions */static Optable t8[] = {{ 0x8100, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB R%y,R%x" },{ 0x8108, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB -(A%y),-(A%x)" },{ 0x8140, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK R%y,R%x,%i" },{ 0x8148, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK -(A%y),-(A%x),%i" },{ 0x8180, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK R%y,R%x,%i" },{ 0x8188, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK -(A%y),-(A%x),%i" }, { 0x80c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVUW %e,R%x" },{ 0x81c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVSW %e,R%x" }, { 0x8000, 0xf100, 0x0000, 0x0000, {EADI}, "OR%s %e,R%x" },{ 0x8100, 0xf100, 0x0000, 0x0000, {EAMA}, "OR%s R%x,%e" },{ 0,0,0,0,{0},0 },}; /* class 9: subtract instruction */static Optable t9[] = {{ 0x90c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "SUBW %e,A%x" },{ 0x91c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "SUBL %e,A%x" },Lines 1–500 of 1940. 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#include <lib9.h> #include <kernel.h> /* * 68020-specific debugger interface */ static int m68020inst(ulong, char, char*, int); static int m68020das(ulong, char*, int); static int m68020instlen(ulong); #define werrstr print /* * 68020 exception frames */ #define BPTTRAP 4 /* breakpoint gives illegal inst */ static char * excep[] = { [2] "bus error", [3] "address error", [4] "illegal instruction", [5] "zero divide", [6] "CHK", [7] "TRAP", [8] "privilege violation", [9] "Trace", [10] "line 1010", [11] "line 1011", [13] "coprocessor protocol violation", [24] "spurious", [25] "incon", [26] "tac", [27] "auto 3", [28] "clock", [29] "auto 5", [30] "parity", [31] "mouse", [32] "system call", [33] "system call 1", [48] "FPCP branch", [49] "FPCP inexact", [50] "FPCP zero div", [51] "FPCP underflow", [52] "FPCP operand err", [53] "FPCP overflow", [54] "FPCP signal NAN", }; static int m68020vec; static struct ftype{ short fmt; short len; char *name; } ftype[] = { /* section 6.5.7 page 6-24 */ { 0, 4*2, "Short Format" }, { 1, 4*2, "Throwaway" }, { 2, 6*2, "Instruction Exception" }, { 3, 6*2, "MC68040 Floating Point Exception" }, { 8, 29*2, "MC68010 Bus Fault" }, { 7, 30*2, "MC68040 Bus Fault" }, { 9, 10*2, "Coprocessor mid-Instruction" }, { 10, 16*2, "MC68020 Short Bus Fault" }, { 11, 46*2, "MC68020 Long Bus Fault" }, { 0, 0, 0 } }; static uchar *dasdata; static char * _hexify(char *buf, ulong p, int zeros) { ulong d; d = p/16; if(d) buf = _hexify(buf, d, zeros-1); else while(zeros--) *buf++ = '0'; *buf++ = "0123456789abcdef"[p&0x0f]; return buf; } /* 68020 Disassembler and related functions */ /* not supported: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc, cpRESTORE, cpSAVE opcode: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 %y - register number x x x %f - trap vector x x x %e - destination eff addr x x x x x x %p - conditional predicate x x x x x x %s - size code x x %C - cache code x x %E - source eff addr. x x x x x x %d - direction bit x %c - condition code x x x x %x - register number x x x %b - shift count x x x %q - daffy 3-bit quick operand or shift count x x x %i - immediate operand <varies> %t - offset(PC) <varies> word 1: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 %a - register number x x x %w - bit field width x x x x x %L - MMU function code (SFC/DFC/D%a/#[0-3]) x x x x x %P - conditional predicate x x x x x x %k - k factor x x x x x x x %m - register mask x x x x x x x x %N - control register id x x x x x x x x x x x x %j - (Dq != Dr) ? Dq:Dr : Dr x x x x x x %K - dynamic k register x x x %h - register number x x x %I - MMU function code mask x x x x %o - bit field offset x x x x x %u - register number x x x %D - float dest reg x x x %F - (fdr==fsr) ? "F%D" :"F%B,F%D" x x x x x x %S - float source type x x x %B - float source register x x x %Z - ATC level number x x x %H - MMU register x x x x %r - register type/number x x x x word 2: 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 %A - register number x x x %U - register number x x x %R - register type,number x x x x ----------------------------------------------------------------------------- %a - register [word 1: 0-2] %c - condition code [opcode: 8-11] %d - direction [opcode: 8] %e - destination effective address [opcode: 0-5] %f - trap vector [opcode: 0-3] %h - register [word 1: 5-7] %i - immediate operand (1, 2, or 4 bytes) %j - Dq:Dr if Dq != Dr; else Dr => Dr [word 1: 0-2] Dq [word 1: 12-14] %k - k factor [word 1: 0-6] %m - register mask [word 1: 0-7] %o - bit field offset [word 1: 6-10] %p - conditional predicate [opcode: 0-5] %q - daffy 3-bit quick operand [opcode: 9-11] %r - register type, [word 1: 15], register [word 1: 12-14] %s - size [opcode: 6-7] %t - offset beyond pc (text address) (2 or 4 bytes) %u - register [word 1: 6-8] %w - bit field width [word 1: 0-4] %x - register [opcode: 9-11] %y - register [opcode: 0-2] %A - register [word 2: 0-2] %B - float source register [word 1: 10-12] %C - cache identifier [opcode: 6-7] (IC, DC, or BC) %D - float dest reg [word 1: 7-9] %E - dest effective address [opcode: 6-11] %F - float dest reg == float src reg => "F%D"; else "F%B,F%D" %H - MMU reg [word 1: 10-13] (see above & p 4-53/54) %I - MMU function code mask [word 1: 5-8] %K - dynamic k factor register [word 1: 4-6] %L - MMU function code [word 1: 0-4] (SFC, DFC, D%a, or #[0-3]) %N - control register [word 1: 0-11] %P - conditional predicate [word 1: 0-5] %R - register type, [word 2: 15], register [word 2: 12-14] %S - float source type code [word 1: 10-12] %U - register [word 2: 6-8] %Z - ATC level number [word 1: 10-12] %1 - Special case: EA as second operand */ /* Operand classes */ enum { EAPI = 1, /* extended address: pre decrement only */ EACA, /* extended address: control alterable */ EACAD, /* extended address: control alterable or Dreg */ EACAPI, /* extended address: control alterable or post-incr */ EACAPD, /* extended address: control alterable or pre-decr */ EAMA, /* extended address: memory alterable */ EADA, /* extended address: data alterable */ EAA, /* extended address: alterable */ EAC, /* extended address: control addressing */ EACPI, /* extended address: control addressing or post-incr */ EACD, /* extended address: control addressing or Dreg */ EAD, /* extended address: data addressing */ EAM, /* extended address: memory addressing */ EAM_B, /* EAM with byte immediate data */ EADI, /* extended address: data addressing or immediate */ EADI_L, /* EADI with long immediate data */ EADI_W, /* EADI with word immediate data */ EAALL, /* extended address: all modes */ EAALL_L, /* EAALL with long immediate data */ EAALL_W, /* EAALL with word immediate data */ EAALL_B, /* EAALL with byte immediate date */ /* special codes not directly used for validation */ EAFLT, /* extended address: EADI for B, W, L, or S; else EAM */ EADDA, /* destination extended address: EADA */ BREAC, /* EAC operand for JMP or CALL */ OP8, /* low 8 bits of op word */ I8, /* low 8-bits of first extension word */ I16, /* 16 bits in first extension word */ I32, /* 32 bits in first and second extension words */ IV, /* 8, 16 or 32 bit data in first & 2nd extension words */ C16, /* CAS2 16 bit immediate with bits 9-11 & 3-5 zero */ BR8, /* 8 bits in op word or 16 or 32 bits in extension words branch instruction format (p. 2-25) */ BR16, /* 16-bit branch displacement */ BR32, /* 32-bit branch displacement */ STACK, /* return PC on stack - follow set only */ }; /* validation bit masks for various EA classes */ enum { Dn = 0x0001, /* Data register */ An = 0x0002, /* Address register */ Ind = 0x0004, /* Address register indirect */ Pinc = 0x0008, /* Address register indirect post-increment */ Pdec = 0x0010, /* Address register indirect pre-decrement */ Bdisp = 0x0020, /* Base/Displacement in all its forms */ PCrel = 0x0040, /* PC relative addressing in all its forms */ Imm = 0x0080, /* Immediate data */ Abs = 0x0100, /* Absolute */ }; /* EA validation table indexed by operand class number */ static short validea[] = { 0, /* none */ Pdec, /* EAPI */ Abs|Bdisp|Ind, /* EACA */ Abs|Bdisp|Ind|Dn, /* EACAD */ Abs|Bdisp|Pinc|Ind, /* EACAPI */ Abs|Bdisp|Pdec|Ind, /* EACAPD */ Abs|Bdisp|Pdec|Pinc|Ind, /* EAMA */ Abs|Bdisp|Pdec|Pinc|Ind|Dn, /* EADA */ Abs|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAA */ Abs|PCrel|Bdisp|Ind, /* EAC */ Abs|PCrel|Bdisp|Pinc|Ind, /* EACPI */ Abs|PCrel|Bdisp|Ind|Dn, /* EACD */ Abs|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EAD */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM_B */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_L */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_W */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_L */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_W */ Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_B */ }; /* EA types */ enum { Dreg, /* Dn */ Areg, /* An */ AInd, /* (An) */ APdec, /* -(An) */ APinc, /* (An)+ */ ADisp, /* Displacement beyond (An) */ BXD, /* Base, Index, Displacement */ PDisp, /* Displacement beyond PC */ PXD, /* PC, Index, Displacement */ ABS, /* absolute */ IMM, /* immediate */ IREAL, /* single precision real immediate */ IEXT, /* extended precision real immediate */ IPACK, /* packed real immediate */ IDBL, /* double precision real immediate */ }; typedef struct optable Optable; typedef struct operand Operand; typedef struct inst Inst; struct optable { ushort opcode; ushort mask0; ushort op2; ushort mask1; char opdata[2]; char *format; }; struct operand { int eatype; short ext; union { long immediate; /* sign-extended integer byte/word/long */ struct { /* index mode displacements */ long disp; long outer; }; char floater[24]; /* floating point immediates */ }; }; struct inst { int n; /* # bytes in instruction */ ulong addr; /* addr of start of instruction */ ushort raw[4+12]; /* longest instruction: 24 byte packed immediate */ Operand and[2]; char *end; /* end of print buffer */ char *curr; /* current fill point in buffer */ char *errmsg; }; /* class 0: bit field, MOVEP & immediate instructions */ static Optable t0[] = { { 0x003c, 0xffff, 0x0000, 0xff00, {I8}, "ORB %i,CCR" }, { 0x007c, 0xffff, 0x0000, 0x0000, {I16}, "ORW %i,SR" }, { 0x023c, 0xffff, 0x0000, 0xff00, {I8}, "ANDB %i,CCR" }, { 0x027c, 0xffff, 0x0000, 0x0000, {I16}, "ANDW %i,SR" }, { 0x0a3c, 0xffff, 0x0000, 0xff00, {I8}, "EORB %i,CCR" }, { 0x0a7c, 0xffff, 0x0000, 0x0000, {I16}, "EORW %i,SR" }, { 0x0cfc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2W R%a:R%A,R%u:R%U,(%r):(%R)"} , { 0x0efc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2L R%a:R%A,R%u:R%U,(%r):(%R)"} , { 0x06c0, 0xfff8, 0x0000, 0x0000, {0}, "RTM R%y" }, { 0x06c8, 0xfff8, 0x0000, 0x0000, {0}, "RTM A%y" }, { 0x0800, 0xfff8, 0x0000, 0x0000, {I16}, "BTSTL %i,R%y" }, { 0x0840, 0xfff8, 0x0000, 0x0000, {I16}, "BCHGL %i,R%y" }, { 0x0880, 0xfff8, 0x0000, 0x0000, {I16}, "BCLRL %i,R%y" }, { 0x00c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2B %e,%r" }, { 0x00c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2B %e,%r" }, { 0x02c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2W %e,%r" }, { 0x02c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2W %e,%r" }, { 0x04c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2L %e,%r" }, { 0x04c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2L %e,%r" }, { 0x06c0, 0xffc0, 0x0000, 0x0000, {I16, BREAC}, "CALLM %i,%e" }, { 0x0800, 0xffc0, 0x0000, 0x0000, {I16, EAD}, "BTSTB %i,%e" }, { 0x0840, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCHG %i,%e" }, { 0x0880, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCLR %i,%e" }, { 0x08c0, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BSET %i,%e" }, { 0x0ac0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASB R%a,R%u,%e" }, { 0x0cc0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASW R%a,R%u,%e" }, { 0x0ec0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASL R%a,R%u,%e" }, { 0x0000, 0xff00, 0x0000, 0x0000, {IV, EADA}, "OR%s %i,%e" }, { 0x0200, 0xff00, 0x0000, 0x0000, {IV, EADA}, "AND%s %i,%e" }, { 0x0400, 0xff00, 0x0000, 0x0000, {IV, EADA}, "SUB%s %i,%e" }, { 0x0600, 0xff00, 0x0000, 0x0000, {IV, EADA}, "ADD%s %i,%e" }, { 0x0a00, 0xff00, 0x0000, 0x0000, {IV, EADA}, "EOR%s %i,%e" }, { 0x0c00, 0xff00, 0x0000, 0x0000, {IV, EAD}, "CMP%s %i,%e" }, { 0x0e00, 0xff00, 0x0000, 0x0800, {EAMA}, "MOVES%s %e,%r" }, { 0x0e00, 0xff00, 0x0800, 0x0800, {EAMA}, "MOVES%s %r,%e" }, { 0x0108, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW (%i,A%y),R%x" }, { 0x0148, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL (%i,A%y),R%x" }, { 0x0188, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW R%x,(%i,A%y)" }, { 0x01c8, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL R%x,(%i,A%y)" }, { 0x0100, 0xf1f8, 0x0000, 0x0000, {0}, "BTSTL R%x,R%y" }, { 0x0140, 0xf1f8, 0x0000, 0x0000, {0}, "BCHGL R%x,R%y" }, { 0x0180, 0xf1f8, 0x0000, 0x0000, {0}, "BCLRL R%x,R%y" }, { 0x01c0, 0xf1f8, 0x0000, 0x0000, {0}, "BSET R%x,R%y" }, { 0x0100, 0xf1c0, 0x0000, 0x0000, {EAM_B}, "BTSTB R%x,%e" }, { 0x0140, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCHG R%x,%e" }, { 0x0180, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCLR R%x,%e" }, { 0x01c0, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BSET R%x,%e" }, { 0,0,0,0,{0},0 }, }; /* class 1: move byte */ static Optable t1[] = { { 0x1000, 0xf000, 0x0000, 0x0000, {EAALL_B,EADDA},"MOVB %e,%E" }, { 0,0,0,0,{0},0 }, }; /* class 2: move long */ static Optable t2[] = { { 0x2040, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "MOVL %e,A%x" }, { 0x2000, 0xf000, 0x0000, 0x0000, {EAALL_L,EADDA},"MOVL %e,%E" }, { 0,0,0,0,{0},0 }, }; /* class 3: move word */ static Optable t3[] = { { 0x3040, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "MOVW %e,A%x" }, { 0x3000, 0xf000, 0x0000, 0x0000, {EAALL_W,EADDA},"MOVW %e,%E" }, { 0,0,0,0,{0},0 }, }; /* class 4: miscellaneous */ static Optable t4[] = { { 0x4e75, 0xffff, 0x0000, 0x0000, {STACK}, "RTS" }, { 0x4e77, 0xffff, 0x0000, 0x0000, {STACK}, "RTR" }, { 0x4afc, 0xffff, 0x0000, 0x0000, {0}, "ILLEGAL" }, { 0x4e71, 0xffff, 0x0000, 0x0000, {0}, "NOP" }, { 0x4e74, 0xffff, 0x0000, 0x0000, {I16, STACK}, "RTD %i" }, { 0x4e76, 0xffff, 0x0000, 0x0000, {0}, "TRAPV" }, { 0x4e70, 0xffff, 0x0000, 0x0000, {0}, "RESET" }, { 0x4e72, 0xffff, 0x0000, 0x0000, {I16}, "STOP %i" }, { 0x4e73, 0xffff, 0x0000, 0x0000, {0}, "RTE" }, { 0x4e7a, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %N,%r" }, { 0x4e7b, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %r,%N" }, { 0x4808, 0xfff8, 0x0000, 0x0000, {I32}, "LINKL A%y,%i" }, { 0x4840, 0xfff8, 0x0000, 0x0000, {0}, "SWAPW R%y" }, { 0x4848, 0xfff8, 0x0000, 0x0000, {0}, "BKPT #%y" }, { 0x4880, 0xfff8, 0x0000, 0x0000, {0}, "EXTW R%y" }, { 0x48C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTL R%y" }, { 0x49C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTBL R%y" }, { 0x4e50, 0xfff8, 0x0000, 0x0000, {I16}, "LINKW A%y,%i" }, { 0x4e58, 0xfff8, 0x0000, 0x0000, {0}, "UNLK A%y" }, { 0x4e60, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL (A%y),USP" }, { 0x4e68, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL USP,(A%y)" }, { 0x4e40, 0xfff0, 0x0000, 0x0000, {0}, "SYS %f" }, { 0x40c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW SR,%e" }, { 0x42c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW CCR,%e" }, { 0x44c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,CCR" }, { 0x46c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,SR" }, { 0x4800, 0xffc0, 0x0000, 0x0000, {EADA}, "NBCDB %e" }, { 0x4840, 0xffc0, 0x0000, 0x0000, {EAC}, "PEA %e" }, { 0x4880, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEMW %i,%e" }, { 0x48c0, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEML %i,%e" }, { 0x4ac0, 0xffc0, 0x0000, 0x0000, {EADA}, "TAS %e" }, { 0x4a00, 0xffc0, 0x0000, 0x0000, {EAD}, "TSTB %e" }, { 0x4c00, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "MULUL %e,%r" }, { 0x4c00, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "MULUL %e,R%a:%r" }, { 0x4c00, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "MULSL %e,%r" }, { 0x4c00, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "MULSL %e,R%a:%r" }, { 0x4c40, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "DIVUL %e,%j" }, { 0x4c40, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "DIVUD %e,%r:R%a" }, { 0x4c40, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "DIVSL %e,%j" }, { 0x4c40, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "DIVSD %e,%r:R%a" }, { 0x4c80, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEMW %1,%i" }, { 0x4cc0, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEML %1,%i" }, { 0x4e80, 0xffc0, 0x0000, 0x0000, {BREAC}, "JSR %e" }, { 0x4ec0, 0xffc0, 0x0000, 0x0000, {BREAC}, "JMP %e" }, { 0x4000, 0xff00, 0x0000, 0x0000, {EADA}, "NEGX%s %e" }, { 0x4200, 0xff00, 0x0000, 0x0000, {EADA}, "CLR%s %e" }, { 0x4400, 0xff00, 0x0000, 0x0000, {EADA}, "NEG%s %e" }, { 0x4600, 0xff00, 0x0000, 0x0000, {EADA}, "NOT%s %e" }, { 0x4a00, 0xff00, 0x0000, 0x0000, {EAALL}, "TST%s %e" }, { 0x4180, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "CHKW %e,R%x" }, { 0x41c0, 0xf1c0, 0x0000, 0x0000, {EAC}, "LEA %e,A%x" }, { 0x4100, 0xf1c0, 0x0000, 0x0000, {EADI_L}, "CHKL %e,R%x" }, { 0,0,0,0,{0},0 }, }; /* class 5: miscellaneous quick, branch & trap instructions */ static Optable t5[] = { { 0x5000, 0xf1c0, 0x0000, 0x0000, {EADA}, "ADDB $Q#%q,%e" }, { 0x5100, 0xf1c0, 0x0000, 0x0000, {EADA}, "SUBB $Q#%q,%e" }, { 0x50c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" }, { 0x51c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" }, { 0x5000, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDB $Q#%q,%e" }, { 0x5040, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDW $Q#%q,%e" }, { 0x5080, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDL $Q#%q,%e" }, { 0x5100, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBB $Q#%q,%e" }, { 0x5140, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBW $Q#%q,%e" }, { 0x5180, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBL $Q#%q,%e" }, { 0x50fa, 0xf0ff, 0x0000, 0x0000, {I16}, "TRAP%cW %i" }, { 0x50fb, 0xf0ff, 0x0000, 0x0000, {I32}, "TRAP%cL %i" }, { 0x50fc, 0xf0ff, 0x0000, 0x0000, {0}, "TRAP%c" }, { 0x50c0, 0xf0c0, 0x0000, 0x0000, {EADA}, "S%c %e" }, { 0,0,0,0,{0},0 }, }; /* class 6: branch instructions */ static Optable t6[] = { { 0x6000, 0xff00, 0x0000, 0x0000, {BR8}, "BRA %t" }, { 0x6100, 0xff00, 0x0000, 0x0000, {BR8}, "BSR %t" }, { 0x6000, 0xf000, 0x0000, 0x0000, {BR8}, "B%c %t" }, { 0,0,0,0,{0},0 }, }; /* class 7: move quick */ static Optable t7[] = { { 0x7000, 0xf100, 0x0000, 0x0000, {OP8}, "MOVL $Q%i,R%x" }, { 0,0,0,0,{0},0 }, }; /* class 8: BCD operations, DIV, and OR instructions */ static Optable t8[] = { { 0x8100, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB R%y,R%x" }, { 0x8108, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB -(A%y),-(A%x)" }, { 0x8140, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK R%y,R%x,%i" }, { 0x8148, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK -(A%y),-(A%x),%i" }, { 0x8180, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK R%y,R%x,%i" }, { 0x8188, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK -(A%y),-(A%x),%i" }, { 0x80c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVUW %e,R%x" }, { 0x81c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVSW %e,R%x" }, { 0x8000, 0xf100, 0x0000, 0x0000, {EADI}, "OR%s %e,R%x" }, { 0x8100, 0xf100, 0x0000, 0x0000, {EAMA}, "OR%s R%x,%e" }, { 0,0,0,0,{0},0 }, }; /* class 9: subtract instruction */ static Optable t9[] = { { 0x90c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "SUBW %e,A%x" }, { 0x91c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "SUBL %e,A%x" },