%{#include "a.h"%}%union{	Sym	*sym;	long	lval;	double	dval;	char	sval[8];	Gen	gen;}%left	'|'%left	'^'%left	'&'%left	'<' '>'%left	'+' '-'%left	'*' '/' '%'%token	<lval>	LMOVW LMOVB LABS LLOGW LSHW LADDW LCMP LCROP%token	<lval>	LBRA LFMOV LFCONV LFCMP LFADD LFMA LTRAP LXORW%token	<lval>	LNOP LEND LRETT LWORD LTEXT LDATA LRETRN%token	<lval>	LCONST LSP LSB LFP LPC LCREG LFLUSH%token	<lval>	LREG LFREG LR LCR LF LFPSCR%token	<lval>	LLR LCTR LSPR LSPREG LSEG LMSR%token	<lval>	LSCHED LXLD LXST LXOP LXMV%token	<lval>	LRLWM LMOVMW LMOVEM LMOVFL LMTFSB LMA%token	<dval>	LFCONST%token	<sval>	LSCONST%token	<sym>	LNAME LLAB LVAR%type	<lval>	con expr pointer offset sreg%type	<gen>	addr rreg regaddr name creg freg xlreg lr ctr%type	<gen>	imm ximm fimm rel psr lcr cbit fpscr fpscrf seg msr mask%%prog:|	prog line line:	LLAB ':'	{		if($1->value != pc)			yyerror("redeclaration of %s", $1->name);		$1->value = pc;	}	line|	LNAME ':'	{		$1->type = LLAB;		$1->value = pc;	}	line|	LNAME '=' expr ';'	{		$1->type = LVAR;		$1->value = $3;	}|	LVAR '=' expr ';'	{		if($1->value != $3)			yyerror("redeclaration of %s", $1->name);		$1->value = $3;	}|	LSCHED ';'	{		nosched = $1;	}|	';'|	inst ';'|	error ';' inst:/* * load ints and bytes */	LMOVW rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW addr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW regaddr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVB rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVB addr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVB regaddr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}/* * load floats */|	LFMOV addr ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFMOV regaddr ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFMOV fimm ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFMOV freg ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFMOV freg ',' addr	{		outcode($1, &$2, NREG, &$4);	}|	LFMOV freg ',' regaddr	{		outcode($1, &$2, NREG, &$4);	}/* * store ints and bytes */|	LMOVW rreg ',' addr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW rreg ',' regaddr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVB rreg ',' addr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVB rreg ',' regaddr	{		outcode($1, &$2, NREG, &$4);	}/* * store floats */|	LMOVW freg ',' addr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW freg ',' regaddr	{		outcode($1, &$2, NREG, &$4);	}/* * floating point status */|	LMOVW fpscr ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW freg ','  fpscr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW freg ',' imm ',' fpscr	{		outgcode($1, &$2, NREG, &$4, &$6);	}|	LMOVW fpscr ',' creg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW imm ',' fpscrf	{		outcode($1, &$2, NREG, &$4);	}|	LMTFSB imm ',' con	{		outcode($1, &$2, $4, &nullgen);	}/* * field moves (mtcrf) */|	LMOVW rreg ',' imm ',' lcr	{		outgcode($1, &$2, NREG, &$4, &$6);	}|	LMOVW rreg ',' creg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW rreg ',' lcr	{		outcode($1, &$2, NREG, &$4);	}/* * integer operations * logical instructions * shift instructions * unary instructions */|	LADDW rreg ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}|	LADDW imm ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}|	LADDW rreg ',' imm ',' rreg	{		outgcode($1, &$2, NREG, &$4, &$6);	}|	LADDW rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LADDW imm ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LLOGW rreg ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}|	LLOGW rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LSHW rreg ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}|	LSHW rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LSHW imm ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}|	LSHW imm ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LABS rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LABS rreg	{		outcode($1, &$2, NREG, &$2);	}/* * multiply-accumulate */|	LMA rreg ',' sreg ',' rreg	{		outcode($1, &$2, $4, &$6);	}/* * move immediate: macro for cau+or, addi, addis, and other combinations */|	LMOVW imm ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW ximm ',' rreg	{		outcode($1, &$2, NREG, &$4);	}/* * condition register operations */|	LCROP cbit ',' cbit	{		outcode($1, &$2, $4.reg, &$4);	}|	LCROP cbit ',' con ',' cbit	{		outcode($1, &$2, $4, &$6);	}/* * condition register moves * move from machine state register */|	LMOVW creg ',' creg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW psr ',' creg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW lcr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW psr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW seg ',' rreg	{		int r;		r = $2.offset;		$2.offset = 0;		outcode($1, &$2, r, &$4);	}|	LMOVW rreg ',' seg	{		int r;		r = $4.offset;		$4.offset = 0;		outcode($1, &$2, r, &$4);	}|	LMOVW xlreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW rreg ',' xlreg	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW creg ',' psr	{		outcode($1, &$2, NREG, &$4);	}|	LMOVW rreg ',' psr	{		outcode($1, &$2, NREG, &$4);	}/* * branch, branch conditional * branch conditional register * branch conditional to count register */|	LBRA rel	{		outcode($1, &nullgen, NREG, &$2);	}|	LBRA addr	{		outcode($1, &nullgen, NREG, &$2);	}|	LBRA '(' xlreg ')'	{		outcode($1, &nullgen, NREG, &$3);	}|	LBRA ',' rel	{		outcode($1, &nullgen, NREG, &$3);	}|	LBRA ',' addr	{		outcode($1, &nullgen, NREG, &$3);	}|	LBRA ',' '(' xlreg ')'	{		outcode($1, &nullgen, NREG, &$4);	}|	LBRA creg ',' rel	{		outcode($1, &$2, NREG, &$4);	}|	LBRA creg ',' addr	{		outcode($1, &$2, NREG, &$4);	}|	LBRA creg ',' '(' xlreg ')'	{		outcode($1, &$2, NREG, &$5);	}|	LBRA con ',' rel	{		outcode($1, &nullgen, $2, &$4);	}|	LBRA con ',' addr	{		outcode($1, &nullgen, $2, &$4);	}|	LBRA con ',' '(' xlreg ')'	{		outcode($1, &nullgen, $2, &$5);	}|	LBRA con ',' con ',' rel	{		Gen g;		g = nullgen;		g.type = D_CONST;		g.offset = $2;		outcode($1, &g, $4, &$6);	}|	LBRA con ',' con ',' addr	{		Gen g;		g = nullgen;		g.type = D_CONST;		g.offset = $2;		outcode($1, &g, $4, &$6);	}|	LBRA con ',' con ',' '(' xlreg ')'	{		Gen g;		g = nullgen;		g.type = D_CONST;		g.offset = $2;		outcode($1, &g, $4, &$7);	}/* * conditional trap */|	LTRAP rreg ',' sreg	{		outcode($1, &$2, $4, &nullgen);	}|	LTRAP imm ',' sreg	{		outcode($1, &$2, $4, &nullgen);	}|	LTRAP rreg comma	{		outcode($1, &$2, NREG, &nullgen);	}|	LTRAP comma	{		outcode($1, &nullgen, NREG, &nullgen);	}/* * floating point operate */|	LFCONV freg ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFADD freg ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFADD freg ',' freg ',' freg	{		outcode($1, &$2, $4.reg, &$6);	}|	LFMA freg ',' freg ',' freg ',' freg	{		outgcode($1, &$2, $4.reg, &$6, &$8);	}|	LFCMP freg ',' freg	{		outcode($1, &$2, NREG, &$4);	}|	LFCMP freg ',' freg ',' creg	{		outcode($1, &$2, $6.reg, &$4);	}/* * CMP */|	LCMP rreg ',' rreg	{		outcode($1, &$2, NREG, &$4);	}|	LCMP rreg ',' imm	{		outcode($1, &$2, NREG, &$4);	}|	LCMP rreg ',' rreg ',' creg	{		outcode($1, &$2, $6.reg, &$4);	}|	LCMP rreg ',' imm ',' creg	{		outcode($1, &$2, $6.reg, &$4);	}/* * rotate and mask */|	LRLWM  imm ',' rreg ',' imm ',' rreg	{		outgcode($1, &$2, $4.reg, &$6, &$8);	}|	LRLWM  imm ',' rreg ',' mask ',' rreg	{		outgcode($1, &$2, $4.reg, &$6, &$8);	}|	LRLWM  rreg ',' rreg ',' imm ',' rreg	{		outgcode($1, &$2, $4.reg, &$6, &$8);	}|	LRLWM  rreg ',' rreg ',' mask ',' rreg	{		outgcode($1, &$2, $4.reg, &$6, &$8);	}/* * load/store multiple */|	LMOVMW addr ',' rreg	{		outcode($1, &$2, NREG, &$4);	}

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