#include "gc.h" voidpeep(void){	Reg *r, *r1, *r2;	Prog *p, *p1;	int t;/* * complete R structure */	t = 0;	for(r=firstr; r!=R; r=r1) {		r1 = r->link;		if(r1 == R)			break;		p = r->prog->link;		while(p != r1->prog)		switch(p->as) {		default:			r2 = rega();			r->link = r2;			r2->link = r1; 			r2->prog = p;			r2->p1 = r;			r->s1 = r2;			r2->s1 = r1;			r1->p1 = r2; 			r = r2;			t++; 		case ADATA:		case AGLOBL:		case ANAME:		case ASIGNAME:			p = p->link;		}	} loop1:	t = 0;	for(r=firstr; r!=R; r=r->link) {		p = r->prog;		if(p->as == AMOVW || p->as == AFMOVS || p->as == AFMOVD)		if(regtyp(&p->to)) {			if(regtyp(&p->from))			if(p->from.type == p->to.type) {				if(copyprop(r)) {					excise(r);					t++;				} else				if(subprop(r) && copyprop(r)) {					excise(r);					t++;				}			}			if(regzer(&p->from))			if(p->to.type == D_REG) {				p->from.type = D_REG;				p->from.reg = REGZERO;				if(copyprop(r)) {					excise(r);					t++;				} else				if(subprop(r) && copyprop(r)) {					excise(r);					t++;				}			}		}	}	if(t)		goto loop1;	/*	 * look for MOVB x,R; MOVB R,R	 */	for(r=firstr; r!=R; r=r->link) {		p = r->prog;		switch(p->as) {		default:			continue;		case AMOVH:		case AMOVHZ:		case AMOVB:		case AMOVBZ:			if(p->to.type != D_REG)				continue;			break;		}		r1 = r->link;		if(r1 == R)			continue;		p1 = r1->prog;		if(p1->as != p->as)			continue;		if(p1->from.type != D_REG || p1->from.reg != p->to.reg)			continue;		if(p1->to.type != D_REG || p1->to.reg != p->to.reg)			continue;		excise(r1);	} 	if(debug['Q'] > 1)		return;	/* allow following code improvement to be suppressed */ 	/*	 * look for OP x,y,R; CMP R, $0 -> OPCC x,y,R	 * when OP can set condition codes correctly	 */	for(r=firstr; r!=R; r=r->link) {		p = r->prog;		switch(p->as) {		case ACMP:			if(!regzer(&p->to))				continue;			r1 = r->s1;			if(r1 == R)				continue;			switch(r1->prog->as) {			default:				continue;			case ABCL:			case ABC:				/* the conditions can be complex and these are currently little used */				continue;			case ABEQ:			case ABGE:			case ABGT:			case ABLE:			case ABLT:			case ABNE:			case ABVC:			case ABVS:				break;			}			r1 = r;			do				r1 = uniqp(r1);			while (r1 != R && r1->prog->as == ANOP);			if(r1 == R)				continue;			p1 = r1->prog;			if(p1->to.type != D_REG || p1->to.reg != p->from.reg)				continue;			switch(p1->as) {			case ASUB:			case AADD:			case AXOR:			case AOR:				/* irregular instructions */				if(p1->from.type == D_CONST)					continue;				break;			}			switch(p1->as) {			default:				continue;			case AMOVW:				if(p1->from.type != D_REG)					continue;				continue;			case AANDCC:			case AANDNCC:			case AORCC:			case AORNCC:			case AXORCC:			case ASUBCC:			case ASUBECC:			case ASUBMECC:			case ASUBZECC:			case AADDCC:			case AADDCCC:			case AADDECC:			case AADDMECC:			case AADDZECC:			case ARLWMICC:			case ARLWNMCC:				t = p1->as;				break;			/* don't deal with floating point instructions for now *//*			case AFABS:	t = AFABSCC; break;			case AFADD:	t = AFADDCC; break;			case AFADDS:	t = AFADDSCC; break;			case AFCTIW:	t = AFCTIWCC; break;			case AFCTIWZ:	t = AFCTIWZCC; break;			case AFDIV:	t = AFDIVCC; break;			case AFDIVS:	t = AFDIVSCC; break;			case AFMADD:	t = AFMADDCC; break;			case AFMADDS:	t = AFMADDSCC; break;			case AFMOVD:	t = AFMOVDCC; break;			case AFMSUB:	t = AFMSUBCC; break;			case AFMSUBS:	t = AFMSUBSCC; break;			case AFMUL:	t = AFMULCC; break;			case AFMULS:	t = AFMULSCC; break;			case AFNABS:	t = AFNABSCC; break;			case AFNEG:	t = AFNEGCC; break;			case AFNMADD:	t = AFNMADDCC; break;			case AFNMADDS:	t = AFNMADDSCC; break;			case AFNMSUB:	t = AFNMSUBCC; break;			case AFNMSUBS:	t = AFNMSUBSCC; break;			case AFRSP:	t = AFRSPCC; break;			case AFSUB:	t = AFSUBCC; break;			case AFSUBS:	t = AFSUBSCC; break;			case ACNTLZW:	t = ACNTLZWCC; break;			case AMTFSB0:	t = AMTFSB0CC; break;			case AMTFSB1:	t = AMTFSB1CC; break;*/			case AADD:	t = AADDCC; break;			case AADDV:	t = AADDVCC; break;			case AADDC:	t = AADDCCC; break;			case AADDCV:	t = AADDCVCC; break;			case AADDME:	t = AADDMECC; break;			case AADDMEV:	t = AADDMEVCC; break;			case AADDE:	t = AADDECC; break;			case AADDEV:	t = AADDEVCC; break;			case AADDZE:	t = AADDZECC; break;			case AADDZEV:	t = AADDZEVCC; break;			case AAND:	t = AANDCC; break;			case AANDN:	t = AANDNCC; break;			case ADIVW:	t = ADIVWCC; break;			case ADIVWV:	t = ADIVWVCC; break;			case ADIVWU:	t = ADIVWUCC; break;			case ADIVWUV:	t = ADIVWUVCC; break;			case AEQV:	t = AEQVCC; break;			case AEXTSB:	t = AEXTSBCC; break;			case AEXTSH:	t = AEXTSHCC; break;			case AMULHW:	t = AMULHWCC; break;			case AMULHWU:	t = AMULHWUCC; break;			case AMULLW:	t = AMULLWCC; break;			case AMULLWV:	t = AMULLWVCC; break;			case ANAND:	t = ANANDCC; break;			case ANEG:	t = ANEGCC; break;			case ANEGV:	t = ANEGVCC; break;			case ANOR:	t = ANORCC; break;			case AOR:	t = AORCC; break;			case AORN:	t = AORNCC; break;			case AREM:	t = AREMCC; break;			case AREMV:	t = AREMVCC; break;			case AREMU:	t = AREMUCC; break;			case AREMUV:	t = AREMUVCC; break;			case ARLWMI:	t = ARLWMICC; break;			case ARLWNM:	t = ARLWNMCC; break;			case ASLW:	t = ASLWCC; break;			case ASRAW:	t = ASRAWCC; break;			case ASRW:	t = ASRWCC; break;			case ASUB:	t = ASUBCC; break;			case ASUBV:	t = ASUBVCC; break;			case ASUBC:	t = ASUBCCC; break;			case ASUBCV:	t = ASUBCVCC; break;			case ASUBME:	t = ASUBMECC; break;			case ASUBMEV:	t = ASUBMEVCC; break;			case ASUBE:	t = ASUBECC; break;			case ASUBEV:	t = ASUBEVCC; break;			case ASUBZE:	t = ASUBZECC; break;			case ASUBZEV:	t = ASUBZEVCC; break;			case AXOR:	t = AXORCC; break;				break;			}			if(debug['Q'])				print("cmp %P; %P -> ", p1, p);			p1->as = t;			if(debug['Q'])				print("%P\n", p1);			excise(r);			continue;		}	}} voidexcise(Reg *r){	Prog *p; 	p = r->prog;	p->as = ANOP;	p->from = zprog.from;	p->from3 = zprog.from3;	p->to = zprog.to;	p->reg = zprog.reg; /**/} Reg*uniqp(Reg *r){	Reg *r1; 	r1 = r->p1;	if(r1 == R) {		r1 = r->p2;		if(r1 == R || r1->p2link != R)			return R;	} else		if(r->p2 != R)			return R;	return r1;} Reg*uniqs(Reg *r){	Reg *r1; 	r1 = r->s1;	if(r1 == R) {		r1 = r->s2;		if(r1 == R)			return R;	} else		if(r->s2 != R)			return R;	return r1;} /* * if the system forces R0 to be zero, * convert references to $0 to references to R0. */intregzer(Adr *a){	if(R0ISZERO) {		if(a->type == D_CONST)			if(a->sym == S)				if(a->offset == 0)					return 1;		if(a->type == D_REG)			if(a->reg == REGZERO)				return 1;	}	return 0;} intregtyp(Adr *a){ 	if(a->type == D_REG) {		if(!R0ISZERO || a->reg != REGZERO)			return 1;		return 0;	}	if(a->type == D_FREG)		return 1;	return 0;} /* * the idea is to substitute * one register for another * from one MOV to another *	MOV	a, R0 *	ADD	b, R0	/ no use of R1 *	MOV	R0, R1 * would be converted to *	MOV	a, R1 *	ADD	b, R1 *	MOV	R1, R0 * hopefully, then the former or latter MOV * will be eliminated by copy propagation. */intsubprop(Reg *r0){	Prog *p;	Adr *v1, *v2;	Reg *r;	int t; 	p = r0->prog;	v1 = &p->from;	if(!regtyp(v1))		return 0;	v2 = &p->to;	if(!regtyp(v2))		return 0;	for(r=uniqp(r0); r!=R; r=uniqp(r)) {		if(uniqs(r) == R)			break;		p = r->prog;		switch(p->as) {		case ABL:			return 0; 		case AADD:		case AADDC:		case AADDCC:		case AADDE:		case AADDECC:		case ASUB:		case ASUBCC:		case ASUBC:		case ASUBCCC:		case ASUBE:		case ASUBECC:		case ASLW:		case ASLWCC:		case ASRW:		case ASRWCC:		case ASRAW:		case ASRAWCC:		case AOR:		case AORCC:		case AORN:		case AORNCC:		case AAND:		case AANDCC:		case AANDN:		case AANDNCC:		case ANAND:		case ANANDCC:		case ANOR:		case ANORCC:		case AXOR:		case AXORCC:		case AMULHW:		case AMULHWU:		case AMULLW:		case ADIVW:		case ADIVWU:		case AREM:		case AREMU:		case ARLWNM:		case ARLWNMCC:		case ARLWMI:		case ARLWMICC: 		case AFADD:		case AFADDS:		case AFSUB:		case AFSUBS:		case AFMUL:		case AFMULS:		case AFDIV:		case AFDIVS:			if(p->to.type == v1->type)			if(p->to.reg == v1->reg) {				if(p->reg == NREG)					p->reg = p->to.reg;				goto gotit;			}			break; 		case AADDME:		case AADDMECC:		case AADDZE:		case AADDZECC:		case ASUBME:		case ASUBMECC:		case ASUBZE:		case ASUBZECC:		case ANEG:		case ANEGCC:		case AFNEG:		case AFNEGCC:		case AFMOVS:		case AFMOVD:		case AMOVW:			if(p->to.type == v1->type)			if(p->to.reg == v1->reg)				goto gotit;			break;		}		if(copyau(&p->from, v2) ||		   copyau1(p, v2) ||		   copyau(&p->to, v2))			break;		if(copysub(&p->from, v1, v2, 0) ||		   copysub1(p, v1, v2, 0) ||		   copysub(&p->to, v1, v2, 0))			break;	}	return 0; gotit:	copysub(&p->to, v1, v2, 1);	if(debug['P']) {		print("gotit: %D->%D\n%P", v1, v2, r->prog);		if(p->from.type == v2->type)			print(" excise");		print("\n");	}	for(r=uniqs(r); r!=r0; r=uniqs(r)) {		p = r->prog;		copysub(&p->from, v1, v2, 1);		copysub1(p, v1, v2, 1);		copysub(&p->to, v1, v2, 1);		if(debug['P'])			print("%P\n", r->prog);	}	t = v1->reg;	v1->reg = v2->reg;	v2->reg = t;	if(debug['P'])		print("%P last\n", r->prog);	return 1;}

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