<html><title>data</title><body BGCOLOR="#FFFFFF" TEXT="#000000" LINK="#0000FF" VLINK="#330088" ALINK="#FF0044"><H1>A Manual for the Plan 9 assembler</H1><DL><DD><I>Rob Pike<br>rob@plan9.bell-labs.com<br></I></DL><H4>Machines</H4><P>There is an assembler for each of the MIPS, SPARC, Intel 386,Intel 960, AMD 29000, Motorola 68020 and 68000, Motorola Power PC, DEC Alpha, and Acorn ARM.The 68020 assembler,<TT>2a</TT>,is the oldest and in many ways the prototype.The assemblers are really just variations of a single program:they share many properties such as left-to-right assignment order forinstruction operands and the synthesis of macro instructionssuch as<TT>MOVE</TT>to hide the peculiarities of the load and store structure of the machines.To keep things concrete, the first part of this manual isspecifically about the 68020.At the end is a description of the differences amongthe other assemblers.</P><P>The document, ``How to Use the Plan 9 C Compiler'', by Rob Pike,is a prerequisite for this manual.</P><H4>Registers</H4><P>All pre-defined symbols in the assembler are upper-case.Data registers are<TT>R0</TT>through<TT>R7</TT>;address registers are<TT>A0</TT>through<TT>A7</TT>;floating-point registers are<TT>F0</TT>through<TT>F7</TT>.</P><P>A pointer in<TT>A6</TT>is used by the C compiler to point to data, enabling short addresses tobe used more often.The value of<TT>A6</TT>is constant and must be set during C program initializationto the address of the externally-defined symbol<TT>a6base</TT>.</P><P>The following hardware registers are defined in the assembler; theirmeaning should be obvious given a 68020 manual:<TT>CAAR</TT>,<TT>CACR</TT>,<TT>CCR</TT>,<TT>DFC</TT>,<TT>ISP</TT>,<TT>MSP</TT>,<TT>SFC</TT>,<TT>SR</TT>,<TT>USP</TT>,and<TT>VBR</TT>.</P><P>The assembler also defines several pseudo-registers thatmanipulate the stack:<TT>FP</TT>,<TT>SP</TT>,and<TT>TOS</TT>.<TT>FP</TT>is the frame pointer, so<TT>0(FP)</TT>is the first argument,<TT>4(FP)</TT>is the second, and so on.<TT>SP</TT>is the local stack pointer, where automatic variables are held(SP is a pseudo-register only on the 68020);<TT>0(SP)</TT>is the first automatic, and so on as with<TT>FP</TT>.Finally,<TT>TOS</TT>is the top-of-stack register, used for pushing parameters to procedures,saving temporary values, and so on.</P><P>The assembler and loader track these pseudo-registers sothe above statements are true regardless of what has beenpushed on the hardware stack, pointed to by<TT>A7</TT>.The name<TT>A7</TT>refers to the hardware stack pointer, but beware of mixed use of<TT>A7</TT>and the above stack-related pseudo-registers, which will cause trouble.Note, too, that the<TT>PEA</TT>instruction is observed by the loader toalter SP and thus will insert a corresponding pop before all returns.The assembler accepts a label-like name to be attached to<TT>FP</TT>and<TT>SP</TT>uses, such as<TT>p+0(FP)</TT>,to help document that<TT>p</TT>is the first argument to a routine.The name goes in the symbol table but has no significance to the resultof the program.</P><H4>Referring to data</H4><P>All external references must be made relative to some pseudo-register,either<TT>PC</TT>(the virtual program counter) or<TT>SB</TT>(the ``static base'' register).<TT>PC</TT>counts instructions, not bytes of data.For example, to branch to the second following instruction, that is,to skip one instruction, one may write<DL><DT><DD><TT><PRE>	BRA	2(PC)</PRE></TT></DL>Labels are also allowed, as in<DL><DT><DD><TT><PRE>	BRA	return	NOPreturn:	RTS</PRE></TT></DL>When using labels, there is no<TT>(PC)</TT>annotation.</P><P>The pseudo-register<TT>SB</TT>refers to the beginning of the address space of the program.Thus, references to global data and procedures are written asoffsets to<TT>SB</TT>,as in<DL><DT><DD><TT><PRE>	MOVL	$array(SB), TOS</PRE></TT></DL>to push the address of a global array on the stack, or<DL><DT><DD><TT><PRE>	MOVL	array+4(SB), TOS</PRE></TT></DL>to push the second (4-byte) element of the array.Note the use of an offset; the complete list of addressing modes is given below.Similarly, subroutine calls must use<TT>SB</TT>:<DL><DT><DD><TT><PRE>	BSR	exit(SB)</PRE></TT></DL>File-static variables have syntax<DL><DT><DD><TT><PRE>	local&#60;&#62;+4(SB)</PRE></TT></DL>The<TT><></TT>will be filled in at load time by a unique integer.</P><P>When a program starts, it must execute<DL><DT><DD><TT><PRE>	MOVL	$a6base(SB), A6</PRE></TT></DL>before accessing any global data.(On machines such as the MIPS and SPARC that cannot load a registerin a single instruction, constants are loaded through the static baseregister.  The loader recognizes code that initializes the staticbase register and treats it specially.  You must be careful, however,not to load large constants on such machines when the static baseregister is not set up, such as early in interrupt routines.)</P><H4>Expressions</H4><P>Expressions are mostly what one might expect.Where an offset or a constant is expected,a primary expression with unary operators is allowed.A general C constant expression is allowed in parentheses.</P><P>Source files are preprocessed exactly as in the C compiler, so<TT>#define</TT>and<TT>#include</TT>work.</P><H4>Addressing modes</H4><P>The simple addressing modes are shared by all the assemblers.Here, for completeness, follows a table of all the 68020 addressing modes,since that machine has the richest set.In the table,<TT>o</TT>is an offset, which if zero may be elided, and<TT>d</TT>is a displacement, which is a constant between -128 and 127 inclusive.Many of the modes listed have the same name;scrutiny of the format will show what default is being applied.For instance, indexed mode with no address register supplied operatesas though a zero-valued register were used.For "offset" read "displacement."For "<TT>.s</TT>" read one of<TT>.L</TT>,or<TT>.W</TT>followed by<TT>*1</TT>,<TT>*2</TT>,<TT>*4</TT>,or<TT>*8</TT>to indicate the size and scaling of the data.</P><DL><DT><DT>&#32;<DD><br><img src="data.10610.gif"><br></dl><H4>Laying down data</H4><P>Placing data in the instruction stream, say for interrupt vectors, is easy:the pseudo-instructions<TT>LONG</TT>and<TT>WORD</TT>(but not<TT>BYTE</TT>)lay down the value of their single argument, of the appropriate size,as if it were an instruction:<DL><DT><DD><TT><PRE>	LONG	$12345</PRE></TT></DL>places the long 12345 (base 10)in the instruction stream.(On most machines,the only such operator is<TT>WORD</TT>and it lays down 32-bit quantities.The 386 has all three:<TT>LONG</TT>,<TT>WORD</TT>,and<TT>BYTE</TT>.The 960 has only one,<TT>LONG</TT>.)</P><P>Placing information in the data section is more painful.The pseudo-instruction<TT>DATA</TT>does the work, given two arguments: an address at which to place the item,including its size,and the value to place there.  For example, to define a character array<TT>array</TT>containing the characters<TT>abc</TT>and a terminating null:<DL><DT><DD><TT><PRE>	DATA    array+0(SB)/1, $'a'	DATA    array+1(SB)/1, $'b'	DATA    array+2(SB)/1, $'c'	GLOBL   array(SB), $4</PRE></TT></DL>or<DL><DT><DD><TT><PRE>	DATA    array+0(SB)/4, $"abc\z"	GLOBL   array(SB), $4</PRE></TT></DL>The<TT>/1</TT>defines the number of bytes to define,<TT>GLOBL</TT>makes the symbol global, and the<TT>$4</TT>says how many bytes the symbol occupies.Uninitialized data is zeroed automatically.The character<TT>z</TT>is equivalent to the C<TT> .</TT>The string in a<TT>DATA</TT>statement may contain a maximum of eight bytes;build larger strings piecewise.Two pseudo-instructions,<TT>DYNT</TT>and<TT>INIT</TT>,allow the (obsolete) Alef compilers to build dynamic type information during the loadphase.The<TT>DYNT</TT>pseudo-instruction has two forms:<DL><DT><DD><TT><PRE>	DYNT	, ALEF_SI_5+0(SB)	DYNT	ALEF_AS+0(SB), ALEF_SI_5+0(SB)</PRE></TT></DL>In the first form,<TT>DYNT</TT>defines the symbol to be a small unique integer constant, chosen by the loader,which is some multiple of the word size.  In the second form,<TT>DYNT</TT>defines the second symbol in the same way,places the address of the most recentlydefined text symbol in the array specified by the first symbol at theindex defined by the value of the second symbol,and then adjusts the size of the array accordingly.</P><P>The<TT>INIT</TT>pseudo-instruction takes the same parameters as a<TT>DATA</TT>statement.  Its symbol is used as the base of an array and thedata item is installed in the array at the offset specified by the most recent<TT>DYNT</TT>pseudo-instruction.The size of the array is adjusted accordingly.The<TT>DYNT</TT>and<TT>INIT</TT>pseudo-instructions are not implemented on the 68020.</P><H4>Defining a procedure</H4><P>Entry points are defined by the pseudo-operation<TT>TEXT</TT>,which takes as arguments the name of the procedure (including the ubiquitous<TT>(SB)</TT>)and the number of bytes of automatic storage to pre-allocate on the stack,which will usually be zero when writing assembly language programs.On machines with a link register, such as the MIPS and SPARC,the special value -4 instructs the loader to generate no PC saveand restore instructions, even if the function is not a leaf.Here is a complete procedure that returns the sumof its two arguments:<DL><DT><DD><TT><PRE>TEXT	sum(SB), $0	MOVL	arg1+0(FP), R0	ADDL	arg2+4(FP), R0	RTS</PRE></TT></DL>An optional middle argumentto the<TT>TEXT</TT>pseudo-op is a bit field of options to the loader.Setting the 1 bit suspends profiling the function when profiling is enabled for the rest ofthe program.For example,<DL><DT><DD><TT><PRE>TEXT	sum(SB), 1, $0	MOVL	arg1+0(FP), R0	ADDL	arg2+4(FP), R0	RTS</PRE></TT></DL>will not be profiled; the first version above would be.Subroutines with peculiar state, such as system call routines,should not be profiled.</P><P>Setting the 2 bit allows multiple definitions of the same<TT>TEXT</TT>symbol in a program; the loader will place only one such function in the image.It was emitted only by the Alef compilers.</P><P>Subroutines to be called from C should place their result in<TT>R0</TT>,even if it is an address.Floating point values are returned in<TT>F0</TT>.Functions that return a structure to a C programreceive as their first argument the address of the location tostore the result;<TT>R0</TT>is unused in the calling protocol for such procedures.A subroutine is responsible for saving its own registers,and therefore is free to use any registers without saving them (``caller saves'').<TT>A6</TT>and<TT>A7</TT>are the exceptions as described above.</P><H4>When in doubt</H4><P>If you get confused, try using the<TT>-S</TT>option to<TT>2c</TT>and compiling a sample program.The standard output is valid input to the assembler.</P><H4>Instructions</H4><P>The instruction set of the assembler is not identical to thatof the machine.It is chosen to match what the compiler generates, augmentedslightly by specific needs of the operating system.For example,<TT>2a</TT>does not distinguish between the various forms of<TT>MOVE</TT>instruction: move quick, move address, etc.  Instead the contextdoes the job.  For example,<DL><DT><DD><TT><PRE>	MOVL	$1, R1	MOVL	A0, R2	MOVW	SR, R3</PRE></TT></DL>generates official<TT>MOVEQ</TT>,<TT>MOVEA</TT>,and<TT>MOVESR</TT>instructions.A number of instructions do not have the syntax necessary to specifytheir entire capabilities.  Notable examples are the bitfieldinstructions, themultiply and divide instructions, etc.For a complete set of generated instruction names (in<TT>2a</TT>notation, not Motorola's) see the file<TT>/sys/src/cmd/2c/2.out.h</TT>.Despite its name, this file contains an enumeration of theinstructions that appear in the intermediate files generatedby the compiler, which correspond exactly to lines of assembly language.</P><P>The MC68000 assembler,<TT>1a</TT>,is essentially the same, honoring the appropriate subset of the instructionsand addressing modes.The definitions of these are, nonetheless, part of<TT>2.out.h</TT>.</P><H4>Laying down instructions</H4><P>The loader modifies the code produced by the assembler and compiler.It folds branches,copies short sequences of code to eliminate branches,and discards unreachable code.The first instruction of every function is assumed to be reachable.The pseudo-instruction<TT>NOP</TT>,which you may see in compiler output,means no instruction at all, rather than an instruction that does nothing.The loader discards all<TT>NOP</TT>'s.</P><P>To generate a true<TT>NOP</TT>instruction, or any other instruction not known to the assembler, use a<TT>WORD</TT>pseudo-instruction.Such instructions on RISCs are not scheduled by the loader and must havetheir delay slots filled manually.</P><H4>MIPS</H4><P>The registers are only addressed by number:<TT>R0</TT>through<TT>R31</TT>.<TT>R29</TT>is the stack pointer;<TT>R30</TT>is used as the static base pointer, the analogue of

Lines 1–500 of 1359. Load more