#include <ucontext.h>#include "libvx32/vx32.h" typedef struct BIOS32si	BIOS32si;typedef struct Conf	Conf;typedef struct Confmem	Confmem;typedef struct FPsave	FPsave;typedef struct ISAConf	ISAConf;typedef struct Label	Label;typedef struct Lock	Lock;typedef struct MMU	MMU;typedef struct Mach	Mach;typedef struct Notsave	Notsave;typedef struct PCArch	PCArch;typedef struct Pcidev	Pcidev;typedef struct PCMmap	PCMmap;typedef struct PCMslot	PCMslot;typedef struct Page	Page;typedef struct PMMU	PMMU;typedef struct Proc	Proc;typedef struct Segdesc	Segdesc;typedef vlong		Tval;typedef struct Ureg	Ureg;typedef struct Vctl	Vctl;  #define MAXSYSARG	5	/* for mount(fd, afd, mpt, flag, arg) */ /* *  parameters for sysproc.c */#define AOUT_MAGIC	(I_MAGIC) struct Lock{	ulong	key;	ulong	sr;	ulong	pc;	Proc	*p;	Mach	*m_;	ushort	isilock;	long	lockcycles;}; struct Label{	uint64	bp;  // Plan 9 VX	uint64	bx;	uint64	si;	uint64	di;	uint64	sp;	uint64	pc;	uint64	r12;	uint64	r13;	uint64	r14;	uint64	r15;};  /* * FPsave.status */enum{	/* this is a state */	FPinit=		0,	FPactive=	1,	FPinactive=	2, 	/* the following is a bit that can be or'd into the state */	FPillegal=	0x100,}; struct	FPsave{	ushort	control;	ushort	r1;	ushort	status;	ushort	r2;	ushort	tag;	ushort	r3;	ulong	pc;	ushort	selector;	ushort	r4;	ulong	operand;	ushort	oselector;	ushort	r5;	uchar	regs[80];	/* floating point registers */}; struct Confmem{	ulong	base;	ulong	npage;	ulong	kbase;	ulong	klimit;}; struct Conf{	ulong	nmach;		/* processors */	ulong	nproc;		/* processes */	ulong	monitor;	/* has monitor? */	Confmem	mem[4];		/* physical memory */	ulong	npage;		/* total physical pages of memory */	ulong	upages;		/* user page pool */	ulong	nimage;		/* number of page cache image headers */	ulong	nswap;		/* number of swap pages */	int	nswppo;		/* max # of pageouts per segment pass */	ulong	base0;		/* base of bank 0 */	ulong	base1;		/* base of bank 1 */	ulong	copymode;	/* 0 is copy on write, 1 is copy on reference */	ulong	ialloc;		/* max interrupt time allocation in bytes */	ulong	pipeqsize;	/* size in bytes of pipe queues */	int	nuart;		/* number of uart devices */}; /* *  MMU stuff in proc */#define NCOLOR 1typedef struct Uspace Uspace;struct PMMU{	struct vxproc *vxproc;	// Plan 9 VX	struct vxmem vxmem;	struct vxmmap vxmm;	// Plan 9 VX	Uspace *us;	uchar *uzero;}; /* *  things saved in the Proc structure during a notify */struct Notsave{	ulong	svflags;	ulong	svcs;	ulong	svss;}; #include "portdat.h" typedef struct {	ulong	link;			/* link (old TSS selector) */	ulong	esp0;			/* privilege level 0 stack pointer */	ulong	ss0;			/* privilege level 0 stack selector */	ulong	esp1;			/* privilege level 1 stack pointer */	ulong	ss1;			/* privilege level 1 stack selector */	ulong	esp2;			/* privilege level 2 stack pointer */	ulong	ss2;			/* privilege level 2 stack selector */	ulong	xcr3;			/* page directory base register - not used because we don't use trap gates */	ulong	eip;			/* instruction pointer */	ulong	eflags;			/* flags register */	ulong	eax;			/* general registers */	ulong 	ecx;	ulong	edx;	ulong	ebx;	ulong	esp;	ulong	ebp;	ulong	esi;	ulong	edi;	ulong	es;			/* segment selectors */	ulong	cs;	ulong	ss;	ulong	ds;	ulong	fs;	ulong	gs;	ulong	ldt;			/* selector for task's LDT */	ulong	iomap;			/* I/O map base address + T-bit */} Tss; struct Segdesc{	ulong	d0;	ulong	d1;}; struct Mach{#ifndef TLS	Proc*	externup;#endif	int	new;	int	machno;			/* physical id of processor (KNOWN TO ASSEMBLY) */	ulong	splpc;			/* pc of last caller to splhi */ 	Segdesc	*gdt;			/* gdt for this processor */ 	Proc*	proc;			/* current process on this processor */ 	Page*	pdbpool;	int	pdbcnt; 	Label	sched;			/* scheduler wakeup */ 	Proc*	readied;		/* for runproc */	ulong	schedticks;		/* next forced context switch */ 	int	tlbfault;	int	tlbpurge;	int	pfault;	int	cs;	int	syscall;	int	load;	int	intr;	int	flushmmu;		/* make current proc flush it's mmu state */	int	ilockdepth;	Perf	perf;			/* performance counters */ 	ulong	spuriousintr;	int	lastintr;  	Lock	apictimerlock;	int	cpumhz;	uvlong	cyclefreq;		/* Frequency of user readable cycle counter */	uvlong	cpuhz;	int	cpuidax;	int	cpuiddx;	char	cpuidid[16];	char*	cpuidtype;	int	havetsc;	int	havepge;	uvlong	tscticks;	int	pdballoc;	int	pdbfree;  	int	spl;	// Plan 9 VX	void	*sigstack;	int	stack[1];}; /* * KMap the structure doesn't exist, but the functions do. */typedef struct KMap		KMap;#define	VA(k)		((void*)(k))KMap*	kmap(Page*);void	kunmap(KMap*); struct{	Lock lk;	int	machs;			/* bitmap of active CPUs */	int	exiting;		/* shutdown */	int	ispanic;		/* shutdown in response to a panic */	int	thunderbirdsarego;	/* lets the added processors continue to schedinit */}active; /* *  routines for things outside the PC model, like power management */struct PCArch{	char*	id;	int	(*ident)(void);		/* this should be in the model */	void	(*reset)(void);		/* this should be in the model */	int	(*serialpower)(int);	/* 1 == on, 0 == off */	int	(*modempower)(int);	/* 1 == on, 0 == off */ 	void	(*intrinit)(void);	int	(*intrenable)(Vctl*);	int	(*intrvecno)(int);	int	(*intrdisable)(int);	void	(*introff)(void);	void	(*intron)(void); 	void	(*clockenable)(void);	uvlong	(*fastclock)(uvlong*);	void	(*timerset)(uvlong);}; /* cpuid instruction result register bits */enum {	/* dx */	Fpuonchip = 1<<0,//	Pse	= 1<<3,		/* page size extensions */	Tsc	= 1<<4,		/* time-stamp counter */	Cpumsr	= 1<<5,		/* model-specific registers, rdmsr/wrmsr */	Pae	= 1<<6,		/* physical-addr extensions */	Mce	= 1<<7,		/* machine-check exception */	Cmpxchg8b = 1<<8,	Cpuapic	= 1<<9,	Mtrr	= 1<<12,	/* memory-type range regs.  */	Pge	= 1<<13,	/* page global extension *///	Pse2	= 1<<17,	/* more page size extensions */	Clflush = 1<<19,	Mmx	= 1<<23,	Sse	= 1<<25,	/* thus sfence instr. */	Sse2	= 1<<26,	/* thus mfence & lfence instr.s */}; /* *  a parsed plan9.ini line */#define NISAOPT		8 struct ISAConf {	char	*type;	ulong	port;	int	irq;	ulong	dma;	ulong	mem;	ulong	size;	ulong	freq; 	int	nopt;	char	*opt[NISAOPT];}; extern PCArch	*arch;			/* PC architecture */ /* * Each processor sees its own Mach structure at address MACHADDR. * However, the Mach structures must also be available via the per-processor * MMU information array machp, mainly for disambiguation and access to * the clock which is only maintained by the bootstrap processor (0). */Mach* machp[MAXMACH];	#define	MACHP(n)	(machp[n]) #ifdef TLS	extern __thread Mach	*m;	// Plan 9 VX	extern __thread Proc	*up;	// Plan 9 VX#	define thismach m#	define setmach(x) (m = (x))#else	extern Mach *getmach(void);	extern void setmach(Mach*);#	define up getmach()->externup#	ifdef WANT_M#		define m getmach()#	endif#endif /* *  hardware info about a device */typedef struct {	ulong	port;		int	size;} Devport; struct DevConf{	ulong	intnum;			/* interrupt number */	char	*type;			/* card type, malloced */	int	nports;			/* Number of ports */	Devport	*ports;			/* The ports themselves */};  // Plan 9 VXextern int traceprocs;extern int tracesyscalls;extern int doabort; /* Pthreads-based sleep and wakeup. */typedef struct Psleep Psleep;typedef struct Pwaiter Pwaiter;struct Psleep{	int init;	pthread_mutex_t mutex;	Pwaiter *waiter;}; struct Uspace{	Proc *p;	// proc currently mapped	uchar *uzero;	ulong lo;	ulong hi;};