x86: h264_idct: port to cpuflags

Diego Biurrun committed 14 years ago

Commit 2e89aee1 parent 490df521 file · +70 −69Browse files

Unified · Split

@@ -76,9 +76,9 @@ SECTION .text · 75 unmodified lines
76	76	STORE_DIFFx2 m2, m3, m4, m5, m7, 6, %1, %3
77	77	%endmacro
78	78
79		−INIT_MMX
	79	+INIT_MMX mmx
80	80	; ff_h264_idct_add_mmx(uint8_t dst, int16_t block, int stride)
81		−cglobal h264_idct_add_8_mmx, 3, 3, 0
	81	+cglobal h264_idct_add_8, 3, 3, 0
82	82	IDCT4_ADD r0, r1, r2
83	83	RET
84	84
@@ -180,9 +180,9 @@ cglobal h264_idct_add_8_mmx, 3, 3, 0 · 95 unmodified lines
180	180	STORE_DIFFx2 m1, m2, m5, m6, m7, 6, %1, %3
181	181	%endmacro
182	182
183		−INIT_MMX
	183	+INIT_MMX mmx
184	184	; ff_h264_idct8_add_mmx(uint8_t dst, int16_t block, int stride)
185		−cglobal h264_idct8_add_8_mmx, 3, 4, 0
	185	+cglobal h264_idct8_add_8, 3, 4, 0
186	186	%assign pad 128+4-(stack_offset&7)
187	187	SUB rsp, pad
188	188
@@ -240,9 +240,9 @@ cglobal h264_idct8_add_8_mmx, 3, 4, 0 · 51 unmodified lines
240	240	STORE_DIFF m1, m6, m7, [%1+%4 ]
241	241	%endmacro
242	242
243		−INIT_XMM
	243	+INIT_XMM sse2
244	244	; ff_h264_idct8_add_sse2(uint8_t dst, int16_t block, int stride)
245		−cglobal h264_idct8_add_8_sse2, 3, 4, 10
	245	+cglobal h264_idct8_add_8, 3, 4, 10
246	246	IDCT8_ADD_SSE r0, r1, r2, r3
247	247	RET
248	248
@@ -285,24 +285,25 @@ cglobal h264_idct8_add_8_sse2, 3, 4, 10 · 36 unmodified lines
285	285	%1 [%2+%4 ], m5
286	286	%endmacro
287	287
288		−INIT_MMX
	288	+INIT_MMX mmxext
289	289	; ff_h264_idct_dc_add_mmxext(uint8_t dst, int16_t block, int stride)
290		−cglobal h264_idct_dc_add_8_mmxext, 3, 3, 0
	290	+cglobal h264_idct_dc_add_8, 3, 3, 0
291	291	DC_ADD_MMXEXT_INIT r1, r2
292	292	DC_ADD_MMXEXT_OP movh, r0, r2, r1
293	293	RET
294	294
295	295	; ff_h264_idct8_dc_add_mmxext(uint8_t dst, int16_t block, int stride)
296		−cglobal h264_idct8_dc_add_8_mmxext, 3, 3, 0
	296	+cglobal h264_idct8_dc_add_8, 3, 3, 0
297	297	DC_ADD_MMXEXT_INIT r1, r2
298	298	DC_ADD_MMXEXT_OP mova, r0, r2, r1
299	299	lea r0, [r0+r2*4]
300	300	DC_ADD_MMXEXT_OP mova, r0, r2, r1
301	301	RET
302	302
	303	+INIT_MMX mmx
303	304	; ff_h264_idct_add16_mmx(uint8_t dst, const int block_offset,
304	305	; DCTELEM block, int stride, const uint8_t nnzc[68])
305		−cglobal h264_idct_add16_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
	306	+cglobal h264_idct_add16_8, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
306	307	xor r5, r5
307	308	%ifdef PIC
308	309	lea picregq, [scan8_mem]
@@ -324,7 +325,7 @@ cglobal h264_idct_add16_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, str · 15 unmodified lines
324	325
325	326	; ff_h264_idct8_add4_mmx(uint8_t dst, const int block_offset,
326	327	; DCTELEM block, int stride, const uint8_t nnzc[68])
327		−cglobal h264_idct8_add4_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
	328	+cglobal h264_idct8_add4_8, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
328	329	%assign pad 128+4-(stack_offset&7)
329	330	SUB rsp, pad
330	331
@@ -354,9 +355,10 @@ cglobal h264_idct8_add4_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, str · 23 unmodified lines
354	355	ADD rsp, pad
355	356	RET
356	357
	358	+INIT_MMX mmxext
357	359	; ff_h264_idct_add16_mmxext(uint8_t dst, const int block_offset,
358	360	; DCTELEM block, int stride, const uint8_t nnzc[68])
359		−cglobal h264_idct_add16_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	361	+cglobal h264_idct_add16_8, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
360	362	xor r5, r5
361	363	%ifdef PIC
362	364	lea picregq, [scan8_mem]
@@ -398,9 +400,10 @@ cglobal h264_idct_add16_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, · 35 unmodified lines
398	400	jl .nextblock
399	401	REP_RET
400	402
	403	+INIT_MMX mmx
401	404	; ff_h264_idct_add16intra_mmx(uint8_t dst, const int block_offset,
402	405	; DCTELEM block, int stride, const uint8_t nnzc[68])
403		−cglobal h264_idct_add16intra_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
	406	+cglobal h264_idct_add16intra_8, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
404	407	xor r5, r5
405	408	%ifdef PIC
406	409	lea picregq, [scan8_mem]
@@ -421,10 +424,11 @@ cglobal h264_idct_add16intra_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block · 14 unmodified lines
421	424	jl .nextblock
422	425	REP_RET
423	426
	427	+INIT_MMX mmxext
424	428	; ff_h264_idct_add16intra_mmxext(uint8_t dst, const int block_offset,
425	429	; DCTELEM *block, int stride,
426	430	; const uint8_t nnzc[6*8])
427		−cglobal h264_idct_add16intra_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	431	+cglobal h264_idct_add16intra_8, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
428	432	xor r5, r5
429	433	%ifdef PIC
430	434	lea picregq, [scan8_mem]
@@ -467,7 +471,7 @@ cglobal h264_idct_add16intra_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, b · 36 unmodified lines
467	471	; ff_h264_idct8_add4_mmxext(uint8_t dst, const int block_offset,
468	472	; DCTELEM *block, int stride,
469	473	; const uint8_t nnzc[6*8])
470		−cglobal h264_idct8_add4_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	474	+cglobal h264_idct8_add4_8, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
471	475	%assign pad 128+4-(stack_offset&7)
472	476	SUB rsp, pad
473	477
@@ -524,10 +528,10 @@ cglobal h264_idct8_add4_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, · 50 unmodified lines
524	528	ADD rsp, pad
525	529	RET
526	530
527		−INIT_XMM
	531	+INIT_XMM sse2
528	532	; ff_h264_idct8_add4_sse2(uint8_t dst, const int block_offset,
529	533	; DCTELEM block, int stride, const uint8_t nnzc[68])
530		−cglobal h264_idct8_add4_8_sse2, 5, 8 + npicregs, 10, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	534	+cglobal h264_idct8_add4_8, 5, 8 + npicregs, 10, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
531	535	xor r5, r5
532	536	%ifdef PIC
533	537	lea picregq, [scan8_mem]
@@ -542,7 +546,7 @@ cglobal h264_idct8_add4_8_sse2, 5, 8 + npicregs, 10, dst1, block_offset, block, · 8 unmodified lines
542	546	movsx r6, word [r2]
543	547	test r6, r6
544	548	jz .no_dc
545		−INIT_MMX
	549	+INIT_MMX cpuname
546	550	DC_ADD_MMXEXT_INIT r2, r3, r6
547	551	%if ARCH_X86_64 == 0
548	552	%define dst2q r1
@@ -562,7 +566,7 @@ INIT_MMX · 13 unmodified lines
562	566	jl .nextblock
563	567	REP_RET
564	568	.no_dc:
565		−INIT_XMM
	569	+INIT_XMM cpuname
566	570	mov dst2d, dword [r1+r5*4]
567	571	add dst2q, r0
568	572	IDCT8_ADD_SSE dst2q, r2, r3, r6
@@ -576,7 +580,7 @@ INIT_XMM · 7 unmodified lines
576	580	jl .nextblock
577	581	REP_RET
578	582
579		−INIT_MMX
	583	+INIT_MMX mmx
580	584	h264_idct_add8_mmx_plane:
581	585	.nextblock:
582	586	movzx r6, byte [scan8+r5]
@@ -602,7 +606,7 @@ h264_idct_add8_mmx_plane: · 19 unmodified lines
602	606
603	607	; ff_h264_idct_add8_mmx(uint8_t *dest, const int block_offset,
604	608	; DCTELEM block, int stride, const uint8_t nnzc[68])
605		−cglobal h264_idct_add8_8_mmx, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	609	+cglobal h264_idct_add8_8, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
606	610	mov r5, 16
607	611	add r2, 512
608	612	%ifdef PIC
@@ -663,9 +667,10 @@ h264_idct_add8_mmxext_plane: · 54 unmodified lines
663	667	jnz .nextblock
664	668	rep ret
665	669
	670	+INIT_MMX mmxext
666	671	; ff_h264_idct_add8_mmxext(uint8_t *dest, const int block_offset,
667	672	; DCTELEM block, int stride, const uint8_t nnzc[68])
668		−cglobal h264_idct_add8_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
	673	+cglobal h264_idct_add8_8, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
669	674	mov r5, 16
670	675	add r2, 512
671	676	%if ARCH_X86_64
@@ -685,7 +690,6 @@ cglobal h264_idct_add8_8_mmxext, 5, 8 + npicregs, 0, dst1, block_offset, block, · 13 unmodified lines
685	690	call h264_idct_add8_mmxext_plane
686	691	RET
687	692
688		−INIT_MMX
689	693	; r0 = uint8_t dst, r2 = int16_t block, r3 = int stride, r6=clobbered
690	694	h264_idct_dc_add8_mmxext:
691	695	movd m0, [r2 ] ; 0 0 X D
@@ -703,7 +707,7 @@ h264_idct_dc_add8_mmxext: · 11 unmodified lines
703	707	ret
704	708
705	709	ALIGN 16
706		−INIT_XMM
	710	+INIT_XMM sse2
707	711	; r0 = uint8_t dst (clobbered), r2 = int16_t block, r3 = int stride
708	712	h264_add8x4_idct_sse2:
709	713	movq m0, [r2+ 0]
@@ -743,7 +747,7 @@ h264_add8x4_idct_sse2: · 33 unmodified lines
743	747
744	748	; ff_h264_idct_add16_sse2(uint8_t dst, const int block_offset,
745	749	; DCTELEM block, int stride, const uint8_t nnzc[68])
746		−cglobal h264_idct_add16_8_sse2, 5, 5 + ARCH_X86_64, 8
	750	+cglobal h264_idct_add16_8, 5, 5 + ARCH_X86_64, 8
747	751	%if ARCH_X86_64
748	752	mov r5, r0
749	753	%endif
@@ -790,7 +794,7 @@ cglobal h264_idct_add16_8_sse2, 5, 5 + ARCH_X86_64, 8 · 40 unmodified lines
790	794
791	795	; ff_h264_idct_add16intra_sse2(uint8_t dst, const int block_offset,
792	796	; DCTELEM block, int stride, const uint8_t nnzc[68])
793		−cglobal h264_idct_add16intra_8_sse2, 5, 7 + ARCH_X86_64, 8
	797	+cglobal h264_idct_add16intra_8, 5, 7 + ARCH_X86_64, 8
794	798	%if ARCH_X86_64
795	799	mov r7, r0
796	800	%endif
@@ -841,7 +845,7 @@ cglobal h264_idct_add16intra_8_sse2, 5, 7 + ARCH_X86_64, 8 · 44 unmodified lines
841	845
842	846	; ff_h264_idct_add8_sse2(uint8_t *dest, const int block_offset,
843	847	; DCTELEM block, int stride, const uint8_t nnzc[68])
844		−cglobal h264_idct_add8_8_sse2, 5, 7 + ARCH_X86_64, 8
	848	+cglobal h264_idct_add8_8, 5, 7 + ARCH_X86_64, 8
845	849	add r2, 512
846	850	%if ARCH_X86_64
847	851	mov r7, r0
@@ -887,29 +891,8 @@ cglobal h264_idct_add8_8_sse2, 5, 7 + ARCH_X86_64, 8 · 39 unmodified lines
887	891	packssdw %2, m5
888	892	%endmacro
889	893
890		−%macro STORE_WORDS_MMX 5
891		− movd t0d, %1
892		− psrlq %1, 32
893		− movd t1d, %1
894		− mov [t2+%2*32], t0w
895		− mov [t2+%4*32], t1w
896		− shr t0d, 16
897		− shr t1d, 16
898		− mov [t2+%3*32], t0w
899		− mov [t2+%5*32], t1w
900		−%endmacro
901		−
902		−%macro DEQUANT_STORE_MMX 1
903		− DEQUANT_MMX m0, m1, %1
904		− STORE_WORDS_MMX m0, 0, 1, 4, 5
905		− STORE_WORDS_MMX m1, 2, 3, 6, 7
906		−
907		− DEQUANT_MMX m2, m3, %1
908		− STORE_WORDS_MMX m2, 8, 9, 12, 13
909		− STORE_WORDS_MMX m3, 10, 11, 14, 15
910		−%endmacro
911		−
912		−%macro STORE_WORDS_SSE 9
	894	+%macro STORE_WORDS 5-9
	895	+%if cpuflag(sse)
913	896	movd t0d, %1
914	897	psrldq %1, 4
915	898	movd t1d, %1
@@ -929,9 +912,21 @@ cglobal h264_idct_add8_8_sse2, 5, 7 + ARCH_X86_64, 8 · 13 unmodified lines
929	912	shr t1d, 16
930	913	mov [t2+%7*32], t0w
931	914	mov [t2+%9*32], t1w
	915	+%else
	916	+ movd t0d, %1
	917	+ psrlq %1, 32
	918	+ movd t1d, %1
	919	+ mov [t2+%2*32], t0w
	920	+ mov [t2+%4*32], t1w
	921	+ shr t0d, 16
	922	+ shr t1d, 16
	923	+ mov [t2+%3*32], t0w
	924	+ mov [t2+%5*32], t1w
	925	+%endif
932	926	%endmacro
933	927
934		−%macro DEQUANT_STORE_SSE2 1
	928	+%macro DEQUANT_STORE 1
	929	+%if cpuflag(sse2)
935	930	movd xmm4, t3d
936	931	movq xmm5, [pw_1]
937	932	pshufd xmm4, xmm4, 0
@@ -953,15 +948,24 @@ cglobal h264_idct_add8_8_sse2, 5, 7 + ARCH_X86_64, 8 · 15 unmodified lines
953	948	psrad xmm3, %1
954	949	packssdw xmm0, xmm1
955	950	packssdw xmm2, xmm3
956		− STORE_WORDS_SSE xmm0, 0, 1, 4, 5, 2, 3, 6, 7
957		− STORE_WORDS_SSE xmm2, 8, 9, 12, 13, 10, 11, 14, 15
	951	+ STORE_WORDS xmm0, 0, 1, 4, 5, 2, 3, 6, 7
	952	+ STORE_WORDS xmm2, 8, 9, 12, 13, 10, 11, 14, 15
	953	+%else
	954	+ DEQUANT_MMX m0, m1, %1
	955	+ STORE_WORDS m0, 0, 1, 4, 5
	956	+ STORE_WORDS m1, 2, 3, 6, 7
	957	+
	958	+ DEQUANT_MMX m2, m3, %1
	959	+ STORE_WORDS m2, 8, 9, 12, 13
	960	+ STORE_WORDS m3, 10, 11, 14, 15
	961	+%endif
958	962	%endmacro
959	963
960		−%macro IDCT_DC_DEQUANT 2
961		−cglobal h264_luma_dc_dequant_idct_%1, 3,4,%2
	964	+%macro IDCT_DC_DEQUANT 1
	965	+cglobal h264_luma_dc_dequant_idct, 3, 4, %1
962	966	; manually spill XMM registers for Win64 because
963	967	; the code here is initialized with INIT_MMX
964		− WIN64_SPILL_XMM %2
	968	+ WIN64_SPILL_XMM %1
965	969	movq m3, [r1+24]
966	970	movq m2, [r1+16]
967	971	movq m1, [r1+ 8]
@@ -984,11 +988,7 @@ cglobal h264_luma_dc_dequant_idct_%1, 3,4,%2 · 16 unmodified lines
984	988	cmp t3d, 32767
985	989	jg .big_qmul
986	990	add t3d, 128 << 16
987		−%ifidn %1,mmx
988		− DEQUANT_STORE_MMX 8
989		−%else
990		− DEQUANT_STORE_SSE2 8
991		−%endif
	991	+ DEQUANT_STORE 8
992	992	RET
993	993	.big_qmul:
994	994	bsr t0d, t3d
@@ -999,16 +999,17 @@ cglobal h264_luma_dc_dequant_idct_%1, 3,4,%2 · 4 unmodified lines
999	999	inc t1d
1000	1000	shr t3d, t0b
1001	1001	sub t1d, t0d
1002		−%ifidn %1,mmx
1003		− movd m6, t1d
1004		− DEQUANT_STORE_MMX m6
1005		−%else
	1002	+%if cpuflag(sse2)
1006	1003	movd xmm6, t1d
1007		− DEQUANT_STORE_SSE2 xmm6
	1004	+ DEQUANT_STORE xmm6
	1005	+%else
	1006	+ movd m6, t1d
	1007	+ DEQUANT_STORE m6
1008	1008	%endif
1009	1009	RET
1010	1010	%endmacro
1011	1011
1012		−INIT_MMX
1013		−IDCT_DC_DEQUANT mmx, 0
1014		−IDCT_DC_DEQUANT sse2, 7
	1012	+INIT_MMX mmx
	1013	+IDCT_DC_DEQUANT 0
	1014	+INIT_MMX sse2
	1015	+IDCT_DC_DEQUANT 7

x86: h264_idct: port to cpuflags

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