#!/usr/bin/pythonfrom __future__ import print_functionfrom unicorn import *from unicorn.x86_const import *from unicorn.arm64_const import *from unicorn.arm_const import *from keystone import *import capstonefrom scareconfig import *import random def printSplash():    print("""\┌──────┐┌──────┐┌──────┐┌──────┐┌──────┐└──────┐│       ┌──────││       │      ││      ││       │      ││       │──────┘└──────┘└──────┘└──────┘└       └──────┘Simple Configurable Asm REPL && Emulator                 [v0.3.∞]    """) helpfile = """scare Help / /? /help                             -- Open help menu/x /exit /q /quit                      -- Quit the program /back n                                -- Go back n number of lines/dis {0xaddress|$register} NUM         -- Disassemble NUM bytes from 0xaddress or $register/export FILETYPE FILENAME              -- Export machine code as FILETYPE to the FILENAME                                          FILETYPE:                                          - bin                                          - elf64                                          - pe32/info                                  -- Info about the emulator state/l /list [TYPE]                        -- List the current program                                          TYPE:                                          - plan9/load file.asm                         -- Load listing from file.asm (overwrites current program)/read {0xaddress|$register} NUM [FILE] -- Read NUM bytes from 0xaddress or $register/write {0xaddress|$register} hexdata   -- Write bytes to 0xaddress or $register/write {0xaddress|$register} ./file    -- Write file data to 0xaddress or $register                                          Note: path *has* to start with a dot/regs                                  -- Print register state/get register [register... ]           -- Print register state/set register value                    -- Set a register/reset                                 -- Reset the emulator to a clean state/run                                   -- Run the current program/save file.asm                         -- Save assembly output to file.asm [[: Config Commands :]] (Use /c or /config)NOTE: Run /reset if you are changing emu/* options, otherwise the emulator may not start! /c               -- Print all config options/c emu/arch      -- Print Arch Value/c emu/arch x64  -- Set Arch to x64/c x86/xmm 1     -- Enable x86/xmm/c x86/ymm 1     -- Enable x86/ymm/c arm64/neon 1  -- Enable arm64/neon"""  ### Register Output Stuff ######################################################rNames = {    "arm32" : {        "r0" : UC_ARM_REG_R0,        "r1" : UC_ARM_REG_R1,        "r2" : UC_ARM_REG_R2,        "r3" : UC_ARM_REG_R3,        "r4" : UC_ARM_REG_R4,        "r5" : UC_ARM_REG_R5,        "r6" : UC_ARM_REG_R6,        "r7" : UC_ARM_REG_R7,        "r8" : UC_ARM_REG_R8,        "r9" : UC_ARM_REG_R9,        "r10": UC_ARM_REG_R10,        "r11": UC_ARM_REG_R11,        "r12": UC_ARM_REG_R12,        "sp":  UC_ARM_REG_SP,        "lr":  UC_ARM_REG_LR,        "pc":  UC_ARM_REG_PC,        "cpsr":  UC_ARM_REG_CPSR,    },    "arm64" : {        "x0" : UC_ARM64_REG_X0,        "x1" : UC_ARM64_REG_X1,        "x2" : UC_ARM64_REG_X2,        "x3" : UC_ARM64_REG_X3,        "x4" : UC_ARM64_REG_X4,        "x5" : UC_ARM64_REG_X5,        "x6" : UC_ARM64_REG_X6,        "x7" : UC_ARM64_REG_X7,        "x8" : UC_ARM64_REG_X8,        "x9" : UC_ARM64_REG_X9,        "x10": UC_ARM64_REG_X10,        "x11": UC_ARM64_REG_X11,        "x12": UC_ARM64_REG_X12,        "x13": UC_ARM64_REG_X13,        "x14": UC_ARM64_REG_X14,        "x15": UC_ARM64_REG_X15,        "x16": UC_ARM64_REG_X16,        "x17": UC_ARM64_REG_X17,        "x18": UC_ARM64_REG_X18,        "x19": UC_ARM64_REG_X19,        "x20": UC_ARM64_REG_X20,        "x21": UC_ARM64_REG_X21,        "x22": UC_ARM64_REG_X22,        "x23": UC_ARM64_REG_X23,        "x24": UC_ARM64_REG_X24,        "x25": UC_ARM64_REG_X25,        "x26": UC_ARM64_REG_X26,        "x27": UC_ARM64_REG_X27,        "x28": UC_ARM64_REG_X28,        "x29": UC_ARM64_REG_X29,        "x30": UC_ARM64_REG_X30,        "sp":  UC_ARM64_REG_SP,        "pc":  UC_ARM64_REG_PC,        "cpsr":  UC_ARM_REG_CPSR,    },    "neon": {        "v0" : UC_ARM64_REG_V0,        "v1" : UC_ARM64_REG_V1,        "v2" : UC_ARM64_REG_V2,        "v3" : UC_ARM64_REG_V3,        "v4" : UC_ARM64_REG_V4,        "v5" : UC_ARM64_REG_V5,        "v6" : UC_ARM64_REG_V6,        "v7" : UC_ARM64_REG_V7,        "v8" : UC_ARM64_REG_V8,        "v9" : UC_ARM64_REG_V9,        "v10": UC_ARM64_REG_V10,        "v11": UC_ARM64_REG_V11,        "v12": UC_ARM64_REG_V12,        "v13": UC_ARM64_REG_V13,        "v14": UC_ARM64_REG_V14,        "v15": UC_ARM64_REG_V15,        "v16": UC_ARM64_REG_V16,        "v17": UC_ARM64_REG_V17,        "v18": UC_ARM64_REG_V18,        "v19": UC_ARM64_REG_V19,        "v20": UC_ARM64_REG_V20,        "v21": UC_ARM64_REG_V21,        "v22": UC_ARM64_REG_V22,        "v23": UC_ARM64_REG_V23,        "v24": UC_ARM64_REG_V24,        "v25": UC_ARM64_REG_V25,        "v26": UC_ARM64_REG_V26,        "v27": UC_ARM64_REG_V27,        "v28": UC_ARM64_REG_V28,        "v29": UC_ARM64_REG_V29,        "v30": UC_ARM64_REG_V30,        "v31": UC_ARM64_REG_V31,    },    "x86": {        "eax": UC_X86_REG_EAX,        "ebx": UC_X86_REG_EBX,        "ecx": UC_X86_REG_ECX,        "edx": UC_X86_REG_EDX,        "esi": UC_X86_REG_ESI,        "edi": UC_X86_REG_EDI,        "eip": UC_X86_REG_EIP,        "esp": UC_X86_REG_ESP,        "ebp": UC_X86_REG_EBP,        "eflags": UC_X86_REG_EFLAGS,    },    "x64": {        "rax": UC_X86_REG_RAX,        "rbx": UC_X86_REG_RBX,        "rcx": UC_X86_REG_RCX,        "rdx": UC_X86_REG_RDX,        "rsi": UC_X86_REG_RSI,        "rdi": UC_X86_REG_RDI,        "rip": UC_X86_REG_RIP,        "rsp": UC_X86_REG_RSP,        "rbp": UC_X86_REG_RBP,        "r8":  UC_X86_REG_R8,        "r9":  UC_X86_REG_R9,        "r10": UC_X86_REG_R10,        "r11": UC_X86_REG_R11,        "r12": UC_X86_REG_R12,        "r13": UC_X86_REG_R13,        "r14": UC_X86_REG_R14,        "r15": UC_X86_REG_R15,        "rflags": UC_X86_REG_EFLAGS,    },    "xmm": {        "xmm0":  UC_X86_REG_XMM0,        "xmm1":  UC_X86_REG_XMM1,        "xmm2":  UC_X86_REG_XMM2,        "xmm3":  UC_X86_REG_XMM3,        "xmm4":  UC_X86_REG_XMM4,        "xmm5":  UC_X86_REG_XMM5,        "xmm6":  UC_X86_REG_XMM6,        "xmm7":  UC_X86_REG_XMM7,        "xmm8":  UC_X86_REG_XMM8,        "xmm9":  UC_X86_REG_XMM9,        "xmm10": UC_X86_REG_XMM10,        "xmm11": UC_X86_REG_XMM11,        "xmm12": UC_X86_REG_XMM12,        "xmm13": UC_X86_REG_XMM13,        "xmm14": UC_X86_REG_XMM14,        "xmm15": UC_X86_REG_XMM15,        "xmm16": UC_X86_REG_XMM16,        "xmm17": UC_X86_REG_XMM17,        "xmm18": UC_X86_REG_XMM18,        "xmm19": UC_X86_REG_XMM19,        "xmm20": UC_X86_REG_XMM20,        "xmm21": UC_X86_REG_XMM21,        "xmm22": UC_X86_REG_XMM22,        "xmm23": UC_X86_REG_XMM23,        "xmm24": UC_X86_REG_XMM24,        "xmm25": UC_X86_REG_XMM25,        "xmm26": UC_X86_REG_XMM26,        "xmm27": UC_X86_REG_XMM27,        "xmm28": UC_X86_REG_XMM28,        "xmm29": UC_X86_REG_XMM29,        "xmm30": UC_X86_REG_XMM30,        "xmm31": UC_X86_REG_XMM31,    },    "ymm": {        "ymm0":  UC_X86_REG_YMM0,        "ymm1":  UC_X86_REG_YMM1,        "ymm2":  UC_X86_REG_YMM2,        "ymm3":  UC_X86_REG_YMM3,        "ymm4":  UC_X86_REG_YMM4,        "ymm5":  UC_X86_REG_YMM5,        "ymm6":  UC_X86_REG_YMM6,        "ymm7":  UC_X86_REG_YMM7,        "ymm8":  UC_X86_REG_YMM8,        "ymm9":  UC_X86_REG_YMM9,        "ymm10": UC_X86_REG_YMM10,        "ymm11": UC_X86_REG_YMM11,        "ymm12": UC_X86_REG_YMM12,        "ymm13": UC_X86_REG_YMM13,        "ymm14": UC_X86_REG_YMM14,        "ymm15": UC_X86_REG_YMM15,        "ymm16": UC_X86_REG_YMM16,        "ymm17": UC_X86_REG_YMM17,        "ymm18": UC_X86_REG_YMM18,        "ymm19": UC_X86_REG_YMM19,        "ymm20": UC_X86_REG_YMM20,        "ymm21": UC_X86_REG_YMM21,        "ymm22": UC_X86_REG_YMM22,        "ymm23": UC_X86_REG_YMM23,        "ymm24": UC_X86_REG_YMM24,        "ymm25": UC_X86_REG_YMM25,        "ymm26": UC_X86_REG_YMM26,        "ymm27": UC_X86_REG_YMM27,        "ymm28": UC_X86_REG_YMM28,        "ymm29": UC_X86_REG_YMM29,        "ymm30": UC_X86_REG_YMM30,        "ymm31": UC_X86_REG_YMM31,    },} # regFmt - Format register for output# mu = Emulator Object# regType = Type of register for custom styling#     0 - General Purpose#     1 - Instruction Pointer#     2 - Stack Pointer# regSize = The size of the register in bits# regName = The emulator specific constant, resolved using rNames dictdef regFmt(mu, regType, regSize, regName):    outRegVal = mu.reg_read(regName)    if regType == 0:        outRegColor = cGReg if outRegVal > 0 else cZero    elif regType == 1:        outRegColor = cIP    elif regType == 2:        outRegColor = cSPtr    else:        print(f"Unknown Register Type {regType}")        return    if regSize == 8:        outRegValFmt = f"{outRegVal:02x}"    elif regSize == 16:        outRegValFmt = f"{outRegVal:04x}"    elif regSize == 32:        outRegValFmt = f"{outRegVal:08x}"    elif regSize == 64:        outRegValFmt = f"{outRegVal:016x}"    elif regSize == 128:        outRegValFmt = f"{outRegVal:032x}"    elif regSize == 256:        outRegValFmt = f"{outRegVal:064x}"    else:        print("Unknown Register Size!")        return    outRegText = f"{outRegColor}{outRegValFmt}{cEnd}"    return outRegText def printRegs_arm32(mu, sConfig):    print(f"{cRegN}  r0: {regFmt(mu,0,32,rNames['arm32']['r0' ])} {cRegN} r1: {regFmt(mu,0,32,rNames['arm32']['r1' ])} {cRegN} r2: {regFmt(mu,0,32,rNames['arm32']['r2' ])} {cRegN} r3: {regFmt(mu,0,32,rNames['arm32']['r3' ])}")    print(f"{cRegN}  r4: {regFmt(mu,0,32,rNames['arm32']['r4' ])} {cRegN} r5: {regFmt(mu,0,32,rNames['arm32']['r5' ])} {cRegN} r6: {regFmt(mu,0,32,rNames['arm32']['r6' ])} {cRegN} r7: {regFmt(mu,0,32,rNames['arm32']['r7' ])} ")    print(f"{cRegN}  r8: {regFmt(mu,0,32,rNames['arm32']['r8' ])} {cRegN} r9: {regFmt(mu,0,32,rNames['arm32']['r9' ])} {cRegN}r10: {regFmt(mu,0,32,rNames['arm32']['r10'])} {cRegN}r11: {regFmt(mu,0,32,rNames['arm32']['r11'])}")    print(f"{cRegN} r12: {regFmt(mu,0,32,rNames['arm32']['r12'])} {cRegN} sp: {regFmt(mu,2,32,rNames['arm32']['sp' ])} {cRegN} lr: {regFmt(mu,0,32,rNames['arm32']['lr' ])} {cRegN} pc: {regFmt(mu,1,32,rNames['arm32']['pc' ])} ")    print(f"{cRegN}cpsr: {regFmt(mu,0,32,rNames['arm32']['cpsr'] )} ")    print(cEnd,end="") def printRegs_arm64(mu, sConfig):    print(f"{cRegN} x0: {regFmt(mu,0,64,rNames['arm64']['x0' ])} {cRegN}  x1: {regFmt(mu,0,64,rNames['arm64']['x1' ])} {cRegN}  x2: {regFmt(mu,0,64,rNames['arm64']['x2' ])} {cRegN}  x3: {regFmt(mu,0,64,rNames['arm64']['x3' ])}")    print(f"{cRegN} x4: {regFmt(mu,0,64,rNames['arm64']['x4' ])} {cRegN}  x5: {regFmt(mu,0,64,rNames['arm64']['x5' ])} {cRegN}  x6: {regFmt(mu,0,64,rNames['arm64']['x6' ])} {cRegN}  x7: {regFmt(mu,0,64,rNames['arm64']['x7' ])}")    print(f"{cRegN} x8: {regFmt(mu,0,64,rNames['arm64']['x8' ])} {cRegN}  x9: {regFmt(mu,0,64,rNames['arm64']['x9' ])} {cRegN} x10: {regFmt(mu,0,64,rNames['arm64']['x10'])} {cRegN} x11: {regFmt(mu,0,64,rNames['arm64']['x11'])}")    print(f"{cRegN}x12: {regFmt(mu,0,64,rNames['arm64']['x12'])} {cRegN} x13: {regFmt(mu,0,64,rNames['arm64']['x13'])} {cRegN} x14: {regFmt(mu,0,64,rNames['arm64']['x14'])} {cRegN} x15: {regFmt(mu,0,64,rNames['arm64']['x15'])}")    print(f"{cRegN}x16: {regFmt(mu,0,64,rNames['arm64']['x16'])} {cRegN} x17: {regFmt(mu,0,64,rNames['arm64']['x17'])} {cRegN} x18: {regFmt(mu,0,64,rNames['arm64']['x18'])} {cRegN} x19: {regFmt(mu,0,64,rNames['arm64']['x19'])}")    print(f"{cRegN}x20: {regFmt(mu,0,64,rNames['arm64']['x20'])} {cRegN} x21: {regFmt(mu,0,64,rNames['arm64']['x21'])} {cRegN} x22: {regFmt(mu,0,64,rNames['arm64']['x22'])} {cRegN} x23: {regFmt(mu,0,64,rNames['arm64']['x23'])}")    print(f"{cRegN}x24: {regFmt(mu,0,64,rNames['arm64']['x24'])} {cRegN} x25: {regFmt(mu,0,64,rNames['arm64']['x25'])} {cRegN} x26: {regFmt(mu,0,64,rNames['arm64']['x26'])} {cRegN} x27: {regFmt(mu,0,64,rNames['arm64']['x27'])}")    print(f"{cRegN}x28: {regFmt(mu,0,64,rNames['arm64']['x28'])} {cRegN} x29: {regFmt(mu,0,64,rNames['arm64']['x29'])} {cRegN} x30: {regFmt(mu,0,64,rNames['arm64']['x30'])} {cRegN}  sp: {regFmt(mu,2,64,rNames['arm64']['sp'] )}")    print(f"{cRegN} pc: {regFmt(mu,1,64,rNames['arm64']['pc'] )} {cRegN}cpsr: {regFmt(mu,0,64,rNames['arm64']['cpsr'])}")    print(cEnd,end="")    if sConfig["arm64/neon"]:        printRegs_NEON(mu, sConfig) def printRegs_NEON(mu, sConfig):    print(f"{cRegN} v0: {regFmt(mu,0,128,rNames['neon']['v0'] )} {cRegN}v16: {regFmt(mu,0,128,rNames['neon']['v16'])}")    print(f"{cRegN} v1: {regFmt(mu,0,128,rNames['neon']['v1'] )} {cRegN}v17: {regFmt(mu,0,128,rNames['neon']['v17'])}")    print(f"{cRegN} v2: {regFmt(mu,0,128,rNames['neon']['v2'] )} {cRegN}v18: {regFmt(mu,0,128,rNames['neon']['v18'])}")    print(f"{cRegN} v3: {regFmt(mu,0,128,rNames['neon']['v3'] )} {cRegN}v19: {regFmt(mu,0,128,rNames['neon']['v19'])}")    print(f"{cRegN} v4: {regFmt(mu,0,128,rNames['neon']['v4'] )} {cRegN}v20: {regFmt(mu,0,128,rNames['neon']['v20'])}")    print(f"{cRegN} v5: {regFmt(mu,0,128,rNames['neon']['v5'] )} {cRegN}v21: {regFmt(mu,0,128,rNames['neon']['v21'])}")    print(f"{cRegN} v6: {regFmt(mu,0,128,rNames['neon']['v6'] )} {cRegN}v22: {regFmt(mu,0,128,rNames['neon']['v22'])}")    print(f"{cRegN} v7: {regFmt(mu,0,128,rNames['neon']['v7'] )} {cRegN}v23: {regFmt(mu,0,128,rNames['neon']['v23'])}")    print(f"{cRegN} v8: {regFmt(mu,0,128,rNames['neon']['v8'] )} {cRegN}v24: {regFmt(mu,0,128,rNames['neon']['v24'])}")    print(f"{cRegN} v9: {regFmt(mu,0,128,rNames['neon']['v9'] )} {cRegN}v25: {regFmt(mu,0,128,rNames['neon']['v25'])}")    print(f"{cRegN}v10: {regFmt(mu,0,128,rNames['neon']['v10'])} {cRegN}v26: {regFmt(mu,0,128,rNames['neon']['v26'])}")    print(f"{cRegN}v11: {regFmt(mu,0,128,rNames['neon']['v11'])} {cRegN}v27: {regFmt(mu,0,128,rNames['neon']['v27'])}")    print(f"{cRegN}v12: {regFmt(mu,0,128,rNames['neon']['v12'])} {cRegN}v28: {regFmt(mu,0,128,rNames['neon']['v28'])}")    print(f"{cRegN}v13: {regFmt(mu,0,128,rNames['neon']['v13'])} {cRegN}v29: {regFmt(mu,0,128,rNames['neon']['v29'])}")    print(f"{cRegN}v14: {regFmt(mu,0,128,rNames['neon']['v14'])} {cRegN}v30: {regFmt(mu,0,128,rNames['neon']['v30'])}")    print(f"{cRegN}v15: {regFmt(mu,0,128,rNames['neon']['v15'])} {cRegN}v31: {regFmt(mu,0,128,rNames['neon']['v31'])}") def printRegs_x86(mu, sConfig):    print(f"{cRegN}eax: {regFmt(mu,0,32,rNames['x86']['eax'])}")    print(f"{cRegN}ecx: {regFmt(mu,0,32,rNames['x86']['ecx'])}")    print(f"{cRegN}edx: {regFmt(mu,0,32,rNames['x86']['edx'])}")    print(f"{cRegN}ebx: {regFmt(mu,0,32,rNames['x86']['ebx'])}")    print(f"{cRegN}esp: {regFmt(mu,2,32,rNames['x86']['esp'])}")    print(f"{cRegN}ebp: {regFmt(mu,0,32,rNames['x86']['ebp'])}")    print(f"{cRegN}esi: {regFmt(mu,0,32,rNames['x86']['esi'])}")    print(f"{cRegN}edi: {regFmt(mu,0,32,rNames['x86']['edi'])}")    print(f"{cRegN}eip: {regFmt(mu,1,32,rNames['x86']['eip'])}")    print(f"{cRegN}efl: {regFmt(mu,0,32,rNames['x86']['eflags'])}")    print(cEnd,end="")    if sConfig["x86/xmm"]:        printRegs_XMM(mu, sConfig) def printRegs_XMM(mu, sConfig):    print(f"{cRegN} xmm0: {regFmt(mu,0,128,rNames['xmm']['xmm0'] )} {cRegN} xmm8: {regFmt(mu,0,128,rNames['xmm']['xmm8'] )}")    print(f"{cRegN} xmm1: {regFmt(mu,0,128,rNames['xmm']['xmm1'] )} {cRegN} xmm9: {regFmt(mu,0,128,rNames['xmm']['xmm9'])}")    print(f"{cRegN} xmm2: {regFmt(mu,0,128,rNames['xmm']['xmm2'] )} {cRegN}xmm10: {regFmt(mu,0,128,rNames['xmm']['xmm10'])}")    print(f"{cRegN} xmm3: {regFmt(mu,0,128,rNames['xmm']['xmm3'] )} {cRegN}xmm11: {regFmt(mu,0,128,rNames['xmm']['xmm11'])}")    print(f"{cRegN} xmm4: {regFmt(mu,0,128,rNames['xmm']['xmm4'] )} {cRegN}xmm12: {regFmt(mu,0,128,rNames['xmm']['xmm12'])}")    print(f"{cRegN} xmm5: {regFmt(mu,0,128,rNames['xmm']['xmm5'] )} {cRegN}xmm13: {regFmt(mu,0,128,rNames['xmm']['xmm13'])}")    print(f"{cRegN} xmm6: {regFmt(mu,0,128,rNames['xmm']['xmm6'] )} {cRegN}xmm14: {regFmt(mu,0,128,rNames['xmm']['xmm14'])}")    print(f"{cRegN} xmm7: {regFmt(mu,0,128,rNames['xmm']['xmm7'] )} {cRegN}xmm15: {regFmt(mu,0,128,rNames['xmm']['xmm15'])}") def printRegs_YMM(mu, sConfig):    print(f"{cRegN} ymm0: {regFmt(mu,0,256,rNames['ymm']['ymm0'] )} {cRegN} ymm8: {regFmt(mu,0,256,rNames['ymm']['ymm8'] )}")    print(f"{cRegN} ymm1: {regFmt(mu,0,256,rNames['ymm']['ymm1'] )} {cRegN} ymm9: {regFmt(mu,0,256,rNames['ymm']['ymm9'])}")    print(f"{cRegN} ymm2: {regFmt(mu,0,256,rNames['ymm']['ymm2'] )} {cRegN}ymm10: {regFmt(mu,0,256,rNames['ymm']['ymm10'])}")    print(f"{cRegN} ymm3: {regFmt(mu,0,256,rNames['ymm']['ymm3'] )} {cRegN}ymm11: {regFmt(mu,0,256,rNames['ymm']['ymm11'])}")    print(f"{cRegN} ymm4: {regFmt(mu,0,256,rNames['ymm']['ymm4'] )} {cRegN}ymm12: {regFmt(mu,0,256,rNames['ymm']['ymm12'])}")    print(f"{cRegN} ymm5: {regFmt(mu,0,256,rNames['ymm']['ymm5'] )} {cRegN}ymm13: {regFmt(mu,0,256,rNames['ymm']['ymm13'])}")    print(f"{cRegN} ymm6: {regFmt(mu,0,256,rNames['ymm']['ymm6'] )} {cRegN}ymm14: {regFmt(mu,0,256,rNames['ymm']['ymm14'])}")    print(f"{cRegN} ymm7: {regFmt(mu,0,256,rNames['ymm']['ymm7'] )} {cRegN}ymm15: {regFmt(mu,0,256,rNames['ymm']['ymm15'])}") def printRegs_x64(mu, sConfig):    print(f"{cRegN}rax: {regFmt(mu,0,64,rNames['x64']['rax'])} {cRegN}rip: {regFmt(mu,1,64,rNames['x64']['rip'])} {cRegN}r11: {regFmt(mu,0,64,rNames['x64']['r11'])}")    print(f"{cRegN}rbx: {regFmt(mu,0,64,rNames['x64']['rbx'])} {cRegN}rsp: {regFmt(mu,2,64,rNames['x64']['rsp'])} {cRegN}r12: {regFmt(mu,0,64,rNames['x64']['r12'])}")    print(f"{cRegN}rcx: {regFmt(mu,0,64,rNames['x64']['rcx'])} {cRegN}rbp: {regFmt(mu,0,64,rNames['x64']['rbp'])} {cRegN}r13: {regFmt(mu,0,64,rNames['x64']['r13'])}")    print(f"{cRegN}rdx: {regFmt(mu,0,64,rNames['x64']['rdx'])} {cRegN} r8: {regFmt(mu,0,64,rNames['x64']['r8'] )} {cRegN}r14: {regFmt(mu,0,64,rNames['x64']['r14'])}")    print(f"{cRegN}rsi: {regFmt(mu,0,64,rNames['x64']['rsi'])} {cRegN} r9: {regFmt(mu,0,64,rNames['x64']['r9'] )} {cRegN}r15: {regFmt(mu,0,64,rNames['x64']['r15'])}")    print(f"{cRegN}rdi: {regFmt(mu,0,64,rNames['x64']['rdi'])} {cRegN}r10: {regFmt(mu,0,64,rNames['x64']['r10'])} {cRegN}rfl: {regFmt(mu,0,64,rNames['x64']['rflags'])}")    print(cEnd,end="")    if sConfig["x86/xmm"]:        printRegs_XMM(mu, sConfig)    if sConfig["x86/ymm"]:        printRegs_YMM(mu, sConfig) archez = {    "x64": {        "emu": {            "unicorn": {                "arch": UC_ARCH_X86,                "mode": UC_MODE_64,                "stack_reg": UC_X86_REG_RSP,                "ip_reg": UC_X86_REG_RIP,            },        },        "asm": {            "keystone": {                "arch": KS_ARCH_X86,                "mode": KS_MODE_64,            },        },        "dis": {            "capstone": {                "arch": capstone.CS_ARCH_X86,                "mode": capstone.CS_MODE_64,            },        },        "funcs": {            "reg_state": printRegs_x64,        },        "cpus": {            "": None,            "qemu64": UC_CPU_X86_QEMU64,            "phenom": UC_CPU_X86_PHENOM,            "core2duo": UC_CPU_X86_CORE2DUO,            "kvm64": UC_CPU_X86_KVM64,            "qemu32": UC_CPU_X86_QEMU32,            "kvm32": UC_CPU_X86_KVM32,            "coreduo": UC_CPU_X86_COREDUO,            "486": UC_CPU_X86_486,            "pentium": UC_CPU_X86_PENTIUM,            "pentium2": UC_CPU_X86_PENTIUM2,            "pentium3": UC_CPU_X86_PENTIUM3,            "athlon": UC_CPU_X86_ATHLON,            "n270": UC_CPU_X86_N270,            "conroe": UC_CPU_X86_CONROE,            "penryn": UC_CPU_X86_PENRYN,            "nehalem": UC_CPU_X86_NEHALEM,            "westmere": UC_CPU_X86_WESTMERE,            "sandybridge": UC_CPU_X86_SANDYBRIDGE,            "ivybridge": UC_CPU_X86_IVYBRIDGE,            "haswell": UC_CPU_X86_HASWELL,            "broadwell": UC_CPU_X86_BROADWELL,            "skylake_client": UC_CPU_X86_SKYLAKE_CLIENT,            "skylake_server": UC_CPU_X86_SKYLAKE_SERVER,            "cascadelake_server": UC_CPU_X86_CASCADELAKE_SERVER,            "cooperlake": UC_CPU_X86_COOPERLAKE,            "icelake_client": UC_CPU_X86_ICELAKE_CLIENT,            "icelake_server": UC_CPU_X86_ICELAKE_SERVER,            "denverton": UC_CPU_X86_DENVERTON,            "snowridge": UC_CPU_X86_SNOWRIDGE,            "knightsmill": UC_CPU_X86_KNIGHTSMILL,            "opteron_g1": UC_CPU_X86_OPTERON_G1,            "opteron_g2": UC_CPU_X86_OPTERON_G2,            "opteron_g3": UC_CPU_X86_OPTERON_G3,            "opteron_g4": UC_CPU_X86_OPTERON_G4,            "opteron_g5": UC_CPU_X86_OPTERON_G5,            "epyc": UC_CPU_X86_EPYC,            "dhyana": UC_CPU_X86_DHYANA,            "epyc_rome": UC_CPU_X86_EPYC_ROME,        },    },    "x86": {        "emu": {            "unicorn": {                "arch": UC_ARCH_X86,                "mode": UC_MODE_32,                "stack_reg": UC_X86_REG_ESP,                "ip_reg": UC_X86_REG_EIP,            },        },        "asm": {            "keystone": {                "arch": KS_ARCH_X86,                "mode": KS_MODE_32,            },        },        "dis": {            "capstone": {                "arch": capstone.CS_ARCH_X86,                "mode": capstone.CS_MODE_32,            },        },        "funcs": {            "reg_state": printRegs_x86,        },    },    "arm64": {        "emu": {            "unicorn": {                "arch": UC_ARCH_ARM64,                "mode": UC_MODE_ARM,                "stack_reg": UC_ARM64_REG_SP,                "ip_reg": UC_ARM64_REG_PC,            },        },        "asm": {            "keystone": {                "arch": KS_ARCH_ARM64,                "mode": KS_MODE_LITTLE_ENDIAN,            },        },        "dis": {            "capstone": {                "arch": capstone.CS_ARCH_ARM64,                "mode": capstone.CS_MODE_ARM,            },        },        "funcs": {            "reg_state": printRegs_arm64,        },        "cpus": {            "": None,            "a57": UC_CPU_ARM64_A57,            "a53": UC_CPU_ARM64_A53,

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