riscv: Add sar, shr insn

fixes 92_enum_bitfield.

Michael Matz committed 7 years ago

Commit 215bc1a1 parent f64d4601 file · +6 −2Browse files

Unified · Split

     d = ireg(d);
     switch (op) {
     case '%':
-    case TOK_SAR:
-    case TOK_SHR:
     case TOK_PDIV:
     default:
         tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
     case '-':
         o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
         break;
+    case TOK_SAR:
+        o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
+        break;
+    case TOK_SHR:
+        o(0x33 | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
+        break;
     case TOK_SHL:
         o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
         break;

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