Two things: negative constants were rejected (e.g. "add $-15,%eax"). Second the insn order was such that the arithmetic IM8S forms weren't used (always the IM32 ones). Switching them prefers those but requires a fix for size calculation in case the opcodes were OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
Unified · Split
| @@ -355,7 +355,7 @@ static void parse_operand(TCCState *s1, Operand *op) · 354 unmodified lines | |||
| 355 | if (op->e.v == (uint16_t)op->e.v) | 355 | if (op->e.v == (uint16_t)op->e.v) |
| 356 | op->type |= OP_IM16; | 356 | op->type |= OP_IM16; |
| 357 | #ifdef TCC_TARGET_X86_64 | 357 | #ifdef TCC_TARGET_X86_64 |
| 358 | if (op->e.v != (uint32_t)op->e.v) | 358 | if (op->e.v != (int32_t)op->e.v) |
| 359 | op->type = OP_IM64; | 359 | op->type = OP_IM64; |
| 360 | #endif | 360 | #endif |
| 361 | } | 361 | } |
| @@ -551,6 +551,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 189 unmodified lines | |||
| 551 | if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX)) | 551 | if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX)) |
| 552 | continue; | 552 | continue; |
| 553 | s = (opcode - pa->sym) % NBWLX; | 553 | s = (opcode - pa->sym) % NBWLX; |
| 554 | if ((pa->instr_type & OPC_BWLX) == OPC_WLX) | ||
| 555 | s++; | ||
| 554 | } else if (pa->instr_type & OPC_SHIFT) { | 556 | } else if (pa->instr_type & OPC_SHIFT) { |
| 555 | if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX)) | 557 | if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX)) |
| 556 | continue; | 558 | continue; |
| @@ -157,8 +157,8 @@ ALT(DEF_ASM_OP2(lgs, 0x0fb5, 0, OPC_MODRM, OPT_EA, OPT_REG32)) · 156 unmodified lines | |||
| 157 | ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */ | 157 | ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */ |
| 158 | ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) | 158 | ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) |
| 159 | ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLX, OPT_IM, OPT_EAX)) | 159 | ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLX, OPT_IM, OPT_EAX)) |
| 160 | ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_IM, OPT_EA | OPT_REG)) | ||
| 161 | ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLX, OPT_IM8S, OPT_EA | OPT_REG)) | 160 | ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLX, OPT_IM8S, OPT_EA | OPT_REG)) |
| 161 | ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_IM, OPT_EA | OPT_REG)) | ||
| 162 | 162 | ||
| 163 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) | 163 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) |
| 164 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) | 164 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) |
| @@ -156,6 +156,8 @@ movl %ebx, %fs · 155 unmodified lines | |||
| 156 | 156 | ||
| 157 | addl $0x123, %eax | 157 | addl $0x123, %eax |
| 158 | add $0x123, %ebx | 158 | add $0x123, %ebx |
| 159 | add $-16, %ecx | ||
| 160 | add $-0x123, %esi | ||
| 159 | addl $0x123, 0x100 | 161 | addl $0x123, 0x100 |
| 160 | addl $0x123, 0x100(%ebx) | 162 | addl $0x123, 0x100(%ebx) |
| 161 | addl $0x123, 0x100(%ebx,%edx,2) | 163 | addl $0x123, 0x100(%ebx,%edx,2) |
| @@ -216,6 +218,8 @@ add (%ebx), %dl · 54 unmodified lines | |||
| 216 | div %bl | 218 | div %bl |
| 217 | div %ecx, %eax | 219 | div %ecx, %eax |
| 218 | 220 | ||
| 221 | and $15,%bx | ||
| 222 | and $-20,%edx | ||
| 219 | 223 | ||
| 220 | shl %edx | 224 | shl %edx |
| 221 | shl $10, %edx | 225 | shl $10, %edx |
| @@ -690,3 +694,6 @@ ft1: ft2: ft3: ft4: ft5: ft6: ft7: ft8: ft9: · 468 unmodified lines | |||
| 690 | .type ft8,"function" | 694 | .type ft8,"function" |
| 691 | 695 | ||
| 692 | pause | 696 | pause |
| 697 | .rept 6 | ||
| 698 | nop | ||
| 699 | .endr | ||
| @@ -166,8 +166,8 @@ ALT(DEF_ASM_OP2(lgs, 0x0fb5, 0, OPC_MODRM, OPT_EA, OPT_REG32)) · 165 unmodified lines | |||
| 166 | ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */ | 166 | ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */ |
| 167 | ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) | 167 | ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) |
| 168 | ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLX, OPT_IM, OPT_EAX)) | 168 | ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLX, OPT_IM, OPT_EAX)) |
| 169 | ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_IM, OPT_EA | OPT_REG)) | ||
| 170 | ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLX, OPT_IM8S, OPT_EA | OPT_REG)) | 169 | ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLX, OPT_IM8S, OPT_EA | OPT_REG)) |
| 170 | ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLX, OPT_IM, OPT_EA | OPT_REG)) | ||
| 171 | 171 | ||
| 172 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) | 172 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_EA | OPT_REG)) |
| 173 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) | 173 | ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG)) |