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Architecture-specific section alignment

Tests found excessive cache thrashing on x86-64 architectures. The problem was traced to the alignment of sections. This patch sets up an architecture-specific alignment of 512 bytes for x86-64 and 16 bytes for all others. It uses preprocessor directives that, hopefully, make it easy to tweak for other architectures.

David Mertens committed 9 years ago

Commit 5d1bc3f1 parent 04869391 file · +7 −1Browse files

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tccrun.c+7−1
@@ -174,6 +174,12 @@ LIBTCCAPI int tcc_run(TCCState *s1, int argc, char **argv) · 173 unmodified lines
174174 return (*prog_main)(argc, argv);
175175 }
176176
177+#ifdef TCC_TARGET_X86_64
178+ #define SECTION_ALIGNMENT 511
179+#else
180+ #define SECTION_ALIGNMENT 15
181+#endif
182+
177183 /* relocate code. Return -1 on error, required size if ptr is NULL,
178184 otherwise copy code into buffer passed by the caller */
179185 static int tcc_relocate_ex(TCCState *s1, void *ptr)
@@ -205,7 +211,7 @@ static int tcc_relocate_ex(TCCState *s1, void *ptr) · 25 unmodified lines
205211 s = s1->sections[i];
206212 if (0 == (s->sh_flags & SHF_ALLOC))
207213 continue;
208− offset = (offset + 15) & ~15;
214+ offset = (offset + SECTION_ALIGNMENT) & ~SECTION_ALIGNMENT;
209215 s->sh_addr = mem ? mem + offset : 0;
210216 offset += s->data_offset;
211217 }

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