[x86] Fix some asm problems

A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.

Michael Matz committed 10 years ago

Commit 5e47b081 parent f5f82ab5 files · +168 −47Browse files

Unified · Split

5 files

i386-asm.c +71 −16
i386-asm.h +1 −1
i386-tok.h +3 −7
tests/asmtest.S +67 −8
x86_64-asm.h +26 −15

i386-asm.c+71−16

@@ -115,11 +115,13 @@ enum { · 114 unmodified lines
115	115	#define OP_ADDR (1 << OPT_ADDR)
116	116	#define OP_INDIR (1 << OPT_INDIR)
117	117	#ifdef TCC_TARGET_X86_64
118		−# define OP_REG64 (1 << OPT_REG64)
119		−# define OP_IM64 (1 << OPT_IM64)
	118	+# define OP_REG64 (1 << OPT_REG64)
	119	+# define OP_IM64 (1 << OPT_IM64)
	120	+# define OP_EA32 (OP_EA << 1)
120	121	#else
121	122	# define OP_REG64 0
122	123	# define OP_IM64 0
	124	+# define OP_EA32 0
123	125	#endif
124	126
125	127	#define OP_EA 0x40000000
@@ -268,15 +270,17 @@ static inline int get_reg_shift(TCCState *s1) · 142 unmodified lines
268	270	return shift;
269	271	}
270	272
271		−static int asm_parse_reg(void)
	273	+static int asm_parse_reg(int *type)
272	274	{
273	275	int reg = 0;
	276	+ *type = 0;
274	277	if (tok != '%')
275	278	goto error_32;
276	279	next();
277	280	if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
278	281	reg = tok - TOK_ASM_eax;
279	282	#ifdef TCC_TARGET_X86_64
	283	+ *type = OP_EA32;
280	284	} else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
281	285	reg = tok - TOK_ASM_rax;
282	286	#endif
@@ -393,20 +397,23 @@ static void parse_operand(TCCState s1, Operand op) · 110 unmodified lines
393	397	}
394	398	}
395	399	if (tok == '(') {
	400	+ int type = 0;
396	401	next();
397	402	if (tok != ',') {
398		− op->reg = asm_parse_reg();
	403	+ op->reg = asm_parse_reg(&type);
399	404	}
400	405	if (tok == ',') {
401	406	next();
402	407	if (tok != ',') {
403		− op->reg2 = asm_parse_reg();
	408	+ op->reg2 = asm_parse_reg(&type);
404	409	}
405	410	if (tok == ',') {
406	411	next();
407	412	op->shift = get_reg_shift(s1);
408	413	}
409	414	}
	415	+ if (type & OP_EA32)
	416	+ op->type \|= OP_EA32;
410	417	skip(')');
411	418	}
412	419	if (op->reg == -1 && op->reg2 == -1)
@@ -493,10 +500,15 @@ static inline void asm_modrm(int reg, Operand *op) · 80 unmodified lines
493	500	gen_expr16(&op->e);
494	501	} else if (tcc_state->seg_size == 32)
495	502	#endif
496		− {
	503	+ {
	504	+#ifdef TCC_TARGET_X86_64
	505	+ g(0x04 + (reg << 3));
	506	+ g(0x25);
	507	+#else
497	508	g(0x05 + (reg << 3));
498		− gen_expr32(&op->e);
499		− }
	509	+#endif
	510	+ gen_expr32(&op->e);
	511	+ }
500	512	} else {
501	513	sib_reg1 = op->reg;
502	514	/* fist compute displacement encoding */
@@ -583,6 +595,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 80 unmodified lines
583	595	int nb_ops, s;
584	596	Operand ops[MAX_OPERANDS], *pop;
585	597	int op_type[3]; /* decoded op type */
	598	+ int alltypes; /* OR of all operand types */
	599	+ int autosize;
586	600	#ifdef I386_ASM_16
587	601	static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
588	602	#endif
@@ -596,6 +610,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 7 unmodified lines
596	610	pop = ops;
597	611	nb_ops = 0;
598	612	seg_prefix = 0;
	613	+ alltypes = 0;
599	614	for(;;) {
600	615	if (tok == ';' \|\| tok == TOK_LINEFEED)
601	616	break;
@@ -645,6 +660,13 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 43 unmodified lines
645	660	if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
646	661	continue;
647	662	} else if (pa->instr_type & OPC_B) {
	663	+#ifdef TCC_TARGET_X86_64
	664	+ /* Some instructions don't have the full size but only
	665	+ bwl form. insb e.g. */
	666	+ if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
	667	+ && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
	668	+ continue;
	669	+#endif
648	670	if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
649	671	continue;
650	672	s = opcode - pa->sym;
@@ -659,6 +681,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 8 unmodified lines
659	681	if (pa->nb_ops != nb_ops)
660	682	continue;
661	683	/* now decode and check each operand */
	684	+ alltypes = 0;
662	685	for(i = 0; i < nb_ops; i++) {
663	686	int op1, op2;
664	687	op1 = pa->op_type[i];
@@ -687,9 +710,10 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 22 unmodified lines
687	710	}
688	711	if (op1 & OPT_EA)
689	712	v \|= OP_EA;
690		− op_type[i] = v;
	713	+ op_type[i] = v;
691	714	if ((ops[i].type & v) == 0)
692	715	goto next;
	716	+ alltypes \|= ops[i].type;
693	717	}
694	718	/* all is matching ! */
695	719	break;
@@ -725,12 +749,19 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 29 unmodified lines
725	749	}
726	750	}
727	751	/* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
728		− if (s == NBWLX-1) {
729		− for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
	752	+ autosize = NBWLX-1;
	753	+#ifdef TCC_TARGET_X86_64
	754	+ /* XXX the autosize should rather be zero, to not have to adjust this
	755	+ all the time. */
	756	+ if ((pa->instr_type & OPC_WLQ) != OPC_WLQ)
	757	+ autosize = NBWLX-2;
	758	+#endif
	759	+ if (s == autosize) {
	760	+ for(i = 0; s == autosize && i < nb_ops; i++) {
730	761	if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL \| OP_DX)))
731	762	s = reg_to_size[ops[i].type & OP_REG];
732	763	}
733		− if (s == NBWLX-1) {
	764	+ if (s == autosize) {
734	765	if ((opcode == TOK_ASM_push \|\| opcode == TOK_ASM_pop) &&
735	766	(ops[0].type & (OP_SEG \| OP_IM8S \| OP_IM32 \| OP_IM64)))
736	767	s = 2;
@@ -770,14 +801,38 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 33 unmodified lines
770	801
771	802	addr32 = data32 = 0;
772	803	#else
	804	+#ifdef TCC_TARGET_X86_64
	805	+ /* Generate addr32 prefix if needed */
	806	+ for(i = 0; i < nb_ops; i++) {
	807	+ if (ops[i].type & OP_EA32) {
	808	+ g(0x67);
	809	+ break;
	810	+ }
	811	+ }
	812	+#endif
773	813	/* generate data16 prefix if needed */
774	814	if (s == 1 \|\| (pa->instr_type & OPC_D16))
775	815	g(0x66);
776	816	#ifdef TCC_TARGET_X86_64
777		− else if (s == 3) {
	817	+ if (s == 3 \|\| (alltypes & OP_REG64)) {
778	818	/* generate REX prefix */
779		− if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
780		− \|\| !(ops[0].type & OP_REG64))
	819	+ int default64 = 0;
	820	+ for(i = 0; i < nb_ops; i++) {
	821	+ if (op_type[i] == OP_REG64) {
	822	+ /* If only 64bit regs are accepted in one operand
	823	+ this is a default64 instruction without need for
	824	+ REX prefixes. */
	825	+ default64 = 1;
	826	+ break;
	827	+ }
	828	+ }
	829	+ /* XXX find better encoding for the default64 instructions. */
	830	+ if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
	831	+ && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
	832	+ && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
	833	+ && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
	834	+ && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
	835	+ && !default64)
781	836	g(0x48);
782	837	}
783	838	#endif
@@ -838,7 +893,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 54 unmodified lines
838	893	goto no_short_jump;
839	894	if (sym->r != cur_text_section->sh_num)
840	895	goto no_short_jump;
841		− jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
	896	+ jmp_disp = ops[0].e.v + sym->jnext - ind - 2 - (v >= 0xff);
842	897	if (jmp_disp == (int8_t)jmp_disp) {
843	898	/* OK to generate jump */
844	899	is_short_jmp = 1;

i386-asm.h+1−1

@@ -165,8 +165,8 @@ ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH \| OPC_BWL, OPT_IM, OPT_EAX)) · 164 unmodified lines
165	165	ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH \| OPC_MODRM \| OPC_BWL, OPT_IM, OPT_EA \| OPT_REG))
166	166	ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH \| OPC_MODRM \| OPC_WL, OPT_IM8S, OPT_EA \| OPT_REG))
167	167
168		−ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWL, OPT_EA \| OPT_REG, OPT_REG))
169	168	ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWL, OPT_REG, OPT_EA \| OPT_REG))
	169	+ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWL, OPT_EA \| OPT_REG, OPT_REG))
170	170	ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWL, OPT_IM, OPT_EAX))
171	171	ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM \| OPC_BWL, OPT_IM, OPT_EA \| OPT_REG))
172	172

i386-tok.h+3−7

@@ -126,12 +126,8 @@ · 125 unmodified lines
126	126	DEF_BWLX(shr)
127	127	DEF_BWLX(sar)
128	128
129		− DEF_ASM(shldw)
130		− DEF_ASM(shldl)
131		− DEF_ASM(shld)
132		− DEF_ASM(shrdw)
133		− DEF_ASM(shrdl)
134		− DEF_ASM(shrd)
	129	+ DEF_WLX(shld)
	130	+ DEF_WLX(shrd)
135	131
136	132	DEF_ASM(pushw)
137	133	DEF_ASM(pushl)
@@ -150,7 +146,7 @@ · 12 unmodified lines
150	146	DEF_BWL(in)
151	147	DEF_BWL(out)
152	148
153		− DEF_WL(movzb)
	149	+ DEF_WLX(movzb)
154	150	DEF_ASM(movzwl)
155	151	DEF_ASM(movsbw)
156	152	DEF_ASM(movsbl)

tests/asmtest.S+67−8

@@ -38,7 +38,7 @@ mov %al, 0x10000 · 37 unmodified lines
38	38
39	39	mov $1, %edx
40	40	mov $1, %dx
41		−mov $1, %dl
	41	+mov $1, %cl
42	42	movb $2, 0x100(%ebx,%edx,2)
43	43	movw $2, 0x100(%ebx,%edx,2)
44	44	movl $2, 0x100(%ebx,%edx,2)
@@ -48,12 +48,20 @@ movw %ax, 0x100(%ebx,%edx,2) · 3 unmodified lines
48	48
49	49	mov %eax, 0x12(,%edx,2)
50	50
	51	+#ifdef __i386__
51	52	mov %cr3, %edx
52	53	mov %ecx, %cr3
53	54	movl %cr3, %eax
54	55	movl %tr3, %eax
55	56	movl %db3, %ebx
56	57	movl %dr6, %eax
	58	+#else
	59	+mov %cr3, %rdx
	60	+mov %rcx, %cr3
	61	+movq %cr3, %rax
	62	+movq %db3, %rbx
	63	+movq %dr6, %rax
	64	+#endif
57	65	movl %fs, %ecx
58	66	movl %ebx, %fs
59	67
@@ -69,18 +77,28 @@ movl %ebx, %fs · 9 unmodified lines
69	77	movzb 0x1000, %ax
70	78
71	79
	80	+#ifdef __i386__
72	81	pushl %eax
73		− pushw %ax
74	82	push %eax
75	83	push %cs
	84	+#else
	85	+ pushq %rax
	86	+ push %rax
	87	+#endif
	88	+ pushw %ax
76	89	push %gs
77	90	push $1
78	91	push $100
79	92
	93	+#ifdef __i386__
80	94	popl %eax
81		− popw %ax
82	95	pop %eax
83	96	pop %ds
	97	+#else
	98	+ popq %rax
	99	+ pop %rax
	100	+#endif
	101	+ popw %ax
84	102	pop %fs
85	103
86	104	xchg %eax, %ecx
@@ -111,11 +129,13 @@ movl %ebx, %fs · 24 unmodified lines
111	129	leal 0x1000(%ebx), %ecx
112	130	lea 0x1000(%ebx), %ecx
113	131
	132	+#ifdef __i386__
114	133	les 0x2000, %eax
115	134	lds 0x2000, %ebx
	135	+ lss 0x2000, %edx
	136	+#endif
116	137	lfs 0x2000, %ecx
117	138	lgs 0x2000, %edx
118		− lss 0x2000, %edx
119	139
120	140	addl $0x123, %eax
121	141	add $0x123, %ebx
@@ -195,7 +215,11 @@ shrd %eax, %edx · 73 unmodified lines
195	215	L4:
196	216	call 0x1000
197	217	call L4
	218	+#ifdef __i386__
198	219	call *%eax
	220	+#else
	221	+call *%rax
	222	+#endif
199	223	call *0x1000
200	224	call func1
201	225
@@ -204,19 +228,37 @@ call func1 · 2 unmodified lines
204	228	L5:
205	229	L6:
206	230
	231	+#ifdef __i386__
207	232	lcall $0x100, $0x1000
	233	+#else
	234	+lcall *0x100
	235	+lcall *(%rax)
	236	+#endif
208	237
209	238	jmp 0x1000
	239	+#ifdef __i386__
210	240	jmp *%eax
	241	+#else
	242	+jmp *%rax
	243	+#endif
211	244	jmp *0x1000
212	245
	246	+#ifdef __i386__
213	247	ljmp $0x100, $0x1000
	248	+#else
	249	+ljmp *0x100
	250	+ljmp *(%rdi)
	251	+#endif
214	252
215	253	ret
216		−retl
217		−
218	254	ret $10
	255	+#ifdef __i386__
	256	+retl
219	257	retl $10
	258	+#else
	259	+retq
	260	+retq $10
	261	+#endif
220	262
221	263	lret
222	264
@@ -436,8 +478,10 @@ fucomip %st(5), %st · 213 unmodified lines
436	478	int $3
437	479	int $0x10
438	480
	481	+#ifdef __i386__
439	482	pusha
440	483	popa
	484	+#endif
441	485	clc
442	486	cld
443	487	cli
@@ -445,19 +489,27 @@ int $0x10 · 1 unmodified line
445	489	cmc
446	490	lahf
447	491	sahf
	492	+#ifdef __i386__
448	493	pushfl
449	494	popfl
	495	+#else
	496	+ pushfq
	497	+ popfq
	498	+#endif
450	499	pushf
451	500	popf
452	501	stc
453	502	std
454	503	sti
	504	+#ifdef __i386__
455	505	aaa
456	506	aas
457	507	daa
458	508	das
459	509	aad
460	510	aam
	511	+ into
	512	+#endif
461	513	cbw
462	514	cwd
463	515	cwde
@@ -468,7 +520,6 @@ int $0x10 · 4 unmodified lines
468	520	cltd
469	521	leave
470	522	int3
471		− into
472	523	iret
473	524	rsm
474	525	hlt
@@ -558,10 +609,12 @@ int $0x10 · 83 unmodified lines
558	609
559	610
560	611
	612	+#ifdef __i386__
561	613	boundl %edx, 0x10000
562	614	boundw %bx, 0x1000
563		−
	615	+
564	616	arpl %bx, 0x1000
	617	+#endif
565	618	lar 0x1000, %eax
566	619	lgdt 0x1000
567	620	lidt 0x1000
@@ -579,15 +632,21 @@ int $0x10 · 11 unmodified lines
579	632	verr 0x1000
580	633	verw 0x1000
581	634
	635	+#ifdef __i386__
582	636	push %ds
583	637	pushw %ds
584	638	pushl %ds
585	639	pop %ds
586	640	popw %ds
587	641	popl %ds
	642	+#endif
588	643	fxsave 1(%ebx)
589	644	fxrstor 1(%ecx)
	645	+#ifdef __i386__
590	646	pushl $1
	647	+#else
	648	+ pushq $1
	649	+#endif
591	650	pushw $1
592	651	push $1
593	652

x86_64-asm.h+26−15

@@ -5,8 +5,8 @@ · 4 unmodified lines
5	5	DEF_ASM_OP0(cmc, 0xf5)
6	6	DEF_ASM_OP0(lahf, 0x9f)
7	7	DEF_ASM_OP0(sahf, 0x9e)
8		− DEF_ASM_OP0(pushfl, 0x9c)
9		− DEF_ASM_OP0(popfl, 0x9d)
	8	+ DEF_ASM_OP0(pushfq, 0x9c)
	9	+ DEF_ASM_OP0(popfq, 0x9d)
10	10	DEF_ASM_OP0(pushf, 0x9c)
11	11	DEF_ASM_OP0(popf, 0x9d)
12	12	DEF_ASM_OP0(stc, 0xf9)
@@ -34,14 +34,15 @@ · 21 unmodified lines
34	34	DEF_ASM_OP0(hlt, 0xf4)
35	35	DEF_ASM_OP0(wait, 0x9b)
36	36	DEF_ASM_OP0(nop, 0x90)
	37	+ DEF_ASM_OP0(pause, 0xf390)
37	38	DEF_ASM_OP0(xlat, 0xd7)
38	39
39	40	/* strings */
40	41	ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWLQ))
41	42	ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWLQ))
42	43
43		−ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWLQ))
44		−ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWLQ))
	44	+ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWL))
	45	+ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWL))
45	46
46	47	ALT(DEF_ASM_OP0L(lodsb, 0xac, 0, OPC_BWLQ))
47	48	ALT(DEF_ASM_OP0L(slodb, 0xac, 0, OPC_BWLQ))
@@ -90,8 +91,10 @@ ALT(DEF_ASM_OP2(btcw, 0x0fba, 7, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW \| OPT_EA · 42 unmodified lines
90	91	DEF_ASM_OP0(ud2, 0x0f0b)
91	92
92	93	/* NOTE: we took the same order as gas opcode definition order */
	94	+/* Right now we can't express the fact that 0xa1/0xa3 can't use $eax and a
	95	+ 32 bit moffset as operands.
93	96	ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWLQ, OPT_ADDR, OPT_EAX))
94		−ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR))
	97	+ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR)) */
95	98	ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG))
96	99	ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
97	100	ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG \| OPC_BWLQ, OPT_IM, OPT_REG))
@@ -102,25 +105,28 @@ ALT(DEF_ASM_OP2(movw, 0x8e, 0, OPC_MODRM \| OPC_WLQ, OPT_EA \| OPT_REG, OPT_SEG)) · 4 unmodified lines
102	105
103	106	ALT(DEF_ASM_OP2(movw, 0x0f20, 0, OPC_MODRM \| OPC_WLQ, OPT_CR, OPT_REG64))
104	107	ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM \| OPC_WLQ, OPT_DB, OPT_REG64))
105		−ALT(DEF_ASM_OP2(movw, 0x0f24, 0, OPC_MODRM \| OPC_WLQ, OPT_TR, OPT_REG64))
106	108	ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_CR))
107	109	ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_DB))
108		−ALT(DEF_ASM_OP2(movw, 0x0f26, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_TR))
109	110
110	111	ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 \| OPT_EA, OPT_REG32))
111	112	ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM \| OPC_D16, OPT_REG8 \| OPT_EA, OPT_REG16))
112	113	ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 \| OPT_EA, OPT_REG32))
113	114	ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 \| OPT_EA, OPT_REG))
114		−ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM \| OPC_WL, OPT_REG8 \| OPT_EA, OPT_REGW))
	115	+ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM \| OPC_WLQ, OPT_REG8 \| OPT_EA, OPT_REGW))
115	116	ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 \| OPT_EA, OPT_REG32))
116	117
	118	+ALT(DEF_ASM_OP1(pushq, 0x6a, 0, 0, OPT_IM8S))
	119	+ALT(DEF_ASM_OP1(push, 0x6a, 0, 0, OPT_IM8S))
	120	+ALT(DEF_ASM_OP1(pushw, 0x6a, 0, OPC_D16, OPT_IM8S))
117	121	ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG \| OPC_WLQ, OPT_REG64))
	122	+ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG \| OPC_WLQ, OPT_REG16))
118	123	ALT(DEF_ASM_OP1(pushw, 0xff, 6, OPC_MODRM \| OPC_WLQ, OPT_REG64 \| OPT_EA))
	124	+ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_D16, OPT_IM16))
119	125	ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_WLQ, OPT_IM32))
120	126	ALT(DEF_ASM_OP1(pushw, 0x06, 0, OPC_WLQ, OPT_SEG))
121		− DEF_ASM_OP1(pushb, 0x6a, 0, OPC_B, OPT_IM8S)
122	127
123		−ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG \| OPC_WLQ, OPT_REGW))
	128	+ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG \| OPC_WLQ, OPT_REG64))
	129	+ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG \| OPC_WLQ, OPT_REG16))
124	130	ALT(DEF_ASM_OP1(popw, 0x8f, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW \| OPT_EA))
125	131	ALT(DEF_ASM_OP1(popw, 0x07, 0, OPC_WLQ, OPT_SEG))
126	132
@@ -154,8 +160,8 @@ ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH \| OPC_BWLQ, OPT_IMNO64, OPT_EAX)) · 27 unmodified lines
154	160	ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH \| OPC_MODRM \| OPC_BWLQ, OPT_IMNO64, OPT_EA \| OPT_REG))
155	161	ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH \| OPC_MODRM \| OPC_WLQ, OPT_IM8S, OPT_EA \| OPT_REG))
156	162
157		−ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
158	163	ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG))
	164	+ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
159	165	ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IMNO64, OPT_EAX))
160	166	ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM \| OPC_BWLQ, OPT_IMNO64, OPT_EA \| OPT_REG))
161	167
@@ -206,7 +212,9 @@ ALT(DEF_ASM_OP1(setob, 0x0f90, 0, OPC_MODRM \| OPC_TEST, OPT_REG8 \| OPT_EA)) · 44 unmodified lines
206	212	DEF_ASM_OP2(enter, 0xc8, 0, 0, OPT_IM16, OPT_IM8)
207	213	DEF_ASM_OP0(leave, 0xc9)
208	214	DEF_ASM_OP0(ret, 0xc3)
	215	+ DEF_ASM_OP0(retq, 0xc3)
209	216	ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
	217	+ALT(DEF_ASM_OP1(retq, 0xc2, 0, 0, OPT_IM16))
210	218	DEF_ASM_OP0(lret, 0xcb)
211	219	ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
212	220
@@ -216,7 +224,7 @@ ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP \| OPC_JMP \| OPC_TEST, OPT_ADDR)) · 3 unmodified lines
216	224	DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
217	225	DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
218	226	DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
219		− DEF_ASM_OP1(jecxz, 0xe3, 0, OPC_SHORTJMP, OPT_ADDR)
	227	+ DEF_ASM_OP1(jecxz, 0x67e3, 0, OPC_SHORTJMP, OPT_ADDR)
220	228
221	229	/* float */
222	230	/* specific fcomp handling */
@@ -224,6 +232,8 @@ ALT(DEF_ASM_OP0L(fcomp, 0xd8d9, 0, 0)) · 1 unmodified line
224	232
225	233	ALT(DEF_ASM_OP1(fadd, 0xd8c0, 0, OPC_FARITH \| OPC_REG, OPT_ST))
226	234	ALT(DEF_ASM_OP2(fadd, 0xd8c0, 0, OPC_FARITH \| OPC_REG, OPT_ST, OPT_ST0))
	235	+ALT(DEF_ASM_OP2(fadd, 0xdcc0, 0, OPC_FARITH \| OPC_REG, OPT_ST0, OPT_ST))
	236	+ALT(DEF_ASM_OP2(fmul, 0xdcc8, 0, OPC_FARITH \| OPC_REG, OPT_ST0, OPT_ST))
227	237	ALT(DEF_ASM_OP0L(fadd, 0xdec1, 0, OPC_FARITH))
228	238	ALT(DEF_ASM_OP1(faddp, 0xdec0, 0, OPC_FARITH \| OPC_REG, OPT_ST))
229	239	ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH \| OPC_REG, OPT_ST, OPT_ST0))
@@ -334,7 +344,7 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM \| OPC_FWAIT, OPT_EA )) · 104 unmodified lines
334	344	DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)
335	345	DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA \| OPT_REG)
336	346	DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA \| OPT_REG)
337		−ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM \| OPC_WL, OPT_EA \| OPT_REG, OPT_REG))
	347	+ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM \| OPC_WLQ, OPT_EA \| OPT_REG, OPT_REG))
338	348	DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA \| OPT_REG)
339	349	DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)
340	350	DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)
@@ -346,8 +356,8 @@ ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM \| OPC_WL, OPT_EA \| OPT_REG, OPT_REG)) · 5 unmodified lines
346	356
347	357	/* 486 */
348	358	DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )
349		−ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM \| OPC_BWL, OPT_REG, OPT_REG \| OPT_EA ))
350		−ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM \| OPC_BWL, OPT_REG, OPT_REG \| OPT_EA ))
	359	+ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_REG \| OPT_EA ))
	360	+ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_REG \| OPT_EA ))
351	361	DEF_ASM_OP1(invlpg, 0x0f01, 7, OPC_MODRM, OPT_EA )
352	362
353	363	DEF_ASM_OP2(boundl, 0x62, 0, OPC_MODRM, OPT_REG32, OPT_EA)
@@ -383,6 +393,7 @@ ALT(DEF_ASM_OP2(cmova, 0x0f47, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_ · 29 unmodified lines
383	393	/* mmx */
384	394	DEF_ASM_OP0(emms, 0x0f77) /* must be last OP0 */
385	395	DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA \| OPT_REG32, OPT_MMX )
	396	+ALT(DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA \| OPT_REG64, OPT_MMX ))
386	397	ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMX, OPT_EA \| OPT_REG32 ))
387	398	ALT(DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX ))
388	399	ALT(DEF_ASM_OP2(movq, 0x0f7f, 0, OPC_MODRM, OPT_MMX, OPT_EA \| OPT_MMX ))

[x86] Fix some asm problems

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