/* SPDX-License-Identifier: GPL-2.0-only *//* * Low-level exception handling code * * Copyright (C) 2012 ARM Ltd. * Authors:	Catalin Marinas <catalin.marinas@arm.com> *		Will Deacon <will.deacon@arm.com> */ #include <linux/arm-smccc.h>#include <linux/init.h>#include <linux/linkage.h> #include <asm/alternative.h>#include <asm/assembler.h>#include <asm/asm-offsets.h>#include <asm/asm_pointer_auth.h>#include <asm/bug.h>#include <asm/cpufeature.h>#include <asm/errno.h>#include <asm/esr.h>#include <asm/irq.h>#include <asm/memory.h>#include <asm/mmu.h>#include <asm/processor.h>#include <asm/ptrace.h>#include <asm/scs.h>#include <asm/stacktrace/frame.h>#include <asm/thread_info.h>#include <asm/asm-uaccess.h>#include <asm/unistd.h> 	.macro	clear_gp_regs	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29	mov	x\n, xzr	.endr	.endm 	.macro kernel_ventry, el:req, ht:req, regsize:req, label:req	.align 7.Lventry_start\@:	.if	\el == 0	/*	 * This must be the first instruction of the EL0 vector entries. It is	 * skipped by the trampoline vectors, to trigger the cleanup.	 */	b	.Lskip_tramp_vectors_cleanup\@	.if	\regsize == 64	mrs	x30, tpidrro_el0	msr	tpidrro_el0, xzr	.else	mov	x30, xzr	.endif.Lskip_tramp_vectors_cleanup\@:	.endif 	sub	sp, sp, #PT_REGS_SIZE	/*	 * Test whether the SP has overflowed, without corrupting a GPR.	 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)	 * should always be zero.	 */	add	sp, sp, x0			// sp' = sp + x0	sub	x0, sp, x0			// x0' = sp' - x0 = (sp + x0) - x0 = sp	tbnz	x0, #THREAD_SHIFT, 0f	sub	x0, sp, x0			// x0'' = sp' - x0' = (sp + x0) - sp = x0	sub	sp, sp, x0			// sp'' = sp' - x0 = (sp + x0) - x0 = sp	b	el\el\ht\()_\regsize\()_\label 0:	/*	 * Either we've just detected an overflow, or we've taken an exception	 * while on the overflow stack. Either way, we won't return to	 * userspace, and can clobber EL0 registers to free up GPRs.	 */ 	/* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */	msr	tpidr_el0, x0 	/* Recover the original x0 value and stash it in tpidrro_el0 */	sub	x0, sp, x0	msr	tpidrro_el0, x0 	/* Switch to the overflow stack */	adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 	/*	 * Check whether we were already on the overflow stack. This may happen	 * after panic() re-enables interrupts.	 */	mrs	x0, tpidr_el0			// sp of interrupted context	sub	x0, sp, x0			// delta with top of overflow stack	tst	x0, #~(OVERFLOW_STACK_SIZE - 1)	// within range?	b.ne	__bad_stack			// no? -> bad stack pointer 	/* We were already on the overflow stack. Restore sp/x0 and carry on. */	sub	sp, sp, x0	mrs	x0, tpidrro_el0	b	el\el\ht\()_\regsize\()_\label.org .Lventry_start\@ + 128	// Did we overflow the ventry slot?	.endm 	.macro	tramp_alias, dst, sym	.set	.Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text	movz	\dst, :abs_g2_s:.Lalias\@	movk	\dst, :abs_g1_nc:.Lalias\@	movk	\dst, :abs_g0_nc:.Lalias\@	.endm 	/*	 * This macro corrupts x0-x3. It is the caller's duty  to save/restore	 * them if required.	 */	.macro	apply_ssbd, state, tmp1, tmp2alternative_cb	ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable	b	.L__asm_ssbd_skip\@		// Patched to NOPalternative_cb_end	ldr_this_cpu	\tmp2, arm64_ssbd_callback_required, \tmp1	cbz	\tmp2,	.L__asm_ssbd_skip\@	ldr	\tmp2, [tsk, #TSK_TI_FLAGS]	tbnz	\tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@	mov	w0, #ARM_SMCCC_ARCH_WORKAROUND_2	mov	w1, #\statealternative_cb	ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit	nop					// Patched to SMC/HVC #0alternative_cb_end.L__asm_ssbd_skip\@:	.endm 	/* Check for MTE asynchronous tag check faults */	.macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr#ifdef CONFIG_ARM64_MTE	.arch_extension lsealternative_if_not ARM64_MTE	b	1falternative_else_nop_endif	/*	 * Asynchronous tag check faults are only possible in ASYNC (2) or	 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is	 * set, so skip the check if it is unset.	 */	tbz	\thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f	mrs_s	\tmp, SYS_TFSRE0_EL1	tbz	\tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f	/* Asynchronous TCF occurred for TTBR0 access, set the TI flag */	mov	\tmp, #_TIF_MTE_ASYNC_FAULT	add	\ti_flags, tsk, #TSK_TI_FLAGS	stset	\tmp, [\ti_flags]1:#endif	.endm 	/* Clear the MTE asynchronous tag check faults */	.macro clear_mte_async_tcf thread_sctlr#ifdef CONFIG_ARM64_MTEalternative_if ARM64_MTE	/* See comment in check_mte_async_tcf above. */	tbz	\thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f	dsb	ish	msr_s	SYS_TFSRE0_EL1, xzr1:alternative_else_nop_endif#endif	.endm 	.macro mte_set_gcr, mte_ctrl, tmp#ifdef CONFIG_ARM64_MTE	ubfx	\tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16	orr	\tmp, \tmp, #SYS_GCR_EL1_RRND	msr_s	SYS_GCR_EL1, \tmp#endif	.endm 	.macro mte_set_kernel_gcr, tmp, tmp2#ifdef CONFIG_KASAN_HW_TAGSalternative_cb	ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable	b	1falternative_cb_end	mov	\tmp, KERNEL_GCR_EL1	msr_s	SYS_GCR_EL1, \tmp1:#endif	.endm 	.macro mte_set_user_gcr, tsk, tmp, tmp2#ifdef CONFIG_KASAN_HW_TAGSalternative_cb	ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable	b	1falternative_cb_end	ldr	\tmp, [\tsk, #THREAD_MTE_CTRL] 	mte_set_gcr \tmp, \tmp21:#endif	.endm 	.macro	kernel_entry, el, regsize = 64	.if	\el == 0	alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT	.endif	.if	\regsize == 32	mov	w0, w0				// zero upper 32 bits of x0	.endif	stp	x0, x1, [sp, #16 * 0]	stp	x2, x3, [sp, #16 * 1]	stp	x4, x5, [sp, #16 * 2]	stp	x6, x7, [sp, #16 * 3]	stp	x8, x9, [sp, #16 * 4]	stp	x10, x11, [sp, #16 * 5]	stp	x12, x13, [sp, #16 * 6]	stp	x14, x15, [sp, #16 * 7]	stp	x16, x17, [sp, #16 * 8]	stp	x18, x19, [sp, #16 * 9]	stp	x20, x21, [sp, #16 * 10]	stp	x22, x23, [sp, #16 * 11]	stp	x24, x25, [sp, #16 * 12]	stp	x26, x27, [sp, #16 * 13]	stp	x28, x29, [sp, #16 * 14] 	.if	\el == 0	clear_gp_regs	mrs	x21, sp_el0	ldr_this_cpu	tsk, __entry_task, x20	msr	sp_el0, tsk 	/*	 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions	 * when scheduling.	 */	ldr	x19, [tsk, #TSK_TI_FLAGS]	disable_step_tsk x19, x20 	/* Check for asynchronous tag check faults in user space */	ldr	x0, [tsk, THREAD_SCTLR_USER]	check_mte_async_tcf x22, x23, x0 #ifdef CONFIG_ARM64_PTR_AUTHalternative_if ARM64_HAS_ADDRESS_AUTH	/*	 * Enable IA for in-kernel PAC if the task had it disabled. Although	 * this could be implemented with an unconditional MRS which would avoid	 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.	 *	 * Install the kernel IA key only if IA was enabled in the task. If IA	 * was disabled on kernel exit then we would have left the kernel IA	 * installed so there is no need to install it again.	 */	tbz	x0, SCTLR_ELx_ENIA_SHIFT, 1f	__ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23	b	2f1:	mrs	x0, sctlr_el1	orr	x0, x0, SCTLR_ELx_ENIA	msr	sctlr_el1, x02:alternative_else_nop_endif#endif 	apply_ssbd 1, x22, x23 	mte_set_kernel_gcr x22, x23 	/*	 * Any non-self-synchronizing system register updates required for	 * kernel entry should be placed before this point.	 */alternative_if ARM64_MTE	isb	b	1falternative_else_nop_endifalternative_if ARM64_HAS_ADDRESS_AUTH	isbalternative_else_nop_endif1: 	scs_load_current_base	.else	add	x21, sp, #PT_REGS_SIZE	get_current_task tsk	.endif /* \el == 0 */	mrs	x22, elr_el1	mrs	x23, spsr_el1	stp	lr, x21, [sp, #S_LR] 	/*	 * Create a metadata frame record. The unwinder will use this to	 * identify and unwind exception boundaries.	 */	stp	xzr, xzr, [sp, #S_STACKFRAME]	.if \el == 0	mov	x0, #FRAME_META_TYPE_FINAL	.else	mov	x0, #FRAME_META_TYPE_PT_REGS	.endif	str	x0, [sp, #S_STACKFRAME_TYPE]	add	x29, sp, #S_STACKFRAME #ifdef CONFIG_ARM64_SW_TTBR0_PANalternative_if_not ARM64_HAS_PAN	bl	__swpan_entry_el\elalternative_else_nop_endif#endif 	stp	x22, x23, [sp, #S_PC] 	/* Not in a syscall by default (el0_svc overwrites for real syscall) */	.if	\el == 0	mov	w21, #NO_SYSCALL	str	w21, [sp, #S_SYSCALLNO]	.endif #ifdef CONFIG_ARM64_PSEUDO_NMIalternative_if_not ARM64_HAS_GIC_PRIO_MASKING	b	.Lskip_pmr_save\@alternative_else_nop_endif 	mrs_s	x20, SYS_ICC_PMR_EL1	str	w20, [sp, #S_PMR]	mov	x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET	msr_s	SYS_ICC_PMR_EL1, x20 .Lskip_pmr_save\@:#endif 	/*	 * Registers that may be useful after this macro is invoked:	 *	 * x20 - ICC_PMR_EL1	 * x21 - aborted SP	 * x22 - aborted PC	 * x23 - aborted PSTATE	*/	.endm 	.macro	kernel_exit, el#ifdef CONFIG_ARM64_PSEUDO_NMIalternative_if_not ARM64_HAS_GIC_PRIO_MASKING	b	.Lskip_pmr_restore\@alternative_else_nop_endif 	ldr	w20, [sp, #S_PMR]	msr_s	SYS_ICC_PMR_EL1, x20 	/* Ensure priority change is seen by redistributor */alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC	dsb	syalternative_else_nop_endif .Lskip_pmr_restore\@:#endif 	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR #ifdef CONFIG_ARM64_SW_TTBR0_PANalternative_if_not ARM64_HAS_PAN	bl	__swpan_exit_el\elalternative_else_nop_endif#endif 	.if	\el == 0	ldr	x23, [sp, #S_SP]		// load return stack pointer	msr	sp_el0, x23	tst	x22, #PSR_MODE32_BIT		// native task?	b.eq	3f #ifdef CONFIG_ARM64_ERRATUM_845719alternative_if ARM64_WORKAROUND_845719#ifdef CONFIG_PID_IN_CONTEXTIDR	mrs	x29, contextidr_el1	msr	contextidr_el1, x29#else	msr contextidr_el1, xzr#endifalternative_else_nop_endif#endif3:	/* Ignore asynchronous tag check faults in the uaccess routines */	ldr	x0, [tsk, THREAD_SCTLR_USER]	clear_mte_async_tcf x0 #ifdef CONFIG_ARM64_PTR_AUTHalternative_if ARM64_HAS_ADDRESS_AUTH	/*	 * IA was enabled for in-kernel PAC. Disable it now if needed, or	 * alternatively install the user's IA. All other per-task keys and	 * SCTLR bits were updated on task switch.	 *	 * No kernel C function calls after this.	 */	tbz	x0, SCTLR_ELx_ENIA_SHIFT, 1f	__ptrauth_keys_install_user tsk, x0, x1, x2	b	2f1:	mrs	x0, sctlr_el1	bic	x0, x0, SCTLR_ELx_ENIA	msr	sctlr_el1, x02:alternative_else_nop_endif#endif 	mte_set_user_gcr tsk, x0, x1 	apply_ssbd 0, x0, x1	.endif 	msr	elr_el1, x21			// set up the return data	msr	spsr_el1, x22	ldp	x0, x1, [sp, #16 * 0]	ldp	x2, x3, [sp, #16 * 1]	ldp	x4, x5, [sp, #16 * 2]	ldp	x6, x7, [sp, #16 * 3]	ldp	x8, x9, [sp, #16 * 4]	ldp	x10, x11, [sp, #16 * 5]	ldp	x12, x13, [sp, #16 * 6]	ldp	x14, x15, [sp, #16 * 7]	ldp	x16, x17, [sp, #16 * 8]	ldp	x18, x19, [sp, #16 * 9]	ldp	x20, x21, [sp, #16 * 10]	ldp	x22, x23, [sp, #16 * 11]	ldp	x24, x25, [sp, #16 * 12]	ldp	x26, x27, [sp, #16 * 13]	ldp	x28, x29, [sp, #16 * 14] 	.if	\el == 0#ifdef CONFIG_UNMAP_KERNEL_AT_EL0	alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 	msr	far_el1, x29 	ldr_this_cpu	x30, this_cpu_vector, x29	tramp_alias	x29, tramp_exit	msr		vbar_el1, x30		// install vector table	ldr		lr, [sp, #S_LR]		// restore x30	add		sp, sp, #PT_REGS_SIZE	// restore sp	br		x29 .L_skip_tramp_exit_\@:#endif	.endif 	ldr	lr, [sp, #S_LR]	add	sp, sp, #PT_REGS_SIZE		// restore sp 	.if \el == 0	/* This must be after the last explicit memory access */alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD	tlbi	vale1, xzr	dsb	nshalternative_else_nop_endif	.else	/* Ensure any device/NC reads complete */	alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412	.endif 	eret	sb	.endm #ifdef CONFIG_ARM64_SW_TTBR0_PAN	/*	 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from	 * EL0, there is no need to check the state of TTBR0_EL1 since	 * accesses are always enabled.	 * Note that the meaning of this bit differs from the ARMv8.1 PAN	 * feature as all TTBR0_EL1 accesses are disabled, not just those to	 * user mappings.	 */SYM_CODE_START_LOCAL(__swpan_entry_el1)	mrs	x21, ttbr0_el1	tst	x21, #TTBRx_EL1_ASID_MASK	// Check for the reserved ASID	orr	x23, x23, #PSR_PAN_BIT		// Set the emulated PAN in the saved SPSR	b.eq	1f				// TTBR0 access already disabled	and	x23, x23, #~PSR_PAN_BIT		// Clear the emulated PAN in the saved SPSRSYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)	__uaccess_ttbr0_disable x211:	retSYM_CODE_END(__swpan_entry_el1) 	/*	 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR	 * PAN bit checking.	 */SYM_CODE_START_LOCAL(__swpan_exit_el1)	tbnz	x22, #22, 1f			// Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set	__uaccess_ttbr0_enable x0, x11:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit	retSYM_CODE_END(__swpan_exit_el1) SYM_CODE_START_LOCAL(__swpan_exit_el0)	__uaccess_ttbr0_enable x0, x1	/*	 * Enable errata workarounds only if returning to user. The only	 * workaround currently required for TTBR0_EL1 changes are for the	 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache	 * corruption).	 */	b	post_ttbr_update_workaroundSYM_CODE_END(__swpan_exit_el0)#endif

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