// SPDX-License-Identifier: GPL-2.0-only/* * Resource Director Technology(RDT) * - Cache Allocation code. * * Copyright (C) 2016 Intel Corporation * * Authors: * Fenghua Yu <fenghua.yu@intel.com> * Tony Luck <tony.luck@intel.com> * Vikas Shivappa <vikas.shivappa@intel.com> * * More information about RDT be found in the Intel (R) x86 Architecture * Software Developer Manual June 2016, volume 3, section 17.17. */ #define pr_fmt(fmt) "resctrl: " fmt #include <linux/cpu.h>#include <linux/slab.h>#include <linux/err.h>#include <linux/cpuhotplug.h> #include <asm/cpu_device_id.h>#include <asm/cpuid/api.h>#include <asm/msr.h>#include <asm/resctrl.h>#include "internal.h" /* * rdt_domain structures are kfree()d when their last CPU goes offline, * and allocated when the first CPU in a new domain comes online. * The rdt_resource's domain list is updated when this happens. Readers of * the domain list must either take cpus_read_lock(), or rely on an RCU * read-side critical section, to avoid observing concurrent modification. * All writers take this mutex: */static DEFINE_MUTEX(domain_list_lock); /* * The cached resctrl_pqr_state is strictly per CPU and can never be * updated from a remote CPU. Functions which modify the state * are called with interrupts disabled and no preemption, which * is sufficient for the protection. */DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); /* * Global boolean for rdt_alloc which is true if any * resource allocation is enabled. */bool rdt_alloc_capable; static void mba_wrmsr_intel(struct msr_param *m);static void cat_wrmsr(struct msr_param *m);static void mba_wrmsr_amd(struct msr_param *m); #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains)#define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = { [RDT_RESOURCE_L3] = { .r_resctrl = { .name = "L3", .ctrl_scope = RESCTRL_L3_CACHE, .mon_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3), .mon_domains = mon_domain_init(RDT_RESOURCE_L3), .schema_fmt = RESCTRL_SCHEMA_BITMAP, }, .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, }, [RDT_RESOURCE_L2] = { .r_resctrl = { .name = "L2", .ctrl_scope = RESCTRL_L2_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2), .schema_fmt = RESCTRL_SCHEMA_BITMAP, }, .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, }, [RDT_RESOURCE_MBA] = { .r_resctrl = { .name = "MB", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_SMBA] = { .r_resctrl = { .name = "SMBA", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_PERF_PKG] = { .r_resctrl = { .name = "PERF_PKG", .mon_scope = RESCTRL_PACKAGE, .mon_domains = mon_domain_init(RDT_RESOURCE_PERF_PKG), }, },}; /** * resctrl_arch_system_num_rmid_idx - Compute number of supported RMIDs * (minimum across all mon_capable resource) * * Return: Number of supported RMIDs at time of call. Note that mount time * enumeration of resources may reduce the number. */u32 resctrl_arch_system_num_rmid_idx(void){ u32 num_rmids = U32_MAX; struct rdt_resource *r; for_each_mon_capable_rdt_resource(r) num_rmids = min(num_rmids, r->mon.num_rmid); /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */ return num_rmids == U32_MAX ? 0 : num_rmids;} struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l){ if (l >= RDT_NUM_RESOURCES) return NULL; return &rdt_resources_all[l].r_resctrl;} /* * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs * as they do not have CPUID enumeration support for Cache allocation. * The check for Vendor/Family/Model is not enough to guarantee that * the MSRs won't #GP fault because only the following SKUs support * CAT: * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz * * Probe by trying to write the first of the L3 cache mask registers * and checking that the bits stick. Max CLOSids is always 4 and max cbm length * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */static inline void cache_alloc_hsw_probe(void){ struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; struct rdt_resource *r = &hw_res->r_resctrl; u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) return; rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); /* If all the bits were set in MSR, return success */ if (l3_cbm_0 != max_cbm) return; hw_res->num_closid = 4; r->cache.cbm_len = 20; r->cache.shareable_bits = 0xc0000; r->cache.min_cbm_bits = 2; r->cache.arch_has_sparse_bitmasks = false; r->alloc_capable = true; rdt_alloc_capable = true;} /* * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values * exposed to user interface and the h/w understandable delay values. * * The non-linear delay values have the granularity of power of two * and also the h/w does not guarantee a curve for configured delay * values vs. actual b/w enforced. * Hence we need a mapping that is pre calibrated so the user can * express the memory b/w as a percentage value. */static inline bool rdt_get_mb_table(struct rdt_resource *r){ /* * There are no Intel SKUs as of now to support non-linear delay. */ pr_info("MBA b/w map not implemented for cpu:%d, model:%d", boot_cpu_data.x86, boot_cpu_data.x86_model); return false;} static __init bool __get_mem_config_intel(struct rdt_resource *r){ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; u32 ebx, ecx, max_delay; cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; max_delay = eax.split.max_delay + 1; r->membw.max_bw = MAX_MBA_BW; r->membw.arch_needs_linear = true; if (ecx & MBA_IS_LINEAR) { r->membw.delay_linear = true; r->membw.min_bw = MAX_MBA_BW - max_delay; r->membw.bw_gran = MAX_MBA_BW - max_delay; } else { if (!rdt_get_mb_table(r)) return false; r->membw.arch_needs_linear = false; } if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; else r->membw.throttle_mode = THREAD_THROTTLE_MAX; r->alloc_capable = true; return true;} static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r){ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); u32 eax, ebx, ecx, edx, subleaf; /* * Query CPUID_Fn80000020_EDX_x01 for MBA and * CPUID_Fn80000020_EDX_x02 for SMBA */ subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1; cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); hw_res->num_closid = edx + 1; if (BITS_PER_TYPE(r->membw.max_bw) <= eax) { pr_warn("Unable to support hardware's maximum bandwidth\n"); return false; } r->membw.max_bw = BIT(eax); /* AMD does not use delay */ r->membw.delay_linear = false; r->membw.arch_needs_linear = false; /* * AMD does not use memory delay throttle model to control * the allocation like Intel does. */ r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; r->membw.min_bw = 0; r->membw.bw_gran = 1; r->alloc_capable = true; return true;} static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r){ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; union cpuid_0x10_x_ecx ecx; union cpuid_0x10_x_edx edx; u32 ebx, default_ctrl; cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; r->cache.cbm_len = eax.split.cbm_len + 1; default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; r->cache.shareable_bits = ebx & default_ctrl; if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; r->alloc_capable = true;} static void rdt_get_cdp_config(int level){ /* * By default, CDP is disabled. CDP can be enabled by mount parameter * "cdp" during resctrl file system mount time. */ rdt_resources_all[level].cdp_enabled = false; rdt_resources_all[level].r_resctrl.cdp_capable = true;} static void rdt_set_io_alloc_capable(struct rdt_resource *r){ r->cache.io_alloc_capable = true;} static void rdt_get_cdp_l3_config(void){ rdt_get_cdp_config(RDT_RESOURCE_L3);} static void rdt_get_cdp_l2_config(void){ rdt_get_cdp_config(RDT_RESOURCE_L2);} static void mba_wrmsr_amd(struct msr_param *m){ struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);} /* * Map the memory b/w percentage value to delay values * that can be written to QOS_MSRs. * There are currently no SKUs which support non linear delay values. */static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r){ if (r->membw.delay_linear) return MAX_MBA_BW - bw; pr_warn_once("Non Linear delay-bw map not supported but queried\n"); return MAX_MBA_BW;} static void mba_wrmsr_intel(struct msr_param *m){ struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; /* Write the delay values for mba. */ for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res));} static void cat_wrmsr(struct msr_param *m){ struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);} u32 resctrl_arch_get_num_closid(struct rdt_resource *r){ return resctrl_to_arch_res(r)->num_closid;} void rdt_ctrl_update(void *arg){ struct rdt_hw_resource *hw_res; struct msr_param *m = arg; hw_res = resctrl_to_arch_res(m->res); hw_res->msr_update(m);} static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc){ struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); int i; /* * Initialize the Control MSRs to having no control. * For Cache Allocation: Set all bits in cbm * For Memory Allocation: Set b/w requested to 100% */ for (i = 0; i < hw_res->num_closid; i++, dc++) *dc = resctrl_get_default_ctrl(r);} static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom){ kfree(hw_dom->ctrl_val); kfree(hw_dom);} static void l3_mon_domain_free(struct rdt_hw_l3_mon_domain *hw_dom){ int idx; for_each_mbm_idx(idx) kfree(hw_dom->arch_mbm_states[idx]); kfree(hw_dom);} static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d){ struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct msr_param m; u32 *dc; dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), GFP_KERNEL); if (!dc) return -ENOMEM; hw_dom->ctrl_val = dc; setup_default_ctrlval(r, dc); m.res = r; m.dom = d; m.low = 0; m.high = hw_res->num_closid; hw_res->msr_update(&m); return 0;} /** * l3_mon_domain_mbm_alloc() - Allocate arch private storage for the MBM counters * @num_rmid: The size of the MBM counter array * @hw_dom: The domain that owns the allocated arrays * * Return: 0 for success, or -ENOMEM. */static int l3_mon_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_l3_mon_domain *hw_dom){ size_t tsize = sizeof(*hw_dom->arch_mbm_states[0]); enum resctrl_event_id eventid; int idx; for_each_mbm_event_id(eventid) { if (!resctrl_is_mon_event_enabled(eventid)) continue; idx = MBM_STATE_IDX(eventid); hw_dom->arch_mbm_states[idx] = kcalloc(num_rmid, tsize, GFP_KERNEL); if (!hw_dom->arch_mbm_states[idx]) goto cleanup; } return 0;cleanup: for_each_mbm_idx(idx) { kfree(hw_dom->arch_mbm_states[idx]); hw_dom->arch_mbm_states[idx] = NULL; } return -ENOMEM;} static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope){ switch (scope) { case RESCTRL_L2_CACHE: case RESCTRL_L3_CACHE: return get_cpu_cacheinfo_id(cpu, scope); case RESCTRL_L3_NODE: return cpu_to_node(cpu); case RESCTRL_PACKAGE: return topology_physical_package_id(cpu); default: break; } return -EINVAL;} static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r){ int id = get_domain_id_from_scope(cpu, r->ctrl_scope); struct rdt_hw_ctrl_domain *hw_dom; struct list_head *add_pos = NULL; struct rdt_domain_hdr *hdr; struct rdt_ctrl_domain *d; int err; lockdep_assert_held(&domain_list_lock); if (id < 0) { pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", cpu, r->ctrl_scope, r->name); return; } hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos); if (hdr) { if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) return; d = container_of(hdr, struct rdt_ctrl_domain, hdr); cpumask_set_cpu(cpu, &d->hdr.cpu_mask); if (r->cache.arch_has_per_cpu_cfg)Lines 1–500 of 1174. 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// SPDX-License-Identifier: GPL-2.0-only /* * Resource Director Technology(RDT) * - Cache Allocation code. * * Copyright (C) 2016 Intel Corporation * * Authors: * Fenghua Yu <fenghua.yu@intel.com> * Tony Luck <tony.luck@intel.com> * Vikas Shivappa <vikas.shivappa@intel.com> * * More information about RDT be found in the Intel (R) x86 Architecture * Software Developer Manual June 2016, volume 3, section 17.17. */ #define pr_fmt(fmt) "resctrl: " fmt #include <linux/cpu.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/cpuhotplug.h> #include <asm/cpu_device_id.h> #include <asm/cpuid/api.h> #include <asm/msr.h> #include <asm/resctrl.h> #include "internal.h" /* * rdt_domain structures are kfree()d when their last CPU goes offline, * and allocated when the first CPU in a new domain comes online. * The rdt_resource's domain list is updated when this happens. Readers of * the domain list must either take cpus_read_lock(), or rely on an RCU * read-side critical section, to avoid observing concurrent modification. * All writers take this mutex: */ static DEFINE_MUTEX(domain_list_lock); /* * The cached resctrl_pqr_state is strictly per CPU and can never be * updated from a remote CPU. Functions which modify the state * are called with interrupts disabled and no preemption, which * is sufficient for the protection. */ DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); /* * Global boolean for rdt_alloc which is true if any * resource allocation is enabled. */ bool rdt_alloc_capable; static void mba_wrmsr_intel(struct msr_param *m); static void cat_wrmsr(struct msr_param *m); static void mba_wrmsr_amd(struct msr_param *m); #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains) #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = { [RDT_RESOURCE_L3] = { .r_resctrl = { .name = "L3", .ctrl_scope = RESCTRL_L3_CACHE, .mon_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3), .mon_domains = mon_domain_init(RDT_RESOURCE_L3), .schema_fmt = RESCTRL_SCHEMA_BITMAP, }, .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, }, [RDT_RESOURCE_L2] = { .r_resctrl = { .name = "L2", .ctrl_scope = RESCTRL_L2_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2), .schema_fmt = RESCTRL_SCHEMA_BITMAP, }, .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, }, [RDT_RESOURCE_MBA] = { .r_resctrl = { .name = "MB", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_SMBA] = { .r_resctrl = { .name = "SMBA", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_PERF_PKG] = { .r_resctrl = { .name = "PERF_PKG", .mon_scope = RESCTRL_PACKAGE, .mon_domains = mon_domain_init(RDT_RESOURCE_PERF_PKG), }, }, }; /** * resctrl_arch_system_num_rmid_idx - Compute number of supported RMIDs * (minimum across all mon_capable resource) * * Return: Number of supported RMIDs at time of call. Note that mount time * enumeration of resources may reduce the number. */ u32 resctrl_arch_system_num_rmid_idx(void) { u32 num_rmids = U32_MAX; struct rdt_resource *r; for_each_mon_capable_rdt_resource(r) num_rmids = min(num_rmids, r->mon.num_rmid); /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */ return num_rmids == U32_MAX ? 0 : num_rmids; } struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) { if (l >= RDT_NUM_RESOURCES) return NULL; return &rdt_resources_all[l].r_resctrl; } /* * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs * as they do not have CPUID enumeration support for Cache allocation. * The check for Vendor/Family/Model is not enough to guarantee that * the MSRs won't #GP fault because only the following SKUs support * CAT: * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz * * Probe by trying to write the first of the L3 cache mask registers * and checking that the bits stick. Max CLOSids is always 4 and max cbm length * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */ static inline void cache_alloc_hsw_probe(void) { struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; struct rdt_resource *r = &hw_res->r_resctrl; u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) return; rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); /* If all the bits were set in MSR, return success */ if (l3_cbm_0 != max_cbm) return; hw_res->num_closid = 4; r->cache.cbm_len = 20; r->cache.shareable_bits = 0xc0000; r->cache.min_cbm_bits = 2; r->cache.arch_has_sparse_bitmasks = false; r->alloc_capable = true; rdt_alloc_capable = true; } /* * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values * exposed to user interface and the h/w understandable delay values. * * The non-linear delay values have the granularity of power of two * and also the h/w does not guarantee a curve for configured delay * values vs. actual b/w enforced. * Hence we need a mapping that is pre calibrated so the user can * express the memory b/w as a percentage value. */ static inline bool rdt_get_mb_table(struct rdt_resource *r) { /* * There are no Intel SKUs as of now to support non-linear delay. */ pr_info("MBA b/w map not implemented for cpu:%d, model:%d", boot_cpu_data.x86, boot_cpu_data.x86_model); return false; } static __init bool __get_mem_config_intel(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; u32 ebx, ecx, max_delay; cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; max_delay = eax.split.max_delay + 1; r->membw.max_bw = MAX_MBA_BW; r->membw.arch_needs_linear = true; if (ecx & MBA_IS_LINEAR) { r->membw.delay_linear = true; r->membw.min_bw = MAX_MBA_BW - max_delay; r->membw.bw_gran = MAX_MBA_BW - max_delay; } else { if (!rdt_get_mb_table(r)) return false; r->membw.arch_needs_linear = false; } if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; else r->membw.throttle_mode = THREAD_THROTTLE_MAX; r->alloc_capable = true; return true; } static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); u32 eax, ebx, ecx, edx, subleaf; /* * Query CPUID_Fn80000020_EDX_x01 for MBA and * CPUID_Fn80000020_EDX_x02 for SMBA */ subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1; cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); hw_res->num_closid = edx + 1; if (BITS_PER_TYPE(r->membw.max_bw) <= eax) { pr_warn("Unable to support hardware's maximum bandwidth\n"); return false; } r->membw.max_bw = BIT(eax); /* AMD does not use delay */ r->membw.delay_linear = false; r->membw.arch_needs_linear = false; /* * AMD does not use memory delay throttle model to control * the allocation like Intel does. */ r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; r->membw.min_bw = 0; r->membw.bw_gran = 1; r->alloc_capable = true; return true; } static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; union cpuid_0x10_x_ecx ecx; union cpuid_0x10_x_edx edx; u32 ebx, default_ctrl; cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; r->cache.cbm_len = eax.split.cbm_len + 1; default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; r->cache.shareable_bits = ebx & default_ctrl; if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; r->alloc_capable = true; } static void rdt_get_cdp_config(int level) { /* * By default, CDP is disabled. CDP can be enabled by mount parameter * "cdp" during resctrl file system mount time. */ rdt_resources_all[level].cdp_enabled = false; rdt_resources_all[level].r_resctrl.cdp_capable = true; } static void rdt_set_io_alloc_capable(struct rdt_resource *r) { r->cache.io_alloc_capable = true; } static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); } static void rdt_get_cdp_l2_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L2); } static void mba_wrmsr_amd(struct msr_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); } /* * Map the memory b/w percentage value to delay values * that can be written to QOS_MSRs. * There are currently no SKUs which support non linear delay values. */ static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) { if (r->membw.delay_linear) return MAX_MBA_BW - bw; pr_warn_once("Non Linear delay-bw map not supported but queried\n"); return MAX_MBA_BW; } static void mba_wrmsr_intel(struct msr_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; /* Write the delay values for mba. */ for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); } static void cat_wrmsr(struct msr_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); unsigned int i; for (i = m->low; i < m->high; i++) wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); } u32 resctrl_arch_get_num_closid(struct rdt_resource *r) { return resctrl_to_arch_res(r)->num_closid; } void rdt_ctrl_update(void *arg) { struct rdt_hw_resource *hw_res; struct msr_param *m = arg; hw_res = resctrl_to_arch_res(m->res); hw_res->msr_update(m); } static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); int i; /* * Initialize the Control MSRs to having no control. * For Cache Allocation: Set all bits in cbm * For Memory Allocation: Set b/w requested to 100% */ for (i = 0; i < hw_res->num_closid; i++, dc++) *dc = resctrl_get_default_ctrl(r); } static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom) { kfree(hw_dom->ctrl_val); kfree(hw_dom); } static void l3_mon_domain_free(struct rdt_hw_l3_mon_domain *hw_dom) { int idx; for_each_mbm_idx(idx) kfree(hw_dom->arch_mbm_states[idx]); kfree(hw_dom); } static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct msr_param m; u32 *dc; dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), GFP_KERNEL); if (!dc) return -ENOMEM; hw_dom->ctrl_val = dc; setup_default_ctrlval(r, dc); m.res = r; m.dom = d; m.low = 0; m.high = hw_res->num_closid; hw_res->msr_update(&m); return 0; } /** * l3_mon_domain_mbm_alloc() - Allocate arch private storage for the MBM counters * @num_rmid: The size of the MBM counter array * @hw_dom: The domain that owns the allocated arrays * * Return: 0 for success, or -ENOMEM. */ static int l3_mon_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_l3_mon_domain *hw_dom) { size_t tsize = sizeof(*hw_dom->arch_mbm_states[0]); enum resctrl_event_id eventid; int idx; for_each_mbm_event_id(eventid) { if (!resctrl_is_mon_event_enabled(eventid)) continue; idx = MBM_STATE_IDX(eventid); hw_dom->arch_mbm_states[idx] = kcalloc(num_rmid, tsize, GFP_KERNEL); if (!hw_dom->arch_mbm_states[idx]) goto cleanup; } return 0; cleanup: for_each_mbm_idx(idx) { kfree(hw_dom->arch_mbm_states[idx]); hw_dom->arch_mbm_states[idx] = NULL; } return -ENOMEM; } static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope) { switch (scope) { case RESCTRL_L2_CACHE: case RESCTRL_L3_CACHE: return get_cpu_cacheinfo_id(cpu, scope); case RESCTRL_L3_NODE: return cpu_to_node(cpu); case RESCTRL_PACKAGE: return topology_physical_package_id(cpu); default: break; } return -EINVAL; } static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r) { int id = get_domain_id_from_scope(cpu, r->ctrl_scope); struct rdt_hw_ctrl_domain *hw_dom; struct list_head *add_pos = NULL; struct rdt_domain_hdr *hdr; struct rdt_ctrl_domain *d; int err; lockdep_assert_held(&domain_list_lock); if (id < 0) { pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n", cpu, r->ctrl_scope, r->name); return; } hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos); if (hdr) { if (!domain_header_is_valid(hdr, RESCTRL_CTRL_DOMAIN, r->rid)) return; d = container_of(hdr, struct rdt_ctrl_domain, hdr); cpumask_set_cpu(cpu, &d->hdr.cpu_mask); if (r->cache.arch_has_per_cpu_cfg)