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{    "SkipList": [        "tsx_aborted_cycles",        "tsx_transactional_cycles",        "C2_Pkg_Residency",        "C6_Pkg_Residency",        "C1_Core_Residency",        "C6_Core_Residency",        "tma_false_sharing",        "tma_remote_cache",        "tma_contested_accesses"    ],    "RelationshipRules": [        {            "RuleIndex": 1,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "Intel(R) Optane(TM) Persistent Memory(PMEM)  bandwidth total includes Intel(R) Optane(TM) Persistent Memory(PMEM) read bandwidth and Intel(R) Optane(TM) Persistent Memory(PMEM) write bandwidth",            "Metrics": [                {                    "Name": "pmem_memory_bandwidth_read",                    "Alias": "a"                },                {                    "Name": "pmem_memory_bandwidth_write",                    "Alias": "b"                },                {                    "Name": "pmem_memory_bandwidth_total",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 2,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write bandwidth",            "Metrics": [                {                    "Name": "memory_bandwidth_read",                    "Alias": "a"                },                {                    "Name": "memory_bandwidth_write",                    "Alias": "b"                },                {                    "Name": "memory_bandwidth_total",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 3,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "100",            "RangeUpper": "100",            "ErrorThreshold": 5.0,            "Description": "Total memory read accesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads from the last level cache (LLC) addressed to remote DRAM.",            "Metrics": [                {                    "Name": "numa_reads_addressed_to_local_dram",                    "Alias": "a"                },                {                    "Name": "numa_reads_addressed_to_remote_dram",                    "Alias": "b"                }            ]        },        {            "RuleIndex": 4,            "Formula": "a",            "TestType": "SingleMetricTest",            "RangeLower": "0.125",            "RangeUpper": "",            "ErrorThreshold": "",            "Description": "",            "Metrics": [                {                    "Name": "cpi",                    "Alias": "a"                }            ]        },        {            "RuleIndex": 5,            "Formula": "",            "TestType": "SingleMetricTest",            "RangeLower": "0",            "RangeUpper": "1",            "ErrorThreshold": 5.0,            "Description": "Ratio values should be within value range [0,1)",            "Metrics": [                {                    "Name": "loads_per_instr",                    "Alias": ""                },                {                    "Name": "stores_per_instr",                    "Alias": ""                },                {                    "Name": "l1d_mpi",                    "Alias": ""                },                {                    "Name": "l1d_demand_data_read_hits_per_instr",                    "Alias": ""                },                {                    "Name": "l1_i_code_read_misses_with_prefetches_per_instr",                    "Alias": ""                },                {                    "Name": "l2_demand_data_read_hits_per_instr",                    "Alias": ""                },                {                    "Name": "l2_mpi",                    "Alias": ""                },                {                    "Name": "l2_demand_data_read_mpi",                    "Alias": ""                },                {                    "Name": "l2_demand_code_mpi",                    "Alias": ""                }            ]        },        {            "RuleIndex": 6,            "Formula": "a+b+c+d",            "TestType": "RelationshipTest",            "RangeLower": "100",            "RangeUpper": "100",            "ErrorThreshold": 5.0,            "Description": "Sum of TMA level 1 metrics should be 100%",            "Metrics": [                {                    "Name": "tma_frontend_bound",                    "Alias": "a"                },                {                    "Name": "tma_bad_speculation",                    "Alias": "b"                },                {                    "Name": "tma_backend_bound",                    "Alias": "c"                },                {                    "Name": "tma_retiring",                    "Alias": "d"                }            ]        },        {            "RuleIndex": 7,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "Sum of the level 2 children should equal level 1 parent",            "Metrics": [                {                    "Name": "tma_fetch_latency",                    "Alias": "a"                },                {                    "Name": "tma_fetch_bandwidth",                    "Alias": "b"                },                {                    "Name": "tma_frontend_bound",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 8,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "Sum of the level 2 children should equal level 1 parent",            "Metrics": [                {                    "Name": "tma_branch_mispredicts",                    "Alias": "a"                },                {                    "Name": "tma_machine_clears",                    "Alias": "b"                },                {                    "Name": "tma_bad_speculation",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 9,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "Sum of the level 2 children should equal level 1 parent",            "Metrics": [                {                    "Name": "tma_memory_bound",                    "Alias": "a"                },                {                    "Name": "tma_core_bound",                    "Alias": "b"                },                {                    "Name": "tma_backend_bound",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 10,            "Formula": "a+b",            "TestType": "RelationshipTest",            "RangeLower": "c",            "RangeUpper": "c",            "ErrorThreshold": 5.0,            "Description": "Sum of the level 2 children should equal level 1 parent",            "Metrics": [                {                    "Name": "tma_light_operations",                    "Alias": "a"                },                {                    "Name": "tma_heavy_operations",                    "Alias": "b"                },                {                    "Name": "tma_retiring",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 11,            "Formula": "a+b+c",            "TestType": "RelationshipTest",            "RangeLower": "100",            "RangeUpper": "100",            "ErrorThreshold": 5.0,            "Description": "The all_requests includes the memory_page_empty, memory_page_misses, and memory_page_hits equals.",            "Metrics": [                {                    "Name": "memory_page_empty_vs_all_requests",                    "Alias": "a"                },                {                    "Name": "memory_page_misses_vs_all_requests",                    "Alias": "b"                },                {                    "Name": "memory_page_hits_vs_all_requests",                    "Alias": "c"                }            ]        },        {            "RuleIndex": 12,            "Formula": "a-b",            "TestType": "RelationshipTest",            "RangeLower": "0",            "RangeUpper": "",            "ErrorThreshold": 5.0,            "Description": "CPU utilization in kernel mode should always be <= cpu utilization",            "Metrics": [                {                    "Name": "cpu_utilization",                    "Alias": "a"                },                {                    "Name": "cpu_utilization_in_kernel_mode",                    "Alias": "b"                }            ]        },        {            "RuleIndex": 13,            "Formula": "a-b",            "TestType": "RelationshipTest",            "RangeLower": "0",            "RangeUpper": "",            "ErrorThreshold": 5.0,            "Description": "Total L2 misses per instruction should be >= L2 demand data read misses per instruction",            "Metrics": [                {                    "Name": "l2_mpi",                    "Alias": "a"                },                {                    "Name": "l2_demand_data_read_mpi",                    "Alias": "b"                }            ]        },        {            "RuleIndex": 14,            "Formula": "a-b",            "TestType": "RelationshipTest",            "RangeLower": "0",            "RangeUpper": "",            "ErrorThreshold": 5.0,            "Description": "Total L2 misses per instruction should be >= L2 demand code misses per instruction",            "Metrics": [                {                    "Name": "l2_mpi",                    "Alias": "a"                },                {                    "Name": "l2_demand_code_mpi",                    "Alias": "b"                }            ]        },        {            "RuleIndex": 15,            "Formula": "b+c+d",            "TestType": "RelationshipTest",            "RangeLower": "a",            "RangeUpper": "a",            "ErrorThreshold": 5.0,            "Description": "L3 data read, rfo, code misses per instruction equals total L3 misses per instruction.",            "Metrics": [                {                    "Name": "llc_mpi",                    "Alias": "a"                },                {                    "Name": "llc_data_read_mpi_demand_plus_prefetch",                    "Alias": "b"                },                {                    "Name": "llc_rfo_read_mpi_demand_plus_prefetch",                    "Alias": "c"                },                {                    "Name": "llc_code_read_mpi_demand_plus_prefetch",                    "Alias": "d"                }            ]        },        {            "RuleIndex": 16,            "Formula": "a",            "TestType": "SingleMetricTest",            "RangeLower": "0",            "RangeUpper": "8",            "ErrorThreshold": 0.0,            "Description": "Setting generous range for allowable frequencies",            "Metrics": [                {                    "Name": "uncore_freq",                    "Alias": "a"                }            ]        },        {            "RuleIndex": 17,            "Formula": "a",            "TestType": "SingleMetricTest",            "RangeLower": "0",            "RangeUpper": "8",            "ErrorThreshold": 0.0,            "Description": "Setting generous range for allowable frequencies",            "Metrics": [                {                    "Name": "cpu_operating_frequency",                    "Alias": "a"                }            ]        }    ]}