// SPDX-License-Identifier: GPL-2.0-only/* * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved. */ #include <linux/cleanup.h>#include <linux/clk.h>#include <linux/delay.h>#include <linux/dma-mapping.h>#include <linux/export.h>#include <linux/interrupt.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/mutex.h>#include <linux/of.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/slab.h>#include <linux/sort.h>#include <linux/tegra-icc.h> #include <soc/tegra/fuse.h> #include "mc.h" static DEFINE_MUTEX(tegra_mc_debugfs_root_lock);static struct dentry *tegra_mc_debugfs_root; static const struct of_device_id tegra_mc_of_match[] = {#ifdef CONFIG_ARCH_TEGRA_2x_SOC	{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_3x_SOC	{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_114_SOC	{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_124_SOC	{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_132_SOC	{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_210_SOC	{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_186_SOC	{ .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_194_SOC	{ .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_234_SOC	{ .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_238_SOC	{ .compatible = "nvidia,tegra238-mc", .data = &tegra238_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_264_SOC	{ .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc },#endif	{ /* sentinel */ }};MODULE_DEVICE_TABLE(of, tegra_mc_of_match); const struct tegra_mc_regs tegra20_mc_regs = {	.cfg_channel_enable = 0xdf8,	.err_status = 0x08,	.err_add = 0x0c,	.err_add_hi = 0x11fc,	.err_vpr_status = 0x654,	.err_vpr_add = 0x658,	.err_sec_status = 0x67c,	.err_sec_add = 0x680,	.err_mts_status = 0x9b0,	.err_mts_add = 0x9b4,	.err_gen_co_status = 0xc00,	.err_gen_co_add = 0xc04,	.err_route_status = 0x9c0,	.err_route_add = 0x9c4,}; static void tegra_mc_devm_action_put_device(void *data){	struct tegra_mc *mc = data; 	put_device(mc->dev);} /** * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle * @dev: device pointer for the consumer device * * This function will search for the Memory Controller node in a device-tree * and retrieve the Memory Controller handle. * * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. */struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev){	struct platform_device *pdev;	struct device_node *np;	struct tegra_mc *mc;	int err; 	np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0);	if (!np)		return ERR_PTR(-ENOENT); 	pdev = of_find_device_by_node(np);	of_node_put(np);	if (!pdev)		return ERR_PTR(-ENODEV); 	mc = platform_get_drvdata(pdev);	if (!mc) {		put_device(&pdev->dev);		return ERR_PTR(-EPROBE_DEFER);	} 	err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc);	if (err)		return ERR_PTR(err); 	return mc;}EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev){	if (mc->soc->ops && mc->soc->ops->probe_device)		return mc->soc->ops->probe_device(mc, dev); 	return 0;}EXPORT_SYMBOL_GPL(tegra_mc_probe_device); int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,                               phys_addr_t *base, u64 *size){	u32 offset; 	if (id < 1 || id >= mc->soc->num_carveouts)		return -EINVAL; 	if (id < 6)		offset = 0xc0c + 0x50 * (id - 1);	else		offset = 0x2004 + 0x50 * (id - 6); 	*base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0);#ifdef CONFIG_PHYS_ADDR_T_64BIT	*base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;#endif 	if (size)		*size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17; 	return 0;}EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info); static int tegra_mc_block_dma_common(struct tegra_mc *mc,				     const struct tegra_mc_reset *rst){	unsigned long flags;	u32 value; 	spin_lock_irqsave(&mc->lock, flags); 	value = mc_readl(mc, rst->control) | BIT(rst->bit);	mc_writel(mc, value, rst->control); 	spin_unlock_irqrestore(&mc->lock, flags); 	return 0;} static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,				       const struct tegra_mc_reset *rst){	return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;} static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,				       const struct tegra_mc_reset *rst){	unsigned long flags;	u32 value; 	spin_lock_irqsave(&mc->lock, flags); 	value = mc_readl(mc, rst->control) & ~BIT(rst->bit);	mc_writel(mc, value, rst->control); 	spin_unlock_irqrestore(&mc->lock, flags); 	return 0;} static int tegra_mc_reset_status_common(struct tegra_mc *mc,					const struct tegra_mc_reset *rst){	return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;} const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {	.block_dma = tegra_mc_block_dma_common,	.dma_idling = tegra_mc_dma_idling_common,	.unblock_dma = tegra_mc_unblock_dma_common,	.reset_status = tegra_mc_reset_status_common,}; static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev){	return container_of(rcdev, struct tegra_mc, reset);} static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,							unsigned long id){	unsigned int i; 	for (i = 0; i < mc->soc->num_resets; i++)		if (mc->soc->resets[i].id == id)			return &mc->soc->resets[i]; 	return NULL;} static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,				    unsigned long id){	struct tegra_mc *mc = reset_to_mc(rcdev);	const struct tegra_mc_reset_ops *rst_ops;	const struct tegra_mc_reset *rst;	int retries = 500;	int err; 	rst = tegra_mc_reset_find(mc, id);	if (!rst)		return -ENODEV; 	rst_ops = mc->soc->reset_ops;	if (!rst_ops)		return -ENODEV; 	/* DMA flushing will fail if reset is already asserted */	if (rst_ops->reset_status) {		/* check whether reset is asserted */		if (rst_ops->reset_status(mc, rst))			return 0;	} 	if (rst_ops->block_dma) {		/* block clients DMA requests */		err = rst_ops->block_dma(mc, rst);		if (err) {			dev_err(mc->dev, "failed to block %s DMA: %d\n",				rst->name, err);			return err;		}	} 	if (rst_ops->dma_idling) {		/* wait for completion of the outstanding DMA requests */		while (!rst_ops->dma_idling(mc, rst)) {			if (!retries--) {				dev_err(mc->dev, "failed to flush %s DMA\n",					rst->name);				return -EBUSY;			} 			usleep_range(10, 100);		}	} 	if (rst_ops->hotreset_assert) {		/* clear clients DMA requests sitting before arbitration */		err = rst_ops->hotreset_assert(mc, rst);		if (err) {			dev_err(mc->dev, "failed to hot reset %s: %d\n",				rst->name, err);			return err;		}	} 	return 0;} static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,				      unsigned long id){	struct tegra_mc *mc = reset_to_mc(rcdev);	const struct tegra_mc_reset_ops *rst_ops;	const struct tegra_mc_reset *rst;	int err; 	rst = tegra_mc_reset_find(mc, id);	if (!rst)		return -ENODEV; 	rst_ops = mc->soc->reset_ops;	if (!rst_ops)		return -ENODEV; 	if (rst_ops->hotreset_deassert) {		/* take out client from hot reset */		err = rst_ops->hotreset_deassert(mc, rst);		if (err) {			dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",				rst->name, err);			return err;		}	} 	if (rst_ops->unblock_dma) {		/* allow new DMA requests to proceed to arbitration */		err = rst_ops->unblock_dma(mc, rst);		if (err) {			dev_err(mc->dev, "failed to unblock %s DMA : %d\n",				rst->name, err);			return err;		}	} 	return 0;} static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,				    unsigned long id){	struct tegra_mc *mc = reset_to_mc(rcdev);	const struct tegra_mc_reset_ops *rst_ops;	const struct tegra_mc_reset *rst; 	rst = tegra_mc_reset_find(mc, id);	if (!rst)		return -ENODEV; 	rst_ops = mc->soc->reset_ops;	if (!rst_ops)		return -ENODEV; 	return rst_ops->reset_status(mc, rst);} static const struct reset_control_ops tegra_mc_reset_ops = {	.assert = tegra_mc_hotreset_assert,	.deassert = tegra_mc_hotreset_deassert,	.status = tegra_mc_hotreset_status,}; static int tegra_mc_reset_setup(struct tegra_mc *mc){	int err; 	mc->reset.ops = &tegra_mc_reset_ops;	mc->reset.owner = THIS_MODULE;	mc->reset.of_node = mc->dev->of_node;	mc->reset.of_reset_n_cells = 1;	mc->reset.nr_resets = mc->soc->num_resets; 	err = reset_controller_register(&mc->reset);	if (err < 0)		return err; 	return 0;} int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate){	unsigned int i;	struct tegra_mc_timing *timing = NULL; 	for (i = 0; i < mc->num_timings; i++) {		if (mc->timings[i].rate == rate) {			timing = &mc->timings[i];			break;		}	} 	if (!timing) {		dev_err(mc->dev, "no memory timing registered for rate %lu\n",			rate);		return -EINVAL;	} 	for (i = 0; i < mc->soc->num_emem_regs; ++i)		mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 	return 0;}EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc){	u8 dram_count; 	dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);	dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;	dram_count++; 	return dram_count;}EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); const irq_handler_t tegra30_mc_irq_handlers[] = {	tegra30_mc_handle_irq}; #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \    defined(CONFIG_ARCH_TEGRA_114_SOC) || \    defined(CONFIG_ARCH_TEGRA_124_SOC) || \    defined(CONFIG_ARCH_TEGRA_132_SOC) || \    defined(CONFIG_ARCH_TEGRA_210_SOC)static void tegra_mc_setup_latency_allowance(struct tegra_mc *mc){	unsigned long long tick;	unsigned int i;	u32 value; 	/* compute the number of MC clock cycles per tick */	tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);	do_div(tick, NSEC_PER_SEC); 	value = mc_readl(mc, MC_EMEM_ARB_CFG);	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);	mc_writel(mc, value, MC_EMEM_ARB_CFG); 	/* write latency allowance defaults */	for (i = 0; i < mc->soc->num_clients; i++) {		const struct tegra_mc_client *client = &mc->soc->clients[i];		u32 value; 		value = mc_readl(mc, client->regs.la.reg);		value &= ~(client->regs.la.mask << client->regs.la.shift);		value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;		mc_writel(mc, value, client->regs.la.reg);	} 	/* latch new values */	mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);} static int load_one_timing(struct tegra_mc *mc,			   struct tegra_mc_timing *timing,			   struct device_node *node){	int err;	u32 tmp; 	err = of_property_read_u32(node, "clock-frequency", &tmp);	if (err) {		dev_err(mc->dev,			"timing %pOFn: failed to read rate\n", node);		return err;	} 	timing->rate = tmp;	timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,					 sizeof(u32), GFP_KERNEL);	if (!timing->emem_data)		return -ENOMEM; 	err = of_property_read_u32_array(node, "nvidia,emem-configuration",					 timing->emem_data,					 mc->soc->num_emem_regs);	if (err) {		dev_err(mc->dev,			"timing %pOFn: failed to read EMEM configuration\n",			node);		return err;	} 	return 0;} static int load_timings(struct tegra_mc *mc, struct device_node *node){	struct tegra_mc_timing *timing;	int child_count = of_get_child_count(node);	int i = 0, err; 	mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),				   GFP_KERNEL);	if (!mc->timings)		return -ENOMEM; 	mc->num_timings = child_count; 	for_each_child_of_node_scoped(node, child) {		timing = &mc->timings[i++]; 		err = load_one_timing(mc, timing, child);		if (err)			return err;

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