/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#ifndef __AMDGPU_H__#define __AMDGPU_H__ #include <linux/atomic.h>#include <linux/wait.h>#include <linux/list.h>#include <linux/kref.h>#include <linux/rbtree.h>#include <linux/hashtable.h>#include <linux/dma-fence.h> #include <drm/ttm/ttm_bo_api.h>#include <drm/ttm/ttm_bo_driver.h>#include <drm/ttm/ttm_placement.h>#include <drm/ttm/ttm_module.h>#include <drm/ttm/ttm_execbuf_util.h> #include <drm/drmP.h>#include <drm/drm_gem.h>#include <drm/amdgpu_drm.h>#include <drm/gpu_scheduler.h> #include <kgd_kfd_interface.h>#include "dm_pp_interface.h"#include "kgd_pp_interface.h" #include "amd_shared.h"#include "amdgpu_mode.h"#include "amdgpu_ih.h"#include "amdgpu_irq.h"#include "amdgpu_ucode.h"#include "amdgpu_ttm.h"#include "amdgpu_psp.h"#include "amdgpu_gds.h"#include "amdgpu_sync.h"#include "amdgpu_ring.h"#include "amdgpu_vm.h"#include "amdgpu_dpm.h"#include "amdgpu_acp.h"#include "amdgpu_uvd.h"#include "amdgpu_vce.h"#include "amdgpu_vcn.h"#include "amdgpu_mn.h"#include "amdgpu_gmc.h"#include "amdgpu_dm.h"#include "amdgpu_virt.h"#include "amdgpu_gart.h"#include "amdgpu_debugfs.h"#include "amdgpu_job.h"#include "amdgpu_bo_list.h" /* * Modules parameters. */extern int amdgpu_modeset;extern int amdgpu_vram_limit;extern int amdgpu_vis_vram_limit;extern int amdgpu_gart_size;extern int amdgpu_gtt_size;extern int amdgpu_moverate;extern int amdgpu_benchmarking;extern int amdgpu_testing;extern int amdgpu_audio;extern int amdgpu_disp_priority;extern int amdgpu_hw_i2c;extern int amdgpu_pcie_gen2;extern int amdgpu_msi;extern int amdgpu_lockup_timeout;extern int amdgpu_dpm;extern int amdgpu_fw_load_type;extern int amdgpu_aspm;extern int amdgpu_runtime_pm;extern uint amdgpu_ip_block_mask;extern int amdgpu_bapm;extern int amdgpu_deep_color;extern int amdgpu_vm_size;extern int amdgpu_vm_block_size;extern int amdgpu_vm_fragment_size;extern int amdgpu_vm_fault_stop;extern int amdgpu_vm_debug;extern int amdgpu_vm_update_mode;extern int amdgpu_dc;extern int amdgpu_sched_jobs;extern int amdgpu_sched_hw_submission;extern uint amdgpu_pcie_gen_cap;extern uint amdgpu_pcie_lane_cap;extern uint amdgpu_cg_mask;extern uint amdgpu_pg_mask;extern uint amdgpu_sdma_phase_quantum;extern char *amdgpu_disable_cu;extern char *amdgpu_virtual_display;extern uint amdgpu_pp_feature_mask;extern int amdgpu_vram_page_split;extern int amdgpu_ngg;extern int amdgpu_prim_buf_per_se;extern int amdgpu_pos_buf_per_se;extern int amdgpu_cntl_sb_buf_per_se;extern int amdgpu_param_buf_per_se;extern int amdgpu_job_hang_limit;extern int amdgpu_lbpw;extern int amdgpu_compute_multipipe;extern int amdgpu_gpu_recovery;extern int amdgpu_emu_mode;extern uint amdgpu_smu_memory_pool_size; #ifdef CONFIG_DRM_AMDGPU_SIextern int amdgpu_si_support;#endif#ifdef CONFIG_DRM_AMDGPU_CIKextern int amdgpu_cik_support;#endif #define AMDGPU_SG_THRESHOLD			(256*1024*1024)#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)/* AMDGPU_IB_POOL_SIZE must be a power of 2 */#define AMDGPU_IB_POOL_SIZE			16#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32#define AMDGPUFB_CONN_LIMIT			4#define AMDGPU_BIOS_NUM_SCRATCH			16 /* max number of IP instances */#define AMDGPU_MAX_SDMA_INSTANCES		2 /* hard reset data */#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b /* reset flags */#define AMDGPU_RESET_GFX			(1 << 0)#define AMDGPU_RESET_COMPUTE			(1 << 1)#define AMDGPU_RESET_DMA			(1 << 2)#define AMDGPU_RESET_CP				(1 << 3)#define AMDGPU_RESET_GRBM			(1 << 4)#define AMDGPU_RESET_DMA1			(1 << 5)#define AMDGPU_RESET_RLC			(1 << 6)#define AMDGPU_RESET_SEM			(1 << 7)#define AMDGPU_RESET_IH				(1 << 8)#define AMDGPU_RESET_VMC			(1 << 9)#define AMDGPU_RESET_MC				(1 << 10)#define AMDGPU_RESET_DISPLAY			(1 << 11)#define AMDGPU_RESET_UVD			(1 << 12)#define AMDGPU_RESET_VCE			(1 << 13)#define AMDGPU_RESET_VCE1			(1 << 14) /* GFX current status */#define AMDGPU_GFX_NORMAL_MODE			0x00000000L#define AMDGPU_GFX_SAFE_MODE			0x00000001L#define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L /* max cursor sizes (in pixels) */#define CIK_CURSOR_WIDTH 128#define CIK_CURSOR_HEIGHT 128 struct amdgpu_device;struct amdgpu_ib;struct amdgpu_cs_parser;struct amdgpu_job;struct amdgpu_irq_src;struct amdgpu_fpriv;struct amdgpu_bo_va_mapping;struct amdgpu_atif; enum amdgpu_cp_irq {	AMDGPU_CP_IRQ_GFX_EOP = 0,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 	AMDGPU_CP_IRQ_LAST}; enum amdgpu_sdma_irq {	AMDGPU_SDMA_IRQ_TRAP0 = 0,	AMDGPU_SDMA_IRQ_TRAP1, 	AMDGPU_SDMA_IRQ_LAST}; enum amdgpu_thermal_irq {	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 	AMDGPU_THERMAL_IRQ_LAST}; enum amdgpu_kiq_irq {	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,	AMDGPU_CP_KIQ_IRQ_LAST}; int amdgpu_device_ip_set_clockgating_state(void *dev,					   enum amd_ip_block_type block_type,					   enum amd_clockgating_state state);int amdgpu_device_ip_set_powergating_state(void *dev,					   enum amd_ip_block_type block_type,					   enum amd_powergating_state state);void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,					    u32 *flags);int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,				   enum amd_ip_block_type block_type);bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,			      enum amd_ip_block_type block_type); #define AMDGPU_MAX_IP_NUM 16 struct amdgpu_ip_block_status {	bool valid;	bool sw;	bool hw;	bool late_initialized;	bool hang;}; struct amdgpu_ip_block_version {	const enum amd_ip_block_type type;	const u32 major;	const u32 minor;	const u32 rev;	const struct amd_ip_funcs *funcs;}; struct amdgpu_ip_block {	struct amdgpu_ip_block_status status;	const struct amdgpu_ip_block_version *version;}; int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,				       enum amd_ip_block_type type,				       u32 major, u32 minor); struct amdgpu_ip_block *amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,			      enum amd_ip_block_type type); int amdgpu_device_ip_block_add(struct amdgpu_device *adev,			       const struct amdgpu_ip_block_version *ip_block_version); /* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */struct amdgpu_buffer_funcs {	/* maximum bytes in a single operation */	uint32_t	copy_max_bytes; 	/* number of dw to reserve per operation */	unsigned	copy_num_dw; 	/* used for buffer migration */	void (*emit_copy_buffer)(struct amdgpu_ib *ib,				 /* src addr in bytes */				 uint64_t src_offset,				 /* dst addr in bytes */				 uint64_t dst_offset,				 /* number of byte to transfer */				 uint32_t byte_count); 	/* maximum bytes in a single operation */	uint32_t	fill_max_bytes; 	/* number of dw to reserve per operation */	unsigned	fill_num_dw; 	/* used for buffer clearing */	void (*emit_fill_buffer)(struct amdgpu_ib *ib,				 /* value to write to memory */				 uint32_t src_data,				 /* dst addr in bytes */				 uint64_t dst_offset,				 /* number of byte to fill */				 uint32_t byte_count);}; /* provided by hw blocks that can write ptes, e.g., sdma */struct amdgpu_vm_pte_funcs {	/* number of dw to reserve per operation */	unsigned	copy_pte_num_dw; 	/* copy pte entries from GART */	void (*copy_pte)(struct amdgpu_ib *ib,			 uint64_t pe, uint64_t src,			 unsigned count); 	/* write pte one entry at a time with addr mapping */	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,			  uint64_t value, unsigned count,			  uint32_t incr);	/* for linear pte/pde updates without addr mapping */	void (*set_pte_pde)(struct amdgpu_ib *ib,			    uint64_t pe,			    uint64_t addr, unsigned count,			    uint32_t incr, uint64_t flags);}; /* provided by the ih block */struct amdgpu_ih_funcs {	/* ring read/write ptr handling, called from interrupt context */	u32 (*get_wptr)(struct amdgpu_device *adev);	bool (*prescreen_iv)(struct amdgpu_device *adev);	void (*decode_iv)(struct amdgpu_device *adev,			  struct amdgpu_iv_entry *entry);	void (*set_rptr)(struct amdgpu_device *adev);}; /* * BIOS. */bool amdgpu_get_bios(struct amdgpu_device *adev);bool amdgpu_read_bios(struct amdgpu_device *adev); /* * Clocks */ #define AMDGPU_MAX_PPLL 3 struct amdgpu_clock {	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];	struct amdgpu_pll spll;	struct amdgpu_pll mpll;	/* 10 Khz units */	uint32_t default_mclk;	uint32_t default_sclk;	uint32_t default_dispclk;	uint32_t current_dispclk;	uint32_t dp_extclk;	uint32_t max_pixel_clock;}; /* * GEM. */ #define AMDGPU_GEM_DOMAIN_MAX		0x3#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) void amdgpu_gem_object_free(struct drm_gem_object *obj);int amdgpu_gem_object_open(struct drm_gem_object *obj,				struct drm_file *file_priv);void amdgpu_gem_object_close(struct drm_gem_object *obj,				struct drm_file *file_priv);unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,				 struct dma_buf_attachment *attach,				 struct sg_table *sg);struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,					struct drm_gem_object *gobj,					int flags);struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,					    struct dma_buf *dma_buf);struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their * locking. * * Principe is simple, we keep a list of sub allocation in offset * order (first entry has offset == 0, last entry has the highest * offset). * * When allocating new object we first check if there is room at * the end total_size - (last_object_offset + last_object_size) >= * alloc_size. If so we allocate new object there. * * When there is not enough room at the end, we start waiting for * each sub object until we reach object_offset+object_size >= * alloc_size, this object then become the sub object we return. * * Alignment can't be bigger than page size. * * Hole are not considered for allocation to keep things simple. * Assumption is that there won't be hole (all object on same * alignment). */ #define AMDGPU_SA_NUM_FENCE_LISTS	32 struct amdgpu_sa_manager {	wait_queue_head_t	wq;	struct amdgpu_bo	*bo;	struct list_head	*hole;	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];	struct list_head	olist;	unsigned		size;	uint64_t		gpu_addr;	void			*cpu_ptr;	uint32_t		domain;	uint32_t		align;}; /* sub-allocation buffer */struct amdgpu_sa_bo {	struct list_head		olist;	struct list_head		flist;	struct amdgpu_sa_manager	*manager;	unsigned			soffset;	unsigned			eoffset;	struct dma_fence	        *fence;}; /* * GEM objects. */void amdgpu_gem_force_release(struct amdgpu_device *adev);int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,			     int alignment, u32 initial_domain,			     u64 flags, enum ttm_bo_type type,			     struct reservation_object *resv,			     struct drm_gem_object **obj); int amdgpu_mode_dumb_create(struct drm_file *file_priv,			    struct drm_device *dev,			    struct drm_mode_create_dumb *args);int amdgpu_mode_dumb_mmap(struct drm_file *filp,			  struct drm_device *dev,			  uint32_t handle, uint64_t *offset_p);int amdgpu_fence_slab_init(void);void amdgpu_fence_slab_fini(void); /* * GPU doorbell structures, functions & helpers */typedef enum _AMDGPU_DOORBELL_ASSIGNMENT{	AMDGPU_DOORBELL_KIQ                     = 0x000,	AMDGPU_DOORBELL_HIQ                     = 0x001,	AMDGPU_DOORBELL_DIQ                     = 0x002,	AMDGPU_DOORBELL_MEC_RING0               = 0x010,	AMDGPU_DOORBELL_MEC_RING1               = 0x011,	AMDGPU_DOORBELL_MEC_RING2               = 0x012,	AMDGPU_DOORBELL_MEC_RING3               = 0x013,	AMDGPU_DOORBELL_MEC_RING4               = 0x014,	AMDGPU_DOORBELL_MEC_RING5               = 0x015,	AMDGPU_DOORBELL_MEC_RING6               = 0x016,	AMDGPU_DOORBELL_MEC_RING7               = 0x017,	AMDGPU_DOORBELL_GFX_RING0               = 0x020,	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,	AMDGPU_DOORBELL_IH                      = 0x1E8,	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,	AMDGPU_DOORBELL_INVALID                 = 0xFFFF} AMDGPU_DOORBELL_ASSIGNMENT; struct amdgpu_doorbell {	/* doorbell mmio */	resource_size_t		base;	resource_size_t		size;	u32 __iomem		*ptr;	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */}; /* * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space */typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT{	/*	 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in	 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.	 *  Compute related doorbells are allocated from 0x00 to 0x8a	 */

Lines 1–500 of 1864. Load more