/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#include <linux/power_supply.h>#include <linux/kthread.h>#include <linux/console.h>#include <linux/slab.h>#include <drm/drmP.h>#include <drm/drm_crtc_helper.h>#include <drm/drm_atomic_helper.h>#include <drm/amdgpu_drm.h>#include <linux/vgaarb.h>#include <linux/vga_switcheroo.h>#include <linux/efi.h>#include "amdgpu.h"#include "amdgpu_trace.h"#include "amdgpu_i2c.h"#include "atom.h"#include "amdgpu_atombios.h"#include "amdgpu_atomfirmware.h"#include "amd_pcie.h"#ifdef CONFIG_DRM_AMDGPU_SI#include "si.h"#endif#ifdef CONFIG_DRM_AMDGPU_CIK#include "cik.h"#endif#include "vi.h"#include "soc15.h"#include "bif/bif_4_1_d.h"#include <linux/pci.h>#include <linux/firmware.h>#include "amdgpu_vf_error.h" #include "amdgpu_amdkfd.h"#include "amdgpu_pm.h" MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); #define AMDGPU_RESUME_MS		2000 static const char *amdgpu_asic_name[] = {	"TAHITI",	"PITCAIRN",	"VERDE",	"OLAND",	"HAINAN",	"BONAIRE",	"KAVERI",	"KABINI",	"HAWAII",	"MULLINS",	"TOPAZ",	"TONGA",	"FIJI",	"CARRIZO",	"STONEY",	"POLARIS10",	"POLARIS11",	"POLARIS12",	"VEGAM",	"VEGA10",	"VEGA12",	"VEGA20",	"RAVEN",	"LAST",}; static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); /** * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control * * @dev: drm_device pointer * * Returns true if the device is a dGPU with HG/PX power control, * otherwise return false. */bool amdgpu_device_is_px(struct drm_device *dev){	struct amdgpu_device *adev = dev->dev_private; 	if (adev->flags & AMD_IS_PX)		return true;	return false;} /* * MMIO register access helper functions. *//** * amdgpu_mm_rreg - read a memory mapped IO register * * @adev: amdgpu_device pointer * @reg: dword aligned register offset * @acc_flags: access flags which require special behavior * * Returns the 32 bit value from the offset specified. */uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,			uint32_t acc_flags){	uint32_t ret; 	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))		return amdgpu_virt_kiq_rreg(adev, reg); 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));	else {		unsigned long flags; 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);	}	trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);	return ret;} /* * MMIO register read with bytes helper functions * @offset:bytes offset from MMIO start **/ /** * amdgpu_mm_rreg8 - read a memory mapped IO register * * @adev: amdgpu_device pointer * @offset: byte aligned register offset * * Returns the 8 bit value from the offset specified. */uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {	if (offset < adev->rmmio_size)		return (readb(adev->rmmio + offset));	BUG();} /* * MMIO register write with bytes helper functions * @offset:bytes offset from MMIO start * @value: the value want to be written to the register **//** * amdgpu_mm_wreg8 - read a memory mapped IO register * * @adev: amdgpu_device pointer * @offset: byte aligned register offset * @value: 8 bit value to write * * Writes the value specified to the offset specified. */void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {	if (offset < adev->rmmio_size)		writeb(value, adev->rmmio + offset);	else		BUG();} /** * amdgpu_mm_wreg - write to a memory mapped IO register * * @adev: amdgpu_device pointer * @reg: dword aligned register offset * @v: 32 bit value to write to the register * @acc_flags: access flags which require special behavior * * Writes the value specified to the offset specified. */void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,		    uint32_t acc_flags){	trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); 	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {		adev->last_mm_index = v;	} 	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))		return amdgpu_virt_kiq_wreg(adev, reg, v); 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));	else {		unsigned long flags; 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);	} 	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {		udelay(500);	}} /** * amdgpu_io_rreg - read an IO register * * @adev: amdgpu_device pointer * @reg: dword aligned register offset * * Returns the 32 bit value from the offset specified. */u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg){	if ((reg * 4) < adev->rio_mem_size)		return ioread32(adev->rio_mem + (reg * 4));	else {		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));		return ioread32(adev->rio_mem + (mmMM_DATA * 4));	}} /** * amdgpu_io_wreg - write to an IO register * * @adev: amdgpu_device pointer * @reg: dword aligned register offset * @v: 32 bit value to write to the register * * Writes the value specified to the offset specified. */void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v){	if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {		adev->last_mm_index = v;	} 	if ((reg * 4) < adev->rio_mem_size)		iowrite32(v, adev->rio_mem + (reg * 4));	else {		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));		iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));	} 	if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {		udelay(500);	}} /** * amdgpu_mm_rdoorbell - read a doorbell dword * * @adev: amdgpu_device pointer * @index: doorbell index * * Returns the value in the doorbell aperture at the * requested doorbell index (CIK). */u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index){	if (index < adev->doorbell.num_doorbells) {		return readl(adev->doorbell.ptr + index);	} else {		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);		return 0;	}} /** * amdgpu_mm_wdoorbell - write a doorbell dword * * @adev: amdgpu_device pointer * @index: doorbell index * @v: value to write * * Writes @v to the doorbell aperture at the * requested doorbell index (CIK). */void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v){	if (index < adev->doorbell.num_doorbells) {		writel(v, adev->doorbell.ptr + index);	} else {		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);	}} /** * amdgpu_mm_rdoorbell64 - read a doorbell Qword * * @adev: amdgpu_device pointer * @index: doorbell index * * Returns the value in the doorbell aperture at the * requested doorbell index (VEGA10+). */u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index){	if (index < adev->doorbell.num_doorbells) {		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));	} else {		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);		return 0;	}} /** * amdgpu_mm_wdoorbell64 - write a doorbell Qword * * @adev: amdgpu_device pointer * @index: doorbell index * @v: value to write * * Writes @v to the doorbell aperture at the * requested doorbell index (VEGA10+). */void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v){	if (index < adev->doorbell.num_doorbells) {		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);	} else {		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);	}} /** * amdgpu_invalid_rreg - dummy reg read function * * @adev: amdgpu device pointer * @reg: offset of register * * Dummy register read function.  Used for register blocks * that certain asics don't have (all asics). * Returns the value in the register. */static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg){	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);	BUG();	return 0;} /** * amdgpu_invalid_wreg - dummy reg write function * * @adev: amdgpu device pointer * @reg: offset of register * @v: value to write to the register * * Dummy register read function.  Used for register blocks * that certain asics don't have (all asics). */static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v){	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",		  reg, v);	BUG();} /** * amdgpu_block_invalid_rreg - dummy reg read function * * @adev: amdgpu device pointer * @block: offset of instance * @reg: offset of register * * Dummy register read function.  Used for register blocks * that certain asics don't have (all asics). * Returns the value in the register. */static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,					  uint32_t block, uint32_t reg){	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",		  reg, block);	BUG();	return 0;} /** * amdgpu_block_invalid_wreg - dummy reg write function * * @adev: amdgpu device pointer * @block: offset of instance * @reg: offset of register * @v: value to write to the register * * Dummy register read function.  Used for register blocks * that certain asics don't have (all asics). */static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,				      uint32_t block,				      uint32_t reg, uint32_t v){	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",		  reg, block, v);	BUG();} /** * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page * * @adev: amdgpu device pointer * * Allocates a scratch page of VRAM for use by various things in the * driver. */static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev){	return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,				       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,				       &adev->vram_scratch.robj,				       &adev->vram_scratch.gpu_addr,				       (void **)&adev->vram_scratch.ptr);} /** * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page * * @adev: amdgpu device pointer * * Frees the VRAM scratch page. */static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev){	amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);} /** * amdgpu_device_program_register_sequence - program an array of registers. * * @adev: amdgpu_device pointer * @registers: pointer to the register array * @array_size: size of the register array * * Programs an array or registers with and and or masks. * This is a helper for setting golden registers. */void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,					     const u32 *registers,					     const u32 array_size){	u32 tmp, reg, and_mask, or_mask;	int i; 	if (array_size % 3)		return; 	for (i = 0; i < array_size; i +=3) {		reg = registers[i + 0];		and_mask = registers[i + 1];		or_mask = registers[i + 2]; 		if (and_mask == 0xffffffff) {			tmp = or_mask;		} else {			tmp = RREG32(reg);			tmp &= ~and_mask;			tmp |= or_mask;		}		WREG32(reg, tmp);	}} /** * amdgpu_device_pci_config_reset - reset the GPU * * @adev: amdgpu_device pointer * * Resets the GPU using the pci config reset sequence. * Only applicable to asics prior to vega10. */void amdgpu_device_pci_config_reset(struct amdgpu_device *adev){	pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);} 

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